if_bgereg.h revision 1.88
1 /* $NetBSD: if_bgereg.h,v 1.88 2014/06/17 17:37:08 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SRAM_FW_MB 0x00000B50 76 #define BGE_SRAM_DATA_SIG 0x00000B54 77 #define BGE_SRAM_DATA_CFG 0x00000B58 78 #define BGE_SRAM_DATA_VER 0x00000B5C 79 #define BGE_SRAM_FW_CMD_MB 0x00000B78 80 #define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 81 #define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 82 #define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 83 #define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 84 #define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 85 #define BGE_SRAM_DATA_CFG_2 0x00000D38 86 #define BGE_SRAM_DATA_CFG_3 0x00000D3C 87 #define BGE_SRAM_DATA_CFG_4 0x00000D60 88 #define BGE_SRAM_DATA_CFG_5 0x00000E0C 89 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 90 #define BGE_UNMAPPED 0x00001000 91 #define BGE_UNMAPPED_END 0x00001FFF 92 #define BGE_DMA_DESCRIPTORS 0x00002000 93 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 94 #define BGE_SEND_RING_5717 0x00004000 95 #define BGE_SEND_RING_1_TO_4 0x00004000 96 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 97 98 /* Firmware interface */ 99 #define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 100 101 #define BGE_FW_CMD_DRV_ALIVE 0x00000001 102 #define BGE_FW_CMD_PAUSE 0x00000002 103 104 #define BGE_FW_HB_TIMEOUT_SEC 3 105 106 #define BGE_FW_DRV_STATE_START 0x00000001 107 #define BGE_FW_DRV_STATE_START_DONE 0x80000001 108 #define BGE_FW_DRV_STATE_UNLOAD 0x00000002 109 #define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 110 #define BGE_FW_DRV_STATE_SUSPEND 0x00000004 111 112 /* SRAM data version */ 113 #define BGE_SRAM_DATA_VER_SHIFT 16 114 115 /* Mappings for internal memory configuration */ 116 #define BGE_STD_RX_RINGS 0x00006000 117 #define BGE_STD_RX_RINGS_END 0x00006FFF 118 #define BGE_JUMBO_RX_RINGS 0x00007000 119 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 120 #define BGE_BUFFPOOL_1 0x00008000 121 #define BGE_BUFFPOOL_1_END 0x0000FFFF 122 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 123 #define BGE_BUFFPOOL_2_END 0x00017FFF 124 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 125 #define BGE_BUFFPOOL_3_END 0x0001FFFF 126 #define BGE_STD_RX_RINGS_5717 0x00040000 127 #define BGE_JUMBO_RX_RINGS_5717 0x00044400 128 129 /* Mappings for external SSRAM configurations */ 130 #define BGE_SEND_RING_5_TO_6 0x00006000 131 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 132 #define BGE_SEND_RING_7_TO_8 0x00007000 133 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 134 #define BGE_SEND_RING_9_TO_16 0x00008000 135 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 136 #define BGE_EXT_STD_RX_RINGS 0x0000C000 137 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 138 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 139 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 140 #define BGE_MINI_RX_RINGS 0x0000E000 141 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 142 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 143 #define BGE_AVAIL_REGION1_END 0x00017FFF 144 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 145 #define BGE_AVAIL_REGION2_END 0x0001FFFF 146 #define BGE_EXT_SSRAM 0x00020000 147 #define BGE_EXT_SSRAM_END 0x000FFFFF 148 149 150 /* 151 * BCM570x register offsets. These are memory mapped registers 152 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 153 * Each register must be accessed using 32 bit operations. 154 * 155 * All registers are accessed through a 32K shared memory block. 156 * The first group of registers are actually copies of the PCI 157 * configuration space registers. 158 */ 159 160 /* 161 * PCI registers defined in the PCI 2.2 spec. 162 */ 163 #define BGE_PCI_VID 0x00 164 #define BGE_PCI_DID 0x02 165 #define BGE_PCI_CMD 0x04 166 #define BGE_PCI_STS 0x06 167 #define BGE_PCI_REV 0x08 168 #define BGE_PCI_CLASS 0x09 169 #define BGE_PCI_CACHESZ 0x0C 170 #define BGE_PCI_LATTIMER 0x0D 171 #define BGE_PCI_HDRTYPE 0x0E 172 #define BGE_PCI_BIST 0x0F 173 #define BGE_PCI_BAR0 0x10 174 #define BGE_PCI_BAR1 0x14 175 #define BGE_PCI_BAR2 0x18 176 #define BGE_PCI_SUBSYS 0x2C 177 #define BGE_PCI_SUBVID 0x2E 178 #define BGE_PCI_ROMBASE 0x30 179 #define BGE_PCI_CAPPTR 0x34 180 #define BGE_PCI_INTLINE 0x3C 181 #define BGE_PCI_INTPIN 0x3D 182 #define BGE_PCI_MINGNT 0x3E 183 #define BGE_PCI_MAXLAT 0x3F 184 #define BGE_PCI_PCIXCAP 0x40 185 #define BGE_PCI_NEXTPTR_PM 0x41 186 #define BGE_PCIX_CMD 0x42 187 #define BGE_PCIX_STS 0x44 188 #define BGE_PCI_PWRMGMT_CAPID 0x48 189 #define BGE_PCI_NEXTPTR_VPD 0x49 190 #define BGE_PCI_PWRMGMT_CAPS 0x4A 191 #define BGE_PCI_PWRMGMT_CMD 0x4C 192 #define BGE_PCI_PWRMGMT_STS 0x4D 193 #define BGE_PCI_PWRMGMT_DATA 0x4F 194 #define BGE_PCI_VPD_CAPID 0x50 195 #define BGE_PCI_NEXTPTR_MSI 0x51 196 #define BGE_PCI_VPD_ADDR 0x52 197 #define BGE_PCI_VPD_DATA 0x54 198 #define BGE_PCI_MSI_CAPID 0x58 199 #define BGE_PCI_NEXTPTR_NONE 0x59 200 #define BGE_PCI_MSI_CTL 0x5A 201 #define BGE_PCI_MSI_ADDR_HI 0x5C 202 #define BGE_PCI_MSI_ADDR_LO 0x60 203 #define BGE_PCI_MSI_DATA 0x64 204 205 /* 206 * PCI Express definitions 207 * According to 208 * PCI Express base specification, REV. 1.0a 209 */ 210 211 /* PCI Express device control, 16bits */ 212 #define BGE_PCIE_DEVCTL 0x08 213 #define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 214 #define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 215 #define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 216 #define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 217 #define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 218 #define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 219 #define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 220 221 /* PCI MSI. ??? */ 222 #define BGE_PCIE_CAPID_REG 0xD0 223 #define BGE_PCIE_CAPID 0x10 224 225 /* 226 * PCI registers specific to the BCM570x family. 227 */ 228 #define BGE_PCI_MISC_CTL 0x68 229 #define BGE_PCI_DMA_RW_CTL 0x6C 230 #define BGE_PCI_PCISTATE 0x70 231 #define BGE_PCI_CLKCTL 0x74 232 #define BGE_PCI_REG_BASEADDR 0x78 233 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 234 #define BGE_PCI_REG_DATA 0x80 235 #define BGE_PCI_MEMWIN_DATA 0x84 236 #define BGE_PCI_MODECTL 0x88 237 #define BGE_PCI_MISC_CFG 0x8C 238 #define BGE_PCI_MISC_LOCALCTL 0x90 239 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 240 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 241 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 242 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 243 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 244 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 245 #define BGE_PCI_ISR_MBX_HI 0xB0 246 #define BGE_PCI_ISR_MBX_LO 0xB4 247 #define BGE_PCI_PRODID_ASICREV 0xBC 248 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 249 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 250 251 #define BGE_PCI_UNKNOWN0 0xC4 252 253 /* PCI Misc. Host control register */ 254 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 255 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 256 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 257 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 258 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 259 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 260 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 261 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 262 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 263 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 264 265 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 266 #if BYTE_ORDER == LITTLE_ENDIAN 267 #define BGE_DMA_SWAP_OPTIONS \ 268 BGE_MODECTL_WORDSWAP_NONFRAME| \ 269 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 270 #else 271 #define BGE_DMA_SWAP_OPTIONS \ 272 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 273 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 274 #endif 275 276 #define BGE_INIT \ 277 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 278 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS| \ 279 BGE_PCIMISCCTL_PCISTATE_RW) 280 281 #define BGE_CHIPID_TIGON_I 0x4000 282 #define BGE_CHIPID_TIGON_II 0x6000 283 #define BGE_CHIPID_BCM5700_A0 0x7000 284 #define BGE_CHIPID_BCM5700_A1 0x7001 285 #define BGE_CHIPID_BCM5700_B0 0x7100 286 #define BGE_CHIPID_BCM5700_B1 0x7101 287 #define BGE_CHIPID_BCM5700_B2 0x7102 288 #define BGE_CHIPID_BCM5700_B3 0x7103 289 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 290 #define BGE_CHIPID_BCM5700_C0 0x7200 291 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 292 #define BGE_CHIPID_BCM5701_B0 0x0100 293 #define BGE_CHIPID_BCM5701_B2 0x0102 294 #define BGE_CHIPID_BCM5701_B5 0x0105 295 #define BGE_CHIPID_BCM5703_A0 0x1000 296 #define BGE_CHIPID_BCM5703_A1 0x1001 297 #define BGE_CHIPID_BCM5703_A2 0x1002 298 #define BGE_CHIPID_BCM5703_A3 0x1003 299 #define BGE_CHIPID_BCM5703_B0 0x1100 300 #define BGE_CHIPID_BCM5704_A0 0x2000 301 #define BGE_CHIPID_BCM5704_A1 0x2001 302 #define BGE_CHIPID_BCM5704_A2 0x2002 303 #define BGE_CHIPID_BCM5704_A3 0x2003 304 #define BGE_CHIPID_BCM5704_B0 0x2100 305 #define BGE_CHIPID_BCM5705_A0 0x3000 306 #define BGE_CHIPID_BCM5705_A1 0x3001 307 #define BGE_CHIPID_BCM5705_A2 0x3002 308 #define BGE_CHIPID_BCM5705_A3 0x3003 309 #define BGE_CHIPID_BCM5750_A0 0x4000 310 #define BGE_CHIPID_BCM5750_A1 0x4001 311 #define BGE_CHIPID_BCM5750_A3 0x4003 312 #define BGE_CHIPID_BCM5750_B0 0x4010 313 #define BGE_CHIPID_BCM5750_B1 0x4101 314 #define BGE_CHIPID_BCM5750_C0 0x4200 315 #define BGE_CHIPID_BCM5750_C1 0x4201 316 #define BGE_CHIPID_BCM5750_C2 0x4202 317 #define BGE_CHIPID_BCM5714_A0 0x5000 318 #define BGE_CHIPID_BCM5761_A0 0x5761000 319 #define BGE_CHIPID_BCM5761_A1 0x5761100 320 #define BGE_CHIPID_BCM5784_A0 0x5784000 321 #define BGE_CHIPID_BCM5784_A1 0x5784100 322 #define BGE_CHIPID_BCM5752_A0 0x6000 323 #define BGE_CHIPID_BCM5752_A1 0x6001 324 #define BGE_CHIPID_BCM5752_A2 0x6002 325 #define BGE_CHIPID_BCM5714_B0 0x8000 326 #define BGE_CHIPID_BCM5714_B3 0x8003 327 #define BGE_CHIPID_BCM5715_A0 0x9000 328 #define BGE_CHIPID_BCM5715_A1 0x9001 329 #define BGE_CHIPID_BCM5715_A3 0x9003 330 #define BGE_CHIPID_BCM5755_A0 0xa000 331 #define BGE_CHIPID_BCM5755_A1 0xa001 332 #define BGE_CHIPID_BCM5755_A2 0xa002 333 #define BGE_CHIPID_BCM5755_C0 0xa200 334 #define BGE_CHIPID_BCM5787_A0 0xb000 335 #define BGE_CHIPID_BCM5787_A1 0xb001 336 #define BGE_CHIPID_BCM5787_A2 0xb002 337 #define BGE_CHIPID_BCM5906_A0 0xc000 338 #define BGE_CHIPID_BCM5906_A1 0xc001 339 #define BGE_CHIPID_BCM5906_A2 0xc002 340 #define BGE_CHIPID_BCM57762 0x57766000 341 #define BGE_CHIPID_BCM57780_A0 0x57780000 342 #define BGE_CHIPID_BCM57780_A1 0x57780001 343 #define BGE_CHIPID_BCM5717_A0 0x05717000 344 #define BGE_CHIPID_BCM5717_B0 0x05717100 345 #define BGE_CHIPID_BCM5719_A0 0x05719000 346 #define BGE_CHIPID_BCM5720_A0 0x05720000 347 #define BGE_CHIPID_BCM57765_A0 0x57785000 348 #define BGE_CHIPID_BCM57765_B0 0x57785100 349 350 /* shorthand one */ 351 #define BGE_ASICREV(x) ((x) >> 12) 352 #define BGE_ASICREV_BCM5700 0x07 353 #define BGE_ASICREV_BCM5701 0x00 354 #define BGE_ASICREV_BCM5703 0x01 355 #define BGE_ASICREV_BCM5704 0x02 356 #define BGE_ASICREV_BCM5705 0x03 357 #define BGE_ASICREV_BCM5750 0x04 358 #define BGE_ASICREV_BCM5714_A0 0x05 359 #define BGE_ASICREV_BCM5752 0x06 360 /* ASIC revision 0x07 is the original bcm5700 */ 361 #define BGE_ASICREV_BCM5780 0x08 362 #define BGE_ASICREV_BCM5714 0x09 363 #define BGE_ASICREV_BCM5755 0x0a 364 #define BGE_ASICREV_BCM5787 0x0b 365 #define BGE_ASICREV_BCM5906 0x0c 366 #define BGE_ASICREV_USE_PRODID_REG 0x0f 367 #define BGE_ASICREV_BCM5761 0x5761 368 #define BGE_ASICREV_BCM5784 0x5784 369 #define BGE_ASICREV_BCM5785 0x5785 370 #define BGE_ASICREV_BCM57780 0x57780 371 #define BGE_ASICREV_BCM5717 0x5717 372 #define BGE_ASICREV_BCM5719 0x5719 373 #define BGE_ASICREV_BCM5720 0x5720 374 #define BGE_ASICREV_BCM57765 0x57785 375 #define BGE_ASICREV_BCM57766 0x57766 376 377 /* chip revisions */ 378 #define BGE_CHIPREV(x) ((x) >> 8) 379 #define BGE_CHIPREV_5700_AX 0x70 380 #define BGE_CHIPREV_5700_BX 0x71 381 #define BGE_CHIPREV_5700_CX 0x72 382 #define BGE_CHIPREV_5701_AX 0x00 383 #define BGE_CHIPREV_5703_AX 0x10 384 #define BGE_CHIPREV_5704_AX 0x20 385 #define BGE_CHIPREV_5704_BX 0x21 386 #define BGE_CHIPREV_5750_AX 0x40 387 #define BGE_CHIPREV_5750_BX 0x41 388 #define BGE_CHIPREV_57765_AX 0x577850 389 390 /* PCI DMA Read/Write Control register */ 391 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 392 #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 393 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 394 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 395 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 396 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 397 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 398 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 399 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 400 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 401 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 402 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 403 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 404 405 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 406 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 407 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 408 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 409 410 #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 411 #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 412 413 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 414 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 415 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 416 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 417 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 418 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 419 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 420 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 421 422 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 423 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 424 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 425 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 426 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 427 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 428 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 429 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 430 431 /* 432 * PCI state register -- note, this register is read only 433 * unless the PCISTATE_RW bit of the PCI Misc. Host Control 434 * register is set. 435 */ 436 #define BGE_PCISTATE_FORCE_RESET 0x00000001 437 #define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 438 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 439 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 440 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 441 #define BGE_PCISTATE_ROM_ENABLE 0x00000020 442 #define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 443 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 444 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 445 #define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 446 #define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 447 #define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 448 #define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 449 450 /* 451 * The following bits in PCI state register are reserved. 452 * If we check that the register values reverts on reset, 453 * do not check these bits. On some 5704C (rev A3) and some 454 * Altima chips, these bits do not revert until much later 455 * in the bge driver's bge_reset() chip-reset state machine. 456 */ 457 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 458 459 /* 460 * PCI Clock Control register -- note, this register is read only 461 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 462 * register is set. 463 */ 464 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 465 #define BGE_PCICLOCKCTL_M66EN 0x00000080 466 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 467 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 468 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 469 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 470 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 471 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 472 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 473 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 474 475 /* 476 * High priority mailbox registers 477 * Each mailbox is 64-bits wide, though we only use the 478 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 479 * first. The NIC will load the mailbox after the lower 32 bit word 480 * has been updated. 481 */ 482 #define BGE_MBX_IRQ0_HI 0x0200 483 #define BGE_MBX_IRQ0_LO 0x0204 484 #define BGE_MBX_IRQ1_HI 0x0208 485 #define BGE_MBX_IRQ1_LO 0x020C 486 #define BGE_MBX_IRQ2_HI 0x0210 487 #define BGE_MBX_IRQ2_LO 0x0214 488 #define BGE_MBX_IRQ3_HI 0x0218 489 #define BGE_MBX_IRQ3_LO 0x021C 490 #define BGE_MBX_GEN0_HI 0x0220 491 #define BGE_MBX_GEN0_LO 0x0224 492 #define BGE_MBX_GEN1_HI 0x0228 493 #define BGE_MBX_GEN1_LO 0x022C 494 #define BGE_MBX_GEN2_HI 0x0230 495 #define BGE_MBX_GEN2_LO 0x0234 496 #define BGE_MBX_GEN3_HI 0x0228 497 #define BGE_MBX_GEN3_LO 0x022C 498 #define BGE_MBX_GEN4_HI 0x0240 499 #define BGE_MBX_GEN4_LO 0x0244 500 #define BGE_MBX_GEN5_HI 0x0248 501 #define BGE_MBX_GEN5_LO 0x024C 502 #define BGE_MBX_GEN6_HI 0x0250 503 #define BGE_MBX_GEN6_LO 0x0254 504 #define BGE_MBX_GEN7_HI 0x0258 505 #define BGE_MBX_GEN7_LO 0x025C 506 #define BGE_MBX_RELOAD_STATS_HI 0x0260 507 #define BGE_MBX_RELOAD_STATS_LO 0x0264 508 #define BGE_MBX_RX_STD_PROD_HI 0x0268 509 #define BGE_MBX_RX_STD_PROD_LO 0x026C 510 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 511 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 512 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 513 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 514 #define BGE_MBX_RX_CONS0_HI 0x0280 515 #define BGE_MBX_RX_CONS0_LO 0x0284 516 #define BGE_MBX_RX_CONS1_HI 0x0288 517 #define BGE_MBX_RX_CONS1_LO 0x028C 518 #define BGE_MBX_RX_CONS2_HI 0x0290 519 #define BGE_MBX_RX_CONS2_LO 0x0294 520 #define BGE_MBX_RX_CONS3_HI 0x0298 521 #define BGE_MBX_RX_CONS3_LO 0x029C 522 #define BGE_MBX_RX_CONS4_HI 0x02A0 523 #define BGE_MBX_RX_CONS4_LO 0x02A4 524 #define BGE_MBX_RX_CONS5_HI 0x02A8 525 #define BGE_MBX_RX_CONS5_LO 0x02AC 526 #define BGE_MBX_RX_CONS6_HI 0x02B0 527 #define BGE_MBX_RX_CONS6_LO 0x02B4 528 #define BGE_MBX_RX_CONS7_HI 0x02B8 529 #define BGE_MBX_RX_CONS7_LO 0x02BC 530 #define BGE_MBX_RX_CONS8_HI 0x02C0 531 #define BGE_MBX_RX_CONS8_LO 0x02C4 532 #define BGE_MBX_RX_CONS9_HI 0x02C8 533 #define BGE_MBX_RX_CONS9_LO 0x02CC 534 #define BGE_MBX_RX_CONS10_HI 0x02D0 535 #define BGE_MBX_RX_CONS10_LO 0x02D4 536 #define BGE_MBX_RX_CONS11_HI 0x02D8 537 #define BGE_MBX_RX_CONS11_LO 0x02DC 538 #define BGE_MBX_RX_CONS12_HI 0x02E0 539 #define BGE_MBX_RX_CONS12_LO 0x02E4 540 #define BGE_MBX_RX_CONS13_HI 0x02E8 541 #define BGE_MBX_RX_CONS13_LO 0x02EC 542 #define BGE_MBX_RX_CONS14_HI 0x02F0 543 #define BGE_MBX_RX_CONS14_LO 0x02F4 544 #define BGE_MBX_RX_CONS15_HI 0x02F8 545 #define BGE_MBX_RX_CONS15_LO 0x02FC 546 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 547 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 548 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 549 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 550 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 551 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 552 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 553 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 554 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 555 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 556 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 557 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 558 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 559 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 560 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 561 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 562 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 563 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 564 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 565 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 566 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 567 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 568 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 569 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 570 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 571 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 572 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 573 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 574 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 575 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 576 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 577 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 578 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 579 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 580 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 581 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 582 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 583 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 584 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 585 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 586 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 587 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 588 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 589 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 590 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 591 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 592 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 593 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 594 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 595 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 596 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 597 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 598 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 599 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 600 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 601 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 602 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 603 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 604 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 605 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 606 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 607 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 608 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 609 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 610 611 #define BGE_TX_RINGS_MAX 1 612 #define BGE_TX_RINGS_57765_MAX 2 613 #define BGE_TX_RINGS_5717_MAX 4 614 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 615 #define BGE_RX_RINGS_MAX 16 616 617 /* Ethernet MAC control registers */ 618 #define BGE_MAC_MODE 0x0400 619 #define BGE_MAC_STS 0x0404 620 #define BGE_MAC_EVT_ENB 0x0408 621 #define BGE_MAC_LED_CTL 0x040C 622 #define BGE_MAC_ADDR1_LO 0x0410 623 #define BGE_MAC_ADDR1_HI 0x0414 624 #define BGE_MAC_ADDR2_LO 0x0418 625 #define BGE_MAC_ADDR2_HI 0x041C 626 #define BGE_MAC_ADDR3_LO 0x0420 627 #define BGE_MAC_ADDR3_HI 0x0424 628 #define BGE_MAC_ADDR4_LO 0x0428 629 #define BGE_MAC_ADDR4_HI 0x042C 630 #define BGE_WOL_PATPTR 0x0430 631 #define BGE_WOL_PATCFG 0x0434 632 #define BGE_TX_RANDOM_BACKOFF 0x0438 633 #define BGE_RX_MTU 0x043C 634 #define BGE_GBIT_PCS_TEST 0x0440 635 #define BGE_TX_TBI_AUTONEG 0x0444 636 #define BGE_RX_TBI_AUTONEG 0x0448 637 #define BGE_MI_COMM 0x044C 638 #define BGE_MI_STS 0x0450 639 #define BGE_MI_MODE 0x0454 640 #define BGE_AUTOPOLL_STS 0x0458 641 #define BGE_TX_MODE 0x045C 642 #define BGE_TX_STS 0x0460 643 #define BGE_TX_LENGTHS 0x0464 644 #define BGE_RX_MODE 0x0468 645 #define BGE_RX_STS 0x046C 646 #define BGE_MAR0 0x0470 647 #define BGE_MAR1 0x0474 648 #define BGE_MAR2 0x0478 649 #define BGE_MAR3 0x047C 650 #define BGE_RX_BD_RULES_CTL0 0x0480 651 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 652 #define BGE_RX_BD_RULES_CTL1 0x0488 653 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 654 #define BGE_RX_BD_RULES_CTL2 0x0490 655 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 656 #define BGE_RX_BD_RULES_CTL3 0x0498 657 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 658 #define BGE_RX_BD_RULES_CTL4 0x04A0 659 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 660 #define BGE_RX_BD_RULES_CTL5 0x04A8 661 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 662 #define BGE_RX_BD_RULES_CTL6 0x04B0 663 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 664 #define BGE_RX_BD_RULES_CTL7 0x04B8 665 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 666 #define BGE_RX_BD_RULES_CTL8 0x04C0 667 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 668 #define BGE_RX_BD_RULES_CTL9 0x04C8 669 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 670 #define BGE_RX_BD_RULES_CTL10 0x04D0 671 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 672 #define BGE_RX_BD_RULES_CTL11 0x04D8 673 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 674 #define BGE_RX_BD_RULES_CTL12 0x04E0 675 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 676 #define BGE_RX_BD_RULES_CTL13 0x04E8 677 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 678 #define BGE_RX_BD_RULES_CTL14 0x04F0 679 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 680 #define BGE_RX_BD_RULES_CTL15 0x04F8 681 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 682 #define BGE_RX_RULES_CFG 0x0500 683 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 684 #define BGE_SERDES_CFG 0x0590 685 #define BGE_SGDIG_CFG 0x05B0 686 #define BGE_SGDIG_STS 0x05B4 687 #define BGE_MAC_STATS 0x0800 688 689 /* Ethernet MAC Mode register */ 690 #define BGE_MACMODE_RESET 0x00000001 691 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 692 #define BGE_MACMODE_PORTMODE 0x0000000C 693 #define BGE_MACMODE_LOOPBACK 0x00000010 694 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 695 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 696 #define BGE_MACMODE_MAX_DEFER 0x00000200 697 #define BGE_MACMODE_LINK_POLARITY 0x00000400 698 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 699 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 700 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 701 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 702 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 703 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 704 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 705 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 706 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 707 #define BGE_MACMODE_MIP_ENB 0x00100000 708 #define BGE_MACMODE_TXDMA_ENB 0x00200000 709 #define BGE_MACMODE_RXDMA_ENB 0x00400000 710 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 711 #define BGE_MACMODE_APE_RX_EN 0x08000000 712 #define BGE_MACMODE_APE_TX_EN 0x10000000 713 714 #define BGE_PORTMODE_NONE 0x00000000 715 #define BGE_PORTMODE_MII 0x00000004 716 #define BGE_PORTMODE_GMII 0x00000008 717 #define BGE_PORTMODE_TBI 0x0000000C 718 719 /* MAC Status register */ 720 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 721 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 722 #define BGE_MACSTAT_RX_CFG 0x00000004 723 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 724 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 725 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 726 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 727 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 728 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 729 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 730 #define BGE_MACSTAT_ODI_ERROR 0x02000000 731 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 732 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 733 734 /* MAC Event Enable Register */ 735 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 736 #define BGE_EVTENB_LINK_CHANGED 0x00001000 737 #define BGE_EVTENB_MI_COMPLETE 0x00400000 738 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 739 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 740 #define BGE_EVTENB_ODI_ERROR 0x02000000 741 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 742 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 743 744 /* LED Control Register */ 745 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 746 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 747 #define BGE_LEDCTL_100MBPS_LED 0x00000004 748 #define BGE_LEDCTL_10MBPS_LED 0x00000008 749 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 750 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 751 #define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 752 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 753 #define BGE_LEDCTL_100MBPS_STS 0x00000100 754 #define BGE_LEDCTL_10MBPS_STS 0x00000200 755 #define BGE_LEDCTL_TRAFLED_STS 0x00000400 756 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 757 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 758 759 /* TX backoff seed register */ 760 #define BGE_TX_BACKOFF_SEED_MASK 0x3FF 761 762 /* Autopoll status register */ 763 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 764 765 /* Transmit MAC mode register */ 766 #define BGE_TXMODE_RESET 0x00000001 767 #define BGE_TXMODE_ENABLE 0x00000002 768 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 769 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 770 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 771 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 772 #define BGE_TXMODE_JMB_FRM_LEN 0x00400000 773 #define BGE_TXMODE_CNT_DN_MODE 0x00800000 774 775 /* Transmit MAC status register */ 776 #define BGE_TXSTAT_RX_XOFFED 0x00000001 777 #define BGE_TXSTAT_SENT_XOFF 0x00000002 778 #define BGE_TXSTAT_SENT_XON 0x00000004 779 #define BGE_TXSTAT_LINK_UP 0x00000008 780 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 781 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 782 783 /* Transmit MAC lengths register */ 784 #define BGE_TXLEN_SLOTTIME 0x000000FF 785 #define BGE_TXLEN_IPG 0x00000F00 786 #define BGE_TXLEN_CRS 0x00003000 787 #define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 788 #define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 789 790 /* Receive MAC mode register */ 791 #define BGE_RXMODE_RESET 0x00000001 792 #define BGE_RXMODE_ENABLE 0x00000002 793 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 794 #define BGE_RXMODE_RX_GIANTS 0x00000020 795 #define BGE_RXMODE_RX_RUNTS 0x00000040 796 #define BGE_RXMODE_8022_LENCHECK 0x00000080 797 #define BGE_RXMODE_RX_PROMISC 0x00000100 798 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 799 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 800 #define BGE_RXMODE_IPV6_ENABLE 0x01000000 801 802 /* Receive MAC status register */ 803 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 804 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 805 #define BGE_RXSTAT_RCVD_XON 0x00000004 806 807 /* Receive Rules Control register */ 808 #define BGE_RXRULECTL_OFFSET 0x000000FF 809 #define BGE_RXRULECTL_CLASS 0x00001F00 810 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 811 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 812 #define BGE_RXRULECTL_MAP 0x01000000 813 #define BGE_RXRULECTL_DISCARD 0x02000000 814 #define BGE_RXRULECTL_MASK 0x04000000 815 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 816 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 817 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 818 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 819 820 /* Receive Rules Mask register */ 821 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 822 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 823 824 /* SGDIG config (not documented) */ 825 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 826 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 827 #define BGE_SGDIGCFG_SEND 0x40000000 828 #define BGE_SGDIGCFG_AUTO 0x80000000 829 830 /* SGDIG status (not documented) */ 831 #define BGE_SGDIGSTS_DONE 0x00000002 832 #define BGE_SGDIGSTS_IS_SERDES 0x00000100 833 834 /* MI communication register */ 835 #define BGE_MICOMM_DATA 0x0000FFFF 836 #define BGE_MICOMM_REG 0x001F0000 837 #define BGE_MICOMM_PHY 0x03E00000 838 #define BGE_MICOMM_CMD 0x0C000000 839 #define BGE_MICOMM_READFAIL 0x10000000 840 #define BGE_MICOMM_BUSY 0x20000000 841 842 #define BGE_MIREG(x) ((x & 0x1F) << 16) 843 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 844 #define BGE_MICMD_WRITE 0x04000000 845 #define BGE_MICMD_READ 0x08000000 846 847 /* MI status register */ 848 #define BGE_MISTS_LINK 0x00000001 849 #define BGE_MISTS_10MBPS 0x00000002 850 851 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 852 #define BGE_MIMODE_AUTOPOLL 0x00000010 853 #define BGE_MIMODE_PHYADDR_SHIFT 5 854 #define BGE_MIMODE_PHYADDR_MASK 0x000003E0 855 #define BGE_MIMODE_CLKCNT 0x001F0000 856 #define BGE_MIMODE_500KHZ_CONST 0x00008000 857 #define BGE_MIMODE_BASE 0x000C0000 858 859 #define BGE_MIMODE_PHYADDR(x) ((x) << BGE_MIMODE_PHYADDR_SHIFT) 860 861 /* 862 * Send data initiator control registers. 863 */ 864 #define BGE_SDI_MODE 0x0C00 865 #define BGE_SDI_STATUS 0x0C04 866 #define BGE_SDI_STATS_CTL 0x0C08 867 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 868 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 869 #define BGE_ISO_PKT_TX 0x0C20 870 #define BGE_LOCSTATS_COS0 0x0C80 871 #define BGE_LOCSTATS_COS1 0x0C84 872 #define BGE_LOCSTATS_COS2 0x0C88 873 #define BGE_LOCSTATS_COS3 0x0C8C 874 #define BGE_LOCSTATS_COS4 0x0C90 875 #define BGE_LOCSTATS_COS5 0x0C84 876 #define BGE_LOCSTATS_COS6 0x0C98 877 #define BGE_LOCSTATS_COS7 0x0C9C 878 #define BGE_LOCSTATS_COS8 0x0CA0 879 #define BGE_LOCSTATS_COS9 0x0CA4 880 #define BGE_LOCSTATS_COS10 0x0CA8 881 #define BGE_LOCSTATS_COS11 0x0CAC 882 #define BGE_LOCSTATS_COS12 0x0CB0 883 #define BGE_LOCSTATS_COS13 0x0CB4 884 #define BGE_LOCSTATS_COS14 0x0CB8 885 #define BGE_LOCSTATS_COS15 0x0CBC 886 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 887 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 888 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 889 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 890 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 891 #define BGE_LOCSTATS_IRQS 0x0CD4 892 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 893 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 894 895 /* Send Data Initiator mode register */ 896 #define BGE_SDIMODE_RESET 0x00000001 897 #define BGE_SDIMODE_ENABLE 0x00000002 898 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 899 #define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 900 901 /* Send Data Initiator stats register */ 902 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 903 904 /* Send Data Initiator stats control register */ 905 #define BGE_SDISTATSCTL_ENABLE 0x00000001 906 #define BGE_SDISTATSCTL_FASTER 0x00000002 907 #define BGE_SDISTATSCTL_CLEAR 0x00000004 908 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 909 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 910 911 /* 912 * Send Data Completion Control registers 913 */ 914 #define BGE_SDC_MODE 0x1000 915 #define BGE_SDC_STATUS 0x1004 916 917 /* Send Data completion mode register */ 918 #define BGE_SDCMODE_RESET 0x00000001 919 #define BGE_SDCMODE_ENABLE 0x00000002 920 #define BGE_SDCMODE_ATTN 0x00000004 921 #define BGE_SDCMODE_CDELAY 0x00000010 922 923 /* Send Data completion status register */ 924 #define BGE_SDCSTAT_ATTN 0x00000004 925 926 /* 927 * Send BD Ring Selector Control registers 928 */ 929 #define BGE_SRS_MODE 0x1400 930 #define BGE_SRS_STATUS 0x1404 931 #define BGE_SRS_HWDIAG 0x1408 932 #define BGE_SRS_LOC_NIC_CONS0 0x1440 933 #define BGE_SRS_LOC_NIC_CONS1 0x1444 934 #define BGE_SRS_LOC_NIC_CONS2 0x1448 935 #define BGE_SRS_LOC_NIC_CONS3 0x144C 936 #define BGE_SRS_LOC_NIC_CONS4 0x1450 937 #define BGE_SRS_LOC_NIC_CONS5 0x1454 938 #define BGE_SRS_LOC_NIC_CONS6 0x1458 939 #define BGE_SRS_LOC_NIC_CONS7 0x145C 940 #define BGE_SRS_LOC_NIC_CONS8 0x1460 941 #define BGE_SRS_LOC_NIC_CONS9 0x1464 942 #define BGE_SRS_LOC_NIC_CONS10 0x1468 943 #define BGE_SRS_LOC_NIC_CONS11 0x146C 944 #define BGE_SRS_LOC_NIC_CONS12 0x1470 945 #define BGE_SRS_LOC_NIC_CONS13 0x1474 946 #define BGE_SRS_LOC_NIC_CONS14 0x1478 947 #define BGE_SRS_LOC_NIC_CONS15 0x147C 948 949 /* Send BD Ring Selector Mode register */ 950 #define BGE_SRSMODE_RESET 0x00000001 951 #define BGE_SRSMODE_ENABLE 0x00000002 952 #define BGE_SRSMODE_ATTN 0x00000004 953 954 /* Send BD Ring Selector Status register */ 955 #define BGE_SRSSTAT_ERROR 0x00000004 956 957 /* Send BD Ring Selector HW Diagnostics register */ 958 #define BGE_SRSHWDIAG_STATE 0x0000000F 959 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 960 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 961 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 962 963 /* 964 * Send BD Initiator Selector Control registers 965 */ 966 #define BGE_SBDI_MODE 0x1800 967 #define BGE_SBDI_STATUS 0x1804 968 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 969 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 970 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 971 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 972 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 973 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 974 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 975 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 976 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 977 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 978 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 979 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 980 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 981 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 982 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 983 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 984 985 /* Send BD Initiator Mode register */ 986 #define BGE_SBDIMODE_RESET 0x00000001 987 #define BGE_SBDIMODE_ENABLE 0x00000002 988 #define BGE_SBDIMODE_ATTN 0x00000004 989 990 /* Send BD Initiator Status register */ 991 #define BGE_SBDISTAT_ERROR 0x00000004 992 993 /* 994 * Send BD Completion Control registers 995 */ 996 #define BGE_SBDC_MODE 0x1C00 997 #define BGE_SBDC_STATUS 0x1C04 998 999 /* Send BD Completion Control Mode register */ 1000 #define BGE_SBDCMODE_RESET 0x00000001 1001 #define BGE_SBDCMODE_ENABLE 0x00000002 1002 #define BGE_SBDCMODE_ATTN 0x00000004 1003 1004 /* Send BD Completion Control Status register */ 1005 #define BGE_SBDCSTAT_ATTN 0x00000004 1006 1007 /* 1008 * Receive List Placement Control registers 1009 */ 1010 #define BGE_RXLP_MODE 0x2000 1011 #define BGE_RXLP_STATUS 0x2004 1012 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 1013 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1014 #define BGE_RXLP_CFG 0x2010 1015 #define BGE_RXLP_STATS_CTL 0x2014 1016 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1017 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1018 #define BGE_RXLP_HEAD0 0x2100 1019 #define BGE_RXLP_TAIL0 0x2104 1020 #define BGE_RXLP_COUNT0 0x2108 1021 #define BGE_RXLP_HEAD1 0x2110 1022 #define BGE_RXLP_TAIL1 0x2114 1023 #define BGE_RXLP_COUNT1 0x2118 1024 #define BGE_RXLP_HEAD2 0x2120 1025 #define BGE_RXLP_TAIL2 0x2124 1026 #define BGE_RXLP_COUNT2 0x2128 1027 #define BGE_RXLP_HEAD3 0x2130 1028 #define BGE_RXLP_TAIL3 0x2134 1029 #define BGE_RXLP_COUNT3 0x2138 1030 #define BGE_RXLP_HEAD4 0x2140 1031 #define BGE_RXLP_TAIL4 0x2144 1032 #define BGE_RXLP_COUNT4 0x2148 1033 #define BGE_RXLP_HEAD5 0x2150 1034 #define BGE_RXLP_TAIL5 0x2154 1035 #define BGE_RXLP_COUNT5 0x2158 1036 #define BGE_RXLP_HEAD6 0x2160 1037 #define BGE_RXLP_TAIL6 0x2164 1038 #define BGE_RXLP_COUNT6 0x2168 1039 #define BGE_RXLP_HEAD7 0x2170 1040 #define BGE_RXLP_TAIL7 0x2174 1041 #define BGE_RXLP_COUNT7 0x2178 1042 #define BGE_RXLP_HEAD8 0x2180 1043 #define BGE_RXLP_TAIL8 0x2184 1044 #define BGE_RXLP_COUNT8 0x2188 1045 #define BGE_RXLP_HEAD9 0x2190 1046 #define BGE_RXLP_TAIL9 0x2194 1047 #define BGE_RXLP_COUNT9 0x2198 1048 #define BGE_RXLP_HEAD10 0x21A0 1049 #define BGE_RXLP_TAIL10 0x21A4 1050 #define BGE_RXLP_COUNT10 0x21A8 1051 #define BGE_RXLP_HEAD11 0x21B0 1052 #define BGE_RXLP_TAIL11 0x21B4 1053 #define BGE_RXLP_COUNT11 0x21B8 1054 #define BGE_RXLP_HEAD12 0x21C0 1055 #define BGE_RXLP_TAIL12 0x21C4 1056 #define BGE_RXLP_COUNT12 0x21C8 1057 #define BGE_RXLP_HEAD13 0x21D0 1058 #define BGE_RXLP_TAIL13 0x21D4 1059 #define BGE_RXLP_COUNT13 0x21D8 1060 #define BGE_RXLP_HEAD14 0x21E0 1061 #define BGE_RXLP_TAIL14 0x21E4 1062 #define BGE_RXLP_COUNT14 0x21E8 1063 #define BGE_RXLP_HEAD15 0x21F0 1064 #define BGE_RXLP_TAIL15 0x21F4 1065 #define BGE_RXLP_COUNT15 0x21F8 1066 #define BGE_RXLP_LOCSTAT_COS0 0x2200 1067 #define BGE_RXLP_LOCSTAT_COS1 0x2204 1068 #define BGE_RXLP_LOCSTAT_COS2 0x2208 1069 #define BGE_RXLP_LOCSTAT_COS3 0x220C 1070 #define BGE_RXLP_LOCSTAT_COS4 0x2210 1071 #define BGE_RXLP_LOCSTAT_COS5 0x2214 1072 #define BGE_RXLP_LOCSTAT_COS6 0x2218 1073 #define BGE_RXLP_LOCSTAT_COS7 0x221C 1074 #define BGE_RXLP_LOCSTAT_COS8 0x2220 1075 #define BGE_RXLP_LOCSTAT_COS9 0x2224 1076 #define BGE_RXLP_LOCSTAT_COS10 0x2228 1077 #define BGE_RXLP_LOCSTAT_COS11 0x222C 1078 #define BGE_RXLP_LOCSTAT_COS12 0x2230 1079 #define BGE_RXLP_LOCSTAT_COS13 0x2234 1080 #define BGE_RXLP_LOCSTAT_COS14 0x2238 1081 #define BGE_RXLP_LOCSTAT_COS15 0x223C 1082 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1083 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1084 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1085 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1086 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1087 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1088 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1089 1090 1091 /* Receive List Placement mode register */ 1092 #define BGE_RXLPMODE_RESET 0x00000001 1093 #define BGE_RXLPMODE_ENABLE 0x00000002 1094 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1095 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1096 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1097 1098 /* Receive List Placement Status register */ 1099 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1100 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1101 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1102 1103 /* Receive List Placement Statistics Enable Mask register */ 1104 #define BGE_RXLPSTATCONTROL_DACK_FIX 0x00040000 1105 #define BGE_RXLPSTATCONTROL_LBIRST_FIX 0x00400000 1106 1107 /* 1108 * Receive Data and Receive BD Initiator Control Registers 1109 */ 1110 #define BGE_RDBDI_MODE 0x2400 1111 #define BGE_RDBDI_STATUS 0x2404 1112 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1113 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1114 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1115 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1116 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1117 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1118 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1119 #define BGE_RX_STD_RCB_NICADDR 0x245C 1120 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1121 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1122 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1123 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1124 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1125 #define BGE_RDBDI_STD_RX_CONS 0x2474 1126 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1127 #define BGE_RDBDI_RETURN_PROD0 0x2480 1128 #define BGE_RDBDI_RETURN_PROD1 0x2484 1129 #define BGE_RDBDI_RETURN_PROD2 0x2488 1130 #define BGE_RDBDI_RETURN_PROD3 0x248C 1131 #define BGE_RDBDI_RETURN_PROD4 0x2490 1132 #define BGE_RDBDI_RETURN_PROD5 0x2494 1133 #define BGE_RDBDI_RETURN_PROD6 0x2498 1134 #define BGE_RDBDI_RETURN_PROD7 0x249C 1135 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1136 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1137 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1138 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1139 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1140 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1141 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1142 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1143 #define BGE_RDBDI_HWDIAG 0x24C0 1144 1145 1146 /* Receive Data and Receive BD Initiator Mode register */ 1147 #define BGE_RDBDIMODE_RESET 0x00000001 1148 #define BGE_RDBDIMODE_ENABLE 0x00000002 1149 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1150 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1151 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1152 1153 /* Receive Data and Receive BD Initiator Status register */ 1154 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1155 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1156 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1157 1158 1159 /* 1160 * Receive Data Completion Control registers 1161 */ 1162 #define BGE_RDC_MODE 0x2800 1163 1164 /* Receive Data Completion Mode register */ 1165 #define BGE_RDCMODE_RESET 0x00000001 1166 #define BGE_RDCMODE_ENABLE 0x00000002 1167 #define BGE_RDCMODE_ATTN 0x00000004 1168 1169 /* 1170 * Receive BD Initiator Control registers 1171 */ 1172 #define BGE_RBDI_MODE 0x2C00 1173 #define BGE_RBDI_STATUS 0x2C04 1174 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1175 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1176 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1177 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1178 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1179 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1180 1181 #define BGE_STD_REPL_LWM 0x2D00 1182 #define BGE_JUMBO_REPL_LWM 0x2D04 1183 1184 /* Receive BD Initiator Mode register */ 1185 #define BGE_RBDIMODE_RESET 0x00000001 1186 #define BGE_RBDIMODE_ENABLE 0x00000002 1187 #define BGE_RBDIMODE_ATTN 0x00000004 1188 1189 /* Receive BD Initiator Status register */ 1190 #define BGE_RBDISTAT_ATTN 0x00000004 1191 1192 /* 1193 * Receive BD Completion Control registers 1194 */ 1195 #define BGE_RBDC_MODE 0x3000 1196 #define BGE_RBDC_STATUS 0x3004 1197 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1198 #define BGE_RBDC_STD_BD_PROD 0x300C 1199 #define BGE_RBDC_MINI_BD_PROD 0x3010 1200 1201 /* Receive BD completion mode register */ 1202 #define BGE_RBDCMODE_RESET 0x00000001 1203 #define BGE_RBDCMODE_ENABLE 0x00000002 1204 #define BGE_RBDCMODE_ATTN 0x00000004 1205 1206 /* Receive BD completion status register */ 1207 #define BGE_RBDCSTAT_ERROR 0x00000004 1208 1209 /* 1210 * Receive List Selector Control registers 1211 */ 1212 #define BGE_RXLS_MODE 0x3400 1213 #define BGE_RXLS_STATUS 0x3404 1214 1215 /* Receive List Selector Mode register */ 1216 #define BGE_RXLSMODE_RESET 0x00000001 1217 #define BGE_RXLSMODE_ENABLE 0x00000002 1218 #define BGE_RXLSMODE_ATTN 0x00000004 1219 1220 /* Receive List Selector Status register */ 1221 #define BGE_RXLSSTAT_ERROR 0x00000004 1222 1223 /* 1224 * Central Power Management Unit (CPMU) registers 1225 */ 1226 #define BGE_CPMU_CTRL 0x3600 1227 #define BGE_CPMU_LSPD_10MB_CLK 0x3604 1228 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1229 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1230 #define BGE_CPMU_HST_ACC 0x361C 1231 #define BGE_CPMU_CLCK_ORIDE 0x3624 1232 #define BGE_CPMU_CLCK_STAT 0x3630 1233 #define BGE_CPMU_MUTEX_REQ 0x365C 1234 #define BGE_CPMU_MUTEX_GNT 0x3660 1235 #define BGE_CPMU_PHY_STRAP 0x3664 1236 #define BGE_CPMU_PADRNG_CTL 0x3668 1237 1238 /* CPMU Control register */ 1239 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1240 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1241 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1242 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1243 1244 /* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1245 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1246 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1247 1248 /* Link Speed 1000MB Power Mode Clock Policy register */ 1249 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1250 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1251 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1252 1253 /* Link Aware Power Mode Clock Policy register */ 1254 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1255 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1256 1257 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1258 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1259 1260 /* Clock Speed Override Policy register */ 1261 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1262 1263 /* CPMU Clock Status register */ 1264 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1265 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1266 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1267 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1268 1269 /* CPMU Mutex Request register */ 1270 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1271 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1272 1273 /* CPMU GPHY Strap register */ 1274 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1275 1276 /* CPMU Padring Control register */ 1277 #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1278 1279 /* 1280 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1281 */ 1282 #define BGE_MBCF_MODE 0x3800 1283 #define BGE_MBCF_STATUS 0x3804 1284 1285 /* Mbuf Cluster Free mode register */ 1286 #define BGE_MBCFMODE_RESET 0x00000001 1287 #define BGE_MBCFMODE_ENABLE 0x00000002 1288 #define BGE_MBCFMODE_ATTN 0x00000004 1289 1290 /* Mbuf Cluster Free status register */ 1291 #define BGE_MBCFSTAT_ERROR 0x00000004 1292 1293 /* 1294 * Host Coalescing Control registers 1295 */ 1296 #define BGE_HCC_MODE 0x3C00 1297 #define BGE_HCC_STATUS 0x3C04 1298 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1299 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1300 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1301 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1302 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1303 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1304 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1305 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1306 #define BGE_HCC_STATS_TICKS 0x3C28 1307 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1308 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1309 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1310 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1311 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1312 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1313 #define BGE_FLOW_ATTN 0x3C48 1314 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1315 #define BGE_HCC_STD_BD_CONS 0x3C54 1316 #define BGE_HCC_MINI_BD_CONS 0x3C58 1317 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1318 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1319 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1320 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1321 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1322 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1323 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1324 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1325 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1326 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1327 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1328 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1329 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1330 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1331 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1332 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1333 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1334 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1335 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1336 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1337 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1338 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1339 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1340 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1341 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1342 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1343 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1344 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1345 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1346 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1347 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1348 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1349 1350 1351 /* Host coalescing mode register */ 1352 #define BGE_HCCMODE_RESET 0x00000001 1353 #define BGE_HCCMODE_ENABLE 0x00000002 1354 #define BGE_HCCMODE_ATTN 0x00000004 1355 #define BGE_HCCMODE_COAL_NOW 0x00000008 1356 #define BGE_HCCMODE_MSI_BITS 0x00000070 1357 #define BGE_HCCMODE_64BYTE 0x00000080 1358 #define BGE_HCCMODE_32BYTE 0x00000100 1359 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1360 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1361 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1362 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1363 1364 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1365 1366 #define BGE_STATBLKSZ_FULL 0x00000000 1367 #define BGE_STATBLKSZ_64BYTE 0x00000080 1368 #define BGE_STATBLKSZ_32BYTE 0x00000100 1369 1370 /* Host coalescing status register */ 1371 #define BGE_HCCSTAT_ERROR 0x00000004 1372 1373 /* Flow attention register */ 1374 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1375 #define BGE_FLOWATTN_MEMARB 0x00000080 1376 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1377 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1378 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1379 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1380 #define BGE_FLOWATTN_RDBDI 0x00080000 1381 #define BGE_FLOWATTN_RXLS 0x00100000 1382 #define BGE_FLOWATTN_RXLP 0x00200000 1383 #define BGE_FLOWATTN_RBDC 0x00400000 1384 #define BGE_FLOWATTN_RBDI 0x00800000 1385 #define BGE_FLOWATTN_SDC 0x08000000 1386 #define BGE_FLOWATTN_SDI 0x10000000 1387 #define BGE_FLOWATTN_SRS 0x20000000 1388 #define BGE_FLOWATTN_SBDC 0x40000000 1389 #define BGE_FLOWATTN_SBDI 0x80000000 1390 1391 /* 1392 * Memory arbiter registers 1393 */ 1394 #define BGE_MARB_MODE 0x4000 1395 #define BGE_MARB_STATUS 0x4004 1396 #define BGE_MARB_TRAPADDR_HI 0x4008 1397 #define BGE_MARB_TRAPADDR_LO 0x400C 1398 1399 /* Memory arbiter mode register */ 1400 #define BGE_MARBMODE_RESET 0x00000001 1401 #define BGE_MARBMODE_ENABLE 0x00000002 1402 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1403 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1404 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1405 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1406 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1407 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1408 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1409 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1410 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1411 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1412 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1413 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1414 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1415 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1416 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1417 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1418 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1419 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1420 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1421 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1422 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1423 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1424 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1425 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1426 1427 /* Memory arbiter status register */ 1428 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1429 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1430 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1431 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1432 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1433 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1434 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1435 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1436 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1437 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1438 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1439 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1440 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1441 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1442 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1443 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1444 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1445 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1446 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1447 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1448 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1449 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1450 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1451 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1452 1453 /* 1454 * Buffer manager control registers 1455 */ 1456 #define BGE_BMAN_MODE 0x4400 1457 #define BGE_BMAN_STATUS 0x4404 1458 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1459 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1460 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1461 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1462 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1463 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1464 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1465 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1466 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1467 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1468 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1469 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1470 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1471 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1472 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1473 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1474 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1475 #define BGE_BMAN_HWDIAG_1 0x444C 1476 #define BGE_BMAN_HWDIAG_2 0x4450 1477 #define BGE_BMAN_HWDIAG_3 0x4454 1478 1479 /* Buffer manager mode register */ 1480 #define BGE_BMANMODE_RESET 0x00000001 1481 #define BGE_BMANMODE_ENABLE 0x00000002 1482 #define BGE_BMANMODE_ATTN 0x00000004 1483 #define BGE_BMANMODE_TESTMODE 0x00000008 1484 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1485 #define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1486 1487 /* Buffer manager status register */ 1488 #define BGE_BMANSTAT_ERRO 0x00000004 1489 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1490 1491 /* 1492 * Read DMA Control registers 1493 */ 1494 #define BGE_RDMA_MODE 0x4800 1495 #define BGE_RDMA_STATUS 0x4804 1496 #define BGE_RDMA_RSRVCTRL 0x4900 1497 #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1498 1499 /* Read DMA mode register */ 1500 #define BGE_RDMAMODE_RESET 0x00000001 1501 #define BGE_RDMAMODE_ENABLE 0x00000002 1502 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1503 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1504 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1505 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1506 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1507 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1508 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1509 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1510 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1511 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1512 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1513 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1514 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1515 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1516 #define BGE_RDMAMODE_JMB_2K_MMRR 0x00800000 1517 #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1518 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1519 #define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1520 #define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1521 1522 /* Read DMA status register */ 1523 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1524 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1525 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1526 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1527 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1528 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1529 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1530 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1531 1532 /* Read DMA Reserved Control register */ 1533 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1534 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1535 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1536 #define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1537 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1538 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1539 #define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1540 1541 /* Read DMA Corruption Enable Control register */ 1542 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1543 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1544 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1545 1546 /* 1547 * Write DMA control registers 1548 */ 1549 #define BGE_WDMA_MODE 0x4C00 1550 #define BGE_WDMA_STATUS 0x4C04 1551 1552 /* Write DMA mode register */ 1553 #define BGE_WDMAMODE_RESET 0x00000001 1554 #define BGE_WDMAMODE_ENABLE 0x00000002 1555 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1556 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1557 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1558 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1559 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1560 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1561 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1562 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1563 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1564 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1565 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1566 1567 /* Write DMA status register */ 1568 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1569 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1570 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1571 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1572 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1573 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1574 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1575 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1576 1577 1578 /* 1579 * RX CPU registers 1580 */ 1581 #define BGE_RXCPU_MODE 0x5000 1582 #define BGE_RXCPU_STATUS 0x5004 1583 #define BGE_RXCPU_PC 0x501C 1584 1585 /* RX CPU mode register */ 1586 #define BGE_RXCPUMODE_RESET 0x00000001 1587 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1588 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1589 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1590 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1591 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1592 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1593 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1594 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1595 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1596 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1597 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1598 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1599 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1600 1601 /* RX CPU status register */ 1602 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1603 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1604 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1605 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1606 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1607 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1608 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1609 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1610 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1611 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1612 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1613 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1614 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1615 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1616 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1617 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1618 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1619 1620 /* 1621 * V? CPU registers 1622 */ 1623 #define BGE_VCPU_STATUS 0x5100 1624 #define BGE_VCPU_EXT_CTRL 0x6890 1625 1626 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1627 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1628 1629 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1630 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1631 1632 /* 1633 * TX CPU registers 1634 */ 1635 #define BGE_TXCPU_MODE 0x5400 1636 #define BGE_TXCPU_STATUS 0x5404 1637 #define BGE_TXCPU_PC 0x541C 1638 1639 /* TX CPU mode register */ 1640 #define BGE_TXCPUMODE_RESET 0x00000001 1641 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1642 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1643 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1644 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1645 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1646 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1647 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1648 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1649 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1650 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1651 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1652 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1653 1654 /* TX CPU status register */ 1655 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1656 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1657 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1658 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1659 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1660 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1661 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1662 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1663 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1664 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1665 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1666 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1667 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1668 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1669 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1670 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1671 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1672 1673 1674 /* 1675 * Low priority mailbox registers 1676 */ 1677 #define BGE_LPMBX_IRQ0_HI 0x5800 1678 #define BGE_LPMBX_IRQ0_LO 0x5804 1679 #define BGE_LPMBX_IRQ1_HI 0x5808 1680 #define BGE_LPMBX_IRQ1_LO 0x580C 1681 #define BGE_LPMBX_IRQ2_HI 0x5810 1682 #define BGE_LPMBX_IRQ2_LO 0x5814 1683 #define BGE_LPMBX_IRQ3_HI 0x5818 1684 #define BGE_LPMBX_IRQ3_LO 0x581C 1685 #define BGE_LPMBX_GEN0_HI 0x5820 1686 #define BGE_LPMBX_GEN0_LO 0x5824 1687 #define BGE_LPMBX_GEN1_HI 0x5828 1688 #define BGE_LPMBX_GEN1_LO 0x582C 1689 #define BGE_LPMBX_GEN2_HI 0x5830 1690 #define BGE_LPMBX_GEN2_LO 0x5834 1691 #define BGE_LPMBX_GEN3_HI 0x5828 1692 #define BGE_LPMBX_GEN3_LO 0x582C 1693 #define BGE_LPMBX_GEN4_HI 0x5840 1694 #define BGE_LPMBX_GEN4_LO 0x5844 1695 #define BGE_LPMBX_GEN5_HI 0x5848 1696 #define BGE_LPMBX_GEN5_LO 0x584C 1697 #define BGE_LPMBX_GEN6_HI 0x5850 1698 #define BGE_LPMBX_GEN6_LO 0x5854 1699 #define BGE_LPMBX_GEN7_HI 0x5858 1700 #define BGE_LPMBX_GEN7_LO 0x585C 1701 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1702 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1703 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1704 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1705 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1706 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1707 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1708 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1709 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1710 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1711 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1712 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1713 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1714 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1715 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1716 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1717 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1718 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1719 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1720 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1721 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1722 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1723 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1724 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1725 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1726 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1727 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1728 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1729 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1730 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1731 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1732 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1733 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1734 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1735 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1736 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1737 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1738 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1739 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1740 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1741 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1742 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1743 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1744 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1745 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1746 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1747 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1748 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1749 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1750 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1751 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1752 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1753 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1754 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1755 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1756 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1757 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1758 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1759 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1760 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1761 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1762 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1763 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1764 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1765 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1766 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1767 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1768 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1769 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1770 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1771 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1772 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1773 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1774 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1775 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1776 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1777 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1778 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1779 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1780 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1781 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1782 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1783 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1784 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1785 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1786 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1787 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1788 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1789 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1790 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1791 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1792 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1793 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1794 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1795 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1796 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1797 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1798 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1799 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1800 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1801 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1802 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1803 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1804 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1805 1806 /* 1807 * Flow throw Queue reset register 1808 */ 1809 #define BGE_FTQ_RESET 0x5C00 1810 1811 #define BGE_FTQRESET_DMAREAD 0x00000002 1812 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1813 #define BGE_FTQRESET_DMADONE 0x00000010 1814 #define BGE_FTQRESET_SBDC 0x00000020 1815 #define BGE_FTQRESET_SDI 0x00000040 1816 #define BGE_FTQRESET_WDMA 0x00000080 1817 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1818 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1819 #define BGE_FTQRESET_SDC 0x00000400 1820 #define BGE_FTQRESET_HCC 0x00000800 1821 #define BGE_FTQRESET_TXFIFO 0x00001000 1822 #define BGE_FTQRESET_MBC 0x00002000 1823 #define BGE_FTQRESET_RBDC 0x00004000 1824 #define BGE_FTQRESET_RXLP 0x00008000 1825 #define BGE_FTQRESET_RDBDI 0x00010000 1826 #define BGE_FTQRESET_RDC 0x00020000 1827 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1828 1829 /* 1830 * Message Signaled Interrupt registers 1831 */ 1832 #define BGE_MSI_MODE 0x6000 1833 #define BGE_MSI_STATUS 0x6004 1834 #define BGE_MSI_FIFOACCESS 0x6008 1835 1836 /* MSI mode register */ 1837 #define BGE_MSIMODE_RESET 0x00000001 1838 #define BGE_MSIMODE_ENABLE 0x00000002 1839 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1840 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1841 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1842 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1843 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1844 1845 /* MSI status register */ 1846 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1847 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1848 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1849 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1850 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1851 1852 1853 /* 1854 * DMA Completion registers 1855 */ 1856 #define BGE_DMAC_MODE 0x6400 1857 1858 /* DMA Completion mode register */ 1859 #define BGE_DMACMODE_RESET 0x00000001 1860 #define BGE_DMACMODE_ENABLE 0x00000002 1861 1862 1863 /* 1864 * General control registers. 1865 */ 1866 #define BGE_MODE_CTL 0x6800 1867 #define BGE_MISC_CFG 0x6804 1868 #define BGE_MISC_LOCAL_CTL 0x6808 1869 #define BGE_RX_CPU_EVENT 0x6810 1870 #define BGE_TX_CPU_EVENT 0x6820 1871 #define BGE_EE_ADDR 0x6838 1872 #define BGE_EE_DATA 0x683C 1873 #define BGE_EE_CTL 0x6840 1874 #define BGE_MDI_CTL 0x6844 1875 #define BGE_EE_DELAY 0x6848 1876 #define BGE_FASTBOOT_PC 0x6894 1877 1878 #define BGE_RX_CPU_DRV_EVENT 0x00004000 1879 1880 /* 1881 * NVRAM Control registers 1882 */ 1883 #define BGE_NVRAM_CMD 0x7000 1884 #define BGE_NVRAM_STAT 0x7004 1885 #define BGE_NVRAM_WRDATA 0x7008 1886 #define BGE_NVRAM_ADDR 0x700c 1887 #define BGE_NVRAM_RDDATA 0x7010 1888 #define BGE_NVRAM_CFG1 0x7014 1889 #define BGE_NVRAM_CFG2 0x7018 1890 #define BGE_NVRAM_CFG3 0x701c 1891 #define BGE_NVRAM_SWARB 0x7020 1892 #define BGE_NVRAM_ACCESS 0x7024 1893 #define BGE_NVRAM_WRITE1 0x7028 1894 1895 #define BGE_NVRAMCMD_RESET 0x00000001 1896 #define BGE_NVRAMCMD_DONE 0x00000008 1897 #define BGE_NVRAMCMD_START 0x00000010 1898 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1899 #define BGE_NVRAMCMD_ERASE 0x00000040 1900 #define BGE_NVRAMCMD_FIRST 0x00000080 1901 #define BGE_NVRAMCMD_LAST 0x00000100 1902 1903 #define BGE_NVRAM_READCMD \ 1904 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1905 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1906 #define BGE_NVRAM_WRITECMD \ 1907 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1908 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1909 1910 #define BGE_NVRAMSWARB_SET0 0x00000001 1911 #define BGE_NVRAMSWARB_SET1 0x00000002 1912 #define BGE_NVRAMSWARB_SET2 0x00000003 1913 #define BGE_NVRAMSWARB_SET3 0x00000004 1914 #define BGE_NVRAMSWARB_CLR0 0x00000010 1915 #define BGE_NVRAMSWARB_CLR1 0x00000020 1916 #define BGE_NVRAMSWARB_CLR2 0x00000040 1917 #define BGE_NVRAMSWARB_CLR3 0x00000080 1918 #define BGE_NVRAMSWARB_GNT0 0x00000100 1919 #define BGE_NVRAMSWARB_GNT1 0x00000200 1920 #define BGE_NVRAMSWARB_GNT2 0x00000400 1921 #define BGE_NVRAMSWARB_GNT3 0x00000800 1922 #define BGE_NVRAMSWARB_REQ0 0x00001000 1923 #define BGE_NVRAMSWARB_REQ1 0x00002000 1924 #define BGE_NVRAMSWARB_REQ2 0x00004000 1925 #define BGE_NVRAMSWARB_REQ3 0x00008000 1926 1927 #define BGE_NVRAMACC_ENABLE 0x00000001 1928 #define BGE_NVRAMACC_WRENABLE 0x00000002 1929 1930 /* 1931 * TLP Control Register 1932 * Applicable to BCM5721 and BCM5751 only 1933 */ 1934 #define BGE_TLP_CONTROL_REG 0x7c00 1935 #define BGE_TLP_FTSMAX 0x000c 1936 #define BGE_TLP_FTSMAX_MSK 0x000000ff 1937 #define BGE_TLP_FTSMAX_VAL 0x0000002c 1938 #define BGE_TLP_PHYCTL1 0x0004 1939 #define BGE_TLP_PHYCTL1_EN_L1PLLPD 0x00001000 1940 #define BGE_TLP_PHYCTL5 0x0014 1941 #define BGE_TLP_PHYCTL5_DIS_L2CLKREQ 0x80000000 1942 #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1943 1944 /* 1945 * PHY Test Control Register 1946 * Applicable to BCM5721 and BCM5751 only 1947 */ 1948 #define BGE_PHY_TEST_CTRL_REG 0x7e2c 1949 #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1950 #define BGE_PHY_PCIE_LTASS_MODE 0x0040 1951 1952 /* Mode control register */ 1953 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1954 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1955 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1956 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1957 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1958 #define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 1959 #define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 1960 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1961 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1962 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1963 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1964 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1965 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1966 #define BGE_MODECTL_B2HRX_ENABLE 0x00008000 1967 #define BGE_MODECTL_STACKUP 0x00010000 1968 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1969 #define BGE_MODECTL_HTX2B_ENABLE 0x00040000 1970 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1971 #define BGE_MODECTL_PCIE_TLPADDR1 0x00400000 1972 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1973 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1974 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1975 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1976 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1977 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1978 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1979 #define BGE_MODECTL_PCIE_TLPADDR0 0x20000000 1980 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1981 #define BGE_MODECTL_PCIE_TLPADDR2 0x80000000 1982 #define BGE_MODECTL_PCIE_TLPADDRMASK (BGE_MODECTL_PCIE_TLPADDR2 | \ 1983 BGE_MODECTL_PCIE_TLPADDR1 | \ 1984 BGE_MODECTL_PCIE_TLPADDR0) 1985 1986 /* Misc. config register */ 1987 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1988 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1989 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1990 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1991 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 1992 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1993 #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1994 #define BGE_MISCCFG_GRC_RESET_DISABLE 0x20000000 1995 1996 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1997 1998 /* Misc. Local Control */ 1999 #define BGE_MLC_INTR_STATE 0x00000001 2000 #define BGE_MLC_INTR_CLR 0x00000002 2001 #define BGE_MLC_INTR_SET 0x00000004 2002 #define BGE_MLC_INTR_ONATTN 0x00000008 2003 #define BGE_MLC_MISCIO_IN0 0x00000100 2004 #define BGE_MLC_MISCIO_IN1 0x00000200 2005 #define BGE_MLC_MISCIO_IN2 0x00000400 2006 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 2007 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 2008 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 2009 #define BGE_MLC_MISCIO_OUT0 0x00004000 2010 #define BGE_MLC_MISCIO_OUT1 0x00008000 2011 #define BGE_MLC_MISCIO_OUT2 0x00010000 2012 #define BGE_MLC_EXTRAM_ENB 0x00020000 2013 #define BGE_MLC_SRAM_SIZE 0x001C0000 2014 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2015 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2016 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2017 #define BGE_MLC_AUTO_EEPROM 0x01000000 2018 2019 #define BGE_SSRAMSIZE_256KB 0x00000000 2020 #define BGE_SSRAMSIZE_512KB 0x00040000 2021 #define BGE_SSRAMSIZE_1MB 0x00080000 2022 #define BGE_SSRAMSIZE_2MB 0x000C0000 2023 #define BGE_SSRAMSIZE_4MB 0x00100000 2024 #define BGE_SSRAMSIZE_8MB 0x00140000 2025 #define BGE_SSRAMSIZE_16M 0x00180000 2026 2027 /* EEPROM address register */ 2028 #define BGE_EEADDR_ADDRESS 0x0000FFFC 2029 #define BGE_EEADDR_HALFCLK 0x01FF0000 2030 #define BGE_EEADDR_START 0x02000000 2031 #define BGE_EEADDR_DEVID 0x1C000000 2032 #define BGE_EEADDR_RESET 0x20000000 2033 #define BGE_EEADDR_DONE 0x40000000 2034 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2035 2036 #define BGE_EEDEVID(x) ((x & 7) << 26) 2037 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2038 #define BGE_HALFCLK_384SCL 0x60 2039 #define BGE_EE_READCMD \ 2040 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2041 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2042 #define BGE_EE_WRCMD \ 2043 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2044 BGE_EEADDR_START|BGE_EEADDR_DONE) 2045 2046 /* EEPROM Control register */ 2047 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2048 #define BGE_EECTL_CLKOUT 0x00000002 2049 #define BGE_EECTL_CLKIN 0x00000004 2050 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2051 #define BGE_EECTL_DATAOUT 0x00000010 2052 #define BGE_EECTL_DATAIN 0x00000020 2053 2054 /* MDI (MII/GMII) access register */ 2055 #define BGE_MDI_DATA 0x00000001 2056 #define BGE_MDI_DIR 0x00000002 2057 #define BGE_MDI_SEL 0x00000004 2058 #define BGE_MDI_CLK 0x00000008 2059 2060 #define BGE_MEMWIN_START 0x00008000 2061 #define BGE_MEMWIN_END 0x0000FFFF 2062 2063 /* BAR2 (APE) Register Definitions */ 2064 2065 #define BGE_APE_GPIO_MSG 0x0008 2066 #define BGE_APE_EVENT 0x000C 2067 #define BGE_APE_LOCK_REQ 0x002C 2068 #define BGE_APE_LOCK_GRANT 0x004C 2069 2070 #define BGE_APE_GPIO_MSG_SHIFT 4 2071 2072 #define BGE_APE_EVENT_1 0x00000001 2073 2074 #define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2075 2076 #define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2077 2078 /* APE Shared Memory block (writable by APE only) */ 2079 #define BGE_APE_SEG_SIG 0x4000 2080 #define BGE_APE_FW_STATUS 0x400C 2081 #define BGE_APE_FW_FEATURES 0x4010 2082 #define BGE_APE_FW_BEHAVIOR 0x4014 2083 #define BGE_APE_FW_VERSION 0x4018 2084 #define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2085 #define BGE_APE_FW_HEARTBEAT 0x4028 2086 #define BGE_APE_FW_ERROR_FLAGS 0x4074 2087 2088 #define BGE_APE_SEG_SIG_MAGIC 0x41504521 2089 2090 #define BGE_APE_FW_STATUS_READY 0x00000100 2091 2092 #define BGE_APE_FW_FEATURE_DASH 0x00000001 2093 #define BGE_APE_FW_FEATURE_NCSI 0x00000002 2094 2095 #define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2096 #define BGE_APE_FW_VERSION_MAJSFT 24 2097 #define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2098 #define BGE_APE_FW_VERSION_MINSFT 16 2099 #define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2100 #define BGE_APE_FW_VERSION_REVSFT 8 2101 #define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2102 2103 /* Host Shared Memory block (writable by host only) */ 2104 #define BGE_APE_HOST_SEG_SIG 0x4200 2105 #define BGE_APE_HOST_SEG_LEN 0x4204 2106 #define BGE_APE_HOST_INIT_COUNT 0x4208 2107 #define BGE_APE_HOST_DRIVER_ID 0x420C 2108 #define BGE_APE_HOST_BEHAVIOR 0x4210 2109 #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2110 #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2111 #define BGE_APE_HOST_DRVR_STATE 0x421C 2112 #define BGE_APE_HOST_WOL_SPEED 0x4224 2113 2114 #define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2115 2116 #define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2117 2118 #define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2119 #define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2120 (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2121 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2122 2123 #define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2124 2125 #define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2126 #define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2127 2128 #define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2129 #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2130 #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2131 #define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2132 2133 #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2134 2135 #define BGE_APE_EVENT_STATUS 0x4300 2136 2137 #define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2138 #define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2139 #define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2140 #define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2141 #define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2142 #define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2143 #define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2144 2145 #define BGE_APE_DEBUG_LOG 0x4E00 2146 #define BGE_APE_DEBUG_LOG_LEN 0x0100 2147 2148 #define BGE_APE_PER_LOCK_REQ 0x8400 2149 #define BGE_APE_PER_LOCK_GRANT 0x8420 2150 2151 #define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2152 #define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2153 #define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2154 #define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2155 2156 #define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2157 #define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2158 #define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2159 #define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2160 2161 /* APE Mutex Resources */ 2162 #define BGE_APE_LOCK_PHY0 0 2163 #define BGE_APE_LOCK_GRC 1 2164 #define BGE_APE_LOCK_PHY1 2 2165 #define BGE_APE_LOCK_PHY2 3 2166 #define BGE_APE_LOCK_MEM 4 2167 #define BGE_APE_LOCK_PHY3 5 2168 #define BGE_APE_LOCK_GPIO 7 2169 2170 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 2171 do { \ 2172 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2173 (0xFFFF0000 & x)); \ 2174 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2175 } while(0) 2176 2177 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 2178 do { \ 2179 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2180 (0xFFFF0000 & x)); \ 2181 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2182 } while(0) 2183 2184 /* 2185 * This magic number is used to prevent PXE restart when we 2186 * issue a software reset. We write this magic number to the 2187 * firmware mailbox at 0xB50 in order to prevent the PXE boot 2188 * code from running. 2189 */ 2190 #define BGE_SRAM_FW_MB_MAGIC 0x4B657654 /* == ~0xB49A89AB */ 2191 2192 typedef struct { 2193 volatile u_int32_t bge_addr_hi; 2194 volatile u_int32_t bge_addr_lo; 2195 } bge_hostaddr; 2196 2197 /* Ring control block structure */ 2198 struct bge_rcb { 2199 bge_hostaddr bge_hostaddr; 2200 volatile u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 2201 volatile u_int32_t bge_nicaddr; 2202 }; 2203 2204 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2205 2206 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2207 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 2208 2209 struct bge_tx_bd { 2210 bge_hostaddr bge_addr; 2211 #if BYTE_ORDER == BIG_ENDIAN 2212 volatile u_int16_t bge_len; 2213 volatile u_int16_t bge_flags; 2214 volatile u_int16_t bge_rsvd; 2215 volatile u_int16_t bge_vlan_tag; 2216 #else 2217 volatile u_int16_t bge_flags; 2218 volatile u_int16_t bge_len; 2219 volatile u_int16_t bge_vlan_tag; 2220 volatile u_int16_t bge_rsvd; 2221 #endif 2222 }; 2223 2224 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2225 #define BGE_TXBDFLAG_IP_CSUM 0x0002 2226 #define BGE_TXBDFLAG_END 0x0004 2227 #define BGE_TXBDFLAG_IP_FRAG 0x0008 2228 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2229 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 2230 #define BGE_TXBDFLAG_COAL_NOW 0x0080 2231 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2232 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2233 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2234 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2235 #define BGE_TXBDFLAG_NO_CRC 0x8000 2236 2237 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 2238 BGE_SEND_RING_1_TO_4 + \ 2239 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2240 2241 struct bge_rx_bd { 2242 bge_hostaddr bge_addr; 2243 #if BYTE_ORDER == BIG_ENDIAN 2244 volatile u_int16_t bge_idx; 2245 volatile u_int16_t bge_len; 2246 volatile u_int16_t bge_type; 2247 volatile u_int16_t bge_flags; 2248 volatile u_int16_t bge_ip_csum; 2249 volatile u_int16_t bge_tcp_udp_csum; 2250 volatile u_int16_t bge_error_flag; 2251 volatile u_int16_t bge_vlan_tag; 2252 #else 2253 volatile u_int16_t bge_len; 2254 volatile u_int16_t bge_idx; 2255 volatile u_int16_t bge_flags; 2256 volatile u_int16_t bge_type; 2257 volatile u_int16_t bge_tcp_udp_csum; 2258 volatile u_int16_t bge_ip_csum; 2259 volatile u_int16_t bge_vlan_tag; 2260 volatile u_int16_t bge_error_flag; 2261 #endif 2262 volatile u_int32_t bge_rsvd; 2263 volatile u_int32_t bge_opaque; 2264 }; 2265 2266 #define BGE_RXBDFLAG_END 0x0004 2267 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 2268 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 2269 #define BGE_RXBDFLAG_ERROR 0x0400 2270 #define BGE_RXBDFLAG_MINI_RING 0x0800 2271 #define BGE_RXBDFLAG_IP_CSUM 0x1000 2272 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2273 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2274 #define BGE_RXBDFLAG_IPV6 0x8000 2275 2276 #define BGE_RXERRFLAG_BAD_CRC 0x0001 2277 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 2278 #define BGE_RXERRFLAG_LINK_LOST 0x0004 2279 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2280 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 2281 #define BGE_RXERRFLAG_RUNT 0x0020 2282 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2283 #define BGE_RXERRFLAG_GIANT 0x0080 2284 #define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2285 2286 struct bge_sts_idx { 2287 #if BYTE_ORDER == BIG_ENDIAN 2288 volatile u_int16_t bge_tx_cons_idx; 2289 volatile u_int16_t bge_rx_prod_idx; 2290 #else 2291 volatile u_int16_t bge_rx_prod_idx; 2292 volatile u_int16_t bge_tx_cons_idx; 2293 #endif 2294 }; 2295 2296 struct bge_status_block { 2297 volatile u_int32_t bge_status; 2298 volatile u_int32_t bge_rsvd0; 2299 #if BYTE_ORDER == BIG_ENDIAN 2300 volatile u_int16_t bge_rx_std_cons_idx; 2301 volatile u_int16_t bge_rx_jumbo_cons_idx; 2302 volatile u_int16_t bge_rsvd1; 2303 volatile u_int16_t bge_rx_mini_cons_idx; 2304 #else 2305 volatile u_int16_t bge_rx_jumbo_cons_idx; 2306 volatile u_int16_t bge_rx_std_cons_idx; 2307 volatile u_int16_t bge_rx_mini_cons_idx; 2308 volatile u_int16_t bge_rsvd1; 2309 #endif 2310 struct bge_sts_idx bge_idx[16]; 2311 }; 2312 2313 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2314 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2315 2316 #define BGE_STATFLAG_UPDATED 0x00000001 2317 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2318 #define BGE_STATFLAG_ERROR 0x00000004 2319 2320 2321 /* 2322 * Broadcom Vendor ID 2323 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2324 * even though they're now manufactured by Broadcom) 2325 */ 2326 #define BCOM_VENDORID 0x14E4 2327 #define BCOM_DEVICEID_BCM5700 0x1644 2328 #define BCOM_DEVICEID_BCM5701 0x1645 2329 #define BCOM_DEVICEID_BCM5789 0x169d 2330 2331 /* 2332 * Alteon AceNIC PCI vendor/device ID. 2333 */ 2334 #define ALT_VENDORID 0x12AE 2335 #define ALT_DEVICEID_ACENIC 0x0001 2336 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 2337 #define ALT_DEVICEID_BCM5700 0x0003 2338 #define ALT_DEVICEID_BCM5701 0x0004 2339 2340 /* 2341 * 3Com 3c985 PCI vendor/device ID. 2342 */ 2343 #define TC_VENDORID 0x10B7 2344 #define TC_DEVICEID_3C985 0x0001 2345 #define TC_DEVICEID_3C996 0x0003 2346 2347 /* 2348 * SysKonnect PCI vendor ID 2349 */ 2350 #define SK_VENDORID 0x1148 2351 #define SK_DEVICEID_ALTIMA 0x4400 2352 #define SK_SUBSYSID_9D21 0x4421 2353 #define SK_SUBSYSID_9D41 0x4441 2354 2355 /* 2356 * Altima PCI vendor/device ID. 2357 */ 2358 #define ALTIMA_VENDORID 0x173b 2359 #define ALTIMA_DEVICE_AC1000 0x03e8 2360 2361 /* 2362 * Offset of MAC address inside EEPROM. 2363 */ 2364 #define BGE_EE_MAC_OFFSET 0x7C 2365 #define BGE_EE_MAC_OFFSET_5906 0x10 2366 #define BGE_EE_HWCFG_OFFSET 0xC8 2367 2368 #define BGE_HWCFG_VOLTAGE 0x00000003 2369 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2370 #define BGE_HWCFG_MEDIA 0x00000030 2371 #define BGE_HWCFG_ASF 0x00000080 2372 #define BGE_HWCFG_EEPROM_WP 0x00000100 2373 2374 #define BGE_VOLTAGE_1POINT3 0x00000000 2375 #define BGE_VOLTAGE_1POINT8 0x00000001 2376 2377 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2378 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2379 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2380 2381 #define BGE_MEDIA_UNSPEC 0x00000000 2382 #define BGE_MEDIA_COPPER 0x00000010 2383 #define BGE_MEDIA_FIBER 0x00000020 2384 2385 #define BGE_PCI_READ_CMD 0x06000000 2386 #define BGE_PCI_WRITE_CMD 0x70000000 2387 2388 #define BGE_TICKS_PER_SEC 1000000 2389 2390 /* 2391 * Ring size constants. 2392 */ 2393 #define BGE_EVENT_RING_CNT 256 2394 #define BGE_CMD_RING_CNT 64 2395 #define BGE_STD_RX_RING_CNT 512 2396 #define BGE_JUMBO_RX_RING_CNT 256 2397 #define BGE_MINI_RX_RING_CNT 1024 2398 #define BGE_RETURN_RING_CNT 1024 2399 #define BGE_RETURN_RING_CNT_5705 512 2400 2401 /* 2402 * Possible TX ring sizes. 2403 */ 2404 #define BGE_TX_RING_CNT_128 128 2405 #define BGE_TX_RING_BASE_128 0x3800 2406 2407 #define BGE_TX_RING_CNT_256 256 2408 #define BGE_TX_RING_BASE_256 0x3000 2409 2410 #define BGE_TX_RING_CNT_512 512 2411 #define BGE_TX_RING_BASE_512 0x2000 2412 2413 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2414 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2415 2416 /* 2417 * Tigon III statistics counters. 2418 */ 2419 2420 /* Stats counters access through registers */ 2421 struct bge_mac_stats_regs { 2422 u_int32_t ifHCOutOctets; 2423 u_int32_t Reserved0; 2424 u_int32_t etherStatsCollisions; 2425 u_int32_t outXonSent; 2426 u_int32_t outXoffSent; 2427 u_int32_t Reserved1; 2428 u_int32_t dot3StatsInternalMacTransmitErrors; 2429 u_int32_t dot3StatsSingleCollisionFrames; 2430 u_int32_t dot3StatsMultipleCollisionFrames; 2431 u_int32_t dot3StatsDeferredTransmissions; 2432 u_int32_t Reserved2; 2433 u_int32_t dot3StatsExcessiveCollisions; 2434 u_int32_t dot3StatsLateCollisions; 2435 u_int32_t Reserved3[14]; 2436 u_int32_t ifHCOutUcastPkts; 2437 u_int32_t ifHCOutMulticastPkts; 2438 u_int32_t ifHCOutBroadcastPkts; 2439 u_int32_t Reserved4[2]; 2440 u_int32_t ifHCInOctets; 2441 u_int32_t Reserved5; 2442 u_int32_t etherStatsFragments; 2443 u_int32_t ifHCInUcastPkts; 2444 u_int32_t ifHCInMulticastPkts; 2445 u_int32_t ifHCInBroadcastPkts; 2446 u_int32_t dot3StatsFCSErrors; 2447 u_int32_t dot3StatsAlignmentErrors; 2448 u_int32_t xonPauseFramesReceived; 2449 u_int32_t xoffPauseFramesReceived; 2450 u_int32_t macControlFramesReceived; 2451 u_int32_t xoffStateEntered; 2452 u_int32_t dot3StatsFramesTooLong; 2453 u_int32_t etherStatsJabbers; 2454 u_int32_t etherStatsUndersizePkts; 2455 }; 2456 2457 struct bge_stats { 2458 u_int8_t Reserved0[256]; 2459 2460 /* Statistics maintained by Receive MAC. */ 2461 bge_hostaddr ifHCInOctets; 2462 bge_hostaddr Reserved1; 2463 bge_hostaddr etherStatsFragments; 2464 bge_hostaddr ifHCInUcastPkts; 2465 bge_hostaddr ifHCInMulticastPkts; 2466 bge_hostaddr ifHCInBroadcastPkts; 2467 bge_hostaddr dot3StatsFCSErrors; 2468 bge_hostaddr dot3StatsAlignmentErrors; 2469 bge_hostaddr xonPauseFramesReceived; 2470 bge_hostaddr xoffPauseFramesReceived; 2471 bge_hostaddr macControlFramesReceived; 2472 bge_hostaddr xoffStateEntered; 2473 bge_hostaddr dot3StatsFramesTooLong; 2474 bge_hostaddr etherStatsJabbers; 2475 bge_hostaddr etherStatsUndersizePkts; 2476 bge_hostaddr inRangeLengthError; 2477 bge_hostaddr outRangeLengthError; 2478 bge_hostaddr etherStatsPkts64Octets; 2479 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2480 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2481 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2482 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2483 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2484 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2485 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2486 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2487 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2488 2489 bge_hostaddr Unused1[37]; 2490 2491 /* Statistics maintained by Transmit MAC. */ 2492 bge_hostaddr ifHCOutOctets; 2493 bge_hostaddr Reserved2; 2494 bge_hostaddr etherStatsCollisions; 2495 bge_hostaddr outXonSent; 2496 bge_hostaddr outXoffSent; 2497 bge_hostaddr flowControlDone; 2498 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2499 bge_hostaddr dot3StatsSingleCollisionFrames; 2500 bge_hostaddr dot3StatsMultipleCollisionFrames; 2501 bge_hostaddr dot3StatsDeferredTransmissions; 2502 bge_hostaddr Reserved3; 2503 bge_hostaddr dot3StatsExcessiveCollisions; 2504 bge_hostaddr dot3StatsLateCollisions; 2505 bge_hostaddr dot3Collided2Times; 2506 bge_hostaddr dot3Collided3Times; 2507 bge_hostaddr dot3Collided4Times; 2508 bge_hostaddr dot3Collided5Times; 2509 bge_hostaddr dot3Collided6Times; 2510 bge_hostaddr dot3Collided7Times; 2511 bge_hostaddr dot3Collided8Times; 2512 bge_hostaddr dot3Collided9Times; 2513 bge_hostaddr dot3Collided10Times; 2514 bge_hostaddr dot3Collided11Times; 2515 bge_hostaddr dot3Collided12Times; 2516 bge_hostaddr dot3Collided13Times; 2517 bge_hostaddr dot3Collided14Times; 2518 bge_hostaddr dot3Collided15Times; 2519 bge_hostaddr ifHCOutUcastPkts; 2520 bge_hostaddr ifHCOutMulticastPkts; 2521 bge_hostaddr ifHCOutBroadcastPkts; 2522 bge_hostaddr dot3StatsCarrierSenseErrors; 2523 bge_hostaddr ifOutDiscards; 2524 bge_hostaddr ifOutErrors; 2525 2526 bge_hostaddr Unused2[31]; 2527 2528 /* Statistics maintained by Receive List Placement. */ 2529 bge_hostaddr COSIfHCInPkts[16]; 2530 bge_hostaddr COSFramesDroppedDueToFilters; 2531 bge_hostaddr nicDmaWriteQueueFull; 2532 bge_hostaddr nicDmaWriteHighPriQueueFull; 2533 bge_hostaddr nicNoMoreRxBDs; 2534 bge_hostaddr ifInDiscards; 2535 bge_hostaddr ifInErrors; 2536 bge_hostaddr nicRecvThresholdHit; 2537 2538 bge_hostaddr Unused3[9]; 2539 2540 /* Statistics maintained by Send Data Initiator. */ 2541 bge_hostaddr COSIfHCOutPkts[16]; 2542 bge_hostaddr nicDmaReadQueueFull; 2543 bge_hostaddr nicDmaReadHighPriQueueFull; 2544 bge_hostaddr nicSendDataCompQueueFull; 2545 2546 /* Statistics maintained by Host Coalescing. */ 2547 bge_hostaddr nicRingSetSendProdIndex; 2548 bge_hostaddr nicRingStatusUpdate; 2549 bge_hostaddr nicInterrupts; 2550 bge_hostaddr nicAvoidedInterrupts; 2551 bge_hostaddr nicSendThresholdHit; 2552 2553 u_int8_t Reserved4[320]; 2554 }; 2555 2556 /* 2557 * Tigon general information block. This resides in host memory 2558 * and contains the status counters, ring control blocks and 2559 * producer pointers. 2560 */ 2561 2562 struct bge_gib { 2563 struct bge_stats bge_stats; 2564 struct bge_rcb bge_tx_rcb[16]; 2565 struct bge_rcb bge_std_rx_rcb; 2566 struct bge_rcb bge_jumbo_rx_rcb; 2567 struct bge_rcb bge_mini_rx_rcb; 2568 struct bge_rcb bge_return_rcb; 2569 }; 2570 2571 /* 2572 * NOTE! On the Alpha, we have an alignment constraint. 2573 * The first thing in the packet is a 14-byte Ethernet header. 2574 * This means that the packet is misaligned. To compensate, 2575 * we actually offset the data 2 bytes into the cluster. This 2576 * alignes the packet after the Ethernet header at a 32-bit 2577 * boundary. 2578 */ 2579 2580 #define ETHER_ALIGN 2 2581 2582 #define BGE_FRAMELEN ETHER_MAX_LEN 2583 #define BGE_MAX_FRAMELEN 1536 2584 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2585 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2586 #define BGE_PAGE_SIZE PAGE_SIZE 2587 #define BGE_MIN_FRAMELEN 60 2588 2589 /* 2590 * Vital product data and structures. 2591 */ 2592 #define BGE_VPD_FLAG 0x8000 2593 2594 /* VPD structures */ 2595 struct vpd_res { 2596 u_int8_t vr_id; 2597 u_int8_t vr_len; 2598 u_int8_t vr_pad; 2599 }; 2600 2601 struct vpd_key { 2602 char vk_key[2]; 2603 u_int8_t vk_len; 2604 }; 2605 2606 #define VPD_RES_ID 0x82 /* ID string */ 2607 #define VPD_RES_READ 0x90 /* start of read only area */ 2608 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2609 #define VPD_RES_END 0x78 /* end tag */ 2610 2611 /* Flags for bge_flags */ 2612 #define BGEF_FIBER_TBI 0x00000001 2613 #define BGEF_JUMBO_CAPABLE 0x00000002 2614 #define BGEF_FIBER_MII 0x00000004 2615 #define BGEF_CPMU_PRESENT 0x00000008 2616 #define BGEF_APE 0x00000010 2617 /* Reserved for BGEF_MSI 0x00000020 */ 2618 #define BGEF_PCIX 0x00000040 2619 #define BGEF_PCIE 0x00000080 2620 #define BGEF_TSO 0x00000100 2621 #define BGEF_NO_EEPROM 0x00000200 2622 #define BGEF_5700_FAMILY 0x00000800 2623 #define BGEF_5705_PLUS 0x00001000 2624 #define BGEF_575X_PLUS 0x00002000 2625 #define BGEF_5755_PLUS 0x00004000 2626 #define BGEF_IS_5788 0x00008000 2627 #define BGEF_5714_FAMILY 0x00010000 2628 #define BGEF_5717_PLUS 0x00020000 2629 #define BGEF_57765_FAMILY 0x00040000 2630 #define BGEF_57765_PLUS 0x00080000 2631 #define BGEF_40BIT_BUG 0x00100000 2632 #define BGEF_RX_ALIGNBUG 0x00800000 2633 #define BGEF_TXRING_VALID 0x20000000 2634 #define BGEF_RXRING_VALID 0x40000000 2635 #define BGEF_JUMBO_RXRING_VALID 0x80000000 2636 2637 /* PHY related flags in bge_phy_flags. Also used in phyflags in proplib. */ 2638 #define BGEPHYF_NO_3LED 0x00000001 2639 #define BGEPHYF_CRC_BUG 0x00000002 2640 #define BGEPHYF_ADC_BUG 0x00000004 2641 #define BGEPHYF_5704_A0_BUG 0x00000008 2642 #define BGEPHYF_JITTER_BUG 0x00000010 2643 #define BGEPHYF_BER_BUG 0x00000020 2644 #define BGEPHYF_ADJUST_TRIM 0x00000040 2645 #define BGEPHYF_NO_WIRESPEED 0x00000080 2646 #define BGEPHYF_JUMBO_CAPABLE 0x00010000 /* Copied from BGEF_JUMBO_CAPAABLE*/ 2647
Indexes created Mon Sep 29 03:10:08 GMT 2025