if_bnx.c revision 1.19 1 1.19 mhitch /* $NetBSD: if_bnx.c,v 1.19 2008/09/09 17:34:10 mhitch Exp $ */
2 1.4 bouyer /* $OpenBSD: if_bnx.c,v 1.43 2007/01/30 03:21:10 krw Exp $ */
3 1.1 bouyer
4 1.1 bouyer /*-
5 1.1 bouyer * Copyright (c) 2006 Broadcom Corporation
6 1.1 bouyer * David Christensen <davidch (at) broadcom.com>. All rights reserved.
7 1.1 bouyer *
8 1.1 bouyer * Redistribution and use in source and binary forms, with or without
9 1.1 bouyer * modification, are permitted provided that the following conditions
10 1.1 bouyer * are met:
11 1.1 bouyer *
12 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
13 1.1 bouyer * notice, this list of conditions and the following disclaimer.
14 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
16 1.1 bouyer * documentation and/or other materials provided with the distribution.
17 1.1 bouyer * 3. Neither the name of Broadcom Corporation nor the name of its contributors
18 1.1 bouyer * may be used to endorse or promote products derived from this software
19 1.1 bouyer * without specific prior written consent.
20 1.1 bouyer *
21 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
22 1.1 bouyer * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 1.1 bouyer * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 1.1 bouyer * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
25 1.1 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 1.1 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 1.1 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 1.1 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 1.1 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 1.1 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 1.1 bouyer * THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 bouyer */
33 1.1 bouyer
34 1.1 bouyer #include <sys/cdefs.h>
35 1.1 bouyer #if 0
36 1.1 bouyer __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $");
37 1.1 bouyer #endif
38 1.19 mhitch __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.19 2008/09/09 17:34:10 mhitch Exp $");
39 1.1 bouyer
40 1.1 bouyer /*
41 1.1 bouyer * The following controllers are supported by this driver:
42 1.1 bouyer * BCM5706C A2, A3
43 1.1 bouyer * BCM5708C B1
44 1.1 bouyer *
45 1.1 bouyer * The following controllers are not supported by this driver:
46 1.1 bouyer * (These are not "Production" versions of the controller.)
47 1.1 bouyer *
48 1.1 bouyer * BCM5706C A0, A1
49 1.1 bouyer * BCM5706S A0, A1, A2, A3
50 1.1 bouyer * BCM5708C A0, B0
51 1.1 bouyer * BCM5708S A0, B0, B1
52 1.1 bouyer */
53 1.1 bouyer
54 1.1 bouyer #include <sys/callout.h>
55 1.1 bouyer
56 1.1 bouyer #include <dev/pci/if_bnxreg.h>
57 1.1 bouyer #include <dev/microcode/bnx/bnxfw.h>
58 1.1 bouyer
59 1.1 bouyer /****************************************************************************/
60 1.1 bouyer /* BNX Driver Version */
61 1.1 bouyer /****************************************************************************/
62 1.1 bouyer const char bnx_driver_version[] = "v0.9.6";
63 1.1 bouyer
64 1.1 bouyer /****************************************************************************/
65 1.1 bouyer /* BNX Debug Options */
66 1.1 bouyer /****************************************************************************/
67 1.1 bouyer #ifdef BNX_DEBUG
68 1.1 bouyer u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND;
69 1.1 bouyer
70 1.1 bouyer /* 0 = Never */
71 1.1 bouyer /* 1 = 1 in 2,147,483,648 */
72 1.1 bouyer /* 256 = 1 in 8,388,608 */
73 1.1 bouyer /* 2048 = 1 in 1,048,576 */
74 1.1 bouyer /* 65536 = 1 in 32,768 */
75 1.1 bouyer /* 1048576 = 1 in 2,048 */
76 1.1 bouyer /* 268435456 = 1 in 8 */
77 1.1 bouyer /* 536870912 = 1 in 4 */
78 1.1 bouyer /* 1073741824 = 1 in 2 */
79 1.1 bouyer
80 1.1 bouyer /* Controls how often the l2_fhdr frame error check will fail. */
81 1.1 bouyer int bnx_debug_l2fhdr_status_check = 0;
82 1.1 bouyer
83 1.1 bouyer /* Controls how often the unexpected attention check will fail. */
84 1.1 bouyer int bnx_debug_unexpected_attention = 0;
85 1.1 bouyer
86 1.1 bouyer /* Controls how often to simulate an mbuf allocation failure. */
87 1.1 bouyer int bnx_debug_mbuf_allocation_failure = 0;
88 1.1 bouyer
89 1.1 bouyer /* Controls how often to simulate a DMA mapping failure. */
90 1.1 bouyer int bnx_debug_dma_map_addr_failure = 0;
91 1.1 bouyer
92 1.1 bouyer /* Controls how often to simulate a bootcode failure. */
93 1.1 bouyer int bnx_debug_bootcode_running_failure = 0;
94 1.1 bouyer #endif
95 1.1 bouyer
96 1.1 bouyer /****************************************************************************/
97 1.1 bouyer /* PCI Device ID Table */
98 1.1 bouyer /* */
99 1.1 bouyer /* Used by bnx_probe() to identify the devices supported by this driver. */
100 1.1 bouyer /****************************************************************************/
101 1.1 bouyer static const struct bnx_product {
102 1.1 bouyer pci_vendor_id_t bp_vendor;
103 1.1 bouyer pci_product_id_t bp_product;
104 1.1 bouyer pci_vendor_id_t bp_subvendor;
105 1.1 bouyer pci_product_id_t bp_subproduct;
106 1.1 bouyer const char *bp_name;
107 1.1 bouyer } bnx_devices[] = {
108 1.1 bouyer #ifdef PCI_SUBPRODUCT_HP_NC370T
109 1.1 bouyer {
110 1.1 bouyer PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706,
111 1.1 bouyer PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T,
112 1.1 bouyer "HP NC370T Multifunction Gigabit Server Adapter"
113 1.1 bouyer },
114 1.1 bouyer #endif
115 1.1 bouyer #ifdef PCI_SUBPRODUCT_HP_NC370i
116 1.1 bouyer {
117 1.1 bouyer PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706,
118 1.1 bouyer PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i,
119 1.1 bouyer "HP NC370i Multifunction Gigabit Server Adapter"
120 1.1 bouyer },
121 1.1 bouyer #endif
122 1.1 bouyer {
123 1.1 bouyer PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706,
124 1.1 bouyer 0, 0,
125 1.1 bouyer "Broadcom NetXtreme II BCM5706 1000Base-T"
126 1.1 bouyer },
127 1.1 bouyer #ifdef PCI_SUBPRODUCT_HP_NC370F
128 1.1 bouyer {
129 1.1 bouyer PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S,
130 1.1 bouyer PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F,
131 1.1 bouyer "HP NC370F Multifunction Gigabit Server Adapter"
132 1.1 bouyer },
133 1.1 bouyer #endif
134 1.1 bouyer {
135 1.1 bouyer PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S,
136 1.1 bouyer 0, 0,
137 1.1 bouyer "Broadcom NetXtreme II BCM5706 1000Base-SX"
138 1.1 bouyer },
139 1.1 bouyer {
140 1.1 bouyer PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708,
141 1.1 bouyer 0, 0,
142 1.1 bouyer "Broadcom NetXtreme II BCM5708 1000Base-T"
143 1.1 bouyer },
144 1.1 bouyer {
145 1.1 bouyer PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S,
146 1.1 bouyer 0, 0,
147 1.1 bouyer "Broadcom NetXtreme II BCM5708 1000Base-SX"
148 1.1 bouyer },
149 1.1 bouyer };
150 1.1 bouyer
151 1.1 bouyer /****************************************************************************/
152 1.1 bouyer /* Supported Flash NVRAM device data. */
153 1.1 bouyer /****************************************************************************/
154 1.1 bouyer static struct flash_spec flash_table[] =
155 1.1 bouyer {
156 1.1 bouyer /* Slow EEPROM */
157 1.1 bouyer {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
158 1.1 bouyer 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
159 1.1 bouyer SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
160 1.1 bouyer "EEPROM - slow"},
161 1.1 bouyer /* Expansion entry 0001 */
162 1.1 bouyer {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
163 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
164 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
165 1.1 bouyer "Entry 0001"},
166 1.1 bouyer /* Saifun SA25F010 (non-buffered flash) */
167 1.1 bouyer /* strap, cfg1, & write1 need updates */
168 1.1 bouyer {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
169 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
170 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
171 1.1 bouyer "Non-buffered flash (128kB)"},
172 1.1 bouyer /* Saifun SA25F020 (non-buffered flash) */
173 1.1 bouyer /* strap, cfg1, & write1 need updates */
174 1.1 bouyer {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
175 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
176 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
177 1.1 bouyer "Non-buffered flash (256kB)"},
178 1.1 bouyer /* Expansion entry 0100 */
179 1.1 bouyer {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
180 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
181 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
182 1.1 bouyer "Entry 0100"},
183 1.1 bouyer /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
184 1.1 bouyer {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
185 1.1 bouyer 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
186 1.1 bouyer ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
187 1.1 bouyer "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
188 1.1 bouyer /* Entry 0110: ST M45PE20 (non-buffered flash)*/
189 1.1 bouyer {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
190 1.1 bouyer 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
191 1.1 bouyer ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
192 1.1 bouyer "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
193 1.1 bouyer /* Saifun SA25F005 (non-buffered flash) */
194 1.1 bouyer /* strap, cfg1, & write1 need updates */
195 1.1 bouyer {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
196 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
197 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
198 1.1 bouyer "Non-buffered flash (64kB)"},
199 1.1 bouyer /* Fast EEPROM */
200 1.1 bouyer {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
201 1.1 bouyer 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
202 1.1 bouyer SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
203 1.1 bouyer "EEPROM - fast"},
204 1.1 bouyer /* Expansion entry 1001 */
205 1.1 bouyer {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
206 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
207 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
208 1.1 bouyer "Entry 1001"},
209 1.1 bouyer /* Expansion entry 1010 */
210 1.1 bouyer {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
211 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
212 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
213 1.1 bouyer "Entry 1010"},
214 1.1 bouyer /* ATMEL AT45DB011B (buffered flash) */
215 1.1 bouyer {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
216 1.1 bouyer 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
217 1.1 bouyer BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
218 1.1 bouyer "Buffered flash (128kB)"},
219 1.1 bouyer /* Expansion entry 1100 */
220 1.1 bouyer {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
221 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
222 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223 1.1 bouyer "Entry 1100"},
224 1.1 bouyer /* Expansion entry 1101 */
225 1.1 bouyer {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
226 1.1 bouyer 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
227 1.1 bouyer SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
228 1.1 bouyer "Entry 1101"},
229 1.1 bouyer /* Ateml Expansion entry 1110 */
230 1.1 bouyer {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
231 1.1 bouyer 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
232 1.1 bouyer BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
233 1.1 bouyer "Entry 1110 (Atmel)"},
234 1.1 bouyer /* ATMEL AT45DB021B (buffered flash) */
235 1.1 bouyer {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
236 1.1 bouyer 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
237 1.1 bouyer BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
238 1.1 bouyer "Buffered flash (256kB)"},
239 1.1 bouyer };
240 1.1 bouyer
241 1.1 bouyer /****************************************************************************/
242 1.1 bouyer /* OpenBSD device entry points. */
243 1.1 bouyer /****************************************************************************/
244 1.1 bouyer static int bnx_probe(device_t, cfdata_t, void *);
245 1.13 dyoung void bnx_attach(device_t, device_t, void *);
246 1.13 dyoung int bnx_detach(device_t, int);
247 1.1 bouyer
248 1.1 bouyer /****************************************************************************/
249 1.1 bouyer /* BNX Debug Data Structure Dump Routines */
250 1.1 bouyer /****************************************************************************/
251 1.1 bouyer #ifdef BNX_DEBUG
252 1.1 bouyer void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *);
253 1.1 bouyer void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int);
254 1.1 bouyer void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int);
255 1.1 bouyer void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *);
256 1.1 bouyer void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *);
257 1.1 bouyer void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *);
258 1.1 bouyer void bnx_dump_tx_chain(struct bnx_softc *, int, int);
259 1.1 bouyer void bnx_dump_rx_chain(struct bnx_softc *, int, int);
260 1.1 bouyer void bnx_dump_status_block(struct bnx_softc *);
261 1.1 bouyer void bnx_dump_stats_block(struct bnx_softc *);
262 1.1 bouyer void bnx_dump_driver_state(struct bnx_softc *);
263 1.1 bouyer void bnx_dump_hw_state(struct bnx_softc *);
264 1.1 bouyer void bnx_breakpoint(struct bnx_softc *);
265 1.1 bouyer #endif
266 1.1 bouyer
267 1.1 bouyer /****************************************************************************/
268 1.1 bouyer /* BNX Register/Memory Access Routines */
269 1.1 bouyer /****************************************************************************/
270 1.1 bouyer u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t);
271 1.1 bouyer void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t);
272 1.1 bouyer void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t);
273 1.13 dyoung int bnx_miibus_read_reg(device_t, int, int);
274 1.13 dyoung void bnx_miibus_write_reg(device_t, int, int, int);
275 1.13 dyoung void bnx_miibus_statchg(device_t);
276 1.1 bouyer
277 1.1 bouyer /****************************************************************************/
278 1.1 bouyer /* BNX NVRAM Access Routines */
279 1.1 bouyer /****************************************************************************/
280 1.1 bouyer int bnx_acquire_nvram_lock(struct bnx_softc *);
281 1.1 bouyer int bnx_release_nvram_lock(struct bnx_softc *);
282 1.1 bouyer void bnx_enable_nvram_access(struct bnx_softc *);
283 1.1 bouyer void bnx_disable_nvram_access(struct bnx_softc *);
284 1.1 bouyer int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *,
285 1.1 bouyer u_int32_t);
286 1.1 bouyer int bnx_init_nvram(struct bnx_softc *);
287 1.1 bouyer int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int);
288 1.1 bouyer int bnx_nvram_test(struct bnx_softc *);
289 1.1 bouyer #ifdef BNX_NVRAM_WRITE_SUPPORT
290 1.1 bouyer int bnx_enable_nvram_write(struct bnx_softc *);
291 1.1 bouyer void bnx_disable_nvram_write(struct bnx_softc *);
292 1.1 bouyer int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t);
293 1.1 bouyer int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *,
294 1.1 bouyer u_int32_t);
295 1.1 bouyer int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int);
296 1.1 bouyer #endif
297 1.1 bouyer
298 1.1 bouyer /****************************************************************************/
299 1.1 bouyer /* */
300 1.1 bouyer /****************************************************************************/
301 1.1 bouyer int bnx_dma_alloc(struct bnx_softc *);
302 1.1 bouyer void bnx_dma_free(struct bnx_softc *);
303 1.1 bouyer void bnx_release_resources(struct bnx_softc *);
304 1.1 bouyer
305 1.1 bouyer /****************************************************************************/
306 1.1 bouyer /* BNX Firmware Synchronization and Load */
307 1.1 bouyer /****************************************************************************/
308 1.1 bouyer int bnx_fw_sync(struct bnx_softc *, u_int32_t);
309 1.1 bouyer void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t,
310 1.1 bouyer u_int32_t);
311 1.1 bouyer void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *,
312 1.1 bouyer struct fw_info *);
313 1.1 bouyer void bnx_init_cpus(struct bnx_softc *);
314 1.1 bouyer
315 1.14 dyoung void bnx_stop(struct ifnet *, int);
316 1.1 bouyer int bnx_reset(struct bnx_softc *, u_int32_t);
317 1.1 bouyer int bnx_chipinit(struct bnx_softc *);
318 1.1 bouyer int bnx_blockinit(struct bnx_softc *);
319 1.1 bouyer int bnx_get_buf(struct bnx_softc *, struct mbuf *, u_int16_t *,
320 1.1 bouyer u_int16_t *, u_int32_t *);
321 1.1 bouyer
322 1.1 bouyer int bnx_init_tx_chain(struct bnx_softc *);
323 1.1 bouyer int bnx_init_rx_chain(struct bnx_softc *);
324 1.1 bouyer void bnx_free_rx_chain(struct bnx_softc *);
325 1.1 bouyer void bnx_free_tx_chain(struct bnx_softc *);
326 1.1 bouyer
327 1.4 bouyer int bnx_tx_encap(struct bnx_softc *, struct mbuf **);
328 1.1 bouyer void bnx_start(struct ifnet *);
329 1.3 christos int bnx_ioctl(struct ifnet *, u_long, void *);
330 1.1 bouyer void bnx_watchdog(struct ifnet *);
331 1.1 bouyer int bnx_init(struct ifnet *);
332 1.1 bouyer
333 1.1 bouyer void bnx_init_context(struct bnx_softc *);
334 1.1 bouyer void bnx_get_mac_addr(struct bnx_softc *);
335 1.1 bouyer void bnx_set_mac_addr(struct bnx_softc *);
336 1.1 bouyer void bnx_phy_intr(struct bnx_softc *);
337 1.1 bouyer void bnx_rx_intr(struct bnx_softc *);
338 1.1 bouyer void bnx_tx_intr(struct bnx_softc *);
339 1.1 bouyer void bnx_disable_intr(struct bnx_softc *);
340 1.1 bouyer void bnx_enable_intr(struct bnx_softc *);
341 1.1 bouyer
342 1.1 bouyer int bnx_intr(void *);
343 1.1 bouyer void bnx_set_rx_mode(struct bnx_softc *);
344 1.1 bouyer void bnx_stats_update(struct bnx_softc *);
345 1.1 bouyer void bnx_tick(void *);
346 1.1 bouyer
347 1.1 bouyer /****************************************************************************/
348 1.1 bouyer /* OpenBSD device dispatch table. */
349 1.1 bouyer /****************************************************************************/
350 1.13 dyoung CFATTACH_DECL_NEW(bnx, sizeof(struct bnx_softc),
351 1.13 dyoung bnx_probe, bnx_attach, bnx_detach, NULL);
352 1.1 bouyer
353 1.1 bouyer /****************************************************************************/
354 1.1 bouyer /* Device probe function. */
355 1.1 bouyer /* */
356 1.1 bouyer /* Compares the device to the driver's list of supported devices and */
357 1.1 bouyer /* reports back to the OS whether this is the right driver for the device. */
358 1.1 bouyer /* */
359 1.1 bouyer /* Returns: */
360 1.1 bouyer /* BUS_PROBE_DEFAULT on success, positive value on failure. */
361 1.1 bouyer /****************************************************************************/
362 1.1 bouyer static const struct bnx_product *
363 1.1 bouyer bnx_lookup(const struct pci_attach_args *pa)
364 1.1 bouyer {
365 1.1 bouyer int i;
366 1.1 bouyer pcireg_t subid;
367 1.1 bouyer
368 1.13 dyoung for (i = 0; i < __arraycount(bnx_devices); i++) {
369 1.1 bouyer if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor ||
370 1.1 bouyer PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product)
371 1.1 bouyer continue;
372 1.1 bouyer if (!bnx_devices[i].bp_subvendor)
373 1.1 bouyer return &bnx_devices[i];
374 1.1 bouyer subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
375 1.1 bouyer if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor &&
376 1.1 bouyer PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct)
377 1.1 bouyer return &bnx_devices[i];
378 1.1 bouyer }
379 1.1 bouyer
380 1.1 bouyer return NULL;
381 1.1 bouyer }
382 1.1 bouyer static int
383 1.1 bouyer bnx_probe(device_t parent, cfdata_t match, void *aux)
384 1.1 bouyer {
385 1.1 bouyer struct pci_attach_args *pa = (struct pci_attach_args *)aux;
386 1.1 bouyer
387 1.1 bouyer if (bnx_lookup(pa) != NULL)
388 1.1 bouyer return (1);
389 1.1 bouyer
390 1.1 bouyer return (0);
391 1.1 bouyer }
392 1.1 bouyer
393 1.1 bouyer /****************************************************************************/
394 1.1 bouyer /* Device attach function. */
395 1.1 bouyer /* */
396 1.1 bouyer /* Allocates device resources, performs secondary chip identification, */
397 1.1 bouyer /* resets and initializes the hardware, and initializes driver instance */
398 1.1 bouyer /* variables. */
399 1.1 bouyer /* */
400 1.1 bouyer /* Returns: */
401 1.1 bouyer /* 0 on success, positive value on failure. */
402 1.1 bouyer /****************************************************************************/
403 1.1 bouyer void
404 1.13 dyoung bnx_attach(device_t parent, device_t self, void *aux)
405 1.1 bouyer {
406 1.1 bouyer const struct bnx_product *bp;
407 1.13 dyoung struct bnx_softc *sc = device_private(self);
408 1.1 bouyer struct pci_attach_args *pa = aux;
409 1.1 bouyer pci_chipset_tag_t pc = pa->pa_pc;
410 1.1 bouyer pci_intr_handle_t ih;
411 1.1 bouyer const char *intrstr = NULL;
412 1.1 bouyer u_int32_t command;
413 1.1 bouyer struct ifnet *ifp;
414 1.1 bouyer u_int32_t val;
415 1.1 bouyer pcireg_t memtype;
416 1.1 bouyer
417 1.1 bouyer bp = bnx_lookup(pa);
418 1.1 bouyer if (bp == NULL)
419 1.1 bouyer panic("unknown device");
420 1.1 bouyer
421 1.13 dyoung sc->bnx_dev = self;
422 1.13 dyoung
423 1.1 bouyer aprint_naive("\n");
424 1.10 martti aprint_normal(": %s\n", bp->bp_name);
425 1.1 bouyer
426 1.1 bouyer sc->bnx_pa = *pa;
427 1.1 bouyer
428 1.1 bouyer /*
429 1.1 bouyer * Map control/status registers.
430 1.1 bouyer */
431 1.1 bouyer command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
432 1.1 bouyer command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
433 1.1 bouyer pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
434 1.1 bouyer command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
435 1.1 bouyer
436 1.1 bouyer if (!(command & PCI_COMMAND_MEM_ENABLE)) {
437 1.13 dyoung aprint_error_dev(sc->bnx_dev,
438 1.13 dyoung "failed to enable memory mapping!\n");
439 1.1 bouyer return;
440 1.1 bouyer }
441 1.1 bouyer
442 1.1 bouyer memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0);
443 1.1 bouyer switch (memtype) {
444 1.1 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
445 1.1 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
446 1.1 bouyer if (pci_mapreg_map(pa, BNX_PCI_BAR0,
447 1.1 bouyer memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle,
448 1.1 bouyer NULL, &sc->bnx_size) == 0)
449 1.1 bouyer break;
450 1.1 bouyer default:
451 1.13 dyoung aprint_error_dev(sc->bnx_dev, "can't find mem space\n");
452 1.1 bouyer return;
453 1.1 bouyer }
454 1.1 bouyer
455 1.1 bouyer if (pci_intr_map(pa, &ih)) {
456 1.13 dyoung aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n");
457 1.1 bouyer goto bnx_attach_fail;
458 1.1 bouyer }
459 1.1 bouyer
460 1.1 bouyer intrstr = pci_intr_string(pc, ih);
461 1.1 bouyer
462 1.1 bouyer /*
463 1.1 bouyer * Configure byte swap and enable indirect register access.
464 1.1 bouyer * Rely on CPU to do target byte swapping on big endian systems.
465 1.1 bouyer * Access to registers outside of PCI configurtion space are not
466 1.1 bouyer * valid until this is done.
467 1.1 bouyer */
468 1.1 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG,
469 1.1 bouyer BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
470 1.1 bouyer BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
471 1.1 bouyer
472 1.1 bouyer /* Save ASIC revsion info. */
473 1.1 bouyer sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID);
474 1.1 bouyer
475 1.1 bouyer /* Weed out any non-production controller revisions. */
476 1.1 bouyer switch(BNX_CHIP_ID(sc)) {
477 1.1 bouyer case BNX_CHIP_ID_5706_A0:
478 1.1 bouyer case BNX_CHIP_ID_5706_A1:
479 1.1 bouyer case BNX_CHIP_ID_5708_A0:
480 1.1 bouyer case BNX_CHIP_ID_5708_B0:
481 1.13 dyoung aprint_error_dev(sc->bnx_dev,
482 1.13 dyoung "unsupported controller revision (%c%d)!\n",
483 1.1 bouyer ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A',
484 1.1 bouyer PCI_REVISION(pa->pa_class) & 0x0f);
485 1.1 bouyer goto bnx_attach_fail;
486 1.1 bouyer }
487 1.1 bouyer
488 1.1 bouyer if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) {
489 1.13 dyoung aprint_error_dev(sc->bnx_dev,
490 1.13 dyoung "SerDes controllers are not supported!\n");
491 1.1 bouyer goto bnx_attach_fail;
492 1.1 bouyer }
493 1.1 bouyer
494 1.1 bouyer /*
495 1.1 bouyer * Find the base address for shared memory access.
496 1.1 bouyer * Newer versions of bootcode use a signature and offset
497 1.1 bouyer * while older versions use a fixed address.
498 1.1 bouyer */
499 1.1 bouyer val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE);
500 1.1 bouyer if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG)
501 1.1 bouyer sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0);
502 1.1 bouyer else
503 1.1 bouyer sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE;
504 1.1 bouyer
505 1.1 bouyer DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base);
506 1.1 bouyer
507 1.1 bouyer /* Set initial device and PHY flags */
508 1.1 bouyer sc->bnx_flags = 0;
509 1.1 bouyer sc->bnx_phy_flags = 0;
510 1.1 bouyer
511 1.1 bouyer /* Get PCI bus information (speed and type). */
512 1.1 bouyer val = REG_RD(sc, BNX_PCICFG_MISC_STATUS);
513 1.1 bouyer if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) {
514 1.1 bouyer u_int32_t clkreg;
515 1.1 bouyer
516 1.1 bouyer sc->bnx_flags |= BNX_PCIX_FLAG;
517 1.1 bouyer
518 1.1 bouyer clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS);
519 1.1 bouyer
520 1.1 bouyer clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
521 1.1 bouyer switch (clkreg) {
522 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
523 1.1 bouyer sc->bus_speed_mhz = 133;
524 1.1 bouyer break;
525 1.1 bouyer
526 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
527 1.1 bouyer sc->bus_speed_mhz = 100;
528 1.1 bouyer break;
529 1.1 bouyer
530 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
531 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
532 1.1 bouyer sc->bus_speed_mhz = 66;
533 1.1 bouyer break;
534 1.1 bouyer
535 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
536 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
537 1.1 bouyer sc->bus_speed_mhz = 50;
538 1.1 bouyer break;
539 1.1 bouyer
540 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
541 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
542 1.1 bouyer case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
543 1.1 bouyer sc->bus_speed_mhz = 33;
544 1.1 bouyer break;
545 1.1 bouyer }
546 1.1 bouyer } else if (val & BNX_PCICFG_MISC_STATUS_M66EN)
547 1.1 bouyer sc->bus_speed_mhz = 66;
548 1.1 bouyer else
549 1.1 bouyer sc->bus_speed_mhz = 33;
550 1.1 bouyer
551 1.1 bouyer if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET)
552 1.1 bouyer sc->bnx_flags |= BNX_PCI_32BIT_FLAG;
553 1.1 bouyer
554 1.1 bouyer /* Reset the controller. */
555 1.1 bouyer if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET))
556 1.1 bouyer goto bnx_attach_fail;
557 1.1 bouyer
558 1.1 bouyer /* Initialize the controller. */
559 1.1 bouyer if (bnx_chipinit(sc)) {
560 1.13 dyoung aprint_error_dev(sc->bnx_dev,
561 1.13 dyoung "Controller initialization failed!\n");
562 1.1 bouyer goto bnx_attach_fail;
563 1.1 bouyer }
564 1.1 bouyer
565 1.1 bouyer /* Perform NVRAM test. */
566 1.1 bouyer if (bnx_nvram_test(sc)) {
567 1.13 dyoung aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n");
568 1.1 bouyer goto bnx_attach_fail;
569 1.1 bouyer }
570 1.1 bouyer
571 1.1 bouyer /* Fetch the permanent Ethernet MAC address. */
572 1.1 bouyer bnx_get_mac_addr(sc);
573 1.13 dyoung aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n",
574 1.1 bouyer ether_sprintf(sc->eaddr));
575 1.1 bouyer
576 1.1 bouyer /*
577 1.1 bouyer * Trip points control how many BDs
578 1.1 bouyer * should be ready before generating an
579 1.1 bouyer * interrupt while ticks control how long
580 1.1 bouyer * a BD can sit in the chain before
581 1.1 bouyer * generating an interrupt. Set the default
582 1.1 bouyer * values for the RX and TX rings.
583 1.1 bouyer */
584 1.1 bouyer
585 1.1 bouyer #ifdef BNX_DEBUG
586 1.1 bouyer /* Force more frequent interrupts. */
587 1.1 bouyer sc->bnx_tx_quick_cons_trip_int = 1;
588 1.1 bouyer sc->bnx_tx_quick_cons_trip = 1;
589 1.1 bouyer sc->bnx_tx_ticks_int = 0;
590 1.1 bouyer sc->bnx_tx_ticks = 0;
591 1.1 bouyer
592 1.1 bouyer sc->bnx_rx_quick_cons_trip_int = 1;
593 1.1 bouyer sc->bnx_rx_quick_cons_trip = 1;
594 1.1 bouyer sc->bnx_rx_ticks_int = 0;
595 1.1 bouyer sc->bnx_rx_ticks = 0;
596 1.1 bouyer #else
597 1.1 bouyer sc->bnx_tx_quick_cons_trip_int = 20;
598 1.1 bouyer sc->bnx_tx_quick_cons_trip = 20;
599 1.1 bouyer sc->bnx_tx_ticks_int = 80;
600 1.1 bouyer sc->bnx_tx_ticks = 80;
601 1.1 bouyer
602 1.1 bouyer sc->bnx_rx_quick_cons_trip_int = 6;
603 1.1 bouyer sc->bnx_rx_quick_cons_trip = 6;
604 1.1 bouyer sc->bnx_rx_ticks_int = 18;
605 1.1 bouyer sc->bnx_rx_ticks = 18;
606 1.1 bouyer #endif
607 1.1 bouyer
608 1.1 bouyer /* Update statistics once every second. */
609 1.1 bouyer sc->bnx_stats_ticks = 1000000 & 0xffff00;
610 1.1 bouyer
611 1.1 bouyer /*
612 1.1 bouyer * The copper based NetXtreme II controllers
613 1.1 bouyer * use an integrated PHY at address 1 while
614 1.1 bouyer * the SerDes controllers use a PHY at
615 1.1 bouyer * address 2.
616 1.1 bouyer */
617 1.1 bouyer sc->bnx_phy_addr = 1;
618 1.1 bouyer
619 1.1 bouyer if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) {
620 1.1 bouyer sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG;
621 1.1 bouyer sc->bnx_flags |= BNX_NO_WOL_FLAG;
622 1.1 bouyer if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) {
623 1.1 bouyer sc->bnx_phy_addr = 2;
624 1.1 bouyer val = REG_RD_IND(sc, sc->bnx_shmem_base +
625 1.1 bouyer BNX_SHARED_HW_CFG_CONFIG);
626 1.1 bouyer if (val & BNX_SHARED_HW_CFG_PHY_2_5G)
627 1.1 bouyer sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG;
628 1.1 bouyer }
629 1.1 bouyer }
630 1.1 bouyer
631 1.1 bouyer if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) {
632 1.13 dyoung aprint_error_dev(sc->bnx_dev,
633 1.13 dyoung "SerDes is not supported by this driver!\n");
634 1.1 bouyer goto bnx_attach_fail;
635 1.1 bouyer }
636 1.1 bouyer
637 1.1 bouyer /* Allocate DMA memory resources. */
638 1.1 bouyer sc->bnx_dmatag = pa->pa_dmat;
639 1.1 bouyer if (bnx_dma_alloc(sc)) {
640 1.13 dyoung aprint_error_dev(sc->bnx_dev,
641 1.13 dyoung "DMA resource allocation failed!\n");
642 1.1 bouyer goto bnx_attach_fail;
643 1.1 bouyer }
644 1.1 bouyer
645 1.1 bouyer /* Initialize the ifnet interface. */
646 1.15 dyoung ifp = &sc->bnx_ec.ec_if;
647 1.1 bouyer ifp->if_softc = sc;
648 1.1 bouyer ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
649 1.1 bouyer ifp->if_ioctl = bnx_ioctl;
650 1.14 dyoung ifp->if_stop = bnx_stop;
651 1.1 bouyer ifp->if_start = bnx_start;
652 1.1 bouyer ifp->if_init = bnx_init;
653 1.1 bouyer ifp->if_timer = 0;
654 1.1 bouyer ifp->if_watchdog = bnx_watchdog;
655 1.1 bouyer if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG)
656 1.1 bouyer ifp->if_baudrate = IF_Gbps(2.5);
657 1.1 bouyer else
658 1.1 bouyer ifp->if_baudrate = IF_Gbps(1);
659 1.4 bouyer IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1);
660 1.1 bouyer IFQ_SET_READY(&ifp->if_snd);
661 1.13 dyoung memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
662 1.1 bouyer
663 1.15 dyoung sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU |
664 1.1 bouyer ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
665 1.1 bouyer
666 1.1 bouyer ifp->if_capabilities |=
667 1.1 bouyer IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
668 1.1 bouyer IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
669 1.1 bouyer IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
670 1.1 bouyer
671 1.1 bouyer /* Hookup IRQ last. */
672 1.1 bouyer sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc);
673 1.1 bouyer if (sc->bnx_intrhand == NULL) {
674 1.13 dyoung aprint_error_dev(self, "couldn't establish interrupt");
675 1.1 bouyer if (intrstr != NULL)
676 1.1 bouyer aprint_error(" at %s", intrstr);
677 1.1 bouyer aprint_error("\n");
678 1.1 bouyer goto bnx_attach_fail;
679 1.1 bouyer }
680 1.1 bouyer
681 1.1 bouyer sc->bnx_mii.mii_ifp = ifp;
682 1.1 bouyer sc->bnx_mii.mii_readreg = bnx_miibus_read_reg;
683 1.1 bouyer sc->bnx_mii.mii_writereg = bnx_miibus_write_reg;
684 1.1 bouyer sc->bnx_mii.mii_statchg = bnx_miibus_statchg;
685 1.1 bouyer
686 1.16 dyoung sc->bnx_ec.ec_mii = &sc->bnx_mii;
687 1.16 dyoung ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange,
688 1.16 dyoung ether_mediastatus);
689 1.13 dyoung mii_attach(self, &sc->bnx_mii, 0xffffffff,
690 1.18 dyoung MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG);
691 1.1 bouyer
692 1.14 dyoung if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) {
693 1.13 dyoung aprint_error_dev(self, "no PHY found!\n");
694 1.1 bouyer ifmedia_add(&sc->bnx_mii.mii_media,
695 1.1 bouyer IFM_ETHER|IFM_MANUAL, 0, NULL);
696 1.1 bouyer ifmedia_set(&sc->bnx_mii.mii_media,
697 1.1 bouyer IFM_ETHER|IFM_MANUAL);
698 1.1 bouyer } else {
699 1.1 bouyer ifmedia_set(&sc->bnx_mii.mii_media,
700 1.1 bouyer IFM_ETHER|IFM_AUTO);
701 1.1 bouyer }
702 1.1 bouyer
703 1.1 bouyer /* Attach to the Ethernet interface list. */
704 1.1 bouyer if_attach(ifp);
705 1.1 bouyer ether_ifattach(ifp,sc->eaddr);
706 1.1 bouyer
707 1.7 ad callout_init(&sc->bnx_timeout, 0);
708 1.1 bouyer
709 1.14 dyoung if (!pmf_device_register(self, NULL, NULL))
710 1.13 dyoung aprint_error_dev(self, "couldn't establish power handler\n");
711 1.13 dyoung else
712 1.13 dyoung pmf_class_network_register(self, ifp);
713 1.13 dyoung
714 1.1 bouyer /* Print some important debugging info. */
715 1.1 bouyer DBRUN(BNX_INFO, bnx_dump_driver_state(sc));
716 1.1 bouyer
717 1.1 bouyer goto bnx_attach_exit;
718 1.1 bouyer
719 1.1 bouyer bnx_attach_fail:
720 1.1 bouyer bnx_release_resources(sc);
721 1.1 bouyer
722 1.1 bouyer bnx_attach_exit:
723 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
724 1.1 bouyer }
725 1.1 bouyer
726 1.1 bouyer /****************************************************************************/
727 1.1 bouyer /* Device detach function. */
728 1.1 bouyer /* */
729 1.1 bouyer /* Stops the controller, resets the controller, and releases resources. */
730 1.1 bouyer /* */
731 1.1 bouyer /* Returns: */
732 1.1 bouyer /* 0 on success, positive value on failure. */
733 1.1 bouyer /****************************************************************************/
734 1.13 dyoung int
735 1.13 dyoung bnx_detach(device_t dev, int flags)
736 1.1 bouyer {
737 1.14 dyoung int s;
738 1.1 bouyer struct bnx_softc *sc;
739 1.13 dyoung struct ifnet *ifp;
740 1.1 bouyer
741 1.13 dyoung sc = device_private(dev);
742 1.15 dyoung ifp = &sc->bnx_ec.ec_if;
743 1.1 bouyer
744 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
745 1.1 bouyer
746 1.1 bouyer /* Stop and reset the controller. */
747 1.14 dyoung s = splnet();
748 1.14 dyoung if (ifp->if_flags & IFF_RUNNING)
749 1.14 dyoung bnx_stop(ifp, 1);
750 1.14 dyoung splx(s);
751 1.1 bouyer
752 1.13 dyoung pmf_device_deregister(dev);
753 1.1 bouyer ether_ifdetach(ifp);
754 1.13 dyoung if_detach(ifp);
755 1.13 dyoung mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY);
756 1.1 bouyer
757 1.1 bouyer /* Release all remaining resources. */
758 1.1 bouyer bnx_release_resources(sc);
759 1.1 bouyer
760 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
761 1.1 bouyer
762 1.1 bouyer return(0);
763 1.1 bouyer }
764 1.1 bouyer
765 1.1 bouyer /****************************************************************************/
766 1.1 bouyer /* Indirect register read. */
767 1.1 bouyer /* */
768 1.1 bouyer /* Reads NetXtreme II registers using an index/data register pair in PCI */
769 1.1 bouyer /* configuration space. Using this mechanism avoids issues with posted */
770 1.1 bouyer /* reads but is much slower than memory-mapped I/O. */
771 1.1 bouyer /* */
772 1.1 bouyer /* Returns: */
773 1.1 bouyer /* The value of the register. */
774 1.1 bouyer /****************************************************************************/
775 1.1 bouyer u_int32_t
776 1.1 bouyer bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset)
777 1.1 bouyer {
778 1.1 bouyer struct pci_attach_args *pa = &(sc->bnx_pa);
779 1.1 bouyer
780 1.1 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS,
781 1.1 bouyer offset);
782 1.1 bouyer #ifdef BNX_DEBUG
783 1.1 bouyer {
784 1.1 bouyer u_int32_t val;
785 1.1 bouyer val = pci_conf_read(pa->pa_pc, pa->pa_tag,
786 1.1 bouyer BNX_PCICFG_REG_WINDOW);
787 1.1 bouyer DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, "
788 1.12 perry "val = 0x%08X\n", __func__, offset, val);
789 1.1 bouyer return (val);
790 1.1 bouyer }
791 1.1 bouyer #else
792 1.1 bouyer return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW);
793 1.1 bouyer #endif
794 1.1 bouyer }
795 1.1 bouyer
796 1.1 bouyer /****************************************************************************/
797 1.1 bouyer /* Indirect register write. */
798 1.1 bouyer /* */
799 1.1 bouyer /* Writes NetXtreme II registers using an index/data register pair in PCI */
800 1.1 bouyer /* configuration space. Using this mechanism avoids issues with posted */
801 1.1 bouyer /* writes but is muchh slower than memory-mapped I/O. */
802 1.1 bouyer /* */
803 1.1 bouyer /* Returns: */
804 1.1 bouyer /* Nothing. */
805 1.1 bouyer /****************************************************************************/
806 1.1 bouyer void
807 1.1 bouyer bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val)
808 1.1 bouyer {
809 1.1 bouyer struct pci_attach_args *pa = &(sc->bnx_pa);
810 1.1 bouyer
811 1.1 bouyer DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
812 1.12 perry __func__, offset, val);
813 1.1 bouyer
814 1.1 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS,
815 1.1 bouyer offset);
816 1.1 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val);
817 1.1 bouyer }
818 1.1 bouyer
819 1.1 bouyer /****************************************************************************/
820 1.1 bouyer /* Context memory write. */
821 1.1 bouyer /* */
822 1.1 bouyer /* The NetXtreme II controller uses context memory to track connection */
823 1.1 bouyer /* information for L2 and higher network protocols. */
824 1.1 bouyer /* */
825 1.1 bouyer /* Returns: */
826 1.1 bouyer /* Nothing. */
827 1.1 bouyer /****************************************************************************/
828 1.1 bouyer void
829 1.1 bouyer bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset,
830 1.1 bouyer u_int32_t val)
831 1.1 bouyer {
832 1.1 bouyer
833 1.1 bouyer DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
834 1.12 perry "val = 0x%08X\n", __func__, cid_addr, offset, val);
835 1.1 bouyer
836 1.1 bouyer offset += cid_addr;
837 1.1 bouyer REG_WR(sc, BNX_CTX_DATA_ADR, offset);
838 1.1 bouyer REG_WR(sc, BNX_CTX_DATA, val);
839 1.1 bouyer }
840 1.1 bouyer
841 1.1 bouyer /****************************************************************************/
842 1.1 bouyer /* PHY register read. */
843 1.1 bouyer /* */
844 1.1 bouyer /* Implements register reads on the MII bus. */
845 1.1 bouyer /* */
846 1.1 bouyer /* Returns: */
847 1.1 bouyer /* The value of the register. */
848 1.1 bouyer /****************************************************************************/
849 1.1 bouyer int
850 1.13 dyoung bnx_miibus_read_reg(device_t dev, int phy, int reg)
851 1.1 bouyer {
852 1.13 dyoung struct bnx_softc *sc = device_private(dev);
853 1.1 bouyer u_int32_t val;
854 1.1 bouyer int i;
855 1.1 bouyer
856 1.1 bouyer /* Make sure we are accessing the correct PHY address. */
857 1.1 bouyer if (phy != sc->bnx_phy_addr) {
858 1.1 bouyer DBPRINT(sc, BNX_VERBOSE,
859 1.1 bouyer "Invalid PHY address %d for PHY read!\n", phy);
860 1.1 bouyer return(0);
861 1.1 bouyer }
862 1.1 bouyer
863 1.1 bouyer if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
864 1.1 bouyer val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
865 1.1 bouyer val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
866 1.1 bouyer
867 1.1 bouyer REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
868 1.1 bouyer REG_RD(sc, BNX_EMAC_MDIO_MODE);
869 1.1 bouyer
870 1.1 bouyer DELAY(40);
871 1.1 bouyer }
872 1.1 bouyer
873 1.1 bouyer val = BNX_MIPHY(phy) | BNX_MIREG(reg) |
874 1.1 bouyer BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT |
875 1.1 bouyer BNX_EMAC_MDIO_COMM_START_BUSY;
876 1.1 bouyer REG_WR(sc, BNX_EMAC_MDIO_COMM, val);
877 1.1 bouyer
878 1.1 bouyer for (i = 0; i < BNX_PHY_TIMEOUT; i++) {
879 1.1 bouyer DELAY(10);
880 1.1 bouyer
881 1.1 bouyer val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
882 1.1 bouyer if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) {
883 1.1 bouyer DELAY(5);
884 1.1 bouyer
885 1.1 bouyer val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
886 1.1 bouyer val &= BNX_EMAC_MDIO_COMM_DATA;
887 1.1 bouyer
888 1.1 bouyer break;
889 1.1 bouyer }
890 1.1 bouyer }
891 1.1 bouyer
892 1.1 bouyer if (val & BNX_EMAC_MDIO_COMM_START_BUSY) {
893 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, "
894 1.1 bouyer "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
895 1.1 bouyer val = 0x0;
896 1.1 bouyer } else
897 1.1 bouyer val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
898 1.1 bouyer
899 1.1 bouyer DBPRINT(sc, BNX_EXCESSIVE,
900 1.12 perry "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy,
901 1.1 bouyer (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
902 1.1 bouyer
903 1.1 bouyer if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
904 1.1 bouyer val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
905 1.1 bouyer val |= BNX_EMAC_MDIO_MODE_AUTO_POLL;
906 1.1 bouyer
907 1.1 bouyer REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
908 1.1 bouyer REG_RD(sc, BNX_EMAC_MDIO_MODE);
909 1.1 bouyer
910 1.1 bouyer DELAY(40);
911 1.1 bouyer }
912 1.1 bouyer
913 1.1 bouyer return (val & 0xffff);
914 1.1 bouyer }
915 1.1 bouyer
916 1.1 bouyer /****************************************************************************/
917 1.1 bouyer /* PHY register write. */
918 1.1 bouyer /* */
919 1.1 bouyer /* Implements register writes on the MII bus. */
920 1.1 bouyer /* */
921 1.1 bouyer /* Returns: */
922 1.1 bouyer /* The value of the register. */
923 1.1 bouyer /****************************************************************************/
924 1.1 bouyer void
925 1.13 dyoung bnx_miibus_write_reg(device_t dev, int phy, int reg, int val)
926 1.1 bouyer {
927 1.13 dyoung struct bnx_softc *sc = device_private(dev);
928 1.1 bouyer u_int32_t val1;
929 1.1 bouyer int i;
930 1.1 bouyer
931 1.1 bouyer /* Make sure we are accessing the correct PHY address. */
932 1.1 bouyer if (phy != sc->bnx_phy_addr) {
933 1.1 bouyer DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n",
934 1.1 bouyer phy);
935 1.1 bouyer return;
936 1.1 bouyer }
937 1.1 bouyer
938 1.1 bouyer DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, "
939 1.12 perry "val = 0x%04X\n", __func__,
940 1.1 bouyer phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
941 1.1 bouyer
942 1.1 bouyer if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
943 1.1 bouyer val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
944 1.1 bouyer val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
945 1.1 bouyer
946 1.1 bouyer REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
947 1.1 bouyer REG_RD(sc, BNX_EMAC_MDIO_MODE);
948 1.1 bouyer
949 1.1 bouyer DELAY(40);
950 1.1 bouyer }
951 1.1 bouyer
952 1.1 bouyer val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
953 1.1 bouyer BNX_EMAC_MDIO_COMM_COMMAND_WRITE |
954 1.1 bouyer BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT;
955 1.1 bouyer REG_WR(sc, BNX_EMAC_MDIO_COMM, val1);
956 1.1 bouyer
957 1.1 bouyer for (i = 0; i < BNX_PHY_TIMEOUT; i++) {
958 1.1 bouyer DELAY(10);
959 1.1 bouyer
960 1.1 bouyer val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM);
961 1.1 bouyer if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) {
962 1.1 bouyer DELAY(5);
963 1.1 bouyer break;
964 1.1 bouyer }
965 1.1 bouyer }
966 1.1 bouyer
967 1.1 bouyer if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) {
968 1.1 bouyer BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__,
969 1.1 bouyer __LINE__);
970 1.1 bouyer }
971 1.1 bouyer
972 1.1 bouyer if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) {
973 1.1 bouyer val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
974 1.1 bouyer val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL;
975 1.1 bouyer
976 1.1 bouyer REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
977 1.1 bouyer REG_RD(sc, BNX_EMAC_MDIO_MODE);
978 1.1 bouyer
979 1.1 bouyer DELAY(40);
980 1.1 bouyer }
981 1.1 bouyer }
982 1.1 bouyer
983 1.1 bouyer /****************************************************************************/
984 1.1 bouyer /* MII bus status change. */
985 1.1 bouyer /* */
986 1.1 bouyer /* Called by the MII bus driver when the PHY establishes link to set the */
987 1.1 bouyer /* MAC interface registers. */
988 1.1 bouyer /* */
989 1.1 bouyer /* Returns: */
990 1.1 bouyer /* Nothing. */
991 1.1 bouyer /****************************************************************************/
992 1.1 bouyer void
993 1.13 dyoung bnx_miibus_statchg(device_t dev)
994 1.1 bouyer {
995 1.13 dyoung struct bnx_softc *sc = device_private(dev);
996 1.1 bouyer struct mii_data *mii = &sc->bnx_mii;
997 1.1 bouyer
998 1.1 bouyer BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT);
999 1.1 bouyer
1000 1.1 bouyer /* Set MII or GMII inerface based on the speed negotiated by the PHY. */
1001 1.1 bouyer if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
1002 1.1 bouyer DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n");
1003 1.1 bouyer BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII);
1004 1.1 bouyer } else {
1005 1.1 bouyer DBPRINT(sc, BNX_INFO, "Setting MII interface.\n");
1006 1.1 bouyer BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII);
1007 1.1 bouyer }
1008 1.1 bouyer
1009 1.1 bouyer /* Set half or full duplex based on the duplicity
1010 1.1 bouyer * negotiated by the PHY.
1011 1.1 bouyer */
1012 1.1 bouyer if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1013 1.1 bouyer DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n");
1014 1.1 bouyer BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX);
1015 1.1 bouyer } else {
1016 1.1 bouyer DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n");
1017 1.1 bouyer BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX);
1018 1.1 bouyer }
1019 1.1 bouyer }
1020 1.1 bouyer
1021 1.1 bouyer /****************************************************************************/
1022 1.1 bouyer /* Acquire NVRAM lock. */
1023 1.1 bouyer /* */
1024 1.1 bouyer /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1025 1.1 bouyer /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1026 1.1 bouyer /* for use by the driver. */
1027 1.1 bouyer /* */
1028 1.1 bouyer /* Returns: */
1029 1.1 bouyer /* 0 on success, positive value on failure. */
1030 1.1 bouyer /****************************************************************************/
1031 1.1 bouyer int
1032 1.1 bouyer bnx_acquire_nvram_lock(struct bnx_softc *sc)
1033 1.1 bouyer {
1034 1.1 bouyer u_int32_t val;
1035 1.1 bouyer int j;
1036 1.1 bouyer
1037 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n");
1038 1.1 bouyer
1039 1.1 bouyer /* Request access to the flash interface. */
1040 1.1 bouyer REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2);
1041 1.1 bouyer for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1042 1.1 bouyer val = REG_RD(sc, BNX_NVM_SW_ARB);
1043 1.1 bouyer if (val & BNX_NVM_SW_ARB_ARB_ARB2)
1044 1.1 bouyer break;
1045 1.1 bouyer
1046 1.1 bouyer DELAY(5);
1047 1.1 bouyer }
1048 1.1 bouyer
1049 1.1 bouyer if (j >= NVRAM_TIMEOUT_COUNT) {
1050 1.1 bouyer DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n");
1051 1.1 bouyer return (EBUSY);
1052 1.1 bouyer }
1053 1.1 bouyer
1054 1.1 bouyer return (0);
1055 1.1 bouyer }
1056 1.1 bouyer
1057 1.1 bouyer /****************************************************************************/
1058 1.1 bouyer /* Release NVRAM lock. */
1059 1.1 bouyer /* */
1060 1.1 bouyer /* When the caller is finished accessing NVRAM the lock must be released. */
1061 1.1 bouyer /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1062 1.1 bouyer /* for use by the driver. */
1063 1.1 bouyer /* */
1064 1.1 bouyer /* Returns: */
1065 1.1 bouyer /* 0 on success, positive value on failure. */
1066 1.1 bouyer /****************************************************************************/
1067 1.1 bouyer int
1068 1.1 bouyer bnx_release_nvram_lock(struct bnx_softc *sc)
1069 1.1 bouyer {
1070 1.1 bouyer int j;
1071 1.1 bouyer u_int32_t val;
1072 1.1 bouyer
1073 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n");
1074 1.1 bouyer
1075 1.1 bouyer /* Relinquish nvram interface. */
1076 1.1 bouyer REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2);
1077 1.1 bouyer
1078 1.1 bouyer for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1079 1.1 bouyer val = REG_RD(sc, BNX_NVM_SW_ARB);
1080 1.1 bouyer if (!(val & BNX_NVM_SW_ARB_ARB_ARB2))
1081 1.1 bouyer break;
1082 1.1 bouyer
1083 1.1 bouyer DELAY(5);
1084 1.1 bouyer }
1085 1.1 bouyer
1086 1.1 bouyer if (j >= NVRAM_TIMEOUT_COUNT) {
1087 1.1 bouyer DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n");
1088 1.1 bouyer return (EBUSY);
1089 1.1 bouyer }
1090 1.1 bouyer
1091 1.1 bouyer return (0);
1092 1.1 bouyer }
1093 1.1 bouyer
1094 1.1 bouyer #ifdef BNX_NVRAM_WRITE_SUPPORT
1095 1.1 bouyer /****************************************************************************/
1096 1.1 bouyer /* Enable NVRAM write access. */
1097 1.1 bouyer /* */
1098 1.1 bouyer /* Before writing to NVRAM the caller must enable NVRAM writes. */
1099 1.1 bouyer /* */
1100 1.1 bouyer /* Returns: */
1101 1.1 bouyer /* 0 on success, positive value on failure. */
1102 1.1 bouyer /****************************************************************************/
1103 1.1 bouyer int
1104 1.1 bouyer bnx_enable_nvram_write(struct bnx_softc *sc)
1105 1.1 bouyer {
1106 1.1 bouyer u_int32_t val;
1107 1.1 bouyer
1108 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n");
1109 1.1 bouyer
1110 1.1 bouyer val = REG_RD(sc, BNX_MISC_CFG);
1111 1.1 bouyer REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI);
1112 1.1 bouyer
1113 1.1 bouyer if (!sc->bnx_flash_info->buffered) {
1114 1.1 bouyer int j;
1115 1.1 bouyer
1116 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1117 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND,
1118 1.1 bouyer BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT);
1119 1.1 bouyer
1120 1.1 bouyer for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1121 1.1 bouyer DELAY(5);
1122 1.1 bouyer
1123 1.1 bouyer val = REG_RD(sc, BNX_NVM_COMMAND);
1124 1.1 bouyer if (val & BNX_NVM_COMMAND_DONE)
1125 1.1 bouyer break;
1126 1.1 bouyer }
1127 1.1 bouyer
1128 1.1 bouyer if (j >= NVRAM_TIMEOUT_COUNT) {
1129 1.1 bouyer DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n");
1130 1.1 bouyer return (EBUSY);
1131 1.1 bouyer }
1132 1.1 bouyer }
1133 1.1 bouyer
1134 1.1 bouyer return (0);
1135 1.1 bouyer }
1136 1.1 bouyer
1137 1.1 bouyer /****************************************************************************/
1138 1.1 bouyer /* Disable NVRAM write access. */
1139 1.1 bouyer /* */
1140 1.1 bouyer /* When the caller is finished writing to NVRAM write access must be */
1141 1.1 bouyer /* disabled. */
1142 1.1 bouyer /* */
1143 1.1 bouyer /* Returns: */
1144 1.1 bouyer /* Nothing. */
1145 1.1 bouyer /****************************************************************************/
1146 1.1 bouyer void
1147 1.1 bouyer bnx_disable_nvram_write(struct bnx_softc *sc)
1148 1.1 bouyer {
1149 1.1 bouyer u_int32_t val;
1150 1.1 bouyer
1151 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n");
1152 1.1 bouyer
1153 1.1 bouyer val = REG_RD(sc, BNX_MISC_CFG);
1154 1.1 bouyer REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN);
1155 1.1 bouyer }
1156 1.1 bouyer #endif
1157 1.1 bouyer
1158 1.1 bouyer /****************************************************************************/
1159 1.1 bouyer /* Enable NVRAM access. */
1160 1.1 bouyer /* */
1161 1.1 bouyer /* Before accessing NVRAM for read or write operations the caller must */
1162 1.1 bouyer /* enabled NVRAM access. */
1163 1.1 bouyer /* */
1164 1.1 bouyer /* Returns: */
1165 1.1 bouyer /* Nothing. */
1166 1.1 bouyer /****************************************************************************/
1167 1.1 bouyer void
1168 1.1 bouyer bnx_enable_nvram_access(struct bnx_softc *sc)
1169 1.1 bouyer {
1170 1.1 bouyer u_int32_t val;
1171 1.1 bouyer
1172 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n");
1173 1.1 bouyer
1174 1.1 bouyer val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
1175 1.1 bouyer /* Enable both bits, even on read. */
1176 1.1 bouyer REG_WR(sc, BNX_NVM_ACCESS_ENABLE,
1177 1.1 bouyer val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN);
1178 1.1 bouyer }
1179 1.1 bouyer
1180 1.1 bouyer /****************************************************************************/
1181 1.1 bouyer /* Disable NVRAM access. */
1182 1.1 bouyer /* */
1183 1.1 bouyer /* When the caller is finished accessing NVRAM access must be disabled. */
1184 1.1 bouyer /* */
1185 1.1 bouyer /* Returns: */
1186 1.1 bouyer /* Nothing. */
1187 1.1 bouyer /****************************************************************************/
1188 1.1 bouyer void
1189 1.1 bouyer bnx_disable_nvram_access(struct bnx_softc *sc)
1190 1.1 bouyer {
1191 1.1 bouyer u_int32_t val;
1192 1.1 bouyer
1193 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n");
1194 1.1 bouyer
1195 1.1 bouyer val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
1196 1.1 bouyer
1197 1.1 bouyer /* Disable both bits, even after read. */
1198 1.1 bouyer REG_WR(sc, BNX_NVM_ACCESS_ENABLE,
1199 1.1 bouyer val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN));
1200 1.1 bouyer }
1201 1.1 bouyer
1202 1.1 bouyer #ifdef BNX_NVRAM_WRITE_SUPPORT
1203 1.1 bouyer /****************************************************************************/
1204 1.1 bouyer /* Erase NVRAM page before writing. */
1205 1.1 bouyer /* */
1206 1.1 bouyer /* Non-buffered flash parts require that a page be erased before it is */
1207 1.1 bouyer /* written. */
1208 1.1 bouyer /* */
1209 1.1 bouyer /* Returns: */
1210 1.1 bouyer /* 0 on success, positive value on failure. */
1211 1.1 bouyer /****************************************************************************/
1212 1.1 bouyer int
1213 1.1 bouyer bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset)
1214 1.1 bouyer {
1215 1.1 bouyer u_int32_t cmd;
1216 1.1 bouyer int j;
1217 1.1 bouyer
1218 1.1 bouyer /* Buffered flash doesn't require an erase. */
1219 1.1 bouyer if (sc->bnx_flash_info->buffered)
1220 1.1 bouyer return (0);
1221 1.1 bouyer
1222 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n");
1223 1.1 bouyer
1224 1.1 bouyer /* Build an erase command. */
1225 1.1 bouyer cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR |
1226 1.1 bouyer BNX_NVM_COMMAND_DOIT;
1227 1.1 bouyer
1228 1.1 bouyer /*
1229 1.1 bouyer * Clear the DONE bit separately, set the NVRAM adress to erase,
1230 1.1 bouyer * and issue the erase command.
1231 1.1 bouyer */
1232 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1233 1.1 bouyer REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1234 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND, cmd);
1235 1.1 bouyer
1236 1.1 bouyer /* Wait for completion. */
1237 1.1 bouyer for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1238 1.1 bouyer u_int32_t val;
1239 1.1 bouyer
1240 1.1 bouyer DELAY(5);
1241 1.1 bouyer
1242 1.1 bouyer val = REG_RD(sc, BNX_NVM_COMMAND);
1243 1.1 bouyer if (val & BNX_NVM_COMMAND_DONE)
1244 1.1 bouyer break;
1245 1.1 bouyer }
1246 1.1 bouyer
1247 1.1 bouyer if (j >= NVRAM_TIMEOUT_COUNT) {
1248 1.1 bouyer DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n");
1249 1.1 bouyer return (EBUSY);
1250 1.1 bouyer }
1251 1.1 bouyer
1252 1.1 bouyer return (0);
1253 1.1 bouyer }
1254 1.1 bouyer #endif /* BNX_NVRAM_WRITE_SUPPORT */
1255 1.1 bouyer
1256 1.1 bouyer /****************************************************************************/
1257 1.1 bouyer /* Read a dword (32 bits) from NVRAM. */
1258 1.1 bouyer /* */
1259 1.1 bouyer /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1260 1.1 bouyer /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1261 1.1 bouyer /* */
1262 1.1 bouyer /* Returns: */
1263 1.1 bouyer /* 0 on success and the 32 bit value read, positive value on failure. */
1264 1.1 bouyer /****************************************************************************/
1265 1.1 bouyer int
1266 1.1 bouyer bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset,
1267 1.1 bouyer u_int8_t *ret_val, u_int32_t cmd_flags)
1268 1.1 bouyer {
1269 1.1 bouyer u_int32_t cmd;
1270 1.1 bouyer int i, rc = 0;
1271 1.1 bouyer
1272 1.1 bouyer /* Build the command word. */
1273 1.1 bouyer cmd = BNX_NVM_COMMAND_DOIT | cmd_flags;
1274 1.1 bouyer
1275 1.1 bouyer /* Calculate the offset for buffered flash. */
1276 1.1 bouyer if (sc->bnx_flash_info->buffered)
1277 1.1 bouyer offset = ((offset / sc->bnx_flash_info->page_size) <<
1278 1.1 bouyer sc->bnx_flash_info->page_bits) +
1279 1.1 bouyer (offset % sc->bnx_flash_info->page_size);
1280 1.1 bouyer
1281 1.1 bouyer /*
1282 1.1 bouyer * Clear the DONE bit separately, set the address to read,
1283 1.1 bouyer * and issue the read.
1284 1.1 bouyer */
1285 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1286 1.1 bouyer REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1287 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND, cmd);
1288 1.1 bouyer
1289 1.1 bouyer /* Wait for completion. */
1290 1.1 bouyer for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1291 1.1 bouyer u_int32_t val;
1292 1.1 bouyer
1293 1.1 bouyer DELAY(5);
1294 1.1 bouyer
1295 1.1 bouyer val = REG_RD(sc, BNX_NVM_COMMAND);
1296 1.1 bouyer if (val & BNX_NVM_COMMAND_DONE) {
1297 1.1 bouyer val = REG_RD(sc, BNX_NVM_READ);
1298 1.1 bouyer
1299 1.1 bouyer val = bnx_be32toh(val);
1300 1.1 bouyer memcpy(ret_val, &val, 4);
1301 1.1 bouyer break;
1302 1.1 bouyer }
1303 1.1 bouyer }
1304 1.1 bouyer
1305 1.1 bouyer /* Check for errors. */
1306 1.1 bouyer if (i >= NVRAM_TIMEOUT_COUNT) {
1307 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at "
1308 1.1 bouyer "offset 0x%08X!\n", __FILE__, __LINE__, offset);
1309 1.1 bouyer rc = EBUSY;
1310 1.1 bouyer }
1311 1.1 bouyer
1312 1.1 bouyer return(rc);
1313 1.1 bouyer }
1314 1.1 bouyer
1315 1.1 bouyer #ifdef BNX_NVRAM_WRITE_SUPPORT
1316 1.1 bouyer /****************************************************************************/
1317 1.1 bouyer /* Write a dword (32 bits) to NVRAM. */
1318 1.1 bouyer /* */
1319 1.1 bouyer /* Write a 32 bit word to NVRAM. The caller is assumed to have already */
1320 1.1 bouyer /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */
1321 1.1 bouyer /* enabled NVRAM write access. */
1322 1.1 bouyer /* */
1323 1.1 bouyer /* Returns: */
1324 1.1 bouyer /* 0 on success, positive value on failure. */
1325 1.1 bouyer /****************************************************************************/
1326 1.1 bouyer int
1327 1.1 bouyer bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val,
1328 1.1 bouyer u_int32_t cmd_flags)
1329 1.1 bouyer {
1330 1.1 bouyer u_int32_t cmd, val32;
1331 1.1 bouyer int j;
1332 1.1 bouyer
1333 1.1 bouyer /* Build the command word. */
1334 1.1 bouyer cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags;
1335 1.1 bouyer
1336 1.1 bouyer /* Calculate the offset for buffered flash. */
1337 1.1 bouyer if (sc->bnx_flash_info->buffered)
1338 1.1 bouyer offset = ((offset / sc->bnx_flash_info->page_size) <<
1339 1.1 bouyer sc->bnx_flash_info->page_bits) +
1340 1.1 bouyer (offset % sc->bnx_flash_info->page_size);
1341 1.1 bouyer
1342 1.1 bouyer /*
1343 1.1 bouyer * Clear the DONE bit separately, convert NVRAM data to big-endian,
1344 1.1 bouyer * set the NVRAM address to write, and issue the write command
1345 1.1 bouyer */
1346 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1347 1.1 bouyer memcpy(&val32, val, 4);
1348 1.1 bouyer val32 = htobe32(val32);
1349 1.1 bouyer REG_WR(sc, BNX_NVM_WRITE, val32);
1350 1.1 bouyer REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1351 1.1 bouyer REG_WR(sc, BNX_NVM_COMMAND, cmd);
1352 1.1 bouyer
1353 1.1 bouyer /* Wait for completion. */
1354 1.1 bouyer for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1355 1.1 bouyer DELAY(5);
1356 1.1 bouyer
1357 1.1 bouyer if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE)
1358 1.1 bouyer break;
1359 1.1 bouyer }
1360 1.1 bouyer if (j >= NVRAM_TIMEOUT_COUNT) {
1361 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at "
1362 1.1 bouyer "offset 0x%08X\n", __FILE__, __LINE__, offset);
1363 1.1 bouyer return (EBUSY);
1364 1.1 bouyer }
1365 1.1 bouyer
1366 1.1 bouyer return (0);
1367 1.1 bouyer }
1368 1.1 bouyer #endif /* BNX_NVRAM_WRITE_SUPPORT */
1369 1.1 bouyer
1370 1.1 bouyer /****************************************************************************/
1371 1.1 bouyer /* Initialize NVRAM access. */
1372 1.1 bouyer /* */
1373 1.1 bouyer /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1374 1.1 bouyer /* access that device. */
1375 1.1 bouyer /* */
1376 1.1 bouyer /* Returns: */
1377 1.1 bouyer /* 0 on success, positive value on failure. */
1378 1.1 bouyer /****************************************************************************/
1379 1.1 bouyer int
1380 1.1 bouyer bnx_init_nvram(struct bnx_softc *sc)
1381 1.1 bouyer {
1382 1.1 bouyer u_int32_t val;
1383 1.1 bouyer int j, entry_count, rc;
1384 1.1 bouyer struct flash_spec *flash;
1385 1.1 bouyer
1386 1.12 perry DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
1387 1.1 bouyer
1388 1.1 bouyer /* Determine the selected interface. */
1389 1.1 bouyer val = REG_RD(sc, BNX_NVM_CFG1);
1390 1.1 bouyer
1391 1.1 bouyer entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1392 1.1 bouyer
1393 1.1 bouyer rc = 0;
1394 1.1 bouyer
1395 1.1 bouyer /*
1396 1.1 bouyer * Flash reconfiguration is required to support additional
1397 1.1 bouyer * NVRAM devices not directly supported in hardware.
1398 1.1 bouyer * Check if the flash interface was reconfigured
1399 1.1 bouyer * by the bootcode.
1400 1.1 bouyer */
1401 1.1 bouyer
1402 1.1 bouyer if (val & 0x40000000) {
1403 1.1 bouyer /* Flash interface reconfigured by bootcode. */
1404 1.1 bouyer
1405 1.1 bouyer DBPRINT(sc,BNX_INFO_LOAD,
1406 1.1 bouyer "bnx_init_nvram(): Flash WAS reconfigured.\n");
1407 1.1 bouyer
1408 1.1 bouyer for (j = 0, flash = &flash_table[0]; j < entry_count;
1409 1.1 bouyer j++, flash++) {
1410 1.1 bouyer if ((val & FLASH_BACKUP_STRAP_MASK) ==
1411 1.1 bouyer (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1412 1.1 bouyer sc->bnx_flash_info = flash;
1413 1.1 bouyer break;
1414 1.1 bouyer }
1415 1.1 bouyer }
1416 1.1 bouyer } else {
1417 1.1 bouyer /* Flash interface not yet reconfigured. */
1418 1.1 bouyer u_int32_t mask;
1419 1.1 bouyer
1420 1.1 bouyer DBPRINT(sc,BNX_INFO_LOAD,
1421 1.1 bouyer "bnx_init_nvram(): Flash was NOT reconfigured.\n");
1422 1.1 bouyer
1423 1.1 bouyer if (val & (1 << 23))
1424 1.1 bouyer mask = FLASH_BACKUP_STRAP_MASK;
1425 1.1 bouyer else
1426 1.1 bouyer mask = FLASH_STRAP_MASK;
1427 1.1 bouyer
1428 1.1 bouyer /* Look for the matching NVRAM device configuration data. */
1429 1.1 bouyer for (j = 0, flash = &flash_table[0]; j < entry_count;
1430 1.1 bouyer j++, flash++) {
1431 1.1 bouyer /* Check if the dev matches any of the known devices. */
1432 1.1 bouyer if ((val & mask) == (flash->strapping & mask)) {
1433 1.1 bouyer /* Found a device match. */
1434 1.1 bouyer sc->bnx_flash_info = flash;
1435 1.1 bouyer
1436 1.1 bouyer /* Request access to the flash interface. */
1437 1.1 bouyer if ((rc = bnx_acquire_nvram_lock(sc)) != 0)
1438 1.1 bouyer return (rc);
1439 1.1 bouyer
1440 1.1 bouyer /* Reconfigure the flash interface. */
1441 1.1 bouyer bnx_enable_nvram_access(sc);
1442 1.1 bouyer REG_WR(sc, BNX_NVM_CFG1, flash->config1);
1443 1.1 bouyer REG_WR(sc, BNX_NVM_CFG2, flash->config2);
1444 1.1 bouyer REG_WR(sc, BNX_NVM_CFG3, flash->config3);
1445 1.1 bouyer REG_WR(sc, BNX_NVM_WRITE1, flash->write1);
1446 1.1 bouyer bnx_disable_nvram_access(sc);
1447 1.1 bouyer bnx_release_nvram_lock(sc);
1448 1.1 bouyer
1449 1.1 bouyer break;
1450 1.1 bouyer }
1451 1.1 bouyer }
1452 1.1 bouyer }
1453 1.1 bouyer
1454 1.1 bouyer /* Check if a matching device was found. */
1455 1.1 bouyer if (j == entry_count) {
1456 1.1 bouyer sc->bnx_flash_info = NULL;
1457 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n",
1458 1.1 bouyer __FILE__, __LINE__);
1459 1.1 bouyer rc = ENODEV;
1460 1.1 bouyer }
1461 1.1 bouyer
1462 1.1 bouyer /* Write the flash config data to the shared memory interface. */
1463 1.1 bouyer val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2);
1464 1.1 bouyer val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK;
1465 1.1 bouyer if (val)
1466 1.1 bouyer sc->bnx_flash_size = val;
1467 1.1 bouyer else
1468 1.1 bouyer sc->bnx_flash_size = sc->bnx_flash_info->total_size;
1469 1.1 bouyer
1470 1.1 bouyer DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = "
1471 1.1 bouyer "0x%08X\n", sc->bnx_flash_info->total_size);
1472 1.1 bouyer
1473 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
1474 1.1 bouyer
1475 1.1 bouyer return (rc);
1476 1.1 bouyer }
1477 1.1 bouyer
1478 1.1 bouyer /****************************************************************************/
1479 1.1 bouyer /* Read an arbitrary range of data from NVRAM. */
1480 1.1 bouyer /* */
1481 1.1 bouyer /* Prepares the NVRAM interface for access and reads the requested data */
1482 1.1 bouyer /* into the supplied buffer. */
1483 1.1 bouyer /* */
1484 1.1 bouyer /* Returns: */
1485 1.1 bouyer /* 0 on success and the data read, positive value on failure. */
1486 1.1 bouyer /****************************************************************************/
1487 1.1 bouyer int
1488 1.1 bouyer bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf,
1489 1.1 bouyer int buf_size)
1490 1.1 bouyer {
1491 1.1 bouyer int rc = 0;
1492 1.1 bouyer u_int32_t cmd_flags, offset32, len32, extra;
1493 1.1 bouyer
1494 1.1 bouyer if (buf_size == 0)
1495 1.1 bouyer return (0);
1496 1.1 bouyer
1497 1.1 bouyer /* Request access to the flash interface. */
1498 1.1 bouyer if ((rc = bnx_acquire_nvram_lock(sc)) != 0)
1499 1.1 bouyer return (rc);
1500 1.1 bouyer
1501 1.1 bouyer /* Enable access to flash interface */
1502 1.1 bouyer bnx_enable_nvram_access(sc);
1503 1.1 bouyer
1504 1.1 bouyer len32 = buf_size;
1505 1.1 bouyer offset32 = offset;
1506 1.1 bouyer extra = 0;
1507 1.1 bouyer
1508 1.1 bouyer cmd_flags = 0;
1509 1.1 bouyer
1510 1.1 bouyer if (offset32 & 3) {
1511 1.1 bouyer u_int8_t buf[4];
1512 1.1 bouyer u_int32_t pre_len;
1513 1.1 bouyer
1514 1.1 bouyer offset32 &= ~3;
1515 1.1 bouyer pre_len = 4 - (offset & 3);
1516 1.1 bouyer
1517 1.1 bouyer if (pre_len >= len32) {
1518 1.1 bouyer pre_len = len32;
1519 1.1 bouyer cmd_flags =
1520 1.1 bouyer BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST;
1521 1.1 bouyer } else
1522 1.1 bouyer cmd_flags = BNX_NVM_COMMAND_FIRST;
1523 1.1 bouyer
1524 1.1 bouyer rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags);
1525 1.1 bouyer
1526 1.1 bouyer if (rc)
1527 1.1 bouyer return (rc);
1528 1.1 bouyer
1529 1.1 bouyer memcpy(ret_buf, buf + (offset & 3), pre_len);
1530 1.1 bouyer
1531 1.1 bouyer offset32 += 4;
1532 1.1 bouyer ret_buf += pre_len;
1533 1.1 bouyer len32 -= pre_len;
1534 1.1 bouyer }
1535 1.1 bouyer
1536 1.1 bouyer if (len32 & 3) {
1537 1.1 bouyer extra = 4 - (len32 & 3);
1538 1.1 bouyer len32 = (len32 + 4) & ~3;
1539 1.1 bouyer }
1540 1.1 bouyer
1541 1.1 bouyer if (len32 == 4) {
1542 1.1 bouyer u_int8_t buf[4];
1543 1.1 bouyer
1544 1.1 bouyer if (cmd_flags)
1545 1.1 bouyer cmd_flags = BNX_NVM_COMMAND_LAST;
1546 1.1 bouyer else
1547 1.1 bouyer cmd_flags =
1548 1.1 bouyer BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST;
1549 1.1 bouyer
1550 1.1 bouyer rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags);
1551 1.1 bouyer
1552 1.1 bouyer memcpy(ret_buf, buf, 4 - extra);
1553 1.1 bouyer } else if (len32 > 0) {
1554 1.1 bouyer u_int8_t buf[4];
1555 1.1 bouyer
1556 1.1 bouyer /* Read the first word. */
1557 1.1 bouyer if (cmd_flags)
1558 1.1 bouyer cmd_flags = 0;
1559 1.1 bouyer else
1560 1.1 bouyer cmd_flags = BNX_NVM_COMMAND_FIRST;
1561 1.1 bouyer
1562 1.1 bouyer rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1563 1.1 bouyer
1564 1.1 bouyer /* Advance to the next dword. */
1565 1.1 bouyer offset32 += 4;
1566 1.1 bouyer ret_buf += 4;
1567 1.1 bouyer len32 -= 4;
1568 1.1 bouyer
1569 1.1 bouyer while (len32 > 4 && rc == 0) {
1570 1.1 bouyer rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0);
1571 1.1 bouyer
1572 1.1 bouyer /* Advance to the next dword. */
1573 1.1 bouyer offset32 += 4;
1574 1.1 bouyer ret_buf += 4;
1575 1.1 bouyer len32 -= 4;
1576 1.1 bouyer }
1577 1.1 bouyer
1578 1.1 bouyer if (rc)
1579 1.1 bouyer return (rc);
1580 1.1 bouyer
1581 1.1 bouyer cmd_flags = BNX_NVM_COMMAND_LAST;
1582 1.1 bouyer rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags);
1583 1.1 bouyer
1584 1.1 bouyer memcpy(ret_buf, buf, 4 - extra);
1585 1.1 bouyer }
1586 1.1 bouyer
1587 1.1 bouyer /* Disable access to flash interface and release the lock. */
1588 1.1 bouyer bnx_disable_nvram_access(sc);
1589 1.1 bouyer bnx_release_nvram_lock(sc);
1590 1.1 bouyer
1591 1.1 bouyer return (rc);
1592 1.1 bouyer }
1593 1.1 bouyer
1594 1.1 bouyer #ifdef BNX_NVRAM_WRITE_SUPPORT
1595 1.1 bouyer /****************************************************************************/
1596 1.1 bouyer /* Write an arbitrary range of data from NVRAM. */
1597 1.1 bouyer /* */
1598 1.1 bouyer /* Prepares the NVRAM interface for write access and writes the requested */
1599 1.1 bouyer /* data from the supplied buffer. The caller is responsible for */
1600 1.1 bouyer /* calculating any appropriate CRCs. */
1601 1.1 bouyer /* */
1602 1.1 bouyer /* Returns: */
1603 1.1 bouyer /* 0 on success, positive value on failure. */
1604 1.1 bouyer /****************************************************************************/
1605 1.1 bouyer int
1606 1.1 bouyer bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf,
1607 1.1 bouyer int buf_size)
1608 1.1 bouyer {
1609 1.1 bouyer u_int32_t written, offset32, len32;
1610 1.1 bouyer u_int8_t *buf, start[4], end[4];
1611 1.1 bouyer int rc = 0;
1612 1.1 bouyer int align_start, align_end;
1613 1.1 bouyer
1614 1.1 bouyer buf = data_buf;
1615 1.1 bouyer offset32 = offset;
1616 1.1 bouyer len32 = buf_size;
1617 1.1 bouyer align_start = align_end = 0;
1618 1.1 bouyer
1619 1.1 bouyer if ((align_start = (offset32 & 3))) {
1620 1.1 bouyer offset32 &= ~3;
1621 1.1 bouyer len32 += align_start;
1622 1.1 bouyer if ((rc = bnx_nvram_read(sc, offset32, start, 4)))
1623 1.1 bouyer return (rc);
1624 1.1 bouyer }
1625 1.1 bouyer
1626 1.1 bouyer if (len32 & 3) {
1627 1.1 bouyer if ((len32 > 4) || !align_start) {
1628 1.1 bouyer align_end = 4 - (len32 & 3);
1629 1.1 bouyer len32 += align_end;
1630 1.1 bouyer if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4,
1631 1.1 bouyer end, 4))) {
1632 1.1 bouyer return (rc);
1633 1.1 bouyer }
1634 1.1 bouyer }
1635 1.1 bouyer }
1636 1.1 bouyer
1637 1.1 bouyer if (align_start || align_end) {
1638 1.1 bouyer buf = malloc(len32, M_DEVBUF, M_NOWAIT);
1639 1.1 bouyer if (buf == 0)
1640 1.1 bouyer return (ENOMEM);
1641 1.1 bouyer
1642 1.1 bouyer if (align_start)
1643 1.1 bouyer memcpy(buf, start, 4);
1644 1.1 bouyer
1645 1.1 bouyer if (align_end)
1646 1.1 bouyer memcpy(buf + len32 - 4, end, 4);
1647 1.1 bouyer
1648 1.1 bouyer memcpy(buf + align_start, data_buf, buf_size);
1649 1.1 bouyer }
1650 1.1 bouyer
1651 1.1 bouyer written = 0;
1652 1.1 bouyer while ((written < len32) && (rc == 0)) {
1653 1.1 bouyer u_int32_t page_start, page_end, data_start, data_end;
1654 1.1 bouyer u_int32_t addr, cmd_flags;
1655 1.1 bouyer int i;
1656 1.1 bouyer u_int8_t flash_buffer[264];
1657 1.1 bouyer
1658 1.1 bouyer /* Find the page_start addr */
1659 1.1 bouyer page_start = offset32 + written;
1660 1.1 bouyer page_start -= (page_start % sc->bnx_flash_info->page_size);
1661 1.1 bouyer /* Find the page_end addr */
1662 1.1 bouyer page_end = page_start + sc->bnx_flash_info->page_size;
1663 1.1 bouyer /* Find the data_start addr */
1664 1.1 bouyer data_start = (written == 0) ? offset32 : page_start;
1665 1.1 bouyer /* Find the data_end addr */
1666 1.1 bouyer data_end = (page_end > offset32 + len32) ?
1667 1.1 bouyer (offset32 + len32) : page_end;
1668 1.1 bouyer
1669 1.1 bouyer /* Request access to the flash interface. */
1670 1.1 bouyer if ((rc = bnx_acquire_nvram_lock(sc)) != 0)
1671 1.1 bouyer goto nvram_write_end;
1672 1.1 bouyer
1673 1.1 bouyer /* Enable access to flash interface */
1674 1.1 bouyer bnx_enable_nvram_access(sc);
1675 1.1 bouyer
1676 1.1 bouyer cmd_flags = BNX_NVM_COMMAND_FIRST;
1677 1.1 bouyer if (sc->bnx_flash_info->buffered == 0) {
1678 1.1 bouyer int j;
1679 1.1 bouyer
1680 1.1 bouyer /* Read the whole page into the buffer
1681 1.1 bouyer * (non-buffer flash only) */
1682 1.1 bouyer for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) {
1683 1.1 bouyer if (j == (sc->bnx_flash_info->page_size - 4))
1684 1.1 bouyer cmd_flags |= BNX_NVM_COMMAND_LAST;
1685 1.1 bouyer
1686 1.1 bouyer rc = bnx_nvram_read_dword(sc,
1687 1.1 bouyer page_start + j,
1688 1.1 bouyer &flash_buffer[j],
1689 1.1 bouyer cmd_flags);
1690 1.1 bouyer
1691 1.1 bouyer if (rc)
1692 1.1 bouyer goto nvram_write_end;
1693 1.1 bouyer
1694 1.1 bouyer cmd_flags = 0;
1695 1.1 bouyer }
1696 1.1 bouyer }
1697 1.1 bouyer
1698 1.1 bouyer /* Enable writes to flash interface (unlock write-protect) */
1699 1.1 bouyer if ((rc = bnx_enable_nvram_write(sc)) != 0)
1700 1.1 bouyer goto nvram_write_end;
1701 1.1 bouyer
1702 1.1 bouyer /* Erase the page */
1703 1.1 bouyer if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0)
1704 1.1 bouyer goto nvram_write_end;
1705 1.1 bouyer
1706 1.1 bouyer /* Re-enable the write again for the actual write */
1707 1.1 bouyer bnx_enable_nvram_write(sc);
1708 1.1 bouyer
1709 1.1 bouyer /* Loop to write back the buffer data from page_start to
1710 1.1 bouyer * data_start */
1711 1.1 bouyer i = 0;
1712 1.1 bouyer if (sc->bnx_flash_info->buffered == 0) {
1713 1.1 bouyer for (addr = page_start; addr < data_start;
1714 1.1 bouyer addr += 4, i += 4) {
1715 1.1 bouyer
1716 1.1 bouyer rc = bnx_nvram_write_dword(sc, addr,
1717 1.1 bouyer &flash_buffer[i], cmd_flags);
1718 1.1 bouyer
1719 1.1 bouyer if (rc != 0)
1720 1.1 bouyer goto nvram_write_end;
1721 1.1 bouyer
1722 1.1 bouyer cmd_flags = 0;
1723 1.1 bouyer }
1724 1.1 bouyer }
1725 1.1 bouyer
1726 1.1 bouyer /* Loop to write the new data from data_start to data_end */
1727 1.1 bouyer for (addr = data_start; addr < data_end; addr += 4, i++) {
1728 1.1 bouyer if ((addr == page_end - 4) ||
1729 1.1 bouyer ((sc->bnx_flash_info->buffered) &&
1730 1.1 bouyer (addr == data_end - 4))) {
1731 1.1 bouyer
1732 1.1 bouyer cmd_flags |= BNX_NVM_COMMAND_LAST;
1733 1.1 bouyer }
1734 1.1 bouyer
1735 1.1 bouyer rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags);
1736 1.1 bouyer
1737 1.1 bouyer if (rc != 0)
1738 1.1 bouyer goto nvram_write_end;
1739 1.1 bouyer
1740 1.1 bouyer cmd_flags = 0;
1741 1.1 bouyer buf += 4;
1742 1.1 bouyer }
1743 1.1 bouyer
1744 1.1 bouyer /* Loop to write back the buffer data from data_end
1745 1.1 bouyer * to page_end */
1746 1.1 bouyer if (sc->bnx_flash_info->buffered == 0) {
1747 1.1 bouyer for (addr = data_end; addr < page_end;
1748 1.1 bouyer addr += 4, i += 4) {
1749 1.1 bouyer
1750 1.1 bouyer if (addr == page_end-4)
1751 1.1 bouyer cmd_flags = BNX_NVM_COMMAND_LAST;
1752 1.1 bouyer
1753 1.1 bouyer rc = bnx_nvram_write_dword(sc, addr,
1754 1.1 bouyer &flash_buffer[i], cmd_flags);
1755 1.1 bouyer
1756 1.1 bouyer if (rc != 0)
1757 1.1 bouyer goto nvram_write_end;
1758 1.1 bouyer
1759 1.1 bouyer cmd_flags = 0;
1760 1.1 bouyer }
1761 1.1 bouyer }
1762 1.1 bouyer
1763 1.1 bouyer /* Disable writes to flash interface (lock write-protect) */
1764 1.1 bouyer bnx_disable_nvram_write(sc);
1765 1.1 bouyer
1766 1.1 bouyer /* Disable access to flash interface */
1767 1.1 bouyer bnx_disable_nvram_access(sc);
1768 1.1 bouyer bnx_release_nvram_lock(sc);
1769 1.1 bouyer
1770 1.1 bouyer /* Increment written */
1771 1.1 bouyer written += data_end - data_start;
1772 1.1 bouyer }
1773 1.1 bouyer
1774 1.1 bouyer nvram_write_end:
1775 1.1 bouyer if (align_start || align_end)
1776 1.1 bouyer free(buf, M_DEVBUF);
1777 1.1 bouyer
1778 1.1 bouyer return (rc);
1779 1.1 bouyer }
1780 1.1 bouyer #endif /* BNX_NVRAM_WRITE_SUPPORT */
1781 1.1 bouyer
1782 1.1 bouyer /****************************************************************************/
1783 1.1 bouyer /* Verifies that NVRAM is accessible and contains valid data. */
1784 1.1 bouyer /* */
1785 1.1 bouyer /* Reads the configuration data from NVRAM and verifies that the CRC is */
1786 1.1 bouyer /* correct. */
1787 1.1 bouyer /* */
1788 1.1 bouyer /* Returns: */
1789 1.1 bouyer /* 0 on success, positive value on failure. */
1790 1.1 bouyer /****************************************************************************/
1791 1.1 bouyer int
1792 1.1 bouyer bnx_nvram_test(struct bnx_softc *sc)
1793 1.1 bouyer {
1794 1.1 bouyer u_int32_t buf[BNX_NVRAM_SIZE / 4];
1795 1.1 bouyer u_int8_t *data = (u_int8_t *) buf;
1796 1.1 bouyer int rc = 0;
1797 1.1 bouyer u_int32_t magic, csum;
1798 1.1 bouyer
1799 1.1 bouyer /*
1800 1.1 bouyer * Check that the device NVRAM is valid by reading
1801 1.1 bouyer * the magic value at offset 0.
1802 1.1 bouyer */
1803 1.1 bouyer if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0)
1804 1.1 bouyer goto bnx_nvram_test_done;
1805 1.1 bouyer
1806 1.1 bouyer magic = bnx_be32toh(buf[0]);
1807 1.1 bouyer if (magic != BNX_NVRAM_MAGIC) {
1808 1.1 bouyer rc = ENODEV;
1809 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! "
1810 1.1 bouyer "Expected: 0x%08X, Found: 0x%08X\n",
1811 1.1 bouyer __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic);
1812 1.1 bouyer goto bnx_nvram_test_done;
1813 1.1 bouyer }
1814 1.1 bouyer
1815 1.1 bouyer /*
1816 1.1 bouyer * Verify that the device NVRAM includes valid
1817 1.1 bouyer * configuration data.
1818 1.1 bouyer */
1819 1.1 bouyer if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0)
1820 1.1 bouyer goto bnx_nvram_test_done;
1821 1.1 bouyer
1822 1.1 bouyer csum = ether_crc32_le(data, 0x100);
1823 1.1 bouyer if (csum != BNX_CRC32_RESIDUAL) {
1824 1.1 bouyer rc = ENODEV;
1825 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information "
1826 1.1 bouyer "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
1827 1.1 bouyer __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum);
1828 1.1 bouyer goto bnx_nvram_test_done;
1829 1.1 bouyer }
1830 1.1 bouyer
1831 1.1 bouyer csum = ether_crc32_le(data + 0x100, 0x100);
1832 1.1 bouyer if (csum != BNX_CRC32_RESIDUAL) {
1833 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration "
1834 1.1 bouyer "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1835 1.1 bouyer __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum);
1836 1.1 bouyer rc = ENODEV;
1837 1.1 bouyer }
1838 1.1 bouyer
1839 1.1 bouyer bnx_nvram_test_done:
1840 1.1 bouyer return (rc);
1841 1.1 bouyer }
1842 1.1 bouyer
1843 1.1 bouyer /****************************************************************************/
1844 1.1 bouyer /* Free any DMA memory owned by the driver. */
1845 1.1 bouyer /* */
1846 1.1 bouyer /* Scans through each data structre that requires DMA memory and frees */
1847 1.1 bouyer /* the memory if allocated. */
1848 1.1 bouyer /* */
1849 1.1 bouyer /* Returns: */
1850 1.1 bouyer /* Nothing. */
1851 1.1 bouyer /****************************************************************************/
1852 1.1 bouyer void
1853 1.1 bouyer bnx_dma_free(struct bnx_softc *sc)
1854 1.1 bouyer {
1855 1.1 bouyer int i;
1856 1.1 bouyer
1857 1.12 perry DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
1858 1.1 bouyer
1859 1.1 bouyer /* Destroy the status block. */
1860 1.1 bouyer if (sc->status_block != NULL && sc->status_map != NULL) {
1861 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag, sc->status_map);
1862 1.3 christos bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block,
1863 1.1 bouyer BNX_STATUS_BLK_SZ);
1864 1.1 bouyer bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg,
1865 1.1 bouyer sc->status_rseg);
1866 1.1 bouyer bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map);
1867 1.1 bouyer sc->status_block = NULL;
1868 1.1 bouyer sc->status_map = NULL;
1869 1.1 bouyer }
1870 1.1 bouyer
1871 1.1 bouyer /* Destroy the statistics block. */
1872 1.1 bouyer if (sc->stats_block != NULL && sc->stats_map != NULL) {
1873 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map);
1874 1.3 christos bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block,
1875 1.1 bouyer BNX_STATS_BLK_SZ);
1876 1.1 bouyer bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg,
1877 1.1 bouyer sc->stats_rseg);
1878 1.1 bouyer bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map);
1879 1.1 bouyer sc->stats_block = NULL;
1880 1.1 bouyer sc->stats_map = NULL;
1881 1.1 bouyer }
1882 1.1 bouyer
1883 1.1 bouyer /* Free, unmap and destroy all TX buffer descriptor chain pages. */
1884 1.1 bouyer for (i = 0; i < TX_PAGES; i++ ) {
1885 1.1 bouyer if (sc->tx_bd_chain[i] != NULL &&
1886 1.1 bouyer sc->tx_bd_chain_map[i] != NULL) {
1887 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag,
1888 1.1 bouyer sc->tx_bd_chain_map[i]);
1889 1.1 bouyer bus_dmamem_unmap(sc->bnx_dmatag,
1890 1.3 christos (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ);
1891 1.1 bouyer bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i],
1892 1.1 bouyer sc->tx_bd_chain_rseg[i]);
1893 1.1 bouyer bus_dmamap_destroy(sc->bnx_dmatag,
1894 1.1 bouyer sc->tx_bd_chain_map[i]);
1895 1.1 bouyer sc->tx_bd_chain[i] = NULL;
1896 1.1 bouyer sc->tx_bd_chain_map[i] = NULL;
1897 1.1 bouyer }
1898 1.1 bouyer }
1899 1.1 bouyer
1900 1.1 bouyer /* Unload and destroy the TX mbuf maps. */
1901 1.1 bouyer for (i = 0; i < TOTAL_TX_BD; i++) {
1902 1.1 bouyer if (sc->tx_mbuf_map[i] != NULL) {
1903 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]);
1904 1.1 bouyer bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]);
1905 1.1 bouyer }
1906 1.1 bouyer }
1907 1.1 bouyer
1908 1.1 bouyer /* Free, unmap and destroy all RX buffer descriptor chain pages. */
1909 1.1 bouyer for (i = 0; i < RX_PAGES; i++ ) {
1910 1.1 bouyer if (sc->rx_bd_chain[i] != NULL &&
1911 1.1 bouyer sc->rx_bd_chain_map[i] != NULL) {
1912 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag,
1913 1.1 bouyer sc->rx_bd_chain_map[i]);
1914 1.1 bouyer bus_dmamem_unmap(sc->bnx_dmatag,
1915 1.3 christos (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ);
1916 1.1 bouyer bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i],
1917 1.1 bouyer sc->rx_bd_chain_rseg[i]);
1918 1.1 bouyer
1919 1.1 bouyer bus_dmamap_destroy(sc->bnx_dmatag,
1920 1.1 bouyer sc->rx_bd_chain_map[i]);
1921 1.1 bouyer sc->rx_bd_chain[i] = NULL;
1922 1.1 bouyer sc->rx_bd_chain_map[i] = NULL;
1923 1.1 bouyer }
1924 1.1 bouyer }
1925 1.1 bouyer
1926 1.1 bouyer /* Unload and destroy the RX mbuf maps. */
1927 1.1 bouyer for (i = 0; i < TOTAL_RX_BD; i++) {
1928 1.1 bouyer if (sc->rx_mbuf_map[i] != NULL) {
1929 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]);
1930 1.1 bouyer bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]);
1931 1.1 bouyer }
1932 1.1 bouyer }
1933 1.1 bouyer
1934 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
1935 1.1 bouyer }
1936 1.1 bouyer
1937 1.1 bouyer /****************************************************************************/
1938 1.1 bouyer /* Allocate any DMA memory needed by the driver. */
1939 1.1 bouyer /* */
1940 1.1 bouyer /* Allocates DMA memory needed for the various global structures needed by */
1941 1.1 bouyer /* hardware. */
1942 1.1 bouyer /* */
1943 1.1 bouyer /* Returns: */
1944 1.1 bouyer /* 0 for success, positive value for failure. */
1945 1.1 bouyer /****************************************************************************/
1946 1.1 bouyer int
1947 1.1 bouyer bnx_dma_alloc(struct bnx_softc *sc)
1948 1.1 bouyer {
1949 1.1 bouyer int i, rc = 0;
1950 1.1 bouyer
1951 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
1952 1.1 bouyer
1953 1.1 bouyer /*
1954 1.1 bouyer * Allocate DMA memory for the status block, map the memory into DMA
1955 1.1 bouyer * space, and fetch the physical address of the block.
1956 1.1 bouyer */
1957 1.1 bouyer if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1,
1958 1.1 bouyer BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) {
1959 1.13 dyoung aprint_error_dev(sc->bnx_dev,
1960 1.13 dyoung "Could not create status block DMA map!\n");
1961 1.1 bouyer rc = ENOMEM;
1962 1.1 bouyer goto bnx_dma_alloc_exit;
1963 1.1 bouyer }
1964 1.1 bouyer
1965 1.1 bouyer if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ,
1966 1.1 bouyer BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1,
1967 1.1 bouyer &sc->status_rseg, BUS_DMA_NOWAIT)) {
1968 1.13 dyoung aprint_error_dev(sc->bnx_dev,
1969 1.13 dyoung "Could not allocate status block DMA memory!\n");
1970 1.1 bouyer rc = ENOMEM;
1971 1.1 bouyer goto bnx_dma_alloc_exit;
1972 1.1 bouyer }
1973 1.1 bouyer
1974 1.1 bouyer if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg,
1975 1.3 christos BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) {
1976 1.13 dyoung aprint_error_dev(sc->bnx_dev,
1977 1.13 dyoung "Could not map status block DMA memory!\n");
1978 1.1 bouyer rc = ENOMEM;
1979 1.1 bouyer goto bnx_dma_alloc_exit;
1980 1.1 bouyer }
1981 1.1 bouyer
1982 1.1 bouyer if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map,
1983 1.1 bouyer sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) {
1984 1.13 dyoung aprint_error_dev(sc->bnx_dev,
1985 1.13 dyoung "Could not load status block DMA memory!\n");
1986 1.1 bouyer rc = ENOMEM;
1987 1.1 bouyer goto bnx_dma_alloc_exit;
1988 1.1 bouyer }
1989 1.1 bouyer
1990 1.1 bouyer sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr;
1991 1.1 bouyer bzero(sc->status_block, BNX_STATUS_BLK_SZ);
1992 1.1 bouyer
1993 1.1 bouyer /* DRC - Fix for 64 bit addresses. */
1994 1.1 bouyer DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n",
1995 1.1 bouyer (u_int32_t) sc->status_block_paddr);
1996 1.1 bouyer
1997 1.1 bouyer /*
1998 1.1 bouyer * Allocate DMA memory for the statistics block, map the memory into
1999 1.1 bouyer * DMA space, and fetch the physical address of the block.
2000 1.1 bouyer */
2001 1.1 bouyer if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1,
2002 1.1 bouyer BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) {
2003 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2004 1.13 dyoung "Could not create stats block DMA map!\n");
2005 1.1 bouyer rc = ENOMEM;
2006 1.1 bouyer goto bnx_dma_alloc_exit;
2007 1.1 bouyer }
2008 1.1 bouyer
2009 1.1 bouyer if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ,
2010 1.1 bouyer BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1,
2011 1.1 bouyer &sc->stats_rseg, BUS_DMA_NOWAIT)) {
2012 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2013 1.13 dyoung "Could not allocate stats block DMA memory!\n");
2014 1.1 bouyer rc = ENOMEM;
2015 1.1 bouyer goto bnx_dma_alloc_exit;
2016 1.1 bouyer }
2017 1.1 bouyer
2018 1.1 bouyer if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg,
2019 1.3 christos BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) {
2020 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2021 1.13 dyoung "Could not map stats block DMA memory!\n");
2022 1.1 bouyer rc = ENOMEM;
2023 1.1 bouyer goto bnx_dma_alloc_exit;
2024 1.1 bouyer }
2025 1.1 bouyer
2026 1.1 bouyer if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map,
2027 1.1 bouyer sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) {
2028 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2029 1.13 dyoung "Could not load status block DMA memory!\n");
2030 1.1 bouyer rc = ENOMEM;
2031 1.1 bouyer goto bnx_dma_alloc_exit;
2032 1.1 bouyer }
2033 1.1 bouyer
2034 1.1 bouyer sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr;
2035 1.1 bouyer bzero(sc->stats_block, BNX_STATS_BLK_SZ);
2036 1.1 bouyer
2037 1.1 bouyer /* DRC - Fix for 64 bit address. */
2038 1.1 bouyer DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n",
2039 1.1 bouyer (u_int32_t) sc->stats_block_paddr);
2040 1.1 bouyer
2041 1.1 bouyer /*
2042 1.1 bouyer * Allocate DMA memory for the TX buffer descriptor chain,
2043 1.1 bouyer * and fetch the physical address of the block.
2044 1.1 bouyer */
2045 1.1 bouyer for (i = 0; i < TX_PAGES; i++) {
2046 1.1 bouyer if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1,
2047 1.1 bouyer BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT,
2048 1.1 bouyer &sc->tx_bd_chain_map[i])) {
2049 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2050 1.13 dyoung "Could not create Tx desc %d DMA map!\n", i);
2051 1.1 bouyer rc = ENOMEM;
2052 1.1 bouyer goto bnx_dma_alloc_exit;
2053 1.1 bouyer }
2054 1.1 bouyer
2055 1.1 bouyer if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ,
2056 1.1 bouyer BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1,
2057 1.1 bouyer &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) {
2058 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2059 1.13 dyoung "Could not allocate TX desc %d DMA memory!\n",
2060 1.13 dyoung i);
2061 1.1 bouyer rc = ENOMEM;
2062 1.1 bouyer goto bnx_dma_alloc_exit;
2063 1.1 bouyer }
2064 1.1 bouyer
2065 1.1 bouyer if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i],
2066 1.1 bouyer sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ,
2067 1.3 christos (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) {
2068 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2069 1.13 dyoung "Could not map TX desc %d DMA memory!\n", i);
2070 1.1 bouyer rc = ENOMEM;
2071 1.1 bouyer goto bnx_dma_alloc_exit;
2072 1.1 bouyer }
2073 1.1 bouyer
2074 1.1 bouyer if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i],
2075 1.3 christos (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL,
2076 1.1 bouyer BUS_DMA_NOWAIT)) {
2077 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2078 1.13 dyoung "Could not load TX desc %d DMA memory!\n", i);
2079 1.1 bouyer rc = ENOMEM;
2080 1.1 bouyer goto bnx_dma_alloc_exit;
2081 1.1 bouyer }
2082 1.1 bouyer
2083 1.1 bouyer sc->tx_bd_chain_paddr[i] =
2084 1.1 bouyer sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr;
2085 1.1 bouyer
2086 1.1 bouyer /* DRC - Fix for 64 bit systems. */
2087 1.1 bouyer DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2088 1.1 bouyer i, (u_int32_t) sc->tx_bd_chain_paddr[i]);
2089 1.1 bouyer }
2090 1.1 bouyer
2091 1.1 bouyer /*
2092 1.1 bouyer * Create DMA maps for the TX buffer mbufs.
2093 1.1 bouyer */
2094 1.1 bouyer for (i = 0; i < TOTAL_TX_BD; i++) {
2095 1.1 bouyer if (bus_dmamap_create(sc->bnx_dmatag,
2096 1.1 bouyer MCLBYTES * BNX_MAX_SEGMENTS,
2097 1.1 bouyer USABLE_TX_BD - BNX_TX_SLACK_SPACE,
2098 1.1 bouyer MCLBYTES, 0, BUS_DMA_NOWAIT,
2099 1.1 bouyer &sc->tx_mbuf_map[i])) {
2100 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2101 1.13 dyoung "Could not create Tx mbuf %d DMA map!\n", i);
2102 1.1 bouyer rc = ENOMEM;
2103 1.1 bouyer goto bnx_dma_alloc_exit;
2104 1.1 bouyer }
2105 1.1 bouyer }
2106 1.1 bouyer
2107 1.1 bouyer /*
2108 1.1 bouyer * Allocate DMA memory for the Rx buffer descriptor chain,
2109 1.1 bouyer * and fetch the physical address of the block.
2110 1.1 bouyer */
2111 1.1 bouyer for (i = 0; i < RX_PAGES; i++) {
2112 1.1 bouyer if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1,
2113 1.1 bouyer BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT,
2114 1.1 bouyer &sc->rx_bd_chain_map[i])) {
2115 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2116 1.13 dyoung "Could not create Rx desc %d DMA map!\n", i);
2117 1.1 bouyer rc = ENOMEM;
2118 1.1 bouyer goto bnx_dma_alloc_exit;
2119 1.1 bouyer }
2120 1.1 bouyer
2121 1.1 bouyer if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ,
2122 1.1 bouyer BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1,
2123 1.1 bouyer &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) {
2124 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2125 1.13 dyoung "Could not allocate Rx desc %d DMA memory!\n", i);
2126 1.1 bouyer rc = ENOMEM;
2127 1.1 bouyer goto bnx_dma_alloc_exit;
2128 1.1 bouyer }
2129 1.1 bouyer
2130 1.1 bouyer if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i],
2131 1.1 bouyer sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ,
2132 1.3 christos (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) {
2133 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2134 1.13 dyoung "Could not map Rx desc %d DMA memory!\n", i);
2135 1.1 bouyer rc = ENOMEM;
2136 1.1 bouyer goto bnx_dma_alloc_exit;
2137 1.1 bouyer }
2138 1.1 bouyer
2139 1.1 bouyer if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i],
2140 1.3 christos (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL,
2141 1.1 bouyer BUS_DMA_NOWAIT)) {
2142 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2143 1.13 dyoung "Could not load Rx desc %d DMA memory!\n", i);
2144 1.1 bouyer rc = ENOMEM;
2145 1.1 bouyer goto bnx_dma_alloc_exit;
2146 1.1 bouyer }
2147 1.1 bouyer
2148 1.1 bouyer bzero(sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ);
2149 1.1 bouyer sc->rx_bd_chain_paddr[i] =
2150 1.1 bouyer sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr;
2151 1.1 bouyer
2152 1.1 bouyer /* DRC - Fix for 64 bit systems. */
2153 1.1 bouyer DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2154 1.1 bouyer i, (u_int32_t) sc->rx_bd_chain_paddr[i]);
2155 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i],
2156 1.1 bouyer 0, BNX_RX_CHAIN_PAGE_SZ,
2157 1.1 bouyer BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2158 1.1 bouyer }
2159 1.1 bouyer
2160 1.1 bouyer /*
2161 1.1 bouyer * Create DMA maps for the Rx buffer mbufs.
2162 1.1 bouyer */
2163 1.1 bouyer for (i = 0; i < TOTAL_RX_BD; i++) {
2164 1.1 bouyer if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU,
2165 1.1 bouyer BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT,
2166 1.1 bouyer &sc->rx_mbuf_map[i])) {
2167 1.13 dyoung aprint_error_dev(sc->bnx_dev,
2168 1.13 dyoung "Could not create Rx mbuf %d DMA map!\n", i);
2169 1.1 bouyer rc = ENOMEM;
2170 1.1 bouyer goto bnx_dma_alloc_exit;
2171 1.1 bouyer }
2172 1.1 bouyer }
2173 1.1 bouyer
2174 1.1 bouyer bnx_dma_alloc_exit:
2175 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
2176 1.1 bouyer
2177 1.1 bouyer return(rc);
2178 1.1 bouyer }
2179 1.1 bouyer
2180 1.1 bouyer /****************************************************************************/
2181 1.1 bouyer /* Release all resources used by the driver. */
2182 1.1 bouyer /* */
2183 1.1 bouyer /* Releases all resources acquired by the driver including interrupts, */
2184 1.1 bouyer /* interrupt handler, interfaces, mutexes, and DMA memory. */
2185 1.1 bouyer /* */
2186 1.1 bouyer /* Returns: */
2187 1.1 bouyer /* Nothing. */
2188 1.1 bouyer /****************************************************************************/
2189 1.1 bouyer void
2190 1.1 bouyer bnx_release_resources(struct bnx_softc *sc)
2191 1.1 bouyer {
2192 1.13 dyoung int i;
2193 1.1 bouyer struct pci_attach_args *pa = &(sc->bnx_pa);
2194 1.1 bouyer
2195 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
2196 1.1 bouyer
2197 1.1 bouyer bnx_dma_free(sc);
2198 1.1 bouyer
2199 1.1 bouyer if (sc->bnx_intrhand != NULL)
2200 1.1 bouyer pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand);
2201 1.1 bouyer
2202 1.1 bouyer if (sc->bnx_size)
2203 1.1 bouyer bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size);
2204 1.1 bouyer
2205 1.13 dyoung for (i = 0; i < TOTAL_RX_BD; i++)
2206 1.19 mhitch if (sc->rx_mbuf_map[i])
2207 1.19 mhitch bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]);
2208 1.13 dyoung
2209 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
2210 1.1 bouyer }
2211 1.1 bouyer
2212 1.1 bouyer /****************************************************************************/
2213 1.1 bouyer /* Firmware synchronization. */
2214 1.1 bouyer /* */
2215 1.1 bouyer /* Before performing certain events such as a chip reset, synchronize with */
2216 1.1 bouyer /* the firmware first. */
2217 1.1 bouyer /* */
2218 1.1 bouyer /* Returns: */
2219 1.1 bouyer /* 0 for success, positive value for failure. */
2220 1.1 bouyer /****************************************************************************/
2221 1.1 bouyer int
2222 1.1 bouyer bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data)
2223 1.1 bouyer {
2224 1.1 bouyer int i, rc = 0;
2225 1.1 bouyer u_int32_t val;
2226 1.1 bouyer
2227 1.1 bouyer /* Don't waste any time if we've timed out before. */
2228 1.1 bouyer if (sc->bnx_fw_timed_out) {
2229 1.1 bouyer rc = EBUSY;
2230 1.1 bouyer goto bnx_fw_sync_exit;
2231 1.1 bouyer }
2232 1.1 bouyer
2233 1.1 bouyer /* Increment the message sequence number. */
2234 1.1 bouyer sc->bnx_fw_wr_seq++;
2235 1.1 bouyer msg_data |= sc->bnx_fw_wr_seq;
2236 1.1 bouyer
2237 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n",
2238 1.1 bouyer msg_data);
2239 1.1 bouyer
2240 1.1 bouyer /* Send the message to the bootcode driver mailbox. */
2241 1.1 bouyer REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data);
2242 1.1 bouyer
2243 1.1 bouyer /* Wait for the bootcode to acknowledge the message. */
2244 1.1 bouyer for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2245 1.1 bouyer /* Check for a response in the bootcode firmware mailbox. */
2246 1.1 bouyer val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB);
2247 1.1 bouyer if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ))
2248 1.1 bouyer break;
2249 1.1 bouyer DELAY(1000);
2250 1.1 bouyer }
2251 1.1 bouyer
2252 1.1 bouyer /* If we've timed out, tell the bootcode that we've stopped waiting. */
2253 1.1 bouyer if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) &&
2254 1.1 bouyer ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) {
2255 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! "
2256 1.1 bouyer "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
2257 1.1 bouyer
2258 1.1 bouyer msg_data &= ~BNX_DRV_MSG_CODE;
2259 1.1 bouyer msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT;
2260 1.1 bouyer
2261 1.1 bouyer REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data);
2262 1.1 bouyer
2263 1.1 bouyer sc->bnx_fw_timed_out = 1;
2264 1.1 bouyer rc = EBUSY;
2265 1.1 bouyer }
2266 1.1 bouyer
2267 1.1 bouyer bnx_fw_sync_exit:
2268 1.1 bouyer return (rc);
2269 1.1 bouyer }
2270 1.1 bouyer
2271 1.1 bouyer /****************************************************************************/
2272 1.1 bouyer /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2273 1.1 bouyer /* */
2274 1.1 bouyer /* Returns: */
2275 1.1 bouyer /* Nothing. */
2276 1.1 bouyer /****************************************************************************/
2277 1.1 bouyer void
2278 1.1 bouyer bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code,
2279 1.1 bouyer u_int32_t rv2p_code_len, u_int32_t rv2p_proc)
2280 1.1 bouyer {
2281 1.1 bouyer int i;
2282 1.1 bouyer u_int32_t val;
2283 1.1 bouyer
2284 1.1 bouyer for (i = 0; i < rv2p_code_len; i += 8) {
2285 1.1 bouyer REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code);
2286 1.1 bouyer rv2p_code++;
2287 1.1 bouyer REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code);
2288 1.1 bouyer rv2p_code++;
2289 1.1 bouyer
2290 1.1 bouyer if (rv2p_proc == RV2P_PROC1) {
2291 1.1 bouyer val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR;
2292 1.1 bouyer REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val);
2293 1.1 bouyer }
2294 1.1 bouyer else {
2295 1.1 bouyer val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR;
2296 1.1 bouyer REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val);
2297 1.1 bouyer }
2298 1.1 bouyer }
2299 1.1 bouyer
2300 1.1 bouyer /* Reset the processor, un-stall is done later. */
2301 1.1 bouyer if (rv2p_proc == RV2P_PROC1)
2302 1.1 bouyer REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET);
2303 1.1 bouyer else
2304 1.1 bouyer REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET);
2305 1.1 bouyer }
2306 1.1 bouyer
2307 1.1 bouyer /****************************************************************************/
2308 1.1 bouyer /* Load RISC processor firmware. */
2309 1.1 bouyer /* */
2310 1.1 bouyer /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */
2311 1.1 bouyer /* associated with a particular processor. */
2312 1.1 bouyer /* */
2313 1.1 bouyer /* Returns: */
2314 1.1 bouyer /* Nothing. */
2315 1.1 bouyer /****************************************************************************/
2316 1.1 bouyer void
2317 1.1 bouyer bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg,
2318 1.1 bouyer struct fw_info *fw)
2319 1.1 bouyer {
2320 1.1 bouyer u_int32_t offset;
2321 1.1 bouyer u_int32_t val;
2322 1.1 bouyer
2323 1.1 bouyer /* Halt the CPU. */
2324 1.1 bouyer val = REG_RD_IND(sc, cpu_reg->mode);
2325 1.1 bouyer val |= cpu_reg->mode_value_halt;
2326 1.1 bouyer REG_WR_IND(sc, cpu_reg->mode, val);
2327 1.1 bouyer REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2328 1.1 bouyer
2329 1.1 bouyer /* Load the Text area. */
2330 1.1 bouyer offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2331 1.1 bouyer if (fw->text) {
2332 1.1 bouyer int j;
2333 1.1 bouyer
2334 1.1 bouyer for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2335 1.1 bouyer REG_WR_IND(sc, offset, fw->text[j]);
2336 1.1 bouyer }
2337 1.1 bouyer
2338 1.1 bouyer /* Load the Data area. */
2339 1.1 bouyer offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2340 1.1 bouyer if (fw->data) {
2341 1.1 bouyer int j;
2342 1.1 bouyer
2343 1.1 bouyer for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2344 1.1 bouyer REG_WR_IND(sc, offset, fw->data[j]);
2345 1.1 bouyer }
2346 1.1 bouyer
2347 1.1 bouyer /* Load the SBSS area. */
2348 1.1 bouyer offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2349 1.1 bouyer if (fw->sbss) {
2350 1.1 bouyer int j;
2351 1.1 bouyer
2352 1.1 bouyer for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2353 1.1 bouyer REG_WR_IND(sc, offset, fw->sbss[j]);
2354 1.1 bouyer }
2355 1.1 bouyer
2356 1.1 bouyer /* Load the BSS area. */
2357 1.1 bouyer offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2358 1.1 bouyer if (fw->bss) {
2359 1.1 bouyer int j;
2360 1.1 bouyer
2361 1.1 bouyer for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2362 1.1 bouyer REG_WR_IND(sc, offset, fw->bss[j]);
2363 1.1 bouyer }
2364 1.1 bouyer
2365 1.1 bouyer /* Load the Read-Only area. */
2366 1.1 bouyer offset = cpu_reg->spad_base +
2367 1.1 bouyer (fw->rodata_addr - cpu_reg->mips_view_base);
2368 1.1 bouyer if (fw->rodata) {
2369 1.1 bouyer int j;
2370 1.1 bouyer
2371 1.1 bouyer for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2372 1.1 bouyer REG_WR_IND(sc, offset, fw->rodata[j]);
2373 1.1 bouyer }
2374 1.1 bouyer
2375 1.1 bouyer /* Clear the pre-fetch instruction. */
2376 1.1 bouyer REG_WR_IND(sc, cpu_reg->inst, 0);
2377 1.1 bouyer REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2378 1.1 bouyer
2379 1.1 bouyer /* Start the CPU. */
2380 1.1 bouyer val = REG_RD_IND(sc, cpu_reg->mode);
2381 1.1 bouyer val &= ~cpu_reg->mode_value_halt;
2382 1.1 bouyer REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2383 1.1 bouyer REG_WR_IND(sc, cpu_reg->mode, val);
2384 1.1 bouyer }
2385 1.1 bouyer
2386 1.1 bouyer /****************************************************************************/
2387 1.1 bouyer /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */
2388 1.1 bouyer /* */
2389 1.1 bouyer /* Loads the firmware for each CPU and starts the CPU. */
2390 1.1 bouyer /* */
2391 1.1 bouyer /* Returns: */
2392 1.1 bouyer /* Nothing. */
2393 1.1 bouyer /****************************************************************************/
2394 1.1 bouyer void
2395 1.1 bouyer bnx_init_cpus(struct bnx_softc *sc)
2396 1.1 bouyer {
2397 1.1 bouyer struct cpu_reg cpu_reg;
2398 1.1 bouyer struct fw_info fw;
2399 1.1 bouyer
2400 1.1 bouyer /* Initialize the RV2P processor. */
2401 1.1 bouyer bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1),
2402 1.1 bouyer RV2P_PROC1);
2403 1.1 bouyer bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2),
2404 1.1 bouyer RV2P_PROC2);
2405 1.1 bouyer
2406 1.1 bouyer /* Initialize the RX Processor. */
2407 1.1 bouyer cpu_reg.mode = BNX_RXP_CPU_MODE;
2408 1.1 bouyer cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT;
2409 1.1 bouyer cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA;
2410 1.1 bouyer cpu_reg.state = BNX_RXP_CPU_STATE;
2411 1.1 bouyer cpu_reg.state_value_clear = 0xffffff;
2412 1.1 bouyer cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE;
2413 1.1 bouyer cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK;
2414 1.1 bouyer cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER;
2415 1.1 bouyer cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;
2416 1.1 bouyer cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT;
2417 1.1 bouyer cpu_reg.spad_base = BNX_RXP_SCRATCH;
2418 1.1 bouyer cpu_reg.mips_view_base = 0x8000000;
2419 1.1 bouyer
2420 1.1 bouyer fw.ver_major = bnx_RXP_b06FwReleaseMajor;
2421 1.1 bouyer fw.ver_minor = bnx_RXP_b06FwReleaseMinor;
2422 1.1 bouyer fw.ver_fix = bnx_RXP_b06FwReleaseFix;
2423 1.1 bouyer fw.start_addr = bnx_RXP_b06FwStartAddr;
2424 1.1 bouyer
2425 1.1 bouyer fw.text_addr = bnx_RXP_b06FwTextAddr;
2426 1.1 bouyer fw.text_len = bnx_RXP_b06FwTextLen;
2427 1.1 bouyer fw.text_index = 0;
2428 1.1 bouyer fw.text = bnx_RXP_b06FwText;
2429 1.1 bouyer
2430 1.1 bouyer fw.data_addr = bnx_RXP_b06FwDataAddr;
2431 1.1 bouyer fw.data_len = bnx_RXP_b06FwDataLen;
2432 1.1 bouyer fw.data_index = 0;
2433 1.1 bouyer fw.data = bnx_RXP_b06FwData;
2434 1.1 bouyer
2435 1.1 bouyer fw.sbss_addr = bnx_RXP_b06FwSbssAddr;
2436 1.1 bouyer fw.sbss_len = bnx_RXP_b06FwSbssLen;
2437 1.1 bouyer fw.sbss_index = 0;
2438 1.1 bouyer fw.sbss = bnx_RXP_b06FwSbss;
2439 1.1 bouyer
2440 1.1 bouyer fw.bss_addr = bnx_RXP_b06FwBssAddr;
2441 1.1 bouyer fw.bss_len = bnx_RXP_b06FwBssLen;
2442 1.1 bouyer fw.bss_index = 0;
2443 1.1 bouyer fw.bss = bnx_RXP_b06FwBss;
2444 1.1 bouyer
2445 1.1 bouyer fw.rodata_addr = bnx_RXP_b06FwRodataAddr;
2446 1.1 bouyer fw.rodata_len = bnx_RXP_b06FwRodataLen;
2447 1.1 bouyer fw.rodata_index = 0;
2448 1.1 bouyer fw.rodata = bnx_RXP_b06FwRodata;
2449 1.1 bouyer
2450 1.1 bouyer DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n");
2451 1.1 bouyer bnx_load_cpu_fw(sc, &cpu_reg, &fw);
2452 1.1 bouyer
2453 1.1 bouyer /* Initialize the TX Processor. */
2454 1.1 bouyer cpu_reg.mode = BNX_TXP_CPU_MODE;
2455 1.1 bouyer cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT;
2456 1.1 bouyer cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA;
2457 1.1 bouyer cpu_reg.state = BNX_TXP_CPU_STATE;
2458 1.1 bouyer cpu_reg.state_value_clear = 0xffffff;
2459 1.1 bouyer cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE;
2460 1.1 bouyer cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK;
2461 1.1 bouyer cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER;
2462 1.1 bouyer cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;
2463 1.1 bouyer cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT;
2464 1.1 bouyer cpu_reg.spad_base = BNX_TXP_SCRATCH;
2465 1.1 bouyer cpu_reg.mips_view_base = 0x8000000;
2466 1.1 bouyer
2467 1.1 bouyer fw.ver_major = bnx_TXP_b06FwReleaseMajor;
2468 1.1 bouyer fw.ver_minor = bnx_TXP_b06FwReleaseMinor;
2469 1.1 bouyer fw.ver_fix = bnx_TXP_b06FwReleaseFix;
2470 1.1 bouyer fw.start_addr = bnx_TXP_b06FwStartAddr;
2471 1.1 bouyer
2472 1.1 bouyer fw.text_addr = bnx_TXP_b06FwTextAddr;
2473 1.1 bouyer fw.text_len = bnx_TXP_b06FwTextLen;
2474 1.1 bouyer fw.text_index = 0;
2475 1.1 bouyer fw.text = bnx_TXP_b06FwText;
2476 1.1 bouyer
2477 1.1 bouyer fw.data_addr = bnx_TXP_b06FwDataAddr;
2478 1.1 bouyer fw.data_len = bnx_TXP_b06FwDataLen;
2479 1.1 bouyer fw.data_index = 0;
2480 1.1 bouyer fw.data = bnx_TXP_b06FwData;
2481 1.1 bouyer
2482 1.1 bouyer fw.sbss_addr = bnx_TXP_b06FwSbssAddr;
2483 1.1 bouyer fw.sbss_len = bnx_TXP_b06FwSbssLen;
2484 1.1 bouyer fw.sbss_index = 0;
2485 1.1 bouyer fw.sbss = bnx_TXP_b06FwSbss;
2486 1.1 bouyer
2487 1.1 bouyer fw.bss_addr = bnx_TXP_b06FwBssAddr;
2488 1.1 bouyer fw.bss_len = bnx_TXP_b06FwBssLen;
2489 1.1 bouyer fw.bss_index = 0;
2490 1.1 bouyer fw.bss = bnx_TXP_b06FwBss;
2491 1.1 bouyer
2492 1.1 bouyer fw.rodata_addr = bnx_TXP_b06FwRodataAddr;
2493 1.1 bouyer fw.rodata_len = bnx_TXP_b06FwRodataLen;
2494 1.1 bouyer fw.rodata_index = 0;
2495 1.1 bouyer fw.rodata = bnx_TXP_b06FwRodata;
2496 1.1 bouyer
2497 1.1 bouyer DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n");
2498 1.1 bouyer bnx_load_cpu_fw(sc, &cpu_reg, &fw);
2499 1.1 bouyer
2500 1.1 bouyer /* Initialize the TX Patch-up Processor. */
2501 1.1 bouyer cpu_reg.mode = BNX_TPAT_CPU_MODE;
2502 1.1 bouyer cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT;
2503 1.1 bouyer cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA;
2504 1.1 bouyer cpu_reg.state = BNX_TPAT_CPU_STATE;
2505 1.1 bouyer cpu_reg.state_value_clear = 0xffffff;
2506 1.1 bouyer cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE;
2507 1.1 bouyer cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK;
2508 1.1 bouyer cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER;
2509 1.1 bouyer cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;
2510 1.1 bouyer cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT;
2511 1.1 bouyer cpu_reg.spad_base = BNX_TPAT_SCRATCH;
2512 1.1 bouyer cpu_reg.mips_view_base = 0x8000000;
2513 1.1 bouyer
2514 1.1 bouyer fw.ver_major = bnx_TPAT_b06FwReleaseMajor;
2515 1.1 bouyer fw.ver_minor = bnx_TPAT_b06FwReleaseMinor;
2516 1.1 bouyer fw.ver_fix = bnx_TPAT_b06FwReleaseFix;
2517 1.1 bouyer fw.start_addr = bnx_TPAT_b06FwStartAddr;
2518 1.1 bouyer
2519 1.1 bouyer fw.text_addr = bnx_TPAT_b06FwTextAddr;
2520 1.1 bouyer fw.text_len = bnx_TPAT_b06FwTextLen;
2521 1.1 bouyer fw.text_index = 0;
2522 1.1 bouyer fw.text = bnx_TPAT_b06FwText;
2523 1.1 bouyer
2524 1.1 bouyer fw.data_addr = bnx_TPAT_b06FwDataAddr;
2525 1.1 bouyer fw.data_len = bnx_TPAT_b06FwDataLen;
2526 1.1 bouyer fw.data_index = 0;
2527 1.1 bouyer fw.data = bnx_TPAT_b06FwData;
2528 1.1 bouyer
2529 1.1 bouyer fw.sbss_addr = bnx_TPAT_b06FwSbssAddr;
2530 1.1 bouyer fw.sbss_len = bnx_TPAT_b06FwSbssLen;
2531 1.1 bouyer fw.sbss_index = 0;
2532 1.1 bouyer fw.sbss = bnx_TPAT_b06FwSbss;
2533 1.1 bouyer
2534 1.1 bouyer fw.bss_addr = bnx_TPAT_b06FwBssAddr;
2535 1.1 bouyer fw.bss_len = bnx_TPAT_b06FwBssLen;
2536 1.1 bouyer fw.bss_index = 0;
2537 1.1 bouyer fw.bss = bnx_TPAT_b06FwBss;
2538 1.1 bouyer
2539 1.1 bouyer fw.rodata_addr = bnx_TPAT_b06FwRodataAddr;
2540 1.1 bouyer fw.rodata_len = bnx_TPAT_b06FwRodataLen;
2541 1.1 bouyer fw.rodata_index = 0;
2542 1.1 bouyer fw.rodata = bnx_TPAT_b06FwRodata;
2543 1.1 bouyer
2544 1.1 bouyer DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n");
2545 1.1 bouyer bnx_load_cpu_fw(sc, &cpu_reg, &fw);
2546 1.1 bouyer
2547 1.1 bouyer /* Initialize the Completion Processor. */
2548 1.1 bouyer cpu_reg.mode = BNX_COM_CPU_MODE;
2549 1.1 bouyer cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT;
2550 1.1 bouyer cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA;
2551 1.1 bouyer cpu_reg.state = BNX_COM_CPU_STATE;
2552 1.1 bouyer cpu_reg.state_value_clear = 0xffffff;
2553 1.1 bouyer cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE;
2554 1.1 bouyer cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK;
2555 1.1 bouyer cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER;
2556 1.1 bouyer cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;
2557 1.1 bouyer cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT;
2558 1.1 bouyer cpu_reg.spad_base = BNX_COM_SCRATCH;
2559 1.1 bouyer cpu_reg.mips_view_base = 0x8000000;
2560 1.1 bouyer
2561 1.1 bouyer fw.ver_major = bnx_COM_b06FwReleaseMajor;
2562 1.1 bouyer fw.ver_minor = bnx_COM_b06FwReleaseMinor;
2563 1.1 bouyer fw.ver_fix = bnx_COM_b06FwReleaseFix;
2564 1.1 bouyer fw.start_addr = bnx_COM_b06FwStartAddr;
2565 1.1 bouyer
2566 1.1 bouyer fw.text_addr = bnx_COM_b06FwTextAddr;
2567 1.1 bouyer fw.text_len = bnx_COM_b06FwTextLen;
2568 1.1 bouyer fw.text_index = 0;
2569 1.1 bouyer fw.text = bnx_COM_b06FwText;
2570 1.1 bouyer
2571 1.1 bouyer fw.data_addr = bnx_COM_b06FwDataAddr;
2572 1.1 bouyer fw.data_len = bnx_COM_b06FwDataLen;
2573 1.1 bouyer fw.data_index = 0;
2574 1.1 bouyer fw.data = bnx_COM_b06FwData;
2575 1.1 bouyer
2576 1.1 bouyer fw.sbss_addr = bnx_COM_b06FwSbssAddr;
2577 1.1 bouyer fw.sbss_len = bnx_COM_b06FwSbssLen;
2578 1.1 bouyer fw.sbss_index = 0;
2579 1.1 bouyer fw.sbss = bnx_COM_b06FwSbss;
2580 1.1 bouyer
2581 1.1 bouyer fw.bss_addr = bnx_COM_b06FwBssAddr;
2582 1.1 bouyer fw.bss_len = bnx_COM_b06FwBssLen;
2583 1.1 bouyer fw.bss_index = 0;
2584 1.1 bouyer fw.bss = bnx_COM_b06FwBss;
2585 1.1 bouyer
2586 1.1 bouyer fw.rodata_addr = bnx_COM_b06FwRodataAddr;
2587 1.1 bouyer fw.rodata_len = bnx_COM_b06FwRodataLen;
2588 1.1 bouyer fw.rodata_index = 0;
2589 1.1 bouyer fw.rodata = bnx_COM_b06FwRodata;
2590 1.1 bouyer
2591 1.1 bouyer DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n");
2592 1.1 bouyer bnx_load_cpu_fw(sc, &cpu_reg, &fw);
2593 1.1 bouyer }
2594 1.1 bouyer
2595 1.1 bouyer /****************************************************************************/
2596 1.1 bouyer /* Initialize context memory. */
2597 1.1 bouyer /* */
2598 1.1 bouyer /* Clears the memory associated with each Context ID (CID). */
2599 1.1 bouyer /* */
2600 1.1 bouyer /* Returns: */
2601 1.1 bouyer /* Nothing. */
2602 1.1 bouyer /****************************************************************************/
2603 1.1 bouyer void
2604 1.1 bouyer bnx_init_context(struct bnx_softc *sc)
2605 1.1 bouyer {
2606 1.1 bouyer u_int32_t vcid;
2607 1.1 bouyer
2608 1.1 bouyer vcid = 96;
2609 1.1 bouyer while (vcid) {
2610 1.1 bouyer u_int32_t vcid_addr, pcid_addr, offset;
2611 1.1 bouyer
2612 1.1 bouyer vcid--;
2613 1.1 bouyer
2614 1.1 bouyer vcid_addr = GET_CID_ADDR(vcid);
2615 1.1 bouyer pcid_addr = vcid_addr;
2616 1.1 bouyer
2617 1.1 bouyer REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00);
2618 1.1 bouyer REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr);
2619 1.1 bouyer
2620 1.1 bouyer /* Zero out the context. */
2621 1.1 bouyer for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2622 1.1 bouyer CTX_WR(sc, 0x00, offset, 0);
2623 1.1 bouyer
2624 1.1 bouyer REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr);
2625 1.1 bouyer REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr);
2626 1.1 bouyer }
2627 1.1 bouyer }
2628 1.1 bouyer
2629 1.1 bouyer /****************************************************************************/
2630 1.1 bouyer /* Fetch the permanent MAC address of the controller. */
2631 1.1 bouyer /* */
2632 1.1 bouyer /* Returns: */
2633 1.1 bouyer /* Nothing. */
2634 1.1 bouyer /****************************************************************************/
2635 1.1 bouyer void
2636 1.1 bouyer bnx_get_mac_addr(struct bnx_softc *sc)
2637 1.1 bouyer {
2638 1.1 bouyer u_int32_t mac_lo = 0, mac_hi = 0;
2639 1.1 bouyer
2640 1.1 bouyer /*
2641 1.1 bouyer * The NetXtreme II bootcode populates various NIC
2642 1.1 bouyer * power-on and runtime configuration items in a
2643 1.1 bouyer * shared memory area. The factory configured MAC
2644 1.1 bouyer * address is available from both NVRAM and the
2645 1.1 bouyer * shared memory area so we'll read the value from
2646 1.1 bouyer * shared memory for speed.
2647 1.1 bouyer */
2648 1.1 bouyer
2649 1.1 bouyer mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER);
2650 1.1 bouyer mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER);
2651 1.1 bouyer
2652 1.1 bouyer if ((mac_lo == 0) && (mac_hi == 0)) {
2653 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n",
2654 1.1 bouyer __FILE__, __LINE__);
2655 1.1 bouyer } else {
2656 1.1 bouyer sc->eaddr[0] = (u_char)(mac_hi >> 8);
2657 1.1 bouyer sc->eaddr[1] = (u_char)(mac_hi >> 0);
2658 1.1 bouyer sc->eaddr[2] = (u_char)(mac_lo >> 24);
2659 1.1 bouyer sc->eaddr[3] = (u_char)(mac_lo >> 16);
2660 1.1 bouyer sc->eaddr[4] = (u_char)(mac_lo >> 8);
2661 1.1 bouyer sc->eaddr[5] = (u_char)(mac_lo >> 0);
2662 1.1 bouyer }
2663 1.1 bouyer
2664 1.1 bouyer DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = "
2665 1.1 bouyer "%s\n", ether_sprintf(sc->eaddr));
2666 1.1 bouyer }
2667 1.1 bouyer
2668 1.1 bouyer /****************************************************************************/
2669 1.1 bouyer /* Program the MAC address. */
2670 1.1 bouyer /* */
2671 1.1 bouyer /* Returns: */
2672 1.1 bouyer /* Nothing. */
2673 1.1 bouyer /****************************************************************************/
2674 1.1 bouyer void
2675 1.1 bouyer bnx_set_mac_addr(struct bnx_softc *sc)
2676 1.1 bouyer {
2677 1.1 bouyer u_int32_t val;
2678 1.15 dyoung const u_int8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl);
2679 1.1 bouyer
2680 1.1 bouyer DBPRINT(sc, BNX_INFO, "Setting Ethernet address = "
2681 1.1 bouyer "%s\n", ether_sprintf(sc->eaddr));
2682 1.1 bouyer
2683 1.1 bouyer val = (mac_addr[0] << 8) | mac_addr[1];
2684 1.1 bouyer
2685 1.1 bouyer REG_WR(sc, BNX_EMAC_MAC_MATCH0, val);
2686 1.1 bouyer
2687 1.1 bouyer val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2688 1.1 bouyer (mac_addr[4] << 8) | mac_addr[5];
2689 1.1 bouyer
2690 1.1 bouyer REG_WR(sc, BNX_EMAC_MAC_MATCH1, val);
2691 1.1 bouyer }
2692 1.1 bouyer
2693 1.1 bouyer /****************************************************************************/
2694 1.1 bouyer /* Stop the controller. */
2695 1.1 bouyer /* */
2696 1.1 bouyer /* Returns: */
2697 1.1 bouyer /* Nothing. */
2698 1.1 bouyer /****************************************************************************/
2699 1.1 bouyer void
2700 1.14 dyoung bnx_stop(struct ifnet *ifp, int disable)
2701 1.1 bouyer {
2702 1.14 dyoung struct bnx_softc *sc = ifp->if_softc;
2703 1.1 bouyer
2704 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
2705 1.1 bouyer
2706 1.14 dyoung if ((ifp->if_flags & IFF_RUNNING) == 0)
2707 1.14 dyoung return;
2708 1.1 bouyer
2709 1.1 bouyer callout_stop(&sc->bnx_timeout);
2710 1.1 bouyer
2711 1.14 dyoung mii_down(&sc->bnx_mii);
2712 1.14 dyoung
2713 1.1 bouyer ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2714 1.1 bouyer
2715 1.1 bouyer /* Disable the transmit/receive blocks. */
2716 1.1 bouyer REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff);
2717 1.1 bouyer REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
2718 1.1 bouyer DELAY(20);
2719 1.1 bouyer
2720 1.1 bouyer bnx_disable_intr(sc);
2721 1.1 bouyer
2722 1.1 bouyer /* Tell firmware that the driver is going away. */
2723 1.14 dyoung if (disable)
2724 1.14 dyoung bnx_reset(sc, BNX_DRV_MSG_CODE_RESET);
2725 1.14 dyoung else
2726 1.14 dyoung bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL);
2727 1.1 bouyer
2728 1.1 bouyer /* Free the RX lists. */
2729 1.1 bouyer bnx_free_rx_chain(sc);
2730 1.1 bouyer
2731 1.1 bouyer /* Free TX buffers. */
2732 1.1 bouyer bnx_free_tx_chain(sc);
2733 1.1 bouyer
2734 1.1 bouyer ifp->if_timer = 0;
2735 1.1 bouyer
2736 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
2737 1.1 bouyer
2738 1.1 bouyer }
2739 1.1 bouyer
2740 1.1 bouyer int
2741 1.1 bouyer bnx_reset(struct bnx_softc *sc, u_int32_t reset_code)
2742 1.1 bouyer {
2743 1.1 bouyer u_int32_t val;
2744 1.1 bouyer int i, rc = 0;
2745 1.1 bouyer
2746 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
2747 1.1 bouyer
2748 1.1 bouyer /* Wait for pending PCI transactions to complete. */
2749 1.1 bouyer REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS,
2750 1.1 bouyer BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2751 1.1 bouyer BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2752 1.1 bouyer BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2753 1.1 bouyer BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2754 1.1 bouyer val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
2755 1.1 bouyer DELAY(5);
2756 1.1 bouyer
2757 1.1 bouyer /* Assume bootcode is running. */
2758 1.1 bouyer sc->bnx_fw_timed_out = 0;
2759 1.1 bouyer
2760 1.1 bouyer /* Give the firmware a chance to prepare for the reset. */
2761 1.1 bouyer rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code);
2762 1.1 bouyer if (rc)
2763 1.1 bouyer goto bnx_reset_exit;
2764 1.1 bouyer
2765 1.1 bouyer /* Set a firmware reminder that this is a soft reset. */
2766 1.1 bouyer REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE,
2767 1.1 bouyer BNX_DRV_RESET_SIGNATURE_MAGIC);
2768 1.1 bouyer
2769 1.1 bouyer /* Dummy read to force the chip to complete all current transactions. */
2770 1.1 bouyer val = REG_RD(sc, BNX_MISC_ID);
2771 1.1 bouyer
2772 1.1 bouyer /* Chip reset. */
2773 1.1 bouyer val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2774 1.1 bouyer BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2775 1.1 bouyer BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2776 1.1 bouyer REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val);
2777 1.1 bouyer
2778 1.1 bouyer /* Allow up to 30us for reset to complete. */
2779 1.1 bouyer for (i = 0; i < 10; i++) {
2780 1.1 bouyer val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG);
2781 1.1 bouyer if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2782 1.1 bouyer BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
2783 1.1 bouyer break;
2784 1.1 bouyer
2785 1.1 bouyer DELAY(10);
2786 1.1 bouyer }
2787 1.1 bouyer
2788 1.1 bouyer /* Check that reset completed successfully. */
2789 1.1 bouyer if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2790 1.1 bouyer BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2791 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__);
2792 1.1 bouyer rc = EBUSY;
2793 1.1 bouyer goto bnx_reset_exit;
2794 1.1 bouyer }
2795 1.1 bouyer
2796 1.1 bouyer /* Make sure byte swapping is properly configured. */
2797 1.1 bouyer val = REG_RD(sc, BNX_PCI_SWAP_DIAG0);
2798 1.1 bouyer if (val != 0x01020304) {
2799 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n",
2800 1.1 bouyer __FILE__, __LINE__);
2801 1.1 bouyer rc = ENODEV;
2802 1.1 bouyer goto bnx_reset_exit;
2803 1.1 bouyer }
2804 1.1 bouyer
2805 1.1 bouyer /* Just completed a reset, assume that firmware is running again. */
2806 1.1 bouyer sc->bnx_fw_timed_out = 0;
2807 1.1 bouyer
2808 1.1 bouyer /* Wait for the firmware to finish its initialization. */
2809 1.1 bouyer rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code);
2810 1.1 bouyer if (rc)
2811 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Firmware did not complete "
2812 1.1 bouyer "initialization!\n", __FILE__, __LINE__);
2813 1.1 bouyer
2814 1.1 bouyer bnx_reset_exit:
2815 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
2816 1.1 bouyer
2817 1.1 bouyer return (rc);
2818 1.1 bouyer }
2819 1.1 bouyer
2820 1.1 bouyer int
2821 1.1 bouyer bnx_chipinit(struct bnx_softc *sc)
2822 1.1 bouyer {
2823 1.1 bouyer struct pci_attach_args *pa = &(sc->bnx_pa);
2824 1.1 bouyer u_int32_t val;
2825 1.1 bouyer int rc = 0;
2826 1.1 bouyer
2827 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
2828 1.1 bouyer
2829 1.1 bouyer /* Make sure the interrupt is not active. */
2830 1.1 bouyer REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);
2831 1.1 bouyer
2832 1.1 bouyer /* Initialize DMA byte/word swapping, configure the number of DMA */
2833 1.1 bouyer /* channels and PCI clock compensation delay. */
2834 1.1 bouyer val = BNX_DMA_CONFIG_DATA_BYTE_SWAP |
2835 1.1 bouyer BNX_DMA_CONFIG_DATA_WORD_SWAP |
2836 1.1 bouyer #if BYTE_ORDER == BIG_ENDIAN
2837 1.1 bouyer BNX_DMA_CONFIG_CNTL_BYTE_SWAP |
2838 1.1 bouyer #endif
2839 1.1 bouyer BNX_DMA_CONFIG_CNTL_WORD_SWAP |
2840 1.1 bouyer DMA_READ_CHANS << 12 |
2841 1.1 bouyer DMA_WRITE_CHANS << 16;
2842 1.1 bouyer
2843 1.1 bouyer val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY;
2844 1.1 bouyer
2845 1.1 bouyer if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
2846 1.1 bouyer val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP;
2847 1.1 bouyer
2848 1.1 bouyer /*
2849 1.1 bouyer * This setting resolves a problem observed on certain Intel PCI
2850 1.1 bouyer * chipsets that cannot handle multiple outstanding DMA operations.
2851 1.1 bouyer * See errata E9_5706A1_65.
2852 1.1 bouyer */
2853 1.1 bouyer if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) &&
2854 1.1 bouyer (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) &&
2855 1.1 bouyer !(sc->bnx_flags & BNX_PCIX_FLAG))
2856 1.1 bouyer val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA;
2857 1.1 bouyer
2858 1.1 bouyer REG_WR(sc, BNX_DMA_CONFIG, val);
2859 1.1 bouyer
2860 1.1 bouyer /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
2861 1.1 bouyer if (sc->bnx_flags & BNX_PCIX_FLAG) {
2862 1.1 bouyer u_int16_t nval;
2863 1.1 bouyer
2864 1.1 bouyer nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD);
2865 1.1 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD,
2866 1.17 joerg nval & ~0x20000);
2867 1.1 bouyer }
2868 1.1 bouyer
2869 1.1 bouyer /* Enable the RX_V2P and Context state machines before access. */
2870 1.1 bouyer REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,
2871 1.1 bouyer BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2872 1.1 bouyer BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2873 1.1 bouyer BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2874 1.1 bouyer
2875 1.1 bouyer /* Initialize context mapping and zero out the quick contexts. */
2876 1.1 bouyer bnx_init_context(sc);
2877 1.1 bouyer
2878 1.1 bouyer /* Initialize the on-boards CPUs */
2879 1.1 bouyer bnx_init_cpus(sc);
2880 1.1 bouyer
2881 1.1 bouyer /* Prepare NVRAM for access. */
2882 1.1 bouyer if (bnx_init_nvram(sc)) {
2883 1.1 bouyer rc = ENODEV;
2884 1.1 bouyer goto bnx_chipinit_exit;
2885 1.1 bouyer }
2886 1.1 bouyer
2887 1.1 bouyer /* Set the kernel bypass block size */
2888 1.1 bouyer val = REG_RD(sc, BNX_MQ_CONFIG);
2889 1.1 bouyer val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2890 1.1 bouyer val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2891 1.1 bouyer REG_WR(sc, BNX_MQ_CONFIG, val);
2892 1.1 bouyer
2893 1.1 bouyer val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2894 1.1 bouyer REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val);
2895 1.1 bouyer REG_WR(sc, BNX_MQ_KNL_WIND_END, val);
2896 1.1 bouyer
2897 1.1 bouyer val = (BCM_PAGE_BITS - 8) << 24;
2898 1.1 bouyer REG_WR(sc, BNX_RV2P_CONFIG, val);
2899 1.1 bouyer
2900 1.1 bouyer /* Configure page size. */
2901 1.1 bouyer val = REG_RD(sc, BNX_TBDR_CONFIG);
2902 1.1 bouyer val &= ~BNX_TBDR_CONFIG_PAGE_SIZE;
2903 1.1 bouyer val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2904 1.1 bouyer REG_WR(sc, BNX_TBDR_CONFIG, val);
2905 1.1 bouyer
2906 1.1 bouyer bnx_chipinit_exit:
2907 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
2908 1.1 bouyer
2909 1.1 bouyer return(rc);
2910 1.1 bouyer }
2911 1.1 bouyer
2912 1.1 bouyer /****************************************************************************/
2913 1.1 bouyer /* Initialize the controller in preparation to send/receive traffic. */
2914 1.1 bouyer /* */
2915 1.1 bouyer /* Returns: */
2916 1.1 bouyer /* 0 for success, positive value for failure. */
2917 1.1 bouyer /****************************************************************************/
2918 1.1 bouyer int
2919 1.1 bouyer bnx_blockinit(struct bnx_softc *sc)
2920 1.1 bouyer {
2921 1.1 bouyer u_int32_t reg, val;
2922 1.1 bouyer int rc = 0;
2923 1.1 bouyer
2924 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
2925 1.1 bouyer
2926 1.1 bouyer /* Load the hardware default MAC address. */
2927 1.1 bouyer bnx_set_mac_addr(sc);
2928 1.1 bouyer
2929 1.1 bouyer /* Set the Ethernet backoff seed value */
2930 1.1 bouyer val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
2931 1.1 bouyer (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
2932 1.1 bouyer REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val);
2933 1.1 bouyer
2934 1.1 bouyer sc->last_status_idx = 0;
2935 1.1 bouyer sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE;
2936 1.1 bouyer
2937 1.1 bouyer /* Set up link change interrupt generation. */
2938 1.1 bouyer REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK);
2939 1.1 bouyer
2940 1.1 bouyer /* Program the physical address of the status block. */
2941 1.1 bouyer REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr));
2942 1.1 bouyer REG_WR(sc, BNX_HC_STATUS_ADDR_H,
2943 1.1 bouyer (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32));
2944 1.1 bouyer
2945 1.1 bouyer /* Program the physical address of the statistics block. */
2946 1.1 bouyer REG_WR(sc, BNX_HC_STATISTICS_ADDR_L,
2947 1.1 bouyer (u_int32_t)(sc->stats_block_paddr));
2948 1.1 bouyer REG_WR(sc, BNX_HC_STATISTICS_ADDR_H,
2949 1.1 bouyer (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32));
2950 1.1 bouyer
2951 1.1 bouyer /* Program various host coalescing parameters. */
2952 1.1 bouyer REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int
2953 1.1 bouyer << 16) | sc->bnx_tx_quick_cons_trip);
2954 1.1 bouyer REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int
2955 1.1 bouyer << 16) | sc->bnx_rx_quick_cons_trip);
2956 1.1 bouyer REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) |
2957 1.1 bouyer sc->bnx_comp_prod_trip);
2958 1.1 bouyer REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) |
2959 1.1 bouyer sc->bnx_tx_ticks);
2960 1.1 bouyer REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) |
2961 1.1 bouyer sc->bnx_rx_ticks);
2962 1.1 bouyer REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) |
2963 1.1 bouyer sc->bnx_com_ticks);
2964 1.1 bouyer REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) |
2965 1.1 bouyer sc->bnx_cmd_ticks);
2966 1.1 bouyer REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00));
2967 1.1 bouyer REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
2968 1.1 bouyer REG_WR(sc, BNX_HC_CONFIG,
2969 1.1 bouyer (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE |
2970 1.1 bouyer BNX_HC_CONFIG_COLLECT_STATS));
2971 1.1 bouyer
2972 1.1 bouyer /* Clear the internal statistics counters. */
2973 1.1 bouyer REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW);
2974 1.1 bouyer
2975 1.1 bouyer /* Verify that bootcode is running. */
2976 1.1 bouyer reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE);
2977 1.1 bouyer
2978 1.1 bouyer DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure),
2979 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n",
2980 1.1 bouyer __FILE__, __LINE__); reg = 0);
2981 1.1 bouyer
2982 1.1 bouyer if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
2983 1.1 bouyer BNX_DEV_INFO_SIGNATURE_MAGIC) {
2984 1.1 bouyer BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, "
2985 1.1 bouyer "Expected: 08%08X\n", __FILE__, __LINE__,
2986 1.1 bouyer (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK),
2987 1.1 bouyer BNX_DEV_INFO_SIGNATURE_MAGIC);
2988 1.1 bouyer rc = ENODEV;
2989 1.1 bouyer goto bnx_blockinit_exit;
2990 1.1 bouyer }
2991 1.1 bouyer
2992 1.1 bouyer /* Check if any management firmware is running. */
2993 1.1 bouyer reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE);
2994 1.1 bouyer if (reg & (BNX_PORT_FEATURE_ASF_ENABLED |
2995 1.1 bouyer BNX_PORT_FEATURE_IMD_ENABLED)) {
2996 1.1 bouyer DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n");
2997 1.1 bouyer sc->bnx_flags |= BNX_MFW_ENABLE_FLAG;
2998 1.1 bouyer }
2999 1.1 bouyer
3000 1.1 bouyer sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base +
3001 1.1 bouyer BNX_DEV_INFO_BC_REV);
3002 1.1 bouyer
3003 1.1 bouyer DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver);
3004 1.1 bouyer
3005 1.1 bouyer /* Allow bootcode to apply any additional fixes before enabling MAC. */
3006 1.1 bouyer rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET);
3007 1.1 bouyer
3008 1.1 bouyer /* Enable link state change interrupt generation. */
3009 1.1 bouyer REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3010 1.1 bouyer
3011 1.1 bouyer /* Enable all remaining blocks in the MAC. */
3012 1.1 bouyer REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff);
3013 1.1 bouyer REG_RD(sc, BNX_MISC_ENABLE_SET_BITS);
3014 1.1 bouyer DELAY(20);
3015 1.1 bouyer
3016 1.1 bouyer bnx_blockinit_exit:
3017 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
3018 1.1 bouyer
3019 1.1 bouyer return (rc);
3020 1.1 bouyer }
3021 1.1 bouyer
3022 1.1 bouyer /****************************************************************************/
3023 1.1 bouyer /* Encapsulate an mbuf cluster into the rx_bd chain. */
3024 1.1 bouyer /* */
3025 1.1 bouyer /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3026 1.1 bouyer /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3027 1.1 bouyer /* necessary. */
3028 1.1 bouyer /* */
3029 1.1 bouyer /* Returns: */
3030 1.1 bouyer /* 0 for success, positive value for failure. */
3031 1.1 bouyer /****************************************************************************/
3032 1.1 bouyer int
3033 1.1 bouyer bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod,
3034 1.1 bouyer u_int16_t *chain_prod, u_int32_t *prod_bseq)
3035 1.1 bouyer {
3036 1.1 bouyer bus_dmamap_t map;
3037 1.1 bouyer struct mbuf *m_new = NULL;
3038 1.1 bouyer struct rx_bd *rxbd;
3039 1.1 bouyer int i, rc = 0;
3040 1.1 bouyer u_int32_t addr;
3041 1.1 bouyer #ifdef BNX_DEBUG
3042 1.1 bouyer u_int16_t debug_chain_prod = *chain_prod;
3043 1.1 bouyer #endif
3044 1.2 bouyer u_int16_t first_chain_prod;
3045 1.5 bouyer u_int16_t min_free_bd;
3046 1.1 bouyer
3047 1.1 bouyer DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n",
3048 1.12 perry __func__);
3049 1.1 bouyer
3050 1.1 bouyer /* Make sure the inputs are valid. */
3051 1.1 bouyer DBRUNIF((*chain_prod > MAX_RX_BD),
3052 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3053 1.13 dyoung "RX producer out of range: 0x%04X > 0x%04X\n",
3054 1.13 dyoung *chain_prod, (u_int16_t)MAX_RX_BD));
3055 1.1 bouyer
3056 1.1 bouyer DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = "
3057 1.12 perry "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod,
3058 1.1 bouyer *prod_bseq);
3059 1.1 bouyer
3060 1.5 bouyer /* try to get in as many mbufs as possible */
3061 1.5 bouyer if (sc->mbuf_alloc_size == MCLBYTES)
3062 1.5 bouyer min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE;
3063 1.5 bouyer else
3064 1.5 bouyer min_free_bd = (BNX_MAX_MRU + PAGE_SIZE - 1) / PAGE_SIZE;
3065 1.5 bouyer while (sc->free_rx_bd >= min_free_bd) {
3066 1.5 bouyer if (m == NULL) {
3067 1.5 bouyer DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure),
3068 1.5 bouyer BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n");
3069 1.5 bouyer
3070 1.5 bouyer sc->mbuf_alloc_failed++;
3071 1.5 bouyer rc = ENOBUFS;
3072 1.5 bouyer goto bnx_get_buf_exit);
3073 1.5 bouyer
3074 1.5 bouyer /* This is a new mbuf allocation. */
3075 1.5 bouyer MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3076 1.5 bouyer if (m_new == NULL) {
3077 1.5 bouyer DBPRINT(sc, BNX_WARN,
3078 1.5 bouyer "%s(%d): RX mbuf header allocation failed!\n",
3079 1.5 bouyer __FILE__, __LINE__);
3080 1.5 bouyer
3081 1.5 bouyer DBRUNIF(1, sc->mbuf_alloc_failed++);
3082 1.1 bouyer
3083 1.5 bouyer rc = ENOBUFS;
3084 1.5 bouyer goto bnx_get_buf_exit;
3085 1.5 bouyer }
3086 1.1 bouyer
3087 1.5 bouyer DBRUNIF(1, sc->rx_mbuf_alloc++);
3088 1.5 bouyer if (sc->mbuf_alloc_size == MCLBYTES)
3089 1.5 bouyer MCLGET(m_new, M_DONTWAIT);
3090 1.5 bouyer else
3091 1.5 bouyer MEXTMALLOC(m_new, sc->mbuf_alloc_size,
3092 1.5 bouyer M_DONTWAIT);
3093 1.5 bouyer if (!(m_new->m_flags & M_EXT)) {
3094 1.5 bouyer DBPRINT(sc, BNX_WARN,
3095 1.5 bouyer "%s(%d): RX mbuf chain allocation failed!\n",
3096 1.5 bouyer __FILE__, __LINE__);
3097 1.5 bouyer
3098 1.5 bouyer m_freem(m_new);
3099 1.1 bouyer
3100 1.5 bouyer DBRUNIF(1, sc->rx_mbuf_alloc--);
3101 1.5 bouyer DBRUNIF(1, sc->mbuf_alloc_failed++);
3102 1.1 bouyer
3103 1.5 bouyer rc = ENOBUFS;
3104 1.5 bouyer goto bnx_get_buf_exit;
3105 1.5 bouyer }
3106 1.5 bouyer
3107 1.5 bouyer } else {
3108 1.5 bouyer m_new = m;
3109 1.5 bouyer m = NULL;
3110 1.5 bouyer m_new->m_data = m_new->m_ext.ext_buf;
3111 1.1 bouyer }
3112 1.5 bouyer m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size;
3113 1.1 bouyer
3114 1.5 bouyer /* Map the mbuf cluster into device memory. */
3115 1.5 bouyer map = sc->rx_mbuf_map[*chain_prod];
3116 1.5 bouyer first_chain_prod = *chain_prod;
3117 1.5 bouyer if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) {
3118 1.5 bouyer BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n",
3119 1.1 bouyer __FILE__, __LINE__);
3120 1.5 bouyer
3121 1.1 bouyer m_freem(m_new);
3122 1.1 bouyer
3123 1.1 bouyer DBRUNIF(1, sc->rx_mbuf_alloc--);
3124 1.1 bouyer
3125 1.1 bouyer rc = ENOBUFS;
3126 1.1 bouyer goto bnx_get_buf_exit;
3127 1.1 bouyer }
3128 1.5 bouyer bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize,
3129 1.5 bouyer BUS_DMASYNC_PREREAD);
3130 1.1 bouyer
3131 1.5 bouyer /* Watch for overflow. */
3132 1.5 bouyer DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3133 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3134 1.13 dyoung "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3135 1.13 dyoung sc->free_rx_bd, (u_int16_t)USABLE_RX_BD));
3136 1.1 bouyer
3137 1.5 bouyer DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3138 1.5 bouyer sc->rx_low_watermark = sc->free_rx_bd);
3139 1.1 bouyer
3140 1.5 bouyer /*
3141 1.5 bouyer * Setup the rx_bd for the first segment
3142 1.5 bouyer */
3143 1.5 bouyer rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3144 1.1 bouyer
3145 1.5 bouyer addr = (u_int32_t)(map->dm_segs[0].ds_addr);
3146 1.5 bouyer rxbd->rx_bd_haddr_lo = htole32(addr);
3147 1.5 bouyer addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32);
3148 1.5 bouyer rxbd->rx_bd_haddr_hi = htole32(addr);
3149 1.5 bouyer rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len);
3150 1.5 bouyer rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3151 1.5 bouyer *prod_bseq += map->dm_segs[0].ds_len;
3152 1.5 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3153 1.5 bouyer sc->rx_bd_chain_map[RX_PAGE(*chain_prod)],
3154 1.5 bouyer sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd),
3155 1.5 bouyer BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3156 1.1 bouyer
3157 1.5 bouyer for (i = 1; i < map->dm_nsegs; i++) {
3158 1.5 bouyer *prod = NEXT_RX_BD(*prod);
3159 1.5 bouyer *chain_prod = RX_CHAIN_IDX(*prod);
3160 1.5 bouyer
3161 1.5 bouyer rxbd =
3162 1.5 bouyer &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3163 1.5 bouyer
3164 1.5 bouyer addr = (u_int32_t)(map->dm_segs[i].ds_addr);
3165 1.5 bouyer rxbd->rx_bd_haddr_lo = htole32(addr);
3166 1.5 bouyer addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32);
3167 1.5 bouyer rxbd->rx_bd_haddr_hi = htole32(addr);
3168 1.5 bouyer rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len);
3169 1.5 bouyer rxbd->rx_bd_flags = 0;
3170 1.5 bouyer *prod_bseq += map->dm_segs[i].ds_len;
3171 1.5 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3172 1.5 bouyer sc->rx_bd_chain_map[RX_PAGE(*chain_prod)],
3173 1.5 bouyer sizeof(struct rx_bd) * RX_IDX(*chain_prod),
3174 1.5 bouyer sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3175 1.5 bouyer }
3176 1.1 bouyer
3177 1.5 bouyer rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3178 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3179 1.1 bouyer sc->rx_bd_chain_map[RX_PAGE(*chain_prod)],
3180 1.1 bouyer sizeof(struct rx_bd) * RX_IDX(*chain_prod),
3181 1.1 bouyer sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3182 1.1 bouyer
3183 1.5 bouyer /*
3184 1.5 bouyer * Save the mbuf, ajust the map pointer (swap map for first and
3185 1.5 bouyer * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches)
3186 1.5 bouyer * and update counter.
3187 1.5 bouyer */
3188 1.5 bouyer sc->rx_mbuf_ptr[*chain_prod] = m_new;
3189 1.5 bouyer sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod];
3190 1.5 bouyer sc->rx_mbuf_map[*chain_prod] = map;
3191 1.5 bouyer sc->free_rx_bd -= map->dm_nsegs;
3192 1.1 bouyer
3193 1.5 bouyer DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod,
3194 1.5 bouyer map->dm_nsegs));
3195 1.5 bouyer *prod = NEXT_RX_BD(*prod);
3196 1.5 bouyer *chain_prod = RX_CHAIN_IDX(*prod);
3197 1.5 bouyer }
3198 1.1 bouyer
3199 1.5 bouyer bnx_get_buf_exit:
3200 1.1 bouyer DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod "
3201 1.12 perry "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod,
3202 1.1 bouyer *chain_prod, *prod_bseq);
3203 1.1 bouyer
3204 1.1 bouyer DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n",
3205 1.12 perry __func__);
3206 1.1 bouyer
3207 1.1 bouyer return(rc);
3208 1.1 bouyer }
3209 1.1 bouyer
3210 1.1 bouyer /****************************************************************************/
3211 1.1 bouyer /* Allocate memory and initialize the TX data structures. */
3212 1.1 bouyer /* */
3213 1.1 bouyer /* Returns: */
3214 1.1 bouyer /* 0 for success, positive value for failure. */
3215 1.1 bouyer /****************************************************************************/
3216 1.1 bouyer int
3217 1.1 bouyer bnx_init_tx_chain(struct bnx_softc *sc)
3218 1.1 bouyer {
3219 1.1 bouyer struct tx_bd *txbd;
3220 1.1 bouyer u_int32_t val, addr;
3221 1.1 bouyer int i, rc = 0;
3222 1.1 bouyer
3223 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
3224 1.1 bouyer
3225 1.1 bouyer /* Set the initial TX producer/consumer indices. */
3226 1.1 bouyer sc->tx_prod = 0;
3227 1.1 bouyer sc->tx_cons = 0;
3228 1.1 bouyer sc->tx_prod_bseq = 0;
3229 1.1 bouyer sc->used_tx_bd = 0;
3230 1.1 bouyer DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3231 1.1 bouyer
3232 1.1 bouyer /*
3233 1.1 bouyer * The NetXtreme II supports a linked-list structure called
3234 1.1 bouyer * a Buffer Descriptor Chain (or BD chain). A BD chain
3235 1.1 bouyer * consists of a series of 1 or more chain pages, each of which
3236 1.1 bouyer * consists of a fixed number of BD entries.
3237 1.1 bouyer * The last BD entry on each page is a pointer to the next page
3238 1.1 bouyer * in the chain, and the last pointer in the BD chain
3239 1.1 bouyer * points back to the beginning of the chain.
3240 1.1 bouyer */
3241 1.1 bouyer
3242 1.1 bouyer /* Set the TX next pointer chain entries. */
3243 1.1 bouyer for (i = 0; i < TX_PAGES; i++) {
3244 1.1 bouyer int j;
3245 1.1 bouyer
3246 1.1 bouyer txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3247 1.1 bouyer
3248 1.1 bouyer /* Check if we've reached the last page. */
3249 1.1 bouyer if (i == (TX_PAGES - 1))
3250 1.1 bouyer j = 0;
3251 1.1 bouyer else
3252 1.1 bouyer j = i + 1;
3253 1.1 bouyer
3254 1.1 bouyer addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]);
3255 1.1 bouyer txbd->tx_bd_haddr_lo = htole32(addr);
3256 1.1 bouyer addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32);
3257 1.1 bouyer txbd->tx_bd_haddr_hi = htole32(addr);
3258 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0,
3259 1.1 bouyer BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE);
3260 1.1 bouyer }
3261 1.1 bouyer
3262 1.1 bouyer /*
3263 1.1 bouyer * Initialize the context ID for an L2 TX chain.
3264 1.1 bouyer */
3265 1.1 bouyer val = BNX_L2CTX_TYPE_TYPE_L2;
3266 1.1 bouyer val |= BNX_L2CTX_TYPE_SIZE_L2;
3267 1.1 bouyer CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val);
3268 1.1 bouyer
3269 1.1 bouyer val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3270 1.1 bouyer CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val);
3271 1.1 bouyer
3272 1.1 bouyer /* Point the hardware to the first page in the chain. */
3273 1.1 bouyer val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32);
3274 1.1 bouyer CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val);
3275 1.1 bouyer val = (u_int32_t)(sc->tx_bd_chain_paddr[0]);
3276 1.1 bouyer CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val);
3277 1.1 bouyer
3278 1.1 bouyer DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD));
3279 1.1 bouyer
3280 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
3281 1.1 bouyer
3282 1.1 bouyer return(rc);
3283 1.1 bouyer }
3284 1.1 bouyer
3285 1.1 bouyer /****************************************************************************/
3286 1.1 bouyer /* Free memory and clear the TX data structures. */
3287 1.1 bouyer /* */
3288 1.1 bouyer /* Returns: */
3289 1.1 bouyer /* Nothing. */
3290 1.1 bouyer /****************************************************************************/
3291 1.1 bouyer void
3292 1.1 bouyer bnx_free_tx_chain(struct bnx_softc *sc)
3293 1.1 bouyer {
3294 1.1 bouyer int i;
3295 1.1 bouyer
3296 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
3297 1.1 bouyer
3298 1.1 bouyer /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3299 1.1 bouyer for (i = 0; i < TOTAL_TX_BD; i++) {
3300 1.1 bouyer if (sc->tx_mbuf_ptr[i] != NULL) {
3301 1.1 bouyer if (sc->tx_mbuf_map != NULL)
3302 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3303 1.1 bouyer sc->tx_mbuf_map[i], 0,
3304 1.1 bouyer sc->tx_mbuf_map[i]->dm_mapsize,
3305 1.1 bouyer BUS_DMASYNC_POSTWRITE);
3306 1.1 bouyer m_freem(sc->tx_mbuf_ptr[i]);
3307 1.1 bouyer sc->tx_mbuf_ptr[i] = NULL;
3308 1.1 bouyer DBRUNIF(1, sc->tx_mbuf_alloc--);
3309 1.1 bouyer }
3310 1.1 bouyer }
3311 1.1 bouyer
3312 1.1 bouyer /* Clear each TX chain page. */
3313 1.1 bouyer for (i = 0; i < TX_PAGES; i++) {
3314 1.1 bouyer bzero((char *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ);
3315 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0,
3316 1.1 bouyer BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE);
3317 1.1 bouyer }
3318 1.1 bouyer
3319 1.1 bouyer /* Check if we lost any mbufs in the process. */
3320 1.1 bouyer DBRUNIF((sc->tx_mbuf_alloc),
3321 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3322 1.13 dyoung "Memory leak! Lost %d mbufs from tx chain!\n",
3323 1.13 dyoung sc->tx_mbuf_alloc));
3324 1.1 bouyer
3325 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
3326 1.1 bouyer }
3327 1.1 bouyer
3328 1.1 bouyer /****************************************************************************/
3329 1.1 bouyer /* Allocate memory and initialize the RX data structures. */
3330 1.1 bouyer /* */
3331 1.1 bouyer /* Returns: */
3332 1.1 bouyer /* 0 for success, positive value for failure. */
3333 1.1 bouyer /****************************************************************************/
3334 1.1 bouyer int
3335 1.1 bouyer bnx_init_rx_chain(struct bnx_softc *sc)
3336 1.1 bouyer {
3337 1.1 bouyer struct rx_bd *rxbd;
3338 1.1 bouyer int i, rc = 0;
3339 1.1 bouyer u_int16_t prod, chain_prod;
3340 1.1 bouyer u_int32_t prod_bseq, val, addr;
3341 1.1 bouyer
3342 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
3343 1.1 bouyer
3344 1.1 bouyer /* Initialize the RX producer and consumer indices. */
3345 1.1 bouyer sc->rx_prod = 0;
3346 1.1 bouyer sc->rx_cons = 0;
3347 1.1 bouyer sc->rx_prod_bseq = 0;
3348 1.1 bouyer sc->free_rx_bd = BNX_RX_SLACK_SPACE;
3349 1.1 bouyer DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3350 1.1 bouyer
3351 1.1 bouyer /* Initialize the RX next pointer chain entries. */
3352 1.1 bouyer for (i = 0; i < RX_PAGES; i++) {
3353 1.1 bouyer int j;
3354 1.1 bouyer
3355 1.1 bouyer rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3356 1.1 bouyer
3357 1.1 bouyer /* Check if we've reached the last page. */
3358 1.1 bouyer if (i == (RX_PAGES - 1))
3359 1.1 bouyer j = 0;
3360 1.1 bouyer else
3361 1.1 bouyer j = i + 1;
3362 1.1 bouyer
3363 1.1 bouyer /* Setup the chain page pointers. */
3364 1.1 bouyer addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32);
3365 1.1 bouyer rxbd->rx_bd_haddr_hi = htole32(addr);
3366 1.1 bouyer addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]);
3367 1.1 bouyer rxbd->rx_bd_haddr_lo = htole32(addr);
3368 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i],
3369 1.1 bouyer 0, BNX_RX_CHAIN_PAGE_SZ,
3370 1.1 bouyer BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3371 1.1 bouyer }
3372 1.1 bouyer
3373 1.1 bouyer /* Initialize the context ID for an L2 RX chain. */
3374 1.1 bouyer val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3375 1.1 bouyer val |= BNX_L2CTX_CTX_TYPE_SIZE_L2;
3376 1.1 bouyer val |= 0x02 << 8;
3377 1.1 bouyer CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val);
3378 1.1 bouyer
3379 1.1 bouyer /* Point the hardware to the first page in the chain. */
3380 1.1 bouyer val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32);
3381 1.1 bouyer CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val);
3382 1.1 bouyer val = (u_int32_t)(sc->rx_bd_chain_paddr[0]);
3383 1.1 bouyer CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val);
3384 1.1 bouyer
3385 1.1 bouyer /* Allocate mbuf clusters for the rx_bd chain. */
3386 1.1 bouyer prod = prod_bseq = 0;
3387 1.5 bouyer chain_prod = RX_CHAIN_IDX(prod);
3388 1.5 bouyer if (bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) {
3389 1.5 bouyer BNX_PRINTF(sc,
3390 1.5 bouyer "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod);
3391 1.1 bouyer }
3392 1.1 bouyer
3393 1.1 bouyer /* Save the RX chain producer index. */
3394 1.1 bouyer sc->rx_prod = prod;
3395 1.1 bouyer sc->rx_prod_bseq = prod_bseq;
3396 1.1 bouyer
3397 1.1 bouyer for (i = 0; i < RX_PAGES; i++)
3398 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0,
3399 1.1 bouyer sc->rx_bd_chain_map[i]->dm_mapsize,
3400 1.1 bouyer BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3401 1.1 bouyer
3402 1.1 bouyer /* Tell the chip about the waiting rx_bd's. */
3403 1.1 bouyer REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod);
3404 1.1 bouyer REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3405 1.1 bouyer
3406 1.1 bouyer DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD));
3407 1.1 bouyer
3408 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
3409 1.1 bouyer
3410 1.1 bouyer return(rc);
3411 1.1 bouyer }
3412 1.1 bouyer
3413 1.1 bouyer /****************************************************************************/
3414 1.1 bouyer /* Free memory and clear the RX data structures. */
3415 1.1 bouyer /* */
3416 1.1 bouyer /* Returns: */
3417 1.1 bouyer /* Nothing. */
3418 1.1 bouyer /****************************************************************************/
3419 1.1 bouyer void
3420 1.1 bouyer bnx_free_rx_chain(struct bnx_softc *sc)
3421 1.1 bouyer {
3422 1.1 bouyer int i;
3423 1.1 bouyer
3424 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
3425 1.1 bouyer
3426 1.1 bouyer /* Free any mbufs still in the RX mbuf chain. */
3427 1.1 bouyer for (i = 0; i < TOTAL_RX_BD; i++) {
3428 1.1 bouyer if (sc->rx_mbuf_ptr[i] != NULL) {
3429 1.1 bouyer if (sc->rx_mbuf_map[i] != NULL)
3430 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3431 1.1 bouyer sc->rx_mbuf_map[i], 0,
3432 1.1 bouyer sc->rx_mbuf_map[i]->dm_mapsize,
3433 1.1 bouyer BUS_DMASYNC_POSTREAD);
3434 1.1 bouyer m_freem(sc->rx_mbuf_ptr[i]);
3435 1.1 bouyer sc->rx_mbuf_ptr[i] = NULL;
3436 1.1 bouyer DBRUNIF(1, sc->rx_mbuf_alloc--);
3437 1.1 bouyer }
3438 1.1 bouyer }
3439 1.1 bouyer
3440 1.1 bouyer /* Clear each RX chain page. */
3441 1.1 bouyer for (i = 0; i < RX_PAGES; i++)
3442 1.1 bouyer bzero((char *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ);
3443 1.1 bouyer
3444 1.1 bouyer /* Check if we lost any mbufs in the process. */
3445 1.1 bouyer DBRUNIF((sc->rx_mbuf_alloc),
3446 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3447 1.13 dyoung "Memory leak! Lost %d mbufs from rx chain!\n",
3448 1.13 dyoung sc->rx_mbuf_alloc));
3449 1.1 bouyer
3450 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
3451 1.1 bouyer }
3452 1.1 bouyer
3453 1.1 bouyer /****************************************************************************/
3454 1.1 bouyer /* Handles PHY generated interrupt events. */
3455 1.1 bouyer /* */
3456 1.1 bouyer /* Returns: */
3457 1.1 bouyer /* Nothing. */
3458 1.1 bouyer /****************************************************************************/
3459 1.1 bouyer void
3460 1.1 bouyer bnx_phy_intr(struct bnx_softc *sc)
3461 1.1 bouyer {
3462 1.1 bouyer u_int32_t new_link_state, old_link_state;
3463 1.1 bouyer
3464 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ,
3465 1.1 bouyer BUS_DMASYNC_POSTREAD);
3466 1.1 bouyer new_link_state = sc->status_block->status_attn_bits &
3467 1.1 bouyer STATUS_ATTN_BITS_LINK_STATE;
3468 1.1 bouyer old_link_state = sc->status_block->status_attn_bits_ack &
3469 1.1 bouyer STATUS_ATTN_BITS_LINK_STATE;
3470 1.1 bouyer
3471 1.1 bouyer /* Handle any changes if the link state has changed. */
3472 1.1 bouyer if (new_link_state != old_link_state) {
3473 1.1 bouyer DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc));
3474 1.1 bouyer
3475 1.1 bouyer callout_stop(&sc->bnx_timeout);
3476 1.1 bouyer bnx_tick(sc);
3477 1.1 bouyer
3478 1.1 bouyer /* Update the status_attn_bits_ack field in the status block. */
3479 1.1 bouyer if (new_link_state) {
3480 1.1 bouyer REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD,
3481 1.1 bouyer STATUS_ATTN_BITS_LINK_STATE);
3482 1.1 bouyer DBPRINT(sc, BNX_INFO, "Link is now UP.\n");
3483 1.1 bouyer } else {
3484 1.1 bouyer REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD,
3485 1.1 bouyer STATUS_ATTN_BITS_LINK_STATE);
3486 1.1 bouyer DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n");
3487 1.1 bouyer }
3488 1.1 bouyer }
3489 1.1 bouyer
3490 1.1 bouyer /* Acknowledge the link change interrupt. */
3491 1.1 bouyer REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE);
3492 1.1 bouyer }
3493 1.1 bouyer
3494 1.1 bouyer /****************************************************************************/
3495 1.1 bouyer /* Handles received frame interrupt events. */
3496 1.1 bouyer /* */
3497 1.1 bouyer /* Returns: */
3498 1.1 bouyer /* Nothing. */
3499 1.1 bouyer /****************************************************************************/
3500 1.1 bouyer void
3501 1.1 bouyer bnx_rx_intr(struct bnx_softc *sc)
3502 1.1 bouyer {
3503 1.1 bouyer struct status_block *sblk = sc->status_block;
3504 1.15 dyoung struct ifnet *ifp = &sc->bnx_ec.ec_if;
3505 1.1 bouyer u_int16_t hw_cons, sw_cons, sw_chain_cons;
3506 1.1 bouyer u_int16_t sw_prod, sw_chain_prod;
3507 1.1 bouyer u_int32_t sw_prod_bseq;
3508 1.1 bouyer struct l2_fhdr *l2fhdr;
3509 1.1 bouyer int i;
3510 1.1 bouyer
3511 1.1 bouyer DBRUNIF(1, sc->rx_interrupts++);
3512 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ,
3513 1.1 bouyer BUS_DMASYNC_POSTREAD);
3514 1.1 bouyer
3515 1.1 bouyer /* Prepare the RX chain pages to be accessed by the host CPU. */
3516 1.1 bouyer for (i = 0; i < RX_PAGES; i++)
3517 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3518 1.1 bouyer sc->rx_bd_chain_map[i], 0,
3519 1.1 bouyer sc->rx_bd_chain_map[i]->dm_mapsize,
3520 1.1 bouyer BUS_DMASYNC_POSTWRITE);
3521 1.1 bouyer
3522 1.1 bouyer /* Get the hardware's view of the RX consumer index. */
3523 1.1 bouyer hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
3524 1.1 bouyer if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
3525 1.1 bouyer hw_cons++;
3526 1.1 bouyer
3527 1.1 bouyer /* Get working copies of the driver's view of the RX indices. */
3528 1.1 bouyer sw_cons = sc->rx_cons;
3529 1.1 bouyer sw_prod = sc->rx_prod;
3530 1.1 bouyer sw_prod_bseq = sc->rx_prod_bseq;
3531 1.1 bouyer
3532 1.1 bouyer DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
3533 1.1 bouyer "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
3534 1.12 perry __func__, sw_prod, sw_cons, sw_prod_bseq);
3535 1.1 bouyer
3536 1.1 bouyer /* Prevent speculative reads from getting ahead of the status block. */
3537 1.1 bouyer bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0,
3538 1.1 bouyer BUS_SPACE_BARRIER_READ);
3539 1.1 bouyer
3540 1.1 bouyer DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3541 1.1 bouyer sc->rx_low_watermark = sc->free_rx_bd);
3542 1.1 bouyer
3543 1.1 bouyer /*
3544 1.1 bouyer * Scan through the receive chain as long
3545 1.1 bouyer * as there is work to do.
3546 1.1 bouyer */
3547 1.1 bouyer while (sw_cons != hw_cons) {
3548 1.1 bouyer struct mbuf *m;
3549 1.1 bouyer struct rx_bd *rxbd;
3550 1.1 bouyer unsigned int len;
3551 1.1 bouyer u_int32_t status;
3552 1.1 bouyer
3553 1.1 bouyer /* Convert the producer/consumer indices to an actual
3554 1.1 bouyer * rx_bd index.
3555 1.1 bouyer */
3556 1.1 bouyer sw_chain_cons = RX_CHAIN_IDX(sw_cons);
3557 1.1 bouyer sw_chain_prod = RX_CHAIN_IDX(sw_prod);
3558 1.1 bouyer
3559 1.1 bouyer /* Get the used rx_bd. */
3560 1.1 bouyer rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)];
3561 1.1 bouyer sc->free_rx_bd++;
3562 1.1 bouyer
3563 1.12 perry DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__);
3564 1.1 bouyer bnx_dump_rxbd(sc, sw_chain_cons, rxbd));
3565 1.1 bouyer
3566 1.1 bouyer /* The mbuf is stored with the last rx_bd entry of a packet. */
3567 1.1 bouyer if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
3568 1.5 bouyer #ifdef DIAGNOSTIC
3569 1.1 bouyer /* Validate that this is the last rx_bd. */
3570 1.5 bouyer if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) {
3571 1.5 bouyer printf("%s: Unexpected mbuf found in "
3572 1.13 dyoung "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev),
3573 1.1 bouyer sw_chain_cons);
3574 1.5 bouyer }
3575 1.5 bouyer #endif
3576 1.1 bouyer
3577 1.1 bouyer /* DRC - ToDo: If the received packet is small, say less
3578 1.1 bouyer * than 128 bytes, allocate a new mbuf here,
3579 1.1 bouyer * copy the data to that mbuf, and recycle
3580 1.1 bouyer * the mapped jumbo frame.
3581 1.1 bouyer */
3582 1.1 bouyer
3583 1.1 bouyer /* Unmap the mbuf from DMA space. */
3584 1.5 bouyer #ifdef DIAGNOSTIC
3585 1.5 bouyer if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) {
3586 1.5 bouyer printf("invalid map sw_cons 0x%x "
3587 1.5 bouyer "sw_prod 0x%x "
3588 1.5 bouyer "sw_chain_cons 0x%x "
3589 1.5 bouyer "sw_chain_prod 0x%x "
3590 1.5 bouyer "hw_cons 0x%x "
3591 1.6 bouyer "TOTAL_RX_BD_PER_PAGE 0x%x "
3592 1.6 bouyer "TOTAL_RX_BD 0x%x\n",
3593 1.5 bouyer sw_cons, sw_prod, sw_chain_cons, sw_chain_prod,
3594 1.6 bouyer hw_cons,
3595 1.6 bouyer (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD);
3596 1.5 bouyer }
3597 1.5 bouyer #endif
3598 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3599 1.1 bouyer sc->rx_mbuf_map[sw_chain_cons], 0,
3600 1.1 bouyer sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize,
3601 1.1 bouyer BUS_DMASYNC_POSTREAD);
3602 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag,
3603 1.1 bouyer sc->rx_mbuf_map[sw_chain_cons]);
3604 1.1 bouyer
3605 1.1 bouyer /* Remove the mbuf from the driver's chain. */
3606 1.1 bouyer m = sc->rx_mbuf_ptr[sw_chain_cons];
3607 1.1 bouyer sc->rx_mbuf_ptr[sw_chain_cons] = NULL;
3608 1.1 bouyer
3609 1.1 bouyer /*
3610 1.1 bouyer * Frames received on the NetXteme II are prepended
3611 1.1 bouyer * with the l2_fhdr structure which provides status
3612 1.1 bouyer * information about the received frame (including
3613 1.1 bouyer * VLAN tags and checksum info) and are also
3614 1.1 bouyer * automatically adjusted to align the IP header
3615 1.1 bouyer * (i.e. two null bytes are inserted before the
3616 1.1 bouyer * Ethernet header).
3617 1.1 bouyer */
3618 1.1 bouyer l2fhdr = mtod(m, struct l2_fhdr *);
3619 1.1 bouyer
3620 1.1 bouyer len = l2fhdr->l2_fhdr_pkt_len;
3621 1.1 bouyer status = l2fhdr->l2_fhdr_status;
3622 1.1 bouyer
3623 1.1 bouyer DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check),
3624 1.1 bouyer aprint_error("Simulating l2_fhdr status error.\n");
3625 1.1 bouyer status = status | L2_FHDR_ERRORS_PHY_DECODE);
3626 1.1 bouyer
3627 1.1 bouyer /* Watch for unusual sized frames. */
3628 1.1 bouyer DBRUNIF(((len < BNX_MIN_MTU) ||
3629 1.1 bouyer (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)),
3630 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3631 1.13 dyoung "Unusual frame size found. "
3632 1.13 dyoung "Min(%d), Actual(%d), Max(%d)\n",
3633 1.13 dyoung (int)BNX_MIN_MTU, len,
3634 1.13 dyoung (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN);
3635 1.1 bouyer
3636 1.1 bouyer bnx_dump_mbuf(sc, m);
3637 1.1 bouyer bnx_breakpoint(sc));
3638 1.1 bouyer
3639 1.1 bouyer len -= ETHER_CRC_LEN;
3640 1.1 bouyer
3641 1.1 bouyer /* Check the received frame for errors. */
3642 1.1 bouyer if ((status & (L2_FHDR_ERRORS_BAD_CRC |
3643 1.1 bouyer L2_FHDR_ERRORS_PHY_DECODE |
3644 1.1 bouyer L2_FHDR_ERRORS_ALIGNMENT |
3645 1.1 bouyer L2_FHDR_ERRORS_TOO_SHORT |
3646 1.1 bouyer L2_FHDR_ERRORS_GIANT_FRAME)) ||
3647 1.1 bouyer len < (BNX_MIN_MTU - ETHER_CRC_LEN) ||
3648 1.1 bouyer len >
3649 1.1 bouyer (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) {
3650 1.1 bouyer ifp->if_ierrors++;
3651 1.1 bouyer DBRUNIF(1, sc->l2fhdr_status_errors++);
3652 1.1 bouyer
3653 1.1 bouyer /* Reuse the mbuf for a new frame. */
3654 1.1 bouyer if (bnx_get_buf(sc, m, &sw_prod,
3655 1.1 bouyer &sw_chain_prod, &sw_prod_bseq)) {
3656 1.1 bouyer DBRUNIF(1, bnx_breakpoint(sc));
3657 1.1 bouyer panic("%s: Can't reuse RX mbuf!\n",
3658 1.13 dyoung device_xname(sc->bnx_dev));
3659 1.1 bouyer }
3660 1.5 bouyer continue;
3661 1.1 bouyer }
3662 1.1 bouyer
3663 1.1 bouyer /*
3664 1.1 bouyer * Get a new mbuf for the rx_bd. If no new
3665 1.1 bouyer * mbufs are available then reuse the current mbuf,
3666 1.1 bouyer * log an ierror on the interface, and generate
3667 1.1 bouyer * an error in the system log.
3668 1.1 bouyer */
3669 1.1 bouyer if (bnx_get_buf(sc, NULL, &sw_prod, &sw_chain_prod,
3670 1.1 bouyer &sw_prod_bseq)) {
3671 1.1 bouyer DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate "
3672 1.1 bouyer "new mbuf, incoming frame dropped!\n"));
3673 1.1 bouyer
3674 1.1 bouyer ifp->if_ierrors++;
3675 1.1 bouyer
3676 1.1 bouyer /* Try and reuse the exisitng mbuf. */
3677 1.1 bouyer if (bnx_get_buf(sc, m, &sw_prod,
3678 1.1 bouyer &sw_chain_prod, &sw_prod_bseq)) {
3679 1.1 bouyer DBRUNIF(1, bnx_breakpoint(sc));
3680 1.1 bouyer panic("%s: Double mbuf allocation "
3681 1.13 dyoung "failure!",
3682 1.13 dyoung device_xname(sc->bnx_dev));
3683 1.1 bouyer }
3684 1.5 bouyer continue;
3685 1.1 bouyer }
3686 1.1 bouyer
3687 1.1 bouyer /* Skip over the l2_fhdr when passing the data up
3688 1.1 bouyer * the stack.
3689 1.1 bouyer */
3690 1.1 bouyer m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
3691 1.1 bouyer
3692 1.1 bouyer /* Adjust the pckt length to match the received data. */
3693 1.1 bouyer m->m_pkthdr.len = m->m_len = len;
3694 1.1 bouyer
3695 1.1 bouyer /* Send the packet to the appropriate interface. */
3696 1.1 bouyer m->m_pkthdr.rcvif = ifp;
3697 1.1 bouyer
3698 1.1 bouyer DBRUN(BNX_VERBOSE_RECV,
3699 1.1 bouyer struct ether_header *eh;
3700 1.1 bouyer eh = mtod(m, struct ether_header *);
3701 1.1 bouyer aprint_error("%s: to: %s, from: %s, type: 0x%04X\n",
3702 1.12 perry __func__, ether_sprintf(eh->ether_dhost),
3703 1.1 bouyer ether_sprintf(eh->ether_shost),
3704 1.1 bouyer htons(eh->ether_type)));
3705 1.1 bouyer
3706 1.1 bouyer /* Validate the checksum. */
3707 1.1 bouyer
3708 1.1 bouyer /* Check for an IP datagram. */
3709 1.1 bouyer if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
3710 1.1 bouyer /* Check if the IP checksum is valid. */
3711 1.1 bouyer if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff)
3712 1.1 bouyer == 0)
3713 1.1 bouyer m->m_pkthdr.csum_flags |=
3714 1.1 bouyer M_CSUM_IPv4;
3715 1.1 bouyer #ifdef BNX_DEBUG
3716 1.1 bouyer else
3717 1.1 bouyer DBPRINT(sc, BNX_WARN_SEND,
3718 1.1 bouyer "%s(): Invalid IP checksum "
3719 1.1 bouyer "= 0x%04X!\n",
3720 1.12 perry __func__,
3721 1.1 bouyer l2fhdr->l2_fhdr_ip_xsum
3722 1.1 bouyer );
3723 1.1 bouyer #endif
3724 1.1 bouyer }
3725 1.1 bouyer
3726 1.1 bouyer /* Check for a valid TCP/UDP frame. */
3727 1.1 bouyer if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3728 1.1 bouyer L2_FHDR_STATUS_UDP_DATAGRAM)) {
3729 1.1 bouyer /* Check for a good TCP/UDP checksum. */
3730 1.1 bouyer if ((status &
3731 1.1 bouyer (L2_FHDR_ERRORS_TCP_XSUM |
3732 1.1 bouyer L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
3733 1.1 bouyer m->m_pkthdr.csum_flags |=
3734 1.1 bouyer M_CSUM_TCPv4 |
3735 1.1 bouyer M_CSUM_UDPv4;
3736 1.1 bouyer } else {
3737 1.1 bouyer DBPRINT(sc, BNX_WARN_SEND,
3738 1.1 bouyer "%s(): Invalid TCP/UDP "
3739 1.1 bouyer "checksum = 0x%04X!\n",
3740 1.12 perry __func__,
3741 1.1 bouyer l2fhdr->l2_fhdr_tcp_udp_xsum);
3742 1.1 bouyer }
3743 1.1 bouyer }
3744 1.1 bouyer
3745 1.1 bouyer /*
3746 1.1 bouyer * If we received a packet with a vlan tag,
3747 1.1 bouyer * attach that information to the packet.
3748 1.1 bouyer */
3749 1.1 bouyer if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
3750 1.1 bouyer #if 0
3751 1.1 bouyer struct ether_vlan_header vh;
3752 1.1 bouyer
3753 1.1 bouyer DBPRINT(sc, BNX_VERBOSE_SEND,
3754 1.1 bouyer "%s(): VLAN tag = 0x%04X\n",
3755 1.12 perry __func__,
3756 1.1 bouyer l2fhdr->l2_fhdr_vlan_tag);
3757 1.1 bouyer
3758 1.1 bouyer if (m->m_pkthdr.len < ETHER_HDR_LEN) {
3759 1.1 bouyer m_freem(m);
3760 1.5 bouyer continue;
3761 1.1 bouyer }
3762 1.3 christos m_copydata(m, 0, ETHER_HDR_LEN, (void *)&vh);
3763 1.1 bouyer vh.evl_proto = vh.evl_encap_proto;
3764 1.4 bouyer vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag;
3765 1.1 bouyer vh.evl_encap_proto = htons(ETHERTYPE_VLAN);
3766 1.1 bouyer m_adj(m, ETHER_HDR_LEN);
3767 1.1 bouyer if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL)
3768 1.5 bouyer continue;
3769 1.1 bouyer m->m_pkthdr.len += sizeof(vh);
3770 1.1 bouyer if (m->m_len < sizeof(vh) &&
3771 1.1 bouyer (m = m_pullup(m, sizeof(vh))) == NULL)
3772 1.1 bouyer goto bnx_rx_int_next_rx;
3773 1.1 bouyer m_copyback(m, 0, sizeof(vh), &vh);
3774 1.1 bouyer #else
3775 1.1 bouyer VLAN_INPUT_TAG(ifp, m,
3776 1.8 bouyer l2fhdr->l2_fhdr_vlan_tag,
3777 1.5 bouyer continue);
3778 1.1 bouyer #endif
3779 1.1 bouyer }
3780 1.1 bouyer
3781 1.1 bouyer #if NBPFILTER > 0
3782 1.1 bouyer /*
3783 1.1 bouyer * Handle BPF listeners. Let the BPF
3784 1.1 bouyer * user see the packet.
3785 1.1 bouyer */
3786 1.1 bouyer if (ifp->if_bpf)
3787 1.1 bouyer bpf_mtap(ifp->if_bpf, m);
3788 1.1 bouyer #endif
3789 1.1 bouyer
3790 1.1 bouyer /* Pass the mbuf off to the upper layers. */
3791 1.1 bouyer ifp->if_ipackets++;
3792 1.1 bouyer DBPRINT(sc, BNX_VERBOSE_RECV,
3793 1.12 perry "%s(): Passing received frame up.\n", __func__);
3794 1.1 bouyer (*ifp->if_input)(ifp, m);
3795 1.1 bouyer DBRUNIF(1, sc->rx_mbuf_alloc--);
3796 1.1 bouyer
3797 1.1 bouyer }
3798 1.1 bouyer
3799 1.1 bouyer sw_cons = NEXT_RX_BD(sw_cons);
3800 1.1 bouyer
3801 1.1 bouyer /* Refresh hw_cons to see if there's new work */
3802 1.1 bouyer if (sw_cons == hw_cons) {
3803 1.1 bouyer hw_cons = sc->hw_rx_cons =
3804 1.1 bouyer sblk->status_rx_quick_consumer_index0;
3805 1.1 bouyer if ((hw_cons & USABLE_RX_BD_PER_PAGE) ==
3806 1.1 bouyer USABLE_RX_BD_PER_PAGE)
3807 1.1 bouyer hw_cons++;
3808 1.1 bouyer }
3809 1.1 bouyer
3810 1.1 bouyer /* Prevent speculative reads from getting ahead of
3811 1.1 bouyer * the status block.
3812 1.1 bouyer */
3813 1.1 bouyer bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0,
3814 1.1 bouyer BUS_SPACE_BARRIER_READ);
3815 1.1 bouyer }
3816 1.1 bouyer
3817 1.1 bouyer for (i = 0; i < RX_PAGES; i++)
3818 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag,
3819 1.1 bouyer sc->rx_bd_chain_map[i], 0,
3820 1.1 bouyer sc->rx_bd_chain_map[i]->dm_mapsize,
3821 1.1 bouyer BUS_DMASYNC_PREWRITE);
3822 1.1 bouyer
3823 1.1 bouyer sc->rx_cons = sw_cons;
3824 1.1 bouyer sc->rx_prod = sw_prod;
3825 1.1 bouyer sc->rx_prod_bseq = sw_prod_bseq;
3826 1.1 bouyer
3827 1.1 bouyer REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod);
3828 1.1 bouyer REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3829 1.1 bouyer
3830 1.1 bouyer DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
3831 1.1 bouyer "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
3832 1.12 perry __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
3833 1.1 bouyer }
3834 1.1 bouyer
3835 1.1 bouyer /****************************************************************************/
3836 1.1 bouyer /* Handles transmit completion interrupt events. */
3837 1.1 bouyer /* */
3838 1.1 bouyer /* Returns: */
3839 1.1 bouyer /* Nothing. */
3840 1.1 bouyer /****************************************************************************/
3841 1.1 bouyer void
3842 1.1 bouyer bnx_tx_intr(struct bnx_softc *sc)
3843 1.1 bouyer {
3844 1.1 bouyer struct status_block *sblk = sc->status_block;
3845 1.15 dyoung struct ifnet *ifp = &sc->bnx_ec.ec_if;
3846 1.1 bouyer u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
3847 1.1 bouyer
3848 1.1 bouyer DBRUNIF(1, sc->tx_interrupts++);
3849 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ,
3850 1.1 bouyer BUS_DMASYNC_POSTREAD);
3851 1.1 bouyer
3852 1.1 bouyer /* Get the hardware's view of the TX consumer index. */
3853 1.1 bouyer hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
3854 1.1 bouyer
3855 1.1 bouyer /* Skip to the next entry if this is a chain page pointer. */
3856 1.1 bouyer if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
3857 1.1 bouyer hw_tx_cons++;
3858 1.1 bouyer
3859 1.1 bouyer sw_tx_cons = sc->tx_cons;
3860 1.1 bouyer
3861 1.1 bouyer /* Prevent speculative reads from getting ahead of the status block. */
3862 1.1 bouyer bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0,
3863 1.1 bouyer BUS_SPACE_BARRIER_READ);
3864 1.1 bouyer
3865 1.1 bouyer /* Cycle through any completed TX chain page entries. */
3866 1.1 bouyer while (sw_tx_cons != hw_tx_cons) {
3867 1.1 bouyer #ifdef BNX_DEBUG
3868 1.1 bouyer struct tx_bd *txbd = NULL;
3869 1.1 bouyer #endif
3870 1.1 bouyer sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
3871 1.1 bouyer
3872 1.1 bouyer DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, "
3873 1.1 bouyer "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n",
3874 1.12 perry __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
3875 1.1 bouyer
3876 1.1 bouyer DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
3877 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3878 1.13 dyoung "TX chain consumer out of range! 0x%04X > 0x%04X\n",
3879 1.13 dyoung sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc));
3880 1.1 bouyer
3881 1.1 bouyer DBRUNIF(1, txbd = &sc->tx_bd_chain
3882 1.1 bouyer [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]);
3883 1.1 bouyer
3884 1.1 bouyer DBRUNIF((txbd == NULL),
3885 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3886 1.13 dyoung "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons);
3887 1.1 bouyer bnx_breakpoint(sc));
3888 1.1 bouyer
3889 1.12 perry DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__);
3890 1.1 bouyer bnx_dump_txbd(sc, sw_tx_chain_cons, txbd));
3891 1.1 bouyer
3892 1.1 bouyer /*
3893 1.1 bouyer * Free the associated mbuf. Remember
3894 1.1 bouyer * that only the last tx_bd of a packet
3895 1.1 bouyer * has an mbuf pointer and DMA map.
3896 1.1 bouyer */
3897 1.1 bouyer if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
3898 1.1 bouyer /* Validate that this is the last tx_bd. */
3899 1.1 bouyer DBRUNIF((!(txbd->tx_bd_vlan_tag_flags &
3900 1.1 bouyer TX_BD_FLAGS_END)),
3901 1.13 dyoung aprint_error_dev(sc->bnx_dev,
3902 1.13 dyoung "tx_bd END flag not set but txmbuf == NULL!\n");
3903 1.1 bouyer bnx_breakpoint(sc));
3904 1.1 bouyer
3905 1.1 bouyer DBRUN(BNX_INFO_SEND,
3906 1.1 bouyer aprint_debug("%s: Unloading map/freeing mbuf "
3907 1.1 bouyer "from tx_bd[0x%04X]\n",
3908 1.12 perry __func__, sw_tx_chain_cons));
3909 1.1 bouyer
3910 1.1 bouyer /* Unmap the mbuf. */
3911 1.1 bouyer bus_dmamap_unload(sc->bnx_dmatag,
3912 1.1 bouyer sc->tx_mbuf_map[sw_tx_chain_cons]);
3913 1.1 bouyer
3914 1.1 bouyer /* Free the mbuf. */
3915 1.1 bouyer m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
3916 1.1 bouyer sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
3917 1.1 bouyer DBRUNIF(1, sc->tx_mbuf_alloc--);
3918 1.1 bouyer
3919 1.1 bouyer ifp->if_opackets++;
3920 1.1 bouyer }
3921 1.1 bouyer
3922 1.1 bouyer sc->used_tx_bd--;
3923 1.1 bouyer sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
3924 1.1 bouyer
3925 1.1 bouyer /* Refresh hw_cons to see if there's new work. */
3926 1.1 bouyer hw_tx_cons = sc->hw_tx_cons =
3927 1.1 bouyer sblk->status_tx_quick_consumer_index0;
3928 1.1 bouyer if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) ==
3929 1.1 bouyer USABLE_TX_BD_PER_PAGE)
3930 1.1 bouyer hw_tx_cons++;
3931 1.1 bouyer
3932 1.1 bouyer /* Prevent speculative reads from getting ahead of
3933 1.1 bouyer * the status block.
3934 1.1 bouyer */
3935 1.1 bouyer bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0,
3936 1.1 bouyer BUS_SPACE_BARRIER_READ);
3937 1.1 bouyer }
3938 1.1 bouyer
3939 1.1 bouyer /* Clear the TX timeout timer. */
3940 1.1 bouyer ifp->if_timer = 0;
3941 1.1 bouyer
3942 1.1 bouyer /* Clear the tx hardware queue full flag. */
3943 1.1 bouyer if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) {
3944 1.1 bouyer DBRUNIF((ifp->if_flags & IFF_OACTIVE),
3945 1.13 dyoung aprint_debug_dev(sc->bnx_dev,
3946 1.13 dyoung "TX chain is open for business! Used tx_bd = %d\n",
3947 1.13 dyoung sc->used_tx_bd));
3948 1.1 bouyer ifp->if_flags &= ~IFF_OACTIVE;
3949 1.1 bouyer }
3950 1.1 bouyer
3951 1.1 bouyer sc->tx_cons = sw_tx_cons;
3952 1.1 bouyer }
3953 1.1 bouyer
3954 1.1 bouyer /****************************************************************************/
3955 1.1 bouyer /* Disables interrupt generation. */
3956 1.1 bouyer /* */
3957 1.1 bouyer /* Returns: */
3958 1.1 bouyer /* Nothing. */
3959 1.1 bouyer /****************************************************************************/
3960 1.1 bouyer void
3961 1.1 bouyer bnx_disable_intr(struct bnx_softc *sc)
3962 1.1 bouyer {
3963 1.1 bouyer REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);
3964 1.1 bouyer REG_RD(sc, BNX_PCICFG_INT_ACK_CMD);
3965 1.1 bouyer }
3966 1.1 bouyer
3967 1.1 bouyer /****************************************************************************/
3968 1.1 bouyer /* Enables interrupt generation. */
3969 1.1 bouyer /* */
3970 1.1 bouyer /* Returns: */
3971 1.1 bouyer /* Nothing. */
3972 1.1 bouyer /****************************************************************************/
3973 1.1 bouyer void
3974 1.1 bouyer bnx_enable_intr(struct bnx_softc *sc)
3975 1.1 bouyer {
3976 1.1 bouyer u_int32_t val;
3977 1.1 bouyer
3978 1.1 bouyer REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |
3979 1.1 bouyer BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
3980 1.1 bouyer
3981 1.1 bouyer REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |
3982 1.1 bouyer sc->last_status_idx);
3983 1.1 bouyer
3984 1.1 bouyer val = REG_RD(sc, BNX_HC_COMMAND);
3985 1.1 bouyer REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW);
3986 1.1 bouyer }
3987 1.1 bouyer
3988 1.1 bouyer /****************************************************************************/
3989 1.1 bouyer /* Handles controller initialization. */
3990 1.1 bouyer /* */
3991 1.1 bouyer /****************************************************************************/
3992 1.1 bouyer int
3993 1.1 bouyer bnx_init(struct ifnet *ifp)
3994 1.1 bouyer {
3995 1.1 bouyer struct bnx_softc *sc = ifp->if_softc;
3996 1.1 bouyer u_int32_t ether_mtu;
3997 1.1 bouyer int s, error = 0;
3998 1.1 bouyer
3999 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__);
4000 1.1 bouyer
4001 1.1 bouyer s = splnet();
4002 1.1 bouyer
4003 1.14 dyoung bnx_stop(ifp, 0);
4004 1.1 bouyer
4005 1.1 bouyer if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) {
4006 1.1 bouyer aprint_error("bnx: Controller reset failed!\n");
4007 1.4 bouyer goto bnx_init_exit;
4008 1.1 bouyer }
4009 1.1 bouyer
4010 1.1 bouyer if ((error = bnx_chipinit(sc)) != 0) {
4011 1.1 bouyer aprint_error("bnx: Controller initialization failed!\n");
4012 1.4 bouyer goto bnx_init_exit;
4013 1.1 bouyer }
4014 1.1 bouyer
4015 1.1 bouyer if ((error = bnx_blockinit(sc)) != 0) {
4016 1.1 bouyer aprint_error("bnx: Block initialization failed!\n");
4017 1.4 bouyer goto bnx_init_exit;
4018 1.1 bouyer }
4019 1.1 bouyer
4020 1.1 bouyer /* Calculate and program the Ethernet MRU size. */
4021 1.5 bouyer if (ifp->if_mtu <= ETHERMTU) {
4022 1.5 bouyer ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN;
4023 1.5 bouyer sc->mbuf_alloc_size = MCLBYTES;
4024 1.5 bouyer } else {
4025 1.5 bouyer ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN;
4026 1.5 bouyer sc->mbuf_alloc_size = BNX_MAX_MRU;
4027 1.5 bouyer }
4028 1.5 bouyer
4029 1.1 bouyer
4030 1.1 bouyer DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n",
4031 1.12 perry __func__, ether_mtu);
4032 1.1 bouyer
4033 1.1 bouyer /*
4034 1.1 bouyer * Program the MRU and enable Jumbo frame
4035 1.1 bouyer * support.
4036 1.1 bouyer */
4037 1.1 bouyer REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu |
4038 1.1 bouyer BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4039 1.1 bouyer
4040 1.1 bouyer /* Calculate the RX Ethernet frame size for rx_bd's. */
4041 1.1 bouyer sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4042 1.1 bouyer
4043 1.1 bouyer DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4044 1.12 perry "max_frame_size = %d\n", __func__, (int)MCLBYTES,
4045 1.1 bouyer sc->mbuf_alloc_size, sc->max_frame_size);
4046 1.1 bouyer
4047 1.1 bouyer /* Program appropriate promiscuous/multicast filtering. */
4048 1.1 bouyer bnx_set_rx_mode(sc);
4049 1.1 bouyer
4050 1.1 bouyer /* Init RX buffer descriptor chain. */
4051 1.1 bouyer bnx_init_rx_chain(sc);
4052 1.1 bouyer
4053 1.1 bouyer /* Init TX buffer descriptor chain. */
4054 1.1 bouyer bnx_init_tx_chain(sc);
4055 1.1 bouyer
4056 1.1 bouyer /* Enable host interrupts. */
4057 1.1 bouyer bnx_enable_intr(sc);
4058 1.1 bouyer
4059 1.16 dyoung if ((error = ether_mediachange(ifp)) != 0)
4060 1.14 dyoung goto bnx_init_exit;
4061 1.1 bouyer
4062 1.1 bouyer ifp->if_flags |= IFF_RUNNING;
4063 1.1 bouyer ifp->if_flags &= ~IFF_OACTIVE;
4064 1.1 bouyer
4065 1.1 bouyer callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc);
4066 1.1 bouyer
4067 1.4 bouyer bnx_init_exit:
4068 1.12 perry DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__);
4069 1.1 bouyer
4070 1.1 bouyer splx(s);
4071 1.1 bouyer
4072 1.1 bouyer return(error);
4073 1.1 bouyer }
4074 1.1 bouyer
4075 1.1 bouyer /****************************************************************************/
4076 1.1 bouyer /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4077 1.1 bouyer /* memory visible to the controller. */
4078 1.1 bouyer /* */
4079 1.1 bouyer /* Returns: */
4080 1.1 bouyer /* 0 for success, positive value for failure. */
4081 1.1 bouyer /****************************************************************************/
4082 1.1 bouyer int
4083 1.4 bouyer bnx_tx_encap(struct bnx_softc *sc, struct mbuf **m_head)
4084 1.1 bouyer {
4085 1.1 bouyer bus_dmamap_t map;
4086 1.4 bouyer struct tx_bd *txbd = NULL;
4087 1.4 bouyer struct mbuf *m0;
4088 1.4 bouyer u_int16_t vlan_tag = 0, flags = 0;
4089 1.4 bouyer u_int16_t chain_prod, prod;
4090 1.4 bouyer #ifdef BNX_DEBUG
4091 1.4 bouyer u_int16_t debug_prod;
4092 1.4 bouyer #endif
4093 1.4 bouyer u_int32_t addr, prod_bseq;
4094 1.4 bouyer int i, error, rc = 0;
4095 1.1 bouyer struct m_tag *mtag;
4096 1.1 bouyer
4097 1.4 bouyer m0 = *m_head;
4098 1.4 bouyer
4099 1.1 bouyer /* Transfer any checksum offload flags to the bd. */
4100 1.4 bouyer if (m0->m_pkthdr.csum_flags) {
4101 1.4 bouyer if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4)
4102 1.4 bouyer flags |= TX_BD_FLAGS_IP_CKSUM;
4103 1.4 bouyer if (m0->m_pkthdr.csum_flags &
4104 1.1 bouyer (M_CSUM_TCPv4 | M_CSUM_UDPv4))
4105 1.4 bouyer flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4106 1.1 bouyer }
4107 1.1 bouyer
4108 1.1 bouyer /* Transfer any VLAN tags to the bd. */
4109 1.15 dyoung mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m0);
4110 1.4 bouyer if (mtag != NULL) {
4111 1.4 bouyer flags |= TX_BD_FLAGS_VLAN_TAG;
4112 1.4 bouyer vlan_tag = VLAN_TAG_VALUE(mtag);
4113 1.4 bouyer }
4114 1.1 bouyer
4115 1.1 bouyer /* Map the mbuf into DMAable memory. */
4116 1.4 bouyer prod = sc->tx_prod;
4117 1.4 bouyer chain_prod = TX_CHAIN_IDX(prod);
4118 1.4 bouyer map = sc->tx_mbuf_map[chain_prod];
4119 1.4 bouyer
4120 1.1 bouyer /* Map the mbuf into our DMA address space. */
4121 1.4 bouyer error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m0, BUS_DMA_NOWAIT);
4122 1.4 bouyer if (error != 0) {
4123 1.13 dyoung aprint_error_dev(sc->bnx_dev,
4124 1.13 dyoung "Error mapping mbuf into TX chain!\n");
4125 1.4 bouyer m_freem(m0);
4126 1.4 bouyer *m_head = NULL;
4127 1.4 bouyer return (error);
4128 1.1 bouyer }
4129 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize,
4130 1.1 bouyer BUS_DMASYNC_PREWRITE);
4131 1.4 bouyer /*
4132 1.4 bouyer * The chip seems to require that at least 16 descriptors be kept
4133 1.4 bouyer * empty at all times. Make sure we honor that.
4134 1.4 bouyer * XXX Would it be faster to assume worst case scenario for
4135 1.4 bouyer * map->dm_nsegs and do this calculation higher up?
4136 1.4 bouyer */
4137 1.4 bouyer if (map->dm_nsegs > (USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE)) {
4138 1.4 bouyer bus_dmamap_unload(sc->bnx_dmatag, map);
4139 1.4 bouyer return (ENOBUFS);
4140 1.4 bouyer }
4141 1.4 bouyer
4142 1.4 bouyer /* prod points to an empty tx_bd at this point. */
4143 1.4 bouyer prod_bseq = sc->tx_prod_bseq;
4144 1.4 bouyer #ifdef BNX_DEBUG
4145 1.4 bouyer debug_prod = chain_prod;
4146 1.4 bouyer #endif
4147 1.4 bouyer DBPRINT(sc, BNX_INFO_SEND,
4148 1.4 bouyer "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4149 1.4 bouyer "prod_bseq = 0x%08X\n",
4150 1.12 perry __func__, *prod, chain_prod, prod_bseq);
4151 1.1 bouyer
4152 1.1 bouyer /*
4153 1.4 bouyer * Cycle through each mbuf segment that makes up
4154 1.4 bouyer * the outgoing frame, gathering the mapping info
4155 1.4 bouyer * for that segment and creating a tx_bd for the
4156 1.4 bouyer * mbuf.
4157 1.4 bouyer */
4158 1.4 bouyer for (i = 0; i < map->dm_nsegs ; i++) {
4159 1.4 bouyer chain_prod = TX_CHAIN_IDX(prod);
4160 1.4 bouyer txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4161 1.4 bouyer
4162 1.4 bouyer addr = (u_int32_t)(map->dm_segs[i].ds_addr);
4163 1.4 bouyer txbd->tx_bd_haddr_lo = htole32(addr);
4164 1.4 bouyer addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32);
4165 1.4 bouyer txbd->tx_bd_haddr_hi = htole32(addr);
4166 1.4 bouyer txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len);
4167 1.4 bouyer txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4168 1.4 bouyer txbd->tx_bd_flags = htole16(flags);
4169 1.4 bouyer prod_bseq += map->dm_segs[i].ds_len;
4170 1.4 bouyer if (i == 0)
4171 1.4 bouyer txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4172 1.4 bouyer prod = NEXT_TX_BD(prod);
4173 1.4 bouyer }
4174 1.4 bouyer /* Set the END flag on the last TX buffer descriptor. */
4175 1.4 bouyer txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4176 1.4 bouyer
4177 1.4 bouyer DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg));
4178 1.4 bouyer
4179 1.4 bouyer DBPRINT(sc, BNX_INFO_SEND,
4180 1.4 bouyer "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4181 1.4 bouyer "prod_bseq = 0x%08X\n",
4182 1.12 perry __func__, prod, chain_prod, prod_bseq);
4183 1.4 bouyer
4184 1.4 bouyer /*
4185 1.4 bouyer * Ensure that the mbuf pointer for this
4186 1.4 bouyer * transmission is placed at the array
4187 1.4 bouyer * index of the last descriptor in this
4188 1.4 bouyer * chain. This is done because a single
4189 1.4 bouyer * map is used for all segments of the mbuf
4190 1.4 bouyer * and we don't want to unload the map before
4191 1.4 bouyer * all of the segments have been freed.
4192 1.1 bouyer */
4193 1.4 bouyer sc->tx_mbuf_ptr[chain_prod] = m0;
4194 1.4 bouyer sc->used_tx_bd += map->dm_nsegs;
4195 1.1 bouyer
4196 1.1 bouyer DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4197 1.1 bouyer sc->tx_hi_watermark = sc->used_tx_bd);
4198 1.1 bouyer
4199 1.1 bouyer DBRUNIF(1, sc->tx_mbuf_alloc++);
4200 1.1 bouyer
4201 1.4 bouyer DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod,
4202 1.1 bouyer map_arg.maxsegs));
4203 1.1 bouyer
4204 1.4 bouyer /* prod points to the next free tx_bd at this point. */
4205 1.4 bouyer sc->tx_prod = prod;
4206 1.4 bouyer sc->tx_prod_bseq = prod_bseq;
4207 1.1 bouyer
4208 1.4 bouyer return (rc);
4209 1.1 bouyer }
4210 1.1 bouyer
4211 1.1 bouyer /****************************************************************************/
4212 1.1 bouyer /* Main transmit routine. */
4213 1.1 bouyer /* */
4214 1.1 bouyer /* Returns: */
4215 1.1 bouyer /* Nothing. */
4216 1.1 bouyer /****************************************************************************/
4217 1.1 bouyer void
4218 1.1 bouyer bnx_start(struct ifnet *ifp)
4219 1.1 bouyer {
4220 1.1 bouyer struct bnx_softc *sc = ifp->if_softc;
4221 1.1 bouyer struct mbuf *m_head = NULL;
4222 1.1 bouyer int count = 0;
4223 1.1 bouyer u_int16_t tx_prod, tx_chain_prod;
4224 1.1 bouyer
4225 1.1 bouyer /* If there's no link or the transmit queue is empty then just exit. */
4226 1.16 dyoung if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) {
4227 1.1 bouyer DBPRINT(sc, BNX_INFO_SEND,
4228 1.16 dyoung "%s(): output active or device not running.\n", __func__);
4229 1.4 bouyer goto bnx_start_exit;
4230 1.1 bouyer }
4231 1.1 bouyer
4232 1.1 bouyer /* prod points to the next free tx_bd. */
4233 1.1 bouyer tx_prod = sc->tx_prod;
4234 1.1 bouyer tx_chain_prod = TX_CHAIN_IDX(tx_prod);
4235 1.1 bouyer
4236 1.1 bouyer DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, "
4237 1.1 bouyer "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n",
4238 1.12 perry __func__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
4239 1.1 bouyer
4240 1.4 bouyer /*
4241 1.4 bouyer * Keep adding entries while there is space in the ring. We keep
4242 1.4 bouyer * BNX_TX_SLACK_SPACE entries unused at all times.
4243 1.4 bouyer */
4244 1.4 bouyer while (sc->used_tx_bd < USABLE_TX_BD - BNX_TX_SLACK_SPACE) {
4245 1.1 bouyer /* Check for any frames to send. */
4246 1.1 bouyer IFQ_POLL(&ifp->if_snd, m_head);
4247 1.1 bouyer if (m_head == NULL)
4248 1.1 bouyer break;
4249 1.1 bouyer
4250 1.1 bouyer /*
4251 1.1 bouyer * Pack the data into the transmit ring. If we
4252 1.4 bouyer * don't have room, set the OACTIVE flag to wait
4253 1.4 bouyer * for the NIC to drain the chain.
4254 1.1 bouyer */
4255 1.4 bouyer if (bnx_tx_encap(sc, &m_head)) {
4256 1.1 bouyer ifp->if_flags |= IFF_OACTIVE;
4257 1.1 bouyer DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for "
4258 1.1 bouyer "business! Total tx_bd used = %d\n",
4259 1.1 bouyer sc->used_tx_bd);
4260 1.1 bouyer break;
4261 1.1 bouyer }
4262 1.1 bouyer
4263 1.1 bouyer IFQ_DEQUEUE(&ifp->if_snd, m_head);
4264 1.1 bouyer count++;
4265 1.1 bouyer
4266 1.1 bouyer #if NBPFILTER > 0
4267 1.1 bouyer /* Send a copy of the frame to any BPF listeners. */
4268 1.1 bouyer if (ifp->if_bpf)
4269 1.1 bouyer bpf_mtap(ifp->if_bpf, m_head);
4270 1.1 bouyer #endif
4271 1.1 bouyer }
4272 1.1 bouyer
4273 1.1 bouyer if (count == 0) {
4274 1.1 bouyer /* no packets were dequeued */
4275 1.1 bouyer DBPRINT(sc, BNX_VERBOSE_SEND,
4276 1.12 perry "%s(): No packets were dequeued\n", __func__);
4277 1.4 bouyer goto bnx_start_exit;
4278 1.1 bouyer }
4279 1.1 bouyer
4280 1.1 bouyer /* Update the driver's counters. */
4281 1.4 bouyer tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod);
4282 1.1 bouyer
4283 1.1 bouyer DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod "
4284 1.12 perry "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, tx_prod,
4285 1.4 bouyer tx_chain_prod, sc->tx_prod_bseq);
4286 1.1 bouyer
4287 1.1 bouyer /* Start the transmit. */
4288 1.1 bouyer REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4289 1.1 bouyer REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4290 1.1 bouyer
4291 1.1 bouyer /* Set the tx timeout. */
4292 1.1 bouyer ifp->if_timer = BNX_TX_TIMEOUT;
4293 1.1 bouyer
4294 1.4 bouyer bnx_start_exit:
4295 1.1 bouyer return;
4296 1.1 bouyer }
4297 1.1 bouyer
4298 1.1 bouyer /****************************************************************************/
4299 1.1 bouyer /* Handles any IOCTL calls from the operating system. */
4300 1.1 bouyer /* */
4301 1.1 bouyer /* Returns: */
4302 1.1 bouyer /* 0 for success, positive value for failure. */
4303 1.1 bouyer /****************************************************************************/
4304 1.1 bouyer int
4305 1.3 christos bnx_ioctl(struct ifnet *ifp, u_long command, void *data)
4306 1.1 bouyer {
4307 1.1 bouyer struct bnx_softc *sc = ifp->if_softc;
4308 1.1 bouyer struct ifreq *ifr = (struct ifreq *) data;
4309 1.1 bouyer struct mii_data *mii;
4310 1.1 bouyer int s, error = 0;
4311 1.1 bouyer
4312 1.1 bouyer s = splnet();
4313 1.1 bouyer
4314 1.1 bouyer switch (command) {
4315 1.1 bouyer case SIOCSIFFLAGS:
4316 1.1 bouyer if (ifp->if_flags & IFF_UP) {
4317 1.1 bouyer if ((ifp->if_flags & IFF_RUNNING) &&
4318 1.1 bouyer ((ifp->if_flags ^ sc->bnx_if_flags) &
4319 1.1 bouyer (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
4320 1.1 bouyer bnx_set_rx_mode(sc);
4321 1.1 bouyer } else if (!(ifp->if_flags & IFF_RUNNING))
4322 1.1 bouyer bnx_init(ifp);
4323 1.1 bouyer
4324 1.4 bouyer } else if (ifp->if_flags & IFF_RUNNING)
4325 1.14 dyoung bnx_stop(ifp, 1);
4326 1.1 bouyer
4327 1.1 bouyer sc->bnx_if_flags = ifp->if_flags;
4328 1.1 bouyer break;
4329 1.1 bouyer
4330 1.1 bouyer case SIOCSIFMEDIA:
4331 1.1 bouyer case SIOCGIFMEDIA:
4332 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n",
4333 1.1 bouyer sc->bnx_phy_flags);
4334 1.1 bouyer
4335 1.1 bouyer if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG)
4336 1.1 bouyer error = ifmedia_ioctl(ifp, ifr,
4337 1.1 bouyer &sc->bnx_ifmedia, command);
4338 1.1 bouyer else {
4339 1.1 bouyer mii = &sc->bnx_mii;
4340 1.1 bouyer error = ifmedia_ioctl(ifp, ifr,
4341 1.1 bouyer &mii->mii_media, command);
4342 1.1 bouyer }
4343 1.1 bouyer break;
4344 1.1 bouyer
4345 1.1 bouyer default:
4346 1.18 dyoung if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
4347 1.11 dyoung break;
4348 1.18 dyoung
4349 1.11 dyoung error = 0;
4350 1.18 dyoung
4351 1.18 dyoung if (command != SIOCADDMULTI && command && SIOCDELMULTI)
4352 1.18 dyoung ;
4353 1.18 dyoung else if (ifp->if_flags & IFF_RUNNING) {
4354 1.11 dyoung /* reload packet filter if running */
4355 1.18 dyoung bnx_set_rx_mode(sc);
4356 1.1 bouyer }
4357 1.1 bouyer break;
4358 1.1 bouyer }
4359 1.1 bouyer
4360 1.1 bouyer splx(s);
4361 1.1 bouyer
4362 1.1 bouyer return (error);
4363 1.1 bouyer }
4364 1.1 bouyer
4365 1.1 bouyer /****************************************************************************/
4366 1.1 bouyer /* Transmit timeout handler. */
4367 1.1 bouyer /* */
4368 1.1 bouyer /* Returns: */
4369 1.1 bouyer /* Nothing. */
4370 1.1 bouyer /****************************************************************************/
4371 1.1 bouyer void
4372 1.1 bouyer bnx_watchdog(struct ifnet *ifp)
4373 1.1 bouyer {
4374 1.1 bouyer struct bnx_softc *sc = ifp->if_softc;
4375 1.1 bouyer
4376 1.1 bouyer DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc);
4377 1.1 bouyer bnx_dump_status_block(sc));
4378 1.1 bouyer
4379 1.13 dyoung aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n");
4380 1.1 bouyer
4381 1.1 bouyer /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */
4382 1.1 bouyer
4383 1.1 bouyer bnx_init(ifp);
4384 1.1 bouyer
4385 1.1 bouyer ifp->if_oerrors++;
4386 1.1 bouyer }
4387 1.1 bouyer
4388 1.1 bouyer /*
4389 1.1 bouyer * Interrupt handler.
4390 1.1 bouyer */
4391 1.1 bouyer /****************************************************************************/
4392 1.1 bouyer /* Main interrupt entry point. Verifies that the controller generated the */
4393 1.1 bouyer /* interrupt and then calls a separate routine for handle the various */
4394 1.1 bouyer /* interrupt causes (PHY, TX, RX). */
4395 1.1 bouyer /* */
4396 1.1 bouyer /* Returns: */
4397 1.1 bouyer /* 0 for success, positive value for failure. */
4398 1.1 bouyer /****************************************************************************/
4399 1.1 bouyer int
4400 1.1 bouyer bnx_intr(void *xsc)
4401 1.1 bouyer {
4402 1.1 bouyer struct bnx_softc *sc;
4403 1.1 bouyer struct ifnet *ifp;
4404 1.1 bouyer u_int32_t status_attn_bits;
4405 1.14 dyoung const struct status_block *sblk;
4406 1.1 bouyer
4407 1.1 bouyer sc = xsc;
4408 1.13 dyoung if (!device_is_active(sc->bnx_dev))
4409 1.13 dyoung return 0;
4410 1.13 dyoung
4411 1.15 dyoung ifp = &sc->bnx_ec.ec_if;
4412 1.1 bouyer
4413 1.1 bouyer DBRUNIF(1, sc->interrupts_generated++);
4414 1.1 bouyer
4415 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0,
4416 1.1 bouyer sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
4417 1.1 bouyer
4418 1.1 bouyer /*
4419 1.1 bouyer * If the hardware status block index
4420 1.1 bouyer * matches the last value read by the
4421 1.1 bouyer * driver and we haven't asserted our
4422 1.1 bouyer * interrupt then there's nothing to do.
4423 1.1 bouyer */
4424 1.1 bouyer if ((sc->status_block->status_idx == sc->last_status_idx) &&
4425 1.1 bouyer (REG_RD(sc, BNX_PCICFG_MISC_STATUS) &
4426 1.1 bouyer BNX_PCICFG_MISC_STATUS_INTA_VALUE))
4427 1.1 bouyer return (0);
4428 1.1 bouyer
4429 1.1 bouyer /* Ack the interrupt and stop others from occuring. */
4430 1.1 bouyer REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
4431 1.1 bouyer BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
4432 1.1 bouyer BNX_PCICFG_INT_ACK_CMD_MASK_INT);
4433 1.1 bouyer
4434 1.1 bouyer /* Keep processing data as long as there is work to do. */
4435 1.1 bouyer for (;;) {
4436 1.14 dyoung sblk = sc->status_block;
4437 1.14 dyoung status_attn_bits = sblk->status_attn_bits;
4438 1.1 bouyer
4439 1.1 bouyer DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention),
4440 1.1 bouyer aprint_debug("Simulating unexpected status attention bit set.");
4441 1.1 bouyer status_attn_bits = status_attn_bits |
4442 1.1 bouyer STATUS_ATTN_BITS_PARITY_ERROR);
4443 1.1 bouyer
4444 1.1 bouyer /* Was it a link change interrupt? */
4445 1.1 bouyer if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4446 1.14 dyoung (sblk->status_attn_bits_ack &
4447 1.1 bouyer STATUS_ATTN_BITS_LINK_STATE))
4448 1.1 bouyer bnx_phy_intr(sc);
4449 1.1 bouyer
4450 1.1 bouyer /* If any other attention is asserted then the chip is toast. */
4451 1.1 bouyer if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4452 1.14 dyoung (sblk->status_attn_bits_ack &
4453 1.1 bouyer ~STATUS_ATTN_BITS_LINK_STATE))) {
4454 1.1 bouyer DBRUN(1, sc->unexpected_attentions++);
4455 1.1 bouyer
4456 1.13 dyoung aprint_error_dev(sc->bnx_dev,
4457 1.13 dyoung "Fatal attention detected: 0x%08X\n",
4458 1.14 dyoung sblk->status_attn_bits);
4459 1.1 bouyer
4460 1.1 bouyer DBRUN(BNX_FATAL,
4461 1.1 bouyer if (bnx_debug_unexpected_attention == 0)
4462 1.1 bouyer bnx_breakpoint(sc));
4463 1.1 bouyer
4464 1.1 bouyer bnx_init(ifp);
4465 1.1 bouyer return (1);
4466 1.1 bouyer }
4467 1.1 bouyer
4468 1.1 bouyer /* Check for any completed RX frames. */
4469 1.14 dyoung if (sblk->status_rx_quick_consumer_index0 !=
4470 1.1 bouyer sc->hw_rx_cons)
4471 1.1 bouyer bnx_rx_intr(sc);
4472 1.1 bouyer
4473 1.1 bouyer /* Check for any completed TX frames. */
4474 1.14 dyoung if (sblk->status_tx_quick_consumer_index0 !=
4475 1.1 bouyer sc->hw_tx_cons)
4476 1.1 bouyer bnx_tx_intr(sc);
4477 1.1 bouyer
4478 1.1 bouyer /* Save the status block index value for use during the
4479 1.1 bouyer * next interrupt.
4480 1.1 bouyer */
4481 1.14 dyoung sc->last_status_idx = sblk->status_idx;
4482 1.1 bouyer
4483 1.1 bouyer /* Prevent speculative reads from getting ahead of the
4484 1.1 bouyer * status block.
4485 1.1 bouyer */
4486 1.1 bouyer bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0,
4487 1.1 bouyer BUS_SPACE_BARRIER_READ);
4488 1.1 bouyer
4489 1.1 bouyer /* If there's no work left then exit the isr. */
4490 1.14 dyoung if ((sblk->status_rx_quick_consumer_index0 ==
4491 1.1 bouyer sc->hw_rx_cons) &&
4492 1.14 dyoung (sblk->status_tx_quick_consumer_index0 ==
4493 1.1 bouyer sc->hw_tx_cons))
4494 1.1 bouyer break;
4495 1.1 bouyer }
4496 1.1 bouyer
4497 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0,
4498 1.1 bouyer sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
4499 1.1 bouyer
4500 1.1 bouyer /* Re-enable interrupts. */
4501 1.1 bouyer REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
4502 1.1 bouyer BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx |
4503 1.4 bouyer BNX_PCICFG_INT_ACK_CMD_MASK_INT);
4504 1.1 bouyer REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
4505 1.1 bouyer BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4506 1.1 bouyer
4507 1.1 bouyer /* Handle any frames that arrived while handling the interrupt. */
4508 1.16 dyoung if (!IFQ_IS_EMPTY(&ifp->if_snd))
4509 1.1 bouyer bnx_start(ifp);
4510 1.1 bouyer
4511 1.1 bouyer return (1);
4512 1.1 bouyer }
4513 1.1 bouyer
4514 1.1 bouyer /****************************************************************************/
4515 1.1 bouyer /* Programs the various packet receive modes (broadcast and multicast). */
4516 1.1 bouyer /* */
4517 1.1 bouyer /* Returns: */
4518 1.1 bouyer /* Nothing. */
4519 1.1 bouyer /****************************************************************************/
4520 1.1 bouyer void
4521 1.1 bouyer bnx_set_rx_mode(struct bnx_softc *sc)
4522 1.1 bouyer {
4523 1.15 dyoung struct ethercom *ec = &sc->bnx_ec;
4524 1.1 bouyer struct ifnet *ifp = &ec->ec_if;
4525 1.1 bouyer struct ether_multi *enm;
4526 1.1 bouyer struct ether_multistep step;
4527 1.4 bouyer u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
4528 1.1 bouyer u_int32_t rx_mode, sort_mode;
4529 1.1 bouyer int h, i;
4530 1.1 bouyer
4531 1.1 bouyer /* Initialize receive mode default settings. */
4532 1.1 bouyer rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS |
4533 1.1 bouyer BNX_EMAC_RX_MODE_KEEP_VLAN_TAG);
4534 1.1 bouyer sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN;
4535 1.1 bouyer
4536 1.1 bouyer /*
4537 1.1 bouyer * ASF/IPMI/UMP firmware requires that VLAN tag stripping
4538 1.1 bouyer * be enbled.
4539 1.1 bouyer */
4540 1.1 bouyer if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG))
4541 1.1 bouyer rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG;
4542 1.1 bouyer
4543 1.1 bouyer /*
4544 1.1 bouyer * Check for promiscuous, all multicast, or selected
4545 1.1 bouyer * multicast address filtering.
4546 1.1 bouyer */
4547 1.1 bouyer if (ifp->if_flags & IFF_PROMISC) {
4548 1.1 bouyer DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n");
4549 1.1 bouyer
4550 1.1 bouyer /* Enable promiscuous mode. */
4551 1.1 bouyer rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS;
4552 1.1 bouyer sort_mode |= BNX_RPM_SORT_USER0_PROM_EN;
4553 1.1 bouyer } else if (ifp->if_flags & IFF_ALLMULTI) {
4554 1.1 bouyer allmulti:
4555 1.1 bouyer DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n");
4556 1.1 bouyer
4557 1.1 bouyer /* Enable all multicast addresses. */
4558 1.1 bouyer for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
4559 1.1 bouyer REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),
4560 1.1 bouyer 0xffffffff);
4561 1.1 bouyer sort_mode |= BNX_RPM_SORT_USER0_MC_EN;
4562 1.1 bouyer } else {
4563 1.1 bouyer /* Accept one or more multicast(s). */
4564 1.1 bouyer DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n");
4565 1.1 bouyer
4566 1.1 bouyer ETHER_FIRST_MULTI(step, ec, enm);
4567 1.1 bouyer while (enm != NULL) {
4568 1.1 bouyer if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
4569 1.1 bouyer ETHER_ADDR_LEN)) {
4570 1.1 bouyer ifp->if_flags |= IFF_ALLMULTI;
4571 1.1 bouyer goto allmulti;
4572 1.1 bouyer }
4573 1.1 bouyer h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) &
4574 1.4 bouyer 0xFF;
4575 1.4 bouyer hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
4576 1.1 bouyer ETHER_NEXT_MULTI(step, enm);
4577 1.1 bouyer }
4578 1.1 bouyer
4579 1.4 bouyer for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
4580 1.1 bouyer REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),
4581 1.1 bouyer hashes[i]);
4582 1.1 bouyer
4583 1.1 bouyer sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN;
4584 1.1 bouyer }
4585 1.1 bouyer
4586 1.1 bouyer /* Only make changes if the recive mode has actually changed. */
4587 1.1 bouyer if (rx_mode != sc->rx_mode) {
4588 1.1 bouyer DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n",
4589 1.1 bouyer rx_mode);
4590 1.1 bouyer
4591 1.1 bouyer sc->rx_mode = rx_mode;
4592 1.1 bouyer REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode);
4593 1.1 bouyer }
4594 1.1 bouyer
4595 1.1 bouyer /* Disable and clear the exisitng sort before enabling a new sort. */
4596 1.1 bouyer REG_WR(sc, BNX_RPM_SORT_USER0, 0x0);
4597 1.1 bouyer REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode);
4598 1.1 bouyer REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA);
4599 1.1 bouyer }
4600 1.1 bouyer
4601 1.1 bouyer /****************************************************************************/
4602 1.1 bouyer /* Called periodically to updates statistics from the controllers */
4603 1.1 bouyer /* statistics block. */
4604 1.1 bouyer /* */
4605 1.1 bouyer /* Returns: */
4606 1.1 bouyer /* Nothing. */
4607 1.1 bouyer /****************************************************************************/
4608 1.1 bouyer void
4609 1.1 bouyer bnx_stats_update(struct bnx_softc *sc)
4610 1.1 bouyer {
4611 1.15 dyoung struct ifnet *ifp = &sc->bnx_ec.ec_if;
4612 1.1 bouyer struct statistics_block *stats;
4613 1.1 bouyer
4614 1.12 perry DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__);
4615 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ,
4616 1.1 bouyer BUS_DMASYNC_POSTREAD);
4617 1.1 bouyer
4618 1.1 bouyer stats = (struct statistics_block *)sc->stats_block;
4619 1.1 bouyer
4620 1.1 bouyer /*
4621 1.1 bouyer * Update the interface statistics from the
4622 1.1 bouyer * hardware statistics.
4623 1.1 bouyer */
4624 1.1 bouyer ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions;
4625 1.1 bouyer
4626 1.1 bouyer ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts +
4627 1.1 bouyer (u_long)stats->stat_EtherStatsOverrsizePkts +
4628 1.1 bouyer (u_long)stats->stat_IfInMBUFDiscards +
4629 1.1 bouyer (u_long)stats->stat_Dot3StatsAlignmentErrors +
4630 1.1 bouyer (u_long)stats->stat_Dot3StatsFCSErrors;
4631 1.1 bouyer
4632 1.1 bouyer ifp->if_oerrors = (u_long)
4633 1.1 bouyer stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
4634 1.1 bouyer (u_long)stats->stat_Dot3StatsExcessiveCollisions +
4635 1.1 bouyer (u_long)stats->stat_Dot3StatsLateCollisions;
4636 1.1 bouyer
4637 1.1 bouyer /*
4638 1.1 bouyer * Certain controllers don't report
4639 1.1 bouyer * carrier sense errors correctly.
4640 1.1 bouyer * See errata E11_5708CA0_1165.
4641 1.1 bouyer */
4642 1.1 bouyer if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) &&
4643 1.1 bouyer !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0))
4644 1.1 bouyer ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
4645 1.1 bouyer
4646 1.1 bouyer /*
4647 1.1 bouyer * Update the sysctl statistics from the
4648 1.1 bouyer * hardware statistics.
4649 1.1 bouyer */
4650 1.1 bouyer sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) +
4651 1.1 bouyer (u_int64_t) stats->stat_IfHCInOctets_lo;
4652 1.1 bouyer
4653 1.1 bouyer sc->stat_IfHCInBadOctets =
4654 1.1 bouyer ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) +
4655 1.1 bouyer (u_int64_t) stats->stat_IfHCInBadOctets_lo;
4656 1.1 bouyer
4657 1.1 bouyer sc->stat_IfHCOutOctets =
4658 1.1 bouyer ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) +
4659 1.1 bouyer (u_int64_t) stats->stat_IfHCOutOctets_lo;
4660 1.1 bouyer
4661 1.1 bouyer sc->stat_IfHCOutBadOctets =
4662 1.1 bouyer ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) +
4663 1.1 bouyer (u_int64_t) stats->stat_IfHCOutBadOctets_lo;
4664 1.1 bouyer
4665 1.1 bouyer sc->stat_IfHCInUcastPkts =
4666 1.1 bouyer ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) +
4667 1.1 bouyer (u_int64_t) stats->stat_IfHCInUcastPkts_lo;
4668 1.1 bouyer
4669 1.1 bouyer sc->stat_IfHCInMulticastPkts =
4670 1.1 bouyer ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) +
4671 1.1 bouyer (u_int64_t) stats->stat_IfHCInMulticastPkts_lo;
4672 1.1 bouyer
4673 1.1 bouyer sc->stat_IfHCInBroadcastPkts =
4674 1.1 bouyer ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) +
4675 1.1 bouyer (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo;
4676 1.1 bouyer
4677 1.1 bouyer sc->stat_IfHCOutUcastPkts =
4678 1.1 bouyer ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) +
4679 1.1 bouyer (u_int64_t) stats->stat_IfHCOutUcastPkts_lo;
4680 1.1 bouyer
4681 1.1 bouyer sc->stat_IfHCOutMulticastPkts =
4682 1.1 bouyer ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) +
4683 1.1 bouyer (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo;
4684 1.1 bouyer
4685 1.1 bouyer sc->stat_IfHCOutBroadcastPkts =
4686 1.1 bouyer ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
4687 1.1 bouyer (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo;
4688 1.1 bouyer
4689 1.1 bouyer sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
4690 1.1 bouyer stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
4691 1.1 bouyer
4692 1.1 bouyer sc->stat_Dot3StatsCarrierSenseErrors =
4693 1.1 bouyer stats->stat_Dot3StatsCarrierSenseErrors;
4694 1.1 bouyer
4695 1.1 bouyer sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors;
4696 1.1 bouyer
4697 1.1 bouyer sc->stat_Dot3StatsAlignmentErrors =
4698 1.1 bouyer stats->stat_Dot3StatsAlignmentErrors;
4699 1.1 bouyer
4700 1.1 bouyer sc->stat_Dot3StatsSingleCollisionFrames =
4701 1.1 bouyer stats->stat_Dot3StatsSingleCollisionFrames;
4702 1.1 bouyer
4703 1.1 bouyer sc->stat_Dot3StatsMultipleCollisionFrames =
4704 1.1 bouyer stats->stat_Dot3StatsMultipleCollisionFrames;
4705 1.1 bouyer
4706 1.1 bouyer sc->stat_Dot3StatsDeferredTransmissions =
4707 1.1 bouyer stats->stat_Dot3StatsDeferredTransmissions;
4708 1.1 bouyer
4709 1.1 bouyer sc->stat_Dot3StatsExcessiveCollisions =
4710 1.1 bouyer stats->stat_Dot3StatsExcessiveCollisions;
4711 1.1 bouyer
4712 1.1 bouyer sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions;
4713 1.1 bouyer
4714 1.1 bouyer sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions;
4715 1.1 bouyer
4716 1.1 bouyer sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments;
4717 1.1 bouyer
4718 1.1 bouyer sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers;
4719 1.1 bouyer
4720 1.1 bouyer sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts;
4721 1.1 bouyer
4722 1.1 bouyer sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts;
4723 1.1 bouyer
4724 1.1 bouyer sc->stat_EtherStatsPktsRx64Octets =
4725 1.1 bouyer stats->stat_EtherStatsPktsRx64Octets;
4726 1.1 bouyer
4727 1.1 bouyer sc->stat_EtherStatsPktsRx65Octetsto127Octets =
4728 1.1 bouyer stats->stat_EtherStatsPktsRx65Octetsto127Octets;
4729 1.1 bouyer
4730 1.1 bouyer sc->stat_EtherStatsPktsRx128Octetsto255Octets =
4731 1.1 bouyer stats->stat_EtherStatsPktsRx128Octetsto255Octets;
4732 1.1 bouyer
4733 1.1 bouyer sc->stat_EtherStatsPktsRx256Octetsto511Octets =
4734 1.1 bouyer stats->stat_EtherStatsPktsRx256Octetsto511Octets;
4735 1.1 bouyer
4736 1.1 bouyer sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
4737 1.1 bouyer stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
4738 1.1 bouyer
4739 1.1 bouyer sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
4740 1.1 bouyer stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
4741 1.1 bouyer
4742 1.1 bouyer sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
4743 1.1 bouyer stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
4744 1.1 bouyer
4745 1.1 bouyer sc->stat_EtherStatsPktsTx64Octets =
4746 1.1 bouyer stats->stat_EtherStatsPktsTx64Octets;
4747 1.1 bouyer
4748 1.1 bouyer sc->stat_EtherStatsPktsTx65Octetsto127Octets =
4749 1.1 bouyer stats->stat_EtherStatsPktsTx65Octetsto127Octets;
4750 1.1 bouyer
4751 1.1 bouyer sc->stat_EtherStatsPktsTx128Octetsto255Octets =
4752 1.1 bouyer stats->stat_EtherStatsPktsTx128Octetsto255Octets;
4753 1.1 bouyer
4754 1.1 bouyer sc->stat_EtherStatsPktsTx256Octetsto511Octets =
4755 1.1 bouyer stats->stat_EtherStatsPktsTx256Octetsto511Octets;
4756 1.1 bouyer
4757 1.1 bouyer sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
4758 1.1 bouyer stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
4759 1.1 bouyer
4760 1.1 bouyer sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
4761 1.1 bouyer stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
4762 1.1 bouyer
4763 1.1 bouyer sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
4764 1.1 bouyer stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
4765 1.1 bouyer
4766 1.1 bouyer sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived;
4767 1.1 bouyer
4768 1.1 bouyer sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived;
4769 1.1 bouyer
4770 1.1 bouyer sc->stat_OutXonSent = stats->stat_OutXonSent;
4771 1.1 bouyer
4772 1.1 bouyer sc->stat_OutXoffSent = stats->stat_OutXoffSent;
4773 1.1 bouyer
4774 1.1 bouyer sc->stat_FlowControlDone = stats->stat_FlowControlDone;
4775 1.1 bouyer
4776 1.1 bouyer sc->stat_MacControlFramesReceived =
4777 1.1 bouyer stats->stat_MacControlFramesReceived;
4778 1.1 bouyer
4779 1.1 bouyer sc->stat_XoffStateEntered = stats->stat_XoffStateEntered;
4780 1.1 bouyer
4781 1.1 bouyer sc->stat_IfInFramesL2FilterDiscards =
4782 1.1 bouyer stats->stat_IfInFramesL2FilterDiscards;
4783 1.1 bouyer
4784 1.1 bouyer sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards;
4785 1.1 bouyer
4786 1.1 bouyer sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards;
4787 1.1 bouyer
4788 1.1 bouyer sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards;
4789 1.1 bouyer
4790 1.1 bouyer sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit;
4791 1.1 bouyer
4792 1.1 bouyer sc->stat_CatchupInRuleCheckerDiscards =
4793 1.1 bouyer stats->stat_CatchupInRuleCheckerDiscards;
4794 1.1 bouyer
4795 1.1 bouyer sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards;
4796 1.1 bouyer
4797 1.1 bouyer sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards;
4798 1.1 bouyer
4799 1.1 bouyer sc->stat_CatchupInRuleCheckerP4Hit =
4800 1.1 bouyer stats->stat_CatchupInRuleCheckerP4Hit;
4801 1.1 bouyer
4802 1.12 perry DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__);
4803 1.1 bouyer }
4804 1.1 bouyer
4805 1.1 bouyer void
4806 1.1 bouyer bnx_tick(void *xsc)
4807 1.1 bouyer {
4808 1.1 bouyer struct bnx_softc *sc = xsc;
4809 1.14 dyoung struct mii_data *mii;
4810 1.1 bouyer u_int32_t msg;
4811 1.5 bouyer u_int16_t prod, chain_prod;
4812 1.5 bouyer u_int32_t prod_bseq;
4813 1.4 bouyer int s = splnet();
4814 1.1 bouyer
4815 1.1 bouyer /* Tell the firmware that the driver is still running. */
4816 1.1 bouyer #ifdef BNX_DEBUG
4817 1.1 bouyer msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
4818 1.1 bouyer #else
4819 1.1 bouyer msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq;
4820 1.1 bouyer #endif
4821 1.1 bouyer REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg);
4822 1.1 bouyer
4823 1.1 bouyer /* Update the statistics from the hardware statistics block. */
4824 1.1 bouyer bnx_stats_update(sc);
4825 1.1 bouyer
4826 1.1 bouyer /* Schedule the next tick. */
4827 1.1 bouyer callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc);
4828 1.1 bouyer
4829 1.1 bouyer /* DRC - ToDo: Add SerDes support and check SerDes link here. */
4830 1.1 bouyer
4831 1.1 bouyer mii = &sc->bnx_mii;
4832 1.1 bouyer mii_tick(mii);
4833 1.1 bouyer
4834 1.5 bouyer /* try to get more RX buffers, just in case */
4835 1.5 bouyer prod = sc->rx_prod;
4836 1.5 bouyer prod_bseq = sc->rx_prod_bseq;
4837 1.5 bouyer chain_prod = RX_CHAIN_IDX(prod);
4838 1.5 bouyer bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq);
4839 1.5 bouyer sc->rx_prod = prod;
4840 1.5 bouyer sc->rx_prod_bseq = prod_bseq;
4841 1.4 bouyer splx(s);
4842 1.1 bouyer return;
4843 1.1 bouyer }
4844 1.1 bouyer
4845 1.1 bouyer /****************************************************************************/
4846 1.1 bouyer /* BNX Debug Routines */
4847 1.1 bouyer /****************************************************************************/
4848 1.1 bouyer #ifdef BNX_DEBUG
4849 1.1 bouyer
4850 1.1 bouyer /****************************************************************************/
4851 1.1 bouyer /* Prints out information about an mbuf. */
4852 1.1 bouyer /* */
4853 1.1 bouyer /* Returns: */
4854 1.1 bouyer /* Nothing. */
4855 1.1 bouyer /****************************************************************************/
4856 1.1 bouyer void
4857 1.1 bouyer bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m)
4858 1.1 bouyer {
4859 1.1 bouyer struct mbuf *mp = m;
4860 1.1 bouyer
4861 1.1 bouyer if (m == NULL) {
4862 1.1 bouyer /* Index out of range. */
4863 1.1 bouyer aprint_error("mbuf ptr is null!\n");
4864 1.1 bouyer return;
4865 1.1 bouyer }
4866 1.1 bouyer
4867 1.1 bouyer while (mp) {
4868 1.1 bouyer aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ",
4869 1.1 bouyer mp, mp->m_len);
4870 1.1 bouyer
4871 1.1 bouyer if (mp->m_flags & M_EXT)
4872 1.1 bouyer aprint_debug("M_EXT ");
4873 1.1 bouyer if (mp->m_flags & M_PKTHDR)
4874 1.1 bouyer aprint_debug("M_PKTHDR ");
4875 1.1 bouyer aprint_debug("\n");
4876 1.1 bouyer
4877 1.1 bouyer if (mp->m_flags & M_EXT)
4878 1.1 bouyer aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n",
4879 1.1 bouyer mp, mp->m_ext.ext_size);
4880 1.1 bouyer
4881 1.1 bouyer mp = mp->m_next;
4882 1.1 bouyer }
4883 1.1 bouyer }
4884 1.1 bouyer
4885 1.1 bouyer /****************************************************************************/
4886 1.1 bouyer /* Prints out the mbufs in the TX mbuf chain. */
4887 1.1 bouyer /* */
4888 1.1 bouyer /* Returns: */
4889 1.1 bouyer /* Nothing. */
4890 1.1 bouyer /****************************************************************************/
4891 1.1 bouyer void
4892 1.1 bouyer bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count)
4893 1.1 bouyer {
4894 1.1 bouyer struct mbuf *m;
4895 1.1 bouyer int i;
4896 1.1 bouyer
4897 1.1 bouyer BNX_PRINTF(sc,
4898 1.1 bouyer "----------------------------"
4899 1.1 bouyer " tx mbuf data "
4900 1.1 bouyer "----------------------------\n");
4901 1.1 bouyer
4902 1.1 bouyer for (i = 0; i < count; i++) {
4903 1.1 bouyer m = sc->tx_mbuf_ptr[chain_prod];
4904 1.1 bouyer BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod);
4905 1.1 bouyer bnx_dump_mbuf(sc, m);
4906 1.1 bouyer chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
4907 1.1 bouyer }
4908 1.1 bouyer
4909 1.1 bouyer BNX_PRINTF(sc,
4910 1.1 bouyer "--------------------------------------------"
4911 1.1 bouyer "----------------------------\n");
4912 1.1 bouyer }
4913 1.1 bouyer
4914 1.1 bouyer /*
4915 1.1 bouyer * This routine prints the RX mbuf chain.
4916 1.1 bouyer */
4917 1.1 bouyer void
4918 1.1 bouyer bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count)
4919 1.1 bouyer {
4920 1.1 bouyer struct mbuf *m;
4921 1.1 bouyer int i;
4922 1.1 bouyer
4923 1.1 bouyer BNX_PRINTF(sc,
4924 1.1 bouyer "----------------------------"
4925 1.1 bouyer " rx mbuf data "
4926 1.1 bouyer "----------------------------\n");
4927 1.1 bouyer
4928 1.1 bouyer for (i = 0; i < count; i++) {
4929 1.1 bouyer m = sc->rx_mbuf_ptr[chain_prod];
4930 1.1 bouyer BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod);
4931 1.1 bouyer bnx_dump_mbuf(sc, m);
4932 1.1 bouyer chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
4933 1.1 bouyer }
4934 1.1 bouyer
4935 1.1 bouyer
4936 1.1 bouyer BNX_PRINTF(sc,
4937 1.1 bouyer "--------------------------------------------"
4938 1.1 bouyer "----------------------------\n");
4939 1.1 bouyer }
4940 1.1 bouyer
4941 1.1 bouyer void
4942 1.1 bouyer bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd)
4943 1.1 bouyer {
4944 1.1 bouyer if (idx > MAX_TX_BD)
4945 1.1 bouyer /* Index out of range. */
4946 1.1 bouyer BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
4947 1.1 bouyer else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4948 1.1 bouyer /* TX Chain page pointer. */
4949 1.1 bouyer BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain "
4950 1.1 bouyer "page pointer\n", idx, txbd->tx_bd_haddr_hi,
4951 1.1 bouyer txbd->tx_bd_haddr_lo);
4952 1.1 bouyer else
4953 1.1 bouyer /* Normal tx_bd entry. */
4954 1.1 bouyer BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
4955 1.4 bouyer "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx,
4956 1.1 bouyer txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
4957 1.4 bouyer txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag,
4958 1.4 bouyer txbd->tx_bd_flags);
4959 1.1 bouyer }
4960 1.1 bouyer
4961 1.1 bouyer void
4962 1.1 bouyer bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd)
4963 1.1 bouyer {
4964 1.1 bouyer if (idx > MAX_RX_BD)
4965 1.1 bouyer /* Index out of range. */
4966 1.1 bouyer BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
4967 1.1 bouyer else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4968 1.1 bouyer /* TX Chain page pointer. */
4969 1.1 bouyer BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
4970 1.1 bouyer "pointer\n", idx, rxbd->rx_bd_haddr_hi,
4971 1.1 bouyer rxbd->rx_bd_haddr_lo);
4972 1.1 bouyer else
4973 1.1 bouyer /* Normal tx_bd entry. */
4974 1.1 bouyer BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
4975 1.1 bouyer "0x%08X, flags = 0x%08X\n", idx,
4976 1.1 bouyer rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
4977 1.1 bouyer rxbd->rx_bd_len, rxbd->rx_bd_flags);
4978 1.1 bouyer }
4979 1.1 bouyer
4980 1.1 bouyer void
4981 1.1 bouyer bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr)
4982 1.1 bouyer {
4983 1.1 bouyer BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, "
4984 1.1 bouyer "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, "
4985 1.1 bouyer "tcp_udp_xsum = 0x%04X\n", idx,
4986 1.1 bouyer l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len,
4987 1.1 bouyer l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum,
4988 1.1 bouyer l2fhdr->l2_fhdr_tcp_udp_xsum);
4989 1.1 bouyer }
4990 1.1 bouyer
4991 1.1 bouyer /*
4992 1.1 bouyer * This routine prints the TX chain.
4993 1.1 bouyer */
4994 1.1 bouyer void
4995 1.1 bouyer bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count)
4996 1.1 bouyer {
4997 1.1 bouyer struct tx_bd *txbd;
4998 1.1 bouyer int i;
4999 1.1 bouyer
5000 1.1 bouyer /* First some info about the tx_bd chain structure. */
5001 1.1 bouyer BNX_PRINTF(sc,
5002 1.1 bouyer "----------------------------"
5003 1.1 bouyer " tx_bd chain "
5004 1.1 bouyer "----------------------------\n");
5005 1.1 bouyer
5006 1.1 bouyer BNX_PRINTF(sc,
5007 1.1 bouyer "page size = 0x%08X, tx chain pages = 0x%08X\n",
5008 1.1 bouyer (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES);
5009 1.1 bouyer
5010 1.1 bouyer BNX_PRINTF(sc,
5011 1.1 bouyer "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
5012 1.1 bouyer (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE);
5013 1.1 bouyer
5014 1.1 bouyer BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD);
5015 1.1 bouyer
5016 1.1 bouyer BNX_PRINTF(sc, ""
5017 1.1 bouyer "-----------------------------"
5018 1.1 bouyer " tx_bd data "
5019 1.1 bouyer "-----------------------------\n");
5020 1.1 bouyer
5021 1.1 bouyer /* Now print out the tx_bd's themselves. */
5022 1.1 bouyer for (i = 0; i < count; i++) {
5023 1.1 bouyer txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
5024 1.1 bouyer bnx_dump_txbd(sc, tx_prod, txbd);
5025 1.1 bouyer tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
5026 1.1 bouyer }
5027 1.1 bouyer
5028 1.1 bouyer BNX_PRINTF(sc,
5029 1.1 bouyer "-----------------------------"
5030 1.1 bouyer "--------------"
5031 1.1 bouyer "-----------------------------\n");
5032 1.1 bouyer }
5033 1.1 bouyer
5034 1.1 bouyer /*
5035 1.1 bouyer * This routine prints the RX chain.
5036 1.1 bouyer */
5037 1.1 bouyer void
5038 1.1 bouyer bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count)
5039 1.1 bouyer {
5040 1.1 bouyer struct rx_bd *rxbd;
5041 1.1 bouyer int i;
5042 1.1 bouyer
5043 1.1 bouyer /* First some info about the tx_bd chain structure. */
5044 1.1 bouyer BNX_PRINTF(sc,
5045 1.1 bouyer "----------------------------"
5046 1.1 bouyer " rx_bd chain "
5047 1.1 bouyer "----------------------------\n");
5048 1.1 bouyer
5049 1.1 bouyer BNX_PRINTF(sc, "----- RX_BD Chain -----\n");
5050 1.1 bouyer
5051 1.1 bouyer BNX_PRINTF(sc,
5052 1.1 bouyer "page size = 0x%08X, rx chain pages = 0x%08X\n",
5053 1.1 bouyer (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES);
5054 1.1 bouyer
5055 1.1 bouyer BNX_PRINTF(sc,
5056 1.1 bouyer "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
5057 1.1 bouyer (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE);
5058 1.1 bouyer
5059 1.1 bouyer BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD);
5060 1.1 bouyer
5061 1.1 bouyer BNX_PRINTF(sc,
5062 1.1 bouyer "----------------------------"
5063 1.1 bouyer " rx_bd data "
5064 1.1 bouyer "----------------------------\n");
5065 1.1 bouyer
5066 1.1 bouyer /* Now print out the rx_bd's themselves. */
5067 1.1 bouyer for (i = 0; i < count; i++) {
5068 1.1 bouyer rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
5069 1.1 bouyer bnx_dump_rxbd(sc, rx_prod, rxbd);
5070 1.1 bouyer rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
5071 1.1 bouyer }
5072 1.1 bouyer
5073 1.1 bouyer BNX_PRINTF(sc,
5074 1.1 bouyer "----------------------------"
5075 1.1 bouyer "--------------"
5076 1.1 bouyer "----------------------------\n");
5077 1.1 bouyer }
5078 1.1 bouyer
5079 1.1 bouyer /*
5080 1.1 bouyer * This routine prints the status block.
5081 1.1 bouyer */
5082 1.1 bouyer void
5083 1.1 bouyer bnx_dump_status_block(struct bnx_softc *sc)
5084 1.1 bouyer {
5085 1.1 bouyer struct status_block *sblk;
5086 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ,
5087 1.1 bouyer BUS_DMASYNC_POSTREAD);
5088 1.1 bouyer
5089 1.1 bouyer sblk = sc->status_block;
5090 1.1 bouyer
5091 1.1 bouyer BNX_PRINTF(sc, "----------------------------- Status Block "
5092 1.1 bouyer "-----------------------------\n");
5093 1.1 bouyer
5094 1.1 bouyer BNX_PRINTF(sc,
5095 1.1 bouyer "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n",
5096 1.1 bouyer sblk->status_attn_bits, sblk->status_attn_bits_ack,
5097 1.1 bouyer sblk->status_idx);
5098 1.1 bouyer
5099 1.1 bouyer BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n",
5100 1.1 bouyer sblk->status_rx_quick_consumer_index0,
5101 1.1 bouyer sblk->status_tx_quick_consumer_index0);
5102 1.1 bouyer
5103 1.1 bouyer BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx);
5104 1.1 bouyer
5105 1.1 bouyer /* Theses indices are not used for normal L2 drivers. */
5106 1.1 bouyer if (sblk->status_rx_quick_consumer_index1 ||
5107 1.1 bouyer sblk->status_tx_quick_consumer_index1)
5108 1.1 bouyer BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n",
5109 1.1 bouyer sblk->status_rx_quick_consumer_index1,
5110 1.1 bouyer sblk->status_tx_quick_consumer_index1);
5111 1.1 bouyer
5112 1.1 bouyer if (sblk->status_rx_quick_consumer_index2 ||
5113 1.1 bouyer sblk->status_tx_quick_consumer_index2)
5114 1.1 bouyer BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n",
5115 1.1 bouyer sblk->status_rx_quick_consumer_index2,
5116 1.1 bouyer sblk->status_tx_quick_consumer_index2);
5117 1.1 bouyer
5118 1.1 bouyer if (sblk->status_rx_quick_consumer_index3 ||
5119 1.1 bouyer sblk->status_tx_quick_consumer_index3)
5120 1.1 bouyer BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n",
5121 1.1 bouyer sblk->status_rx_quick_consumer_index3,
5122 1.1 bouyer sblk->status_tx_quick_consumer_index3);
5123 1.1 bouyer
5124 1.1 bouyer if (sblk->status_rx_quick_consumer_index4 ||
5125 1.1 bouyer sblk->status_rx_quick_consumer_index5)
5126 1.1 bouyer BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
5127 1.1 bouyer sblk->status_rx_quick_consumer_index4,
5128 1.1 bouyer sblk->status_rx_quick_consumer_index5);
5129 1.1 bouyer
5130 1.1 bouyer if (sblk->status_rx_quick_consumer_index6 ||
5131 1.1 bouyer sblk->status_rx_quick_consumer_index7)
5132 1.1 bouyer BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
5133 1.1 bouyer sblk->status_rx_quick_consumer_index6,
5134 1.1 bouyer sblk->status_rx_quick_consumer_index7);
5135 1.1 bouyer
5136 1.1 bouyer if (sblk->status_rx_quick_consumer_index8 ||
5137 1.1 bouyer sblk->status_rx_quick_consumer_index9)
5138 1.1 bouyer BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
5139 1.1 bouyer sblk->status_rx_quick_consumer_index8,
5140 1.1 bouyer sblk->status_rx_quick_consumer_index9);
5141 1.1 bouyer
5142 1.1 bouyer if (sblk->status_rx_quick_consumer_index10 ||
5143 1.1 bouyer sblk->status_rx_quick_consumer_index11)
5144 1.1 bouyer BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
5145 1.1 bouyer sblk->status_rx_quick_consumer_index10,
5146 1.1 bouyer sblk->status_rx_quick_consumer_index11);
5147 1.1 bouyer
5148 1.1 bouyer if (sblk->status_rx_quick_consumer_index12 ||
5149 1.1 bouyer sblk->status_rx_quick_consumer_index13)
5150 1.1 bouyer BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
5151 1.1 bouyer sblk->status_rx_quick_consumer_index12,
5152 1.1 bouyer sblk->status_rx_quick_consumer_index13);
5153 1.1 bouyer
5154 1.1 bouyer if (sblk->status_rx_quick_consumer_index14 ||
5155 1.1 bouyer sblk->status_rx_quick_consumer_index15)
5156 1.1 bouyer BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
5157 1.1 bouyer sblk->status_rx_quick_consumer_index14,
5158 1.1 bouyer sblk->status_rx_quick_consumer_index15);
5159 1.1 bouyer
5160 1.1 bouyer if (sblk->status_completion_producer_index ||
5161 1.1 bouyer sblk->status_cmd_consumer_index)
5162 1.1 bouyer BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
5163 1.1 bouyer sblk->status_completion_producer_index,
5164 1.1 bouyer sblk->status_cmd_consumer_index);
5165 1.1 bouyer
5166 1.1 bouyer BNX_PRINTF(sc, "-------------------------------------------"
5167 1.1 bouyer "-----------------------------\n");
5168 1.1 bouyer }
5169 1.1 bouyer
5170 1.1 bouyer /*
5171 1.1 bouyer * This routine prints the statistics block.
5172 1.1 bouyer */
5173 1.1 bouyer void
5174 1.1 bouyer bnx_dump_stats_block(struct bnx_softc *sc)
5175 1.1 bouyer {
5176 1.1 bouyer struct statistics_block *sblk;
5177 1.1 bouyer bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ,
5178 1.1 bouyer BUS_DMASYNC_POSTREAD);
5179 1.1 bouyer
5180 1.1 bouyer sblk = sc->stats_block;
5181 1.1 bouyer
5182 1.1 bouyer BNX_PRINTF(sc, ""
5183 1.1 bouyer "-----------------------------"
5184 1.1 bouyer " Stats Block "
5185 1.1 bouyer "-----------------------------\n");
5186 1.1 bouyer
5187 1.1 bouyer BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, "
5188 1.1 bouyer "IfHcInBadOctets = 0x%08X:%08X\n",
5189 1.1 bouyer sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo,
5190 1.1 bouyer sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo);
5191 1.1 bouyer
5192 1.1 bouyer BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, "
5193 1.1 bouyer "IfHcOutBadOctets = 0x%08X:%08X\n",
5194 1.1 bouyer sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo,
5195 1.1 bouyer sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo);
5196 1.1 bouyer
5197 1.1 bouyer BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, "
5198 1.1 bouyer "IfHcInMulticastPkts = 0x%08X:%08X\n",
5199 1.1 bouyer sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo,
5200 1.1 bouyer sblk->stat_IfHCInMulticastPkts_hi,
5201 1.1 bouyer sblk->stat_IfHCInMulticastPkts_lo);
5202 1.1 bouyer
5203 1.1 bouyer BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, "
5204 1.1 bouyer "IfHcOutUcastPkts = 0x%08X:%08X\n",
5205 1.1 bouyer sblk->stat_IfHCInBroadcastPkts_hi,
5206 1.1 bouyer sblk->stat_IfHCInBroadcastPkts_lo,
5207 1.1 bouyer sblk->stat_IfHCOutUcastPkts_hi,
5208 1.1 bouyer sblk->stat_IfHCOutUcastPkts_lo);
5209 1.1 bouyer
5210 1.1 bouyer BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, "
5211 1.1 bouyer "IfHcOutBroadcastPkts = 0x%08X:%08X\n",
5212 1.1 bouyer sblk->stat_IfHCOutMulticastPkts_hi,
5213 1.1 bouyer sblk->stat_IfHCOutMulticastPkts_lo,
5214 1.1 bouyer sblk->stat_IfHCOutBroadcastPkts_hi,
5215 1.1 bouyer sblk->stat_IfHCOutBroadcastPkts_lo);
5216 1.1 bouyer
5217 1.1 bouyer if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors)
5218 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5219 1.1 bouyer "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
5220 1.1 bouyer sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
5221 1.1 bouyer
5222 1.1 bouyer if (sblk->stat_Dot3StatsCarrierSenseErrors)
5223 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n",
5224 1.1 bouyer sblk->stat_Dot3StatsCarrierSenseErrors);
5225 1.1 bouyer
5226 1.1 bouyer if (sblk->stat_Dot3StatsFCSErrors)
5227 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n",
5228 1.1 bouyer sblk->stat_Dot3StatsFCSErrors);
5229 1.1 bouyer
5230 1.1 bouyer if (sblk->stat_Dot3StatsAlignmentErrors)
5231 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n",
5232 1.1 bouyer sblk->stat_Dot3StatsAlignmentErrors);
5233 1.1 bouyer
5234 1.1 bouyer if (sblk->stat_Dot3StatsSingleCollisionFrames)
5235 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n",
5236 1.1 bouyer sblk->stat_Dot3StatsSingleCollisionFrames);
5237 1.1 bouyer
5238 1.1 bouyer if (sblk->stat_Dot3StatsMultipleCollisionFrames)
5239 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n",
5240 1.1 bouyer sblk->stat_Dot3StatsMultipleCollisionFrames);
5241 1.1 bouyer
5242 1.1 bouyer if (sblk->stat_Dot3StatsDeferredTransmissions)
5243 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n",
5244 1.1 bouyer sblk->stat_Dot3StatsDeferredTransmissions);
5245 1.1 bouyer
5246 1.1 bouyer if (sblk->stat_Dot3StatsExcessiveCollisions)
5247 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n",
5248 1.1 bouyer sblk->stat_Dot3StatsExcessiveCollisions);
5249 1.1 bouyer
5250 1.1 bouyer if (sblk->stat_Dot3StatsLateCollisions)
5251 1.1 bouyer BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n",
5252 1.1 bouyer sblk->stat_Dot3StatsLateCollisions);
5253 1.1 bouyer
5254 1.1 bouyer if (sblk->stat_EtherStatsCollisions)
5255 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n",
5256 1.1 bouyer sblk->stat_EtherStatsCollisions);
5257 1.1 bouyer
5258 1.1 bouyer if (sblk->stat_EtherStatsFragments)
5259 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n",
5260 1.1 bouyer sblk->stat_EtherStatsFragments);
5261 1.1 bouyer
5262 1.1 bouyer if (sblk->stat_EtherStatsJabbers)
5263 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n",
5264 1.1 bouyer sblk->stat_EtherStatsJabbers);
5265 1.1 bouyer
5266 1.1 bouyer if (sblk->stat_EtherStatsUndersizePkts)
5267 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n",
5268 1.1 bouyer sblk->stat_EtherStatsUndersizePkts);
5269 1.1 bouyer
5270 1.1 bouyer if (sblk->stat_EtherStatsOverrsizePkts)
5271 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n",
5272 1.1 bouyer sblk->stat_EtherStatsOverrsizePkts);
5273 1.1 bouyer
5274 1.1 bouyer if (sblk->stat_EtherStatsPktsRx64Octets)
5275 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n",
5276 1.1 bouyer sblk->stat_EtherStatsPktsRx64Octets);
5277 1.1 bouyer
5278 1.1 bouyer if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets)
5279 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n",
5280 1.1 bouyer sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
5281 1.1 bouyer
5282 1.1 bouyer if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets)
5283 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5284 1.1 bouyer "EtherStatsPktsRx128Octetsto255Octets\n",
5285 1.1 bouyer sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
5286 1.1 bouyer
5287 1.1 bouyer if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets)
5288 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5289 1.1 bouyer "EtherStatsPktsRx256Octetsto511Octets\n",
5290 1.1 bouyer sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
5291 1.1 bouyer
5292 1.1 bouyer if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets)
5293 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5294 1.1 bouyer "EtherStatsPktsRx512Octetsto1023Octets\n",
5295 1.1 bouyer sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
5296 1.1 bouyer
5297 1.1 bouyer if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets)
5298 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5299 1.1 bouyer "EtherStatsPktsRx1024Octetsto1522Octets\n",
5300 1.1 bouyer sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
5301 1.1 bouyer
5302 1.1 bouyer if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets)
5303 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5304 1.1 bouyer "EtherStatsPktsRx1523Octetsto9022Octets\n",
5305 1.1 bouyer sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
5306 1.1 bouyer
5307 1.1 bouyer if (sblk->stat_EtherStatsPktsTx64Octets)
5308 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n",
5309 1.1 bouyer sblk->stat_EtherStatsPktsTx64Octets);
5310 1.1 bouyer
5311 1.1 bouyer if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets)
5312 1.1 bouyer BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n",
5313 1.1 bouyer sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
5314 1.1 bouyer
5315 1.1 bouyer if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets)
5316 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5317 1.1 bouyer "EtherStatsPktsTx128Octetsto255Octets\n",
5318 1.1 bouyer sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
5319 1.1 bouyer
5320 1.1 bouyer if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets)
5321 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5322 1.1 bouyer "EtherStatsPktsTx256Octetsto511Octets\n",
5323 1.1 bouyer sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
5324 1.1 bouyer
5325 1.1 bouyer if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets)
5326 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5327 1.1 bouyer "EtherStatsPktsTx512Octetsto1023Octets\n",
5328 1.1 bouyer sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
5329 1.1 bouyer
5330 1.1 bouyer if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets)
5331 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5332 1.1 bouyer "EtherStatsPktsTx1024Octetsto1522Octets\n",
5333 1.1 bouyer sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
5334 1.1 bouyer
5335 1.1 bouyer if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets)
5336 1.1 bouyer BNX_PRINTF(sc, "0x%08X : "
5337 1.1 bouyer "EtherStatsPktsTx1523Octetsto9022Octets\n",
5338 1.1 bouyer sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
5339 1.1 bouyer
5340 1.1 bouyer if (sblk->stat_XonPauseFramesReceived)
5341 1.1 bouyer BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n",
5342 1.1 bouyer sblk->stat_XonPauseFramesReceived);
5343 1.1 bouyer
5344 1.1 bouyer if (sblk->stat_XoffPauseFramesReceived)
5345 1.1 bouyer BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n",
5346 1.1 bouyer sblk->stat_XoffPauseFramesReceived);
5347 1.1 bouyer
5348 1.1 bouyer if (sblk->stat_OutXonSent)
5349 1.1 bouyer BNX_PRINTF(sc, "0x%08X : OutXonSent\n",
5350 1.1 bouyer sblk->stat_OutXonSent);
5351 1.1 bouyer
5352 1.1 bouyer if (sblk->stat_OutXoffSent)
5353 1.1 bouyer BNX_PRINTF(sc, "0x%08X : OutXoffSent\n",
5354 1.1 bouyer sblk->stat_OutXoffSent);
5355 1.1 bouyer
5356 1.1 bouyer if (sblk->stat_FlowControlDone)
5357 1.1 bouyer BNX_PRINTF(sc, "0x%08X : FlowControlDone\n",
5358 1.1 bouyer sblk->stat_FlowControlDone);
5359 1.1 bouyer
5360 1.1 bouyer if (sblk->stat_MacControlFramesReceived)
5361 1.1 bouyer BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n",
5362 1.1 bouyer sblk->stat_MacControlFramesReceived);
5363 1.1 bouyer
5364 1.1 bouyer if (sblk->stat_XoffStateEntered)
5365 1.1 bouyer BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n",
5366 1.1 bouyer sblk->stat_XoffStateEntered);
5367 1.1 bouyer
5368 1.1 bouyer if (sblk->stat_IfInFramesL2FilterDiscards)
5369 1.1 bouyer BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n",
5370 1.1 bouyer sblk->stat_IfInFramesL2FilterDiscards);
5371 1.1 bouyer
5372 1.1 bouyer if (sblk->stat_IfInRuleCheckerDiscards)
5373 1.1 bouyer BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n",
5374 1.1 bouyer sblk->stat_IfInRuleCheckerDiscards);
5375 1.1 bouyer
5376 1.1 bouyer if (sblk->stat_IfInFTQDiscards)
5377 1.1 bouyer BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n",
5378 1.1 bouyer sblk->stat_IfInFTQDiscards);
5379 1.1 bouyer
5380 1.1 bouyer if (sblk->stat_IfInMBUFDiscards)
5381 1.1 bouyer BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n",
5382 1.1 bouyer sblk->stat_IfInMBUFDiscards);
5383 1.1 bouyer
5384 1.1 bouyer if (sblk->stat_IfInRuleCheckerP4Hit)
5385 1.1 bouyer BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n",
5386 1.1 bouyer sblk->stat_IfInRuleCheckerP4Hit);
5387 1.1 bouyer
5388 1.1 bouyer if (sblk->stat_CatchupInRuleCheckerDiscards)
5389 1.1 bouyer BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n",
5390 1.1 bouyer sblk->stat_CatchupInRuleCheckerDiscards);
5391 1.1 bouyer
5392 1.1 bouyer if (sblk->stat_CatchupInFTQDiscards)
5393 1.1 bouyer BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n",
5394 1.1 bouyer sblk->stat_CatchupInFTQDiscards);
5395 1.1 bouyer
5396 1.1 bouyer if (sblk->stat_CatchupInMBUFDiscards)
5397 1.1 bouyer BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n",
5398 1.1 bouyer sblk->stat_CatchupInMBUFDiscards);
5399 1.1 bouyer
5400 1.1 bouyer if (sblk->stat_CatchupInRuleCheckerP4Hit)
5401 1.1 bouyer BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n",
5402 1.1 bouyer sblk->stat_CatchupInRuleCheckerP4Hit);
5403 1.1 bouyer
5404 1.1 bouyer BNX_PRINTF(sc,
5405 1.1 bouyer "-----------------------------"
5406 1.1 bouyer "--------------"
5407 1.1 bouyer "-----------------------------\n");
5408 1.1 bouyer }
5409 1.1 bouyer
5410 1.1 bouyer void
5411 1.1 bouyer bnx_dump_driver_state(struct bnx_softc *sc)
5412 1.1 bouyer {
5413 1.1 bouyer BNX_PRINTF(sc,
5414 1.1 bouyer "-----------------------------"
5415 1.1 bouyer " Driver State "
5416 1.1 bouyer "-----------------------------\n");
5417 1.1 bouyer
5418 1.1 bouyer BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual "
5419 1.1 bouyer "address\n", sc);
5420 1.1 bouyer
5421 1.1 bouyer BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n",
5422 1.1 bouyer sc->status_block);
5423 1.1 bouyer
5424 1.1 bouyer BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual "
5425 1.1 bouyer "address\n", sc->stats_block);
5426 1.1 bouyer
5427 1.1 bouyer BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual "
5428 1.1 bouyer "adddress\n", sc->tx_bd_chain);
5429 1.1 bouyer
5430 1.1 bouyer BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n",
5431 1.1 bouyer sc->rx_bd_chain);
5432 1.1 bouyer
5433 1.1 bouyer BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n",
5434 1.1 bouyer sc->tx_mbuf_ptr);
5435 1.1 bouyer
5436 1.1 bouyer BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n",
5437 1.1 bouyer sc->rx_mbuf_ptr);
5438 1.1 bouyer
5439 1.1 bouyer BNX_PRINTF(sc,
5440 1.1 bouyer " 0x%08X - (sc->interrupts_generated) h/w intrs\n",
5441 1.1 bouyer sc->interrupts_generated);
5442 1.1 bouyer
5443 1.1 bouyer BNX_PRINTF(sc,
5444 1.1 bouyer " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n",
5445 1.1 bouyer sc->rx_interrupts);
5446 1.1 bouyer
5447 1.1 bouyer BNX_PRINTF(sc,
5448 1.1 bouyer " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n",
5449 1.1 bouyer sc->tx_interrupts);
5450 1.1 bouyer
5451 1.1 bouyer BNX_PRINTF(sc,
5452 1.1 bouyer " 0x%08X - (sc->last_status_idx) status block index\n",
5453 1.1 bouyer sc->last_status_idx);
5454 1.1 bouyer
5455 1.1 bouyer BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n",
5456 1.1 bouyer sc->tx_prod);
5457 1.1 bouyer
5458 1.1 bouyer BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n",
5459 1.1 bouyer sc->tx_cons);
5460 1.1 bouyer
5461 1.1 bouyer BNX_PRINTF(sc,
5462 1.1 bouyer " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n",
5463 1.1 bouyer sc->tx_prod_bseq);
5464 1.1 bouyer
5465 1.1 bouyer BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n",
5466 1.1 bouyer sc->rx_prod);
5467 1.1 bouyer
5468 1.1 bouyer BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n",
5469 1.1 bouyer sc->rx_cons);
5470 1.1 bouyer
5471 1.1 bouyer BNX_PRINTF(sc,
5472 1.1 bouyer " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n",
5473 1.1 bouyer sc->rx_prod_bseq);
5474 1.1 bouyer
5475 1.1 bouyer BNX_PRINTF(sc,
5476 1.1 bouyer " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n",
5477 1.1 bouyer sc->rx_mbuf_alloc);
5478 1.1 bouyer
5479 1.1 bouyer BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n",
5480 1.1 bouyer sc->free_rx_bd);
5481 1.1 bouyer
5482 1.1 bouyer BNX_PRINTF(sc,
5483 1.1 bouyer "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n",
5484 1.1 bouyer sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD);
5485 1.1 bouyer
5486 1.1 bouyer BNX_PRINTF(sc,
5487 1.1 bouyer " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n",
5488 1.1 bouyer sc->tx_mbuf_alloc);
5489 1.1 bouyer
5490 1.1 bouyer BNX_PRINTF(sc,
5491 1.1 bouyer " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n",
5492 1.1 bouyer sc->rx_mbuf_alloc);
5493 1.1 bouyer
5494 1.1 bouyer BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
5495 1.1 bouyer sc->used_tx_bd);
5496 1.1 bouyer
5497 1.1 bouyer BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
5498 1.1 bouyer sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD);
5499 1.1 bouyer
5500 1.1 bouyer BNX_PRINTF(sc,
5501 1.1 bouyer " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n",
5502 1.1 bouyer sc->mbuf_alloc_failed);
5503 1.1 bouyer
5504 1.1 bouyer BNX_PRINTF(sc, "-------------------------------------------"
5505 1.1 bouyer "-----------------------------\n");
5506 1.1 bouyer }
5507 1.1 bouyer
5508 1.1 bouyer void
5509 1.1 bouyer bnx_dump_hw_state(struct bnx_softc *sc)
5510 1.1 bouyer {
5511 1.1 bouyer u_int32_t val1;
5512 1.1 bouyer int i;
5513 1.1 bouyer
5514 1.1 bouyer BNX_PRINTF(sc,
5515 1.1 bouyer "----------------------------"
5516 1.1 bouyer " Hardware State "
5517 1.1 bouyer "----------------------------\n");
5518 1.1 bouyer
5519 1.1 bouyer BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver);
5520 1.1 bouyer
5521 1.1 bouyer val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS);
5522 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n",
5523 1.1 bouyer val1, BNX_MISC_ENABLE_STATUS_BITS);
5524 1.1 bouyer
5525 1.1 bouyer val1 = REG_RD(sc, BNX_DMA_STATUS);
5526 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS);
5527 1.1 bouyer
5528 1.1 bouyer val1 = REG_RD(sc, BNX_CTX_STATUS);
5529 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS);
5530 1.1 bouyer
5531 1.1 bouyer val1 = REG_RD(sc, BNX_EMAC_STATUS);
5532 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1,
5533 1.1 bouyer BNX_EMAC_STATUS);
5534 1.1 bouyer
5535 1.1 bouyer val1 = REG_RD(sc, BNX_RPM_STATUS);
5536 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS);
5537 1.1 bouyer
5538 1.1 bouyer val1 = REG_RD(sc, BNX_TBDR_STATUS);
5539 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1,
5540 1.1 bouyer BNX_TBDR_STATUS);
5541 1.1 bouyer
5542 1.1 bouyer val1 = REG_RD(sc, BNX_TDMA_STATUS);
5543 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1,
5544 1.1 bouyer BNX_TDMA_STATUS);
5545 1.1 bouyer
5546 1.1 bouyer val1 = REG_RD(sc, BNX_HC_STATUS);
5547 1.1 bouyer BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS);
5548 1.1 bouyer
5549 1.1 bouyer BNX_PRINTF(sc,
5550 1.1 bouyer "----------------------------"
5551 1.1 bouyer "----------------"
5552 1.1 bouyer "----------------------------\n");
5553 1.1 bouyer
5554 1.1 bouyer BNX_PRINTF(sc,
5555 1.1 bouyer "----------------------------"
5556 1.1 bouyer " Register Dump "
5557 1.1 bouyer "----------------------------\n");
5558 1.1 bouyer
5559 1.1 bouyer for (i = 0x400; i < 0x8000; i += 0x10)
5560 1.1 bouyer BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
5561 1.1 bouyer i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
5562 1.1 bouyer REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
5563 1.1 bouyer
5564 1.1 bouyer BNX_PRINTF(sc,
5565 1.1 bouyer "----------------------------"
5566 1.1 bouyer "----------------"
5567 1.1 bouyer "----------------------------\n");
5568 1.1 bouyer }
5569 1.1 bouyer
5570 1.1 bouyer void
5571 1.1 bouyer bnx_breakpoint(struct bnx_softc *sc)
5572 1.1 bouyer {
5573 1.1 bouyer /* Unreachable code to shut the compiler up about unused functions. */
5574 1.1 bouyer if (0) {
5575 1.1 bouyer bnx_dump_txbd(sc, 0, NULL);
5576 1.1 bouyer bnx_dump_rxbd(sc, 0, NULL);
5577 1.1 bouyer bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
5578 1.1 bouyer bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
5579 1.1 bouyer bnx_dump_l2fhdr(sc, 0, NULL);
5580 1.1 bouyer bnx_dump_tx_chain(sc, 0, USABLE_TX_BD);
5581 1.1 bouyer bnx_dump_rx_chain(sc, 0, USABLE_RX_BD);
5582 1.1 bouyer bnx_dump_status_block(sc);
5583 1.1 bouyer bnx_dump_stats_block(sc);
5584 1.1 bouyer bnx_dump_driver_state(sc);
5585 1.1 bouyer bnx_dump_hw_state(sc);
5586 1.1 bouyer }
5587 1.1 bouyer
5588 1.1 bouyer bnx_dump_driver_state(sc);
5589 1.1 bouyer /* Print the important status block fields. */
5590 1.1 bouyer bnx_dump_status_block(sc);
5591 1.1 bouyer
5592 1.1 bouyer #if 0
5593 1.1 bouyer /* Call the debugger. */
5594 1.1 bouyer breakpoint();
5595 1.1 bouyer #endif
5596 1.1 bouyer
5597 1.1 bouyer return;
5598 1.1 bouyer }
5599 1.1 bouyer #endif
5600