if_bnx.c revision 1.1
1 /* $NetBSD: if_bnx.c,v 1.1 2006/12/17 23:02:06 bouyer Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.21 2006/08/21 03:32:11 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.1 2006/12/17 23:02:06 bouyer Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5708C B1 44 * 45 * The following controllers are not supported by this driver: 46 * (These are not "Production" versions of the controller.) 47 * 48 * BCM5706C A0, A1 49 * BCM5706S A0, A1, A2, A3 50 * BCM5708C A0, B0 51 * BCM5708S A0, B0, B1 52 */ 53 54 #include <sys/callout.h> 55 56 #include <dev/pci/if_bnxreg.h> 57 #include <dev/microcode/bnx/bnxfw.h> 58 59 /****************************************************************************/ 60 /* BNX Driver Version */ 61 /****************************************************************************/ 62 const char bnx_driver_version[] = "v0.9.6"; 63 64 /****************************************************************************/ 65 /* BNX Debug Options */ 66 /****************************************************************************/ 67 #ifdef BNX_DEBUG 68 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 69 70 /* 0 = Never */ 71 /* 1 = 1 in 2,147,483,648 */ 72 /* 256 = 1 in 8,388,608 */ 73 /* 2048 = 1 in 1,048,576 */ 74 /* 65536 = 1 in 32,768 */ 75 /* 1048576 = 1 in 2,048 */ 76 /* 268435456 = 1 in 8 */ 77 /* 536870912 = 1 in 4 */ 78 /* 1073741824 = 1 in 2 */ 79 80 /* Controls how often the l2_fhdr frame error check will fail. */ 81 int bnx_debug_l2fhdr_status_check = 0; 82 83 /* Controls how often the unexpected attention check will fail. */ 84 int bnx_debug_unexpected_attention = 0; 85 86 /* Controls how often to simulate an mbuf allocation failure. */ 87 int bnx_debug_mbuf_allocation_failure = 0; 88 89 /* Controls how often to simulate a DMA mapping failure. */ 90 int bnx_debug_dma_map_addr_failure = 0; 91 92 /* Controls how often to simulate a bootcode failure. */ 93 int bnx_debug_bootcode_running_failure = 0; 94 #endif 95 96 /****************************************************************************/ 97 /* PCI Device ID Table */ 98 /* */ 99 /* Used by bnx_probe() to identify the devices supported by this driver. */ 100 /****************************************************************************/ 101 static const struct bnx_product { 102 pci_vendor_id_t bp_vendor; 103 pci_product_id_t bp_product; 104 pci_vendor_id_t bp_subvendor; 105 pci_product_id_t bp_subproduct; 106 const char *bp_name; 107 } bnx_devices[] = { 108 #ifdef PCI_SUBPRODUCT_HP_NC370T 109 { 110 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 111 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 112 "HP NC370T Multifunction Gigabit Server Adapter" 113 }, 114 #endif 115 #ifdef PCI_SUBPRODUCT_HP_NC370i 116 { 117 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 118 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 119 "HP NC370i Multifunction Gigabit Server Adapter" 120 }, 121 #endif 122 { 123 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 124 0, 0, 125 "Broadcom NetXtreme II BCM5706 1000Base-T" 126 }, 127 #ifdef PCI_SUBPRODUCT_HP_NC370F 128 { 129 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 130 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 131 "HP NC370F Multifunction Gigabit Server Adapter" 132 }, 133 #endif 134 { 135 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 136 0, 0, 137 "Broadcom NetXtreme II BCM5706 1000Base-SX" 138 }, 139 { 140 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 141 0, 0, 142 "Broadcom NetXtreme II BCM5708 1000Base-T" 143 }, 144 { 145 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 146 0, 0, 147 "Broadcom NetXtreme II BCM5708 1000Base-SX" 148 }, 149 }; 150 151 /****************************************************************************/ 152 /* Supported Flash NVRAM device data. */ 153 /****************************************************************************/ 154 static struct flash_spec flash_table[] = 155 { 156 /* Slow EEPROM */ 157 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 158 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 159 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 160 "EEPROM - slow"}, 161 /* Expansion entry 0001 */ 162 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 164 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 165 "Entry 0001"}, 166 /* Saifun SA25F010 (non-buffered flash) */ 167 /* strap, cfg1, & write1 need updates */ 168 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 169 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 171 "Non-buffered flash (128kB)"}, 172 /* Saifun SA25F020 (non-buffered flash) */ 173 /* strap, cfg1, & write1 need updates */ 174 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 175 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 176 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 177 "Non-buffered flash (256kB)"}, 178 /* Expansion entry 0100 */ 179 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 0100"}, 183 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 184 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 185 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 186 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 187 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 188 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 189 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 190 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 191 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 192 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 193 /* Saifun SA25F005 (non-buffered flash) */ 194 /* strap, cfg1, & write1 need updates */ 195 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 196 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 197 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 198 "Non-buffered flash (64kB)"}, 199 /* Fast EEPROM */ 200 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 201 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 202 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 203 "EEPROM - fast"}, 204 /* Expansion entry 1001 */ 205 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 206 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 208 "Entry 1001"}, 209 /* Expansion entry 1010 */ 210 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 211 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 1010"}, 214 /* ATMEL AT45DB011B (buffered flash) */ 215 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 216 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 217 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 218 "Buffered flash (128kB)"}, 219 /* Expansion entry 1100 */ 220 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 221 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 223 "Entry 1100"}, 224 /* Expansion entry 1101 */ 225 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 226 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 228 "Entry 1101"}, 229 /* Ateml Expansion entry 1110 */ 230 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 231 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 232 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 233 "Entry 1110 (Atmel)"}, 234 /* ATMEL AT45DB021B (buffered flash) */ 235 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 236 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 237 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 238 "Buffered flash (256kB)"}, 239 }; 240 241 /****************************************************************************/ 242 /* OpenBSD device entry points. */ 243 /****************************************************************************/ 244 static int bnx_probe(device_t, cfdata_t, void *); 245 void bnx_attach(struct device *, struct device *, void *); 246 #if 0 247 void bnx_detach(void *); 248 #endif 249 void bnx_shutdown(void *); 250 251 /****************************************************************************/ 252 /* BNX Debug Data Structure Dump Routines */ 253 /****************************************************************************/ 254 #ifdef BNX_DEBUG 255 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 256 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 257 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 258 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 259 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 260 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 261 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 262 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 263 void bnx_dump_status_block(struct bnx_softc *); 264 void bnx_dump_stats_block(struct bnx_softc *); 265 void bnx_dump_driver_state(struct bnx_softc *); 266 void bnx_dump_hw_state(struct bnx_softc *); 267 void bnx_breakpoint(struct bnx_softc *); 268 #endif 269 270 /****************************************************************************/ 271 /* BNX Register/Memory Access Routines */ 272 /****************************************************************************/ 273 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 274 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 275 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 276 int bnx_miibus_read_reg(struct device *, int, int); 277 void bnx_miibus_write_reg(struct device *, int, int, int); 278 void bnx_miibus_statchg(struct device *); 279 280 /****************************************************************************/ 281 /* BNX NVRAM Access Routines */ 282 /****************************************************************************/ 283 int bnx_acquire_nvram_lock(struct bnx_softc *); 284 int bnx_release_nvram_lock(struct bnx_softc *); 285 void bnx_enable_nvram_access(struct bnx_softc *); 286 void bnx_disable_nvram_access(struct bnx_softc *); 287 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 288 u_int32_t); 289 int bnx_init_nvram(struct bnx_softc *); 290 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 291 int bnx_nvram_test(struct bnx_softc *); 292 #ifdef BNX_NVRAM_WRITE_SUPPORT 293 int bnx_enable_nvram_write(struct bnx_softc *); 294 void bnx_disable_nvram_write(struct bnx_softc *); 295 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 296 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 297 u_int32_t); 298 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 299 #endif 300 301 /****************************************************************************/ 302 /* */ 303 /****************************************************************************/ 304 int bnx_dma_alloc(struct bnx_softc *); 305 void bnx_dma_free(struct bnx_softc *); 306 void bnx_release_resources(struct bnx_softc *); 307 void bnx_dma_map_tx_desc(void *, bus_dmamap_t); 308 309 /****************************************************************************/ 310 /* BNX Firmware Synchronization and Load */ 311 /****************************************************************************/ 312 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 313 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 314 u_int32_t); 315 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 316 struct fw_info *); 317 void bnx_init_cpus(struct bnx_softc *); 318 319 void bnx_stop(struct bnx_softc *); 320 int bnx_reset(struct bnx_softc *, u_int32_t); 321 int bnx_chipinit(struct bnx_softc *); 322 int bnx_blockinit(struct bnx_softc *); 323 int bnx_get_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 324 u_int16_t *, u_int32_t *); 325 326 int bnx_init_tx_chain(struct bnx_softc *); 327 int bnx_init_rx_chain(struct bnx_softc *); 328 void bnx_free_rx_chain(struct bnx_softc *); 329 void bnx_free_tx_chain(struct bnx_softc *); 330 331 int bnx_tx_encap(struct bnx_softc *, struct mbuf *, u_int16_t *, 332 u_int16_t *, u_int32_t *); 333 void bnx_start(struct ifnet *); 334 int bnx_ioctl(struct ifnet *, u_long, caddr_t); 335 void bnx_watchdog(struct ifnet *); 336 int bnx_ifmedia_upd(struct ifnet *); 337 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 338 int bnx_init(struct ifnet *); 339 340 void bnx_init_context(struct bnx_softc *); 341 void bnx_get_mac_addr(struct bnx_softc *); 342 void bnx_set_mac_addr(struct bnx_softc *); 343 void bnx_phy_intr(struct bnx_softc *); 344 void bnx_rx_intr(struct bnx_softc *); 345 void bnx_tx_intr(struct bnx_softc *); 346 void bnx_disable_intr(struct bnx_softc *); 347 void bnx_enable_intr(struct bnx_softc *); 348 349 int bnx_intr(void *); 350 void bnx_set_rx_mode(struct bnx_softc *); 351 void bnx_stats_update(struct bnx_softc *); 352 void bnx_tick(void *); 353 354 /****************************************************************************/ 355 /* OpenBSD device dispatch table. */ 356 /****************************************************************************/ 357 CFATTACH_DECL(bnx, sizeof(struct bnx_softc), 358 bnx_probe, bnx_attach, NULL, NULL); 359 360 /****************************************************************************/ 361 /* Device probe function. */ 362 /* */ 363 /* Compares the device to the driver's list of supported devices and */ 364 /* reports back to the OS whether this is the right driver for the device. */ 365 /* */ 366 /* Returns: */ 367 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 368 /****************************************************************************/ 369 static const struct bnx_product * 370 bnx_lookup(const struct pci_attach_args *pa) 371 { 372 int i; 373 pcireg_t subid; 374 375 for (i = 0; i < sizeof(bnx_devices)/sizeof(struct bnx_product); i++) { 376 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 377 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 378 continue; 379 if (!bnx_devices[i].bp_subvendor) 380 return &bnx_devices[i]; 381 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 382 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 383 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 384 return &bnx_devices[i]; 385 } 386 387 return NULL; 388 } 389 static int 390 bnx_probe(device_t parent, cfdata_t match, void *aux) 391 { 392 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 393 394 if (bnx_lookup(pa) != NULL) 395 return (1); 396 397 return (0); 398 } 399 400 /****************************************************************************/ 401 /* Device attach function. */ 402 /* */ 403 /* Allocates device resources, performs secondary chip identification, */ 404 /* resets and initializes the hardware, and initializes driver instance */ 405 /* variables. */ 406 /* */ 407 /* Returns: */ 408 /* 0 on success, positive value on failure. */ 409 /****************************************************************************/ 410 void 411 bnx_attach(struct device *parent, struct device *self, void *aux) 412 { 413 const struct bnx_product *bp; 414 struct bnx_softc *sc = (struct bnx_softc *)self; 415 struct pci_attach_args *pa = aux; 416 pci_chipset_tag_t pc = pa->pa_pc; 417 pci_intr_handle_t ih; 418 const char *intrstr = NULL; 419 u_int32_t command; 420 struct ifnet *ifp; 421 u_int32_t val; 422 pcireg_t memtype; 423 424 bp = bnx_lookup(pa); 425 if (bp == NULL) 426 panic("unknown device"); 427 428 aprint_naive("\n"); 429 aprint_normal(": %s", bp->bp_name); 430 431 sc->bnx_pa = *pa; 432 433 /* 434 * Map control/status registers. 435 */ 436 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 437 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 438 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 439 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 440 441 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 442 aprint_error("%s: failed to enable memory mapping!\n", 443 sc->bnx_dev.dv_xname); 444 return; 445 } 446 447 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 448 switch (memtype) { 449 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 450 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 451 if (pci_mapreg_map(pa, BNX_PCI_BAR0, 452 memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, 453 NULL, &sc->bnx_size) == 0) 454 break; 455 default: 456 aprint_error("%s: can't find mem space\n", 457 sc->bnx_dev.dv_xname); 458 return; 459 } 460 461 if (pci_intr_map(pa, &ih)) { 462 aprint_error("%s: couldn't map interrupt\n", 463 sc->bnx_dev.dv_xname); 464 goto bnx_attach_fail; 465 } 466 467 intrstr = pci_intr_string(pc, ih); 468 469 /* 470 * Configure byte swap and enable indirect register access. 471 * Rely on CPU to do target byte swapping on big endian systems. 472 * Access to registers outside of PCI configurtion space are not 473 * valid until this is done. 474 */ 475 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 476 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 477 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 478 479 /* Save ASIC revsion info. */ 480 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 481 482 /* Weed out any non-production controller revisions. */ 483 switch(BNX_CHIP_ID(sc)) { 484 case BNX_CHIP_ID_5706_A0: 485 case BNX_CHIP_ID_5706_A1: 486 case BNX_CHIP_ID_5708_A0: 487 case BNX_CHIP_ID_5708_B0: 488 aprint_error("%s: unsupported controller revision (%c%d)!\n", 489 sc->bnx_dev.dv_xname, 490 ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A', 491 PCI_REVISION(pa->pa_class) & 0x0f); 492 goto bnx_attach_fail; 493 } 494 495 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 496 aprint_error("%s: SerDes controllers are not supported!\n", 497 sc->bnx_dev.dv_xname); 498 goto bnx_attach_fail; 499 } 500 501 /* 502 * Find the base address for shared memory access. 503 * Newer versions of bootcode use a signature and offset 504 * while older versions use a fixed address. 505 */ 506 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 507 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 508 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0); 509 else 510 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 511 512 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 513 514 /* Set initial device and PHY flags */ 515 sc->bnx_flags = 0; 516 sc->bnx_phy_flags = 0; 517 518 /* Get PCI bus information (speed and type). */ 519 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 520 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 521 u_int32_t clkreg; 522 523 sc->bnx_flags |= BNX_PCIX_FLAG; 524 525 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 526 527 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 528 switch (clkreg) { 529 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 530 sc->bus_speed_mhz = 133; 531 break; 532 533 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 534 sc->bus_speed_mhz = 100; 535 break; 536 537 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 538 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 539 sc->bus_speed_mhz = 66; 540 break; 541 542 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 543 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 544 sc->bus_speed_mhz = 50; 545 break; 546 547 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 548 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 549 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 550 sc->bus_speed_mhz = 33; 551 break; 552 } 553 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 554 sc->bus_speed_mhz = 66; 555 else 556 sc->bus_speed_mhz = 33; 557 558 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 559 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 560 561 /* Reset the controller. */ 562 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 563 goto bnx_attach_fail; 564 565 /* Initialize the controller. */ 566 if (bnx_chipinit(sc)) { 567 aprint_error("%s: Controller initialization failed!\n", 568 sc->bnx_dev.dv_xname); 569 goto bnx_attach_fail; 570 } 571 572 /* Perform NVRAM test. */ 573 if (bnx_nvram_test(sc)) { 574 aprint_error("%s: NVRAM test failed!\n", sc->bnx_dev.dv_xname); 575 goto bnx_attach_fail; 576 } 577 578 /* Fetch the permanent Ethernet MAC address. */ 579 bnx_get_mac_addr(sc); 580 aprint_normal("%s: Ethernet address %s\n", sc->bnx_dev.dv_xname, 581 ether_sprintf(sc->eaddr)); 582 583 /* 584 * Trip points control how many BDs 585 * should be ready before generating an 586 * interrupt while ticks control how long 587 * a BD can sit in the chain before 588 * generating an interrupt. Set the default 589 * values for the RX and TX rings. 590 */ 591 592 #ifdef BNX_DEBUG 593 /* Force more frequent interrupts. */ 594 sc->bnx_tx_quick_cons_trip_int = 1; 595 sc->bnx_tx_quick_cons_trip = 1; 596 sc->bnx_tx_ticks_int = 0; 597 sc->bnx_tx_ticks = 0; 598 599 sc->bnx_rx_quick_cons_trip_int = 1; 600 sc->bnx_rx_quick_cons_trip = 1; 601 sc->bnx_rx_ticks_int = 0; 602 sc->bnx_rx_ticks = 0; 603 #else 604 sc->bnx_tx_quick_cons_trip_int = 20; 605 sc->bnx_tx_quick_cons_trip = 20; 606 sc->bnx_tx_ticks_int = 80; 607 sc->bnx_tx_ticks = 80; 608 609 sc->bnx_rx_quick_cons_trip_int = 6; 610 sc->bnx_rx_quick_cons_trip = 6; 611 sc->bnx_rx_ticks_int = 18; 612 sc->bnx_rx_ticks = 18; 613 #endif 614 615 /* Update statistics once every second. */ 616 sc->bnx_stats_ticks = 1000000 & 0xffff00; 617 618 /* 619 * The copper based NetXtreme II controllers 620 * use an integrated PHY at address 1 while 621 * the SerDes controllers use a PHY at 622 * address 2. 623 */ 624 sc->bnx_phy_addr = 1; 625 626 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 627 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 628 sc->bnx_flags |= BNX_NO_WOL_FLAG; 629 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) { 630 sc->bnx_phy_addr = 2; 631 val = REG_RD_IND(sc, sc->bnx_shmem_base + 632 BNX_SHARED_HW_CFG_CONFIG); 633 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) 634 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 635 } 636 } 637 638 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 639 aprint_error("%s: SerDes is not supported by this driver!\n", 640 sc->bnx_dev.dv_xname); 641 goto bnx_attach_fail; 642 } 643 644 /* Allocate DMA memory resources. */ 645 sc->bnx_dmatag = pa->pa_dmat; 646 if (bnx_dma_alloc(sc)) { 647 aprint_error("%s: DMA resource allocation failed!\n", 648 sc->bnx_dev.dv_xname); 649 goto bnx_attach_fail; 650 } 651 652 /* Initialize the ifnet interface. */ 653 ifp = &sc->ethercom.ec_if; 654 ifp->if_softc = sc; 655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 656 ifp->if_ioctl = bnx_ioctl; 657 ifp->if_start = bnx_start; 658 ifp->if_init = bnx_init; 659 ifp->if_timer = 0; 660 ifp->if_watchdog = bnx_watchdog; 661 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 662 ifp->if_baudrate = IF_Gbps(2.5); 663 else 664 ifp->if_baudrate = IF_Gbps(1); 665 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD); 666 IFQ_SET_READY(&ifp->if_snd); 667 bcopy(sc->bnx_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 668 669 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU | 670 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 671 672 ifp->if_capabilities |= 673 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 674 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 675 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 676 677 sc->mbuf_alloc_size = BNX_MAX_MRU; 678 679 /* Hookup IRQ last. */ 680 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 681 if (sc->bnx_intrhand == NULL) { 682 aprint_error("%s: couldn't establish interrupt", 683 sc->bnx_dev.dv_xname); 684 if (intrstr != NULL) 685 aprint_error(" at %s", intrstr); 686 aprint_error("\n"); 687 goto bnx_attach_fail; 688 } 689 690 sc->bnx_mii.mii_ifp = ifp; 691 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 692 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 693 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 694 695 /* Look for our PHY. */ 696 ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, 697 bnx_ifmedia_sts); 698 mii_attach(&sc->bnx_dev, &sc->bnx_mii, 0xffffffff, 699 MII_PHY_ANY, MII_OFFSET_ANY, 0); 700 701 if (LIST_FIRST(&sc->bnx_mii.mii_phys) == NULL) { 702 aprint_error("%s: no PHY found!\n", sc->bnx_dev.dv_xname); 703 ifmedia_add(&sc->bnx_mii.mii_media, 704 IFM_ETHER|IFM_MANUAL, 0, NULL); 705 ifmedia_set(&sc->bnx_mii.mii_media, 706 IFM_ETHER|IFM_MANUAL); 707 } else { 708 ifmedia_set(&sc->bnx_mii.mii_media, 709 IFM_ETHER|IFM_AUTO); 710 } 711 712 /* Attach to the Ethernet interface list. */ 713 if_attach(ifp); 714 ether_ifattach(ifp,sc->eaddr); 715 716 callout_init(&sc->bnx_timeout); 717 718 /* Print some important debugging info. */ 719 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 720 721 goto bnx_attach_exit; 722 723 bnx_attach_fail: 724 bnx_release_resources(sc); 725 726 bnx_attach_exit: 727 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 728 } 729 730 /****************************************************************************/ 731 /* Device detach function. */ 732 /* */ 733 /* Stops the controller, resets the controller, and releases resources. */ 734 /* */ 735 /* Returns: */ 736 /* 0 on success, positive value on failure. */ 737 /****************************************************************************/ 738 #if 0 739 void 740 bnx_detach(void *xsc) 741 { 742 struct bnx_softc *sc; 743 struct ifnet *ifp = &sc->arpcom.ac_if; 744 745 sc = device_get_softc(dev); 746 747 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 748 749 /* Stop and reset the controller. */ 750 bnx_stop(sc); 751 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 752 753 ether_ifdetach(ifp); 754 755 /* If we have a child device on the MII bus remove it too. */ 756 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 757 ifmedia_removeall(&sc->bnx_ifmedia); 758 } else { 759 bus_generic_detach(dev); 760 device_delete_child(dev, sc->bnx_mii); 761 } 762 763 /* Release all remaining resources. */ 764 bnx_release_resources(sc); 765 766 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 767 768 return(0); 769 } 770 #endif 771 772 /****************************************************************************/ 773 /* Device shutdown function. */ 774 /* */ 775 /* Stops and resets the controller. */ 776 /* */ 777 /* Returns: */ 778 /* Nothing */ 779 /****************************************************************************/ 780 void 781 bnx_shutdown(void *xsc) 782 { 783 struct bnx_softc *sc = (struct bnx_softc *)xsc; 784 785 bnx_stop(sc); 786 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 787 } 788 789 /****************************************************************************/ 790 /* Indirect register read. */ 791 /* */ 792 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 793 /* configuration space. Using this mechanism avoids issues with posted */ 794 /* reads but is much slower than memory-mapped I/O. */ 795 /* */ 796 /* Returns: */ 797 /* The value of the register. */ 798 /****************************************************************************/ 799 u_int32_t 800 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 801 { 802 struct pci_attach_args *pa = &(sc->bnx_pa); 803 804 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 805 offset); 806 #ifdef BNX_DEBUG 807 { 808 u_int32_t val; 809 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 810 BNX_PCICFG_REG_WINDOW); 811 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 812 "val = 0x%08X\n", __FUNCTION__, offset, val); 813 return (val); 814 } 815 #else 816 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 817 #endif 818 } 819 820 /****************************************************************************/ 821 /* Indirect register write. */ 822 /* */ 823 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 824 /* configuration space. Using this mechanism avoids issues with posted */ 825 /* writes but is muchh slower than memory-mapped I/O. */ 826 /* */ 827 /* Returns: */ 828 /* Nothing. */ 829 /****************************************************************************/ 830 void 831 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 832 { 833 struct pci_attach_args *pa = &(sc->bnx_pa); 834 835 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 836 __FUNCTION__, offset, val); 837 838 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 839 offset); 840 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 841 } 842 843 /****************************************************************************/ 844 /* Context memory write. */ 845 /* */ 846 /* The NetXtreme II controller uses context memory to track connection */ 847 /* information for L2 and higher network protocols. */ 848 /* */ 849 /* Returns: */ 850 /* Nothing. */ 851 /****************************************************************************/ 852 void 853 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, 854 u_int32_t val) 855 { 856 857 DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 858 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 859 860 offset += cid_addr; 861 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 862 REG_WR(sc, BNX_CTX_DATA, val); 863 } 864 865 /****************************************************************************/ 866 /* PHY register read. */ 867 /* */ 868 /* Implements register reads on the MII bus. */ 869 /* */ 870 /* Returns: */ 871 /* The value of the register. */ 872 /****************************************************************************/ 873 int 874 bnx_miibus_read_reg(struct device *dev, int phy, int reg) 875 { 876 struct bnx_softc *sc = (struct bnx_softc *)dev; 877 u_int32_t val; 878 int i; 879 880 /* Make sure we are accessing the correct PHY address. */ 881 if (phy != sc->bnx_phy_addr) { 882 DBPRINT(sc, BNX_VERBOSE, 883 "Invalid PHY address %d for PHY read!\n", phy); 884 return(0); 885 } 886 887 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 888 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 889 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 890 891 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 892 REG_RD(sc, BNX_EMAC_MDIO_MODE); 893 894 DELAY(40); 895 } 896 897 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 898 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 899 BNX_EMAC_MDIO_COMM_START_BUSY; 900 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 901 902 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 903 DELAY(10); 904 905 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 906 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 907 DELAY(5); 908 909 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 910 val &= BNX_EMAC_MDIO_COMM_DATA; 911 912 break; 913 } 914 } 915 916 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 917 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 918 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 919 val = 0x0; 920 } else 921 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 922 923 DBPRINT(sc, BNX_EXCESSIVE, 924 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __FUNCTION__, phy, 925 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 926 927 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 928 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 929 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 930 931 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 932 REG_RD(sc, BNX_EMAC_MDIO_MODE); 933 934 DELAY(40); 935 } 936 937 return (val & 0xffff); 938 } 939 940 /****************************************************************************/ 941 /* PHY register write. */ 942 /* */ 943 /* Implements register writes on the MII bus. */ 944 /* */ 945 /* Returns: */ 946 /* The value of the register. */ 947 /****************************************************************************/ 948 void 949 bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val) 950 { 951 struct bnx_softc *sc = (struct bnx_softc *)dev; 952 u_int32_t val1; 953 int i; 954 955 /* Make sure we are accessing the correct PHY address. */ 956 if (phy != sc->bnx_phy_addr) { 957 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 958 phy); 959 return; 960 } 961 962 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 963 "val = 0x%04X\n", __FUNCTION__, 964 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 965 966 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 967 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 968 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 969 970 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 971 REG_RD(sc, BNX_EMAC_MDIO_MODE); 972 973 DELAY(40); 974 } 975 976 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 977 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 978 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 979 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 980 981 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 982 DELAY(10); 983 984 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 985 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 986 DELAY(5); 987 break; 988 } 989 } 990 991 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 992 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 993 __LINE__); 994 } 995 996 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 997 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 998 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 999 1000 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1001 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1002 1003 DELAY(40); 1004 } 1005 } 1006 1007 /****************************************************************************/ 1008 /* MII bus status change. */ 1009 /* */ 1010 /* Called by the MII bus driver when the PHY establishes link to set the */ 1011 /* MAC interface registers. */ 1012 /* */ 1013 /* Returns: */ 1014 /* Nothing. */ 1015 /****************************************************************************/ 1016 void 1017 bnx_miibus_statchg(struct device *dev) 1018 { 1019 struct bnx_softc *sc = (struct bnx_softc *)dev; 1020 struct mii_data *mii = &sc->bnx_mii; 1021 1022 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT); 1023 1024 /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ 1025 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 1026 DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n"); 1027 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII); 1028 } else { 1029 DBPRINT(sc, BNX_INFO, "Setting MII interface.\n"); 1030 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII); 1031 } 1032 1033 /* Set half or full duplex based on the duplicity 1034 * negotiated by the PHY. 1035 */ 1036 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1037 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1038 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1039 } else { 1040 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1041 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1042 } 1043 } 1044 1045 /****************************************************************************/ 1046 /* Acquire NVRAM lock. */ 1047 /* */ 1048 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1049 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1050 /* for use by the driver. */ 1051 /* */ 1052 /* Returns: */ 1053 /* 0 on success, positive value on failure. */ 1054 /****************************************************************************/ 1055 int 1056 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1057 { 1058 u_int32_t val; 1059 int j; 1060 1061 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1062 1063 /* Request access to the flash interface. */ 1064 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1065 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1066 val = REG_RD(sc, BNX_NVM_SW_ARB); 1067 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1068 break; 1069 1070 DELAY(5); 1071 } 1072 1073 if (j >= NVRAM_TIMEOUT_COUNT) { 1074 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1075 return (EBUSY); 1076 } 1077 1078 return (0); 1079 } 1080 1081 /****************************************************************************/ 1082 /* Release NVRAM lock. */ 1083 /* */ 1084 /* When the caller is finished accessing NVRAM the lock must be released. */ 1085 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1086 /* for use by the driver. */ 1087 /* */ 1088 /* Returns: */ 1089 /* 0 on success, positive value on failure. */ 1090 /****************************************************************************/ 1091 int 1092 bnx_release_nvram_lock(struct bnx_softc *sc) 1093 { 1094 int j; 1095 u_int32_t val; 1096 1097 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1098 1099 /* Relinquish nvram interface. */ 1100 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1101 1102 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1103 val = REG_RD(sc, BNX_NVM_SW_ARB); 1104 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1105 break; 1106 1107 DELAY(5); 1108 } 1109 1110 if (j >= NVRAM_TIMEOUT_COUNT) { 1111 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1112 return (EBUSY); 1113 } 1114 1115 return (0); 1116 } 1117 1118 #ifdef BNX_NVRAM_WRITE_SUPPORT 1119 /****************************************************************************/ 1120 /* Enable NVRAM write access. */ 1121 /* */ 1122 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1123 /* */ 1124 /* Returns: */ 1125 /* 0 on success, positive value on failure. */ 1126 /****************************************************************************/ 1127 int 1128 bnx_enable_nvram_write(struct bnx_softc *sc) 1129 { 1130 u_int32_t val; 1131 1132 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1133 1134 val = REG_RD(sc, BNX_MISC_CFG); 1135 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1136 1137 if (!sc->bnx_flash_info->buffered) { 1138 int j; 1139 1140 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1141 REG_WR(sc, BNX_NVM_COMMAND, 1142 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1143 1144 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1145 DELAY(5); 1146 1147 val = REG_RD(sc, BNX_NVM_COMMAND); 1148 if (val & BNX_NVM_COMMAND_DONE) 1149 break; 1150 } 1151 1152 if (j >= NVRAM_TIMEOUT_COUNT) { 1153 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1154 return (EBUSY); 1155 } 1156 } 1157 1158 return (0); 1159 } 1160 1161 /****************************************************************************/ 1162 /* Disable NVRAM write access. */ 1163 /* */ 1164 /* When the caller is finished writing to NVRAM write access must be */ 1165 /* disabled. */ 1166 /* */ 1167 /* Returns: */ 1168 /* Nothing. */ 1169 /****************************************************************************/ 1170 void 1171 bnx_disable_nvram_write(struct bnx_softc *sc) 1172 { 1173 u_int32_t val; 1174 1175 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1176 1177 val = REG_RD(sc, BNX_MISC_CFG); 1178 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1179 } 1180 #endif 1181 1182 /****************************************************************************/ 1183 /* Enable NVRAM access. */ 1184 /* */ 1185 /* Before accessing NVRAM for read or write operations the caller must */ 1186 /* enabled NVRAM access. */ 1187 /* */ 1188 /* Returns: */ 1189 /* Nothing. */ 1190 /****************************************************************************/ 1191 void 1192 bnx_enable_nvram_access(struct bnx_softc *sc) 1193 { 1194 u_int32_t val; 1195 1196 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1197 1198 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1199 /* Enable both bits, even on read. */ 1200 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1201 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1202 } 1203 1204 /****************************************************************************/ 1205 /* Disable NVRAM access. */ 1206 /* */ 1207 /* When the caller is finished accessing NVRAM access must be disabled. */ 1208 /* */ 1209 /* Returns: */ 1210 /* Nothing. */ 1211 /****************************************************************************/ 1212 void 1213 bnx_disable_nvram_access(struct bnx_softc *sc) 1214 { 1215 u_int32_t val; 1216 1217 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1218 1219 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1220 1221 /* Disable both bits, even after read. */ 1222 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1223 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1224 } 1225 1226 #ifdef BNX_NVRAM_WRITE_SUPPORT 1227 /****************************************************************************/ 1228 /* Erase NVRAM page before writing. */ 1229 /* */ 1230 /* Non-buffered flash parts require that a page be erased before it is */ 1231 /* written. */ 1232 /* */ 1233 /* Returns: */ 1234 /* 0 on success, positive value on failure. */ 1235 /****************************************************************************/ 1236 int 1237 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1238 { 1239 u_int32_t cmd; 1240 int j; 1241 1242 /* Buffered flash doesn't require an erase. */ 1243 if (sc->bnx_flash_info->buffered) 1244 return (0); 1245 1246 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1247 1248 /* Build an erase command. */ 1249 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1250 BNX_NVM_COMMAND_DOIT; 1251 1252 /* 1253 * Clear the DONE bit separately, set the NVRAM adress to erase, 1254 * and issue the erase command. 1255 */ 1256 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1257 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1258 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1259 1260 /* Wait for completion. */ 1261 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1262 u_int32_t val; 1263 1264 DELAY(5); 1265 1266 val = REG_RD(sc, BNX_NVM_COMMAND); 1267 if (val & BNX_NVM_COMMAND_DONE) 1268 break; 1269 } 1270 1271 if (j >= NVRAM_TIMEOUT_COUNT) { 1272 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1273 return (EBUSY); 1274 } 1275 1276 return (0); 1277 } 1278 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1279 1280 /****************************************************************************/ 1281 /* Read a dword (32 bits) from NVRAM. */ 1282 /* */ 1283 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1284 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1285 /* */ 1286 /* Returns: */ 1287 /* 0 on success and the 32 bit value read, positive value on failure. */ 1288 /****************************************************************************/ 1289 int 1290 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1291 u_int8_t *ret_val, u_int32_t cmd_flags) 1292 { 1293 u_int32_t cmd; 1294 int i, rc = 0; 1295 1296 /* Build the command word. */ 1297 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1298 1299 /* Calculate the offset for buffered flash. */ 1300 if (sc->bnx_flash_info->buffered) 1301 offset = ((offset / sc->bnx_flash_info->page_size) << 1302 sc->bnx_flash_info->page_bits) + 1303 (offset % sc->bnx_flash_info->page_size); 1304 1305 /* 1306 * Clear the DONE bit separately, set the address to read, 1307 * and issue the read. 1308 */ 1309 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1310 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1311 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1312 1313 /* Wait for completion. */ 1314 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1315 u_int32_t val; 1316 1317 DELAY(5); 1318 1319 val = REG_RD(sc, BNX_NVM_COMMAND); 1320 if (val & BNX_NVM_COMMAND_DONE) { 1321 val = REG_RD(sc, BNX_NVM_READ); 1322 1323 val = bnx_be32toh(val); 1324 memcpy(ret_val, &val, 4); 1325 break; 1326 } 1327 } 1328 1329 /* Check for errors. */ 1330 if (i >= NVRAM_TIMEOUT_COUNT) { 1331 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1332 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1333 rc = EBUSY; 1334 } 1335 1336 return(rc); 1337 } 1338 1339 #ifdef BNX_NVRAM_WRITE_SUPPORT 1340 /****************************************************************************/ 1341 /* Write a dword (32 bits) to NVRAM. */ 1342 /* */ 1343 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1344 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1345 /* enabled NVRAM write access. */ 1346 /* */ 1347 /* Returns: */ 1348 /* 0 on success, positive value on failure. */ 1349 /****************************************************************************/ 1350 int 1351 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1352 u_int32_t cmd_flags) 1353 { 1354 u_int32_t cmd, val32; 1355 int j; 1356 1357 /* Build the command word. */ 1358 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1359 1360 /* Calculate the offset for buffered flash. */ 1361 if (sc->bnx_flash_info->buffered) 1362 offset = ((offset / sc->bnx_flash_info->page_size) << 1363 sc->bnx_flash_info->page_bits) + 1364 (offset % sc->bnx_flash_info->page_size); 1365 1366 /* 1367 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1368 * set the NVRAM address to write, and issue the write command 1369 */ 1370 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1371 memcpy(&val32, val, 4); 1372 val32 = htobe32(val32); 1373 REG_WR(sc, BNX_NVM_WRITE, val32); 1374 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1375 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1376 1377 /* Wait for completion. */ 1378 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1379 DELAY(5); 1380 1381 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1382 break; 1383 } 1384 if (j >= NVRAM_TIMEOUT_COUNT) { 1385 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1386 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1387 return (EBUSY); 1388 } 1389 1390 return (0); 1391 } 1392 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1393 1394 /****************************************************************************/ 1395 /* Initialize NVRAM access. */ 1396 /* */ 1397 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1398 /* access that device. */ 1399 /* */ 1400 /* Returns: */ 1401 /* 0 on success, positive value on failure. */ 1402 /****************************************************************************/ 1403 int 1404 bnx_init_nvram(struct bnx_softc *sc) 1405 { 1406 u_int32_t val; 1407 int j, entry_count, rc; 1408 struct flash_spec *flash; 1409 1410 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1411 1412 /* Determine the selected interface. */ 1413 val = REG_RD(sc, BNX_NVM_CFG1); 1414 1415 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1416 1417 rc = 0; 1418 1419 /* 1420 * Flash reconfiguration is required to support additional 1421 * NVRAM devices not directly supported in hardware. 1422 * Check if the flash interface was reconfigured 1423 * by the bootcode. 1424 */ 1425 1426 if (val & 0x40000000) { 1427 /* Flash interface reconfigured by bootcode. */ 1428 1429 DBPRINT(sc,BNX_INFO_LOAD, 1430 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1431 1432 for (j = 0, flash = &flash_table[0]; j < entry_count; 1433 j++, flash++) { 1434 if ((val & FLASH_BACKUP_STRAP_MASK) == 1435 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1436 sc->bnx_flash_info = flash; 1437 break; 1438 } 1439 } 1440 } else { 1441 /* Flash interface not yet reconfigured. */ 1442 u_int32_t mask; 1443 1444 DBPRINT(sc,BNX_INFO_LOAD, 1445 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1446 1447 if (val & (1 << 23)) 1448 mask = FLASH_BACKUP_STRAP_MASK; 1449 else 1450 mask = FLASH_STRAP_MASK; 1451 1452 /* Look for the matching NVRAM device configuration data. */ 1453 for (j = 0, flash = &flash_table[0]; j < entry_count; 1454 j++, flash++) { 1455 /* Check if the dev matches any of the known devices. */ 1456 if ((val & mask) == (flash->strapping & mask)) { 1457 /* Found a device match. */ 1458 sc->bnx_flash_info = flash; 1459 1460 /* Request access to the flash interface. */ 1461 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1462 return (rc); 1463 1464 /* Reconfigure the flash interface. */ 1465 bnx_enable_nvram_access(sc); 1466 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1467 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1468 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1469 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1470 bnx_disable_nvram_access(sc); 1471 bnx_release_nvram_lock(sc); 1472 1473 break; 1474 } 1475 } 1476 } 1477 1478 /* Check if a matching device was found. */ 1479 if (j == entry_count) { 1480 sc->bnx_flash_info = NULL; 1481 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1482 __FILE__, __LINE__); 1483 rc = ENODEV; 1484 } 1485 1486 /* Write the flash config data to the shared memory interface. */ 1487 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1488 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1489 if (val) 1490 sc->bnx_flash_size = val; 1491 else 1492 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1493 1494 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1495 "0x%08X\n", sc->bnx_flash_info->total_size); 1496 1497 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1498 1499 return (rc); 1500 } 1501 1502 /****************************************************************************/ 1503 /* Read an arbitrary range of data from NVRAM. */ 1504 /* */ 1505 /* Prepares the NVRAM interface for access and reads the requested data */ 1506 /* into the supplied buffer. */ 1507 /* */ 1508 /* Returns: */ 1509 /* 0 on success and the data read, positive value on failure. */ 1510 /****************************************************************************/ 1511 int 1512 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1513 int buf_size) 1514 { 1515 int rc = 0; 1516 u_int32_t cmd_flags, offset32, len32, extra; 1517 1518 if (buf_size == 0) 1519 return (0); 1520 1521 /* Request access to the flash interface. */ 1522 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1523 return (rc); 1524 1525 /* Enable access to flash interface */ 1526 bnx_enable_nvram_access(sc); 1527 1528 len32 = buf_size; 1529 offset32 = offset; 1530 extra = 0; 1531 1532 cmd_flags = 0; 1533 1534 if (offset32 & 3) { 1535 u_int8_t buf[4]; 1536 u_int32_t pre_len; 1537 1538 offset32 &= ~3; 1539 pre_len = 4 - (offset & 3); 1540 1541 if (pre_len >= len32) { 1542 pre_len = len32; 1543 cmd_flags = 1544 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1545 } else 1546 cmd_flags = BNX_NVM_COMMAND_FIRST; 1547 1548 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1549 1550 if (rc) 1551 return (rc); 1552 1553 memcpy(ret_buf, buf + (offset & 3), pre_len); 1554 1555 offset32 += 4; 1556 ret_buf += pre_len; 1557 len32 -= pre_len; 1558 } 1559 1560 if (len32 & 3) { 1561 extra = 4 - (len32 & 3); 1562 len32 = (len32 + 4) & ~3; 1563 } 1564 1565 if (len32 == 4) { 1566 u_int8_t buf[4]; 1567 1568 if (cmd_flags) 1569 cmd_flags = BNX_NVM_COMMAND_LAST; 1570 else 1571 cmd_flags = 1572 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1573 1574 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1575 1576 memcpy(ret_buf, buf, 4 - extra); 1577 } else if (len32 > 0) { 1578 u_int8_t buf[4]; 1579 1580 /* Read the first word. */ 1581 if (cmd_flags) 1582 cmd_flags = 0; 1583 else 1584 cmd_flags = BNX_NVM_COMMAND_FIRST; 1585 1586 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1587 1588 /* Advance to the next dword. */ 1589 offset32 += 4; 1590 ret_buf += 4; 1591 len32 -= 4; 1592 1593 while (len32 > 4 && rc == 0) { 1594 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1595 1596 /* Advance to the next dword. */ 1597 offset32 += 4; 1598 ret_buf += 4; 1599 len32 -= 4; 1600 } 1601 1602 if (rc) 1603 return (rc); 1604 1605 cmd_flags = BNX_NVM_COMMAND_LAST; 1606 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1607 1608 memcpy(ret_buf, buf, 4 - extra); 1609 } 1610 1611 /* Disable access to flash interface and release the lock. */ 1612 bnx_disable_nvram_access(sc); 1613 bnx_release_nvram_lock(sc); 1614 1615 return (rc); 1616 } 1617 1618 #ifdef BNX_NVRAM_WRITE_SUPPORT 1619 /****************************************************************************/ 1620 /* Write an arbitrary range of data from NVRAM. */ 1621 /* */ 1622 /* Prepares the NVRAM interface for write access and writes the requested */ 1623 /* data from the supplied buffer. The caller is responsible for */ 1624 /* calculating any appropriate CRCs. */ 1625 /* */ 1626 /* Returns: */ 1627 /* 0 on success, positive value on failure. */ 1628 /****************************************************************************/ 1629 int 1630 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1631 int buf_size) 1632 { 1633 u_int32_t written, offset32, len32; 1634 u_int8_t *buf, start[4], end[4]; 1635 int rc = 0; 1636 int align_start, align_end; 1637 1638 buf = data_buf; 1639 offset32 = offset; 1640 len32 = buf_size; 1641 align_start = align_end = 0; 1642 1643 if ((align_start = (offset32 & 3))) { 1644 offset32 &= ~3; 1645 len32 += align_start; 1646 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1647 return (rc); 1648 } 1649 1650 if (len32 & 3) { 1651 if ((len32 > 4) || !align_start) { 1652 align_end = 4 - (len32 & 3); 1653 len32 += align_end; 1654 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1655 end, 4))) { 1656 return (rc); 1657 } 1658 } 1659 } 1660 1661 if (align_start || align_end) { 1662 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1663 if (buf == 0) 1664 return (ENOMEM); 1665 1666 if (align_start) 1667 memcpy(buf, start, 4); 1668 1669 if (align_end) 1670 memcpy(buf + len32 - 4, end, 4); 1671 1672 memcpy(buf + align_start, data_buf, buf_size); 1673 } 1674 1675 written = 0; 1676 while ((written < len32) && (rc == 0)) { 1677 u_int32_t page_start, page_end, data_start, data_end; 1678 u_int32_t addr, cmd_flags; 1679 int i; 1680 u_int8_t flash_buffer[264]; 1681 1682 /* Find the page_start addr */ 1683 page_start = offset32 + written; 1684 page_start -= (page_start % sc->bnx_flash_info->page_size); 1685 /* Find the page_end addr */ 1686 page_end = page_start + sc->bnx_flash_info->page_size; 1687 /* Find the data_start addr */ 1688 data_start = (written == 0) ? offset32 : page_start; 1689 /* Find the data_end addr */ 1690 data_end = (page_end > offset32 + len32) ? 1691 (offset32 + len32) : page_end; 1692 1693 /* Request access to the flash interface. */ 1694 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1695 goto nvram_write_end; 1696 1697 /* Enable access to flash interface */ 1698 bnx_enable_nvram_access(sc); 1699 1700 cmd_flags = BNX_NVM_COMMAND_FIRST; 1701 if (sc->bnx_flash_info->buffered == 0) { 1702 int j; 1703 1704 /* Read the whole page into the buffer 1705 * (non-buffer flash only) */ 1706 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1707 if (j == (sc->bnx_flash_info->page_size - 4)) 1708 cmd_flags |= BNX_NVM_COMMAND_LAST; 1709 1710 rc = bnx_nvram_read_dword(sc, 1711 page_start + j, 1712 &flash_buffer[j], 1713 cmd_flags); 1714 1715 if (rc) 1716 goto nvram_write_end; 1717 1718 cmd_flags = 0; 1719 } 1720 } 1721 1722 /* Enable writes to flash interface (unlock write-protect) */ 1723 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1724 goto nvram_write_end; 1725 1726 /* Erase the page */ 1727 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1728 goto nvram_write_end; 1729 1730 /* Re-enable the write again for the actual write */ 1731 bnx_enable_nvram_write(sc); 1732 1733 /* Loop to write back the buffer data from page_start to 1734 * data_start */ 1735 i = 0; 1736 if (sc->bnx_flash_info->buffered == 0) { 1737 for (addr = page_start; addr < data_start; 1738 addr += 4, i += 4) { 1739 1740 rc = bnx_nvram_write_dword(sc, addr, 1741 &flash_buffer[i], cmd_flags); 1742 1743 if (rc != 0) 1744 goto nvram_write_end; 1745 1746 cmd_flags = 0; 1747 } 1748 } 1749 1750 /* Loop to write the new data from data_start to data_end */ 1751 for (addr = data_start; addr < data_end; addr += 4, i++) { 1752 if ((addr == page_end - 4) || 1753 ((sc->bnx_flash_info->buffered) && 1754 (addr == data_end - 4))) { 1755 1756 cmd_flags |= BNX_NVM_COMMAND_LAST; 1757 } 1758 1759 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1760 1761 if (rc != 0) 1762 goto nvram_write_end; 1763 1764 cmd_flags = 0; 1765 buf += 4; 1766 } 1767 1768 /* Loop to write back the buffer data from data_end 1769 * to page_end */ 1770 if (sc->bnx_flash_info->buffered == 0) { 1771 for (addr = data_end; addr < page_end; 1772 addr += 4, i += 4) { 1773 1774 if (addr == page_end-4) 1775 cmd_flags = BNX_NVM_COMMAND_LAST; 1776 1777 rc = bnx_nvram_write_dword(sc, addr, 1778 &flash_buffer[i], cmd_flags); 1779 1780 if (rc != 0) 1781 goto nvram_write_end; 1782 1783 cmd_flags = 0; 1784 } 1785 } 1786 1787 /* Disable writes to flash interface (lock write-protect) */ 1788 bnx_disable_nvram_write(sc); 1789 1790 /* Disable access to flash interface */ 1791 bnx_disable_nvram_access(sc); 1792 bnx_release_nvram_lock(sc); 1793 1794 /* Increment written */ 1795 written += data_end - data_start; 1796 } 1797 1798 nvram_write_end: 1799 if (align_start || align_end) 1800 free(buf, M_DEVBUF); 1801 1802 return (rc); 1803 } 1804 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1805 1806 /****************************************************************************/ 1807 /* Verifies that NVRAM is accessible and contains valid data. */ 1808 /* */ 1809 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1810 /* correct. */ 1811 /* */ 1812 /* Returns: */ 1813 /* 0 on success, positive value on failure. */ 1814 /****************************************************************************/ 1815 int 1816 bnx_nvram_test(struct bnx_softc *sc) 1817 { 1818 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1819 u_int8_t *data = (u_int8_t *) buf; 1820 int rc = 0; 1821 u_int32_t magic, csum; 1822 1823 /* 1824 * Check that the device NVRAM is valid by reading 1825 * the magic value at offset 0. 1826 */ 1827 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1828 goto bnx_nvram_test_done; 1829 1830 magic = bnx_be32toh(buf[0]); 1831 if (magic != BNX_NVRAM_MAGIC) { 1832 rc = ENODEV; 1833 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1834 "Expected: 0x%08X, Found: 0x%08X\n", 1835 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1836 goto bnx_nvram_test_done; 1837 } 1838 1839 /* 1840 * Verify that the device NVRAM includes valid 1841 * configuration data. 1842 */ 1843 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1844 goto bnx_nvram_test_done; 1845 1846 csum = ether_crc32_le(data, 0x100); 1847 if (csum != BNX_CRC32_RESIDUAL) { 1848 rc = ENODEV; 1849 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1850 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1851 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1852 goto bnx_nvram_test_done; 1853 } 1854 1855 csum = ether_crc32_le(data + 0x100, 0x100); 1856 if (csum != BNX_CRC32_RESIDUAL) { 1857 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1858 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1859 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1860 rc = ENODEV; 1861 } 1862 1863 bnx_nvram_test_done: 1864 return (rc); 1865 } 1866 1867 /****************************************************************************/ 1868 /* Free any DMA memory owned by the driver. */ 1869 /* */ 1870 /* Scans through each data structre that requires DMA memory and frees */ 1871 /* the memory if allocated. */ 1872 /* */ 1873 /* Returns: */ 1874 /* Nothing. */ 1875 /****************************************************************************/ 1876 void 1877 bnx_dma_free(struct bnx_softc *sc) 1878 { 1879 int i; 1880 1881 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1882 1883 /* Destroy the status block. */ 1884 if (sc->status_block != NULL && sc->status_map != NULL) { 1885 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 1886 bus_dmamem_unmap(sc->bnx_dmatag, (caddr_t)sc->status_block, 1887 BNX_STATUS_BLK_SZ); 1888 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 1889 sc->status_rseg); 1890 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 1891 sc->status_block = NULL; 1892 sc->status_map = NULL; 1893 } 1894 1895 /* Destroy the statistics block. */ 1896 if (sc->stats_block != NULL && sc->stats_map != NULL) { 1897 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 1898 bus_dmamem_unmap(sc->bnx_dmatag, (caddr_t)sc->stats_block, 1899 BNX_STATS_BLK_SZ); 1900 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 1901 sc->stats_rseg); 1902 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 1903 sc->stats_block = NULL; 1904 sc->stats_map = NULL; 1905 } 1906 1907 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 1908 for (i = 0; i < TX_PAGES; i++ ) { 1909 if (sc->tx_bd_chain[i] != NULL && 1910 sc->tx_bd_chain_map[i] != NULL) { 1911 bus_dmamap_unload(sc->bnx_dmatag, 1912 sc->tx_bd_chain_map[i]); 1913 bus_dmamem_unmap(sc->bnx_dmatag, 1914 (caddr_t)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 1915 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 1916 sc->tx_bd_chain_rseg[i]); 1917 bus_dmamap_destroy(sc->bnx_dmatag, 1918 sc->tx_bd_chain_map[i]); 1919 sc->tx_bd_chain[i] = NULL; 1920 sc->tx_bd_chain_map[i] = NULL; 1921 } 1922 } 1923 1924 /* Unload and destroy the TX mbuf maps. */ 1925 for (i = 0; i < TOTAL_TX_BD; i++) { 1926 if (sc->tx_mbuf_map[i] != NULL) { 1927 bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1928 bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1929 } 1930 } 1931 1932 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 1933 for (i = 0; i < RX_PAGES; i++ ) { 1934 if (sc->rx_bd_chain[i] != NULL && 1935 sc->rx_bd_chain_map[i] != NULL) { 1936 bus_dmamap_unload(sc->bnx_dmatag, 1937 sc->rx_bd_chain_map[i]); 1938 bus_dmamem_unmap(sc->bnx_dmatag, 1939 (caddr_t)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 1940 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 1941 sc->rx_bd_chain_rseg[i]); 1942 1943 bus_dmamap_destroy(sc->bnx_dmatag, 1944 sc->rx_bd_chain_map[i]); 1945 sc->rx_bd_chain[i] = NULL; 1946 sc->rx_bd_chain_map[i] = NULL; 1947 } 1948 } 1949 1950 /* Unload and destroy the RX mbuf maps. */ 1951 for (i = 0; i < TOTAL_RX_BD; i++) { 1952 if (sc->rx_mbuf_map[i] != NULL) { 1953 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1954 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1955 } 1956 } 1957 1958 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1959 } 1960 1961 /****************************************************************************/ 1962 /* Map TX buffers into TX buffer descriptors. */ 1963 /* */ 1964 /* Given a series of DMA memory containting an outgoing frame, map the */ 1965 /* segments into the tx_bd structure used by the hardware. */ 1966 /* */ 1967 /* Returns: */ 1968 /* Nothing. */ 1969 /****************************************************************************/ 1970 void 1971 bnx_dma_map_tx_desc(void *arg, bus_dmamap_t map) 1972 { 1973 struct bnx_dmamap_arg *map_arg; 1974 struct bnx_softc *sc; 1975 struct tx_bd *txbd = NULL; 1976 int i = 0, nseg; 1977 u_int16_t prod, chain_prod; 1978 u_int32_t prod_bseq, addr; 1979 #ifdef BNX_DEBUG 1980 u_int16_t debug_prod; 1981 #endif 1982 1983 map_arg = arg; 1984 sc = map_arg->sc; 1985 nseg = map->dm_nsegs; 1986 1987 /* Signal error to caller if there's too many segments */ 1988 if (nseg > map_arg->maxsegs) { 1989 DBPRINT(sc, BNX_WARN, "%s(): Mapped TX descriptors: max segs " 1990 "= %d, " "actual segs = %d\n", 1991 __FUNCTION__, map_arg->maxsegs, nseg); 1992 1993 map_arg->maxsegs = 0; 1994 return; 1995 } 1996 1997 /* prod points to an empty tx_bd at this point. */ 1998 prod = map_arg->prod; 1999 chain_prod = map_arg->chain_prod; 2000 prod_bseq = map_arg->prod_bseq; 2001 2002 #ifdef BNX_DEBUG 2003 debug_prod = chain_prod; 2004 #endif 2005 2006 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: prod = 0x%04X, chain_prod " 2007 "= %04X, " "prod_bseq = 0x%08X\n", 2008 __FUNCTION__, prod, chain_prod, prod_bseq); 2009 2010 /* 2011 * Cycle through each mbuf segment that makes up 2012 * the outgoing frame, gathering the mapping info 2013 * for that segment and creating a tx_bd for the 2014 * mbuf. 2015 */ 2016 2017 txbd = &map_arg->tx_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 2018 2019 /* Setup the first tx_bd for the first segment. */ 2020 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 2021 txbd->tx_bd_haddr_lo = htole32(addr); 2022 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 2023 txbd->tx_bd_haddr_hi = htole32(addr); 2024 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 2025 txbd->tx_bd_vlan_tag_flags = htole16(map_arg->tx_flags | 2026 TX_BD_FLAGS_START); 2027 prod_bseq += map->dm_segs[i].ds_len; 2028 2029 bus_dmamap_sync(sc->bnx_dmatag, 2030 sc->tx_bd_chain_map[TX_PAGE(chain_prod)], 2031 sizeof(struct tx_bd) * TX_IDX(chain_prod), 2032 sizeof(struct tx_bd), BUS_DMASYNC_PREWRITE); 2033 2034 /* Setup any remaing segments. */ 2035 for (i = 1; i < nseg; i++) { 2036 prod = NEXT_TX_BD(prod); 2037 chain_prod = TX_CHAIN_IDX(prod); 2038 2039 txbd = 2040 &map_arg->tx_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 2041 2042 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 2043 txbd->tx_bd_haddr_lo = htole32(addr); 2044 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 2045 txbd->tx_bd_haddr_hi = htole32(addr); 2046 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 2047 txbd->tx_bd_vlan_tag_flags = htole16(map_arg->tx_flags); 2048 2049 prod_bseq += map->dm_segs[i].ds_len; 2050 bus_dmamap_sync(sc->bnx_dmatag, 2051 sc->tx_bd_chain_map[TX_PAGE(chain_prod)], 2052 sizeof(struct tx_bd) * TX_IDX(chain_prod), 2053 sizeof(struct tx_bd), BUS_DMASYNC_PREWRITE); 2054 } 2055 2056 /* Set the END flag on the last TX buffer descriptor. */ 2057 txbd->tx_bd_vlan_tag_flags |= htole16(TX_BD_FLAGS_END); 2058 bus_dmamap_sync(sc->bnx_dmatag, 2059 sc->tx_bd_chain_map[TX_PAGE(chain_prod)], 2060 sizeof(struct tx_bd) * TX_IDX(chain_prod), 2061 sizeof(struct tx_bd), BUS_DMASYNC_PREWRITE); 2062 2063 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg)); 2064 2065 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: prod = 0x%04X, chain_prod " 2066 "= %04X, " "prod_bseq = 0x%08X\n", 2067 __FUNCTION__, prod, chain_prod, prod_bseq); 2068 2069 /* prod points to the last tx_bd at this point. */ 2070 map_arg->maxsegs = nseg; 2071 map_arg->prod = prod; 2072 map_arg->chain_prod = chain_prod; 2073 map_arg->prod_bseq = prod_bseq; 2074 } 2075 2076 /****************************************************************************/ 2077 /* Allocate any DMA memory needed by the driver. */ 2078 /* */ 2079 /* Allocates DMA memory needed for the various global structures needed by */ 2080 /* hardware. */ 2081 /* */ 2082 /* Returns: */ 2083 /* 0 for success, positive value for failure. */ 2084 /****************************************************************************/ 2085 int 2086 bnx_dma_alloc(struct bnx_softc *sc) 2087 { 2088 int i, rc = 0; 2089 2090 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2091 2092 /* 2093 * Allocate DMA memory for the status block, map the memory into DMA 2094 * space, and fetch the physical address of the block. 2095 */ 2096 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2097 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2098 aprint_error("%s: Could not create status block DMA map!\n", 2099 sc->bnx_dev.dv_xname); 2100 rc = ENOMEM; 2101 goto bnx_dma_alloc_exit; 2102 } 2103 2104 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2105 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2106 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2107 aprint_error( 2108 "%s: Could not allocate status block DMA memory!\n", 2109 sc->bnx_dev.dv_xname); 2110 rc = ENOMEM; 2111 goto bnx_dma_alloc_exit; 2112 } 2113 2114 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2115 BNX_STATUS_BLK_SZ, (caddr_t *)&sc->status_block, BUS_DMA_NOWAIT)) { 2116 aprint_error("%s: Could not map status block DMA memory!\n", 2117 sc->bnx_dev.dv_xname); 2118 rc = ENOMEM; 2119 goto bnx_dma_alloc_exit; 2120 } 2121 2122 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2123 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2124 aprint_error("%s: Could not load status block DMA memory!\n", 2125 sc->bnx_dev.dv_xname); 2126 rc = ENOMEM; 2127 goto bnx_dma_alloc_exit; 2128 } 2129 2130 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2131 bzero(sc->status_block, BNX_STATUS_BLK_SZ); 2132 2133 /* DRC - Fix for 64 bit addresses. */ 2134 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2135 (u_int32_t) sc->status_block_paddr); 2136 2137 /* 2138 * Allocate DMA memory for the statistics block, map the memory into 2139 * DMA space, and fetch the physical address of the block. 2140 */ 2141 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2142 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2143 aprint_error("%s: Could not create stats block DMA map!\n", 2144 sc->bnx_dev.dv_xname); 2145 rc = ENOMEM; 2146 goto bnx_dma_alloc_exit; 2147 } 2148 2149 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2150 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2151 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2152 aprint_error("%s: Could not allocate stats block DMA memory!\n", 2153 sc->bnx_dev.dv_xname); 2154 rc = ENOMEM; 2155 goto bnx_dma_alloc_exit; 2156 } 2157 2158 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2159 BNX_STATS_BLK_SZ, (caddr_t *)&sc->stats_block, BUS_DMA_NOWAIT)) { 2160 aprint_error("%s: Could not map stats block DMA memory!\n", 2161 sc->bnx_dev.dv_xname); 2162 rc = ENOMEM; 2163 goto bnx_dma_alloc_exit; 2164 } 2165 2166 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2167 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2168 aprint_error("%s: Could not load status block DMA memory!\n", 2169 sc->bnx_dev.dv_xname); 2170 rc = ENOMEM; 2171 goto bnx_dma_alloc_exit; 2172 } 2173 2174 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2175 bzero(sc->stats_block, BNX_STATS_BLK_SZ); 2176 2177 /* DRC - Fix for 64 bit address. */ 2178 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2179 (u_int32_t) sc->stats_block_paddr); 2180 2181 /* 2182 * Allocate DMA memory for the TX buffer descriptor chain, 2183 * and fetch the physical address of the block. 2184 */ 2185 for (i = 0; i < TX_PAGES; i++) { 2186 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2187 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2188 &sc->tx_bd_chain_map[i])) { 2189 aprint_error( 2190 "%s: Could not create Tx desc %d DMA map!\n", 2191 sc->bnx_dev.dv_xname, i); 2192 rc = ENOMEM; 2193 goto bnx_dma_alloc_exit; 2194 } 2195 2196 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2197 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2198 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2199 aprint_error( 2200 "%s: Could not allocate TX desc %d DMA memory!\n", 2201 sc->bnx_dev.dv_xname, i); 2202 rc = ENOMEM; 2203 goto bnx_dma_alloc_exit; 2204 } 2205 2206 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2207 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2208 (caddr_t *)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2209 aprint_error( 2210 "%s: Could not map TX desc %d DMA memory!\n", 2211 sc->bnx_dev.dv_xname, i); 2212 rc = ENOMEM; 2213 goto bnx_dma_alloc_exit; 2214 } 2215 2216 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2217 (caddr_t)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2218 BUS_DMA_NOWAIT)) { 2219 aprint_error( 2220 "%s: Could not load TX desc %d DMA memory!\n", 2221 sc->bnx_dev.dv_xname, i); 2222 rc = ENOMEM; 2223 goto bnx_dma_alloc_exit; 2224 } 2225 2226 sc->tx_bd_chain_paddr[i] = 2227 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2228 2229 /* DRC - Fix for 64 bit systems. */ 2230 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2231 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2232 } 2233 2234 /* 2235 * Create DMA maps for the TX buffer mbufs. 2236 */ 2237 for (i = 0; i < TOTAL_TX_BD; i++) { 2238 if (bus_dmamap_create(sc->bnx_dmatag, 2239 MCLBYTES * BNX_MAX_SEGMENTS, 2240 USABLE_TX_BD - BNX_TX_SLACK_SPACE, 2241 MCLBYTES, 0, BUS_DMA_NOWAIT, 2242 &sc->tx_mbuf_map[i])) { 2243 aprint_error( 2244 "%s: Could not create Tx mbuf %d DMA map!\n", 2245 sc->bnx_dev.dv_xname, i); 2246 rc = ENOMEM; 2247 goto bnx_dma_alloc_exit; 2248 } 2249 } 2250 2251 /* 2252 * Allocate DMA memory for the Rx buffer descriptor chain, 2253 * and fetch the physical address of the block. 2254 */ 2255 for (i = 0; i < RX_PAGES; i++) { 2256 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2257 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2258 &sc->rx_bd_chain_map[i])) { 2259 aprint_error( 2260 "%s: Could not create Rx desc %d DMA map!\n", 2261 sc->bnx_dev.dv_xname, i); 2262 rc = ENOMEM; 2263 goto bnx_dma_alloc_exit; 2264 } 2265 2266 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2267 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2268 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2269 aprint_error( 2270 "%s: Could not allocate Rx desc %d DMA memory!\n", 2271 sc->bnx_dev.dv_xname, i); 2272 rc = ENOMEM; 2273 goto bnx_dma_alloc_exit; 2274 } 2275 2276 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2277 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2278 (caddr_t *)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2279 aprint_error( 2280 "%s: Could not map Rx desc %d DMA memory!\n", 2281 sc->bnx_dev.dv_xname, i); 2282 rc = ENOMEM; 2283 goto bnx_dma_alloc_exit; 2284 } 2285 2286 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2287 (caddr_t)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2288 BUS_DMA_NOWAIT)) { 2289 aprint_error( 2290 "%s: Could not load Rx desc %d DMA memory!\n", 2291 sc->bnx_dev.dv_xname, i); 2292 rc = ENOMEM; 2293 goto bnx_dma_alloc_exit; 2294 } 2295 2296 bzero(sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2297 sc->rx_bd_chain_paddr[i] = 2298 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2299 2300 /* DRC - Fix for 64 bit systems. */ 2301 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2302 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2303 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2304 0, BNX_RX_CHAIN_PAGE_SZ, 2305 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2306 } 2307 2308 /* 2309 * Create DMA maps for the Rx buffer mbufs. 2310 */ 2311 for (i = 0; i < TOTAL_RX_BD; i++) { 2312 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU, 2313 BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT, 2314 &sc->rx_mbuf_map[i])) { 2315 aprint_error( 2316 "%s: Could not create Rx mbuf %d DMA map!\n", 2317 sc->bnx_dev.dv_xname, i); 2318 rc = ENOMEM; 2319 goto bnx_dma_alloc_exit; 2320 } 2321 } 2322 2323 bnx_dma_alloc_exit: 2324 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2325 2326 return(rc); 2327 } 2328 2329 /****************************************************************************/ 2330 /* Release all resources used by the driver. */ 2331 /* */ 2332 /* Releases all resources acquired by the driver including interrupts, */ 2333 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2334 /* */ 2335 /* Returns: */ 2336 /* Nothing. */ 2337 /****************************************************************************/ 2338 void 2339 bnx_release_resources(struct bnx_softc *sc) 2340 { 2341 struct pci_attach_args *pa = &(sc->bnx_pa); 2342 2343 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2344 2345 bnx_dma_free(sc); 2346 2347 if (sc->bnx_intrhand != NULL) 2348 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2349 2350 if (sc->bnx_size) 2351 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2352 2353 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2354 } 2355 2356 /****************************************************************************/ 2357 /* Firmware synchronization. */ 2358 /* */ 2359 /* Before performing certain events such as a chip reset, synchronize with */ 2360 /* the firmware first. */ 2361 /* */ 2362 /* Returns: */ 2363 /* 0 for success, positive value for failure. */ 2364 /****************************************************************************/ 2365 int 2366 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2367 { 2368 int i, rc = 0; 2369 u_int32_t val; 2370 2371 /* Don't waste any time if we've timed out before. */ 2372 if (sc->bnx_fw_timed_out) { 2373 rc = EBUSY; 2374 goto bnx_fw_sync_exit; 2375 } 2376 2377 /* Increment the message sequence number. */ 2378 sc->bnx_fw_wr_seq++; 2379 msg_data |= sc->bnx_fw_wr_seq; 2380 2381 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2382 msg_data); 2383 2384 /* Send the message to the bootcode driver mailbox. */ 2385 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2386 2387 /* Wait for the bootcode to acknowledge the message. */ 2388 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2389 /* Check for a response in the bootcode firmware mailbox. */ 2390 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2391 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2392 break; 2393 DELAY(1000); 2394 } 2395 2396 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2397 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2398 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2399 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2400 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2401 2402 msg_data &= ~BNX_DRV_MSG_CODE; 2403 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2404 2405 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2406 2407 sc->bnx_fw_timed_out = 1; 2408 rc = EBUSY; 2409 } 2410 2411 bnx_fw_sync_exit: 2412 return (rc); 2413 } 2414 2415 /****************************************************************************/ 2416 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2417 /* */ 2418 /* Returns: */ 2419 /* Nothing. */ 2420 /****************************************************************************/ 2421 void 2422 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2423 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2424 { 2425 int i; 2426 u_int32_t val; 2427 2428 for (i = 0; i < rv2p_code_len; i += 8) { 2429 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2430 rv2p_code++; 2431 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2432 rv2p_code++; 2433 2434 if (rv2p_proc == RV2P_PROC1) { 2435 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2436 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2437 } 2438 else { 2439 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2440 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2441 } 2442 } 2443 2444 /* Reset the processor, un-stall is done later. */ 2445 if (rv2p_proc == RV2P_PROC1) 2446 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2447 else 2448 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2449 } 2450 2451 /****************************************************************************/ 2452 /* Load RISC processor firmware. */ 2453 /* */ 2454 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2455 /* associated with a particular processor. */ 2456 /* */ 2457 /* Returns: */ 2458 /* Nothing. */ 2459 /****************************************************************************/ 2460 void 2461 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2462 struct fw_info *fw) 2463 { 2464 u_int32_t offset; 2465 u_int32_t val; 2466 2467 /* Halt the CPU. */ 2468 val = REG_RD_IND(sc, cpu_reg->mode); 2469 val |= cpu_reg->mode_value_halt; 2470 REG_WR_IND(sc, cpu_reg->mode, val); 2471 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2472 2473 /* Load the Text area. */ 2474 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2475 if (fw->text) { 2476 int j; 2477 2478 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2479 REG_WR_IND(sc, offset, fw->text[j]); 2480 } 2481 2482 /* Load the Data area. */ 2483 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2484 if (fw->data) { 2485 int j; 2486 2487 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2488 REG_WR_IND(sc, offset, fw->data[j]); 2489 } 2490 2491 /* Load the SBSS area. */ 2492 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2493 if (fw->sbss) { 2494 int j; 2495 2496 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2497 REG_WR_IND(sc, offset, fw->sbss[j]); 2498 } 2499 2500 /* Load the BSS area. */ 2501 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2502 if (fw->bss) { 2503 int j; 2504 2505 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2506 REG_WR_IND(sc, offset, fw->bss[j]); 2507 } 2508 2509 /* Load the Read-Only area. */ 2510 offset = cpu_reg->spad_base + 2511 (fw->rodata_addr - cpu_reg->mips_view_base); 2512 if (fw->rodata) { 2513 int j; 2514 2515 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2516 REG_WR_IND(sc, offset, fw->rodata[j]); 2517 } 2518 2519 /* Clear the pre-fetch instruction. */ 2520 REG_WR_IND(sc, cpu_reg->inst, 0); 2521 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2522 2523 /* Start the CPU. */ 2524 val = REG_RD_IND(sc, cpu_reg->mode); 2525 val &= ~cpu_reg->mode_value_halt; 2526 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2527 REG_WR_IND(sc, cpu_reg->mode, val); 2528 } 2529 2530 /****************************************************************************/ 2531 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2532 /* */ 2533 /* Loads the firmware for each CPU and starts the CPU. */ 2534 /* */ 2535 /* Returns: */ 2536 /* Nothing. */ 2537 /****************************************************************************/ 2538 void 2539 bnx_init_cpus(struct bnx_softc *sc) 2540 { 2541 struct cpu_reg cpu_reg; 2542 struct fw_info fw; 2543 2544 /* Initialize the RV2P processor. */ 2545 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2546 RV2P_PROC1); 2547 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2548 RV2P_PROC2); 2549 2550 /* Initialize the RX Processor. */ 2551 cpu_reg.mode = BNX_RXP_CPU_MODE; 2552 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2553 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2554 cpu_reg.state = BNX_RXP_CPU_STATE; 2555 cpu_reg.state_value_clear = 0xffffff; 2556 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2557 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2558 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2559 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2560 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2561 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2562 cpu_reg.mips_view_base = 0x8000000; 2563 2564 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2565 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2566 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2567 fw.start_addr = bnx_RXP_b06FwStartAddr; 2568 2569 fw.text_addr = bnx_RXP_b06FwTextAddr; 2570 fw.text_len = bnx_RXP_b06FwTextLen; 2571 fw.text_index = 0; 2572 fw.text = bnx_RXP_b06FwText; 2573 2574 fw.data_addr = bnx_RXP_b06FwDataAddr; 2575 fw.data_len = bnx_RXP_b06FwDataLen; 2576 fw.data_index = 0; 2577 fw.data = bnx_RXP_b06FwData; 2578 2579 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2580 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2581 fw.sbss_index = 0; 2582 fw.sbss = bnx_RXP_b06FwSbss; 2583 2584 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2585 fw.bss_len = bnx_RXP_b06FwBssLen; 2586 fw.bss_index = 0; 2587 fw.bss = bnx_RXP_b06FwBss; 2588 2589 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2590 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2591 fw.rodata_index = 0; 2592 fw.rodata = bnx_RXP_b06FwRodata; 2593 2594 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2595 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2596 2597 /* Initialize the TX Processor. */ 2598 cpu_reg.mode = BNX_TXP_CPU_MODE; 2599 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2600 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2601 cpu_reg.state = BNX_TXP_CPU_STATE; 2602 cpu_reg.state_value_clear = 0xffffff; 2603 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2604 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2605 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2606 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2607 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2608 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2609 cpu_reg.mips_view_base = 0x8000000; 2610 2611 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2612 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2613 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2614 fw.start_addr = bnx_TXP_b06FwStartAddr; 2615 2616 fw.text_addr = bnx_TXP_b06FwTextAddr; 2617 fw.text_len = bnx_TXP_b06FwTextLen; 2618 fw.text_index = 0; 2619 fw.text = bnx_TXP_b06FwText; 2620 2621 fw.data_addr = bnx_TXP_b06FwDataAddr; 2622 fw.data_len = bnx_TXP_b06FwDataLen; 2623 fw.data_index = 0; 2624 fw.data = bnx_TXP_b06FwData; 2625 2626 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2627 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2628 fw.sbss_index = 0; 2629 fw.sbss = bnx_TXP_b06FwSbss; 2630 2631 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2632 fw.bss_len = bnx_TXP_b06FwBssLen; 2633 fw.bss_index = 0; 2634 fw.bss = bnx_TXP_b06FwBss; 2635 2636 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 2637 fw.rodata_len = bnx_TXP_b06FwRodataLen; 2638 fw.rodata_index = 0; 2639 fw.rodata = bnx_TXP_b06FwRodata; 2640 2641 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2642 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2643 2644 /* Initialize the TX Patch-up Processor. */ 2645 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2646 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2647 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2648 cpu_reg.state = BNX_TPAT_CPU_STATE; 2649 cpu_reg.state_value_clear = 0xffffff; 2650 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2651 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2652 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2653 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2654 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2655 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2656 cpu_reg.mips_view_base = 0x8000000; 2657 2658 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 2659 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 2660 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 2661 fw.start_addr = bnx_TPAT_b06FwStartAddr; 2662 2663 fw.text_addr = bnx_TPAT_b06FwTextAddr; 2664 fw.text_len = bnx_TPAT_b06FwTextLen; 2665 fw.text_index = 0; 2666 fw.text = bnx_TPAT_b06FwText; 2667 2668 fw.data_addr = bnx_TPAT_b06FwDataAddr; 2669 fw.data_len = bnx_TPAT_b06FwDataLen; 2670 fw.data_index = 0; 2671 fw.data = bnx_TPAT_b06FwData; 2672 2673 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 2674 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 2675 fw.sbss_index = 0; 2676 fw.sbss = bnx_TPAT_b06FwSbss; 2677 2678 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 2679 fw.bss_len = bnx_TPAT_b06FwBssLen; 2680 fw.bss_index = 0; 2681 fw.bss = bnx_TPAT_b06FwBss; 2682 2683 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 2684 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 2685 fw.rodata_index = 0; 2686 fw.rodata = bnx_TPAT_b06FwRodata; 2687 2688 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2689 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2690 2691 /* Initialize the Completion Processor. */ 2692 cpu_reg.mode = BNX_COM_CPU_MODE; 2693 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2694 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2695 cpu_reg.state = BNX_COM_CPU_STATE; 2696 cpu_reg.state_value_clear = 0xffffff; 2697 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2698 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2699 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2700 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2701 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2702 cpu_reg.spad_base = BNX_COM_SCRATCH; 2703 cpu_reg.mips_view_base = 0x8000000; 2704 2705 fw.ver_major = bnx_COM_b06FwReleaseMajor; 2706 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 2707 fw.ver_fix = bnx_COM_b06FwReleaseFix; 2708 fw.start_addr = bnx_COM_b06FwStartAddr; 2709 2710 fw.text_addr = bnx_COM_b06FwTextAddr; 2711 fw.text_len = bnx_COM_b06FwTextLen; 2712 fw.text_index = 0; 2713 fw.text = bnx_COM_b06FwText; 2714 2715 fw.data_addr = bnx_COM_b06FwDataAddr; 2716 fw.data_len = bnx_COM_b06FwDataLen; 2717 fw.data_index = 0; 2718 fw.data = bnx_COM_b06FwData; 2719 2720 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 2721 fw.sbss_len = bnx_COM_b06FwSbssLen; 2722 fw.sbss_index = 0; 2723 fw.sbss = bnx_COM_b06FwSbss; 2724 2725 fw.bss_addr = bnx_COM_b06FwBssAddr; 2726 fw.bss_len = bnx_COM_b06FwBssLen; 2727 fw.bss_index = 0; 2728 fw.bss = bnx_COM_b06FwBss; 2729 2730 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 2731 fw.rodata_len = bnx_COM_b06FwRodataLen; 2732 fw.rodata_index = 0; 2733 fw.rodata = bnx_COM_b06FwRodata; 2734 2735 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2736 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2737 } 2738 2739 /****************************************************************************/ 2740 /* Initialize context memory. */ 2741 /* */ 2742 /* Clears the memory associated with each Context ID (CID). */ 2743 /* */ 2744 /* Returns: */ 2745 /* Nothing. */ 2746 /****************************************************************************/ 2747 void 2748 bnx_init_context(struct bnx_softc *sc) 2749 { 2750 u_int32_t vcid; 2751 2752 vcid = 96; 2753 while (vcid) { 2754 u_int32_t vcid_addr, pcid_addr, offset; 2755 2756 vcid--; 2757 2758 vcid_addr = GET_CID_ADDR(vcid); 2759 pcid_addr = vcid_addr; 2760 2761 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); 2762 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2763 2764 /* Zero out the context. */ 2765 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2766 CTX_WR(sc, 0x00, offset, 0); 2767 2768 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 2769 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2770 } 2771 } 2772 2773 /****************************************************************************/ 2774 /* Fetch the permanent MAC address of the controller. */ 2775 /* */ 2776 /* Returns: */ 2777 /* Nothing. */ 2778 /****************************************************************************/ 2779 void 2780 bnx_get_mac_addr(struct bnx_softc *sc) 2781 { 2782 u_int32_t mac_lo = 0, mac_hi = 0; 2783 2784 /* 2785 * The NetXtreme II bootcode populates various NIC 2786 * power-on and runtime configuration items in a 2787 * shared memory area. The factory configured MAC 2788 * address is available from both NVRAM and the 2789 * shared memory area so we'll read the value from 2790 * shared memory for speed. 2791 */ 2792 2793 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 2794 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 2795 2796 if ((mac_lo == 0) && (mac_hi == 0)) { 2797 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 2798 __FILE__, __LINE__); 2799 } else { 2800 sc->eaddr[0] = (u_char)(mac_hi >> 8); 2801 sc->eaddr[1] = (u_char)(mac_hi >> 0); 2802 sc->eaddr[2] = (u_char)(mac_lo >> 24); 2803 sc->eaddr[3] = (u_char)(mac_lo >> 16); 2804 sc->eaddr[4] = (u_char)(mac_lo >> 8); 2805 sc->eaddr[5] = (u_char)(mac_lo >> 0); 2806 } 2807 2808 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 2809 "%s\n", ether_sprintf(sc->eaddr)); 2810 } 2811 2812 /****************************************************************************/ 2813 /* Program the MAC address. */ 2814 /* */ 2815 /* Returns: */ 2816 /* Nothing. */ 2817 /****************************************************************************/ 2818 void 2819 bnx_set_mac_addr(struct bnx_softc *sc) 2820 { 2821 u_int32_t val; 2822 u_int8_t *mac_addr = LLADDR(sc->ethercom.ec_if.if_sadl); 2823 2824 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 2825 "%s\n", ether_sprintf(sc->eaddr)); 2826 2827 val = (mac_addr[0] << 8) | mac_addr[1]; 2828 2829 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 2830 2831 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2832 (mac_addr[4] << 8) | mac_addr[5]; 2833 2834 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 2835 } 2836 2837 /****************************************************************************/ 2838 /* Stop the controller. */ 2839 /* */ 2840 /* Returns: */ 2841 /* Nothing. */ 2842 /****************************************************************************/ 2843 void 2844 bnx_stop(struct bnx_softc *sc) 2845 { 2846 struct ifnet *ifp = &sc->ethercom.ec_if; 2847 struct ifmedia_entry *ifm; 2848 struct mii_data *mii = NULL; 2849 int mtmp, itmp; 2850 2851 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2852 2853 mii = &sc->bnx_mii; 2854 2855 callout_stop(&sc->bnx_timeout); 2856 2857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2858 2859 /* Disable the transmit/receive blocks. */ 2860 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 2861 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2862 DELAY(20); 2863 2864 bnx_disable_intr(sc); 2865 2866 /* Tell firmware that the driver is going away. */ 2867 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 2868 2869 /* Free the RX lists. */ 2870 bnx_free_rx_chain(sc); 2871 2872 /* Free TX buffers. */ 2873 bnx_free_tx_chain(sc); 2874 2875 /* 2876 * Isolate/power down the PHY, but leave the media selection 2877 * unchanged so that things will be put back to normal when 2878 * we bring the interface back up. 2879 */ 2880 2881 itmp = ifp->if_flags; 2882 ifp->if_flags |= IFF_UP; 2883 /* 2884 * If we are called from bnx_detach(), mii is already NULL. 2885 */ 2886 if (mii != NULL) { 2887 ifm = mii->mii_media.ifm_cur; 2888 mtmp = ifm->ifm_media; 2889 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2890 mii_mediachg(mii); 2891 ifm->ifm_media = mtmp; 2892 } 2893 2894 ifp->if_flags = itmp; 2895 ifp->if_timer = 0; 2896 2897 sc->bnx_link = 0; 2898 2899 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2900 2901 } 2902 2903 int 2904 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 2905 { 2906 u_int32_t val; 2907 int i, rc = 0; 2908 2909 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2910 2911 /* Wait for pending PCI transactions to complete. */ 2912 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 2913 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 2914 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 2915 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 2916 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 2917 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2918 DELAY(5); 2919 2920 /* Assume bootcode is running. */ 2921 sc->bnx_fw_timed_out = 0; 2922 2923 /* Give the firmware a chance to prepare for the reset. */ 2924 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 2925 if (rc) 2926 goto bnx_reset_exit; 2927 2928 /* Set a firmware reminder that this is a soft reset. */ 2929 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 2930 BNX_DRV_RESET_SIGNATURE_MAGIC); 2931 2932 /* Dummy read to force the chip to complete all current transactions. */ 2933 val = REG_RD(sc, BNX_MISC_ID); 2934 2935 /* Chip reset. */ 2936 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2937 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 2938 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 2939 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 2940 2941 /* Allow up to 30us for reset to complete. */ 2942 for (i = 0; i < 10; i++) { 2943 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 2944 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2945 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 2946 break; 2947 2948 DELAY(10); 2949 } 2950 2951 /* Check that reset completed successfully. */ 2952 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2953 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 2954 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__); 2955 rc = EBUSY; 2956 goto bnx_reset_exit; 2957 } 2958 2959 /* Make sure byte swapping is properly configured. */ 2960 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 2961 if (val != 0x01020304) { 2962 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 2963 __FILE__, __LINE__); 2964 rc = ENODEV; 2965 goto bnx_reset_exit; 2966 } 2967 2968 /* Just completed a reset, assume that firmware is running again. */ 2969 sc->bnx_fw_timed_out = 0; 2970 2971 /* Wait for the firmware to finish its initialization. */ 2972 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 2973 if (rc) 2974 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 2975 "initialization!\n", __FILE__, __LINE__); 2976 2977 bnx_reset_exit: 2978 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2979 2980 return (rc); 2981 } 2982 2983 int 2984 bnx_chipinit(struct bnx_softc *sc) 2985 { 2986 struct pci_attach_args *pa = &(sc->bnx_pa); 2987 u_int32_t val; 2988 int rc = 0; 2989 2990 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2991 2992 /* Make sure the interrupt is not active. */ 2993 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 2994 2995 /* Initialize DMA byte/word swapping, configure the number of DMA */ 2996 /* channels and PCI clock compensation delay. */ 2997 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 2998 BNX_DMA_CONFIG_DATA_WORD_SWAP | 2999 #if BYTE_ORDER == BIG_ENDIAN 3000 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3001 #endif 3002 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3003 DMA_READ_CHANS << 12 | 3004 DMA_WRITE_CHANS << 16; 3005 3006 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3007 3008 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3009 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3010 3011 /* 3012 * This setting resolves a problem observed on certain Intel PCI 3013 * chipsets that cannot handle multiple outstanding DMA operations. 3014 * See errata E9_5706A1_65. 3015 */ 3016 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3017 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3018 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3019 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3020 3021 REG_WR(sc, BNX_DMA_CONFIG, val); 3022 3023 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3024 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3025 u_int16_t nval; 3026 3027 nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3028 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3029 nval & ~0x2); 3030 } 3031 3032 /* Enable the RX_V2P and Context state machines before access. */ 3033 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3034 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3035 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3036 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3037 3038 /* Initialize context mapping and zero out the quick contexts. */ 3039 bnx_init_context(sc); 3040 3041 /* Initialize the on-boards CPUs */ 3042 bnx_init_cpus(sc); 3043 3044 /* Prepare NVRAM for access. */ 3045 if (bnx_init_nvram(sc)) { 3046 rc = ENODEV; 3047 goto bnx_chipinit_exit; 3048 } 3049 3050 /* Set the kernel bypass block size */ 3051 val = REG_RD(sc, BNX_MQ_CONFIG); 3052 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3053 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3054 REG_WR(sc, BNX_MQ_CONFIG, val); 3055 3056 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3057 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3058 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3059 3060 val = (BCM_PAGE_BITS - 8) << 24; 3061 REG_WR(sc, BNX_RV2P_CONFIG, val); 3062 3063 /* Configure page size. */ 3064 val = REG_RD(sc, BNX_TBDR_CONFIG); 3065 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3066 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3067 REG_WR(sc, BNX_TBDR_CONFIG, val); 3068 3069 bnx_chipinit_exit: 3070 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3071 3072 return(rc); 3073 } 3074 3075 /****************************************************************************/ 3076 /* Initialize the controller in preparation to send/receive traffic. */ 3077 /* */ 3078 /* Returns: */ 3079 /* 0 for success, positive value for failure. */ 3080 /****************************************************************************/ 3081 int 3082 bnx_blockinit(struct bnx_softc *sc) 3083 { 3084 u_int32_t reg, val; 3085 int rc = 0; 3086 3087 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3088 3089 /* Load the hardware default MAC address. */ 3090 bnx_set_mac_addr(sc); 3091 3092 /* Set the Ethernet backoff seed value */ 3093 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3094 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3095 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3096 3097 sc->last_status_idx = 0; 3098 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3099 3100 /* Set up link change interrupt generation. */ 3101 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3102 3103 /* Program the physical address of the status block. */ 3104 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 3105 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3106 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 3107 3108 /* Program the physical address of the statistics block. */ 3109 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3110 (u_int32_t)(sc->stats_block_paddr)); 3111 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3112 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 3113 3114 /* Program various host coalescing parameters. */ 3115 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3116 << 16) | sc->bnx_tx_quick_cons_trip); 3117 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3118 << 16) | sc->bnx_rx_quick_cons_trip); 3119 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3120 sc->bnx_comp_prod_trip); 3121 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3122 sc->bnx_tx_ticks); 3123 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3124 sc->bnx_rx_ticks); 3125 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3126 sc->bnx_com_ticks); 3127 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3128 sc->bnx_cmd_ticks); 3129 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3130 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3131 REG_WR(sc, BNX_HC_CONFIG, 3132 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3133 BNX_HC_CONFIG_COLLECT_STATS)); 3134 3135 /* Clear the internal statistics counters. */ 3136 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3137 3138 /* Verify that bootcode is running. */ 3139 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3140 3141 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3142 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3143 __FILE__, __LINE__); reg = 0); 3144 3145 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3146 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3147 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3148 "Expected: 08%08X\n", __FILE__, __LINE__, 3149 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3150 BNX_DEV_INFO_SIGNATURE_MAGIC); 3151 rc = ENODEV; 3152 goto bnx_blockinit_exit; 3153 } 3154 3155 /* Check if any management firmware is running. */ 3156 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3157 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3158 BNX_PORT_FEATURE_IMD_ENABLED)) { 3159 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3160 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3161 } 3162 3163 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3164 BNX_DEV_INFO_BC_REV); 3165 3166 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3167 3168 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3169 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3170 3171 /* Enable link state change interrupt generation. */ 3172 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3173 3174 /* Enable all remaining blocks in the MAC. */ 3175 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3176 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3177 DELAY(20); 3178 3179 bnx_blockinit_exit: 3180 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3181 3182 return (rc); 3183 } 3184 3185 /****************************************************************************/ 3186 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3187 /* */ 3188 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3189 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3190 /* necessary. */ 3191 /* */ 3192 /* Returns: */ 3193 /* 0 for success, positive value for failure. */ 3194 /****************************************************************************/ 3195 int 3196 bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod, 3197 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3198 { 3199 bus_dmamap_t map; 3200 struct mbuf *m_new = NULL; 3201 struct rx_bd *rxbd; 3202 int i, rc = 0; 3203 u_int32_t addr; 3204 #ifdef BNX_DEBUG 3205 u_int16_t debug_chain_prod = *chain_prod; 3206 #endif 3207 3208 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3209 __FUNCTION__); 3210 3211 /* Make sure the inputs are valid. */ 3212 DBRUNIF((*chain_prod > MAX_RX_BD), 3213 aprint_error("%s: RX producer out of range: 0x%04X > 0x%04X\n", 3214 sc->bnx_dev.dv_xname, *chain_prod, (u_int16_t) MAX_RX_BD)); 3215 3216 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3217 "0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, 3218 *prod_bseq); 3219 3220 if (m == NULL) { 3221 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3222 BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n"); 3223 3224 sc->mbuf_alloc_failed++; 3225 rc = ENOBUFS; 3226 goto bnx_get_buf_exit); 3227 3228 /* This is a new mbuf allocation. */ 3229 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3230 if (m_new == NULL) { 3231 DBPRINT(sc, BNX_WARN, 3232 "%s(%d): RX mbuf header allocation failed!\n", 3233 __FILE__, __LINE__); 3234 3235 DBRUNIF(1, sc->mbuf_alloc_failed++); 3236 3237 rc = ENOBUFS; 3238 goto bnx_get_buf_exit; 3239 } 3240 3241 DBRUNIF(1, sc->rx_mbuf_alloc++); 3242 MEXTMALLOC(m_new, sc->mbuf_alloc_size, M_DONTWAIT); 3243 if (!(m_new->m_flags & M_EXT)) { 3244 DBPRINT(sc, BNX_WARN, 3245 "%s(%d): RX mbuf chain allocation failed!\n", 3246 __FILE__, __LINE__); 3247 3248 m_freem(m_new); 3249 3250 DBRUNIF(1, sc->rx_mbuf_alloc--); 3251 DBRUNIF(1, sc->mbuf_alloc_failed++); 3252 3253 rc = ENOBUFS; 3254 goto bnx_get_buf_exit; 3255 } 3256 3257 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3258 } else { 3259 m_new = m; 3260 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3261 m_new->m_data = m_new->m_ext.ext_buf; 3262 } 3263 3264 /* Map the mbuf cluster into device memory. */ 3265 map = sc->rx_mbuf_map[*chain_prod]; 3266 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3267 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3268 __FILE__, __LINE__); 3269 3270 m_freem(m_new); 3271 3272 DBRUNIF(1, sc->rx_mbuf_alloc--); 3273 3274 rc = ENOBUFS; 3275 goto bnx_get_buf_exit; 3276 } 3277 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3278 BUS_DMASYNC_PREREAD); 3279 3280 /* Watch for overflow. */ 3281 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3282 aprint_error("%s: Too many free rx_bd (0x%04X > 0x%04X)!\n", 3283 sc->bnx_dev.dv_xname, 3284 sc->free_rx_bd, (u_int16_t) USABLE_RX_BD)); 3285 3286 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3287 sc->rx_low_watermark = sc->free_rx_bd); 3288 3289 /* Setup the rx_bd for the first segment. */ 3290 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3291 3292 addr = (u_int32_t)(map->dm_segs[0].ds_addr); 3293 rxbd->rx_bd_haddr_lo = htole32(addr); 3294 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3295 rxbd->rx_bd_haddr_hi = htole32(addr); 3296 rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); 3297 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3298 *prod_bseq += map->dm_segs[0].ds_len; 3299 bus_dmamap_sync(sc->bnx_dmatag, 3300 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3301 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3302 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3303 3304 for (i = 1; i < map->dm_nsegs; i++) { 3305 *prod = NEXT_RX_BD(*prod); 3306 *chain_prod = RX_CHAIN_IDX(*prod); 3307 3308 rxbd = 3309 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3310 3311 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 3312 rxbd->rx_bd_haddr_lo = htole32(addr); 3313 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3314 rxbd->rx_bd_haddr_hi = htole32(addr); 3315 rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); 3316 rxbd->rx_bd_flags = 0; 3317 *prod_bseq += map->dm_segs[i].ds_len; 3318 bus_dmamap_sync(sc->bnx_dmatag, 3319 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3320 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3321 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3322 } 3323 3324 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3325 bus_dmamap_sync(sc->bnx_dmatag, 3326 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3327 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3328 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3329 3330 /* Save the mbuf and update our counter. */ 3331 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3332 sc->free_rx_bd -= map->dm_nsegs; 3333 3334 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3335 map->dm_nsegs)); 3336 3337 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3338 "= 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, 3339 *chain_prod, *prod_bseq); 3340 3341 bnx_get_buf_exit: 3342 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3343 __FUNCTION__); 3344 3345 return(rc); 3346 } 3347 3348 /****************************************************************************/ 3349 /* Allocate memory and initialize the TX data structures. */ 3350 /* */ 3351 /* Returns: */ 3352 /* 0 for success, positive value for failure. */ 3353 /****************************************************************************/ 3354 int 3355 bnx_init_tx_chain(struct bnx_softc *sc) 3356 { 3357 struct tx_bd *txbd; 3358 u_int32_t val, addr; 3359 int i, rc = 0; 3360 3361 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3362 3363 /* Set the initial TX producer/consumer indices. */ 3364 sc->tx_prod = 0; 3365 sc->tx_cons = 0; 3366 sc->tx_prod_bseq = 0; 3367 sc->used_tx_bd = 0; 3368 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3369 3370 /* 3371 * The NetXtreme II supports a linked-list structure called 3372 * a Buffer Descriptor Chain (or BD chain). A BD chain 3373 * consists of a series of 1 or more chain pages, each of which 3374 * consists of a fixed number of BD entries. 3375 * The last BD entry on each page is a pointer to the next page 3376 * in the chain, and the last pointer in the BD chain 3377 * points back to the beginning of the chain. 3378 */ 3379 3380 /* Set the TX next pointer chain entries. */ 3381 for (i = 0; i < TX_PAGES; i++) { 3382 int j; 3383 3384 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3385 3386 /* Check if we've reached the last page. */ 3387 if (i == (TX_PAGES - 1)) 3388 j = 0; 3389 else 3390 j = i + 1; 3391 3392 addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); 3393 txbd->tx_bd_haddr_lo = htole32(addr); 3394 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3395 txbd->tx_bd_haddr_hi = htole32(addr); 3396 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3397 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3398 } 3399 3400 /* 3401 * Initialize the context ID for an L2 TX chain. 3402 */ 3403 val = BNX_L2CTX_TYPE_TYPE_L2; 3404 val |= BNX_L2CTX_TYPE_SIZE_L2; 3405 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3406 3407 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3408 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3409 3410 /* Point the hardware to the first page in the chain. */ 3411 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3412 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3413 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3414 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3415 3416 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3417 3418 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3419 3420 return(rc); 3421 } 3422 3423 /****************************************************************************/ 3424 /* Free memory and clear the TX data structures. */ 3425 /* */ 3426 /* Returns: */ 3427 /* Nothing. */ 3428 /****************************************************************************/ 3429 void 3430 bnx_free_tx_chain(struct bnx_softc *sc) 3431 { 3432 int i; 3433 3434 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3435 3436 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3437 for (i = 0; i < TOTAL_TX_BD; i++) { 3438 if (sc->tx_mbuf_ptr[i] != NULL) { 3439 if (sc->tx_mbuf_map != NULL) 3440 bus_dmamap_sync(sc->bnx_dmatag, 3441 sc->tx_mbuf_map[i], 0, 3442 sc->tx_mbuf_map[i]->dm_mapsize, 3443 BUS_DMASYNC_POSTWRITE); 3444 m_freem(sc->tx_mbuf_ptr[i]); 3445 sc->tx_mbuf_ptr[i] = NULL; 3446 DBRUNIF(1, sc->tx_mbuf_alloc--); 3447 } 3448 } 3449 3450 /* Clear each TX chain page. */ 3451 for (i = 0; i < TX_PAGES; i++) { 3452 bzero((char *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 3453 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3454 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3455 } 3456 3457 /* Check if we lost any mbufs in the process. */ 3458 DBRUNIF((sc->tx_mbuf_alloc), 3459 aprint_error("%s: Memory leak! Lost %d mbufs from tx chain!\n", 3460 sc->bnx_dev.dv_xname, sc->tx_mbuf_alloc)); 3461 3462 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3463 } 3464 3465 /****************************************************************************/ 3466 /* Allocate memory and initialize the RX data structures. */ 3467 /* */ 3468 /* Returns: */ 3469 /* 0 for success, positive value for failure. */ 3470 /****************************************************************************/ 3471 int 3472 bnx_init_rx_chain(struct bnx_softc *sc) 3473 { 3474 struct rx_bd *rxbd; 3475 int i, rc = 0; 3476 u_int16_t prod, chain_prod; 3477 u_int32_t prod_bseq, val, addr; 3478 3479 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3480 3481 /* Initialize the RX producer and consumer indices. */ 3482 sc->rx_prod = 0; 3483 sc->rx_cons = 0; 3484 sc->rx_prod_bseq = 0; 3485 sc->free_rx_bd = BNX_RX_SLACK_SPACE; 3486 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3487 3488 /* Initialize the RX next pointer chain entries. */ 3489 for (i = 0; i < RX_PAGES; i++) { 3490 int j; 3491 3492 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3493 3494 /* Check if we've reached the last page. */ 3495 if (i == (RX_PAGES - 1)) 3496 j = 0; 3497 else 3498 j = i + 1; 3499 3500 /* Setup the chain page pointers. */ 3501 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 3502 rxbd->rx_bd_haddr_hi = htole32(addr); 3503 addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); 3504 rxbd->rx_bd_haddr_lo = htole32(addr); 3505 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 3506 0, BNX_RX_CHAIN_PAGE_SZ, 3507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3508 } 3509 3510 /* Initialize the context ID for an L2 RX chain. */ 3511 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3512 val |= BNX_L2CTX_CTX_TYPE_SIZE_L2; 3513 val |= 0x02 << 8; 3514 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 3515 3516 /* Point the hardware to the first page in the chain. */ 3517 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 3518 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 3519 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 3520 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 3521 3522 /* Allocate mbuf clusters for the rx_bd chain. */ 3523 prod = prod_bseq = 0; 3524 while (prod < BNX_RX_SLACK_SPACE) { 3525 chain_prod = RX_CHAIN_IDX(prod); 3526 if (bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3527 BNX_PRINTF(sc, 3528 "Error filling RX chain: rx_bd[0x%04X]!\n", 3529 chain_prod); 3530 rc = ENOBUFS; 3531 break; 3532 } 3533 prod = NEXT_RX_BD(prod); 3534 } 3535 3536 /* Save the RX chain producer index. */ 3537 sc->rx_prod = prod; 3538 sc->rx_prod_bseq = prod_bseq; 3539 3540 for (i = 0; i < RX_PAGES; i++) 3541 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 3542 sc->rx_bd_chain_map[i]->dm_mapsize, 3543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3544 3545 /* Tell the chip about the waiting rx_bd's. */ 3546 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3547 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3548 3549 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3550 3551 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3552 3553 return(rc); 3554 } 3555 3556 /****************************************************************************/ 3557 /* Free memory and clear the RX data structures. */ 3558 /* */ 3559 /* Returns: */ 3560 /* Nothing. */ 3561 /****************************************************************************/ 3562 void 3563 bnx_free_rx_chain(struct bnx_softc *sc) 3564 { 3565 int i; 3566 3567 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3568 3569 /* Free any mbufs still in the RX mbuf chain. */ 3570 for (i = 0; i < TOTAL_RX_BD; i++) { 3571 if (sc->rx_mbuf_ptr[i] != NULL) { 3572 if (sc->rx_mbuf_map[i] != NULL) 3573 bus_dmamap_sync(sc->bnx_dmatag, 3574 sc->rx_mbuf_map[i], 0, 3575 sc->rx_mbuf_map[i]->dm_mapsize, 3576 BUS_DMASYNC_POSTREAD); 3577 m_freem(sc->rx_mbuf_ptr[i]); 3578 sc->rx_mbuf_ptr[i] = NULL; 3579 DBRUNIF(1, sc->rx_mbuf_alloc--); 3580 } 3581 } 3582 3583 /* Clear each RX chain page. */ 3584 for (i = 0; i < RX_PAGES; i++) 3585 bzero((char *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 3586 3587 /* Check if we lost any mbufs in the process. */ 3588 DBRUNIF((sc->rx_mbuf_alloc), 3589 aprint_error("%s: Memory leak! Lost %d mbufs from rx chain!\n", 3590 sc->bnx_dev.dv_xname, sc->rx_mbuf_alloc)); 3591 3592 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3593 } 3594 3595 /****************************************************************************/ 3596 /* Set media options. */ 3597 /* */ 3598 /* Returns: */ 3599 /* 0 for success, positive value for failure. */ 3600 /****************************************************************************/ 3601 int 3602 bnx_ifmedia_upd(struct ifnet *ifp) 3603 { 3604 struct bnx_softc *sc; 3605 struct mii_data *mii; 3606 struct ifmedia *ifm; 3607 int rc = 0; 3608 3609 sc = ifp->if_softc; 3610 ifm = &sc->bnx_ifmedia; 3611 3612 /* DRC - ToDo: Add SerDes support. */ 3613 3614 mii = &sc->bnx_mii; 3615 sc->bnx_link = 0; 3616 if (mii->mii_instance) { 3617 struct mii_softc *miisc; 3618 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3619 miisc = LIST_NEXT(miisc, mii_list)) 3620 mii_phy_reset(miisc); 3621 } 3622 mii_mediachg(mii); 3623 3624 return(rc); 3625 } 3626 3627 /****************************************************************************/ 3628 /* Reports current media status. */ 3629 /* */ 3630 /* Returns: */ 3631 /* Nothing. */ 3632 /****************************************************************************/ 3633 void 3634 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3635 { 3636 struct bnx_softc *sc; 3637 struct mii_data *mii; 3638 int s; 3639 3640 sc = ifp->if_softc; 3641 3642 s = splnet(); 3643 3644 mii = &sc->bnx_mii; 3645 3646 /* DRC - ToDo: Add SerDes support. */ 3647 3648 mii_pollstat(mii); 3649 ifmr->ifm_active = mii->mii_media_active; 3650 ifmr->ifm_status = mii->mii_media_status; 3651 3652 splx(s); 3653 } 3654 3655 /****************************************************************************/ 3656 /* Handles PHY generated interrupt events. */ 3657 /* */ 3658 /* Returns: */ 3659 /* Nothing. */ 3660 /****************************************************************************/ 3661 void 3662 bnx_phy_intr(struct bnx_softc *sc) 3663 { 3664 u_int32_t new_link_state, old_link_state; 3665 3666 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3667 BUS_DMASYNC_POSTREAD); 3668 new_link_state = sc->status_block->status_attn_bits & 3669 STATUS_ATTN_BITS_LINK_STATE; 3670 old_link_state = sc->status_block->status_attn_bits_ack & 3671 STATUS_ATTN_BITS_LINK_STATE; 3672 3673 /* Handle any changes if the link state has changed. */ 3674 if (new_link_state != old_link_state) { 3675 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 3676 3677 sc->bnx_link = 0; 3678 callout_stop(&sc->bnx_timeout); 3679 bnx_tick(sc); 3680 3681 /* Update the status_attn_bits_ack field in the status block. */ 3682 if (new_link_state) { 3683 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 3684 STATUS_ATTN_BITS_LINK_STATE); 3685 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 3686 } else { 3687 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 3688 STATUS_ATTN_BITS_LINK_STATE); 3689 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 3690 } 3691 } 3692 3693 /* Acknowledge the link change interrupt. */ 3694 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 3695 } 3696 3697 /****************************************************************************/ 3698 /* Handles received frame interrupt events. */ 3699 /* */ 3700 /* Returns: */ 3701 /* Nothing. */ 3702 /****************************************************************************/ 3703 void 3704 bnx_rx_intr(struct bnx_softc *sc) 3705 { 3706 struct status_block *sblk = sc->status_block; 3707 struct ifnet *ifp = &sc->ethercom.ec_if; 3708 u_int16_t hw_cons, sw_cons, sw_chain_cons; 3709 u_int16_t sw_prod, sw_chain_prod; 3710 u_int32_t sw_prod_bseq; 3711 struct l2_fhdr *l2fhdr; 3712 int i; 3713 3714 DBRUNIF(1, sc->rx_interrupts++); 3715 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3716 BUS_DMASYNC_POSTREAD); 3717 3718 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3719 for (i = 0; i < RX_PAGES; i++) 3720 bus_dmamap_sync(sc->bnx_dmatag, 3721 sc->rx_bd_chain_map[i], 0, 3722 sc->rx_bd_chain_map[i]->dm_mapsize, 3723 BUS_DMASYNC_POSTWRITE); 3724 3725 /* Get the hardware's view of the RX consumer index. */ 3726 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3727 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3728 hw_cons++; 3729 3730 /* Get working copies of the driver's view of the RX indices. */ 3731 sw_cons = sc->rx_cons; 3732 sw_prod = sc->rx_prod; 3733 sw_prod_bseq = sc->rx_prod_bseq; 3734 3735 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3736 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3737 __FUNCTION__, sw_prod, sw_cons, sw_prod_bseq); 3738 3739 /* Prevent speculative reads from getting ahead of the status block. */ 3740 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3741 BUS_SPACE_BARRIER_READ); 3742 3743 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3744 sc->rx_low_watermark = sc->free_rx_bd); 3745 3746 /* 3747 * Scan through the receive chain as long 3748 * as there is work to do. 3749 */ 3750 while (sw_cons != hw_cons) { 3751 struct mbuf *m; 3752 struct rx_bd *rxbd; 3753 unsigned int len; 3754 u_int32_t status; 3755 3756 /* Convert the producer/consumer indices to an actual 3757 * rx_bd index. 3758 */ 3759 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3760 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3761 3762 /* Get the used rx_bd. */ 3763 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3764 sc->free_rx_bd++; 3765 3766 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __FUNCTION__); 3767 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 3768 3769 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3770 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3771 /* Validate that this is the last rx_bd. */ 3772 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), 3773 aprint_error("%s: Unexpected mbuf found in " 3774 "rx_bd[0x%04X]!\n", sc->bnx_dev.dv_xname, 3775 sw_chain_cons); 3776 bnx_breakpoint(sc)); 3777 3778 /* DRC - ToDo: If the received packet is small, say less 3779 * than 128 bytes, allocate a new mbuf here, 3780 * copy the data to that mbuf, and recycle 3781 * the mapped jumbo frame. 3782 */ 3783 3784 /* Unmap the mbuf from DMA space. */ 3785 bus_dmamap_sync(sc->bnx_dmatag, 3786 sc->rx_mbuf_map[sw_chain_cons], 0, 3787 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 3788 BUS_DMASYNC_POSTREAD); 3789 bus_dmamap_unload(sc->bnx_dmatag, 3790 sc->rx_mbuf_map[sw_chain_cons]); 3791 3792 /* Remove the mbuf from the driver's chain. */ 3793 m = sc->rx_mbuf_ptr[sw_chain_cons]; 3794 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 3795 3796 /* 3797 * Frames received on the NetXteme II are prepended 3798 * with the l2_fhdr structure which provides status 3799 * information about the received frame (including 3800 * VLAN tags and checksum info) and are also 3801 * automatically adjusted to align the IP header 3802 * (i.e. two null bytes are inserted before the 3803 * Ethernet header). 3804 */ 3805 l2fhdr = mtod(m, struct l2_fhdr *); 3806 3807 len = l2fhdr->l2_fhdr_pkt_len; 3808 status = l2fhdr->l2_fhdr_status; 3809 3810 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 3811 aprint_error("Simulating l2_fhdr status error.\n"); 3812 status = status | L2_FHDR_ERRORS_PHY_DECODE); 3813 3814 /* Watch for unusual sized frames. */ 3815 DBRUNIF(((len < BNX_MIN_MTU) || 3816 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 3817 aprint_error("%s: Unusual frame size found. " 3818 "Min(%d), Actual(%d), Max(%d)\n", 3819 sc->bnx_dev.dv_xname, (int)BNX_MIN_MTU, len, 3820 (int) BNX_MAX_JUMBO_ETHER_MTU_VLAN); 3821 3822 bnx_dump_mbuf(sc, m); 3823 bnx_breakpoint(sc)); 3824 3825 len -= ETHER_CRC_LEN; 3826 3827 /* Check the received frame for errors. */ 3828 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 3829 L2_FHDR_ERRORS_PHY_DECODE | 3830 L2_FHDR_ERRORS_ALIGNMENT | 3831 L2_FHDR_ERRORS_TOO_SHORT | 3832 L2_FHDR_ERRORS_GIANT_FRAME)) || 3833 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 3834 len > 3835 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 3836 ifp->if_ierrors++; 3837 DBRUNIF(1, sc->l2fhdr_status_errors++); 3838 3839 /* Reuse the mbuf for a new frame. */ 3840 if (bnx_get_buf(sc, m, &sw_prod, 3841 &sw_chain_prod, &sw_prod_bseq)) { 3842 DBRUNIF(1, bnx_breakpoint(sc)); 3843 panic("%s: Can't reuse RX mbuf!\n", 3844 sc->bnx_dev.dv_xname); 3845 } 3846 goto bnx_rx_int_next_rx; 3847 } 3848 3849 /* 3850 * Get a new mbuf for the rx_bd. If no new 3851 * mbufs are available then reuse the current mbuf, 3852 * log an ierror on the interface, and generate 3853 * an error in the system log. 3854 */ 3855 if (bnx_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, 3856 &sw_prod_bseq)) { 3857 DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate " 3858 "new mbuf, incoming frame dropped!\n")); 3859 3860 ifp->if_ierrors++; 3861 3862 /* Try and reuse the exisitng mbuf. */ 3863 if (bnx_get_buf(sc, m, &sw_prod, 3864 &sw_chain_prod, &sw_prod_bseq)) { 3865 DBRUNIF(1, bnx_breakpoint(sc)); 3866 panic("%s: Double mbuf allocation " 3867 "failure!", sc->bnx_dev.dv_xname); 3868 } 3869 goto bnx_rx_int_next_rx; 3870 } 3871 3872 /* Skip over the l2_fhdr when passing the data up 3873 * the stack. 3874 */ 3875 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 3876 3877 /* Adjust the pckt length to match the received data. */ 3878 m->m_pkthdr.len = m->m_len = len; 3879 3880 /* Send the packet to the appropriate interface. */ 3881 m->m_pkthdr.rcvif = ifp; 3882 3883 DBRUN(BNX_VERBOSE_RECV, 3884 struct ether_header *eh; 3885 eh = mtod(m, struct ether_header *); 3886 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 3887 __FUNCTION__, ether_sprintf(eh->ether_dhost), 3888 ether_sprintf(eh->ether_shost), 3889 htons(eh->ether_type))); 3890 3891 /* Validate the checksum. */ 3892 3893 /* Check for an IP datagram. */ 3894 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 3895 /* Check if the IP checksum is valid. */ 3896 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 3897 == 0) 3898 m->m_pkthdr.csum_flags |= 3899 M_CSUM_IPv4; 3900 #ifdef BNX_DEBUG 3901 else 3902 DBPRINT(sc, BNX_WARN_SEND, 3903 "%s(): Invalid IP checksum " 3904 "= 0x%04X!\n", 3905 __FUNCTION__, 3906 l2fhdr->l2_fhdr_ip_xsum 3907 ); 3908 #endif 3909 } 3910 3911 /* Check for a valid TCP/UDP frame. */ 3912 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3913 L2_FHDR_STATUS_UDP_DATAGRAM)) { 3914 /* Check for a good TCP/UDP checksum. */ 3915 if ((status & 3916 (L2_FHDR_ERRORS_TCP_XSUM | 3917 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 3918 m->m_pkthdr.csum_flags |= 3919 M_CSUM_TCPv4 | 3920 M_CSUM_UDPv4; 3921 } else { 3922 DBPRINT(sc, BNX_WARN_SEND, 3923 "%s(): Invalid TCP/UDP " 3924 "checksum = 0x%04X!\n", 3925 __FUNCTION__, 3926 l2fhdr->l2_fhdr_tcp_udp_xsum); 3927 } 3928 } 3929 3930 /* 3931 * If we received a packet with a vlan tag, 3932 * attach that information to the packet. 3933 */ 3934 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 3935 #if 0 3936 struct ether_vlan_header vh; 3937 3938 DBPRINT(sc, BNX_VERBOSE_SEND, 3939 "%s(): VLAN tag = 0x%04X\n", 3940 __FUNCTION__, 3941 l2fhdr->l2_fhdr_vlan_tag); 3942 3943 if (m->m_pkthdr.len < ETHER_HDR_LEN) { 3944 m_freem(m); 3945 goto bnx_rx_int_next_rx; 3946 } 3947 m_copydata(m, 0, ETHER_HDR_LEN, (caddr_t)&vh); 3948 vh.evl_proto = vh.evl_encap_proto; 3949 vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag >> 16; 3950 vh.evl_encap_proto = htons(ETHERTYPE_VLAN); 3951 m_adj(m, ETHER_HDR_LEN); 3952 if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL) 3953 goto bnx_rx_int_next_rx; 3954 m->m_pkthdr.len += sizeof(vh); 3955 if (m->m_len < sizeof(vh) && 3956 (m = m_pullup(m, sizeof(vh))) == NULL) 3957 goto bnx_rx_int_next_rx; 3958 m_copyback(m, 0, sizeof(vh), &vh); 3959 #else 3960 VLAN_INPUT_TAG(ifp, m, 3961 l2fhdr->l2_fhdr_vlan_tag >> 16, 3962 goto bnx_rx_int_next_rx); 3963 #endif 3964 } 3965 3966 #if NBPFILTER > 0 3967 /* 3968 * Handle BPF listeners. Let the BPF 3969 * user see the packet. 3970 */ 3971 if (ifp->if_bpf) 3972 bpf_mtap(ifp->if_bpf, m); 3973 #endif 3974 3975 /* Pass the mbuf off to the upper layers. */ 3976 ifp->if_ipackets++; 3977 DBPRINT(sc, BNX_VERBOSE_RECV, 3978 "%s(): Passing received frame up.\n", __FUNCTION__); 3979 //ether_input_mbuf(ifp, m); 3980 (*ifp->if_input)(ifp, m); 3981 DBRUNIF(1, sc->rx_mbuf_alloc--); 3982 3983 bnx_rx_int_next_rx: 3984 sw_prod = NEXT_RX_BD(sw_prod); 3985 } 3986 3987 sw_cons = NEXT_RX_BD(sw_cons); 3988 3989 /* Refresh hw_cons to see if there's new work */ 3990 if (sw_cons == hw_cons) { 3991 hw_cons = sc->hw_rx_cons = 3992 sblk->status_rx_quick_consumer_index0; 3993 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 3994 USABLE_RX_BD_PER_PAGE) 3995 hw_cons++; 3996 } 3997 3998 /* Prevent speculative reads from getting ahead of 3999 * the status block. 4000 */ 4001 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4002 BUS_SPACE_BARRIER_READ); 4003 } 4004 4005 for (i = 0; i < RX_PAGES; i++) 4006 bus_dmamap_sync(sc->bnx_dmatag, 4007 sc->rx_bd_chain_map[i], 0, 4008 sc->rx_bd_chain_map[i]->dm_mapsize, 4009 BUS_DMASYNC_PREWRITE); 4010 4011 sc->rx_cons = sw_cons; 4012 sc->rx_prod = sw_prod; 4013 sc->rx_prod_bseq = sw_prod_bseq; 4014 4015 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4016 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4017 4018 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4019 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4020 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4021 } 4022 4023 /****************************************************************************/ 4024 /* Handles transmit completion interrupt events. */ 4025 /* */ 4026 /* Returns: */ 4027 /* Nothing. */ 4028 /****************************************************************************/ 4029 void 4030 bnx_tx_intr(struct bnx_softc *sc) 4031 { 4032 struct status_block *sblk = sc->status_block; 4033 struct ifnet *ifp = &sc->ethercom.ec_if; 4034 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4035 4036 DBRUNIF(1, sc->tx_interrupts++); 4037 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4038 BUS_DMASYNC_POSTREAD); 4039 4040 /* Get the hardware's view of the TX consumer index. */ 4041 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4042 4043 /* Skip to the next entry if this is a chain page pointer. */ 4044 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4045 hw_tx_cons++; 4046 4047 sw_tx_cons = sc->tx_cons; 4048 4049 /* Prevent speculative reads from getting ahead of the status block. */ 4050 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4051 BUS_SPACE_BARRIER_READ); 4052 4053 /* Cycle through any completed TX chain page entries. */ 4054 while (sw_tx_cons != hw_tx_cons) { 4055 #ifdef BNX_DEBUG 4056 struct tx_bd *txbd = NULL; 4057 #endif 4058 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4059 4060 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4061 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4062 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4063 4064 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4065 aprint_error("%s: TX chain consumer out of range! " 4066 " 0x%04X > 0x%04X\n", sc->bnx_dev.dv_xname, 4067 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4068 4069 DBRUNIF(1, txbd = &sc->tx_bd_chain 4070 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4071 4072 DBRUNIF((txbd == NULL), 4073 aprint_error("%s: Unexpected NULL tx_bd[0x%04X]!\n", 4074 sc->bnx_dev.dv_xname, sw_tx_chain_cons); 4075 bnx_breakpoint(sc)); 4076 4077 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __FUNCTION__); 4078 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4079 4080 /* 4081 * Free the associated mbuf. Remember 4082 * that only the last tx_bd of a packet 4083 * has an mbuf pointer and DMA map. 4084 */ 4085 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 4086 /* Validate that this is the last tx_bd. */ 4087 DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & 4088 TX_BD_FLAGS_END)), 4089 aprint_error("%s: tx_bd END flag not set but " 4090 "txmbuf == NULL!\n", sc->bnx_dev.dv_xname); 4091 bnx_breakpoint(sc)); 4092 4093 DBRUN(BNX_INFO_SEND, 4094 aprint_debug("%s: Unloading map/freeing mbuf " 4095 "from tx_bd[0x%04X]\n", 4096 __FUNCTION__, sw_tx_chain_cons)); 4097 4098 /* Unmap the mbuf. */ 4099 bus_dmamap_unload(sc->bnx_dmatag, 4100 sc->tx_mbuf_map[sw_tx_chain_cons]); 4101 4102 /* Free the mbuf. */ 4103 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 4104 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 4105 DBRUNIF(1, sc->tx_mbuf_alloc--); 4106 4107 ifp->if_opackets++; 4108 } 4109 4110 sc->used_tx_bd--; 4111 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4112 4113 /* Refresh hw_cons to see if there's new work. */ 4114 hw_tx_cons = sc->hw_tx_cons = 4115 sblk->status_tx_quick_consumer_index0; 4116 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4117 USABLE_TX_BD_PER_PAGE) 4118 hw_tx_cons++; 4119 4120 /* Prevent speculative reads from getting ahead of 4121 * the status block. 4122 */ 4123 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4124 BUS_SPACE_BARRIER_READ); 4125 } 4126 4127 /* Clear the TX timeout timer. */ 4128 ifp->if_timer = 0; 4129 4130 /* Clear the tx hardware queue full flag. */ 4131 if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) { 4132 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4133 aprint_debug("%s: TX chain is open for business! Used " 4134 "tx_bd = %d\n", sc->bnx_dev.dv_xname, 4135 sc->used_tx_bd)); 4136 ifp->if_flags &= ~IFF_OACTIVE; 4137 } 4138 4139 sc->tx_cons = sw_tx_cons; 4140 } 4141 4142 /****************************************************************************/ 4143 /* Disables interrupt generation. */ 4144 /* */ 4145 /* Returns: */ 4146 /* Nothing. */ 4147 /****************************************************************************/ 4148 void 4149 bnx_disable_intr(struct bnx_softc *sc) 4150 { 4151 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4152 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4153 } 4154 4155 /****************************************************************************/ 4156 /* Enables interrupt generation. */ 4157 /* */ 4158 /* Returns: */ 4159 /* Nothing. */ 4160 /****************************************************************************/ 4161 void 4162 bnx_enable_intr(struct bnx_softc *sc) 4163 { 4164 u_int32_t val; 4165 4166 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4167 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4168 4169 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4170 sc->last_status_idx); 4171 4172 val = REG_RD(sc, BNX_HC_COMMAND); 4173 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4174 } 4175 4176 /****************************************************************************/ 4177 /* Handles controller initialization. */ 4178 /* */ 4179 /****************************************************************************/ 4180 int 4181 bnx_init(struct ifnet *ifp) 4182 { 4183 struct bnx_softc *sc = ifp->if_softc; 4184 u_int32_t ether_mtu; 4185 int s, error = 0; 4186 4187 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4188 4189 s = splnet(); 4190 4191 bnx_stop(sc); 4192 4193 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4194 aprint_error("bnx: Controller reset failed!\n"); 4195 goto bnx_init_locked_exit; 4196 } 4197 4198 if ((error = bnx_chipinit(sc)) != 0) { 4199 aprint_error("bnx: Controller initialization failed!\n"); 4200 goto bnx_init_locked_exit; 4201 } 4202 4203 if ((error = bnx_blockinit(sc)) != 0) { 4204 aprint_error("bnx: Block initialization failed!\n"); 4205 goto bnx_init_locked_exit; 4206 } 4207 4208 /* Calculate and program the Ethernet MRU size. */ 4209 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4210 4211 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4212 __FUNCTION__, ether_mtu); 4213 4214 /* 4215 * Program the MRU and enable Jumbo frame 4216 * support. 4217 */ 4218 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4219 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4220 4221 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4222 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4223 4224 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4225 "max_frame_size = %d\n", __FUNCTION__, (int)MCLBYTES, 4226 sc->mbuf_alloc_size, sc->max_frame_size); 4227 4228 /* Program appropriate promiscuous/multicast filtering. */ 4229 bnx_set_rx_mode(sc); 4230 4231 /* Init RX buffer descriptor chain. */ 4232 bnx_init_rx_chain(sc); 4233 4234 /* Init TX buffer descriptor chain. */ 4235 bnx_init_tx_chain(sc); 4236 4237 /* Enable host interrupts. */ 4238 bnx_enable_intr(sc); 4239 4240 bnx_ifmedia_upd(ifp); 4241 4242 ifp->if_flags |= IFF_RUNNING; 4243 ifp->if_flags &= ~IFF_OACTIVE; 4244 4245 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4246 4247 bnx_init_locked_exit: 4248 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4249 4250 splx(s); 4251 4252 return(error); 4253 } 4254 4255 /****************************************************************************/ 4256 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4257 /* memory visible to the controller. */ 4258 /* */ 4259 /* Returns: */ 4260 /* 0 for success, positive value for failure. */ 4261 /****************************************************************************/ 4262 int 4263 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m_head, u_int16_t *prod, 4264 u_int16_t *chain_prod, u_int32_t *prod_bseq) 4265 { 4266 u_int32_t vlan_tag_flags = 0; 4267 struct bnx_dmamap_arg map_arg; 4268 bus_dmamap_t map; 4269 int i, rc = 0; 4270 struct m_tag *mtag; 4271 4272 /* Transfer any checksum offload flags to the bd. */ 4273 if (m_head->m_pkthdr.csum_flags) { 4274 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4275 vlan_tag_flags |= TX_BD_FLAGS_IP_CKSUM; 4276 if (m_head->m_pkthdr.csum_flags & 4277 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4278 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4279 } 4280 4281 /* Transfer any VLAN tags to the bd. */ 4282 mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head); 4283 if (mtag != NULL) 4284 vlan_tag_flags |= (TX_BD_FLAGS_VLAN_TAG | 4285 VLAN_TAG_VALUE(mtag)); 4286 4287 /* Map the mbuf into DMAable memory. */ 4288 map = sc->tx_mbuf_map[*chain_prod]; 4289 map_arg.sc = sc; 4290 map_arg.prod = *prod; 4291 map_arg.chain_prod = *chain_prod; 4292 map_arg.prod_bseq = *prod_bseq; 4293 map_arg.tx_flags = vlan_tag_flags; 4294 map_arg.maxsegs = USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE; 4295 4296 #if 0 4297 KASSERT(map_arg.maxsegs > 0, ("Invalid TX maxsegs value!")); 4298 #endif 4299 4300 for (i = 0; i < TX_PAGES; i++) 4301 map_arg.tx_chain[i] = sc->tx_bd_chain[i]; 4302 4303 /* Map the mbuf into our DMA address space. */ 4304 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_head, 4305 BUS_DMA_NOWAIT)) { 4306 aprint_error("%s: Error mapping mbuf into TX chain!\n", 4307 sc->bnx_dev.dv_xname); 4308 rc = ENOBUFS; 4309 goto bnx_tx_encap_exit; 4310 } 4311 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4312 BUS_DMASYNC_PREWRITE); 4313 bnx_dma_map_tx_desc(&map_arg, map); 4314 4315 /* 4316 * Ensure that the map for this transmission 4317 * is placed at the array index of the last 4318 * descriptor in this chain. This is done 4319 * because a single map is used for all 4320 * segments of the mbuf and we don't want to 4321 * delete the map before all of the segments 4322 * have been freed. 4323 */ 4324 sc->tx_mbuf_map[*chain_prod] = sc->tx_mbuf_map[map_arg.chain_prod]; 4325 sc->tx_mbuf_map[map_arg.chain_prod] = map; 4326 sc->tx_mbuf_ptr[map_arg.chain_prod] = m_head; 4327 sc->used_tx_bd += map_arg.maxsegs; 4328 4329 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4330 sc->tx_hi_watermark = sc->used_tx_bd); 4331 4332 DBRUNIF(1, sc->tx_mbuf_alloc++); 4333 4334 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, *chain_prod, 4335 map_arg.maxsegs)); 4336 4337 /* prod still points the last used tx_bd at this point. */ 4338 *prod = map_arg.prod; 4339 *chain_prod = map_arg.chain_prod; 4340 *prod_bseq = map_arg.prod_bseq; 4341 4342 bnx_tx_encap_exit: 4343 4344 return(rc); 4345 } 4346 4347 /****************************************************************************/ 4348 /* Main transmit routine. */ 4349 /* */ 4350 /* Returns: */ 4351 /* Nothing. */ 4352 /****************************************************************************/ 4353 void 4354 bnx_start(struct ifnet *ifp) 4355 { 4356 struct bnx_softc *sc = ifp->if_softc; 4357 struct mbuf *m_head = NULL; 4358 int count = 0; 4359 u_int16_t tx_prod, tx_chain_prod; 4360 u_int32_t tx_prod_bseq; 4361 4362 /* If there's no link or the transmit queue is empty then just exit. */ 4363 if (!sc->bnx_link || IFQ_IS_EMPTY(&ifp->if_snd)) { 4364 DBPRINT(sc, BNX_INFO_SEND, 4365 "%s(): No link or transmit queue empty.\n", __FUNCTION__); 4366 goto bnx_start_locked_exit; 4367 } 4368 4369 /* prod points to the next free tx_bd. */ 4370 tx_prod = sc->tx_prod; 4371 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4372 tx_prod_bseq = sc->tx_prod_bseq; 4373 4374 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 4375 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n", 4376 __FUNCTION__, tx_prod, tx_chain_prod, tx_prod_bseq); 4377 4378 /* Keep adding entries while there is space in the ring. */ 4379 while (sc->tx_mbuf_ptr[tx_chain_prod] == NULL) { 4380 /* Check for any frames to send. */ 4381 IFQ_POLL(&ifp->if_snd, m_head); 4382 if (m_head == NULL) 4383 break; 4384 4385 /* 4386 * Pack the data into the transmit ring. If we 4387 * don't have room, place the mbuf back at the 4388 * head of the queue and set the OACTIVE flag 4389 * to wait for the NIC to drain the chain. 4390 */ 4391 if (bnx_tx_encap(sc, m_head, &tx_prod, &tx_chain_prod, 4392 &tx_prod_bseq)) { 4393 ifp->if_flags |= IFF_OACTIVE; 4394 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 4395 "business! Total tx_bd used = %d\n", 4396 sc->used_tx_bd); 4397 break; 4398 } 4399 4400 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4401 count++; 4402 4403 #if NBPFILTER > 0 4404 /* Send a copy of the frame to any BPF listeners. */ 4405 if (ifp->if_bpf) 4406 bpf_mtap(ifp->if_bpf, m_head); 4407 #endif 4408 tx_prod = NEXT_TX_BD(tx_prod); 4409 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4410 } 4411 4412 if (count == 0) { 4413 /* no packets were dequeued */ 4414 DBPRINT(sc, BNX_VERBOSE_SEND, 4415 "%s(): No packets were dequeued\n", __FUNCTION__); 4416 goto bnx_start_locked_exit; 4417 } 4418 4419 /* Update the driver's counters. */ 4420 sc->tx_prod = tx_prod; 4421 sc->tx_prod_bseq = tx_prod_bseq; 4422 4423 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 4424 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __FUNCTION__, tx_prod, 4425 tx_chain_prod, tx_prod_bseq); 4426 4427 /* Start the transmit. */ 4428 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4429 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4430 4431 /* Set the tx timeout. */ 4432 ifp->if_timer = BNX_TX_TIMEOUT; 4433 4434 bnx_start_locked_exit: 4435 return; 4436 } 4437 4438 /****************************************************************************/ 4439 /* Handles any IOCTL calls from the operating system. */ 4440 /* */ 4441 /* Returns: */ 4442 /* 0 for success, positive value for failure. */ 4443 /****************************************************************************/ 4444 int 4445 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4446 { 4447 struct bnx_softc *sc = ifp->if_softc; 4448 struct ifreq *ifr = (struct ifreq *) data; 4449 struct mii_data *mii; 4450 int s, error = 0; 4451 4452 s = splnet(); 4453 4454 switch (command) { 4455 case SIOCSIFFLAGS: 4456 if (ifp->if_flags & IFF_UP) { 4457 if ((ifp->if_flags & IFF_RUNNING) && 4458 ((ifp->if_flags ^ sc->bnx_if_flags) & 4459 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 4460 bnx_set_rx_mode(sc); 4461 } else if (!(ifp->if_flags & IFF_RUNNING)) 4462 bnx_init(ifp); 4463 4464 } else if (ifp->if_flags & IFF_RUNNING) 4465 bnx_stop(sc); 4466 4467 sc->bnx_if_flags = ifp->if_flags; 4468 break; 4469 4470 case SIOCSIFMEDIA: 4471 case SIOCGIFMEDIA: 4472 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 4473 sc->bnx_phy_flags); 4474 4475 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 4476 error = ifmedia_ioctl(ifp, ifr, 4477 &sc->bnx_ifmedia, command); 4478 else { 4479 mii = &sc->bnx_mii; 4480 error = ifmedia_ioctl(ifp, ifr, 4481 &mii->mii_media, command); 4482 } 4483 break; 4484 4485 default: 4486 error = ether_ioctl(ifp, command, data); 4487 if (error == ENETRESET) { 4488 #if 0 4489 if (ifp->if_flags & IFF_RUNNING) 4490 /*bnx_setmulti(sc)*/; 4491 #endif 4492 error = 0; 4493 } 4494 break; 4495 } 4496 4497 splx(s); 4498 4499 return (error); 4500 } 4501 4502 /****************************************************************************/ 4503 /* Transmit timeout handler. */ 4504 /* */ 4505 /* Returns: */ 4506 /* Nothing. */ 4507 /****************************************************************************/ 4508 void 4509 bnx_watchdog(struct ifnet *ifp) 4510 { 4511 struct bnx_softc *sc = ifp->if_softc; 4512 4513 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 4514 bnx_dump_status_block(sc)); 4515 4516 aprint_error("%s: Watchdog timeout -- resetting!\n", 4517 sc->bnx_dev.dv_xname); 4518 4519 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 4520 4521 bnx_init(ifp); 4522 4523 ifp->if_oerrors++; 4524 } 4525 4526 /* 4527 * Interrupt handler. 4528 */ 4529 /****************************************************************************/ 4530 /* Main interrupt entry point. Verifies that the controller generated the */ 4531 /* interrupt and then calls a separate routine for handle the various */ 4532 /* interrupt causes (PHY, TX, RX). */ 4533 /* */ 4534 /* Returns: */ 4535 /* 0 for success, positive value for failure. */ 4536 /****************************************************************************/ 4537 int 4538 bnx_intr(void *xsc) 4539 { 4540 struct bnx_softc *sc; 4541 struct ifnet *ifp; 4542 u_int32_t status_attn_bits; 4543 4544 sc = xsc; 4545 ifp = &sc->ethercom.ec_if; 4546 4547 DBRUNIF(1, sc->interrupts_generated++); 4548 4549 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4550 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4551 4552 /* 4553 * If the hardware status block index 4554 * matches the last value read by the 4555 * driver and we haven't asserted our 4556 * interrupt then there's nothing to do. 4557 */ 4558 if ((sc->status_block->status_idx == sc->last_status_idx) && 4559 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 4560 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 4561 return (0); 4562 4563 /* Ack the interrupt and stop others from occuring. */ 4564 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4565 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 4566 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4567 4568 /* Keep processing data as long as there is work to do. */ 4569 for (;;) { 4570 status_attn_bits = sc->status_block->status_attn_bits; 4571 4572 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 4573 aprint_debug("Simulating unexpected status attention bit set."); 4574 status_attn_bits = status_attn_bits | 4575 STATUS_ATTN_BITS_PARITY_ERROR); 4576 4577 /* Was it a link change interrupt? */ 4578 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 4579 (sc->status_block->status_attn_bits_ack & 4580 STATUS_ATTN_BITS_LINK_STATE)) 4581 bnx_phy_intr(sc); 4582 4583 /* If any other attention is asserted then the chip is toast. */ 4584 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 4585 (sc->status_block->status_attn_bits_ack & 4586 ~STATUS_ATTN_BITS_LINK_STATE))) { 4587 DBRUN(1, sc->unexpected_attentions++); 4588 4589 aprint_error("%s: Fatal attention detected: 0x%08X\n", 4590 sc->bnx_dev.dv_xname, 4591 sc->status_block->status_attn_bits); 4592 4593 DBRUN(BNX_FATAL, 4594 if (bnx_debug_unexpected_attention == 0) 4595 bnx_breakpoint(sc)); 4596 4597 bnx_init(ifp); 4598 return (1); 4599 } 4600 4601 /* Check for any completed RX frames. */ 4602 if (sc->status_block->status_rx_quick_consumer_index0 != 4603 sc->hw_rx_cons) 4604 bnx_rx_intr(sc); 4605 4606 /* Check for any completed TX frames. */ 4607 if (sc->status_block->status_tx_quick_consumer_index0 != 4608 sc->hw_tx_cons) 4609 bnx_tx_intr(sc); 4610 4611 /* Save the status block index value for use during the 4612 * next interrupt. 4613 */ 4614 sc->last_status_idx = sc->status_block->status_idx; 4615 4616 /* Prevent speculative reads from getting ahead of the 4617 * status block. 4618 */ 4619 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4620 BUS_SPACE_BARRIER_READ); 4621 4622 /* If there's no work left then exit the isr. */ 4623 if ((sc->status_block->status_rx_quick_consumer_index0 == 4624 sc->hw_rx_cons) && 4625 (sc->status_block->status_tx_quick_consumer_index0 == 4626 sc->hw_tx_cons)) 4627 break; 4628 } 4629 4630 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4631 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 4632 4633 /* Re-enable interrupts. */ 4634 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4635 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 4636 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4637 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4638 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4639 4640 /* Handle any frames that arrived while handling the interrupt. */ 4641 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4642 bnx_start(ifp); 4643 4644 return (1); 4645 } 4646 4647 /****************************************************************************/ 4648 /* Programs the various packet receive modes (broadcast and multicast). */ 4649 /* */ 4650 /* Returns: */ 4651 /* Nothing. */ 4652 /****************************************************************************/ 4653 void 4654 bnx_set_rx_mode(struct bnx_softc *sc) 4655 { 4656 struct ethercom *ec = &sc->ethercom; 4657 struct ifnet *ifp = &ec->ec_if; 4658 struct ether_multi *enm; 4659 struct ether_multistep step; 4660 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 4661 u_int32_t rx_mode, sort_mode; 4662 int h, i; 4663 4664 /* Initialize receive mode default settings. */ 4665 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 4666 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 4667 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 4668 4669 /* 4670 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 4671 * be enbled. 4672 */ 4673 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 4674 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 4675 4676 /* 4677 * Check for promiscuous, all multicast, or selected 4678 * multicast address filtering. 4679 */ 4680 if (ifp->if_flags & IFF_PROMISC) { 4681 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 4682 4683 /* Enable promiscuous mode. */ 4684 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 4685 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 4686 } else if (ifp->if_flags & IFF_ALLMULTI) { 4687 allmulti: 4688 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 4689 4690 /* Enable all multicast addresses. */ 4691 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4692 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4693 0xffffffff); 4694 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 4695 } else { 4696 /* Accept one or more multicast(s). */ 4697 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 4698 4699 ETHER_FIRST_MULTI(step, ec, enm); 4700 while (enm != NULL) { 4701 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 4702 ETHER_ADDR_LEN)) { 4703 ifp->if_flags |= IFF_ALLMULTI; 4704 goto allmulti; 4705 } 4706 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 4707 0x7F; 4708 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 4709 ETHER_NEXT_MULTI(step, enm); 4710 } 4711 4712 for (i = 0; i < 4; i++) 4713 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4714 hashes[i]); 4715 4716 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 4717 } 4718 4719 /* Only make changes if the recive mode has actually changed. */ 4720 if (rx_mode != sc->rx_mode) { 4721 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 4722 rx_mode); 4723 4724 sc->rx_mode = rx_mode; 4725 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 4726 } 4727 4728 /* Disable and clear the exisitng sort before enabling a new sort. */ 4729 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 4730 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 4731 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 4732 } 4733 4734 /****************************************************************************/ 4735 /* Called periodically to updates statistics from the controllers */ 4736 /* statistics block. */ 4737 /* */ 4738 /* Returns: */ 4739 /* Nothing. */ 4740 /****************************************************************************/ 4741 void 4742 bnx_stats_update(struct bnx_softc *sc) 4743 { 4744 struct ifnet *ifp = &sc->ethercom.ec_if; 4745 struct statistics_block *stats; 4746 4747 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 4748 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4749 BUS_DMASYNC_POSTREAD); 4750 4751 stats = (struct statistics_block *)sc->stats_block; 4752 4753 /* 4754 * Update the interface statistics from the 4755 * hardware statistics. 4756 */ 4757 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 4758 4759 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 4760 (u_long)stats->stat_EtherStatsOverrsizePkts + 4761 (u_long)stats->stat_IfInMBUFDiscards + 4762 (u_long)stats->stat_Dot3StatsAlignmentErrors + 4763 (u_long)stats->stat_Dot3StatsFCSErrors; 4764 4765 ifp->if_oerrors = (u_long) 4766 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 4767 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 4768 (u_long)stats->stat_Dot3StatsLateCollisions; 4769 4770 /* 4771 * Certain controllers don't report 4772 * carrier sense errors correctly. 4773 * See errata E11_5708CA0_1165. 4774 */ 4775 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 4776 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 4777 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 4778 4779 /* 4780 * Update the sysctl statistics from the 4781 * hardware statistics. 4782 */ 4783 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 4784 (u_int64_t) stats->stat_IfHCInOctets_lo; 4785 4786 sc->stat_IfHCInBadOctets = 4787 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 4788 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 4789 4790 sc->stat_IfHCOutOctets = 4791 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 4792 (u_int64_t) stats->stat_IfHCOutOctets_lo; 4793 4794 sc->stat_IfHCOutBadOctets = 4795 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 4796 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 4797 4798 sc->stat_IfHCInUcastPkts = 4799 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 4800 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 4801 4802 sc->stat_IfHCInMulticastPkts = 4803 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 4804 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 4805 4806 sc->stat_IfHCInBroadcastPkts = 4807 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 4808 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 4809 4810 sc->stat_IfHCOutUcastPkts = 4811 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 4812 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 4813 4814 sc->stat_IfHCOutMulticastPkts = 4815 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 4816 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 4817 4818 sc->stat_IfHCOutBroadcastPkts = 4819 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 4820 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 4821 4822 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 4823 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4824 4825 sc->stat_Dot3StatsCarrierSenseErrors = 4826 stats->stat_Dot3StatsCarrierSenseErrors; 4827 4828 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 4829 4830 sc->stat_Dot3StatsAlignmentErrors = 4831 stats->stat_Dot3StatsAlignmentErrors; 4832 4833 sc->stat_Dot3StatsSingleCollisionFrames = 4834 stats->stat_Dot3StatsSingleCollisionFrames; 4835 4836 sc->stat_Dot3StatsMultipleCollisionFrames = 4837 stats->stat_Dot3StatsMultipleCollisionFrames; 4838 4839 sc->stat_Dot3StatsDeferredTransmissions = 4840 stats->stat_Dot3StatsDeferredTransmissions; 4841 4842 sc->stat_Dot3StatsExcessiveCollisions = 4843 stats->stat_Dot3StatsExcessiveCollisions; 4844 4845 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 4846 4847 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 4848 4849 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 4850 4851 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 4852 4853 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 4854 4855 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 4856 4857 sc->stat_EtherStatsPktsRx64Octets = 4858 stats->stat_EtherStatsPktsRx64Octets; 4859 4860 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 4861 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 4862 4863 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 4864 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 4865 4866 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 4867 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 4868 4869 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 4870 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 4871 4872 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 4873 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 4874 4875 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 4876 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 4877 4878 sc->stat_EtherStatsPktsTx64Octets = 4879 stats->stat_EtherStatsPktsTx64Octets; 4880 4881 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 4882 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 4883 4884 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 4885 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 4886 4887 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 4888 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 4889 4890 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 4891 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 4892 4893 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 4894 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 4895 4896 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 4897 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 4898 4899 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 4900 4901 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 4902 4903 sc->stat_OutXonSent = stats->stat_OutXonSent; 4904 4905 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 4906 4907 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 4908 4909 sc->stat_MacControlFramesReceived = 4910 stats->stat_MacControlFramesReceived; 4911 4912 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 4913 4914 sc->stat_IfInFramesL2FilterDiscards = 4915 stats->stat_IfInFramesL2FilterDiscards; 4916 4917 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 4918 4919 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 4920 4921 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 4922 4923 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 4924 4925 sc->stat_CatchupInRuleCheckerDiscards = 4926 stats->stat_CatchupInRuleCheckerDiscards; 4927 4928 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 4929 4930 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 4931 4932 sc->stat_CatchupInRuleCheckerP4Hit = 4933 stats->stat_CatchupInRuleCheckerP4Hit; 4934 4935 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 4936 } 4937 4938 void 4939 bnx_tick(void *xsc) 4940 { 4941 struct bnx_softc *sc = xsc; 4942 struct ifnet *ifp = &sc->ethercom.ec_if; 4943 struct mii_data *mii = NULL; 4944 u_int32_t msg; 4945 4946 /* Tell the firmware that the driver is still running. */ 4947 #ifdef BNX_DEBUG 4948 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 4949 #else 4950 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 4951 #endif 4952 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 4953 4954 /* Update the statistics from the hardware statistics block. */ 4955 bnx_stats_update(sc); 4956 4957 /* Schedule the next tick. */ 4958 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4959 4960 /* If link is up already up then we're done. */ 4961 if (sc->bnx_link) 4962 goto bnx_tick_locked_exit; 4963 4964 /* DRC - ToDo: Add SerDes support and check SerDes link here. */ 4965 4966 mii = &sc->bnx_mii; 4967 mii_tick(mii); 4968 4969 /* Check if the link has come up. */ 4970 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 4971 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4972 sc->bnx_link++; 4973 /* Now that link is up, handle any outstanding TX traffic. */ 4974 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4975 bnx_start(ifp); 4976 } 4977 4978 bnx_tick_locked_exit: 4979 return; 4980 } 4981 4982 /****************************************************************************/ 4983 /* BNX Debug Routines */ 4984 /****************************************************************************/ 4985 #ifdef BNX_DEBUG 4986 4987 /****************************************************************************/ 4988 /* Prints out information about an mbuf. */ 4989 /* */ 4990 /* Returns: */ 4991 /* Nothing. */ 4992 /****************************************************************************/ 4993 void 4994 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 4995 { 4996 struct mbuf *mp = m; 4997 4998 if (m == NULL) { 4999 /* Index out of range. */ 5000 aprint_error("mbuf ptr is null!\n"); 5001 return; 5002 } 5003 5004 while (mp) { 5005 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5006 mp, mp->m_len); 5007 5008 if (mp->m_flags & M_EXT) 5009 aprint_debug("M_EXT "); 5010 if (mp->m_flags & M_PKTHDR) 5011 aprint_debug("M_PKTHDR "); 5012 aprint_debug("\n"); 5013 5014 if (mp->m_flags & M_EXT) 5015 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 5016 mp, mp->m_ext.ext_size); 5017 5018 mp = mp->m_next; 5019 } 5020 } 5021 5022 /****************************************************************************/ 5023 /* Prints out the mbufs in the TX mbuf chain. */ 5024 /* */ 5025 /* Returns: */ 5026 /* Nothing. */ 5027 /****************************************************************************/ 5028 void 5029 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5030 { 5031 struct mbuf *m; 5032 int i; 5033 5034 BNX_PRINTF(sc, 5035 "----------------------------" 5036 " tx mbuf data " 5037 "----------------------------\n"); 5038 5039 for (i = 0; i < count; i++) { 5040 m = sc->tx_mbuf_ptr[chain_prod]; 5041 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5042 bnx_dump_mbuf(sc, m); 5043 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5044 } 5045 5046 BNX_PRINTF(sc, 5047 "--------------------------------------------" 5048 "----------------------------\n"); 5049 } 5050 5051 /* 5052 * This routine prints the RX mbuf chain. 5053 */ 5054 void 5055 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5056 { 5057 struct mbuf *m; 5058 int i; 5059 5060 BNX_PRINTF(sc, 5061 "----------------------------" 5062 " rx mbuf data " 5063 "----------------------------\n"); 5064 5065 for (i = 0; i < count; i++) { 5066 m = sc->rx_mbuf_ptr[chain_prod]; 5067 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5068 bnx_dump_mbuf(sc, m); 5069 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5070 } 5071 5072 5073 BNX_PRINTF(sc, 5074 "--------------------------------------------" 5075 "----------------------------\n"); 5076 } 5077 5078 void 5079 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5080 { 5081 if (idx > MAX_TX_BD) 5082 /* Index out of range. */ 5083 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5084 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5085 /* TX Chain page pointer. */ 5086 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5087 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5088 txbd->tx_bd_haddr_lo); 5089 else 5090 /* Normal tx_bd entry. */ 5091 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5092 "0x%08X, flags = 0x%08X\n", idx, 5093 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5094 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag_flags); 5095 } 5096 5097 void 5098 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5099 { 5100 if (idx > MAX_RX_BD) 5101 /* Index out of range. */ 5102 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5103 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5104 /* TX Chain page pointer. */ 5105 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5106 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5107 rxbd->rx_bd_haddr_lo); 5108 else 5109 /* Normal tx_bd entry. */ 5110 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5111 "0x%08X, flags = 0x%08X\n", idx, 5112 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5113 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5114 } 5115 5116 void 5117 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5118 { 5119 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5120 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5121 "tcp_udp_xsum = 0x%04X\n", idx, 5122 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5123 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5124 l2fhdr->l2_fhdr_tcp_udp_xsum); 5125 } 5126 5127 /* 5128 * This routine prints the TX chain. 5129 */ 5130 void 5131 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5132 { 5133 struct tx_bd *txbd; 5134 int i; 5135 5136 /* First some info about the tx_bd chain structure. */ 5137 BNX_PRINTF(sc, 5138 "----------------------------" 5139 " tx_bd chain " 5140 "----------------------------\n"); 5141 5142 BNX_PRINTF(sc, 5143 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5144 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5145 5146 BNX_PRINTF(sc, 5147 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5148 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5149 5150 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD); 5151 5152 BNX_PRINTF(sc, "" 5153 "-----------------------------" 5154 " tx_bd data " 5155 "-----------------------------\n"); 5156 5157 /* Now print out the tx_bd's themselves. */ 5158 for (i = 0; i < count; i++) { 5159 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5160 bnx_dump_txbd(sc, tx_prod, txbd); 5161 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5162 } 5163 5164 BNX_PRINTF(sc, 5165 "-----------------------------" 5166 "--------------" 5167 "-----------------------------\n"); 5168 } 5169 5170 /* 5171 * This routine prints the RX chain. 5172 */ 5173 void 5174 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5175 { 5176 struct rx_bd *rxbd; 5177 int i; 5178 5179 /* First some info about the tx_bd chain structure. */ 5180 BNX_PRINTF(sc, 5181 "----------------------------" 5182 " rx_bd chain " 5183 "----------------------------\n"); 5184 5185 BNX_PRINTF(sc, "----- RX_BD Chain -----\n"); 5186 5187 BNX_PRINTF(sc, 5188 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5189 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5190 5191 BNX_PRINTF(sc, 5192 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5193 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5194 5195 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD); 5196 5197 BNX_PRINTF(sc, 5198 "----------------------------" 5199 " rx_bd data " 5200 "----------------------------\n"); 5201 5202 /* Now print out the rx_bd's themselves. */ 5203 for (i = 0; i < count; i++) { 5204 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5205 bnx_dump_rxbd(sc, rx_prod, rxbd); 5206 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5207 } 5208 5209 BNX_PRINTF(sc, 5210 "----------------------------" 5211 "--------------" 5212 "----------------------------\n"); 5213 } 5214 5215 /* 5216 * This routine prints the status block. 5217 */ 5218 void 5219 bnx_dump_status_block(struct bnx_softc *sc) 5220 { 5221 struct status_block *sblk; 5222 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5223 BUS_DMASYNC_POSTREAD); 5224 5225 sblk = sc->status_block; 5226 5227 BNX_PRINTF(sc, "----------------------------- Status Block " 5228 "-----------------------------\n"); 5229 5230 BNX_PRINTF(sc, 5231 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5232 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5233 sblk->status_idx); 5234 5235 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5236 sblk->status_rx_quick_consumer_index0, 5237 sblk->status_tx_quick_consumer_index0); 5238 5239 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5240 5241 /* Theses indices are not used for normal L2 drivers. */ 5242 if (sblk->status_rx_quick_consumer_index1 || 5243 sblk->status_tx_quick_consumer_index1) 5244 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5245 sblk->status_rx_quick_consumer_index1, 5246 sblk->status_tx_quick_consumer_index1); 5247 5248 if (sblk->status_rx_quick_consumer_index2 || 5249 sblk->status_tx_quick_consumer_index2) 5250 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5251 sblk->status_rx_quick_consumer_index2, 5252 sblk->status_tx_quick_consumer_index2); 5253 5254 if (sblk->status_rx_quick_consumer_index3 || 5255 sblk->status_tx_quick_consumer_index3) 5256 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5257 sblk->status_rx_quick_consumer_index3, 5258 sblk->status_tx_quick_consumer_index3); 5259 5260 if (sblk->status_rx_quick_consumer_index4 || 5261 sblk->status_rx_quick_consumer_index5) 5262 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5263 sblk->status_rx_quick_consumer_index4, 5264 sblk->status_rx_quick_consumer_index5); 5265 5266 if (sblk->status_rx_quick_consumer_index6 || 5267 sblk->status_rx_quick_consumer_index7) 5268 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5269 sblk->status_rx_quick_consumer_index6, 5270 sblk->status_rx_quick_consumer_index7); 5271 5272 if (sblk->status_rx_quick_consumer_index8 || 5273 sblk->status_rx_quick_consumer_index9) 5274 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5275 sblk->status_rx_quick_consumer_index8, 5276 sblk->status_rx_quick_consumer_index9); 5277 5278 if (sblk->status_rx_quick_consumer_index10 || 5279 sblk->status_rx_quick_consumer_index11) 5280 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5281 sblk->status_rx_quick_consumer_index10, 5282 sblk->status_rx_quick_consumer_index11); 5283 5284 if (sblk->status_rx_quick_consumer_index12 || 5285 sblk->status_rx_quick_consumer_index13) 5286 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5287 sblk->status_rx_quick_consumer_index12, 5288 sblk->status_rx_quick_consumer_index13); 5289 5290 if (sblk->status_rx_quick_consumer_index14 || 5291 sblk->status_rx_quick_consumer_index15) 5292 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5293 sblk->status_rx_quick_consumer_index14, 5294 sblk->status_rx_quick_consumer_index15); 5295 5296 if (sblk->status_completion_producer_index || 5297 sblk->status_cmd_consumer_index) 5298 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5299 sblk->status_completion_producer_index, 5300 sblk->status_cmd_consumer_index); 5301 5302 BNX_PRINTF(sc, "-------------------------------------------" 5303 "-----------------------------\n"); 5304 } 5305 5306 /* 5307 * This routine prints the statistics block. 5308 */ 5309 void 5310 bnx_dump_stats_block(struct bnx_softc *sc) 5311 { 5312 struct statistics_block *sblk; 5313 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5314 BUS_DMASYNC_POSTREAD); 5315 5316 sblk = sc->stats_block; 5317 5318 BNX_PRINTF(sc, "" 5319 "-----------------------------" 5320 " Stats Block " 5321 "-----------------------------\n"); 5322 5323 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5324 "IfHcInBadOctets = 0x%08X:%08X\n", 5325 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5326 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5327 5328 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5329 "IfHcOutBadOctets = 0x%08X:%08X\n", 5330 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5331 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5332 5333 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5334 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5335 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5336 sblk->stat_IfHCInMulticastPkts_hi, 5337 sblk->stat_IfHCInMulticastPkts_lo); 5338 5339 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5340 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5341 sblk->stat_IfHCInBroadcastPkts_hi, 5342 sblk->stat_IfHCInBroadcastPkts_lo, 5343 sblk->stat_IfHCOutUcastPkts_hi, 5344 sblk->stat_IfHCOutUcastPkts_lo); 5345 5346 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5347 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5348 sblk->stat_IfHCOutMulticastPkts_hi, 5349 sblk->stat_IfHCOutMulticastPkts_lo, 5350 sblk->stat_IfHCOutBroadcastPkts_hi, 5351 sblk->stat_IfHCOutBroadcastPkts_lo); 5352 5353 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5354 BNX_PRINTF(sc, "0x%08X : " 5355 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5356 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5357 5358 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5359 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5360 sblk->stat_Dot3StatsCarrierSenseErrors); 5361 5362 if (sblk->stat_Dot3StatsFCSErrors) 5363 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5364 sblk->stat_Dot3StatsFCSErrors); 5365 5366 if (sblk->stat_Dot3StatsAlignmentErrors) 5367 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5368 sblk->stat_Dot3StatsAlignmentErrors); 5369 5370 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5371 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5372 sblk->stat_Dot3StatsSingleCollisionFrames); 5373 5374 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5375 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 5376 sblk->stat_Dot3StatsMultipleCollisionFrames); 5377 5378 if (sblk->stat_Dot3StatsDeferredTransmissions) 5379 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 5380 sblk->stat_Dot3StatsDeferredTransmissions); 5381 5382 if (sblk->stat_Dot3StatsExcessiveCollisions) 5383 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 5384 sblk->stat_Dot3StatsExcessiveCollisions); 5385 5386 if (sblk->stat_Dot3StatsLateCollisions) 5387 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 5388 sblk->stat_Dot3StatsLateCollisions); 5389 5390 if (sblk->stat_EtherStatsCollisions) 5391 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 5392 sblk->stat_EtherStatsCollisions); 5393 5394 if (sblk->stat_EtherStatsFragments) 5395 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 5396 sblk->stat_EtherStatsFragments); 5397 5398 if (sblk->stat_EtherStatsJabbers) 5399 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 5400 sblk->stat_EtherStatsJabbers); 5401 5402 if (sblk->stat_EtherStatsUndersizePkts) 5403 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 5404 sblk->stat_EtherStatsUndersizePkts); 5405 5406 if (sblk->stat_EtherStatsOverrsizePkts) 5407 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 5408 sblk->stat_EtherStatsOverrsizePkts); 5409 5410 if (sblk->stat_EtherStatsPktsRx64Octets) 5411 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 5412 sblk->stat_EtherStatsPktsRx64Octets); 5413 5414 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 5415 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 5416 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 5417 5418 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 5419 BNX_PRINTF(sc, "0x%08X : " 5420 "EtherStatsPktsRx128Octetsto255Octets\n", 5421 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 5422 5423 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 5424 BNX_PRINTF(sc, "0x%08X : " 5425 "EtherStatsPktsRx256Octetsto511Octets\n", 5426 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 5427 5428 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 5429 BNX_PRINTF(sc, "0x%08X : " 5430 "EtherStatsPktsRx512Octetsto1023Octets\n", 5431 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 5432 5433 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 5434 BNX_PRINTF(sc, "0x%08X : " 5435 "EtherStatsPktsRx1024Octetsto1522Octets\n", 5436 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 5437 5438 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 5439 BNX_PRINTF(sc, "0x%08X : " 5440 "EtherStatsPktsRx1523Octetsto9022Octets\n", 5441 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 5442 5443 if (sblk->stat_EtherStatsPktsTx64Octets) 5444 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 5445 sblk->stat_EtherStatsPktsTx64Octets); 5446 5447 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 5448 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 5449 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 5450 5451 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 5452 BNX_PRINTF(sc, "0x%08X : " 5453 "EtherStatsPktsTx128Octetsto255Octets\n", 5454 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 5455 5456 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 5457 BNX_PRINTF(sc, "0x%08X : " 5458 "EtherStatsPktsTx256Octetsto511Octets\n", 5459 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 5460 5461 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 5462 BNX_PRINTF(sc, "0x%08X : " 5463 "EtherStatsPktsTx512Octetsto1023Octets\n", 5464 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 5465 5466 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 5467 BNX_PRINTF(sc, "0x%08X : " 5468 "EtherStatsPktsTx1024Octetsto1522Octets\n", 5469 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 5470 5471 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 5472 BNX_PRINTF(sc, "0x%08X : " 5473 "EtherStatsPktsTx1523Octetsto9022Octets\n", 5474 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 5475 5476 if (sblk->stat_XonPauseFramesReceived) 5477 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 5478 sblk->stat_XonPauseFramesReceived); 5479 5480 if (sblk->stat_XoffPauseFramesReceived) 5481 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 5482 sblk->stat_XoffPauseFramesReceived); 5483 5484 if (sblk->stat_OutXonSent) 5485 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 5486 sblk->stat_OutXonSent); 5487 5488 if (sblk->stat_OutXoffSent) 5489 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 5490 sblk->stat_OutXoffSent); 5491 5492 if (sblk->stat_FlowControlDone) 5493 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 5494 sblk->stat_FlowControlDone); 5495 5496 if (sblk->stat_MacControlFramesReceived) 5497 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 5498 sblk->stat_MacControlFramesReceived); 5499 5500 if (sblk->stat_XoffStateEntered) 5501 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 5502 sblk->stat_XoffStateEntered); 5503 5504 if (sblk->stat_IfInFramesL2FilterDiscards) 5505 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 5506 sblk->stat_IfInFramesL2FilterDiscards); 5507 5508 if (sblk->stat_IfInRuleCheckerDiscards) 5509 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 5510 sblk->stat_IfInRuleCheckerDiscards); 5511 5512 if (sblk->stat_IfInFTQDiscards) 5513 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 5514 sblk->stat_IfInFTQDiscards); 5515 5516 if (sblk->stat_IfInMBUFDiscards) 5517 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 5518 sblk->stat_IfInMBUFDiscards); 5519 5520 if (sblk->stat_IfInRuleCheckerP4Hit) 5521 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 5522 sblk->stat_IfInRuleCheckerP4Hit); 5523 5524 if (sblk->stat_CatchupInRuleCheckerDiscards) 5525 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 5526 sblk->stat_CatchupInRuleCheckerDiscards); 5527 5528 if (sblk->stat_CatchupInFTQDiscards) 5529 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 5530 sblk->stat_CatchupInFTQDiscards); 5531 5532 if (sblk->stat_CatchupInMBUFDiscards) 5533 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 5534 sblk->stat_CatchupInMBUFDiscards); 5535 5536 if (sblk->stat_CatchupInRuleCheckerP4Hit) 5537 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 5538 sblk->stat_CatchupInRuleCheckerP4Hit); 5539 5540 BNX_PRINTF(sc, 5541 "-----------------------------" 5542 "--------------" 5543 "-----------------------------\n"); 5544 } 5545 5546 void 5547 bnx_dump_driver_state(struct bnx_softc *sc) 5548 { 5549 BNX_PRINTF(sc, 5550 "-----------------------------" 5551 " Driver State " 5552 "-----------------------------\n"); 5553 5554 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 5555 "address\n", sc); 5556 5557 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 5558 sc->status_block); 5559 5560 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 5561 "address\n", sc->stats_block); 5562 5563 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 5564 "adddress\n", sc->tx_bd_chain); 5565 5566 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 5567 sc->rx_bd_chain); 5568 5569 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 5570 sc->tx_mbuf_ptr); 5571 5572 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 5573 sc->rx_mbuf_ptr); 5574 5575 BNX_PRINTF(sc, 5576 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 5577 sc->interrupts_generated); 5578 5579 BNX_PRINTF(sc, 5580 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 5581 sc->rx_interrupts); 5582 5583 BNX_PRINTF(sc, 5584 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 5585 sc->tx_interrupts); 5586 5587 BNX_PRINTF(sc, 5588 " 0x%08X - (sc->last_status_idx) status block index\n", 5589 sc->last_status_idx); 5590 5591 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 5592 sc->tx_prod); 5593 5594 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 5595 sc->tx_cons); 5596 5597 BNX_PRINTF(sc, 5598 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 5599 sc->tx_prod_bseq); 5600 5601 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 5602 sc->rx_prod); 5603 5604 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 5605 sc->rx_cons); 5606 5607 BNX_PRINTF(sc, 5608 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 5609 sc->rx_prod_bseq); 5610 5611 BNX_PRINTF(sc, 5612 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5613 sc->rx_mbuf_alloc); 5614 5615 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 5616 sc->free_rx_bd); 5617 5618 BNX_PRINTF(sc, 5619 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 5620 sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD); 5621 5622 BNX_PRINTF(sc, 5623 " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 5624 sc->tx_mbuf_alloc); 5625 5626 BNX_PRINTF(sc, 5627 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5628 sc->rx_mbuf_alloc); 5629 5630 BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 5631 sc->used_tx_bd); 5632 5633 BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 5634 sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD); 5635 5636 BNX_PRINTF(sc, 5637 " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 5638 sc->mbuf_alloc_failed); 5639 5640 BNX_PRINTF(sc, "-------------------------------------------" 5641 "-----------------------------\n"); 5642 } 5643 5644 void 5645 bnx_dump_hw_state(struct bnx_softc *sc) 5646 { 5647 u_int32_t val1; 5648 int i; 5649 5650 BNX_PRINTF(sc, 5651 "----------------------------" 5652 " Hardware State " 5653 "----------------------------\n"); 5654 5655 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 5656 5657 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 5658 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 5659 val1, BNX_MISC_ENABLE_STATUS_BITS); 5660 5661 val1 = REG_RD(sc, BNX_DMA_STATUS); 5662 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 5663 5664 val1 = REG_RD(sc, BNX_CTX_STATUS); 5665 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 5666 5667 val1 = REG_RD(sc, BNX_EMAC_STATUS); 5668 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 5669 BNX_EMAC_STATUS); 5670 5671 val1 = REG_RD(sc, BNX_RPM_STATUS); 5672 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 5673 5674 val1 = REG_RD(sc, BNX_TBDR_STATUS); 5675 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 5676 BNX_TBDR_STATUS); 5677 5678 val1 = REG_RD(sc, BNX_TDMA_STATUS); 5679 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 5680 BNX_TDMA_STATUS); 5681 5682 val1 = REG_RD(sc, BNX_HC_STATUS); 5683 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 5684 5685 BNX_PRINTF(sc, 5686 "----------------------------" 5687 "----------------" 5688 "----------------------------\n"); 5689 5690 BNX_PRINTF(sc, 5691 "----------------------------" 5692 " Register Dump " 5693 "----------------------------\n"); 5694 5695 for (i = 0x400; i < 0x8000; i += 0x10) 5696 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 5697 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 5698 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 5699 5700 BNX_PRINTF(sc, 5701 "----------------------------" 5702 "----------------" 5703 "----------------------------\n"); 5704 } 5705 5706 void 5707 bnx_breakpoint(struct bnx_softc *sc) 5708 { 5709 /* Unreachable code to shut the compiler up about unused functions. */ 5710 if (0) { 5711 bnx_dump_txbd(sc, 0, NULL); 5712 bnx_dump_rxbd(sc, 0, NULL); 5713 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 5714 bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 5715 bnx_dump_l2fhdr(sc, 0, NULL); 5716 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 5717 bnx_dump_rx_chain(sc, 0, USABLE_RX_BD); 5718 bnx_dump_status_block(sc); 5719 bnx_dump_stats_block(sc); 5720 bnx_dump_driver_state(sc); 5721 bnx_dump_hw_state(sc); 5722 } 5723 5724 bnx_dump_driver_state(sc); 5725 /* Print the important status block fields. */ 5726 bnx_dump_status_block(sc); 5727 5728 #if 0 5729 /* Call the debugger. */ 5730 breakpoint(); 5731 #endif 5732 5733 return; 5734 } 5735 #endif 5736
Indexes created Tue Sep 23 02:09:52 GMT 2025