if_bnx.c revision 1.100
1 /* $NetBSD: if_bnx.c,v 1.100 2020/07/16 14:44:43 jdolecek Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.100 2020/07/16 14:44:43 jdolecek Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 device_t dev = sc->bnx_dev; 466 int i = 0; 467 468 aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 469 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 470 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 471 ? "Serdes " : "", sc->bnx_chipid); 472 473 /* Bus info. */ 474 if (sc->bnx_flags & BNX_PCIE_FLAG) { 475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); 476 switch (sc->link_speed) { 477 case 1: aprint_normal("2.5GT/s\n"); break; 478 case 2: aprint_normal("5GT/s\n"); break; 479 default: aprint_normal("Unknown link speed\n"); 480 } 481 } else { 482 aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n", 483 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 484 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 485 sc->bus_speed_mhz); 486 } 487 488 /* Firmware version and device features. */ 489 aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (", 490 sc->bnx_bc_ver, RX_PAGES, TX_PAGES); 491 492 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) { 493 if (i > 0) aprint_normal("|"); 494 aprint_normal("2.5G"); i++; 495 } 496 497 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 498 if (i > 0) aprint_normal("|"); 499 aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver); 500 } else { 501 aprint_normal(")\n"); 502 } 503 504 aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 505 sc->bnx_rx_quick_cons_trip_int, 506 sc->bnx_rx_quick_cons_trip, 507 sc->bnx_rx_ticks_int, 508 sc->bnx_rx_ticks, 509 sc->bnx_tx_quick_cons_trip_int, 510 sc->bnx_tx_quick_cons_trip, 511 sc->bnx_tx_ticks_int, 512 sc->bnx_tx_ticks); 513 } 514 515 516 /****************************************************************************/ 517 /* PCI Capabilities Probe Function. */ 518 /* */ 519 /* Walks the PCI capabiites list for the device to find what features are */ 520 /* supported. */ 521 /* */ 522 /* Returns: */ 523 /* None. */ 524 /****************************************************************************/ 525 static void 526 bnx_probe_pci_caps(struct bnx_softc *sc) 527 { 528 struct pci_attach_args *pa = &(sc->bnx_pa); 529 pcireg_t reg; 530 531 /* Check if PCI-X capability is enabled. */ 532 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 533 NULL) != 0) { 534 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 535 } 536 537 /* Check if PCIe capability is enabled. */ 538 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 539 NULL) != 0) { 540 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 541 reg + PCIE_LCSR); 542 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 543 "0x%08X\n", link_status); 544 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 546 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 547 sc->bnx_flags |= BNX_PCIE_FLAG; 548 } 549 550 /* Check if MSI capability is enabled. */ 551 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 552 NULL) != 0) 553 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 554 555 /* Check if MSI-X capability is enabled. */ 556 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 557 NULL) != 0) 558 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 559 } 560 561 562 /****************************************************************************/ 563 /* Device attach function. */ 564 /* */ 565 /* Allocates device resources, performs secondary chip identification, */ 566 /* resets and initializes the hardware, and initializes driver instance */ 567 /* variables. */ 568 /* */ 569 /* Returns: */ 570 /* 0 on success, positive value on failure. */ 571 /****************************************************************************/ 572 void 573 bnx_attach(device_t parent, device_t self, void *aux) 574 { 575 const struct bnx_product *bp; 576 struct bnx_softc *sc = device_private(self); 577 prop_dictionary_t dict; 578 struct pci_attach_args *pa = aux; 579 pci_chipset_tag_t pc = pa->pa_pc; 580 const char *intrstr = NULL; 581 uint32_t command; 582 struct ifnet *ifp; 583 struct mii_data * const mii = &sc->bnx_mii; 584 uint32_t val; 585 int mii_flags = MIIF_FORCEANEG; 586 pcireg_t memtype; 587 char intrbuf[PCI_INTRSTR_LEN]; 588 int i, j; 589 590 if (bnx_tx_pool == NULL) { 591 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_WAITOK); 592 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 593 0, 0, 0, "bnxpkts", NULL, IPL_NET); 594 } 595 596 bp = bnx_lookup(pa); 597 if (bp == NULL) 598 panic("unknown device"); 599 600 sc->bnx_dev = self; 601 602 aprint_naive("\n"); 603 aprint_normal(": %s\n", bp->bp_name); 604 605 sc->bnx_pa = *pa; 606 607 /* 608 * Map control/status registers. 609 */ 610 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 611 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 612 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 613 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 614 615 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 616 aprint_error_dev(sc->bnx_dev, 617 "failed to enable memory mapping!\n"); 618 return; 619 } 620 621 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 622 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 623 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 624 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 625 return; 626 } 627 628 /* XXX using MSI-X causes TX timeouts, needs to be debugged */ 629 int counts[PCI_INTR_TYPE_SIZE] = { 630 [PCI_INTR_TYPE_INTX] = 1, 631 [PCI_INTR_TYPE_MSI] = 0, 632 [PCI_INTR_TYPE_MSIX] = 0, 633 }; 634 635 if (pci_intr_alloc(pa, &sc->bnx_ih, counts, PCI_INTR_TYPE_INTX)) { 636 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 637 goto bnx_attach_fail; 638 } 639 intrstr = pci_intr_string(pc, sc->bnx_ih[0], intrbuf, sizeof(intrbuf)); 640 641 /* 642 * Configure byte swap and enable indirect register access. 643 * Rely on CPU to do target byte swapping on big endian systems. 644 * Access to registers outside of PCI configurtion space are not 645 * valid until this is done. 646 */ 647 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 648 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 649 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 650 651 /* Save ASIC revision info. */ 652 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 653 654 /* 655 * Find the base address for shared memory access. 656 * Newer versions of bootcode use a signature and offset 657 * while older versions use a fixed address. 658 */ 659 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 660 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 661 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 662 (sc->bnx_pa.pa_function << 2)); 663 else 664 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 665 666 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 667 668 /* Set initial device and PHY flags */ 669 sc->bnx_flags = 0; 670 sc->bnx_phy_flags = 0; 671 672 /* Fetch the bootcode revision. */ 673 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 674 for (i = 0, j = 0; i < 3; i++) { 675 uint8_t num; 676 int k, skip0; 677 678 num = (uint8_t)(val >> (24 - (i * 8))); 679 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 680 if (num >= k || !skip0 || k == 1) { 681 sc->bnx_bc_ver[j++] = (num / k) + '0'; 682 skip0 = 0; 683 } 684 } 685 if (i != 2) 686 sc->bnx_bc_ver[j++] = '.'; 687 } 688 689 /* Check if any management firmware is enabled. */ 690 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 691 if (val & BNX_PORT_FEATURE_ASF_ENABLED) { 692 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 693 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 694 695 /* Allow time for firmware to enter the running state. */ 696 for (i = 0; i < 30; i++) { 697 val = REG_RD_IND(sc, sc->bnx_shmem_base + 698 BNX_BC_STATE_CONDITION); 699 if (val & BNX_CONDITION_MFW_RUN_MASK) 700 break; 701 DELAY(10000); 702 } 703 704 /* Check if management firmware is running. */ 705 val = REG_RD_IND(sc, sc->bnx_shmem_base + 706 BNX_BC_STATE_CONDITION); 707 val &= BNX_CONDITION_MFW_RUN_MASK; 708 if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) && 709 (val != BNX_CONDITION_MFW_RUN_NONE)) { 710 uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base + 711 BNX_MFW_VER_PTR); 712 713 /* Read the management firmware version string. */ 714 for (j = 0; j < 3; j++) { 715 val = bnx_reg_rd_ind(sc, addr + j * 4); 716 val = bswap32(val); 717 memcpy(&sc->bnx_mfw_ver[i], &val, 4); 718 i += 4; 719 } 720 } else { 721 /* May cause firmware synchronization timeouts. */ 722 BNX_PRINTF(sc, "%s(%d): Management firmware enabled " 723 "but not running!\n", __FILE__, __LINE__); 724 strcpy(sc->bnx_mfw_ver, "NOT RUNNING!"); 725 726 /* ToDo: Any action the driver should take? */ 727 } 728 } 729 730 bnx_probe_pci_caps(sc); 731 732 /* Get PCI bus information (speed and type). */ 733 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 734 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 735 uint32_t clkreg; 736 737 sc->bnx_flags |= BNX_PCIX_FLAG; 738 739 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 740 741 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 742 switch (clkreg) { 743 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 744 sc->bus_speed_mhz = 133; 745 break; 746 747 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 748 sc->bus_speed_mhz = 100; 749 break; 750 751 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 752 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 753 sc->bus_speed_mhz = 66; 754 break; 755 756 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 757 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 758 sc->bus_speed_mhz = 50; 759 break; 760 761 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 762 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 763 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 764 sc->bus_speed_mhz = 33; 765 break; 766 } 767 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 768 sc->bus_speed_mhz = 66; 769 else 770 sc->bus_speed_mhz = 33; 771 772 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 773 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 774 775 /* Reset the controller. */ 776 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 777 goto bnx_attach_fail; 778 779 /* Initialize the controller. */ 780 if (bnx_chipinit(sc)) { 781 aprint_error_dev(sc->bnx_dev, 782 "Controller initialization failed!\n"); 783 goto bnx_attach_fail; 784 } 785 786 /* Perform NVRAM test. */ 787 if (bnx_nvram_test(sc)) { 788 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 789 goto bnx_attach_fail; 790 } 791 792 /* Fetch the permanent Ethernet MAC address. */ 793 bnx_get_mac_addr(sc); 794 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 795 ether_sprintf(sc->eaddr)); 796 797 /* 798 * Trip points control how many BDs 799 * should be ready before generating an 800 * interrupt while ticks control how long 801 * a BD can sit in the chain before 802 * generating an interrupt. Set the default 803 * values for the RX and TX rings. 804 */ 805 806 #ifdef BNX_DEBUG 807 /* Force more frequent interrupts. */ 808 sc->bnx_tx_quick_cons_trip_int = 1; 809 sc->bnx_tx_quick_cons_trip = 1; 810 sc->bnx_tx_ticks_int = 0; 811 sc->bnx_tx_ticks = 0; 812 813 sc->bnx_rx_quick_cons_trip_int = 1; 814 sc->bnx_rx_quick_cons_trip = 1; 815 sc->bnx_rx_ticks_int = 0; 816 sc->bnx_rx_ticks = 0; 817 #else 818 sc->bnx_tx_quick_cons_trip_int = 20; 819 sc->bnx_tx_quick_cons_trip = 20; 820 sc->bnx_tx_ticks_int = 80; 821 sc->bnx_tx_ticks = 80; 822 823 sc->bnx_rx_quick_cons_trip_int = 6; 824 sc->bnx_rx_quick_cons_trip = 6; 825 sc->bnx_rx_ticks_int = 18; 826 sc->bnx_rx_ticks = 18; 827 #endif 828 829 /* Update statistics once every second. */ 830 sc->bnx_stats_ticks = 1000000 & 0xffff00; 831 832 /* Find the media type for the adapter. */ 833 bnx_get_media(sc); 834 835 /* 836 * Store config data needed by the PHY driver for 837 * backplane applications 838 */ 839 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 840 BNX_SHARED_HW_CFG_CONFIG); 841 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 842 BNX_PORT_HW_CFG_CONFIG); 843 844 /* Allocate DMA memory resources. */ 845 sc->bnx_dmatag = pa->pa_dmat; 846 if (bnx_dma_alloc(sc)) { 847 aprint_error_dev(sc->bnx_dev, 848 "DMA resource allocation failed!\n"); 849 goto bnx_attach_fail; 850 } 851 852 /* Initialize the ifnet interface. */ 853 ifp = &sc->bnx_ec.ec_if; 854 ifp->if_softc = sc; 855 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 856 ifp->if_ioctl = bnx_ioctl; 857 ifp->if_stop = bnx_stop; 858 ifp->if_start = bnx_start; 859 ifp->if_init = bnx_init; 860 ifp->if_watchdog = bnx_watchdog; 861 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 862 IFQ_SET_READY(&ifp->if_snd); 863 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 864 865 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 866 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 867 sc->bnx_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 868 869 ifp->if_capabilities |= 870 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 871 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 872 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 873 874 /* create workqueue to handle packet allocations */ 875 if (workqueue_create(&sc->bnx_wq, device_xname(self), 876 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 877 aprint_error_dev(self, "failed to create workqueue\n"); 878 goto bnx_attach_fail; 879 } 880 881 mii->mii_ifp = ifp; 882 mii->mii_readreg = bnx_miibus_read_reg; 883 mii->mii_writereg = bnx_miibus_write_reg; 884 mii->mii_statchg = bnx_miibus_statchg; 885 886 /* Handle any special PHY initialization for SerDes PHYs. */ 887 bnx_init_media(sc); 888 889 sc->bnx_ec.ec_mii = mii; 890 ifmedia_init(&mii->mii_media, 0, bnx_ifmedia_upd, bnx_ifmedia_sts); 891 892 /* set phyflags and chipid before mii_attach() */ 893 dict = device_properties(self); 894 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 895 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 896 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 897 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 898 899 /* Print some useful adapter info */ 900 bnx_print_adapter_info(sc); 901 902 mii_flags |= MIIF_DOPAUSE; 903 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 904 mii_flags |= MIIF_HAVEFIBER; 905 mii_attach(self, mii, 0xffffffff, 906 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 907 908 if (LIST_EMPTY(&mii->mii_phys)) { 909 aprint_error_dev(self, "no PHY found!\n"); 910 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 911 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 912 } else 913 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 914 915 /* Attach to the Ethernet interface list. */ 916 if_attach(ifp); 917 if_deferred_start_init(ifp, NULL); 918 ether_ifattach(ifp, sc->eaddr); 919 920 callout_init(&sc->bnx_timeout, 0); 921 callout_setfunc(&sc->bnx_timeout, bnx_tick, sc); 922 923 /* Hookup IRQ last. */ 924 sc->bnx_intrhand = pci_intr_establish_xname(pc, sc->bnx_ih[0], IPL_NET, 925 bnx_intr, sc, device_xname(self)); 926 if (sc->bnx_intrhand == NULL) { 927 aprint_error_dev(self, "couldn't establish interrupt"); 928 if (intrstr != NULL) 929 aprint_error(" at %s", intrstr); 930 aprint_error("\n"); 931 goto bnx_attach_fail; 932 } 933 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 934 935 if (pmf_device_register(self, NULL, NULL)) 936 pmf_class_network_register(self, ifp); 937 else 938 aprint_error_dev(self, "couldn't establish power handler\n"); 939 940 /* Print some important debugging info. */ 941 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 942 943 /* Get the firmware running so ASF still works. */ 944 bnx_mgmt_init(sc); 945 946 goto bnx_attach_exit; 947 948 bnx_attach_fail: 949 bnx_release_resources(sc); 950 951 bnx_attach_exit: 952 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 953 } 954 955 /****************************************************************************/ 956 /* Device detach function. */ 957 /* */ 958 /* Stops the controller, resets the controller, and releases resources. */ 959 /* */ 960 /* Returns: */ 961 /* 0 on success, positive value on failure. */ 962 /****************************************************************************/ 963 int 964 bnx_detach(device_t dev, int flags) 965 { 966 int s; 967 struct bnx_softc *sc; 968 struct ifnet *ifp; 969 970 sc = device_private(dev); 971 ifp = &sc->bnx_ec.ec_if; 972 973 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 974 975 /* Stop and reset the controller. */ 976 s = splnet(); 977 bnx_stop(ifp, 1); 978 splx(s); 979 980 pmf_device_deregister(dev); 981 callout_destroy(&sc->bnx_timeout); 982 ether_ifdetach(ifp); 983 workqueue_destroy(sc->bnx_wq); 984 985 if_detach(ifp); 986 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 987 988 /* Delete all remaining media. */ 989 ifmedia_fini(&sc->bnx_mii.mii_media); 990 991 /* Release all remaining resources. */ 992 bnx_release_resources(sc); 993 994 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 995 996 return 0; 997 } 998 999 /****************************************************************************/ 1000 /* Indirect register read. */ 1001 /* */ 1002 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1003 /* configuration space. Using this mechanism avoids issues with posted */ 1004 /* reads but is much slower than memory-mapped I/O. */ 1005 /* */ 1006 /* Returns: */ 1007 /* The value of the register. */ 1008 /****************************************************************************/ 1009 uint32_t 1010 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 1011 { 1012 struct pci_attach_args *pa = &(sc->bnx_pa); 1013 1014 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1015 offset); 1016 #ifdef BNX_DEBUG 1017 { 1018 uint32_t val; 1019 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 1020 BNX_PCICFG_REG_WINDOW); 1021 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 1022 "val = 0x%08X\n", __func__, offset, val); 1023 return val; 1024 } 1025 #else 1026 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 1027 #endif 1028 } 1029 1030 /****************************************************************************/ 1031 /* Indirect register write. */ 1032 /* */ 1033 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1034 /* configuration space. Using this mechanism avoids issues with posted */ 1035 /* writes but is muchh slower than memory-mapped I/O. */ 1036 /* */ 1037 /* Returns: */ 1038 /* Nothing. */ 1039 /****************************************************************************/ 1040 void 1041 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 1042 { 1043 struct pci_attach_args *pa = &(sc->bnx_pa); 1044 1045 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 1046 __func__, offset, val); 1047 1048 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1049 offset); 1050 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 1051 } 1052 1053 /****************************************************************************/ 1054 /* Context memory write. */ 1055 /* */ 1056 /* The NetXtreme II controller uses context memory to track connection */ 1057 /* information for L2 and higher network protocols. */ 1058 /* */ 1059 /* Returns: */ 1060 /* Nothing. */ 1061 /****************************************************************************/ 1062 void 1063 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 1064 uint32_t ctx_val) 1065 { 1066 uint32_t idx, offset = ctx_offset + cid_addr; 1067 uint32_t val, retry_cnt = 5; 1068 1069 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1070 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1071 REG_WR(sc, BNX_CTX_CTX_CTRL, 1072 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 1073 1074 for (idx = 0; idx < retry_cnt; idx++) { 1075 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1076 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1077 break; 1078 DELAY(5); 1079 } 1080 1081 #if 0 1082 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1083 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1084 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1085 __FILE__, __LINE__, cid_addr, ctx_offset); 1086 #endif 1087 1088 } else { 1089 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1090 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1091 } 1092 } 1093 1094 /****************************************************************************/ 1095 /* PHY register read. */ 1096 /* */ 1097 /* Implements register reads on the MII bus. */ 1098 /* */ 1099 /* Returns: */ 1100 /* The value of the register. */ 1101 /****************************************************************************/ 1102 int 1103 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1104 { 1105 struct bnx_softc *sc = device_private(dev); 1106 uint32_t data; 1107 int i, rv = 0; 1108 1109 /* 1110 * The BCM5709S PHY is an IEEE Clause 45 PHY 1111 * with special mappings to work with IEEE 1112 * Clause 22 register accesses. 1113 */ 1114 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1115 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1116 reg += 0x10; 1117 } 1118 1119 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1120 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1121 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1122 1123 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1124 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1125 1126 DELAY(40); 1127 } 1128 1129 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1130 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1131 BNX_EMAC_MDIO_COMM_START_BUSY; 1132 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1133 1134 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1135 DELAY(10); 1136 1137 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1138 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1139 DELAY(5); 1140 1141 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1142 data &= BNX_EMAC_MDIO_COMM_DATA; 1143 1144 break; 1145 } 1146 } 1147 1148 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1149 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1150 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1151 rv = ETIMEDOUT; 1152 } else { 1153 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1154 *val = data & 0xffff; 1155 1156 DBPRINT(sc, BNX_EXCESSIVE, 1157 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1158 phy, (uint16_t) reg & 0xffff, *val); 1159 } 1160 1161 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1162 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1163 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1164 1165 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1166 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1167 1168 DELAY(40); 1169 } 1170 1171 return rv; 1172 } 1173 1174 /****************************************************************************/ 1175 /* PHY register write. */ 1176 /* */ 1177 /* Implements register writes on the MII bus. */ 1178 /* */ 1179 /* Returns: */ 1180 /* The value of the register. */ 1181 /****************************************************************************/ 1182 int 1183 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1184 { 1185 struct bnx_softc *sc = device_private(dev); 1186 uint32_t val1; 1187 int i, rv = 0; 1188 1189 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1190 "val = 0x%04hX\n", __func__, 1191 phy, (uint16_t) reg & 0xffff, val); 1192 1193 /* 1194 * The BCM5709S PHY is an IEEE Clause 45 PHY 1195 * with special mappings to work with IEEE 1196 * Clause 22 register accesses. 1197 */ 1198 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1199 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1200 reg += 0x10; 1201 } 1202 1203 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1204 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1205 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1206 1207 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1208 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1209 1210 DELAY(40); 1211 } 1212 1213 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1214 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1215 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1216 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1217 1218 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1219 DELAY(10); 1220 1221 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1222 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1223 DELAY(5); 1224 break; 1225 } 1226 } 1227 1228 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1229 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1230 __LINE__); 1231 rv = ETIMEDOUT; 1232 } 1233 1234 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1235 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1236 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1237 1238 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1239 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1240 1241 DELAY(40); 1242 } 1243 1244 return rv; 1245 } 1246 1247 /****************************************************************************/ 1248 /* MII bus status change. */ 1249 /* */ 1250 /* Called by the MII bus driver when the PHY establishes link to set the */ 1251 /* MAC interface registers. */ 1252 /* */ 1253 /* Returns: */ 1254 /* Nothing. */ 1255 /****************************************************************************/ 1256 void 1257 bnx_miibus_statchg(struct ifnet *ifp) 1258 { 1259 struct bnx_softc *sc = ifp->if_softc; 1260 struct mii_data *mii = &sc->bnx_mii; 1261 uint32_t rx_mode = sc->rx_mode; 1262 int val; 1263 1264 val = REG_RD(sc, BNX_EMAC_MODE); 1265 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1266 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1267 BNX_EMAC_MODE_25G); 1268 1269 /* 1270 * Get flow control negotiation result. 1271 */ 1272 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1273 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1274 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1275 mii->mii_media_active &= ~IFM_ETH_FMASK; 1276 } 1277 1278 /* Set MII or GMII interface based on the speed 1279 * negotiated by the PHY. 1280 */ 1281 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1282 case IFM_10_T: 1283 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1284 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1285 val |= BNX_EMAC_MODE_PORT_MII_10; 1286 break; 1287 } 1288 /* FALLTHROUGH */ 1289 case IFM_100_TX: 1290 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1291 val |= BNX_EMAC_MODE_PORT_MII; 1292 break; 1293 case IFM_2500_SX: 1294 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1295 val |= BNX_EMAC_MODE_25G; 1296 /* FALLTHROUGH */ 1297 case IFM_1000_T: 1298 case IFM_1000_SX: 1299 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1300 val |= BNX_EMAC_MODE_PORT_GMII; 1301 break; 1302 default: 1303 val |= BNX_EMAC_MODE_PORT_GMII; 1304 break; 1305 } 1306 1307 /* Set half or full duplex based on the duplicity 1308 * negotiated by the PHY. 1309 */ 1310 if ((mii->mii_media_active & IFM_HDX) != 0) { 1311 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1312 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1313 } else 1314 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1315 1316 REG_WR(sc, BNX_EMAC_MODE, val); 1317 1318 /* 1319 * 802.3x flow control 1320 */ 1321 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1322 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1323 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1324 } else { 1325 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1326 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1327 } 1328 1329 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1330 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1331 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1332 } else { 1333 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1334 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1335 } 1336 1337 /* Only make changes if the receive mode has actually changed. */ 1338 if (rx_mode != sc->rx_mode) { 1339 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1340 rx_mode); 1341 1342 sc->rx_mode = rx_mode; 1343 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1344 1345 bnx_init_rx_context(sc); 1346 } 1347 } 1348 1349 /****************************************************************************/ 1350 /* Acquire NVRAM lock. */ 1351 /* */ 1352 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1353 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1354 /* for use by the driver. */ 1355 /* */ 1356 /* Returns: */ 1357 /* 0 on success, positive value on failure. */ 1358 /****************************************************************************/ 1359 int 1360 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1361 { 1362 uint32_t val; 1363 int j; 1364 1365 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1366 1367 /* Request access to the flash interface. */ 1368 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1369 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1370 val = REG_RD(sc, BNX_NVM_SW_ARB); 1371 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1372 break; 1373 1374 DELAY(5); 1375 } 1376 1377 if (j >= NVRAM_TIMEOUT_COUNT) { 1378 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1379 return EBUSY; 1380 } 1381 1382 return 0; 1383 } 1384 1385 /****************************************************************************/ 1386 /* Release NVRAM lock. */ 1387 /* */ 1388 /* When the caller is finished accessing NVRAM the lock must be released. */ 1389 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1390 /* for use by the driver. */ 1391 /* */ 1392 /* Returns: */ 1393 /* 0 on success, positive value on failure. */ 1394 /****************************************************************************/ 1395 int 1396 bnx_release_nvram_lock(struct bnx_softc *sc) 1397 { 1398 int j; 1399 uint32_t val; 1400 1401 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1402 1403 /* Relinquish nvram interface. */ 1404 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1405 1406 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1407 val = REG_RD(sc, BNX_NVM_SW_ARB); 1408 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1409 break; 1410 1411 DELAY(5); 1412 } 1413 1414 if (j >= NVRAM_TIMEOUT_COUNT) { 1415 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1416 return EBUSY; 1417 } 1418 1419 return 0; 1420 } 1421 1422 #ifdef BNX_NVRAM_WRITE_SUPPORT 1423 /****************************************************************************/ 1424 /* Enable NVRAM write access. */ 1425 /* */ 1426 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1427 /* */ 1428 /* Returns: */ 1429 /* 0 on success, positive value on failure. */ 1430 /****************************************************************************/ 1431 int 1432 bnx_enable_nvram_write(struct bnx_softc *sc) 1433 { 1434 uint32_t val; 1435 1436 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1437 1438 val = REG_RD(sc, BNX_MISC_CFG); 1439 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1440 1441 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1442 int j; 1443 1444 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1445 REG_WR(sc, BNX_NVM_COMMAND, 1446 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1447 1448 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1449 DELAY(5); 1450 1451 val = REG_RD(sc, BNX_NVM_COMMAND); 1452 if (val & BNX_NVM_COMMAND_DONE) 1453 break; 1454 } 1455 1456 if (j >= NVRAM_TIMEOUT_COUNT) { 1457 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1458 return EBUSY; 1459 } 1460 } 1461 1462 return 0; 1463 } 1464 1465 /****************************************************************************/ 1466 /* Disable NVRAM write access. */ 1467 /* */ 1468 /* When the caller is finished writing to NVRAM write access must be */ 1469 /* disabled. */ 1470 /* */ 1471 /* Returns: */ 1472 /* Nothing. */ 1473 /****************************************************************************/ 1474 void 1475 bnx_disable_nvram_write(struct bnx_softc *sc) 1476 { 1477 uint32_t val; 1478 1479 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1480 1481 val = REG_RD(sc, BNX_MISC_CFG); 1482 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1483 } 1484 #endif 1485 1486 /****************************************************************************/ 1487 /* Enable NVRAM access. */ 1488 /* */ 1489 /* Before accessing NVRAM for read or write operations the caller must */ 1490 /* enabled NVRAM access. */ 1491 /* */ 1492 /* Returns: */ 1493 /* Nothing. */ 1494 /****************************************************************************/ 1495 void 1496 bnx_enable_nvram_access(struct bnx_softc *sc) 1497 { 1498 uint32_t val; 1499 1500 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1501 1502 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1503 /* Enable both bits, even on read. */ 1504 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1505 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1506 } 1507 1508 /****************************************************************************/ 1509 /* Disable NVRAM access. */ 1510 /* */ 1511 /* When the caller is finished accessing NVRAM access must be disabled. */ 1512 /* */ 1513 /* Returns: */ 1514 /* Nothing. */ 1515 /****************************************************************************/ 1516 void 1517 bnx_disable_nvram_access(struct bnx_softc *sc) 1518 { 1519 uint32_t val; 1520 1521 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1522 1523 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1524 1525 /* Disable both bits, even after read. */ 1526 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1527 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1528 } 1529 1530 #ifdef BNX_NVRAM_WRITE_SUPPORT 1531 /****************************************************************************/ 1532 /* Erase NVRAM page before writing. */ 1533 /* */ 1534 /* Non-buffered flash parts require that a page be erased before it is */ 1535 /* written. */ 1536 /* */ 1537 /* Returns: */ 1538 /* 0 on success, positive value on failure. */ 1539 /****************************************************************************/ 1540 int 1541 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1542 { 1543 uint32_t cmd; 1544 int j; 1545 1546 /* Buffered flash doesn't require an erase. */ 1547 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1548 return 0; 1549 1550 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1551 1552 /* Build an erase command. */ 1553 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1554 BNX_NVM_COMMAND_DOIT; 1555 1556 /* 1557 * Clear the DONE bit separately, set the NVRAM address to erase, 1558 * and issue the erase command. 1559 */ 1560 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1561 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1562 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1563 1564 /* Wait for completion. */ 1565 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1566 uint32_t val; 1567 1568 DELAY(5); 1569 1570 val = REG_RD(sc, BNX_NVM_COMMAND); 1571 if (val & BNX_NVM_COMMAND_DONE) 1572 break; 1573 } 1574 1575 if (j >= NVRAM_TIMEOUT_COUNT) { 1576 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1577 return EBUSY; 1578 } 1579 1580 return 0; 1581 } 1582 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1583 1584 /****************************************************************************/ 1585 /* Read a dword (32 bits) from NVRAM. */ 1586 /* */ 1587 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1588 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1589 /* */ 1590 /* Returns: */ 1591 /* 0 on success and the 32 bit value read, positive value on failure. */ 1592 /****************************************************************************/ 1593 int 1594 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1595 uint8_t *ret_val, uint32_t cmd_flags) 1596 { 1597 uint32_t cmd; 1598 int i, rc = 0; 1599 1600 /* Build the command word. */ 1601 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1602 1603 /* Calculate the offset for buffered flash if translation is used. */ 1604 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1605 offset = ((offset / sc->bnx_flash_info->page_size) << 1606 sc->bnx_flash_info->page_bits) + 1607 (offset % sc->bnx_flash_info->page_size); 1608 } 1609 1610 /* 1611 * Clear the DONE bit separately, set the address to read, 1612 * and issue the read. 1613 */ 1614 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1615 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1616 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1617 1618 /* Wait for completion. */ 1619 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1620 uint32_t val; 1621 1622 DELAY(5); 1623 1624 val = REG_RD(sc, BNX_NVM_COMMAND); 1625 if (val & BNX_NVM_COMMAND_DONE) { 1626 val = REG_RD(sc, BNX_NVM_READ); 1627 1628 val = be32toh(val); 1629 memcpy(ret_val, &val, 4); 1630 break; 1631 } 1632 } 1633 1634 /* Check for errors. */ 1635 if (i >= NVRAM_TIMEOUT_COUNT) { 1636 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1637 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1638 rc = EBUSY; 1639 } 1640 1641 return rc; 1642 } 1643 1644 #ifdef BNX_NVRAM_WRITE_SUPPORT 1645 /****************************************************************************/ 1646 /* Write a dword (32 bits) to NVRAM. */ 1647 /* */ 1648 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1649 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1650 /* enabled NVRAM write access. */ 1651 /* */ 1652 /* Returns: */ 1653 /* 0 on success, positive value on failure. */ 1654 /****************************************************************************/ 1655 int 1656 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1657 uint32_t cmd_flags) 1658 { 1659 uint32_t cmd, val32; 1660 int j; 1661 1662 /* Build the command word. */ 1663 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1664 1665 /* Calculate the offset for buffered flash if translation is used. */ 1666 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1667 offset = ((offset / sc->bnx_flash_info->page_size) << 1668 sc->bnx_flash_info->page_bits) + 1669 (offset % sc->bnx_flash_info->page_size); 1670 } 1671 1672 /* 1673 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1674 * set the NVRAM address to write, and issue the write command 1675 */ 1676 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1677 memcpy(&val32, val, 4); 1678 val32 = htobe32(val32); 1679 REG_WR(sc, BNX_NVM_WRITE, val32); 1680 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1681 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1682 1683 /* Wait for completion. */ 1684 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1685 DELAY(5); 1686 1687 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1688 break; 1689 } 1690 if (j >= NVRAM_TIMEOUT_COUNT) { 1691 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1692 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1693 return EBUSY; 1694 } 1695 1696 return 0; 1697 } 1698 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1699 1700 /****************************************************************************/ 1701 /* Initialize NVRAM access. */ 1702 /* */ 1703 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1704 /* access that device. */ 1705 /* */ 1706 /* Returns: */ 1707 /* 0 on success, positive value on failure. */ 1708 /****************************************************************************/ 1709 int 1710 bnx_init_nvram(struct bnx_softc *sc) 1711 { 1712 uint32_t val; 1713 int j, entry_count, rc = 0; 1714 struct flash_spec *flash; 1715 1716 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1717 1718 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1719 sc->bnx_flash_info = &flash_5709; 1720 goto bnx_init_nvram_get_flash_size; 1721 } 1722 1723 /* Determine the selected interface. */ 1724 val = REG_RD(sc, BNX_NVM_CFG1); 1725 1726 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1727 1728 /* 1729 * Flash reconfiguration is required to support additional 1730 * NVRAM devices not directly supported in hardware. 1731 * Check if the flash interface was reconfigured 1732 * by the bootcode. 1733 */ 1734 1735 if (val & 0x40000000) { 1736 /* Flash interface reconfigured by bootcode. */ 1737 1738 DBPRINT(sc, BNX_INFO_LOAD, 1739 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1740 1741 for (j = 0, flash = &flash_table[0]; j < entry_count; 1742 j++, flash++) { 1743 if ((val & FLASH_BACKUP_STRAP_MASK) == 1744 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1745 sc->bnx_flash_info = flash; 1746 break; 1747 } 1748 } 1749 } else { 1750 /* Flash interface not yet reconfigured. */ 1751 uint32_t mask; 1752 1753 DBPRINT(sc, BNX_INFO_LOAD, 1754 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1755 1756 if (val & (1 << 23)) 1757 mask = FLASH_BACKUP_STRAP_MASK; 1758 else 1759 mask = FLASH_STRAP_MASK; 1760 1761 /* Look for the matching NVRAM device configuration data. */ 1762 for (j = 0, flash = &flash_table[0]; j < entry_count; 1763 j++, flash++) { 1764 /* Check if the dev matches any of the known devices. */ 1765 if ((val & mask) == (flash->strapping & mask)) { 1766 /* Found a device match. */ 1767 sc->bnx_flash_info = flash; 1768 1769 /* Request access to the flash interface. */ 1770 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1771 return rc; 1772 1773 /* Reconfigure the flash interface. */ 1774 bnx_enable_nvram_access(sc); 1775 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1776 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1777 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1778 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1779 bnx_disable_nvram_access(sc); 1780 bnx_release_nvram_lock(sc); 1781 1782 break; 1783 } 1784 } 1785 } 1786 1787 /* Check if a matching device was found. */ 1788 if (j == entry_count) { 1789 sc->bnx_flash_info = NULL; 1790 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1791 __FILE__, __LINE__); 1792 rc = ENODEV; 1793 } 1794 1795 bnx_init_nvram_get_flash_size: 1796 /* Write the flash config data to the shared memory interface. */ 1797 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1798 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1799 if (val) 1800 sc->bnx_flash_size = val; 1801 else 1802 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1803 1804 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1805 "0x%08X\n", sc->bnx_flash_info->total_size); 1806 1807 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1808 1809 return rc; 1810 } 1811 1812 /****************************************************************************/ 1813 /* Read an arbitrary range of data from NVRAM. */ 1814 /* */ 1815 /* Prepares the NVRAM interface for access and reads the requested data */ 1816 /* into the supplied buffer. */ 1817 /* */ 1818 /* Returns: */ 1819 /* 0 on success and the data read, positive value on failure. */ 1820 /****************************************************************************/ 1821 int 1822 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1823 int buf_size) 1824 { 1825 int rc = 0; 1826 uint32_t cmd_flags, offset32, len32, extra; 1827 1828 if (buf_size == 0) 1829 return 0; 1830 1831 /* Request access to the flash interface. */ 1832 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1833 return rc; 1834 1835 /* Enable access to flash interface */ 1836 bnx_enable_nvram_access(sc); 1837 1838 len32 = buf_size; 1839 offset32 = offset; 1840 extra = 0; 1841 1842 cmd_flags = 0; 1843 1844 if (offset32 & 3) { 1845 uint8_t buf[4]; 1846 uint32_t pre_len; 1847 1848 offset32 &= ~3; 1849 pre_len = 4 - (offset & 3); 1850 1851 if (pre_len >= len32) { 1852 pre_len = len32; 1853 cmd_flags = 1854 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1855 } else 1856 cmd_flags = BNX_NVM_COMMAND_FIRST; 1857 1858 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1859 1860 if (rc) 1861 return rc; 1862 1863 memcpy(ret_buf, buf + (offset & 3), pre_len); 1864 1865 offset32 += 4; 1866 ret_buf += pre_len; 1867 len32 -= pre_len; 1868 } 1869 1870 if (len32 & 3) { 1871 extra = 4 - (len32 & 3); 1872 len32 = (len32 + 4) & ~3; 1873 } 1874 1875 if (len32 == 4) { 1876 uint8_t buf[4]; 1877 1878 if (cmd_flags) 1879 cmd_flags = BNX_NVM_COMMAND_LAST; 1880 else 1881 cmd_flags = 1882 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1883 1884 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1885 1886 memcpy(ret_buf, buf, 4 - extra); 1887 } else if (len32 > 0) { 1888 uint8_t buf[4]; 1889 1890 /* Read the first word. */ 1891 if (cmd_flags) 1892 cmd_flags = 0; 1893 else 1894 cmd_flags = BNX_NVM_COMMAND_FIRST; 1895 1896 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1897 1898 /* Advance to the next dword. */ 1899 offset32 += 4; 1900 ret_buf += 4; 1901 len32 -= 4; 1902 1903 while (len32 > 4 && rc == 0) { 1904 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1905 1906 /* Advance to the next dword. */ 1907 offset32 += 4; 1908 ret_buf += 4; 1909 len32 -= 4; 1910 } 1911 1912 if (rc) 1913 return rc; 1914 1915 cmd_flags = BNX_NVM_COMMAND_LAST; 1916 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1917 1918 memcpy(ret_buf, buf, 4 - extra); 1919 } 1920 1921 /* Disable access to flash interface and release the lock. */ 1922 bnx_disable_nvram_access(sc); 1923 bnx_release_nvram_lock(sc); 1924 1925 return rc; 1926 } 1927 1928 #ifdef BNX_NVRAM_WRITE_SUPPORT 1929 /****************************************************************************/ 1930 /* Write an arbitrary range of data from NVRAM. */ 1931 /* */ 1932 /* Prepares the NVRAM interface for write access and writes the requested */ 1933 /* data from the supplied buffer. The caller is responsible for */ 1934 /* calculating any appropriate CRCs. */ 1935 /* */ 1936 /* Returns: */ 1937 /* 0 on success, positive value on failure. */ 1938 /****************************************************************************/ 1939 int 1940 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1941 int buf_size) 1942 { 1943 uint32_t written, offset32, len32; 1944 uint8_t *buf, start[4], end[4]; 1945 int rc = 0; 1946 int align_start, align_end; 1947 1948 buf = data_buf; 1949 offset32 = offset; 1950 len32 = buf_size; 1951 align_start = align_end = 0; 1952 1953 if ((align_start = (offset32 & 3))) { 1954 offset32 &= ~3; 1955 len32 += align_start; 1956 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1957 return rc; 1958 } 1959 1960 if (len32 & 3) { 1961 if ((len32 > 4) || !align_start) { 1962 align_end = 4 - (len32 & 3); 1963 len32 += align_end; 1964 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1965 end, 4))) 1966 return rc; 1967 } 1968 } 1969 1970 if (align_start || align_end) { 1971 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1972 if (buf == NULL) 1973 return ENOMEM; 1974 1975 if (align_start) 1976 memcpy(buf, start, 4); 1977 1978 if (align_end) 1979 memcpy(buf + len32 - 4, end, 4); 1980 1981 memcpy(buf + align_start, data_buf, buf_size); 1982 } 1983 1984 written = 0; 1985 while ((written < len32) && (rc == 0)) { 1986 uint32_t page_start, page_end, data_start, data_end; 1987 uint32_t addr, cmd_flags; 1988 int i; 1989 uint8_t flash_buffer[264]; 1990 1991 /* Find the page_start addr */ 1992 page_start = offset32 + written; 1993 page_start -= (page_start % sc->bnx_flash_info->page_size); 1994 /* Find the page_end addr */ 1995 page_end = page_start + sc->bnx_flash_info->page_size; 1996 /* Find the data_start addr */ 1997 data_start = (written == 0) ? offset32 : page_start; 1998 /* Find the data_end addr */ 1999 data_end = (page_end > offset32 + len32) ? 2000 (offset32 + len32) : page_end; 2001 2002 /* Request access to the flash interface. */ 2003 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 2004 goto nvram_write_end; 2005 2006 /* Enable access to flash interface */ 2007 bnx_enable_nvram_access(sc); 2008 2009 cmd_flags = BNX_NVM_COMMAND_FIRST; 2010 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2011 int j; 2012 2013 /* Read the whole page into the buffer 2014 * (non-buffer flash only) */ 2015 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 2016 if (j == (sc->bnx_flash_info->page_size - 4)) 2017 cmd_flags |= BNX_NVM_COMMAND_LAST; 2018 2019 rc = bnx_nvram_read_dword(sc, 2020 page_start + j, 2021 &flash_buffer[j], 2022 cmd_flags); 2023 2024 if (rc) 2025 goto nvram_write_end; 2026 2027 cmd_flags = 0; 2028 } 2029 } 2030 2031 /* Enable writes to flash interface (unlock write-protect) */ 2032 if ((rc = bnx_enable_nvram_write(sc)) != 0) 2033 goto nvram_write_end; 2034 2035 /* Erase the page */ 2036 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 2037 goto nvram_write_end; 2038 2039 /* Re-enable the write again for the actual write */ 2040 bnx_enable_nvram_write(sc); 2041 2042 /* Loop to write back the buffer data from page_start to 2043 * data_start */ 2044 i = 0; 2045 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2046 for (addr = page_start; addr < data_start; 2047 addr += 4, i += 4) { 2048 2049 rc = bnx_nvram_write_dword(sc, addr, 2050 &flash_buffer[i], cmd_flags); 2051 2052 if (rc != 0) 2053 goto nvram_write_end; 2054 2055 cmd_flags = 0; 2056 } 2057 } 2058 2059 /* Loop to write the new data from data_start to data_end */ 2060 for (addr = data_start; addr < data_end; addr += 4, i++) { 2061 if ((addr == page_end - 4) || 2062 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 2063 && (addr == data_end - 4))) { 2064 2065 cmd_flags |= BNX_NVM_COMMAND_LAST; 2066 } 2067 2068 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2069 2070 if (rc != 0) 2071 goto nvram_write_end; 2072 2073 cmd_flags = 0; 2074 buf += 4; 2075 } 2076 2077 /* Loop to write back the buffer data from data_end 2078 * to page_end */ 2079 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2080 for (addr = data_end; addr < page_end; 2081 addr += 4, i += 4) { 2082 2083 if (addr == page_end-4) 2084 cmd_flags = BNX_NVM_COMMAND_LAST; 2085 2086 rc = bnx_nvram_write_dword(sc, addr, 2087 &flash_buffer[i], cmd_flags); 2088 2089 if (rc != 0) 2090 goto nvram_write_end; 2091 2092 cmd_flags = 0; 2093 } 2094 } 2095 2096 /* Disable writes to flash interface (lock write-protect) */ 2097 bnx_disable_nvram_write(sc); 2098 2099 /* Disable access to flash interface */ 2100 bnx_disable_nvram_access(sc); 2101 bnx_release_nvram_lock(sc); 2102 2103 /* Increment written */ 2104 written += data_end - data_start; 2105 } 2106 2107 nvram_write_end: 2108 if (align_start || align_end) 2109 free(buf, M_DEVBUF); 2110 2111 return rc; 2112 } 2113 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2114 2115 /****************************************************************************/ 2116 /* Verifies that NVRAM is accessible and contains valid data. */ 2117 /* */ 2118 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2119 /* correct. */ 2120 /* */ 2121 /* Returns: */ 2122 /* 0 on success, positive value on failure. */ 2123 /****************************************************************************/ 2124 int 2125 bnx_nvram_test(struct bnx_softc *sc) 2126 { 2127 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2128 uint8_t *data = (uint8_t *) buf; 2129 int rc = 0; 2130 uint32_t magic, csum; 2131 2132 /* 2133 * Check that the device NVRAM is valid by reading 2134 * the magic value at offset 0. 2135 */ 2136 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2137 goto bnx_nvram_test_done; 2138 2139 magic = be32toh(buf[0]); 2140 if (magic != BNX_NVRAM_MAGIC) { 2141 rc = ENODEV; 2142 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2143 "Expected: 0x%08X, Found: 0x%08X\n", 2144 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2145 goto bnx_nvram_test_done; 2146 } 2147 2148 /* 2149 * Verify that the device NVRAM includes valid 2150 * configuration data. 2151 */ 2152 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2153 goto bnx_nvram_test_done; 2154 2155 csum = ether_crc32_le(data, 0x100); 2156 if (csum != BNX_CRC32_RESIDUAL) { 2157 rc = ENODEV; 2158 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2159 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2160 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2161 goto bnx_nvram_test_done; 2162 } 2163 2164 csum = ether_crc32_le(data + 0x100, 0x100); 2165 if (csum != BNX_CRC32_RESIDUAL) { 2166 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2167 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2168 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2169 rc = ENODEV; 2170 } 2171 2172 bnx_nvram_test_done: 2173 return rc; 2174 } 2175 2176 /****************************************************************************/ 2177 /* Identifies the current media type of the controller and sets the PHY */ 2178 /* address. */ 2179 /* */ 2180 /* Returns: */ 2181 /* Nothing. */ 2182 /****************************************************************************/ 2183 void 2184 bnx_get_media(struct bnx_softc *sc) 2185 { 2186 sc->bnx_phy_addr = 1; 2187 2188 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2189 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2190 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2191 uint32_t strap; 2192 2193 /* 2194 * The BCM5709S is software configurable 2195 * for Copper or SerDes operation. 2196 */ 2197 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2198 DBPRINT(sc, BNX_INFO_LOAD, 2199 "5709 bonded for copper.\n"); 2200 goto bnx_get_media_exit; 2201 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2202 DBPRINT(sc, BNX_INFO_LOAD, 2203 "5709 bonded for dual media.\n"); 2204 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2205 goto bnx_get_media_exit; 2206 } 2207 2208 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2209 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2210 else { 2211 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2212 >> 8; 2213 } 2214 2215 if (sc->bnx_pa.pa_function == 0) { 2216 switch (strap) { 2217 case 0x4: 2218 case 0x5: 2219 case 0x6: 2220 DBPRINT(sc, BNX_INFO_LOAD, 2221 "BCM5709 s/w configured for SerDes.\n"); 2222 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2223 break; 2224 default: 2225 DBPRINT(sc, BNX_INFO_LOAD, 2226 "BCM5709 s/w configured for Copper.\n"); 2227 } 2228 } else { 2229 switch (strap) { 2230 case 0x1: 2231 case 0x2: 2232 case 0x4: 2233 DBPRINT(sc, BNX_INFO_LOAD, 2234 "BCM5709 s/w configured for SerDes.\n"); 2235 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2236 break; 2237 default: 2238 DBPRINT(sc, BNX_INFO_LOAD, 2239 "BCM5709 s/w configured for Copper.\n"); 2240 } 2241 } 2242 2243 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2244 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2245 2246 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2247 uint32_t val; 2248 2249 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2250 2251 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2252 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2253 2254 /* 2255 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2256 * separate PHY for SerDes. 2257 */ 2258 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2259 sc->bnx_phy_addr = 2; 2260 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2261 BNX_SHARED_HW_CFG_CONFIG); 2262 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2263 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2264 DBPRINT(sc, BNX_INFO_LOAD, 2265 "Found 2.5Gb capable adapter\n"); 2266 } 2267 } 2268 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2269 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2270 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2271 2272 bnx_get_media_exit: 2273 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2274 "Using PHY address %d.\n", sc->bnx_phy_addr); 2275 } 2276 2277 /****************************************************************************/ 2278 /* Performs PHY initialization required before MII drivers access the */ 2279 /* device. */ 2280 /* */ 2281 /* Returns: */ 2282 /* Nothing. */ 2283 /****************************************************************************/ 2284 void 2285 bnx_init_media(struct bnx_softc *sc) 2286 { 2287 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2288 /* 2289 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2290 * IEEE Clause 22 method. Otherwise we have no way to attach 2291 * the PHY to the mii(4) layer. PHY specific configuration 2292 * is done by the mii(4) layer. 2293 */ 2294 2295 /* Select auto-negotiation MMD of the PHY. */ 2296 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2297 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2298 2299 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2300 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2301 2302 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2303 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2304 } 2305 } 2306 2307 /****************************************************************************/ 2308 /* Free any DMA memory owned by the driver. */ 2309 /* */ 2310 /* Scans through each data structre that requires DMA memory and frees */ 2311 /* the memory if allocated. */ 2312 /* */ 2313 /* Returns: */ 2314 /* Nothing. */ 2315 /****************************************************************************/ 2316 void 2317 bnx_dma_free(struct bnx_softc *sc) 2318 { 2319 int i; 2320 2321 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2322 2323 /* Destroy the status block. */ 2324 if (sc->status_block != NULL && sc->status_map != NULL) { 2325 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2326 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2327 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2328 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2329 BNX_STATUS_BLK_SZ); 2330 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2331 sc->status_rseg); 2332 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2333 sc->status_block = NULL; 2334 sc->status_map = NULL; 2335 } 2336 2337 /* Destroy the statistics block. */ 2338 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2339 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2340 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2341 BNX_STATS_BLK_SZ); 2342 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2343 sc->stats_rseg); 2344 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2345 sc->stats_block = NULL; 2346 sc->stats_map = NULL; 2347 } 2348 2349 /* Free, unmap and destroy all context memory pages. */ 2350 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2351 for (i = 0; i < sc->ctx_pages; i++) { 2352 if (sc->ctx_block[i] != NULL) { 2353 bus_dmamap_unload(sc->bnx_dmatag, 2354 sc->ctx_map[i]); 2355 bus_dmamem_unmap(sc->bnx_dmatag, 2356 (void *)sc->ctx_block[i], 2357 BCM_PAGE_SIZE); 2358 bus_dmamem_free(sc->bnx_dmatag, 2359 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2360 bus_dmamap_destroy(sc->bnx_dmatag, 2361 sc->ctx_map[i]); 2362 sc->ctx_block[i] = NULL; 2363 } 2364 } 2365 } 2366 2367 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2368 for (i = 0; i < TX_PAGES; i++ ) { 2369 if (sc->tx_bd_chain[i] != NULL && 2370 sc->tx_bd_chain_map[i] != NULL) { 2371 bus_dmamap_unload(sc->bnx_dmatag, 2372 sc->tx_bd_chain_map[i]); 2373 bus_dmamem_unmap(sc->bnx_dmatag, 2374 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2375 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2376 sc->tx_bd_chain_rseg[i]); 2377 bus_dmamap_destroy(sc->bnx_dmatag, 2378 sc->tx_bd_chain_map[i]); 2379 sc->tx_bd_chain[i] = NULL; 2380 sc->tx_bd_chain_map[i] = NULL; 2381 } 2382 } 2383 2384 /* Destroy the TX dmamaps. */ 2385 struct bnx_pkt *pkt; 2386 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 2387 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 2388 sc->tx_pkt_count--; 2389 2390 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 2391 pool_put(bnx_tx_pool, pkt); 2392 } 2393 2394 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2395 for (i = 0; i < RX_PAGES; i++ ) { 2396 if (sc->rx_bd_chain[i] != NULL && 2397 sc->rx_bd_chain_map[i] != NULL) { 2398 bus_dmamap_unload(sc->bnx_dmatag, 2399 sc->rx_bd_chain_map[i]); 2400 bus_dmamem_unmap(sc->bnx_dmatag, 2401 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2402 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2403 sc->rx_bd_chain_rseg[i]); 2404 2405 bus_dmamap_destroy(sc->bnx_dmatag, 2406 sc->rx_bd_chain_map[i]); 2407 sc->rx_bd_chain[i] = NULL; 2408 sc->rx_bd_chain_map[i] = NULL; 2409 } 2410 } 2411 2412 /* Unload and destroy the RX mbuf maps. */ 2413 for (i = 0; i < TOTAL_RX_BD; i++) { 2414 if (sc->rx_mbuf_map[i] != NULL) { 2415 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2416 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2417 } 2418 } 2419 2420 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2421 } 2422 2423 /****************************************************************************/ 2424 /* Allocate any DMA memory needed by the driver. */ 2425 /* */ 2426 /* Allocates DMA memory needed for the various global structures needed by */ 2427 /* hardware. */ 2428 /* */ 2429 /* Returns: */ 2430 /* 0 for success, positive value for failure. */ 2431 /****************************************************************************/ 2432 int 2433 bnx_dma_alloc(struct bnx_softc *sc) 2434 { 2435 int i, rc = 0; 2436 2437 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2438 2439 /* 2440 * Allocate DMA memory for the status block, map the memory into DMA 2441 * space, and fetch the physical address of the block. 2442 */ 2443 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2444 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2445 aprint_error_dev(sc->bnx_dev, 2446 "Could not create status block DMA map!\n"); 2447 rc = ENOMEM; 2448 goto bnx_dma_alloc_exit; 2449 } 2450 2451 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2452 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2453 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2454 aprint_error_dev(sc->bnx_dev, 2455 "Could not allocate status block DMA memory!\n"); 2456 rc = ENOMEM; 2457 goto bnx_dma_alloc_exit; 2458 } 2459 2460 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2461 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2462 aprint_error_dev(sc->bnx_dev, 2463 "Could not map status block DMA memory!\n"); 2464 rc = ENOMEM; 2465 goto bnx_dma_alloc_exit; 2466 } 2467 2468 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2469 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2470 aprint_error_dev(sc->bnx_dev, 2471 "Could not load status block DMA memory!\n"); 2472 rc = ENOMEM; 2473 goto bnx_dma_alloc_exit; 2474 } 2475 2476 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2477 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2478 2479 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2480 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2481 2482 /* DRC - Fix for 64 bit addresses. */ 2483 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2484 (uint32_t) sc->status_block_paddr); 2485 2486 /* BCM5709 uses host memory as cache for context memory. */ 2487 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2488 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2489 if (sc->ctx_pages == 0) 2490 sc->ctx_pages = 1; 2491 if (sc->ctx_pages > 4) /* XXX */ 2492 sc->ctx_pages = 4; 2493 2494 DBRUNIF((sc->ctx_pages > 512), 2495 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2496 __FILE__, __LINE__, sc->ctx_pages)); 2497 2498 2499 for (i = 0; i < sc->ctx_pages; i++) { 2500 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2501 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2502 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2503 &sc->ctx_map[i]) != 0) { 2504 rc = ENOMEM; 2505 goto bnx_dma_alloc_exit; 2506 } 2507 2508 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2509 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2510 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2511 rc = ENOMEM; 2512 goto bnx_dma_alloc_exit; 2513 } 2514 2515 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2516 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2517 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2518 rc = ENOMEM; 2519 goto bnx_dma_alloc_exit; 2520 } 2521 2522 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2523 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2524 BUS_DMA_NOWAIT) != 0) { 2525 rc = ENOMEM; 2526 goto bnx_dma_alloc_exit; 2527 } 2528 2529 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2530 } 2531 } 2532 2533 /* 2534 * Allocate DMA memory for the statistics block, map the memory into 2535 * DMA space, and fetch the physical address of the block. 2536 */ 2537 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2538 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2539 aprint_error_dev(sc->bnx_dev, 2540 "Could not create stats block DMA map!\n"); 2541 rc = ENOMEM; 2542 goto bnx_dma_alloc_exit; 2543 } 2544 2545 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2546 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2547 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2548 aprint_error_dev(sc->bnx_dev, 2549 "Could not allocate stats block DMA memory!\n"); 2550 rc = ENOMEM; 2551 goto bnx_dma_alloc_exit; 2552 } 2553 2554 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2555 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2556 aprint_error_dev(sc->bnx_dev, 2557 "Could not map stats block DMA memory!\n"); 2558 rc = ENOMEM; 2559 goto bnx_dma_alloc_exit; 2560 } 2561 2562 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2563 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2564 aprint_error_dev(sc->bnx_dev, 2565 "Could not load status block DMA memory!\n"); 2566 rc = ENOMEM; 2567 goto bnx_dma_alloc_exit; 2568 } 2569 2570 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2571 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2572 2573 /* DRC - Fix for 64 bit address. */ 2574 DBPRINT(sc, BNX_INFO, "stats_block_paddr = 0x%08X\n", 2575 (uint32_t) sc->stats_block_paddr); 2576 2577 /* 2578 * Allocate DMA memory for the TX buffer descriptor chain, 2579 * and fetch the physical address of the block. 2580 */ 2581 for (i = 0; i < TX_PAGES; i++) { 2582 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2583 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2584 &sc->tx_bd_chain_map[i])) { 2585 aprint_error_dev(sc->bnx_dev, 2586 "Could not create Tx desc %d DMA map!\n", i); 2587 rc = ENOMEM; 2588 goto bnx_dma_alloc_exit; 2589 } 2590 2591 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2592 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2593 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2594 aprint_error_dev(sc->bnx_dev, 2595 "Could not allocate TX desc %d DMA memory!\n", 2596 i); 2597 rc = ENOMEM; 2598 goto bnx_dma_alloc_exit; 2599 } 2600 2601 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2602 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2603 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2604 aprint_error_dev(sc->bnx_dev, 2605 "Could not map TX desc %d DMA memory!\n", i); 2606 rc = ENOMEM; 2607 goto bnx_dma_alloc_exit; 2608 } 2609 2610 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2611 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2612 BUS_DMA_NOWAIT)) { 2613 aprint_error_dev(sc->bnx_dev, 2614 "Could not load TX desc %d DMA memory!\n", i); 2615 rc = ENOMEM; 2616 goto bnx_dma_alloc_exit; 2617 } 2618 2619 sc->tx_bd_chain_paddr[i] = 2620 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2621 2622 /* DRC - Fix for 64 bit systems. */ 2623 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2624 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2625 } 2626 2627 /* 2628 * Create lists to hold TX mbufs. 2629 */ 2630 TAILQ_INIT(&sc->tx_free_pkts); 2631 TAILQ_INIT(&sc->tx_used_pkts); 2632 sc->tx_pkt_count = 0; 2633 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2634 2635 /* 2636 * Allocate DMA memory for the Rx buffer descriptor chain, 2637 * and fetch the physical address of the block. 2638 */ 2639 for (i = 0; i < RX_PAGES; i++) { 2640 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2641 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2642 &sc->rx_bd_chain_map[i])) { 2643 aprint_error_dev(sc->bnx_dev, 2644 "Could not create Rx desc %d DMA map!\n", i); 2645 rc = ENOMEM; 2646 goto bnx_dma_alloc_exit; 2647 } 2648 2649 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2650 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2651 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2652 aprint_error_dev(sc->bnx_dev, 2653 "Could not allocate Rx desc %d DMA memory!\n", i); 2654 rc = ENOMEM; 2655 goto bnx_dma_alloc_exit; 2656 } 2657 2658 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2659 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2660 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2661 aprint_error_dev(sc->bnx_dev, 2662 "Could not map Rx desc %d DMA memory!\n", i); 2663 rc = ENOMEM; 2664 goto bnx_dma_alloc_exit; 2665 } 2666 2667 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2668 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2669 BUS_DMA_NOWAIT)) { 2670 aprint_error_dev(sc->bnx_dev, 2671 "Could not load Rx desc %d DMA memory!\n", i); 2672 rc = ENOMEM; 2673 goto bnx_dma_alloc_exit; 2674 } 2675 2676 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2677 sc->rx_bd_chain_paddr[i] = 2678 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2679 2680 /* DRC - Fix for 64 bit systems. */ 2681 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2682 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2683 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2684 0, BNX_RX_CHAIN_PAGE_SZ, 2685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2686 } 2687 2688 /* 2689 * Create DMA maps for the Rx buffer mbufs. 2690 */ 2691 for (i = 0; i < TOTAL_RX_BD; i++) { 2692 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2693 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2694 &sc->rx_mbuf_map[i])) { 2695 aprint_error_dev(sc->bnx_dev, 2696 "Could not create Rx mbuf %d DMA map!\n", i); 2697 rc = ENOMEM; 2698 goto bnx_dma_alloc_exit; 2699 } 2700 } 2701 2702 bnx_dma_alloc_exit: 2703 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2704 2705 return rc; 2706 } 2707 2708 /****************************************************************************/ 2709 /* Release all resources used by the driver. */ 2710 /* */ 2711 /* Releases all resources acquired by the driver including interrupts, */ 2712 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2713 /* */ 2714 /* Returns: */ 2715 /* Nothing. */ 2716 /****************************************************************************/ 2717 void 2718 bnx_release_resources(struct bnx_softc *sc) 2719 { 2720 struct pci_attach_args *pa = &(sc->bnx_pa); 2721 2722 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2723 2724 bnx_dma_free(sc); 2725 2726 if (sc->bnx_intrhand != NULL) 2727 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2728 2729 if (sc->bnx_ih != NULL) 2730 pci_intr_release(pa->pa_pc, sc->bnx_ih, 1); 2731 2732 if (sc->bnx_size) 2733 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2734 2735 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2736 } 2737 2738 /****************************************************************************/ 2739 /* Firmware synchronization. */ 2740 /* */ 2741 /* Before performing certain events such as a chip reset, synchronize with */ 2742 /* the firmware first. */ 2743 /* */ 2744 /* Returns: */ 2745 /* 0 for success, positive value for failure. */ 2746 /****************************************************************************/ 2747 int 2748 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2749 { 2750 int i, rc = 0; 2751 uint32_t val; 2752 2753 /* Don't waste any time if we've timed out before. */ 2754 if (sc->bnx_fw_timed_out) { 2755 rc = EBUSY; 2756 goto bnx_fw_sync_exit; 2757 } 2758 2759 /* Increment the message sequence number. */ 2760 sc->bnx_fw_wr_seq++; 2761 msg_data |= sc->bnx_fw_wr_seq; 2762 2763 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2764 msg_data); 2765 2766 /* Send the message to the bootcode driver mailbox. */ 2767 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2768 2769 /* Wait for the bootcode to acknowledge the message. */ 2770 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2771 /* Check for a response in the bootcode firmware mailbox. */ 2772 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2773 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2774 break; 2775 DELAY(1000); 2776 } 2777 2778 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2779 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2780 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2781 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2782 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2783 2784 msg_data &= ~BNX_DRV_MSG_CODE; 2785 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2786 2787 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2788 2789 sc->bnx_fw_timed_out = 1; 2790 rc = EBUSY; 2791 } 2792 2793 bnx_fw_sync_exit: 2794 return rc; 2795 } 2796 2797 /****************************************************************************/ 2798 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2799 /* */ 2800 /* Returns: */ 2801 /* Nothing. */ 2802 /****************************************************************************/ 2803 void 2804 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2805 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2806 { 2807 int i; 2808 uint32_t val; 2809 2810 /* Set the page size used by RV2P. */ 2811 if (rv2p_proc == RV2P_PROC2) { 2812 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2813 USABLE_RX_BD_PER_PAGE); 2814 } 2815 2816 for (i = 0; i < rv2p_code_len; i += 8) { 2817 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2818 rv2p_code++; 2819 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2820 rv2p_code++; 2821 2822 if (rv2p_proc == RV2P_PROC1) { 2823 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2824 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2825 } else { 2826 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2827 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2828 } 2829 } 2830 2831 /* Reset the processor, un-stall is done later. */ 2832 if (rv2p_proc == RV2P_PROC1) 2833 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2834 else 2835 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2836 } 2837 2838 /****************************************************************************/ 2839 /* Load RISC processor firmware. */ 2840 /* */ 2841 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2842 /* associated with a particular processor. */ 2843 /* */ 2844 /* Returns: */ 2845 /* Nothing. */ 2846 /****************************************************************************/ 2847 void 2848 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2849 struct fw_info *fw) 2850 { 2851 uint32_t offset; 2852 uint32_t val; 2853 2854 /* Halt the CPU. */ 2855 val = REG_RD_IND(sc, cpu_reg->mode); 2856 val |= cpu_reg->mode_value_halt; 2857 REG_WR_IND(sc, cpu_reg->mode, val); 2858 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2859 2860 /* Load the Text area. */ 2861 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2862 if (fw->text) { 2863 int j; 2864 2865 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2866 REG_WR_IND(sc, offset, fw->text[j]); 2867 } 2868 2869 /* Load the Data area. */ 2870 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2871 if (fw->data) { 2872 int j; 2873 2874 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2875 REG_WR_IND(sc, offset, fw->data[j]); 2876 } 2877 2878 /* Load the SBSS area. */ 2879 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2880 if (fw->sbss) { 2881 int j; 2882 2883 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2884 REG_WR_IND(sc, offset, fw->sbss[j]); 2885 } 2886 2887 /* Load the BSS area. */ 2888 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2889 if (fw->bss) { 2890 int j; 2891 2892 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2893 REG_WR_IND(sc, offset, fw->bss[j]); 2894 } 2895 2896 /* Load the Read-Only area. */ 2897 offset = cpu_reg->spad_base + 2898 (fw->rodata_addr - cpu_reg->mips_view_base); 2899 if (fw->rodata) { 2900 int j; 2901 2902 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2903 REG_WR_IND(sc, offset, fw->rodata[j]); 2904 } 2905 2906 /* Clear the pre-fetch instruction. */ 2907 REG_WR_IND(sc, cpu_reg->inst, 0); 2908 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2909 2910 /* Start the CPU. */ 2911 val = REG_RD_IND(sc, cpu_reg->mode); 2912 val &= ~cpu_reg->mode_value_halt; 2913 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2914 REG_WR_IND(sc, cpu_reg->mode, val); 2915 } 2916 2917 /****************************************************************************/ 2918 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2919 /* */ 2920 /* Loads the firmware for each CPU and starts the CPU. */ 2921 /* */ 2922 /* Returns: */ 2923 /* Nothing. */ 2924 /****************************************************************************/ 2925 void 2926 bnx_init_cpus(struct bnx_softc *sc) 2927 { 2928 struct cpu_reg cpu_reg; 2929 struct fw_info fw; 2930 2931 switch (BNX_CHIP_NUM(sc)) { 2932 case BNX_CHIP_NUM_5709: 2933 /* Initialize the RV2P processor. */ 2934 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2935 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2936 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2937 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2938 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2939 } else { 2940 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2941 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2942 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2943 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2944 } 2945 2946 /* Initialize the RX Processor. */ 2947 cpu_reg.mode = BNX_RXP_CPU_MODE; 2948 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2949 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2950 cpu_reg.state = BNX_RXP_CPU_STATE; 2951 cpu_reg.state_value_clear = 0xffffff; 2952 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2953 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2954 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2955 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2956 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2957 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2958 cpu_reg.mips_view_base = 0x8000000; 2959 2960 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2961 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2962 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2963 fw.start_addr = bnx_RXP_b09FwStartAddr; 2964 2965 fw.text_addr = bnx_RXP_b09FwTextAddr; 2966 fw.text_len = bnx_RXP_b09FwTextLen; 2967 fw.text_index = 0; 2968 fw.text = bnx_RXP_b09FwText; 2969 2970 fw.data_addr = bnx_RXP_b09FwDataAddr; 2971 fw.data_len = bnx_RXP_b09FwDataLen; 2972 fw.data_index = 0; 2973 fw.data = bnx_RXP_b09FwData; 2974 2975 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2976 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2977 fw.sbss_index = 0; 2978 fw.sbss = bnx_RXP_b09FwSbss; 2979 2980 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2981 fw.bss_len = bnx_RXP_b09FwBssLen; 2982 fw.bss_index = 0; 2983 fw.bss = bnx_RXP_b09FwBss; 2984 2985 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2986 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2987 fw.rodata_index = 0; 2988 fw.rodata = bnx_RXP_b09FwRodata; 2989 2990 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2991 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2992 2993 /* Initialize the TX Processor. */ 2994 cpu_reg.mode = BNX_TXP_CPU_MODE; 2995 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2996 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2997 cpu_reg.state = BNX_TXP_CPU_STATE; 2998 cpu_reg.state_value_clear = 0xffffff; 2999 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3000 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3001 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3002 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3003 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3004 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3005 cpu_reg.mips_view_base = 0x8000000; 3006 3007 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 3008 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 3009 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 3010 fw.start_addr = bnx_TXP_b09FwStartAddr; 3011 3012 fw.text_addr = bnx_TXP_b09FwTextAddr; 3013 fw.text_len = bnx_TXP_b09FwTextLen; 3014 fw.text_index = 0; 3015 fw.text = bnx_TXP_b09FwText; 3016 3017 fw.data_addr = bnx_TXP_b09FwDataAddr; 3018 fw.data_len = bnx_TXP_b09FwDataLen; 3019 fw.data_index = 0; 3020 fw.data = bnx_TXP_b09FwData; 3021 3022 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 3023 fw.sbss_len = bnx_TXP_b09FwSbssLen; 3024 fw.sbss_index = 0; 3025 fw.sbss = bnx_TXP_b09FwSbss; 3026 3027 fw.bss_addr = bnx_TXP_b09FwBssAddr; 3028 fw.bss_len = bnx_TXP_b09FwBssLen; 3029 fw.bss_index = 0; 3030 fw.bss = bnx_TXP_b09FwBss; 3031 3032 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 3033 fw.rodata_len = bnx_TXP_b09FwRodataLen; 3034 fw.rodata_index = 0; 3035 fw.rodata = bnx_TXP_b09FwRodata; 3036 3037 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3038 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3039 3040 /* Initialize the TX Patch-up Processor. */ 3041 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3042 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3043 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3044 cpu_reg.state = BNX_TPAT_CPU_STATE; 3045 cpu_reg.state_value_clear = 0xffffff; 3046 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3047 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3048 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3049 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3050 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3051 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3052 cpu_reg.mips_view_base = 0x8000000; 3053 3054 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 3055 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 3056 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 3057 fw.start_addr = bnx_TPAT_b09FwStartAddr; 3058 3059 fw.text_addr = bnx_TPAT_b09FwTextAddr; 3060 fw.text_len = bnx_TPAT_b09FwTextLen; 3061 fw.text_index = 0; 3062 fw.text = bnx_TPAT_b09FwText; 3063 3064 fw.data_addr = bnx_TPAT_b09FwDataAddr; 3065 fw.data_len = bnx_TPAT_b09FwDataLen; 3066 fw.data_index = 0; 3067 fw.data = bnx_TPAT_b09FwData; 3068 3069 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 3070 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 3071 fw.sbss_index = 0; 3072 fw.sbss = bnx_TPAT_b09FwSbss; 3073 3074 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 3075 fw.bss_len = bnx_TPAT_b09FwBssLen; 3076 fw.bss_index = 0; 3077 fw.bss = bnx_TPAT_b09FwBss; 3078 3079 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3080 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3081 fw.rodata_index = 0; 3082 fw.rodata = bnx_TPAT_b09FwRodata; 3083 3084 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3085 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3086 3087 /* Initialize the Completion Processor. */ 3088 cpu_reg.mode = BNX_COM_CPU_MODE; 3089 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3090 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3091 cpu_reg.state = BNX_COM_CPU_STATE; 3092 cpu_reg.state_value_clear = 0xffffff; 3093 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3094 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3095 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3096 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3097 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3098 cpu_reg.spad_base = BNX_COM_SCRATCH; 3099 cpu_reg.mips_view_base = 0x8000000; 3100 3101 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3102 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3103 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3104 fw.start_addr = bnx_COM_b09FwStartAddr; 3105 3106 fw.text_addr = bnx_COM_b09FwTextAddr; 3107 fw.text_len = bnx_COM_b09FwTextLen; 3108 fw.text_index = 0; 3109 fw.text = bnx_COM_b09FwText; 3110 3111 fw.data_addr = bnx_COM_b09FwDataAddr; 3112 fw.data_len = bnx_COM_b09FwDataLen; 3113 fw.data_index = 0; 3114 fw.data = bnx_COM_b09FwData; 3115 3116 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3117 fw.sbss_len = bnx_COM_b09FwSbssLen; 3118 fw.sbss_index = 0; 3119 fw.sbss = bnx_COM_b09FwSbss; 3120 3121 fw.bss_addr = bnx_COM_b09FwBssAddr; 3122 fw.bss_len = bnx_COM_b09FwBssLen; 3123 fw.bss_index = 0; 3124 fw.bss = bnx_COM_b09FwBss; 3125 3126 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3127 fw.rodata_len = bnx_COM_b09FwRodataLen; 3128 fw.rodata_index = 0; 3129 fw.rodata = bnx_COM_b09FwRodata; 3130 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3131 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3132 break; 3133 default: 3134 /* Initialize the RV2P processor. */ 3135 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3136 RV2P_PROC1); 3137 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3138 RV2P_PROC2); 3139 3140 /* Initialize the RX Processor. */ 3141 cpu_reg.mode = BNX_RXP_CPU_MODE; 3142 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3143 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3144 cpu_reg.state = BNX_RXP_CPU_STATE; 3145 cpu_reg.state_value_clear = 0xffffff; 3146 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3147 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3148 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3149 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3150 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3151 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3152 cpu_reg.mips_view_base = 0x8000000; 3153 3154 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3155 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3156 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3157 fw.start_addr = bnx_RXP_b06FwStartAddr; 3158 3159 fw.text_addr = bnx_RXP_b06FwTextAddr; 3160 fw.text_len = bnx_RXP_b06FwTextLen; 3161 fw.text_index = 0; 3162 fw.text = bnx_RXP_b06FwText; 3163 3164 fw.data_addr = bnx_RXP_b06FwDataAddr; 3165 fw.data_len = bnx_RXP_b06FwDataLen; 3166 fw.data_index = 0; 3167 fw.data = bnx_RXP_b06FwData; 3168 3169 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3170 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3171 fw.sbss_index = 0; 3172 fw.sbss = bnx_RXP_b06FwSbss; 3173 3174 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3175 fw.bss_len = bnx_RXP_b06FwBssLen; 3176 fw.bss_index = 0; 3177 fw.bss = bnx_RXP_b06FwBss; 3178 3179 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3180 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3181 fw.rodata_index = 0; 3182 fw.rodata = bnx_RXP_b06FwRodata; 3183 3184 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3185 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3186 3187 /* Initialize the TX Processor. */ 3188 cpu_reg.mode = BNX_TXP_CPU_MODE; 3189 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3190 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3191 cpu_reg.state = BNX_TXP_CPU_STATE; 3192 cpu_reg.state_value_clear = 0xffffff; 3193 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3194 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3195 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3196 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3197 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3198 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3199 cpu_reg.mips_view_base = 0x8000000; 3200 3201 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3202 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3203 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3204 fw.start_addr = bnx_TXP_b06FwStartAddr; 3205 3206 fw.text_addr = bnx_TXP_b06FwTextAddr; 3207 fw.text_len = bnx_TXP_b06FwTextLen; 3208 fw.text_index = 0; 3209 fw.text = bnx_TXP_b06FwText; 3210 3211 fw.data_addr = bnx_TXP_b06FwDataAddr; 3212 fw.data_len = bnx_TXP_b06FwDataLen; 3213 fw.data_index = 0; 3214 fw.data = bnx_TXP_b06FwData; 3215 3216 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3217 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3218 fw.sbss_index = 0; 3219 fw.sbss = bnx_TXP_b06FwSbss; 3220 3221 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3222 fw.bss_len = bnx_TXP_b06FwBssLen; 3223 fw.bss_index = 0; 3224 fw.bss = bnx_TXP_b06FwBss; 3225 3226 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3227 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3228 fw.rodata_index = 0; 3229 fw.rodata = bnx_TXP_b06FwRodata; 3230 3231 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3232 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3233 3234 /* Initialize the TX Patch-up Processor. */ 3235 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3236 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3237 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3238 cpu_reg.state = BNX_TPAT_CPU_STATE; 3239 cpu_reg.state_value_clear = 0xffffff; 3240 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3241 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3242 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3243 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3244 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3245 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3246 cpu_reg.mips_view_base = 0x8000000; 3247 3248 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3249 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3250 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3251 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3252 3253 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3254 fw.text_len = bnx_TPAT_b06FwTextLen; 3255 fw.text_index = 0; 3256 fw.text = bnx_TPAT_b06FwText; 3257 3258 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3259 fw.data_len = bnx_TPAT_b06FwDataLen; 3260 fw.data_index = 0; 3261 fw.data = bnx_TPAT_b06FwData; 3262 3263 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3264 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3265 fw.sbss_index = 0; 3266 fw.sbss = bnx_TPAT_b06FwSbss; 3267 3268 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3269 fw.bss_len = bnx_TPAT_b06FwBssLen; 3270 fw.bss_index = 0; 3271 fw.bss = bnx_TPAT_b06FwBss; 3272 3273 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3274 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3275 fw.rodata_index = 0; 3276 fw.rodata = bnx_TPAT_b06FwRodata; 3277 3278 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3279 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3280 3281 /* Initialize the Completion Processor. */ 3282 cpu_reg.mode = BNX_COM_CPU_MODE; 3283 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3284 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3285 cpu_reg.state = BNX_COM_CPU_STATE; 3286 cpu_reg.state_value_clear = 0xffffff; 3287 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3288 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3289 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3290 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3291 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3292 cpu_reg.spad_base = BNX_COM_SCRATCH; 3293 cpu_reg.mips_view_base = 0x8000000; 3294 3295 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3296 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3297 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3298 fw.start_addr = bnx_COM_b06FwStartAddr; 3299 3300 fw.text_addr = bnx_COM_b06FwTextAddr; 3301 fw.text_len = bnx_COM_b06FwTextLen; 3302 fw.text_index = 0; 3303 fw.text = bnx_COM_b06FwText; 3304 3305 fw.data_addr = bnx_COM_b06FwDataAddr; 3306 fw.data_len = bnx_COM_b06FwDataLen; 3307 fw.data_index = 0; 3308 fw.data = bnx_COM_b06FwData; 3309 3310 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3311 fw.sbss_len = bnx_COM_b06FwSbssLen; 3312 fw.sbss_index = 0; 3313 fw.sbss = bnx_COM_b06FwSbss; 3314 3315 fw.bss_addr = bnx_COM_b06FwBssAddr; 3316 fw.bss_len = bnx_COM_b06FwBssLen; 3317 fw.bss_index = 0; 3318 fw.bss = bnx_COM_b06FwBss; 3319 3320 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3321 fw.rodata_len = bnx_COM_b06FwRodataLen; 3322 fw.rodata_index = 0; 3323 fw.rodata = bnx_COM_b06FwRodata; 3324 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3325 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3326 break; 3327 } 3328 } 3329 3330 /****************************************************************************/ 3331 /* Initialize context memory. */ 3332 /* */ 3333 /* Clears the memory associated with each Context ID (CID). */ 3334 /* */ 3335 /* Returns: */ 3336 /* Nothing. */ 3337 /****************************************************************************/ 3338 void 3339 bnx_init_context(struct bnx_softc *sc) 3340 { 3341 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3342 /* DRC: Replace this constant value with a #define. */ 3343 int i, retry_cnt = 10; 3344 uint32_t val; 3345 3346 /* 3347 * BCM5709 context memory may be cached 3348 * in host memory so prepare the host memory 3349 * for access. 3350 */ 3351 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3352 | (1 << 12); 3353 val |= (BCM_PAGE_BITS - 8) << 16; 3354 REG_WR(sc, BNX_CTX_COMMAND, val); 3355 3356 /* Wait for mem init command to complete. */ 3357 for (i = 0; i < retry_cnt; i++) { 3358 val = REG_RD(sc, BNX_CTX_COMMAND); 3359 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3360 break; 3361 DELAY(2); 3362 } 3363 3364 /* ToDo: Consider returning an error here. */ 3365 3366 for (i = 0; i < sc->ctx_pages; i++) { 3367 int j; 3368 3369 /* Set the physaddr of the context memory cache. */ 3370 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3371 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3372 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3373 val = (uint32_t) 3374 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3375 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3376 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3377 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3378 3379 /* Verify that the context memory write was successful. */ 3380 for (j = 0; j < retry_cnt; j++) { 3381 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3382 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3383 break; 3384 DELAY(5); 3385 } 3386 3387 /* ToDo: Consider returning an error here. */ 3388 } 3389 } else { 3390 uint32_t vcid_addr, offset; 3391 3392 /* 3393 * For the 5706/5708, context memory is local to the 3394 * controller, so initialize the controller context memory. 3395 */ 3396 3397 vcid_addr = GET_CID_ADDR(96); 3398 while (vcid_addr) { 3399 3400 vcid_addr -= BNX_PHY_CTX_SIZE; 3401 3402 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3403 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3404 3405 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3406 offset += 4) 3407 CTX_WR(sc, 0x00, offset, 0); 3408 3409 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3410 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3411 } 3412 } 3413 } 3414 3415 /****************************************************************************/ 3416 /* Fetch the permanent MAC address of the controller. */ 3417 /* */ 3418 /* Returns: */ 3419 /* Nothing. */ 3420 /****************************************************************************/ 3421 void 3422 bnx_get_mac_addr(struct bnx_softc *sc) 3423 { 3424 uint32_t mac_lo = 0, mac_hi = 0; 3425 3426 /* 3427 * The NetXtreme II bootcode populates various NIC 3428 * power-on and runtime configuration items in a 3429 * shared memory area. The factory configured MAC 3430 * address is available from both NVRAM and the 3431 * shared memory area so we'll read the value from 3432 * shared memory for speed. 3433 */ 3434 3435 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3436 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3437 3438 if ((mac_lo == 0) && (mac_hi == 0)) { 3439 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3440 __FILE__, __LINE__); 3441 } else { 3442 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3443 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3444 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3445 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3446 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3447 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3448 } 3449 3450 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3451 "%s\n", ether_sprintf(sc->eaddr)); 3452 } 3453 3454 /****************************************************************************/ 3455 /* Program the MAC address. */ 3456 /* */ 3457 /* Returns: */ 3458 /* Nothing. */ 3459 /****************************************************************************/ 3460 void 3461 bnx_set_mac_addr(struct bnx_softc *sc) 3462 { 3463 uint32_t val; 3464 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3465 3466 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3467 "%s\n", ether_sprintf(sc->eaddr)); 3468 3469 val = (mac_addr[0] << 8) | mac_addr[1]; 3470 3471 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3472 3473 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3474 (mac_addr[4] << 8) | mac_addr[5]; 3475 3476 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3477 } 3478 3479 /****************************************************************************/ 3480 /* Stop the controller. */ 3481 /* */ 3482 /* Returns: */ 3483 /* Nothing. */ 3484 /****************************************************************************/ 3485 void 3486 bnx_stop(struct ifnet *ifp, int disable) 3487 { 3488 struct bnx_softc *sc = ifp->if_softc; 3489 3490 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3491 3492 if (disable) { 3493 sc->bnx_detaching = 1; 3494 callout_halt(&sc->bnx_timeout, NULL); 3495 } else 3496 callout_stop(&sc->bnx_timeout); 3497 3498 mii_down(&sc->bnx_mii); 3499 3500 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3501 3502 /* Disable the transmit/receive blocks. */ 3503 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3504 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3505 DELAY(20); 3506 3507 bnx_disable_intr(sc); 3508 3509 /* Tell firmware that the driver is going away. */ 3510 if (disable) 3511 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3512 else 3513 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3514 3515 /* Free RX buffers. */ 3516 bnx_free_rx_chain(sc); 3517 3518 /* Free TX buffers. */ 3519 bnx_free_tx_chain(sc); 3520 3521 ifp->if_timer = 0; 3522 3523 sc->bnx_link = 0; 3524 3525 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3526 3527 bnx_mgmt_init(sc); 3528 } 3529 3530 int 3531 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3532 { 3533 struct pci_attach_args *pa = &(sc->bnx_pa); 3534 uint32_t val; 3535 int i, rc = 0; 3536 3537 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3538 3539 /* Wait for pending PCI transactions to complete. */ 3540 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 3541 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) { 3542 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3543 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3544 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3545 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3546 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3547 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3548 DELAY(5); 3549 } else { 3550 /* Disable DMA */ 3551 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3552 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3553 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3554 REG_RD(sc, BNX_MISC_NEW_CORE_CTL); /* barrier */ 3555 3556 for (i = 0; i < 100; i++) { 3557 delay(1 * 1000); 3558 val = REG_RD(sc, BNX_PCICFG_DEVICE_CONTROL); 3559 if ((val & PCIE_DCSR_TRANSACTION_PND) == 0) 3560 break; 3561 } 3562 } 3563 3564 /* Assume bootcode is running. */ 3565 sc->bnx_fw_timed_out = 0; 3566 3567 /* Give the firmware a chance to prepare for the reset. */ 3568 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3569 if (rc) 3570 goto bnx_reset_exit; 3571 3572 /* Set a firmware reminder that this is a soft reset. */ 3573 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3574 BNX_DRV_RESET_SIGNATURE_MAGIC); 3575 3576 /* Dummy read to force the chip to complete all current transactions. */ 3577 val = REG_RD(sc, BNX_MISC_ID); 3578 3579 /* Chip reset. */ 3580 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3581 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3582 REG_RD(sc, BNX_MISC_COMMAND); 3583 DELAY(5); 3584 3585 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3586 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3587 3588 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3589 val); 3590 } else { 3591 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3592 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3593 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3594 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3595 3596 /* Allow up to 30us for reset to complete. */ 3597 for (i = 0; i < 10; i++) { 3598 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3599 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3600 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3601 break; 3602 } 3603 DELAY(10); 3604 } 3605 3606 /* Check that reset completed successfully. */ 3607 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3608 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3609 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3610 __FILE__, __LINE__); 3611 rc = EBUSY; 3612 goto bnx_reset_exit; 3613 } 3614 } 3615 3616 /* Make sure byte swapping is properly configured. */ 3617 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3618 if (val != 0x01020304) { 3619 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3620 __FILE__, __LINE__); 3621 rc = ENODEV; 3622 goto bnx_reset_exit; 3623 } 3624 3625 /* Just completed a reset, assume that firmware is running again. */ 3626 sc->bnx_fw_timed_out = 0; 3627 3628 /* Wait for the firmware to finish its initialization. */ 3629 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3630 if (rc) 3631 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3632 "initialization!\n", __FILE__, __LINE__); 3633 3634 bnx_reset_exit: 3635 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3636 3637 return rc; 3638 } 3639 3640 int 3641 bnx_chipinit(struct bnx_softc *sc) 3642 { 3643 struct pci_attach_args *pa = &(sc->bnx_pa); 3644 uint32_t val; 3645 int rc = 0; 3646 3647 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3648 3649 /* Make sure the interrupt is not active. */ 3650 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3651 3652 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3653 /* channels and PCI clock compensation delay. */ 3654 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3655 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3656 #if BYTE_ORDER == BIG_ENDIAN 3657 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3658 #endif 3659 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3660 DMA_READ_CHANS << 12 | 3661 DMA_WRITE_CHANS << 16; 3662 3663 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3664 3665 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3666 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3667 3668 /* 3669 * This setting resolves a problem observed on certain Intel PCI 3670 * chipsets that cannot handle multiple outstanding DMA operations. 3671 * See errata E9_5706A1_65. 3672 */ 3673 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3674 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3675 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3676 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3677 3678 REG_WR(sc, BNX_DMA_CONFIG, val); 3679 3680 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3681 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3682 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3683 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3684 val & ~0x20000); 3685 } 3686 3687 /* Enable the RX_V2P and Context state machines before access. */ 3688 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3689 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3690 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3691 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3692 3693 /* Initialize context mapping and zero out the quick contexts. */ 3694 bnx_init_context(sc); 3695 3696 /* Initialize the on-boards CPUs */ 3697 bnx_init_cpus(sc); 3698 3699 /* Enable management frames (NC-SI) to flow to the MCP. */ 3700 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3701 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) | 3702 BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3703 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3704 } 3705 3706 /* Prepare NVRAM for access. */ 3707 if (bnx_init_nvram(sc)) { 3708 rc = ENODEV; 3709 goto bnx_chipinit_exit; 3710 } 3711 3712 /* Set the kernel bypass block size */ 3713 val = REG_RD(sc, BNX_MQ_CONFIG); 3714 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3715 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3716 3717 /* Enable bins used on the 5709. */ 3718 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3719 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3720 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3721 val |= BNX_MQ_CONFIG_HALT_DIS; 3722 } 3723 3724 REG_WR(sc, BNX_MQ_CONFIG, val); 3725 3726 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3727 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3728 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3729 3730 val = (BCM_PAGE_BITS - 8) << 24; 3731 REG_WR(sc, BNX_RV2P_CONFIG, val); 3732 3733 /* Configure page size. */ 3734 val = REG_RD(sc, BNX_TBDR_CONFIG); 3735 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3736 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3737 REG_WR(sc, BNX_TBDR_CONFIG, val); 3738 3739 #if 0 3740 /* Set the perfect match control register to default. */ 3741 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3742 #endif 3743 3744 bnx_chipinit_exit: 3745 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3746 3747 return rc; 3748 } 3749 3750 /****************************************************************************/ 3751 /* Initialize the controller in preparation to send/receive traffic. */ 3752 /* */ 3753 /* Returns: */ 3754 /* 0 for success, positive value for failure. */ 3755 /****************************************************************************/ 3756 int 3757 bnx_blockinit(struct bnx_softc *sc) 3758 { 3759 uint32_t reg, val; 3760 int rc = 0; 3761 3762 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3763 3764 /* Load the hardware default MAC address. */ 3765 bnx_set_mac_addr(sc); 3766 3767 /* Set the Ethernet backoff seed value */ 3768 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3769 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3770 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3771 3772 sc->last_status_idx = 0; 3773 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3774 3775 /* Set up link change interrupt generation. */ 3776 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3777 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3778 3779 /* Program the physical address of the status block. */ 3780 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3781 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3782 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3783 3784 /* Program the physical address of the statistics block. */ 3785 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3786 (uint32_t)(sc->stats_block_paddr)); 3787 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3788 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3789 3790 /* Program various host coalescing parameters. */ 3791 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3792 << 16) | sc->bnx_tx_quick_cons_trip); 3793 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3794 << 16) | sc->bnx_rx_quick_cons_trip); 3795 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3796 sc->bnx_comp_prod_trip); 3797 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3798 sc->bnx_tx_ticks); 3799 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3800 sc->bnx_rx_ticks); 3801 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3802 sc->bnx_com_ticks); 3803 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3804 sc->bnx_cmd_ticks); 3805 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3806 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3807 REG_WR(sc, BNX_HC_CONFIG, 3808 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3809 BNX_HC_CONFIG_COLLECT_STATS)); 3810 3811 /* Clear the internal statistics counters. */ 3812 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3813 3814 /* Verify that bootcode is running. */ 3815 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3816 3817 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3818 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3819 __FILE__, __LINE__); reg = 0); 3820 3821 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3822 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3823 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3824 "Expected: 08%08X\n", __FILE__, __LINE__, 3825 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3826 BNX_DEV_INFO_SIGNATURE_MAGIC); 3827 rc = ENODEV; 3828 goto bnx_blockinit_exit; 3829 } 3830 3831 /* Enable DMA */ 3832 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3833 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3834 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3835 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3836 } 3837 3838 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3839 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3840 3841 /* Disable management frames (NC-SI) from flowing to the MCP. */ 3842 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3843 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) & 3844 ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3845 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3846 } 3847 3848 /* Enable all remaining blocks in the MAC. */ 3849 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3850 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3851 BNX_MISC_ENABLE_DEFAULT_XI); 3852 } else 3853 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3854 3855 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3856 DELAY(20); 3857 3858 bnx_blockinit_exit: 3859 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3860 3861 return rc; 3862 } 3863 3864 static int 3865 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3866 uint16_t *chain_prod, uint32_t *prod_bseq) 3867 { 3868 bus_dmamap_t map; 3869 struct rx_bd *rxbd; 3870 uint32_t addr; 3871 int i; 3872 #ifdef BNX_DEBUG 3873 uint16_t debug_chain_prod = *chain_prod; 3874 #endif 3875 uint16_t first_chain_prod; 3876 3877 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3878 3879 /* Map the mbuf cluster into device memory. */ 3880 map = sc->rx_mbuf_map[*chain_prod]; 3881 first_chain_prod = *chain_prod; 3882 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3883 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3884 __FILE__, __LINE__); 3885 3886 m_freem(m_new); 3887 3888 DBRUNIF(1, sc->rx_mbuf_alloc--); 3889 3890 return ENOBUFS; 3891 } 3892 /* Make sure there is room in the receive chain. */ 3893 if (map->dm_nsegs > sc->free_rx_bd) { 3894 bus_dmamap_unload(sc->bnx_dmatag, map); 3895 m_freem(m_new); 3896 return EFBIG; 3897 } 3898 #ifdef BNX_DEBUG 3899 /* Track the distribution of buffer segments. */ 3900 sc->rx_mbuf_segs[map->dm_nsegs]++; 3901 #endif 3902 3903 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3904 BUS_DMASYNC_PREREAD); 3905 3906 /* Update some debug statistics counters */ 3907 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3908 sc->rx_low_watermark = sc->free_rx_bd); 3909 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3910 3911 /* 3912 * Setup the rx_bd for the first segment 3913 */ 3914 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3915 3916 addr = (uint32_t)map->dm_segs[0].ds_addr; 3917 rxbd->rx_bd_haddr_lo = addr; 3918 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3919 rxbd->rx_bd_haddr_hi = addr; 3920 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3921 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3922 *prod_bseq += map->dm_segs[0].ds_len; 3923 bus_dmamap_sync(sc->bnx_dmatag, 3924 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3925 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3927 3928 for (i = 1; i < map->dm_nsegs; i++) { 3929 *prod = NEXT_RX_BD(*prod); 3930 *chain_prod = RX_CHAIN_IDX(*prod); 3931 3932 rxbd = 3933 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3934 3935 addr = (uint32_t)map->dm_segs[i].ds_addr; 3936 rxbd->rx_bd_haddr_lo = addr; 3937 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3938 rxbd->rx_bd_haddr_hi = addr; 3939 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3940 rxbd->rx_bd_flags = 0; 3941 *prod_bseq += map->dm_segs[i].ds_len; 3942 bus_dmamap_sync(sc->bnx_dmatag, 3943 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3944 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3945 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3946 } 3947 3948 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3949 bus_dmamap_sync(sc->bnx_dmatag, 3950 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3951 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3952 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3953 3954 /* 3955 * Save the mbuf, adjust the map pointer (swap map for first and 3956 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3957 * and update our counter. 3958 */ 3959 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3960 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3961 sc->rx_mbuf_map[*chain_prod] = map; 3962 sc->free_rx_bd -= map->dm_nsegs; 3963 3964 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3965 map->dm_nsegs)); 3966 *prod = NEXT_RX_BD(*prod); 3967 *chain_prod = RX_CHAIN_IDX(*prod); 3968 3969 return 0; 3970 } 3971 3972 /****************************************************************************/ 3973 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3974 /* */ 3975 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3976 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3977 /* necessary. */ 3978 /* */ 3979 /* Returns: */ 3980 /* 0 for success, positive value for failure. */ 3981 /****************************************************************************/ 3982 int 3983 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3984 uint16_t *chain_prod, uint32_t *prod_bseq) 3985 { 3986 struct mbuf *m_new = NULL; 3987 int rc = 0; 3988 uint16_t min_free_bd; 3989 3990 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3991 __func__); 3992 3993 /* Make sure the inputs are valid. */ 3994 DBRUNIF((*chain_prod > MAX_RX_BD), 3995 aprint_error_dev(sc->bnx_dev, 3996 "RX producer out of range: 0x%04X > 0x%04X\n", 3997 *chain_prod, (uint16_t)MAX_RX_BD)); 3998 3999 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 4000 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 4001 *prod_bseq); 4002 4003 /* try to get in as many mbufs as possible */ 4004 if (sc->mbuf_alloc_size == MCLBYTES) 4005 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 4006 else 4007 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 4008 while (sc->free_rx_bd >= min_free_bd) { 4009 /* Simulate an mbuf allocation failure. */ 4010 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4011 aprint_error_dev(sc->bnx_dev, 4012 "Simulating mbuf allocation failure.\n"); 4013 sc->mbuf_sim_alloc_failed++; 4014 rc = ENOBUFS; 4015 goto bnx_get_buf_exit); 4016 4017 /* This is a new mbuf allocation. */ 4018 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4019 if (m_new == NULL) { 4020 DBPRINT(sc, BNX_WARN, 4021 "%s(%d): RX mbuf header allocation failed!\n", 4022 __FILE__, __LINE__); 4023 4024 sc->mbuf_alloc_failed++; 4025 4026 rc = ENOBUFS; 4027 goto bnx_get_buf_exit; 4028 } 4029 4030 DBRUNIF(1, sc->rx_mbuf_alloc++); 4031 4032 /* Simulate an mbuf cluster allocation failure. */ 4033 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4034 m_freem(m_new); 4035 sc->rx_mbuf_alloc--; 4036 sc->mbuf_alloc_failed++; 4037 sc->mbuf_sim_alloc_failed++; 4038 rc = ENOBUFS; 4039 goto bnx_get_buf_exit); 4040 4041 if (sc->mbuf_alloc_size == MCLBYTES) 4042 MCLGET(m_new, M_DONTWAIT); 4043 else 4044 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 4045 M_DONTWAIT); 4046 if (!(m_new->m_flags & M_EXT)) { 4047 DBPRINT(sc, BNX_WARN, 4048 "%s(%d): RX mbuf chain allocation failed!\n", 4049 __FILE__, __LINE__); 4050 4051 m_freem(m_new); 4052 4053 DBRUNIF(1, sc->rx_mbuf_alloc--); 4054 sc->mbuf_alloc_failed++; 4055 4056 rc = ENOBUFS; 4057 goto bnx_get_buf_exit; 4058 } 4059 4060 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 4061 if (rc != 0) 4062 goto bnx_get_buf_exit; 4063 } 4064 4065 bnx_get_buf_exit: 4066 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 4067 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 4068 *chain_prod, *prod_bseq); 4069 4070 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 4071 __func__); 4072 4073 return rc; 4074 } 4075 4076 void 4077 bnx_alloc_pkts(struct work * unused, void * arg) 4078 { 4079 struct bnx_softc *sc = arg; 4080 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4081 struct bnx_pkt *pkt; 4082 int i, s; 4083 4084 for (i = 0; i < 4; i++) { /* magic! */ 4085 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 4086 if (pkt == NULL) 4087 break; 4088 4089 if (bus_dmamap_create(sc->bnx_dmatag, 4090 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4091 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4092 &pkt->pkt_dmamap) != 0) 4093 goto put; 4094 4095 if (!ISSET(ifp->if_flags, IFF_UP)) 4096 goto stopping; 4097 4098 mutex_enter(&sc->tx_pkt_mtx); 4099 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4100 sc->tx_pkt_count++; 4101 mutex_exit(&sc->tx_pkt_mtx); 4102 } 4103 4104 mutex_enter(&sc->tx_pkt_mtx); 4105 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4106 mutex_exit(&sc->tx_pkt_mtx); 4107 4108 /* fire-up TX now that allocations have been done */ 4109 s = splnet(); 4110 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4111 bnx_start(ifp); 4112 splx(s); 4113 4114 return; 4115 4116 stopping: 4117 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4118 put: 4119 pool_put(bnx_tx_pool, pkt); 4120 return; 4121 } 4122 4123 /****************************************************************************/ 4124 /* Initialize the TX context memory. */ 4125 /* */ 4126 /* Returns: */ 4127 /* Nothing */ 4128 /****************************************************************************/ 4129 void 4130 bnx_init_tx_context(struct bnx_softc *sc) 4131 { 4132 uint32_t val; 4133 4134 /* Initialize the context ID for an L2 TX chain. */ 4135 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4136 /* Set the CID type to support an L2 connection. */ 4137 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4138 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4139 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4140 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4141 4142 /* Point the hardware to the first page in the chain. */ 4143 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4144 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4145 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4146 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4147 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4148 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4149 } else { 4150 /* Set the CID type to support an L2 connection. */ 4151 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4152 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4153 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4154 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4155 4156 /* Point the hardware to the first page in the chain. */ 4157 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4158 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4159 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4160 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4161 } 4162 } 4163 4164 4165 /****************************************************************************/ 4166 /* Allocate memory and initialize the TX data structures. */ 4167 /* */ 4168 /* Returns: */ 4169 /* 0 for success, positive value for failure. */ 4170 /****************************************************************************/ 4171 int 4172 bnx_init_tx_chain(struct bnx_softc *sc) 4173 { 4174 struct tx_bd *txbd; 4175 uint32_t addr; 4176 int i, rc = 0; 4177 4178 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4179 4180 /* Set the initial TX producer/consumer indices. */ 4181 sc->tx_prod = 0; 4182 sc->tx_cons = 0; 4183 sc->tx_prod_bseq = 0; 4184 sc->used_tx_bd = 0; 4185 sc->max_tx_bd = USABLE_TX_BD; 4186 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4187 DBRUNIF(1, sc->tx_full_count = 0); 4188 4189 /* 4190 * The NetXtreme II supports a linked-list structure called 4191 * a Buffer Descriptor Chain (or BD chain). A BD chain 4192 * consists of a series of 1 or more chain pages, each of which 4193 * consists of a fixed number of BD entries. 4194 * The last BD entry on each page is a pointer to the next page 4195 * in the chain, and the last pointer in the BD chain 4196 * points back to the beginning of the chain. 4197 */ 4198 4199 /* Set the TX next pointer chain entries. */ 4200 for (i = 0; i < TX_PAGES; i++) { 4201 int j; 4202 4203 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4204 4205 /* Check if we've reached the last page. */ 4206 if (i == (TX_PAGES - 1)) 4207 j = 0; 4208 else 4209 j = i + 1; 4210 4211 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4212 txbd->tx_bd_haddr_lo = addr; 4213 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4214 txbd->tx_bd_haddr_hi = addr; 4215 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4216 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4217 } 4218 4219 /* 4220 * Initialize the context ID for an L2 TX chain. 4221 */ 4222 bnx_init_tx_context(sc); 4223 4224 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4225 4226 return rc; 4227 } 4228 4229 /****************************************************************************/ 4230 /* Free memory and clear the TX data structures. */ 4231 /* */ 4232 /* Returns: */ 4233 /* Nothing. */ 4234 /****************************************************************************/ 4235 void 4236 bnx_free_tx_chain(struct bnx_softc *sc) 4237 { 4238 struct bnx_pkt *pkt; 4239 int i; 4240 4241 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4242 4243 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4244 mutex_enter(&sc->tx_pkt_mtx); 4245 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4246 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4247 mutex_exit(&sc->tx_pkt_mtx); 4248 4249 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4250 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4251 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4252 4253 m_freem(pkt->pkt_mbuf); 4254 DBRUNIF(1, sc->tx_mbuf_alloc--); 4255 4256 mutex_enter(&sc->tx_pkt_mtx); 4257 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4258 } 4259 mutex_exit(&sc->tx_pkt_mtx); 4260 4261 /* Clear each TX chain page. */ 4262 for (i = 0; i < TX_PAGES; i++) { 4263 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4264 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4265 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4266 } 4267 4268 sc->used_tx_bd = 0; 4269 4270 /* Check if we lost any mbufs in the process. */ 4271 DBRUNIF((sc->tx_mbuf_alloc), 4272 aprint_error_dev(sc->bnx_dev, 4273 "Memory leak! Lost %d mbufs from tx chain!\n", 4274 sc->tx_mbuf_alloc)); 4275 4276 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4277 } 4278 4279 /****************************************************************************/ 4280 /* Initialize the RX context memory. */ 4281 /* */ 4282 /* Returns: */ 4283 /* Nothing */ 4284 /****************************************************************************/ 4285 void 4286 bnx_init_rx_context(struct bnx_softc *sc) 4287 { 4288 uint32_t val; 4289 4290 /* Initialize the context ID for an L2 RX chain. */ 4291 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4292 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4293 4294 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4295 val |= 0x000000ff; 4296 4297 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4298 4299 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4300 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4301 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4302 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4303 } 4304 4305 /* Point the hardware to the first page in the chain. */ 4306 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4307 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4308 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4309 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4310 } 4311 4312 /****************************************************************************/ 4313 /* Allocate memory and initialize the RX data structures. */ 4314 /* */ 4315 /* Returns: */ 4316 /* 0 for success, positive value for failure. */ 4317 /****************************************************************************/ 4318 int 4319 bnx_init_rx_chain(struct bnx_softc *sc) 4320 { 4321 struct rx_bd *rxbd; 4322 int i, rc = 0; 4323 uint16_t prod, chain_prod; 4324 uint32_t prod_bseq, addr; 4325 4326 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4327 4328 /* Initialize the RX producer and consumer indices. */ 4329 sc->rx_prod = 0; 4330 sc->rx_cons = 0; 4331 sc->rx_prod_bseq = 0; 4332 sc->free_rx_bd = USABLE_RX_BD; 4333 sc->max_rx_bd = USABLE_RX_BD; 4334 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4335 DBRUNIF(1, sc->rx_empty_count = 0); 4336 4337 /* Initialize the RX next pointer chain entries. */ 4338 for (i = 0; i < RX_PAGES; i++) { 4339 int j; 4340 4341 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4342 4343 /* Check if we've reached the last page. */ 4344 if (i == (RX_PAGES - 1)) 4345 j = 0; 4346 else 4347 j = i + 1; 4348 4349 /* Setup the chain page pointers. */ 4350 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4351 rxbd->rx_bd_haddr_hi = addr; 4352 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4353 rxbd->rx_bd_haddr_lo = addr; 4354 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4355 0, BNX_RX_CHAIN_PAGE_SZ, 4356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4357 } 4358 4359 /* Allocate mbuf clusters for the rx_bd chain. */ 4360 prod = prod_bseq = 0; 4361 chain_prod = RX_CHAIN_IDX(prod); 4362 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4363 BNX_PRINTF(sc, 4364 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4365 } 4366 4367 /* Save the RX chain producer index. */ 4368 sc->rx_prod = prod; 4369 sc->rx_prod_bseq = prod_bseq; 4370 4371 for (i = 0; i < RX_PAGES; i++) 4372 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4373 sc->rx_bd_chain_map[i]->dm_mapsize, 4374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4375 4376 /* Tell the chip about the waiting rx_bd's. */ 4377 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4378 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4379 4380 bnx_init_rx_context(sc); 4381 4382 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4383 4384 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4385 4386 return rc; 4387 } 4388 4389 /****************************************************************************/ 4390 /* Free memory and clear the RX data structures. */ 4391 /* */ 4392 /* Returns: */ 4393 /* Nothing. */ 4394 /****************************************************************************/ 4395 void 4396 bnx_free_rx_chain(struct bnx_softc *sc) 4397 { 4398 int i; 4399 4400 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4401 4402 /* Free any mbufs still in the RX mbuf chain. */ 4403 for (i = 0; i < TOTAL_RX_BD; i++) { 4404 if (sc->rx_mbuf_ptr[i] != NULL) { 4405 if (sc->rx_mbuf_map[i] != NULL) { 4406 bus_dmamap_sync(sc->bnx_dmatag, 4407 sc->rx_mbuf_map[i], 0, 4408 sc->rx_mbuf_map[i]->dm_mapsize, 4409 BUS_DMASYNC_POSTREAD); 4410 bus_dmamap_unload(sc->bnx_dmatag, 4411 sc->rx_mbuf_map[i]); 4412 } 4413 m_freem(sc->rx_mbuf_ptr[i]); 4414 sc->rx_mbuf_ptr[i] = NULL; 4415 DBRUNIF(1, sc->rx_mbuf_alloc--); 4416 } 4417 } 4418 4419 /* Clear each RX chain page. */ 4420 for (i = 0; i < RX_PAGES; i++) 4421 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4422 4423 sc->free_rx_bd = sc->max_rx_bd; 4424 4425 /* Check if we lost any mbufs in the process. */ 4426 DBRUNIF((sc->rx_mbuf_alloc), 4427 aprint_error_dev(sc->bnx_dev, 4428 "Memory leak! Lost %d mbufs from rx chain!\n", 4429 sc->rx_mbuf_alloc)); 4430 4431 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4432 } 4433 4434 /****************************************************************************/ 4435 /* Set media options. */ 4436 /* */ 4437 /* Returns: */ 4438 /* 0 for success, positive value for failure. */ 4439 /****************************************************************************/ 4440 int 4441 bnx_ifmedia_upd(struct ifnet *ifp) 4442 { 4443 struct bnx_softc *sc; 4444 struct mii_data *mii; 4445 int rc = 0; 4446 4447 sc = ifp->if_softc; 4448 4449 mii = &sc->bnx_mii; 4450 sc->bnx_link = 0; 4451 if (mii->mii_instance) { 4452 struct mii_softc *miisc; 4453 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4454 mii_phy_reset(miisc); 4455 } 4456 mii_mediachg(mii); 4457 4458 return rc; 4459 } 4460 4461 /****************************************************************************/ 4462 /* Reports current media status. */ 4463 /* */ 4464 /* Returns: */ 4465 /* Nothing. */ 4466 /****************************************************************************/ 4467 void 4468 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4469 { 4470 struct bnx_softc *sc; 4471 struct mii_data *mii; 4472 int s; 4473 4474 sc = ifp->if_softc; 4475 4476 s = splnet(); 4477 4478 mii = &sc->bnx_mii; 4479 4480 mii_pollstat(mii); 4481 ifmr->ifm_status = mii->mii_media_status; 4482 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4483 sc->bnx_flowflags; 4484 4485 splx(s); 4486 } 4487 4488 /****************************************************************************/ 4489 /* Handles PHY generated interrupt events. */ 4490 /* */ 4491 /* Returns: */ 4492 /* Nothing. */ 4493 /****************************************************************************/ 4494 void 4495 bnx_phy_intr(struct bnx_softc *sc) 4496 { 4497 uint32_t new_link_state, old_link_state; 4498 4499 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4500 BUS_DMASYNC_POSTREAD); 4501 new_link_state = sc->status_block->status_attn_bits & 4502 STATUS_ATTN_BITS_LINK_STATE; 4503 old_link_state = sc->status_block->status_attn_bits_ack & 4504 STATUS_ATTN_BITS_LINK_STATE; 4505 4506 /* Handle any changes if the link state has changed. */ 4507 if (new_link_state != old_link_state) { 4508 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4509 4510 sc->bnx_link = 0; 4511 callout_stop(&sc->bnx_timeout); 4512 bnx_tick(sc); 4513 4514 /* Update the status_attn_bits_ack field in the status block. */ 4515 if (new_link_state) { 4516 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4517 STATUS_ATTN_BITS_LINK_STATE); 4518 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4519 } else { 4520 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4521 STATUS_ATTN_BITS_LINK_STATE); 4522 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4523 } 4524 } 4525 4526 /* Acknowledge the link change interrupt. */ 4527 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4528 } 4529 4530 /****************************************************************************/ 4531 /* Handles received frame interrupt events. */ 4532 /* */ 4533 /* Returns: */ 4534 /* Nothing. */ 4535 /****************************************************************************/ 4536 void 4537 bnx_rx_intr(struct bnx_softc *sc) 4538 { 4539 struct status_block *sblk = sc->status_block; 4540 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4541 uint16_t hw_cons, sw_cons, sw_chain_cons; 4542 uint16_t sw_prod, sw_chain_prod; 4543 uint32_t sw_prod_bseq; 4544 struct l2_fhdr *l2fhdr; 4545 int i; 4546 4547 DBRUNIF(1, sc->rx_interrupts++); 4548 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4549 BUS_DMASYNC_POSTREAD); 4550 4551 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4552 for (i = 0; i < RX_PAGES; i++) 4553 bus_dmamap_sync(sc->bnx_dmatag, 4554 sc->rx_bd_chain_map[i], 0, 4555 sc->rx_bd_chain_map[i]->dm_mapsize, 4556 BUS_DMASYNC_POSTWRITE); 4557 4558 /* Get the hardware's view of the RX consumer index. */ 4559 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4560 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4561 hw_cons++; 4562 4563 /* Get working copies of the driver's view of the RX indices. */ 4564 sw_cons = sc->rx_cons; 4565 sw_prod = sc->rx_prod; 4566 sw_prod_bseq = sc->rx_prod_bseq; 4567 4568 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4569 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4570 __func__, sw_prod, sw_cons, sw_prod_bseq); 4571 4572 /* Prevent speculative reads from getting ahead of the status block. */ 4573 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4574 BUS_SPACE_BARRIER_READ); 4575 4576 /* Update some debug statistics counters */ 4577 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4578 sc->rx_low_watermark = sc->free_rx_bd); 4579 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4580 4581 /* 4582 * Scan through the receive chain as long 4583 * as there is work to do. 4584 */ 4585 while (sw_cons != hw_cons) { 4586 struct mbuf *m; 4587 struct rx_bd *rxbd __diagused; 4588 unsigned int len; 4589 uint32_t status; 4590 4591 /* Convert the producer/consumer indices to an actual 4592 * rx_bd index. 4593 */ 4594 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4595 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4596 4597 /* Get the used rx_bd. */ 4598 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4599 sc->free_rx_bd++; 4600 4601 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4602 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4603 4604 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4605 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4606 #ifdef DIAGNOSTIC 4607 /* Validate that this is the last rx_bd. */ 4608 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4609 printf("%s: Unexpected mbuf found in " 4610 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4611 sw_chain_cons); 4612 } 4613 #endif 4614 4615 /* DRC - ToDo: If the received packet is small, say 4616 * less than 128 bytes, allocate a new mbuf 4617 * here, copy the data to that mbuf, and 4618 * recycle the mapped jumbo frame. 4619 */ 4620 4621 /* Unmap the mbuf from DMA space. */ 4622 #ifdef DIAGNOSTIC 4623 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4624 printf("invalid map sw_cons 0x%x " 4625 "sw_prod 0x%x " 4626 "sw_chain_cons 0x%x " 4627 "sw_chain_prod 0x%x " 4628 "hw_cons 0x%x " 4629 "TOTAL_RX_BD_PER_PAGE 0x%x " 4630 "TOTAL_RX_BD 0x%x\n", 4631 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4632 hw_cons, 4633 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4634 } 4635 #endif 4636 bus_dmamap_sync(sc->bnx_dmatag, 4637 sc->rx_mbuf_map[sw_chain_cons], 0, 4638 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4639 BUS_DMASYNC_POSTREAD); 4640 bus_dmamap_unload(sc->bnx_dmatag, 4641 sc->rx_mbuf_map[sw_chain_cons]); 4642 4643 /* Remove the mbuf from the driver's chain. */ 4644 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4645 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4646 4647 /* 4648 * Frames received on the NetXteme II are prepended 4649 * with the l2_fhdr structure which provides status 4650 * information about the received frame (including 4651 * VLAN tags and checksum info) and are also 4652 * automatically adjusted to align the IP header 4653 * (i.e. two null bytes are inserted before the 4654 * Ethernet header). 4655 */ 4656 l2fhdr = mtod(m, struct l2_fhdr *); 4657 4658 len = l2fhdr->l2_fhdr_pkt_len; 4659 status = l2fhdr->l2_fhdr_status; 4660 4661 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4662 aprint_error("Simulating l2_fhdr status error.\n"); 4663 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4664 4665 /* Watch for unusual sized frames. */ 4666 DBRUNIF(((len < BNX_MIN_MTU) || 4667 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4668 aprint_error_dev(sc->bnx_dev, 4669 "Unusual frame size found. " 4670 "Min(%d), Actual(%d), Max(%d)\n", 4671 (int)BNX_MIN_MTU, len, 4672 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4673 4674 bnx_dump_mbuf(sc, m); 4675 bnx_breakpoint(sc)); 4676 4677 len -= ETHER_CRC_LEN; 4678 4679 /* Check the received frame for errors. */ 4680 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4681 L2_FHDR_ERRORS_PHY_DECODE | 4682 L2_FHDR_ERRORS_ALIGNMENT | 4683 L2_FHDR_ERRORS_TOO_SHORT | 4684 L2_FHDR_ERRORS_GIANT_FRAME)) || 4685 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4686 len > 4687 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4688 if_statinc(ifp, if_ierrors); 4689 DBRUNIF(1, sc->l2fhdr_status_errors++); 4690 4691 /* Reuse the mbuf for a new frame. */ 4692 if (bnx_add_buf(sc, m, &sw_prod, 4693 &sw_chain_prod, &sw_prod_bseq)) { 4694 DBRUNIF(1, bnx_breakpoint(sc)); 4695 panic("%s: Can't reuse RX mbuf!\n", 4696 device_xname(sc->bnx_dev)); 4697 } 4698 continue; 4699 } 4700 4701 /* 4702 * Get a new mbuf for the rx_bd. If no new 4703 * mbufs are available then reuse the current mbuf, 4704 * log an ierror on the interface, and generate 4705 * an error in the system log. 4706 */ 4707 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4708 &sw_prod_bseq)) { 4709 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4710 "Failed to allocate " 4711 "new mbuf, incoming frame dropped!\n")); 4712 4713 if_statinc(ifp, if_ierrors); 4714 4715 /* Try and reuse the exisitng mbuf. */ 4716 if (bnx_add_buf(sc, m, &sw_prod, 4717 &sw_chain_prod, &sw_prod_bseq)) { 4718 DBRUNIF(1, bnx_breakpoint(sc)); 4719 panic("%s: Double mbuf allocation " 4720 "failure!", 4721 device_xname(sc->bnx_dev)); 4722 } 4723 continue; 4724 } 4725 4726 /* Skip over the l2_fhdr when passing the data up 4727 * the stack. 4728 */ 4729 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4730 4731 /* Adjust the pckt length to match the received data. */ 4732 m->m_pkthdr.len = m->m_len = len; 4733 4734 /* Send the packet to the appropriate interface. */ 4735 m_set_rcvif(m, ifp); 4736 4737 DBRUN(BNX_VERBOSE_RECV, 4738 struct ether_header *eh; 4739 eh = mtod(m, struct ether_header *); 4740 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4741 __func__, ether_sprintf(eh->ether_dhost), 4742 ether_sprintf(eh->ether_shost), 4743 htons(eh->ether_type))); 4744 4745 /* Validate the checksum. */ 4746 4747 /* Check for an IP datagram. */ 4748 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4749 /* Check if the IP checksum is valid. */ 4750 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4751 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4752 #ifdef BNX_DEBUG 4753 else 4754 DBPRINT(sc, BNX_WARN_SEND, 4755 "%s(): Invalid IP checksum " 4756 "= 0x%04X!\n", 4757 __func__, 4758 l2fhdr->l2_fhdr_ip_xsum 4759 ); 4760 #endif 4761 } 4762 4763 /* Check for a valid TCP/UDP frame. */ 4764 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4765 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4766 /* Check for a good TCP/UDP checksum. */ 4767 if ((status & 4768 (L2_FHDR_ERRORS_TCP_XSUM | 4769 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4770 m->m_pkthdr.csum_flags |= 4771 M_CSUM_TCPv4 | 4772 M_CSUM_UDPv4; 4773 } else { 4774 DBPRINT(sc, BNX_WARN_SEND, 4775 "%s(): Invalid TCP/UDP " 4776 "checksum = 0x%04X!\n", 4777 __func__, 4778 l2fhdr->l2_fhdr_tcp_udp_xsum); 4779 } 4780 } 4781 4782 /* 4783 * If we received a packet with a vlan tag, 4784 * attach that information to the packet. 4785 */ 4786 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4787 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4788 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4789 } 4790 4791 /* Pass the mbuf off to the upper layers. */ 4792 4793 DBPRINT(sc, BNX_VERBOSE_RECV, 4794 "%s(): Passing received frame up.\n", __func__); 4795 if_percpuq_enqueue(ifp->if_percpuq, m); 4796 DBRUNIF(1, sc->rx_mbuf_alloc--); 4797 4798 } 4799 4800 sw_cons = NEXT_RX_BD(sw_cons); 4801 4802 /* Refresh hw_cons to see if there's new work */ 4803 if (sw_cons == hw_cons) { 4804 hw_cons = sc->hw_rx_cons = 4805 sblk->status_rx_quick_consumer_index0; 4806 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4807 USABLE_RX_BD_PER_PAGE) 4808 hw_cons++; 4809 } 4810 4811 /* Prevent speculative reads from getting ahead of 4812 * the status block. 4813 */ 4814 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4815 BUS_SPACE_BARRIER_READ); 4816 } 4817 4818 for (i = 0; i < RX_PAGES; i++) 4819 bus_dmamap_sync(sc->bnx_dmatag, 4820 sc->rx_bd_chain_map[i], 0, 4821 sc->rx_bd_chain_map[i]->dm_mapsize, 4822 BUS_DMASYNC_PREWRITE); 4823 4824 sc->rx_cons = sw_cons; 4825 sc->rx_prod = sw_prod; 4826 sc->rx_prod_bseq = sw_prod_bseq; 4827 4828 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4829 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4830 4831 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4832 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4833 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4834 } 4835 4836 /****************************************************************************/ 4837 /* Handles transmit completion interrupt events. */ 4838 /* */ 4839 /* Returns: */ 4840 /* Nothing. */ 4841 /****************************************************************************/ 4842 void 4843 bnx_tx_intr(struct bnx_softc *sc) 4844 { 4845 struct status_block *sblk = sc->status_block; 4846 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4847 struct bnx_pkt *pkt; 4848 bus_dmamap_t map; 4849 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4850 4851 DBRUNIF(1, sc->tx_interrupts++); 4852 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4853 BUS_DMASYNC_POSTREAD); 4854 4855 /* Get the hardware's view of the TX consumer index. */ 4856 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4857 4858 /* Skip to the next entry if this is a chain page pointer. */ 4859 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4860 hw_tx_cons++; 4861 4862 sw_tx_cons = sc->tx_cons; 4863 4864 /* Prevent speculative reads from getting ahead of the status block. */ 4865 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4866 BUS_SPACE_BARRIER_READ); 4867 4868 /* Cycle through any completed TX chain page entries. */ 4869 while (sw_tx_cons != hw_tx_cons) { 4870 #ifdef BNX_DEBUG 4871 struct tx_bd *txbd = NULL; 4872 #endif 4873 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4874 4875 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4876 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4877 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4878 4879 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4880 aprint_error_dev(sc->bnx_dev, 4881 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4882 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4883 4884 DBRUNIF(1, txbd = &sc->tx_bd_chain 4885 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4886 4887 DBRUNIF((txbd == NULL), 4888 aprint_error_dev(sc->bnx_dev, 4889 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4890 bnx_breakpoint(sc)); 4891 4892 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4893 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4894 4895 4896 mutex_enter(&sc->tx_pkt_mtx); 4897 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4898 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4899 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4900 mutex_exit(&sc->tx_pkt_mtx); 4901 /* 4902 * Free the associated mbuf. Remember 4903 * that only the last tx_bd of a packet 4904 * has an mbuf pointer and DMA map. 4905 */ 4906 map = pkt->pkt_dmamap; 4907 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4908 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4909 bus_dmamap_unload(sc->bnx_dmatag, map); 4910 4911 m_freem(pkt->pkt_mbuf); 4912 DBRUNIF(1, sc->tx_mbuf_alloc--); 4913 4914 if_statinc(ifp, if_opackets); 4915 4916 mutex_enter(&sc->tx_pkt_mtx); 4917 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4918 } 4919 mutex_exit(&sc->tx_pkt_mtx); 4920 4921 sc->used_tx_bd--; 4922 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4923 __FILE__, __LINE__, sc->used_tx_bd); 4924 4925 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4926 4927 /* Refresh hw_cons to see if there's new work. */ 4928 hw_tx_cons = sc->hw_tx_cons = 4929 sblk->status_tx_quick_consumer_index0; 4930 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4931 USABLE_TX_BD_PER_PAGE) 4932 hw_tx_cons++; 4933 4934 /* Prevent speculative reads from getting ahead of 4935 * the status block. 4936 */ 4937 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4938 BUS_SPACE_BARRIER_READ); 4939 } 4940 4941 /* Clear the TX timeout timer. */ 4942 ifp->if_timer = 0; 4943 4944 /* Clear the tx hardware queue full flag. */ 4945 if (sc->used_tx_bd < sc->max_tx_bd) { 4946 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4947 aprint_debug_dev(sc->bnx_dev, 4948 "Open TX chain! %d/%d (used/total)\n", 4949 sc->used_tx_bd, sc->max_tx_bd)); 4950 ifp->if_flags &= ~IFF_OACTIVE; 4951 } 4952 4953 sc->tx_cons = sw_tx_cons; 4954 } 4955 4956 /****************************************************************************/ 4957 /* Disables interrupt generation. */ 4958 /* */ 4959 /* Returns: */ 4960 /* Nothing. */ 4961 /****************************************************************************/ 4962 void 4963 bnx_disable_intr(struct bnx_softc *sc) 4964 { 4965 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4966 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4967 } 4968 4969 /****************************************************************************/ 4970 /* Enables interrupt generation. */ 4971 /* */ 4972 /* Returns: */ 4973 /* Nothing. */ 4974 /****************************************************************************/ 4975 void 4976 bnx_enable_intr(struct bnx_softc *sc) 4977 { 4978 uint32_t val; 4979 4980 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4981 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4982 4983 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4984 sc->last_status_idx); 4985 4986 val = REG_RD(sc, BNX_HC_COMMAND); 4987 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4988 } 4989 4990 /****************************************************************************/ 4991 /* Handles controller initialization. */ 4992 /* */ 4993 /****************************************************************************/ 4994 int 4995 bnx_init(struct ifnet *ifp) 4996 { 4997 struct bnx_softc *sc = ifp->if_softc; 4998 uint32_t ether_mtu; 4999 int s, error = 0; 5000 5001 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 5002 5003 s = splnet(); 5004 5005 bnx_stop(ifp, 0); 5006 5007 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 5008 aprint_error_dev(sc->bnx_dev, 5009 "Controller reset failed!\n"); 5010 goto bnx_init_exit; 5011 } 5012 5013 if ((error = bnx_chipinit(sc)) != 0) { 5014 aprint_error_dev(sc->bnx_dev, 5015 "Controller initialization failed!\n"); 5016 goto bnx_init_exit; 5017 } 5018 5019 if ((error = bnx_blockinit(sc)) != 0) { 5020 aprint_error_dev(sc->bnx_dev, 5021 "Block initialization failed!\n"); 5022 goto bnx_init_exit; 5023 } 5024 5025 /* Calculate and program the Ethernet MRU size. */ 5026 if (ifp->if_mtu <= ETHERMTU) { 5027 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 5028 sc->mbuf_alloc_size = MCLBYTES; 5029 } else { 5030 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 5031 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 5032 } 5033 5034 5035 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 5036 5037 /* 5038 * Program the MRU and enable Jumbo frame 5039 * support. 5040 */ 5041 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 5042 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 5043 5044 /* Calculate the RX Ethernet frame size for rx_bd's. */ 5045 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 5046 5047 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 5048 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 5049 sc->mbuf_alloc_size, sc->max_frame_size); 5050 5051 /* Program appropriate promiscuous/multicast filtering. */ 5052 bnx_iff(sc); 5053 5054 /* Init RX buffer descriptor chain. */ 5055 bnx_init_rx_chain(sc); 5056 5057 /* Init TX buffer descriptor chain. */ 5058 bnx_init_tx_chain(sc); 5059 5060 /* Enable host interrupts. */ 5061 bnx_enable_intr(sc); 5062 5063 mii_ifmedia_change(&sc->bnx_mii); 5064 5065 SET(ifp->if_flags, IFF_RUNNING); 5066 CLR(ifp->if_flags, IFF_OACTIVE); 5067 5068 callout_schedule(&sc->bnx_timeout, hz); 5069 5070 bnx_init_exit: 5071 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5072 5073 splx(s); 5074 5075 return error; 5076 } 5077 5078 void 5079 bnx_mgmt_init(struct bnx_softc *sc) 5080 { 5081 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5082 uint32_t val; 5083 5084 /* Check if the driver is still running and bail out if it is. */ 5085 if (ifp->if_flags & IFF_RUNNING) 5086 goto bnx_mgmt_init_exit; 5087 5088 /* Initialize the on-boards CPUs */ 5089 bnx_init_cpus(sc); 5090 5091 val = (BCM_PAGE_BITS - 8) << 24; 5092 REG_WR(sc, BNX_RV2P_CONFIG, val); 5093 5094 /* Enable all critical blocks in the MAC. */ 5095 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5096 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5097 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5098 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5099 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5100 DELAY(20); 5101 5102 mii_ifmedia_change(&sc->bnx_mii); 5103 5104 bnx_mgmt_init_exit: 5105 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5106 } 5107 5108 /****************************************************************************/ 5109 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5110 /* memory visible to the controller. */ 5111 /* */ 5112 /* Returns: */ 5113 /* 0 for success, positive value for failure. */ 5114 /****************************************************************************/ 5115 int 5116 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5117 { 5118 struct bnx_pkt *pkt; 5119 bus_dmamap_t map; 5120 struct tx_bd *txbd = NULL; 5121 uint16_t vlan_tag = 0, flags = 0; 5122 uint16_t chain_prod, prod; 5123 #ifdef BNX_DEBUG 5124 uint16_t debug_prod; 5125 #endif 5126 uint32_t addr, prod_bseq; 5127 int i, error; 5128 bool remap = true; 5129 5130 mutex_enter(&sc->tx_pkt_mtx); 5131 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5132 if (pkt == NULL) { 5133 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5134 mutex_exit(&sc->tx_pkt_mtx); 5135 return ENETDOWN; 5136 } 5137 5138 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5139 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5140 workqueue_enqueue(sc->bnx_wq, &sc->bnx_wk, NULL); 5141 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5142 } 5143 5144 mutex_exit(&sc->tx_pkt_mtx); 5145 return ENOMEM; 5146 } 5147 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5148 mutex_exit(&sc->tx_pkt_mtx); 5149 5150 /* Transfer any checksum offload flags to the bd. */ 5151 if (m->m_pkthdr.csum_flags) { 5152 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5153 flags |= TX_BD_FLAGS_IP_CKSUM; 5154 if (m->m_pkthdr.csum_flags & 5155 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5156 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5157 } 5158 5159 /* Transfer any VLAN tags to the bd. */ 5160 if (vlan_has_tag(m)) { 5161 flags |= TX_BD_FLAGS_VLAN_TAG; 5162 vlan_tag = vlan_get_tag(m); 5163 } 5164 5165 /* Map the mbuf into DMAable memory. */ 5166 prod = sc->tx_prod; 5167 chain_prod = TX_CHAIN_IDX(prod); 5168 map = pkt->pkt_dmamap; 5169 5170 /* Map the mbuf into our DMA address space. */ 5171 retry: 5172 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5173 if (__predict_false(error)) { 5174 if (error == EFBIG) { 5175 if (remap == true) { 5176 struct mbuf *newm; 5177 5178 remap = false; 5179 newm = m_defrag(m, M_NOWAIT); 5180 if (newm != NULL) { 5181 m = newm; 5182 goto retry; 5183 } 5184 } 5185 } 5186 sc->tx_dma_map_failures++; 5187 goto maperr; 5188 } 5189 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5190 BUS_DMASYNC_PREWRITE); 5191 /* Make sure there's room in the chain */ 5192 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5193 goto nospace; 5194 5195 /* prod points to an empty tx_bd at this point. */ 5196 prod_bseq = sc->tx_prod_bseq; 5197 #ifdef BNX_DEBUG 5198 debug_prod = chain_prod; 5199 #endif 5200 DBPRINT(sc, BNX_INFO_SEND, 5201 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5202 "prod_bseq = 0x%08X\n", 5203 __func__, prod, chain_prod, prod_bseq); 5204 5205 /* 5206 * Cycle through each mbuf segment that makes up 5207 * the outgoing frame, gathering the mapping info 5208 * for that segment and creating a tx_bd for the 5209 * mbuf. 5210 */ 5211 for (i = 0; i < map->dm_nsegs ; i++) { 5212 chain_prod = TX_CHAIN_IDX(prod); 5213 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5214 5215 addr = (uint32_t)map->dm_segs[i].ds_addr; 5216 txbd->tx_bd_haddr_lo = addr; 5217 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5218 txbd->tx_bd_haddr_hi = addr; 5219 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5220 txbd->tx_bd_vlan_tag = vlan_tag; 5221 txbd->tx_bd_flags = flags; 5222 prod_bseq += map->dm_segs[i].ds_len; 5223 if (i == 0) 5224 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5225 prod = NEXT_TX_BD(prod); 5226 } 5227 5228 /* Set the END flag on the last TX buffer descriptor. */ 5229 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5230 5231 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5232 5233 DBPRINT(sc, BNX_INFO_SEND, 5234 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5235 "prod_bseq = 0x%08X\n", 5236 __func__, prod, chain_prod, prod_bseq); 5237 5238 pkt->pkt_mbuf = m; 5239 pkt->pkt_end_desc = chain_prod; 5240 5241 mutex_enter(&sc->tx_pkt_mtx); 5242 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5243 mutex_exit(&sc->tx_pkt_mtx); 5244 5245 sc->used_tx_bd += map->dm_nsegs; 5246 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5247 __FILE__, __LINE__, sc->used_tx_bd); 5248 5249 /* Update some debug statistics counters */ 5250 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5251 sc->tx_hi_watermark = sc->used_tx_bd); 5252 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5253 DBRUNIF(1, sc->tx_mbuf_alloc++); 5254 5255 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5256 map->dm_nsegs)); 5257 5258 /* prod points to the next free tx_bd at this point. */ 5259 sc->tx_prod = prod; 5260 sc->tx_prod_bseq = prod_bseq; 5261 5262 return 0; 5263 5264 5265 nospace: 5266 bus_dmamap_unload(sc->bnx_dmatag, map); 5267 maperr: 5268 mutex_enter(&sc->tx_pkt_mtx); 5269 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5270 mutex_exit(&sc->tx_pkt_mtx); 5271 5272 return ENOMEM; 5273 } 5274 5275 /****************************************************************************/ 5276 /* Main transmit routine. */ 5277 /* */ 5278 /* Returns: */ 5279 /* Nothing. */ 5280 /****************************************************************************/ 5281 void 5282 bnx_start(struct ifnet *ifp) 5283 { 5284 struct bnx_softc *sc = ifp->if_softc; 5285 struct mbuf *m_head = NULL; 5286 int count = 0; 5287 #ifdef BNX_DEBUG 5288 uint16_t tx_chain_prod; 5289 #endif 5290 5291 /* If there's no link or the transmit queue is empty then just exit. */ 5292 if (!sc->bnx_link 5293 ||(ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) { 5294 DBPRINT(sc, BNX_INFO_SEND, 5295 "%s(): output active or device not running.\n", __func__); 5296 goto bnx_start_exit; 5297 } 5298 5299 /* prod points to the next free tx_bd. */ 5300 #ifdef BNX_DEBUG 5301 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5302 #endif 5303 5304 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5305 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5306 "used_tx %d max_tx %d\n", 5307 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5308 sc->used_tx_bd, sc->max_tx_bd); 5309 5310 /* 5311 * Keep adding entries while there is space in the ring. 5312 */ 5313 while (sc->used_tx_bd < sc->max_tx_bd) { 5314 /* Check for any frames to send. */ 5315 IFQ_POLL(&ifp->if_snd, m_head); 5316 if (m_head == NULL) 5317 break; 5318 5319 /* 5320 * Pack the data into the transmit ring. If we 5321 * don't have room, set the OACTIVE flag to wait 5322 * for the NIC to drain the chain. 5323 */ 5324 if (bnx_tx_encap(sc, m_head)) { 5325 ifp->if_flags |= IFF_OACTIVE; 5326 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5327 "business! Total tx_bd used = %d\n", 5328 sc->used_tx_bd); 5329 break; 5330 } 5331 5332 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5333 count++; 5334 5335 /* Send a copy of the frame to any BPF listeners. */ 5336 bpf_mtap(ifp, m_head, BPF_D_OUT); 5337 } 5338 5339 if (count == 0) { 5340 /* no packets were dequeued */ 5341 DBPRINT(sc, BNX_VERBOSE_SEND, 5342 "%s(): No packets were dequeued\n", __func__); 5343 goto bnx_start_exit; 5344 } 5345 5346 /* Update the driver's counters. */ 5347 #ifdef BNX_DEBUG 5348 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5349 #endif 5350 5351 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5352 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5353 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5354 5355 /* Start the transmit. */ 5356 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5357 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5358 5359 /* Set the tx timeout. */ 5360 ifp->if_timer = BNX_TX_TIMEOUT; 5361 5362 bnx_start_exit: 5363 return; 5364 } 5365 5366 /****************************************************************************/ 5367 /* Handles any IOCTL calls from the operating system. */ 5368 /* */ 5369 /* Returns: */ 5370 /* 0 for success, positive value for failure. */ 5371 /****************************************************************************/ 5372 int 5373 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5374 { 5375 struct bnx_softc *sc = ifp->if_softc; 5376 struct ifreq *ifr = (struct ifreq *) data; 5377 struct mii_data *mii = &sc->bnx_mii; 5378 int s, error = 0; 5379 5380 s = splnet(); 5381 5382 switch (command) { 5383 case SIOCSIFFLAGS: 5384 if ((error = ifioctl_common(ifp, command, data)) != 0) 5385 break; 5386 /* XXX set an ifflags callback and let ether_ioctl 5387 * handle all of this. 5388 */ 5389 if (ISSET(ifp->if_flags, IFF_UP)) { 5390 if (ifp->if_flags & IFF_RUNNING) 5391 error = ENETRESET; 5392 else 5393 bnx_init(ifp); 5394 } else if (ifp->if_flags & IFF_RUNNING) 5395 bnx_stop(ifp, 1); 5396 break; 5397 5398 case SIOCSIFMEDIA: 5399 /* Flow control requires full-duplex mode. */ 5400 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5401 (ifr->ifr_media & IFM_FDX) == 0) 5402 ifr->ifr_media &= ~IFM_ETH_FMASK; 5403 5404 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5405 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5406 /* We can do both TXPAUSE and RXPAUSE. */ 5407 ifr->ifr_media |= 5408 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5409 } 5410 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5411 } 5412 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5413 sc->bnx_phy_flags); 5414 5415 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5416 break; 5417 5418 default: 5419 error = ether_ioctl(ifp, command, data); 5420 } 5421 5422 if (error == ENETRESET) { 5423 if (ifp->if_flags & IFF_RUNNING) 5424 bnx_iff(sc); 5425 error = 0; 5426 } 5427 5428 splx(s); 5429 return error; 5430 } 5431 5432 /****************************************************************************/ 5433 /* Transmit timeout handler. */ 5434 /* */ 5435 /* Returns: */ 5436 /* Nothing. */ 5437 /****************************************************************************/ 5438 void 5439 bnx_watchdog(struct ifnet *ifp) 5440 { 5441 struct bnx_softc *sc = ifp->if_softc; 5442 5443 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5444 bnx_dump_status_block(sc)); 5445 /* 5446 * If we are in this routine because of pause frames, then 5447 * don't reset the hardware. 5448 */ 5449 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5450 return; 5451 5452 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5453 5454 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5455 5456 bnx_init(ifp); 5457 5458 if_statinc(ifp, if_oerrors); 5459 } 5460 5461 /* 5462 * Interrupt handler. 5463 */ 5464 /****************************************************************************/ 5465 /* Main interrupt entry point. Verifies that the controller generated the */ 5466 /* interrupt and then calls a separate routine for handle the various */ 5467 /* interrupt causes (PHY, TX, RX). */ 5468 /* */ 5469 /* Returns: */ 5470 /* 0 for success, positive value for failure. */ 5471 /****************************************************************************/ 5472 int 5473 bnx_intr(void *xsc) 5474 { 5475 struct bnx_softc *sc = xsc; 5476 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5477 uint32_t status_attn_bits; 5478 uint16_t status_idx; 5479 const struct status_block *sblk; 5480 int rv = 0; 5481 5482 if (!device_is_active(sc->bnx_dev) || 5483 (ifp->if_flags & IFF_RUNNING) == 0) 5484 return 0; 5485 5486 DBRUNIF(1, sc->interrupts_generated++); 5487 5488 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5489 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5490 5491 sblk = sc->status_block; 5492 /* 5493 * If the hardware status block index 5494 * matches the last value read by the 5495 * driver and we haven't asserted our 5496 * interrupt then there's nothing to do. 5497 */ 5498 status_idx = sblk->status_idx; 5499 if ((status_idx != sc->last_status_idx) || 5500 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5501 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5502 rv = 1; 5503 5504 /* Ack the interrupt */ 5505 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5506 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5507 5508 status_attn_bits = sblk->status_attn_bits; 5509 5510 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5511 aprint_debug("Simulating unexpected status attention bit set."); 5512 status_attn_bits = status_attn_bits | 5513 STATUS_ATTN_BITS_PARITY_ERROR); 5514 5515 /* Was it a link change interrupt? */ 5516 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5517 (sblk->status_attn_bits_ack & 5518 STATUS_ATTN_BITS_LINK_STATE)) 5519 bnx_phy_intr(sc); 5520 5521 /* If any other attention is asserted then the chip is toast. */ 5522 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5523 (sblk->status_attn_bits_ack & 5524 ~STATUS_ATTN_BITS_LINK_STATE))) { 5525 DBRUN(sc->unexpected_attentions++); 5526 5527 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5528 sblk->status_attn_bits); 5529 5530 DBRUNIF((bnx_debug_unexpected_attention == 0), 5531 bnx_breakpoint(sc)); 5532 5533 bnx_init(ifp); 5534 goto out; 5535 } 5536 5537 /* Check for any completed RX frames. */ 5538 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5539 bnx_rx_intr(sc); 5540 5541 /* Check for any completed TX frames. */ 5542 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5543 bnx_tx_intr(sc); 5544 5545 /* 5546 * Save the status block index value for use during the 5547 * next interrupt. 5548 */ 5549 sc->last_status_idx = status_idx; 5550 5551 /* Start moving packets again */ 5552 if (ifp->if_flags & IFF_RUNNING) 5553 if_schedule_deferred_start(ifp); 5554 } 5555 5556 out: 5557 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5558 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5559 5560 return rv; 5561 } 5562 5563 /****************************************************************************/ 5564 /* Programs the various packet receive modes (broadcast and multicast). */ 5565 /* */ 5566 /* Returns: */ 5567 /* Nothing. */ 5568 /****************************************************************************/ 5569 void 5570 bnx_iff(struct bnx_softc *sc) 5571 { 5572 struct ethercom *ec = &sc->bnx_ec; 5573 struct ifnet *ifp = &ec->ec_if; 5574 struct ether_multi *enm; 5575 struct ether_multistep step; 5576 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5577 uint32_t rx_mode, sort_mode; 5578 int h, i; 5579 5580 /* Initialize receive mode default settings. */ 5581 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5582 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5583 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5584 ifp->if_flags &= ~IFF_ALLMULTI; 5585 5586 /* 5587 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5588 * be enbled. 5589 */ 5590 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5591 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5592 5593 /* 5594 * Check for promiscuous, all multicast, or selected 5595 * multicast address filtering. 5596 */ 5597 if (ifp->if_flags & IFF_PROMISC) { 5598 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5599 5600 ifp->if_flags |= IFF_ALLMULTI; 5601 /* Enable promiscuous mode. */ 5602 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5603 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5604 } else if (ifp->if_flags & IFF_ALLMULTI) { 5605 allmulti: 5606 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5607 5608 ifp->if_flags |= IFF_ALLMULTI; 5609 /* Enable all multicast addresses. */ 5610 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5611 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5612 0xffffffff); 5613 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5614 } else { 5615 /* Accept one or more multicast(s). */ 5616 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5617 5618 ETHER_LOCK(ec); 5619 ETHER_FIRST_MULTI(step, ec, enm); 5620 while (enm != NULL) { 5621 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5622 ETHER_ADDR_LEN)) { 5623 ETHER_UNLOCK(ec); 5624 goto allmulti; 5625 } 5626 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5627 0xFF; 5628 hashes[(h & 0xE0) >> 5] |= __BIT(h & 0x1F); 5629 ETHER_NEXT_MULTI(step, enm); 5630 } 5631 ETHER_UNLOCK(ec); 5632 5633 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5634 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5635 hashes[i]); 5636 5637 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5638 } 5639 5640 /* Only make changes if the receive mode has actually changed. */ 5641 if (rx_mode != sc->rx_mode) { 5642 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5643 rx_mode); 5644 5645 sc->rx_mode = rx_mode; 5646 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5647 } 5648 5649 /* Disable and clear the exisitng sort before enabling a new sort. */ 5650 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5651 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5652 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5653 } 5654 5655 /****************************************************************************/ 5656 /* Called periodically to updates statistics from the controllers */ 5657 /* statistics block. */ 5658 /* */ 5659 /* Returns: */ 5660 /* Nothing. */ 5661 /****************************************************************************/ 5662 void 5663 bnx_stats_update(struct bnx_softc *sc) 5664 { 5665 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5666 struct statistics_block *stats; 5667 5668 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5669 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5670 BUS_DMASYNC_POSTREAD); 5671 5672 stats = (struct statistics_block *)sc->stats_block; 5673 5674 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 5675 uint64_t value; 5676 5677 /* 5678 * Update the interface statistics from the 5679 * hardware statistics. 5680 */ 5681 value = (u_long)stats->stat_EtherStatsCollisions; 5682 if_statadd_ref(nsr, if_collisions, value - sc->if_stat_collisions); 5683 sc->if_stat_collisions = value; 5684 5685 value = (u_long)stats->stat_EtherStatsUndersizePkts + 5686 (u_long)stats->stat_EtherStatsOverrsizePkts + 5687 (u_long)stats->stat_IfInMBUFDiscards + 5688 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5689 (u_long)stats->stat_Dot3StatsFCSErrors; 5690 if_statadd_ref(nsr, if_ierrors, value - sc->if_stat_ierrors); 5691 sc->if_stat_ierrors = value; 5692 5693 value = (u_long) 5694 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5695 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5696 (u_long)stats->stat_Dot3StatsLateCollisions; 5697 if_statadd_ref(nsr, if_oerrors, value - sc->if_stat_oerrors); 5698 sc->if_stat_oerrors = value; 5699 5700 /* 5701 * Certain controllers don't report 5702 * carrier sense errors correctly. 5703 * See errata E11_5708CA0_1165. 5704 */ 5705 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5706 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) { 5707 if_statadd_ref(nsr, if_oerrors, 5708 (u_long) stats->stat_Dot3StatsCarrierSenseErrors); 5709 } 5710 5711 IF_STAT_PUTREF(ifp); 5712 5713 /* 5714 * Update the sysctl statistics from the 5715 * hardware statistics. 5716 */ 5717 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5718 (uint64_t) stats->stat_IfHCInOctets_lo; 5719 5720 sc->stat_IfHCInBadOctets = 5721 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5722 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5723 5724 sc->stat_IfHCOutOctets = 5725 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5726 (uint64_t) stats->stat_IfHCOutOctets_lo; 5727 5728 sc->stat_IfHCOutBadOctets = 5729 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5730 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5731 5732 sc->stat_IfHCInUcastPkts = 5733 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5734 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5735 5736 sc->stat_IfHCInMulticastPkts = 5737 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5738 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5739 5740 sc->stat_IfHCInBroadcastPkts = 5741 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5742 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5743 5744 sc->stat_IfHCOutUcastPkts = 5745 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5746 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5747 5748 sc->stat_IfHCOutMulticastPkts = 5749 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5750 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5751 5752 sc->stat_IfHCOutBroadcastPkts = 5753 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5754 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5755 5756 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5757 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5758 5759 sc->stat_Dot3StatsCarrierSenseErrors = 5760 stats->stat_Dot3StatsCarrierSenseErrors; 5761 5762 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5763 5764 sc->stat_Dot3StatsAlignmentErrors = 5765 stats->stat_Dot3StatsAlignmentErrors; 5766 5767 sc->stat_Dot3StatsSingleCollisionFrames = 5768 stats->stat_Dot3StatsSingleCollisionFrames; 5769 5770 sc->stat_Dot3StatsMultipleCollisionFrames = 5771 stats->stat_Dot3StatsMultipleCollisionFrames; 5772 5773 sc->stat_Dot3StatsDeferredTransmissions = 5774 stats->stat_Dot3StatsDeferredTransmissions; 5775 5776 sc->stat_Dot3StatsExcessiveCollisions = 5777 stats->stat_Dot3StatsExcessiveCollisions; 5778 5779 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5780 5781 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5782 5783 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5784 5785 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5786 5787 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5788 5789 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5790 5791 sc->stat_EtherStatsPktsRx64Octets = 5792 stats->stat_EtherStatsPktsRx64Octets; 5793 5794 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5795 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5796 5797 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5798 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5799 5800 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5801 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5802 5803 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5804 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5805 5806 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5807 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5808 5809 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5810 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5811 5812 sc->stat_EtherStatsPktsTx64Octets = 5813 stats->stat_EtherStatsPktsTx64Octets; 5814 5815 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5816 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5817 5818 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5819 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5820 5821 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5822 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5823 5824 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5825 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5826 5827 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5828 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5829 5830 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5831 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5832 5833 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5834 5835 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5836 5837 sc->stat_OutXonSent = stats->stat_OutXonSent; 5838 5839 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5840 5841 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5842 5843 sc->stat_MacControlFramesReceived = 5844 stats->stat_MacControlFramesReceived; 5845 5846 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5847 5848 sc->stat_IfInFramesL2FilterDiscards = 5849 stats->stat_IfInFramesL2FilterDiscards; 5850 5851 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5852 5853 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5854 5855 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5856 5857 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5858 5859 sc->stat_CatchupInRuleCheckerDiscards = 5860 stats->stat_CatchupInRuleCheckerDiscards; 5861 5862 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5863 5864 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5865 5866 sc->stat_CatchupInRuleCheckerP4Hit = 5867 stats->stat_CatchupInRuleCheckerP4Hit; 5868 5869 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5870 } 5871 5872 void 5873 bnx_tick(void *xsc) 5874 { 5875 struct bnx_softc *sc = xsc; 5876 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5877 struct mii_data *mii; 5878 uint32_t msg; 5879 uint16_t prod, chain_prod; 5880 uint32_t prod_bseq; 5881 int s = splnet(); 5882 5883 /* Tell the firmware that the driver is still running. */ 5884 #ifdef BNX_DEBUG 5885 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5886 #else 5887 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5888 #endif 5889 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5890 5891 /* Update the statistics from the hardware statistics block. */ 5892 bnx_stats_update(sc); 5893 5894 /* Schedule the next tick. */ 5895 if (!sc->bnx_detaching) 5896 callout_schedule(&sc->bnx_timeout, hz); 5897 5898 if (sc->bnx_link) 5899 goto bnx_tick_exit; 5900 5901 mii = &sc->bnx_mii; 5902 mii_tick(mii); 5903 5904 /* Check if the link has come up. */ 5905 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5906 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5907 sc->bnx_link++; 5908 /* Now that link is up, handle any outstanding TX traffic. */ 5909 if_schedule_deferred_start(ifp); 5910 } 5911 5912 bnx_tick_exit: 5913 /* try to get more RX buffers, just in case */ 5914 prod = sc->rx_prod; 5915 prod_bseq = sc->rx_prod_bseq; 5916 chain_prod = RX_CHAIN_IDX(prod); 5917 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5918 sc->rx_prod = prod; 5919 sc->rx_prod_bseq = prod_bseq; 5920 5921 splx(s); 5922 return; 5923 } 5924 5925 /****************************************************************************/ 5926 /* BNX Debug Routines */ 5927 /****************************************************************************/ 5928 #ifdef BNX_DEBUG 5929 5930 /****************************************************************************/ 5931 /* Prints out information about an mbuf. */ 5932 /* */ 5933 /* Returns: */ 5934 /* Nothing. */ 5935 /****************************************************************************/ 5936 void 5937 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5938 { 5939 struct mbuf *mp = m; 5940 5941 if (m == NULL) { 5942 /* Index out of range. */ 5943 aprint_error("mbuf ptr is null!\n"); 5944 return; 5945 } 5946 5947 while (mp) { 5948 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5949 mp, mp->m_len); 5950 5951 if (mp->m_flags & M_EXT) 5952 aprint_debug("M_EXT "); 5953 if (mp->m_flags & M_PKTHDR) 5954 aprint_debug("M_PKTHDR "); 5955 aprint_debug("\n"); 5956 5957 if (mp->m_flags & M_EXT) 5958 aprint_debug("- m_ext: vaddr = %p, " 5959 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5960 5961 mp = mp->m_next; 5962 } 5963 } 5964 5965 /****************************************************************************/ 5966 /* Prints out the mbufs in the TX mbuf chain. */ 5967 /* */ 5968 /* Returns: */ 5969 /* Nothing. */ 5970 /****************************************************************************/ 5971 void 5972 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5973 { 5974 #if 0 5975 struct mbuf *m; 5976 int i; 5977 5978 aprint_debug_dev(sc->bnx_dev, 5979 "----------------------------" 5980 " tx mbuf data " 5981 "----------------------------\n"); 5982 5983 for (i = 0; i < count; i++) { 5984 m = sc->tx_mbuf_ptr[chain_prod]; 5985 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5986 bnx_dump_mbuf(sc, m); 5987 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5988 } 5989 5990 aprint_debug_dev(sc->bnx_dev, 5991 "--------------------------------------------" 5992 "----------------------------\n"); 5993 #endif 5994 } 5995 5996 /* 5997 * This routine prints the RX mbuf chain. 5998 */ 5999 void 6000 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 6001 { 6002 struct mbuf *m; 6003 int i; 6004 6005 aprint_debug_dev(sc->bnx_dev, 6006 "----------------------------" 6007 " rx mbuf data " 6008 "----------------------------\n"); 6009 6010 for (i = 0; i < count; i++) { 6011 m = sc->rx_mbuf_ptr[chain_prod]; 6012 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6013 bnx_dump_mbuf(sc, m); 6014 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6015 } 6016 6017 6018 aprint_debug_dev(sc->bnx_dev, 6019 "--------------------------------------------" 6020 "----------------------------\n"); 6021 } 6022 6023 void 6024 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 6025 { 6026 if (idx > MAX_TX_BD) 6027 /* Index out of range. */ 6028 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6029 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6030 /* TX Chain page pointer. */ 6031 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 6032 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 6033 txbd->tx_bd_haddr_lo); 6034 else 6035 /* Normal tx_bd entry. */ 6036 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6037 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 6038 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6039 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6040 txbd->tx_bd_flags); 6041 } 6042 6043 void 6044 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 6045 { 6046 if (idx > MAX_RX_BD) 6047 /* Index out of range. */ 6048 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6049 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6050 /* TX Chain page pointer. */ 6051 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 6052 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 6053 rxbd->rx_bd_haddr_lo); 6054 else 6055 /* Normal tx_bd entry. */ 6056 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6057 "0x%08X, flags = 0x%08X\n", idx, 6058 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6059 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6060 } 6061 6062 void 6063 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6064 { 6065 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6066 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6067 "tcp_udp_xsum = 0x%04X\n", idx, 6068 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6069 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6070 l2fhdr->l2_fhdr_tcp_udp_xsum); 6071 } 6072 6073 /* 6074 * This routine prints the TX chain. 6075 */ 6076 void 6077 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 6078 { 6079 struct tx_bd *txbd; 6080 int i; 6081 6082 /* First some info about the tx_bd chain structure. */ 6083 aprint_debug_dev(sc->bnx_dev, 6084 "----------------------------" 6085 " tx_bd chain " 6086 "----------------------------\n"); 6087 6088 BNX_PRINTF(sc, 6089 "page size = 0x%08X, tx chain pages = 0x%08X\n", 6090 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6091 6092 BNX_PRINTF(sc, 6093 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6094 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6095 6096 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6097 6098 aprint_error_dev(sc->bnx_dev, "" 6099 "-----------------------------" 6100 " tx_bd data " 6101 "-----------------------------\n"); 6102 6103 /* Now print out the tx_bd's themselves. */ 6104 for (i = 0; i < count; i++) { 6105 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6106 bnx_dump_txbd(sc, tx_prod, txbd); 6107 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6108 } 6109 6110 aprint_debug_dev(sc->bnx_dev, 6111 "-----------------------------" 6112 "--------------" 6113 "-----------------------------\n"); 6114 } 6115 6116 /* 6117 * This routine prints the RX chain. 6118 */ 6119 void 6120 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6121 { 6122 struct rx_bd *rxbd; 6123 int i; 6124 6125 /* First some info about the tx_bd chain structure. */ 6126 aprint_debug_dev(sc->bnx_dev, 6127 "----------------------------" 6128 " rx_bd chain " 6129 "----------------------------\n"); 6130 6131 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6132 6133 BNX_PRINTF(sc, 6134 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6135 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6136 6137 BNX_PRINTF(sc, 6138 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6139 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6140 6141 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6142 6143 aprint_error_dev(sc->bnx_dev, 6144 "----------------------------" 6145 " rx_bd data " 6146 "----------------------------\n"); 6147 6148 /* Now print out the rx_bd's themselves. */ 6149 for (i = 0; i < count; i++) { 6150 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6151 bnx_dump_rxbd(sc, rx_prod, rxbd); 6152 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6153 } 6154 6155 aprint_debug_dev(sc->bnx_dev, 6156 "----------------------------" 6157 "--------------" 6158 "----------------------------\n"); 6159 } 6160 6161 /* 6162 * This routine prints the status block. 6163 */ 6164 void 6165 bnx_dump_status_block(struct bnx_softc *sc) 6166 { 6167 struct status_block *sblk; 6168 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6169 BUS_DMASYNC_POSTREAD); 6170 6171 sblk = sc->status_block; 6172 6173 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6174 "Status Block -----------------------------\n"); 6175 6176 BNX_PRINTF(sc, 6177 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6178 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6179 sblk->status_idx); 6180 6181 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6182 sblk->status_rx_quick_consumer_index0, 6183 sblk->status_tx_quick_consumer_index0); 6184 6185 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6186 6187 /* Theses indices are not used for normal L2 drivers. */ 6188 if (sblk->status_rx_quick_consumer_index1 || 6189 sblk->status_tx_quick_consumer_index1) 6190 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6191 sblk->status_rx_quick_consumer_index1, 6192 sblk->status_tx_quick_consumer_index1); 6193 6194 if (sblk->status_rx_quick_consumer_index2 || 6195 sblk->status_tx_quick_consumer_index2) 6196 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6197 sblk->status_rx_quick_consumer_index2, 6198 sblk->status_tx_quick_consumer_index2); 6199 6200 if (sblk->status_rx_quick_consumer_index3 || 6201 sblk->status_tx_quick_consumer_index3) 6202 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6203 sblk->status_rx_quick_consumer_index3, 6204 sblk->status_tx_quick_consumer_index3); 6205 6206 if (sblk->status_rx_quick_consumer_index4 || 6207 sblk->status_rx_quick_consumer_index5) 6208 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6209 sblk->status_rx_quick_consumer_index4, 6210 sblk->status_rx_quick_consumer_index5); 6211 6212 if (sblk->status_rx_quick_consumer_index6 || 6213 sblk->status_rx_quick_consumer_index7) 6214 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6215 sblk->status_rx_quick_consumer_index6, 6216 sblk->status_rx_quick_consumer_index7); 6217 6218 if (sblk->status_rx_quick_consumer_index8 || 6219 sblk->status_rx_quick_consumer_index9) 6220 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6221 sblk->status_rx_quick_consumer_index8, 6222 sblk->status_rx_quick_consumer_index9); 6223 6224 if (sblk->status_rx_quick_consumer_index10 || 6225 sblk->status_rx_quick_consumer_index11) 6226 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6227 sblk->status_rx_quick_consumer_index10, 6228 sblk->status_rx_quick_consumer_index11); 6229 6230 if (sblk->status_rx_quick_consumer_index12 || 6231 sblk->status_rx_quick_consumer_index13) 6232 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6233 sblk->status_rx_quick_consumer_index12, 6234 sblk->status_rx_quick_consumer_index13); 6235 6236 if (sblk->status_rx_quick_consumer_index14 || 6237 sblk->status_rx_quick_consumer_index15) 6238 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6239 sblk->status_rx_quick_consumer_index14, 6240 sblk->status_rx_quick_consumer_index15); 6241 6242 if (sblk->status_completion_producer_index || 6243 sblk->status_cmd_consumer_index) 6244 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6245 sblk->status_completion_producer_index, 6246 sblk->status_cmd_consumer_index); 6247 6248 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6249 "-----------------------------\n"); 6250 } 6251 6252 /* 6253 * This routine prints the statistics block. 6254 */ 6255 void 6256 bnx_dump_stats_block(struct bnx_softc *sc) 6257 { 6258 struct statistics_block *sblk; 6259 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6260 BUS_DMASYNC_POSTREAD); 6261 6262 sblk = sc->stats_block; 6263 6264 aprint_debug_dev(sc->bnx_dev, "" 6265 "-----------------------------" 6266 " Stats Block " 6267 "-----------------------------\n"); 6268 6269 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6270 "IfHcInBadOctets = 0x%08X:%08X\n", 6271 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6272 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6273 6274 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6275 "IfHcOutBadOctets = 0x%08X:%08X\n", 6276 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6277 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6278 6279 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6280 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6281 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6282 sblk->stat_IfHCInMulticastPkts_hi, 6283 sblk->stat_IfHCInMulticastPkts_lo); 6284 6285 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6286 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6287 sblk->stat_IfHCInBroadcastPkts_hi, 6288 sblk->stat_IfHCInBroadcastPkts_lo, 6289 sblk->stat_IfHCOutUcastPkts_hi, 6290 sblk->stat_IfHCOutUcastPkts_lo); 6291 6292 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6293 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6294 sblk->stat_IfHCOutMulticastPkts_hi, 6295 sblk->stat_IfHCOutMulticastPkts_lo, 6296 sblk->stat_IfHCOutBroadcastPkts_hi, 6297 sblk->stat_IfHCOutBroadcastPkts_lo); 6298 6299 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6300 BNX_PRINTF(sc, "0x%08X : " 6301 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6302 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6303 6304 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6305 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6306 sblk->stat_Dot3StatsCarrierSenseErrors); 6307 6308 if (sblk->stat_Dot3StatsFCSErrors) 6309 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6310 sblk->stat_Dot3StatsFCSErrors); 6311 6312 if (sblk->stat_Dot3StatsAlignmentErrors) 6313 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6314 sblk->stat_Dot3StatsAlignmentErrors); 6315 6316 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6317 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6318 sblk->stat_Dot3StatsSingleCollisionFrames); 6319 6320 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6321 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6322 sblk->stat_Dot3StatsMultipleCollisionFrames); 6323 6324 if (sblk->stat_Dot3StatsDeferredTransmissions) 6325 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6326 sblk->stat_Dot3StatsDeferredTransmissions); 6327 6328 if (sblk->stat_Dot3StatsExcessiveCollisions) 6329 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6330 sblk->stat_Dot3StatsExcessiveCollisions); 6331 6332 if (sblk->stat_Dot3StatsLateCollisions) 6333 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6334 sblk->stat_Dot3StatsLateCollisions); 6335 6336 if (sblk->stat_EtherStatsCollisions) 6337 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6338 sblk->stat_EtherStatsCollisions); 6339 6340 if (sblk->stat_EtherStatsFragments) 6341 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6342 sblk->stat_EtherStatsFragments); 6343 6344 if (sblk->stat_EtherStatsJabbers) 6345 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6346 sblk->stat_EtherStatsJabbers); 6347 6348 if (sblk->stat_EtherStatsUndersizePkts) 6349 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6350 sblk->stat_EtherStatsUndersizePkts); 6351 6352 if (sblk->stat_EtherStatsOverrsizePkts) 6353 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6354 sblk->stat_EtherStatsOverrsizePkts); 6355 6356 if (sblk->stat_EtherStatsPktsRx64Octets) 6357 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6358 sblk->stat_EtherStatsPktsRx64Octets); 6359 6360 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6361 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6362 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6363 6364 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6365 BNX_PRINTF(sc, "0x%08X : " 6366 "EtherStatsPktsRx128Octetsto255Octets\n", 6367 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6368 6369 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6370 BNX_PRINTF(sc, "0x%08X : " 6371 "EtherStatsPktsRx256Octetsto511Octets\n", 6372 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6373 6374 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6375 BNX_PRINTF(sc, "0x%08X : " 6376 "EtherStatsPktsRx512Octetsto1023Octets\n", 6377 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6378 6379 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6380 BNX_PRINTF(sc, "0x%08X : " 6381 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6382 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6383 6384 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6385 BNX_PRINTF(sc, "0x%08X : " 6386 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6387 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6388 6389 if (sblk->stat_EtherStatsPktsTx64Octets) 6390 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6391 sblk->stat_EtherStatsPktsTx64Octets); 6392 6393 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6394 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6395 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6396 6397 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6398 BNX_PRINTF(sc, "0x%08X : " 6399 "EtherStatsPktsTx128Octetsto255Octets\n", 6400 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6401 6402 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6403 BNX_PRINTF(sc, "0x%08X : " 6404 "EtherStatsPktsTx256Octetsto511Octets\n", 6405 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6406 6407 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6408 BNX_PRINTF(sc, "0x%08X : " 6409 "EtherStatsPktsTx512Octetsto1023Octets\n", 6410 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6411 6412 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6413 BNX_PRINTF(sc, "0x%08X : " 6414 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6415 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6416 6417 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6418 BNX_PRINTF(sc, "0x%08X : " 6419 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6420 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6421 6422 if (sblk->stat_XonPauseFramesReceived) 6423 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6424 sblk->stat_XonPauseFramesReceived); 6425 6426 if (sblk->stat_XoffPauseFramesReceived) 6427 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6428 sblk->stat_XoffPauseFramesReceived); 6429 6430 if (sblk->stat_OutXonSent) 6431 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6432 sblk->stat_OutXonSent); 6433 6434 if (sblk->stat_OutXoffSent) 6435 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6436 sblk->stat_OutXoffSent); 6437 6438 if (sblk->stat_FlowControlDone) 6439 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6440 sblk->stat_FlowControlDone); 6441 6442 if (sblk->stat_MacControlFramesReceived) 6443 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6444 sblk->stat_MacControlFramesReceived); 6445 6446 if (sblk->stat_XoffStateEntered) 6447 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6448 sblk->stat_XoffStateEntered); 6449 6450 if (sblk->stat_IfInFramesL2FilterDiscards) 6451 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6452 sblk->stat_IfInFramesL2FilterDiscards); 6453 6454 if (sblk->stat_IfInRuleCheckerDiscards) 6455 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6456 sblk->stat_IfInRuleCheckerDiscards); 6457 6458 if (sblk->stat_IfInFTQDiscards) 6459 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6460 sblk->stat_IfInFTQDiscards); 6461 6462 if (sblk->stat_IfInMBUFDiscards) 6463 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6464 sblk->stat_IfInMBUFDiscards); 6465 6466 if (sblk->stat_IfInRuleCheckerP4Hit) 6467 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6468 sblk->stat_IfInRuleCheckerP4Hit); 6469 6470 if (sblk->stat_CatchupInRuleCheckerDiscards) 6471 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6472 sblk->stat_CatchupInRuleCheckerDiscards); 6473 6474 if (sblk->stat_CatchupInFTQDiscards) 6475 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6476 sblk->stat_CatchupInFTQDiscards); 6477 6478 if (sblk->stat_CatchupInMBUFDiscards) 6479 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6480 sblk->stat_CatchupInMBUFDiscards); 6481 6482 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6483 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6484 sblk->stat_CatchupInRuleCheckerP4Hit); 6485 6486 aprint_debug_dev(sc->bnx_dev, 6487 "-----------------------------" 6488 "--------------" 6489 "-----------------------------\n"); 6490 } 6491 6492 void 6493 bnx_dump_driver_state(struct bnx_softc *sc) 6494 { 6495 aprint_debug_dev(sc->bnx_dev, 6496 "-----------------------------" 6497 " Driver State " 6498 "-----------------------------\n"); 6499 6500 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6501 "address\n", sc); 6502 6503 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6504 sc->status_block); 6505 6506 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6507 "address\n", sc->stats_block); 6508 6509 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6510 "address\n", sc->tx_bd_chain); 6511 6512 #if 0 6513 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6514 sc->rx_bd_chain); 6515 6516 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6517 sc->tx_mbuf_ptr); 6518 #endif 6519 6520 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6521 sc->rx_mbuf_ptr); 6522 6523 BNX_PRINTF(sc, 6524 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6525 sc->interrupts_generated); 6526 6527 BNX_PRINTF(sc, 6528 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6529 sc->rx_interrupts); 6530 6531 BNX_PRINTF(sc, 6532 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6533 sc->tx_interrupts); 6534 6535 BNX_PRINTF(sc, 6536 " 0x%08X - (sc->last_status_idx) status block index\n", 6537 sc->last_status_idx); 6538 6539 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6540 sc->tx_prod); 6541 6542 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6543 sc->tx_cons); 6544 6545 BNX_PRINTF(sc, 6546 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6547 sc->tx_prod_bseq); 6548 BNX_PRINTF(sc, 6549 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6550 sc->tx_mbuf_alloc); 6551 6552 BNX_PRINTF(sc, 6553 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6554 sc->used_tx_bd); 6555 6556 BNX_PRINTF(sc, 6557 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6558 sc->tx_hi_watermark, sc->max_tx_bd); 6559 6560 6561 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6562 sc->rx_prod); 6563 6564 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6565 sc->rx_cons); 6566 6567 BNX_PRINTF(sc, 6568 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6569 sc->rx_prod_bseq); 6570 6571 BNX_PRINTF(sc, 6572 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6573 sc->rx_mbuf_alloc); 6574 6575 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6576 sc->free_rx_bd); 6577 6578 BNX_PRINTF(sc, 6579 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6580 sc->rx_low_watermark, sc->max_rx_bd); 6581 6582 BNX_PRINTF(sc, 6583 " 0x%08X - (sc->mbuf_alloc_failed) " 6584 "mbuf alloc failures\n", 6585 sc->mbuf_alloc_failed); 6586 6587 BNX_PRINTF(sc, 6588 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6589 "simulated mbuf alloc failures\n", 6590 sc->mbuf_sim_alloc_failed); 6591 6592 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6593 "-----------------------------\n"); 6594 } 6595 6596 void 6597 bnx_dump_hw_state(struct bnx_softc *sc) 6598 { 6599 uint32_t val1; 6600 int i; 6601 6602 aprint_debug_dev(sc->bnx_dev, 6603 "----------------------------" 6604 " Hardware State " 6605 "----------------------------\n"); 6606 6607 val1 = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 6608 BNX_PRINTF(sc, "0x%08X : bootcode version\n", val1); 6609 6610 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6611 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6612 val1, BNX_MISC_ENABLE_STATUS_BITS); 6613 6614 val1 = REG_RD(sc, BNX_DMA_STATUS); 6615 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6616 6617 val1 = REG_RD(sc, BNX_CTX_STATUS); 6618 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6619 6620 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6621 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6622 BNX_EMAC_STATUS); 6623 6624 val1 = REG_RD(sc, BNX_RPM_STATUS); 6625 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6626 6627 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6628 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6629 BNX_TBDR_STATUS); 6630 6631 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6632 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6633 BNX_TDMA_STATUS); 6634 6635 val1 = REG_RD(sc, BNX_HC_STATUS); 6636 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6637 6638 aprint_debug_dev(sc->bnx_dev, 6639 "----------------------------" 6640 "----------------" 6641 "----------------------------\n"); 6642 6643 aprint_debug_dev(sc->bnx_dev, 6644 "----------------------------" 6645 " Register Dump " 6646 "----------------------------\n"); 6647 6648 for (i = 0x400; i < 0x8000; i += 0x10) 6649 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6650 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6651 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6652 6653 aprint_debug_dev(sc->bnx_dev, 6654 "----------------------------" 6655 "----------------" 6656 "----------------------------\n"); 6657 } 6658 6659 void 6660 bnx_breakpoint(struct bnx_softc *sc) 6661 { 6662 /* Unreachable code to shut the compiler up about unused functions. */ 6663 if (0) { 6664 bnx_dump_txbd(sc, 0, NULL); 6665 bnx_dump_rxbd(sc, 0, NULL); 6666 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6667 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6668 bnx_dump_l2fhdr(sc, 0, NULL); 6669 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6670 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6671 bnx_dump_status_block(sc); 6672 bnx_dump_stats_block(sc); 6673 bnx_dump_driver_state(sc); 6674 bnx_dump_hw_state(sc); 6675 } 6676 6677 bnx_dump_driver_state(sc); 6678 /* Print the important status block fields. */ 6679 bnx_dump_status_block(sc); 6680 6681 #if 0 6682 /* Call the debugger. */ 6683 breakpoint(); 6684 #endif 6685 6686 return; 6687 } 6688 #endif 6689
Indexes created Thu Sep 25 16:09:42 GMT 2025