if_bnx.c revision 1.106
1 /* $NetBSD: if_bnx.c,v 1.106 2021/02/13 01:51:24 jakllsch Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.106 2021/02/13 01:51:24 jakllsch Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 device_t dev = sc->bnx_dev; 466 int i = 0; 467 468 aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 469 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 470 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 471 ? "Serdes " : "", sc->bnx_chipid); 472 473 /* Bus info. */ 474 if (sc->bnx_flags & BNX_PCIE_FLAG) { 475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); 476 switch (sc->link_speed) { 477 case 1: aprint_normal("2.5GT/s\n"); break; 478 case 2: aprint_normal("5GT/s\n"); break; 479 default: aprint_normal("Unknown link speed\n"); 480 } 481 } else { 482 aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n", 483 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 484 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 485 sc->bus_speed_mhz); 486 } 487 488 /* Firmware version and device features. */ 489 aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (", 490 sc->bnx_bc_ver, RX_PAGES, TX_PAGES); 491 492 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) { 493 if (i > 0) aprint_normal("|"); 494 aprint_normal("2.5G"); i++; 495 } 496 497 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 498 if (i > 0) aprint_normal("|"); 499 aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver); 500 } else { 501 aprint_normal(")\n"); 502 } 503 504 aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 505 sc->bnx_rx_quick_cons_trip_int, 506 sc->bnx_rx_quick_cons_trip, 507 sc->bnx_rx_ticks_int, 508 sc->bnx_rx_ticks, 509 sc->bnx_tx_quick_cons_trip_int, 510 sc->bnx_tx_quick_cons_trip, 511 sc->bnx_tx_ticks_int, 512 sc->bnx_tx_ticks); 513 } 514 515 516 /****************************************************************************/ 517 /* PCI Capabilities Probe Function. */ 518 /* */ 519 /* Walks the PCI capabiites list for the device to find what features are */ 520 /* supported. */ 521 /* */ 522 /* Returns: */ 523 /* None. */ 524 /****************************************************************************/ 525 static void 526 bnx_probe_pci_caps(struct bnx_softc *sc) 527 { 528 struct pci_attach_args *pa = &(sc->bnx_pa); 529 pcireg_t reg; 530 531 /* Check if PCI-X capability is enabled. */ 532 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 533 NULL) != 0) { 534 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 535 } 536 537 /* Check if PCIe capability is enabled. */ 538 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 539 NULL) != 0) { 540 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 541 reg + PCIE_LCSR); 542 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 543 "0x%08X\n", link_status); 544 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 546 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 547 sc->bnx_flags |= BNX_PCIE_FLAG; 548 } 549 550 /* Check if MSI capability is enabled. */ 551 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 552 NULL) != 0) 553 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 554 555 /* Check if MSI-X capability is enabled. */ 556 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 557 NULL) != 0) 558 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 559 } 560 561 562 /****************************************************************************/ 563 /* Device attach function. */ 564 /* */ 565 /* Allocates device resources, performs secondary chip identification, */ 566 /* resets and initializes the hardware, and initializes driver instance */ 567 /* variables. */ 568 /* */ 569 /* Returns: */ 570 /* 0 on success, positive value on failure. */ 571 /****************************************************************************/ 572 void 573 bnx_attach(device_t parent, device_t self, void *aux) 574 { 575 const struct bnx_product *bp; 576 struct bnx_softc *sc = device_private(self); 577 prop_dictionary_t dict; 578 struct pci_attach_args *pa = aux; 579 pci_chipset_tag_t pc = pa->pa_pc; 580 const char *intrstr = NULL; 581 uint32_t command; 582 struct ifnet *ifp; 583 struct mii_data * const mii = &sc->bnx_mii; 584 uint32_t val; 585 int mii_flags = MIIF_FORCEANEG; 586 pcireg_t memtype; 587 char intrbuf[PCI_INTRSTR_LEN]; 588 int i, j; 589 590 if (bnx_tx_pool == NULL) { 591 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_WAITOK); 592 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 593 0, 0, 0, "bnxpkts", NULL, IPL_NET); 594 } 595 596 bp = bnx_lookup(pa); 597 if (bp == NULL) 598 panic("unknown device"); 599 600 sc->bnx_dev = self; 601 602 aprint_naive("\n"); 603 aprint_normal(": %s\n", bp->bp_name); 604 605 sc->bnx_pa = *pa; 606 607 /* 608 * Map control/status registers. 609 */ 610 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 611 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 612 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 613 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 614 615 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 616 aprint_error_dev(sc->bnx_dev, 617 "failed to enable memory mapping!\n"); 618 return; 619 } 620 621 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 622 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 623 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 624 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 625 return; 626 } 627 628 /* XXX driver needs more work before MSI or MSI-X can be enabled */ 629 int counts[PCI_INTR_TYPE_SIZE] = { 630 [PCI_INTR_TYPE_INTX] = 1, 631 [PCI_INTR_TYPE_MSI] = 0, 632 [PCI_INTR_TYPE_MSIX] = 0, 633 }; 634 if (pci_intr_alloc(pa, &sc->bnx_ih, counts, PCI_INTR_TYPE_INTX)) { 635 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 636 goto bnx_attach_fail; 637 } 638 intrstr = pci_intr_string(pc, sc->bnx_ih[0], intrbuf, sizeof(intrbuf)); 639 640 /* 641 * Configure byte swap and enable indirect register access. 642 * Rely on CPU to do target byte swapping on big endian systems. 643 * Access to registers outside of PCI configurtion space are not 644 * valid until this is done. 645 */ 646 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 647 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 648 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 649 650 /* Save ASIC revision info. */ 651 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 652 653 /* 654 * Find the base address for shared memory access. 655 * Newer versions of bootcode use a signature and offset 656 * while older versions use a fixed address. 657 */ 658 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 659 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 660 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 661 (sc->bnx_pa.pa_function << 2)); 662 else 663 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 664 665 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 666 667 /* Set initial device and PHY flags */ 668 sc->bnx_flags = 0; 669 sc->bnx_phy_flags = 0; 670 671 /* Fetch the bootcode revision. */ 672 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 673 for (i = 0, j = 0; i < 3; i++) { 674 uint8_t num; 675 int k, skip0; 676 677 num = (uint8_t)(val >> (24 - (i * 8))); 678 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 679 if (num >= k || !skip0 || k == 1) { 680 sc->bnx_bc_ver[j++] = (num / k) + '0'; 681 skip0 = 0; 682 } 683 } 684 if (i != 2) 685 sc->bnx_bc_ver[j++] = '.'; 686 } 687 688 /* Check if any management firmware is enabled. */ 689 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 690 if (val & BNX_PORT_FEATURE_ASF_ENABLED) { 691 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 692 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 693 694 /* Allow time for firmware to enter the running state. */ 695 for (i = 0; i < 30; i++) { 696 val = REG_RD_IND(sc, sc->bnx_shmem_base + 697 BNX_BC_STATE_CONDITION); 698 if (val & BNX_CONDITION_MFW_RUN_MASK) 699 break; 700 DELAY(10000); 701 } 702 703 /* Check if management firmware is running. */ 704 val = REG_RD_IND(sc, sc->bnx_shmem_base + 705 BNX_BC_STATE_CONDITION); 706 val &= BNX_CONDITION_MFW_RUN_MASK; 707 if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) && 708 (val != BNX_CONDITION_MFW_RUN_NONE)) { 709 uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base + 710 BNX_MFW_VER_PTR); 711 712 /* Read the management firmware version string. */ 713 for (j = 0; j < 3; j++) { 714 val = bnx_reg_rd_ind(sc, addr + j * 4); 715 val = bswap32(val); 716 memcpy(&sc->bnx_mfw_ver[i], &val, 4); 717 i += 4; 718 } 719 } else { 720 /* May cause firmware synchronization timeouts. */ 721 BNX_PRINTF(sc, "%s(%d): Management firmware enabled " 722 "but not running!\n", __FILE__, __LINE__); 723 strcpy(sc->bnx_mfw_ver, "NOT RUNNING!"); 724 725 /* ToDo: Any action the driver should take? */ 726 } 727 } 728 729 bnx_probe_pci_caps(sc); 730 731 /* Get PCI bus information (speed and type). */ 732 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 733 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 734 uint32_t clkreg; 735 736 sc->bnx_flags |= BNX_PCIX_FLAG; 737 738 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 739 740 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 741 switch (clkreg) { 742 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 743 sc->bus_speed_mhz = 133; 744 break; 745 746 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 747 sc->bus_speed_mhz = 100; 748 break; 749 750 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 751 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 752 sc->bus_speed_mhz = 66; 753 break; 754 755 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 756 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 757 sc->bus_speed_mhz = 50; 758 break; 759 760 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 761 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 762 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 763 sc->bus_speed_mhz = 33; 764 break; 765 } 766 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 767 sc->bus_speed_mhz = 66; 768 else 769 sc->bus_speed_mhz = 33; 770 771 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 772 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 773 774 /* Reset the controller. */ 775 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 776 goto bnx_attach_fail; 777 778 /* Initialize the controller. */ 779 if (bnx_chipinit(sc)) { 780 aprint_error_dev(sc->bnx_dev, 781 "Controller initialization failed!\n"); 782 goto bnx_attach_fail; 783 } 784 785 /* Perform NVRAM test. */ 786 if (bnx_nvram_test(sc)) { 787 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 788 goto bnx_attach_fail; 789 } 790 791 /* Fetch the permanent Ethernet MAC address. */ 792 bnx_get_mac_addr(sc); 793 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 794 ether_sprintf(sc->eaddr)); 795 796 /* 797 * Trip points control how many BDs 798 * should be ready before generating an 799 * interrupt while ticks control how long 800 * a BD can sit in the chain before 801 * generating an interrupt. Set the default 802 * values for the RX and TX rings. 803 */ 804 805 #ifdef BNX_DEBUG 806 /* Force more frequent interrupts. */ 807 sc->bnx_tx_quick_cons_trip_int = 1; 808 sc->bnx_tx_quick_cons_trip = 1; 809 sc->bnx_tx_ticks_int = 0; 810 sc->bnx_tx_ticks = 0; 811 812 sc->bnx_rx_quick_cons_trip_int = 1; 813 sc->bnx_rx_quick_cons_trip = 1; 814 sc->bnx_rx_ticks_int = 0; 815 sc->bnx_rx_ticks = 0; 816 #else 817 sc->bnx_tx_quick_cons_trip_int = 20; 818 sc->bnx_tx_quick_cons_trip = 20; 819 sc->bnx_tx_ticks_int = 80; 820 sc->bnx_tx_ticks = 80; 821 822 sc->bnx_rx_quick_cons_trip_int = 6; 823 sc->bnx_rx_quick_cons_trip = 6; 824 sc->bnx_rx_ticks_int = 18; 825 sc->bnx_rx_ticks = 18; 826 #endif 827 828 /* Update statistics once every second. */ 829 sc->bnx_stats_ticks = 1000000 & 0xffff00; 830 831 /* Find the media type for the adapter. */ 832 bnx_get_media(sc); 833 834 /* 835 * Store config data needed by the PHY driver for 836 * backplane applications 837 */ 838 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 839 BNX_SHARED_HW_CFG_CONFIG); 840 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 841 BNX_PORT_HW_CFG_CONFIG); 842 843 /* Allocate DMA memory resources. */ 844 sc->bnx_dmatag = pa->pa_dmat; 845 if (bnx_dma_alloc(sc)) { 846 aprint_error_dev(sc->bnx_dev, 847 "DMA resource allocation failed!\n"); 848 goto bnx_attach_fail; 849 } 850 851 /* Initialize the ifnet interface. */ 852 ifp = &sc->bnx_ec.ec_if; 853 ifp->if_softc = sc; 854 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 855 ifp->if_ioctl = bnx_ioctl; 856 ifp->if_stop = bnx_stop; 857 ifp->if_start = bnx_start; 858 ifp->if_init = bnx_init; 859 ifp->if_watchdog = bnx_watchdog; 860 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 861 IFQ_SET_READY(&ifp->if_snd); 862 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 863 864 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 865 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 866 sc->bnx_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 867 868 ifp->if_capabilities |= 869 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 870 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 871 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 872 873 /* create workqueue to handle packet allocations */ 874 if (workqueue_create(&sc->bnx_wq, device_xname(self), 875 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 876 aprint_error_dev(self, "failed to create workqueue\n"); 877 goto bnx_attach_fail; 878 } 879 880 mii->mii_ifp = ifp; 881 mii->mii_readreg = bnx_miibus_read_reg; 882 mii->mii_writereg = bnx_miibus_write_reg; 883 mii->mii_statchg = bnx_miibus_statchg; 884 885 /* Handle any special PHY initialization for SerDes PHYs. */ 886 bnx_init_media(sc); 887 888 sc->bnx_ec.ec_mii = mii; 889 ifmedia_init(&mii->mii_media, 0, bnx_ifmedia_upd, bnx_ifmedia_sts); 890 891 /* set phyflags and chipid before mii_attach() */ 892 dict = device_properties(self); 893 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 894 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 895 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 896 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 897 898 /* Print some useful adapter info */ 899 bnx_print_adapter_info(sc); 900 901 mii_flags |= MIIF_DOPAUSE; 902 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 903 mii_flags |= MIIF_HAVEFIBER; 904 mii_attach(self, mii, 0xffffffff, 905 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 906 907 if (LIST_EMPTY(&mii->mii_phys)) { 908 aprint_error_dev(self, "no PHY found!\n"); 909 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 910 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 911 } else 912 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 913 914 /* Attach to the Ethernet interface list. */ 915 if_attach(ifp); 916 if_deferred_start_init(ifp, NULL); 917 ether_ifattach(ifp, sc->eaddr); 918 919 callout_init(&sc->bnx_timeout, 0); 920 callout_setfunc(&sc->bnx_timeout, bnx_tick, sc); 921 922 /* Hookup IRQ last. */ 923 sc->bnx_intrhand = pci_intr_establish_xname(pc, sc->bnx_ih[0], IPL_NET, 924 bnx_intr, sc, device_xname(self)); 925 if (sc->bnx_intrhand == NULL) { 926 aprint_error_dev(self, "couldn't establish interrupt"); 927 if (intrstr != NULL) 928 aprint_error(" at %s", intrstr); 929 aprint_error("\n"); 930 goto bnx_attach_fail; 931 } 932 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 933 934 if (pmf_device_register(self, NULL, NULL)) 935 pmf_class_network_register(self, ifp); 936 else 937 aprint_error_dev(self, "couldn't establish power handler\n"); 938 939 /* Print some important debugging info. */ 940 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 941 942 /* Get the firmware running so ASF still works. */ 943 bnx_mgmt_init(sc); 944 945 goto bnx_attach_exit; 946 947 bnx_attach_fail: 948 bnx_release_resources(sc); 949 950 bnx_attach_exit: 951 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 952 } 953 954 /****************************************************************************/ 955 /* Device detach function. */ 956 /* */ 957 /* Stops the controller, resets the controller, and releases resources. */ 958 /* */ 959 /* Returns: */ 960 /* 0 on success, positive value on failure. */ 961 /****************************************************************************/ 962 int 963 bnx_detach(device_t dev, int flags) 964 { 965 int s; 966 struct bnx_softc *sc; 967 struct ifnet *ifp; 968 969 sc = device_private(dev); 970 ifp = &sc->bnx_ec.ec_if; 971 972 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 973 974 /* Stop and reset the controller. */ 975 s = splnet(); 976 bnx_stop(ifp, 1); 977 splx(s); 978 979 pmf_device_deregister(dev); 980 callout_destroy(&sc->bnx_timeout); 981 ether_ifdetach(ifp); 982 workqueue_destroy(sc->bnx_wq); 983 984 if_detach(ifp); 985 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 986 987 /* Delete all remaining media. */ 988 ifmedia_fini(&sc->bnx_mii.mii_media); 989 990 /* Release all remaining resources. */ 991 bnx_release_resources(sc); 992 993 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 994 995 return 0; 996 } 997 998 /****************************************************************************/ 999 /* Indirect register read. */ 1000 /* */ 1001 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1002 /* configuration space. Using this mechanism avoids issues with posted */ 1003 /* reads but is much slower than memory-mapped I/O. */ 1004 /* */ 1005 /* Returns: */ 1006 /* The value of the register. */ 1007 /****************************************************************************/ 1008 uint32_t 1009 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 1010 { 1011 struct pci_attach_args *pa = &(sc->bnx_pa); 1012 1013 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1014 offset); 1015 #ifdef BNX_DEBUG 1016 { 1017 uint32_t val; 1018 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 1019 BNX_PCICFG_REG_WINDOW); 1020 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 1021 "val = 0x%08X\n", __func__, offset, val); 1022 return val; 1023 } 1024 #else 1025 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 1026 #endif 1027 } 1028 1029 /****************************************************************************/ 1030 /* Indirect register write. */ 1031 /* */ 1032 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1033 /* configuration space. Using this mechanism avoids issues with posted */ 1034 /* writes but is muchh slower than memory-mapped I/O. */ 1035 /* */ 1036 /* Returns: */ 1037 /* Nothing. */ 1038 /****************************************************************************/ 1039 void 1040 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 1041 { 1042 struct pci_attach_args *pa = &(sc->bnx_pa); 1043 1044 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 1045 __func__, offset, val); 1046 1047 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1048 offset); 1049 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 1050 } 1051 1052 /****************************************************************************/ 1053 /* Context memory write. */ 1054 /* */ 1055 /* The NetXtreme II controller uses context memory to track connection */ 1056 /* information for L2 and higher network protocols. */ 1057 /* */ 1058 /* Returns: */ 1059 /* Nothing. */ 1060 /****************************************************************************/ 1061 void 1062 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 1063 uint32_t ctx_val) 1064 { 1065 uint32_t idx, offset = ctx_offset + cid_addr; 1066 uint32_t val, retry_cnt = 5; 1067 1068 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1069 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1070 REG_WR(sc, BNX_CTX_CTX_CTRL, 1071 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 1072 1073 for (idx = 0; idx < retry_cnt; idx++) { 1074 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1075 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1076 break; 1077 DELAY(5); 1078 } 1079 1080 #if 0 1081 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1082 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1083 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1084 __FILE__, __LINE__, cid_addr, ctx_offset); 1085 #endif 1086 1087 } else { 1088 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1089 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1090 } 1091 } 1092 1093 /****************************************************************************/ 1094 /* PHY register read. */ 1095 /* */ 1096 /* Implements register reads on the MII bus. */ 1097 /* */ 1098 /* Returns: */ 1099 /* The value of the register. */ 1100 /****************************************************************************/ 1101 int 1102 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1103 { 1104 struct bnx_softc *sc = device_private(dev); 1105 uint32_t data; 1106 int i, rv = 0; 1107 1108 /* 1109 * The BCM5709S PHY is an IEEE Clause 45 PHY 1110 * with special mappings to work with IEEE 1111 * Clause 22 register accesses. 1112 */ 1113 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1114 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1115 reg += 0x10; 1116 } 1117 1118 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1119 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1120 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1121 1122 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1123 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1124 1125 DELAY(40); 1126 } 1127 1128 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1129 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1130 BNX_EMAC_MDIO_COMM_START_BUSY; 1131 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1132 1133 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1134 DELAY(10); 1135 1136 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1137 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1138 DELAY(5); 1139 1140 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1141 data &= BNX_EMAC_MDIO_COMM_DATA; 1142 1143 break; 1144 } 1145 } 1146 1147 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1148 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1149 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1150 rv = ETIMEDOUT; 1151 } else { 1152 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1153 *val = data & 0xffff; 1154 1155 DBPRINT(sc, BNX_EXCESSIVE, 1156 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1157 phy, (uint16_t) reg & 0xffff, *val); 1158 } 1159 1160 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1161 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1162 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1163 1164 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1165 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1166 1167 DELAY(40); 1168 } 1169 1170 return rv; 1171 } 1172 1173 /****************************************************************************/ 1174 /* PHY register write. */ 1175 /* */ 1176 /* Implements register writes on the MII bus. */ 1177 /* */ 1178 /* Returns: */ 1179 /* The value of the register. */ 1180 /****************************************************************************/ 1181 int 1182 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1183 { 1184 struct bnx_softc *sc = device_private(dev); 1185 uint32_t val1; 1186 int i, rv = 0; 1187 1188 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1189 "val = 0x%04hX\n", __func__, 1190 phy, (uint16_t) reg & 0xffff, val); 1191 1192 /* 1193 * The BCM5709S PHY is an IEEE Clause 45 PHY 1194 * with special mappings to work with IEEE 1195 * Clause 22 register accesses. 1196 */ 1197 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1198 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1199 reg += 0x10; 1200 } 1201 1202 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1203 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1204 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1205 1206 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1207 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1208 1209 DELAY(40); 1210 } 1211 1212 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1213 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1214 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1215 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1216 1217 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1218 DELAY(10); 1219 1220 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1221 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1222 DELAY(5); 1223 break; 1224 } 1225 } 1226 1227 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1228 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1229 __LINE__); 1230 rv = ETIMEDOUT; 1231 } 1232 1233 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1234 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1235 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1236 1237 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1238 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1239 1240 DELAY(40); 1241 } 1242 1243 return rv; 1244 } 1245 1246 /****************************************************************************/ 1247 /* MII bus status change. */ 1248 /* */ 1249 /* Called by the MII bus driver when the PHY establishes link to set the */ 1250 /* MAC interface registers. */ 1251 /* */ 1252 /* Returns: */ 1253 /* Nothing. */ 1254 /****************************************************************************/ 1255 void 1256 bnx_miibus_statchg(struct ifnet *ifp) 1257 { 1258 struct bnx_softc *sc = ifp->if_softc; 1259 struct mii_data *mii = &sc->bnx_mii; 1260 uint32_t rx_mode = sc->rx_mode; 1261 int val; 1262 1263 val = REG_RD(sc, BNX_EMAC_MODE); 1264 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1265 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1266 BNX_EMAC_MODE_25G); 1267 1268 /* 1269 * Get flow control negotiation result. 1270 */ 1271 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1272 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1273 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1274 mii->mii_media_active &= ~IFM_ETH_FMASK; 1275 } 1276 1277 /* Set MII or GMII interface based on the speed 1278 * negotiated by the PHY. 1279 */ 1280 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1281 case IFM_10_T: 1282 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1283 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1284 val |= BNX_EMAC_MODE_PORT_MII_10; 1285 break; 1286 } 1287 /* FALLTHROUGH */ 1288 case IFM_100_TX: 1289 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1290 val |= BNX_EMAC_MODE_PORT_MII; 1291 break; 1292 case IFM_2500_SX: 1293 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1294 val |= BNX_EMAC_MODE_25G; 1295 /* FALLTHROUGH */ 1296 case IFM_1000_T: 1297 case IFM_1000_SX: 1298 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1299 val |= BNX_EMAC_MODE_PORT_GMII; 1300 break; 1301 default: 1302 val |= BNX_EMAC_MODE_PORT_GMII; 1303 break; 1304 } 1305 1306 /* Set half or full duplex based on the duplicity 1307 * negotiated by the PHY. 1308 */ 1309 if ((mii->mii_media_active & IFM_HDX) != 0) { 1310 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1311 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1312 } else 1313 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1314 1315 REG_WR(sc, BNX_EMAC_MODE, val); 1316 1317 /* 1318 * 802.3x flow control 1319 */ 1320 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1321 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1322 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1323 } else { 1324 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1325 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1326 } 1327 1328 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1329 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1330 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1331 } else { 1332 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1333 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1334 } 1335 1336 /* Only make changes if the receive mode has actually changed. */ 1337 if (rx_mode != sc->rx_mode) { 1338 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1339 rx_mode); 1340 1341 sc->rx_mode = rx_mode; 1342 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1343 1344 bnx_init_rx_context(sc); 1345 } 1346 } 1347 1348 /****************************************************************************/ 1349 /* Acquire NVRAM lock. */ 1350 /* */ 1351 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1352 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1353 /* for use by the driver. */ 1354 /* */ 1355 /* Returns: */ 1356 /* 0 on success, positive value on failure. */ 1357 /****************************************************************************/ 1358 int 1359 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1360 { 1361 uint32_t val; 1362 int j; 1363 1364 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1365 1366 /* Request access to the flash interface. */ 1367 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1368 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1369 val = REG_RD(sc, BNX_NVM_SW_ARB); 1370 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1371 break; 1372 1373 DELAY(5); 1374 } 1375 1376 if (j >= NVRAM_TIMEOUT_COUNT) { 1377 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1378 return EBUSY; 1379 } 1380 1381 return 0; 1382 } 1383 1384 /****************************************************************************/ 1385 /* Release NVRAM lock. */ 1386 /* */ 1387 /* When the caller is finished accessing NVRAM the lock must be released. */ 1388 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1389 /* for use by the driver. */ 1390 /* */ 1391 /* Returns: */ 1392 /* 0 on success, positive value on failure. */ 1393 /****************************************************************************/ 1394 int 1395 bnx_release_nvram_lock(struct bnx_softc *sc) 1396 { 1397 int j; 1398 uint32_t val; 1399 1400 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1401 1402 /* Relinquish nvram interface. */ 1403 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1404 1405 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1406 val = REG_RD(sc, BNX_NVM_SW_ARB); 1407 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1408 break; 1409 1410 DELAY(5); 1411 } 1412 1413 if (j >= NVRAM_TIMEOUT_COUNT) { 1414 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1415 return EBUSY; 1416 } 1417 1418 return 0; 1419 } 1420 1421 #ifdef BNX_NVRAM_WRITE_SUPPORT 1422 /****************************************************************************/ 1423 /* Enable NVRAM write access. */ 1424 /* */ 1425 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1426 /* */ 1427 /* Returns: */ 1428 /* 0 on success, positive value on failure. */ 1429 /****************************************************************************/ 1430 int 1431 bnx_enable_nvram_write(struct bnx_softc *sc) 1432 { 1433 uint32_t val; 1434 1435 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1436 1437 val = REG_RD(sc, BNX_MISC_CFG); 1438 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1439 1440 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1441 int j; 1442 1443 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1444 REG_WR(sc, BNX_NVM_COMMAND, 1445 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1446 1447 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1448 DELAY(5); 1449 1450 val = REG_RD(sc, BNX_NVM_COMMAND); 1451 if (val & BNX_NVM_COMMAND_DONE) 1452 break; 1453 } 1454 1455 if (j >= NVRAM_TIMEOUT_COUNT) { 1456 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1457 return EBUSY; 1458 } 1459 } 1460 1461 return 0; 1462 } 1463 1464 /****************************************************************************/ 1465 /* Disable NVRAM write access. */ 1466 /* */ 1467 /* When the caller is finished writing to NVRAM write access must be */ 1468 /* disabled. */ 1469 /* */ 1470 /* Returns: */ 1471 /* Nothing. */ 1472 /****************************************************************************/ 1473 void 1474 bnx_disable_nvram_write(struct bnx_softc *sc) 1475 { 1476 uint32_t val; 1477 1478 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1479 1480 val = REG_RD(sc, BNX_MISC_CFG); 1481 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1482 } 1483 #endif 1484 1485 /****************************************************************************/ 1486 /* Enable NVRAM access. */ 1487 /* */ 1488 /* Before accessing NVRAM for read or write operations the caller must */ 1489 /* enabled NVRAM access. */ 1490 /* */ 1491 /* Returns: */ 1492 /* Nothing. */ 1493 /****************************************************************************/ 1494 void 1495 bnx_enable_nvram_access(struct bnx_softc *sc) 1496 { 1497 uint32_t val; 1498 1499 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1500 1501 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1502 /* Enable both bits, even on read. */ 1503 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1504 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1505 } 1506 1507 /****************************************************************************/ 1508 /* Disable NVRAM access. */ 1509 /* */ 1510 /* When the caller is finished accessing NVRAM access must be disabled. */ 1511 /* */ 1512 /* Returns: */ 1513 /* Nothing. */ 1514 /****************************************************************************/ 1515 void 1516 bnx_disable_nvram_access(struct bnx_softc *sc) 1517 { 1518 uint32_t val; 1519 1520 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1521 1522 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1523 1524 /* Disable both bits, even after read. */ 1525 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1526 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1527 } 1528 1529 #ifdef BNX_NVRAM_WRITE_SUPPORT 1530 /****************************************************************************/ 1531 /* Erase NVRAM page before writing. */ 1532 /* */ 1533 /* Non-buffered flash parts require that a page be erased before it is */ 1534 /* written. */ 1535 /* */ 1536 /* Returns: */ 1537 /* 0 on success, positive value on failure. */ 1538 /****************************************************************************/ 1539 int 1540 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1541 { 1542 uint32_t cmd; 1543 int j; 1544 1545 /* Buffered flash doesn't require an erase. */ 1546 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1547 return 0; 1548 1549 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1550 1551 /* Build an erase command. */ 1552 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1553 BNX_NVM_COMMAND_DOIT; 1554 1555 /* 1556 * Clear the DONE bit separately, set the NVRAM address to erase, 1557 * and issue the erase command. 1558 */ 1559 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1560 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1561 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1562 1563 /* Wait for completion. */ 1564 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1565 uint32_t val; 1566 1567 DELAY(5); 1568 1569 val = REG_RD(sc, BNX_NVM_COMMAND); 1570 if (val & BNX_NVM_COMMAND_DONE) 1571 break; 1572 } 1573 1574 if (j >= NVRAM_TIMEOUT_COUNT) { 1575 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1576 return EBUSY; 1577 } 1578 1579 return 0; 1580 } 1581 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1582 1583 /****************************************************************************/ 1584 /* Read a dword (32 bits) from NVRAM. */ 1585 /* */ 1586 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1587 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1588 /* */ 1589 /* Returns: */ 1590 /* 0 on success and the 32 bit value read, positive value on failure. */ 1591 /****************************************************************************/ 1592 int 1593 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1594 uint8_t *ret_val, uint32_t cmd_flags) 1595 { 1596 uint32_t cmd; 1597 int i, rc = 0; 1598 1599 /* Build the command word. */ 1600 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1601 1602 /* Calculate the offset for buffered flash if translation is used. */ 1603 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1604 offset = ((offset / sc->bnx_flash_info->page_size) << 1605 sc->bnx_flash_info->page_bits) + 1606 (offset % sc->bnx_flash_info->page_size); 1607 } 1608 1609 /* 1610 * Clear the DONE bit separately, set the address to read, 1611 * and issue the read. 1612 */ 1613 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1614 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1615 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1616 1617 /* Wait for completion. */ 1618 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1619 uint32_t val; 1620 1621 DELAY(5); 1622 1623 val = REG_RD(sc, BNX_NVM_COMMAND); 1624 if (val & BNX_NVM_COMMAND_DONE) { 1625 val = REG_RD(sc, BNX_NVM_READ); 1626 1627 val = be32toh(val); 1628 memcpy(ret_val, &val, 4); 1629 break; 1630 } 1631 } 1632 1633 /* Check for errors. */ 1634 if (i >= NVRAM_TIMEOUT_COUNT) { 1635 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1636 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1637 rc = EBUSY; 1638 } 1639 1640 return rc; 1641 } 1642 1643 #ifdef BNX_NVRAM_WRITE_SUPPORT 1644 /****************************************************************************/ 1645 /* Write a dword (32 bits) to NVRAM. */ 1646 /* */ 1647 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1648 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1649 /* enabled NVRAM write access. */ 1650 /* */ 1651 /* Returns: */ 1652 /* 0 on success, positive value on failure. */ 1653 /****************************************************************************/ 1654 int 1655 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1656 uint32_t cmd_flags) 1657 { 1658 uint32_t cmd, val32; 1659 int j; 1660 1661 /* Build the command word. */ 1662 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1663 1664 /* Calculate the offset for buffered flash if translation is used. */ 1665 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1666 offset = ((offset / sc->bnx_flash_info->page_size) << 1667 sc->bnx_flash_info->page_bits) + 1668 (offset % sc->bnx_flash_info->page_size); 1669 } 1670 1671 /* 1672 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1673 * set the NVRAM address to write, and issue the write command 1674 */ 1675 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1676 memcpy(&val32, val, 4); 1677 val32 = htobe32(val32); 1678 REG_WR(sc, BNX_NVM_WRITE, val32); 1679 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1680 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1681 1682 /* Wait for completion. */ 1683 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1684 DELAY(5); 1685 1686 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1687 break; 1688 } 1689 if (j >= NVRAM_TIMEOUT_COUNT) { 1690 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1691 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1692 return EBUSY; 1693 } 1694 1695 return 0; 1696 } 1697 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1698 1699 /****************************************************************************/ 1700 /* Initialize NVRAM access. */ 1701 /* */ 1702 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1703 /* access that device. */ 1704 /* */ 1705 /* Returns: */ 1706 /* 0 on success, positive value on failure. */ 1707 /****************************************************************************/ 1708 int 1709 bnx_init_nvram(struct bnx_softc *sc) 1710 { 1711 uint32_t val; 1712 int j, entry_count, rc = 0; 1713 struct flash_spec *flash; 1714 1715 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1716 1717 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1718 sc->bnx_flash_info = &flash_5709; 1719 goto bnx_init_nvram_get_flash_size; 1720 } 1721 1722 /* Determine the selected interface. */ 1723 val = REG_RD(sc, BNX_NVM_CFG1); 1724 1725 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1726 1727 /* 1728 * Flash reconfiguration is required to support additional 1729 * NVRAM devices not directly supported in hardware. 1730 * Check if the flash interface was reconfigured 1731 * by the bootcode. 1732 */ 1733 1734 if (val & 0x40000000) { 1735 /* Flash interface reconfigured by bootcode. */ 1736 1737 DBPRINT(sc, BNX_INFO_LOAD, 1738 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1739 1740 for (j = 0, flash = &flash_table[0]; j < entry_count; 1741 j++, flash++) { 1742 if ((val & FLASH_BACKUP_STRAP_MASK) == 1743 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1744 sc->bnx_flash_info = flash; 1745 break; 1746 } 1747 } 1748 } else { 1749 /* Flash interface not yet reconfigured. */ 1750 uint32_t mask; 1751 1752 DBPRINT(sc, BNX_INFO_LOAD, 1753 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1754 1755 if (val & (1 << 23)) 1756 mask = FLASH_BACKUP_STRAP_MASK; 1757 else 1758 mask = FLASH_STRAP_MASK; 1759 1760 /* Look for the matching NVRAM device configuration data. */ 1761 for (j = 0, flash = &flash_table[0]; j < entry_count; 1762 j++, flash++) { 1763 /* Check if the dev matches any of the known devices. */ 1764 if ((val & mask) == (flash->strapping & mask)) { 1765 /* Found a device match. */ 1766 sc->bnx_flash_info = flash; 1767 1768 /* Request access to the flash interface. */ 1769 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1770 return rc; 1771 1772 /* Reconfigure the flash interface. */ 1773 bnx_enable_nvram_access(sc); 1774 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1775 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1776 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1777 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1778 bnx_disable_nvram_access(sc); 1779 bnx_release_nvram_lock(sc); 1780 1781 break; 1782 } 1783 } 1784 } 1785 1786 /* Check if a matching device was found. */ 1787 if (j == entry_count) { 1788 sc->bnx_flash_info = NULL; 1789 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1790 __FILE__, __LINE__); 1791 rc = ENODEV; 1792 } 1793 1794 bnx_init_nvram_get_flash_size: 1795 /* Write the flash config data to the shared memory interface. */ 1796 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1797 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1798 if (val) 1799 sc->bnx_flash_size = val; 1800 else 1801 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1802 1803 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1804 "0x%08X\n", sc->bnx_flash_info->total_size); 1805 1806 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1807 1808 return rc; 1809 } 1810 1811 /****************************************************************************/ 1812 /* Read an arbitrary range of data from NVRAM. */ 1813 /* */ 1814 /* Prepares the NVRAM interface for access and reads the requested data */ 1815 /* into the supplied buffer. */ 1816 /* */ 1817 /* Returns: */ 1818 /* 0 on success and the data read, positive value on failure. */ 1819 /****************************************************************************/ 1820 int 1821 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1822 int buf_size) 1823 { 1824 int rc = 0; 1825 uint32_t cmd_flags, offset32, len32, extra; 1826 1827 if (buf_size == 0) 1828 return 0; 1829 1830 /* Request access to the flash interface. */ 1831 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1832 return rc; 1833 1834 /* Enable access to flash interface */ 1835 bnx_enable_nvram_access(sc); 1836 1837 len32 = buf_size; 1838 offset32 = offset; 1839 extra = 0; 1840 1841 cmd_flags = 0; 1842 1843 if (offset32 & 3) { 1844 uint8_t buf[4]; 1845 uint32_t pre_len; 1846 1847 offset32 &= ~3; 1848 pre_len = 4 - (offset & 3); 1849 1850 if (pre_len >= len32) { 1851 pre_len = len32; 1852 cmd_flags = 1853 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1854 } else 1855 cmd_flags = BNX_NVM_COMMAND_FIRST; 1856 1857 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1858 1859 if (rc) 1860 return rc; 1861 1862 memcpy(ret_buf, buf + (offset & 3), pre_len); 1863 1864 offset32 += 4; 1865 ret_buf += pre_len; 1866 len32 -= pre_len; 1867 } 1868 1869 if (len32 & 3) { 1870 extra = 4 - (len32 & 3); 1871 len32 = (len32 + 4) & ~3; 1872 } 1873 1874 if (len32 == 4) { 1875 uint8_t buf[4]; 1876 1877 if (cmd_flags) 1878 cmd_flags = BNX_NVM_COMMAND_LAST; 1879 else 1880 cmd_flags = 1881 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1882 1883 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1884 1885 memcpy(ret_buf, buf, 4 - extra); 1886 } else if (len32 > 0) { 1887 uint8_t buf[4]; 1888 1889 /* Read the first word. */ 1890 if (cmd_flags) 1891 cmd_flags = 0; 1892 else 1893 cmd_flags = BNX_NVM_COMMAND_FIRST; 1894 1895 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1896 1897 /* Advance to the next dword. */ 1898 offset32 += 4; 1899 ret_buf += 4; 1900 len32 -= 4; 1901 1902 while (len32 > 4 && rc == 0) { 1903 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1904 1905 /* Advance to the next dword. */ 1906 offset32 += 4; 1907 ret_buf += 4; 1908 len32 -= 4; 1909 } 1910 1911 if (rc) 1912 return rc; 1913 1914 cmd_flags = BNX_NVM_COMMAND_LAST; 1915 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1916 1917 memcpy(ret_buf, buf, 4 - extra); 1918 } 1919 1920 /* Disable access to flash interface and release the lock. */ 1921 bnx_disable_nvram_access(sc); 1922 bnx_release_nvram_lock(sc); 1923 1924 return rc; 1925 } 1926 1927 #ifdef BNX_NVRAM_WRITE_SUPPORT 1928 /****************************************************************************/ 1929 /* Write an arbitrary range of data from NVRAM. */ 1930 /* */ 1931 /* Prepares the NVRAM interface for write access and writes the requested */ 1932 /* data from the supplied buffer. The caller is responsible for */ 1933 /* calculating any appropriate CRCs. */ 1934 /* */ 1935 /* Returns: */ 1936 /* 0 on success, positive value on failure. */ 1937 /****************************************************************************/ 1938 int 1939 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1940 int buf_size) 1941 { 1942 uint32_t written, offset32, len32; 1943 uint8_t *buf, start[4], end[4]; 1944 int rc = 0; 1945 int align_start, align_end; 1946 1947 buf = data_buf; 1948 offset32 = offset; 1949 len32 = buf_size; 1950 align_start = align_end = 0; 1951 1952 if ((align_start = (offset32 & 3))) { 1953 offset32 &= ~3; 1954 len32 += align_start; 1955 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1956 return rc; 1957 } 1958 1959 if (len32 & 3) { 1960 if ((len32 > 4) || !align_start) { 1961 align_end = 4 - (len32 & 3); 1962 len32 += align_end; 1963 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1964 end, 4))) 1965 return rc; 1966 } 1967 } 1968 1969 if (align_start || align_end) { 1970 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1971 if (buf == NULL) 1972 return ENOMEM; 1973 1974 if (align_start) 1975 memcpy(buf, start, 4); 1976 1977 if (align_end) 1978 memcpy(buf + len32 - 4, end, 4); 1979 1980 memcpy(buf + align_start, data_buf, buf_size); 1981 } 1982 1983 written = 0; 1984 while ((written < len32) && (rc == 0)) { 1985 uint32_t page_start, page_end, data_start, data_end; 1986 uint32_t addr, cmd_flags; 1987 int i; 1988 uint8_t flash_buffer[264]; 1989 1990 /* Find the page_start addr */ 1991 page_start = offset32 + written; 1992 page_start -= (page_start % sc->bnx_flash_info->page_size); 1993 /* Find the page_end addr */ 1994 page_end = page_start + sc->bnx_flash_info->page_size; 1995 /* Find the data_start addr */ 1996 data_start = (written == 0) ? offset32 : page_start; 1997 /* Find the data_end addr */ 1998 data_end = (page_end > offset32 + len32) ? 1999 (offset32 + len32) : page_end; 2000 2001 /* Request access to the flash interface. */ 2002 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 2003 goto nvram_write_end; 2004 2005 /* Enable access to flash interface */ 2006 bnx_enable_nvram_access(sc); 2007 2008 cmd_flags = BNX_NVM_COMMAND_FIRST; 2009 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2010 int j; 2011 2012 /* Read the whole page into the buffer 2013 * (non-buffer flash only) */ 2014 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 2015 if (j == (sc->bnx_flash_info->page_size - 4)) 2016 cmd_flags |= BNX_NVM_COMMAND_LAST; 2017 2018 rc = bnx_nvram_read_dword(sc, 2019 page_start + j, 2020 &flash_buffer[j], 2021 cmd_flags); 2022 2023 if (rc) 2024 goto nvram_write_end; 2025 2026 cmd_flags = 0; 2027 } 2028 } 2029 2030 /* Enable writes to flash interface (unlock write-protect) */ 2031 if ((rc = bnx_enable_nvram_write(sc)) != 0) 2032 goto nvram_write_end; 2033 2034 /* Erase the page */ 2035 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 2036 goto nvram_write_end; 2037 2038 /* Re-enable the write again for the actual write */ 2039 bnx_enable_nvram_write(sc); 2040 2041 /* Loop to write back the buffer data from page_start to 2042 * data_start */ 2043 i = 0; 2044 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2045 for (addr = page_start; addr < data_start; 2046 addr += 4, i += 4) { 2047 2048 rc = bnx_nvram_write_dword(sc, addr, 2049 &flash_buffer[i], cmd_flags); 2050 2051 if (rc != 0) 2052 goto nvram_write_end; 2053 2054 cmd_flags = 0; 2055 } 2056 } 2057 2058 /* Loop to write the new data from data_start to data_end */ 2059 for (addr = data_start; addr < data_end; addr += 4, i++) { 2060 if ((addr == page_end - 4) || 2061 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 2062 && (addr == data_end - 4))) { 2063 2064 cmd_flags |= BNX_NVM_COMMAND_LAST; 2065 } 2066 2067 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2068 2069 if (rc != 0) 2070 goto nvram_write_end; 2071 2072 cmd_flags = 0; 2073 buf += 4; 2074 } 2075 2076 /* Loop to write back the buffer data from data_end 2077 * to page_end */ 2078 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2079 for (addr = data_end; addr < page_end; 2080 addr += 4, i += 4) { 2081 2082 if (addr == page_end-4) 2083 cmd_flags = BNX_NVM_COMMAND_LAST; 2084 2085 rc = bnx_nvram_write_dword(sc, addr, 2086 &flash_buffer[i], cmd_flags); 2087 2088 if (rc != 0) 2089 goto nvram_write_end; 2090 2091 cmd_flags = 0; 2092 } 2093 } 2094 2095 /* Disable writes to flash interface (lock write-protect) */ 2096 bnx_disable_nvram_write(sc); 2097 2098 /* Disable access to flash interface */ 2099 bnx_disable_nvram_access(sc); 2100 bnx_release_nvram_lock(sc); 2101 2102 /* Increment written */ 2103 written += data_end - data_start; 2104 } 2105 2106 nvram_write_end: 2107 if (align_start || align_end) 2108 free(buf, M_DEVBUF); 2109 2110 return rc; 2111 } 2112 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2113 2114 /****************************************************************************/ 2115 /* Verifies that NVRAM is accessible and contains valid data. */ 2116 /* */ 2117 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2118 /* correct. */ 2119 /* */ 2120 /* Returns: */ 2121 /* 0 on success, positive value on failure. */ 2122 /****************************************************************************/ 2123 int 2124 bnx_nvram_test(struct bnx_softc *sc) 2125 { 2126 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2127 uint8_t *data = (uint8_t *) buf; 2128 int rc = 0; 2129 uint32_t magic, csum; 2130 2131 /* 2132 * Check that the device NVRAM is valid by reading 2133 * the magic value at offset 0. 2134 */ 2135 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2136 goto bnx_nvram_test_done; 2137 2138 magic = be32toh(buf[0]); 2139 if (magic != BNX_NVRAM_MAGIC) { 2140 rc = ENODEV; 2141 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2142 "Expected: 0x%08X, Found: 0x%08X\n", 2143 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2144 goto bnx_nvram_test_done; 2145 } 2146 2147 /* 2148 * Verify that the device NVRAM includes valid 2149 * configuration data. 2150 */ 2151 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2152 goto bnx_nvram_test_done; 2153 2154 csum = ether_crc32_le(data, 0x100); 2155 if (csum != BNX_CRC32_RESIDUAL) { 2156 rc = ENODEV; 2157 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2158 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2159 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2160 goto bnx_nvram_test_done; 2161 } 2162 2163 csum = ether_crc32_le(data + 0x100, 0x100); 2164 if (csum != BNX_CRC32_RESIDUAL) { 2165 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2166 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2167 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2168 rc = ENODEV; 2169 } 2170 2171 bnx_nvram_test_done: 2172 return rc; 2173 } 2174 2175 /****************************************************************************/ 2176 /* Identifies the current media type of the controller and sets the PHY */ 2177 /* address. */ 2178 /* */ 2179 /* Returns: */ 2180 /* Nothing. */ 2181 /****************************************************************************/ 2182 void 2183 bnx_get_media(struct bnx_softc *sc) 2184 { 2185 sc->bnx_phy_addr = 1; 2186 2187 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2188 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2189 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2190 uint32_t strap; 2191 2192 /* 2193 * The BCM5709S is software configurable 2194 * for Copper or SerDes operation. 2195 */ 2196 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2197 DBPRINT(sc, BNX_INFO_LOAD, 2198 "5709 bonded for copper.\n"); 2199 goto bnx_get_media_exit; 2200 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2201 DBPRINT(sc, BNX_INFO_LOAD, 2202 "5709 bonded for dual media.\n"); 2203 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2204 goto bnx_get_media_exit; 2205 } 2206 2207 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2208 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2209 else { 2210 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2211 >> 8; 2212 } 2213 2214 if (sc->bnx_pa.pa_function == 0) { 2215 switch (strap) { 2216 case 0x4: 2217 case 0x5: 2218 case 0x6: 2219 DBPRINT(sc, BNX_INFO_LOAD, 2220 "BCM5709 s/w configured for SerDes.\n"); 2221 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2222 break; 2223 default: 2224 DBPRINT(sc, BNX_INFO_LOAD, 2225 "BCM5709 s/w configured for Copper.\n"); 2226 } 2227 } else { 2228 switch (strap) { 2229 case 0x1: 2230 case 0x2: 2231 case 0x4: 2232 DBPRINT(sc, BNX_INFO_LOAD, 2233 "BCM5709 s/w configured for SerDes.\n"); 2234 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2235 break; 2236 default: 2237 DBPRINT(sc, BNX_INFO_LOAD, 2238 "BCM5709 s/w configured for Copper.\n"); 2239 } 2240 } 2241 2242 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2243 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2244 2245 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2246 uint32_t val; 2247 2248 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2249 2250 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2251 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2252 2253 /* 2254 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2255 * separate PHY for SerDes. 2256 */ 2257 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2258 sc->bnx_phy_addr = 2; 2259 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2260 BNX_SHARED_HW_CFG_CONFIG); 2261 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2262 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2263 DBPRINT(sc, BNX_INFO_LOAD, 2264 "Found 2.5Gb capable adapter\n"); 2265 } 2266 } 2267 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2268 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2269 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2270 2271 bnx_get_media_exit: 2272 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2273 "Using PHY address %d.\n", sc->bnx_phy_addr); 2274 } 2275 2276 /****************************************************************************/ 2277 /* Performs PHY initialization required before MII drivers access the */ 2278 /* device. */ 2279 /* */ 2280 /* Returns: */ 2281 /* Nothing. */ 2282 /****************************************************************************/ 2283 void 2284 bnx_init_media(struct bnx_softc *sc) 2285 { 2286 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2287 /* 2288 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2289 * IEEE Clause 22 method. Otherwise we have no way to attach 2290 * the PHY to the mii(4) layer. PHY specific configuration 2291 * is done by the mii(4) layer. 2292 */ 2293 2294 /* Select auto-negotiation MMD of the PHY. */ 2295 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2296 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2297 2298 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2299 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2300 2301 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2302 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2303 } 2304 } 2305 2306 /****************************************************************************/ 2307 /* Free any DMA memory owned by the driver. */ 2308 /* */ 2309 /* Scans through each data structre that requires DMA memory and frees */ 2310 /* the memory if allocated. */ 2311 /* */ 2312 /* Returns: */ 2313 /* Nothing. */ 2314 /****************************************************************************/ 2315 void 2316 bnx_dma_free(struct bnx_softc *sc) 2317 { 2318 int i; 2319 2320 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2321 2322 /* Destroy the status block. */ 2323 if (sc->status_block != NULL && sc->status_map != NULL) { 2324 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2325 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2326 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2327 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2328 BNX_STATUS_BLK_SZ); 2329 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2330 sc->status_rseg); 2331 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2332 sc->status_block = NULL; 2333 sc->status_map = NULL; 2334 } 2335 2336 /* Destroy the statistics block. */ 2337 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2338 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2339 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2340 BNX_STATS_BLK_SZ); 2341 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2342 sc->stats_rseg); 2343 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2344 sc->stats_block = NULL; 2345 sc->stats_map = NULL; 2346 } 2347 2348 /* Free, unmap and destroy all context memory pages. */ 2349 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2350 for (i = 0; i < sc->ctx_pages; i++) { 2351 if (sc->ctx_block[i] != NULL) { 2352 bus_dmamap_unload(sc->bnx_dmatag, 2353 sc->ctx_map[i]); 2354 bus_dmamem_unmap(sc->bnx_dmatag, 2355 (void *)sc->ctx_block[i], 2356 BCM_PAGE_SIZE); 2357 bus_dmamem_free(sc->bnx_dmatag, 2358 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2359 bus_dmamap_destroy(sc->bnx_dmatag, 2360 sc->ctx_map[i]); 2361 sc->ctx_block[i] = NULL; 2362 } 2363 } 2364 } 2365 2366 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2367 for (i = 0; i < TX_PAGES; i++ ) { 2368 if (sc->tx_bd_chain[i] != NULL && 2369 sc->tx_bd_chain_map[i] != NULL) { 2370 bus_dmamap_unload(sc->bnx_dmatag, 2371 sc->tx_bd_chain_map[i]); 2372 bus_dmamem_unmap(sc->bnx_dmatag, 2373 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2374 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2375 sc->tx_bd_chain_rseg[i]); 2376 bus_dmamap_destroy(sc->bnx_dmatag, 2377 sc->tx_bd_chain_map[i]); 2378 sc->tx_bd_chain[i] = NULL; 2379 sc->tx_bd_chain_map[i] = NULL; 2380 } 2381 } 2382 2383 /* Destroy the TX dmamaps. */ 2384 struct bnx_pkt *pkt; 2385 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 2386 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 2387 sc->tx_pkt_count--; 2388 2389 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 2390 pool_put(bnx_tx_pool, pkt); 2391 } 2392 2393 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2394 for (i = 0; i < RX_PAGES; i++ ) { 2395 if (sc->rx_bd_chain[i] != NULL && 2396 sc->rx_bd_chain_map[i] != NULL) { 2397 bus_dmamap_unload(sc->bnx_dmatag, 2398 sc->rx_bd_chain_map[i]); 2399 bus_dmamem_unmap(sc->bnx_dmatag, 2400 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2401 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2402 sc->rx_bd_chain_rseg[i]); 2403 2404 bus_dmamap_destroy(sc->bnx_dmatag, 2405 sc->rx_bd_chain_map[i]); 2406 sc->rx_bd_chain[i] = NULL; 2407 sc->rx_bd_chain_map[i] = NULL; 2408 } 2409 } 2410 2411 /* Unload and destroy the RX mbuf maps. */ 2412 for (i = 0; i < TOTAL_RX_BD; i++) { 2413 if (sc->rx_mbuf_map[i] != NULL) { 2414 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2415 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2416 } 2417 } 2418 2419 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2420 } 2421 2422 /****************************************************************************/ 2423 /* Allocate any DMA memory needed by the driver. */ 2424 /* */ 2425 /* Allocates DMA memory needed for the various global structures needed by */ 2426 /* hardware. */ 2427 /* */ 2428 /* Returns: */ 2429 /* 0 for success, positive value for failure. */ 2430 /****************************************************************************/ 2431 int 2432 bnx_dma_alloc(struct bnx_softc *sc) 2433 { 2434 int i, rc = 0; 2435 2436 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2437 2438 /* 2439 * Allocate DMA memory for the status block, map the memory into DMA 2440 * space, and fetch the physical address of the block. 2441 */ 2442 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2443 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2444 aprint_error_dev(sc->bnx_dev, 2445 "Could not create status block DMA map!\n"); 2446 rc = ENOMEM; 2447 goto bnx_dma_alloc_exit; 2448 } 2449 2450 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2451 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2452 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2453 aprint_error_dev(sc->bnx_dev, 2454 "Could not allocate status block DMA memory!\n"); 2455 rc = ENOMEM; 2456 goto bnx_dma_alloc_exit; 2457 } 2458 2459 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2460 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2461 aprint_error_dev(sc->bnx_dev, 2462 "Could not map status block DMA memory!\n"); 2463 rc = ENOMEM; 2464 goto bnx_dma_alloc_exit; 2465 } 2466 2467 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2468 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2469 aprint_error_dev(sc->bnx_dev, 2470 "Could not load status block DMA memory!\n"); 2471 rc = ENOMEM; 2472 goto bnx_dma_alloc_exit; 2473 } 2474 2475 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2476 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2477 2478 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2479 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2480 2481 /* DRC - Fix for 64 bit addresses. */ 2482 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2483 (uint32_t) sc->status_block_paddr); 2484 2485 /* BCM5709 uses host memory as cache for context memory. */ 2486 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2487 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2488 if (sc->ctx_pages == 0) 2489 sc->ctx_pages = 1; 2490 if (sc->ctx_pages > 4) /* XXX */ 2491 sc->ctx_pages = 4; 2492 2493 DBRUNIF((sc->ctx_pages > 512), 2494 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2495 __FILE__, __LINE__, sc->ctx_pages)); 2496 2497 2498 for (i = 0; i < sc->ctx_pages; i++) { 2499 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2500 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2501 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2502 &sc->ctx_map[i]) != 0) { 2503 rc = ENOMEM; 2504 goto bnx_dma_alloc_exit; 2505 } 2506 2507 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2508 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2509 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2510 rc = ENOMEM; 2511 goto bnx_dma_alloc_exit; 2512 } 2513 2514 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2515 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2516 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2517 rc = ENOMEM; 2518 goto bnx_dma_alloc_exit; 2519 } 2520 2521 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2522 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2523 BUS_DMA_NOWAIT) != 0) { 2524 rc = ENOMEM; 2525 goto bnx_dma_alloc_exit; 2526 } 2527 2528 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2529 } 2530 } 2531 2532 /* 2533 * Allocate DMA memory for the statistics block, map the memory into 2534 * DMA space, and fetch the physical address of the block. 2535 */ 2536 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2537 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2538 aprint_error_dev(sc->bnx_dev, 2539 "Could not create stats block DMA map!\n"); 2540 rc = ENOMEM; 2541 goto bnx_dma_alloc_exit; 2542 } 2543 2544 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2545 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2546 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2547 aprint_error_dev(sc->bnx_dev, 2548 "Could not allocate stats block DMA memory!\n"); 2549 rc = ENOMEM; 2550 goto bnx_dma_alloc_exit; 2551 } 2552 2553 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2554 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2555 aprint_error_dev(sc->bnx_dev, 2556 "Could not map stats block DMA memory!\n"); 2557 rc = ENOMEM; 2558 goto bnx_dma_alloc_exit; 2559 } 2560 2561 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2562 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2563 aprint_error_dev(sc->bnx_dev, 2564 "Could not load status block DMA memory!\n"); 2565 rc = ENOMEM; 2566 goto bnx_dma_alloc_exit; 2567 } 2568 2569 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2570 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2571 2572 /* DRC - Fix for 64 bit address. */ 2573 DBPRINT(sc, BNX_INFO, "stats_block_paddr = 0x%08X\n", 2574 (uint32_t) sc->stats_block_paddr); 2575 2576 /* 2577 * Allocate DMA memory for the TX buffer descriptor chain, 2578 * and fetch the physical address of the block. 2579 */ 2580 for (i = 0; i < TX_PAGES; i++) { 2581 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2582 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2583 &sc->tx_bd_chain_map[i])) { 2584 aprint_error_dev(sc->bnx_dev, 2585 "Could not create Tx desc %d DMA map!\n", i); 2586 rc = ENOMEM; 2587 goto bnx_dma_alloc_exit; 2588 } 2589 2590 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2591 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2592 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2593 aprint_error_dev(sc->bnx_dev, 2594 "Could not allocate TX desc %d DMA memory!\n", 2595 i); 2596 rc = ENOMEM; 2597 goto bnx_dma_alloc_exit; 2598 } 2599 2600 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2601 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2602 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2603 aprint_error_dev(sc->bnx_dev, 2604 "Could not map TX desc %d DMA memory!\n", i); 2605 rc = ENOMEM; 2606 goto bnx_dma_alloc_exit; 2607 } 2608 2609 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2610 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2611 BUS_DMA_NOWAIT)) { 2612 aprint_error_dev(sc->bnx_dev, 2613 "Could not load TX desc %d DMA memory!\n", i); 2614 rc = ENOMEM; 2615 goto bnx_dma_alloc_exit; 2616 } 2617 2618 sc->tx_bd_chain_paddr[i] = 2619 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2620 2621 /* DRC - Fix for 64 bit systems. */ 2622 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2623 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2624 } 2625 2626 /* 2627 * Create lists to hold TX mbufs. 2628 */ 2629 TAILQ_INIT(&sc->tx_free_pkts); 2630 TAILQ_INIT(&sc->tx_used_pkts); 2631 sc->tx_pkt_count = 0; 2632 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2633 2634 /* 2635 * Allocate DMA memory for the Rx buffer descriptor chain, 2636 * and fetch the physical address of the block. 2637 */ 2638 for (i = 0; i < RX_PAGES; i++) { 2639 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2640 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2641 &sc->rx_bd_chain_map[i])) { 2642 aprint_error_dev(sc->bnx_dev, 2643 "Could not create Rx desc %d DMA map!\n", i); 2644 rc = ENOMEM; 2645 goto bnx_dma_alloc_exit; 2646 } 2647 2648 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2649 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2650 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2651 aprint_error_dev(sc->bnx_dev, 2652 "Could not allocate Rx desc %d DMA memory!\n", i); 2653 rc = ENOMEM; 2654 goto bnx_dma_alloc_exit; 2655 } 2656 2657 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2658 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2659 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2660 aprint_error_dev(sc->bnx_dev, 2661 "Could not map Rx desc %d DMA memory!\n", i); 2662 rc = ENOMEM; 2663 goto bnx_dma_alloc_exit; 2664 } 2665 2666 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2667 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2668 BUS_DMA_NOWAIT)) { 2669 aprint_error_dev(sc->bnx_dev, 2670 "Could not load Rx desc %d DMA memory!\n", i); 2671 rc = ENOMEM; 2672 goto bnx_dma_alloc_exit; 2673 } 2674 2675 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2676 sc->rx_bd_chain_paddr[i] = 2677 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2678 2679 /* DRC - Fix for 64 bit systems. */ 2680 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2681 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2682 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2683 0, BNX_RX_CHAIN_PAGE_SZ, 2684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2685 } 2686 2687 /* 2688 * Create DMA maps for the Rx buffer mbufs. 2689 */ 2690 for (i = 0; i < TOTAL_RX_BD; i++) { 2691 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2692 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2693 &sc->rx_mbuf_map[i])) { 2694 aprint_error_dev(sc->bnx_dev, 2695 "Could not create Rx mbuf %d DMA map!\n", i); 2696 rc = ENOMEM; 2697 goto bnx_dma_alloc_exit; 2698 } 2699 } 2700 2701 bnx_dma_alloc_exit: 2702 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2703 2704 return rc; 2705 } 2706 2707 /****************************************************************************/ 2708 /* Release all resources used by the driver. */ 2709 /* */ 2710 /* Releases all resources acquired by the driver including interrupts, */ 2711 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2712 /* */ 2713 /* Returns: */ 2714 /* Nothing. */ 2715 /****************************************************************************/ 2716 void 2717 bnx_release_resources(struct bnx_softc *sc) 2718 { 2719 struct pci_attach_args *pa = &(sc->bnx_pa); 2720 2721 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2722 2723 bnx_dma_free(sc); 2724 2725 if (sc->bnx_intrhand != NULL) 2726 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2727 2728 if (sc->bnx_ih != NULL) 2729 pci_intr_release(pa->pa_pc, sc->bnx_ih, 1); 2730 2731 if (sc->bnx_size) 2732 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2733 2734 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2735 } 2736 2737 /****************************************************************************/ 2738 /* Firmware synchronization. */ 2739 /* */ 2740 /* Before performing certain events such as a chip reset, synchronize with */ 2741 /* the firmware first. */ 2742 /* */ 2743 /* Returns: */ 2744 /* 0 for success, positive value for failure. */ 2745 /****************************************************************************/ 2746 int 2747 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2748 { 2749 int i, rc = 0; 2750 uint32_t val; 2751 2752 /* Don't waste any time if we've timed out before. */ 2753 if (sc->bnx_fw_timed_out) { 2754 rc = EBUSY; 2755 goto bnx_fw_sync_exit; 2756 } 2757 2758 /* Increment the message sequence number. */ 2759 sc->bnx_fw_wr_seq++; 2760 msg_data |= sc->bnx_fw_wr_seq; 2761 2762 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2763 msg_data); 2764 2765 /* Send the message to the bootcode driver mailbox. */ 2766 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2767 2768 /* Wait for the bootcode to acknowledge the message. */ 2769 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2770 /* Check for a response in the bootcode firmware mailbox. */ 2771 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2772 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2773 break; 2774 DELAY(1000); 2775 } 2776 2777 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2778 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2779 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2780 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2781 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2782 2783 msg_data &= ~BNX_DRV_MSG_CODE; 2784 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2785 2786 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2787 2788 sc->bnx_fw_timed_out = 1; 2789 rc = EBUSY; 2790 } 2791 2792 bnx_fw_sync_exit: 2793 return rc; 2794 } 2795 2796 /****************************************************************************/ 2797 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2798 /* */ 2799 /* Returns: */ 2800 /* Nothing. */ 2801 /****************************************************************************/ 2802 void 2803 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2804 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2805 { 2806 int i; 2807 uint32_t val; 2808 2809 /* Set the page size used by RV2P. */ 2810 if (rv2p_proc == RV2P_PROC2) { 2811 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2812 USABLE_RX_BD_PER_PAGE); 2813 } 2814 2815 for (i = 0; i < rv2p_code_len; i += 8) { 2816 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2817 rv2p_code++; 2818 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2819 rv2p_code++; 2820 2821 if (rv2p_proc == RV2P_PROC1) { 2822 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2823 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2824 } else { 2825 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2826 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2827 } 2828 } 2829 2830 /* Reset the processor, un-stall is done later. */ 2831 if (rv2p_proc == RV2P_PROC1) 2832 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2833 else 2834 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2835 } 2836 2837 /****************************************************************************/ 2838 /* Load RISC processor firmware. */ 2839 /* */ 2840 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2841 /* associated with a particular processor. */ 2842 /* */ 2843 /* Returns: */ 2844 /* Nothing. */ 2845 /****************************************************************************/ 2846 void 2847 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2848 struct fw_info *fw) 2849 { 2850 uint32_t offset; 2851 uint32_t val; 2852 2853 /* Halt the CPU. */ 2854 val = REG_RD_IND(sc, cpu_reg->mode); 2855 val |= cpu_reg->mode_value_halt; 2856 REG_WR_IND(sc, cpu_reg->mode, val); 2857 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2858 2859 /* Load the Text area. */ 2860 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2861 if (fw->text) { 2862 int j; 2863 2864 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2865 REG_WR_IND(sc, offset, fw->text[j]); 2866 } 2867 2868 /* Load the Data area. */ 2869 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2870 if (fw->data) { 2871 int j; 2872 2873 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2874 REG_WR_IND(sc, offset, fw->data[j]); 2875 } 2876 2877 /* Load the SBSS area. */ 2878 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2879 if (fw->sbss) { 2880 int j; 2881 2882 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2883 REG_WR_IND(sc, offset, fw->sbss[j]); 2884 } 2885 2886 /* Load the BSS area. */ 2887 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2888 if (fw->bss) { 2889 int j; 2890 2891 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2892 REG_WR_IND(sc, offset, fw->bss[j]); 2893 } 2894 2895 /* Load the Read-Only area. */ 2896 offset = cpu_reg->spad_base + 2897 (fw->rodata_addr - cpu_reg->mips_view_base); 2898 if (fw->rodata) { 2899 int j; 2900 2901 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2902 REG_WR_IND(sc, offset, fw->rodata[j]); 2903 } 2904 2905 /* Clear the pre-fetch instruction. */ 2906 REG_WR_IND(sc, cpu_reg->inst, 0); 2907 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2908 2909 /* Start the CPU. */ 2910 val = REG_RD_IND(sc, cpu_reg->mode); 2911 val &= ~cpu_reg->mode_value_halt; 2912 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2913 REG_WR_IND(sc, cpu_reg->mode, val); 2914 } 2915 2916 /****************************************************************************/ 2917 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2918 /* */ 2919 /* Loads the firmware for each CPU and starts the CPU. */ 2920 /* */ 2921 /* Returns: */ 2922 /* Nothing. */ 2923 /****************************************************************************/ 2924 void 2925 bnx_init_cpus(struct bnx_softc *sc) 2926 { 2927 struct cpu_reg cpu_reg; 2928 struct fw_info fw; 2929 2930 switch (BNX_CHIP_NUM(sc)) { 2931 case BNX_CHIP_NUM_5709: 2932 /* Initialize the RV2P processor. */ 2933 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2934 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2935 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2936 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2937 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2938 } else { 2939 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2940 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2941 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2942 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2943 } 2944 2945 /* Initialize the RX Processor. */ 2946 cpu_reg.mode = BNX_RXP_CPU_MODE; 2947 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2948 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2949 cpu_reg.state = BNX_RXP_CPU_STATE; 2950 cpu_reg.state_value_clear = 0xffffff; 2951 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2952 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2953 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2954 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2955 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2956 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2957 cpu_reg.mips_view_base = 0x8000000; 2958 2959 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2960 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2961 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2962 fw.start_addr = bnx_RXP_b09FwStartAddr; 2963 2964 fw.text_addr = bnx_RXP_b09FwTextAddr; 2965 fw.text_len = bnx_RXP_b09FwTextLen; 2966 fw.text_index = 0; 2967 fw.text = bnx_RXP_b09FwText; 2968 2969 fw.data_addr = bnx_RXP_b09FwDataAddr; 2970 fw.data_len = bnx_RXP_b09FwDataLen; 2971 fw.data_index = 0; 2972 fw.data = bnx_RXP_b09FwData; 2973 2974 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2975 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2976 fw.sbss_index = 0; 2977 fw.sbss = bnx_RXP_b09FwSbss; 2978 2979 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2980 fw.bss_len = bnx_RXP_b09FwBssLen; 2981 fw.bss_index = 0; 2982 fw.bss = bnx_RXP_b09FwBss; 2983 2984 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2985 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2986 fw.rodata_index = 0; 2987 fw.rodata = bnx_RXP_b09FwRodata; 2988 2989 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2990 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2991 2992 /* Initialize the TX Processor. */ 2993 cpu_reg.mode = BNX_TXP_CPU_MODE; 2994 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2995 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2996 cpu_reg.state = BNX_TXP_CPU_STATE; 2997 cpu_reg.state_value_clear = 0xffffff; 2998 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2999 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3000 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3001 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3002 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3003 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3004 cpu_reg.mips_view_base = 0x8000000; 3005 3006 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 3007 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 3008 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 3009 fw.start_addr = bnx_TXP_b09FwStartAddr; 3010 3011 fw.text_addr = bnx_TXP_b09FwTextAddr; 3012 fw.text_len = bnx_TXP_b09FwTextLen; 3013 fw.text_index = 0; 3014 fw.text = bnx_TXP_b09FwText; 3015 3016 fw.data_addr = bnx_TXP_b09FwDataAddr; 3017 fw.data_len = bnx_TXP_b09FwDataLen; 3018 fw.data_index = 0; 3019 fw.data = bnx_TXP_b09FwData; 3020 3021 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 3022 fw.sbss_len = bnx_TXP_b09FwSbssLen; 3023 fw.sbss_index = 0; 3024 fw.sbss = bnx_TXP_b09FwSbss; 3025 3026 fw.bss_addr = bnx_TXP_b09FwBssAddr; 3027 fw.bss_len = bnx_TXP_b09FwBssLen; 3028 fw.bss_index = 0; 3029 fw.bss = bnx_TXP_b09FwBss; 3030 3031 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 3032 fw.rodata_len = bnx_TXP_b09FwRodataLen; 3033 fw.rodata_index = 0; 3034 fw.rodata = bnx_TXP_b09FwRodata; 3035 3036 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3037 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3038 3039 /* Initialize the TX Patch-up Processor. */ 3040 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3041 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3042 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3043 cpu_reg.state = BNX_TPAT_CPU_STATE; 3044 cpu_reg.state_value_clear = 0xffffff; 3045 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3046 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3047 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3048 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3049 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3050 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3051 cpu_reg.mips_view_base = 0x8000000; 3052 3053 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 3054 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 3055 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 3056 fw.start_addr = bnx_TPAT_b09FwStartAddr; 3057 3058 fw.text_addr = bnx_TPAT_b09FwTextAddr; 3059 fw.text_len = bnx_TPAT_b09FwTextLen; 3060 fw.text_index = 0; 3061 fw.text = bnx_TPAT_b09FwText; 3062 3063 fw.data_addr = bnx_TPAT_b09FwDataAddr; 3064 fw.data_len = bnx_TPAT_b09FwDataLen; 3065 fw.data_index = 0; 3066 fw.data = bnx_TPAT_b09FwData; 3067 3068 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 3069 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 3070 fw.sbss_index = 0; 3071 fw.sbss = bnx_TPAT_b09FwSbss; 3072 3073 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 3074 fw.bss_len = bnx_TPAT_b09FwBssLen; 3075 fw.bss_index = 0; 3076 fw.bss = bnx_TPAT_b09FwBss; 3077 3078 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3079 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3080 fw.rodata_index = 0; 3081 fw.rodata = bnx_TPAT_b09FwRodata; 3082 3083 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3084 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3085 3086 /* Initialize the Completion Processor. */ 3087 cpu_reg.mode = BNX_COM_CPU_MODE; 3088 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3089 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3090 cpu_reg.state = BNX_COM_CPU_STATE; 3091 cpu_reg.state_value_clear = 0xffffff; 3092 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3093 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3094 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3095 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3096 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3097 cpu_reg.spad_base = BNX_COM_SCRATCH; 3098 cpu_reg.mips_view_base = 0x8000000; 3099 3100 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3101 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3102 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3103 fw.start_addr = bnx_COM_b09FwStartAddr; 3104 3105 fw.text_addr = bnx_COM_b09FwTextAddr; 3106 fw.text_len = bnx_COM_b09FwTextLen; 3107 fw.text_index = 0; 3108 fw.text = bnx_COM_b09FwText; 3109 3110 fw.data_addr = bnx_COM_b09FwDataAddr; 3111 fw.data_len = bnx_COM_b09FwDataLen; 3112 fw.data_index = 0; 3113 fw.data = bnx_COM_b09FwData; 3114 3115 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3116 fw.sbss_len = bnx_COM_b09FwSbssLen; 3117 fw.sbss_index = 0; 3118 fw.sbss = bnx_COM_b09FwSbss; 3119 3120 fw.bss_addr = bnx_COM_b09FwBssAddr; 3121 fw.bss_len = bnx_COM_b09FwBssLen; 3122 fw.bss_index = 0; 3123 fw.bss = bnx_COM_b09FwBss; 3124 3125 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3126 fw.rodata_len = bnx_COM_b09FwRodataLen; 3127 fw.rodata_index = 0; 3128 fw.rodata = bnx_COM_b09FwRodata; 3129 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3130 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3131 break; 3132 default: 3133 /* Initialize the RV2P processor. */ 3134 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3135 RV2P_PROC1); 3136 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3137 RV2P_PROC2); 3138 3139 /* Initialize the RX Processor. */ 3140 cpu_reg.mode = BNX_RXP_CPU_MODE; 3141 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3142 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3143 cpu_reg.state = BNX_RXP_CPU_STATE; 3144 cpu_reg.state_value_clear = 0xffffff; 3145 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3146 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3147 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3148 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3149 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3150 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3151 cpu_reg.mips_view_base = 0x8000000; 3152 3153 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3154 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3155 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3156 fw.start_addr = bnx_RXP_b06FwStartAddr; 3157 3158 fw.text_addr = bnx_RXP_b06FwTextAddr; 3159 fw.text_len = bnx_RXP_b06FwTextLen; 3160 fw.text_index = 0; 3161 fw.text = bnx_RXP_b06FwText; 3162 3163 fw.data_addr = bnx_RXP_b06FwDataAddr; 3164 fw.data_len = bnx_RXP_b06FwDataLen; 3165 fw.data_index = 0; 3166 fw.data = bnx_RXP_b06FwData; 3167 3168 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3169 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3170 fw.sbss_index = 0; 3171 fw.sbss = bnx_RXP_b06FwSbss; 3172 3173 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3174 fw.bss_len = bnx_RXP_b06FwBssLen; 3175 fw.bss_index = 0; 3176 fw.bss = bnx_RXP_b06FwBss; 3177 3178 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3179 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3180 fw.rodata_index = 0; 3181 fw.rodata = bnx_RXP_b06FwRodata; 3182 3183 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3184 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3185 3186 /* Initialize the TX Processor. */ 3187 cpu_reg.mode = BNX_TXP_CPU_MODE; 3188 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3189 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3190 cpu_reg.state = BNX_TXP_CPU_STATE; 3191 cpu_reg.state_value_clear = 0xffffff; 3192 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3193 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3194 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3195 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3196 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3197 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3198 cpu_reg.mips_view_base = 0x8000000; 3199 3200 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3201 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3202 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3203 fw.start_addr = bnx_TXP_b06FwStartAddr; 3204 3205 fw.text_addr = bnx_TXP_b06FwTextAddr; 3206 fw.text_len = bnx_TXP_b06FwTextLen; 3207 fw.text_index = 0; 3208 fw.text = bnx_TXP_b06FwText; 3209 3210 fw.data_addr = bnx_TXP_b06FwDataAddr; 3211 fw.data_len = bnx_TXP_b06FwDataLen; 3212 fw.data_index = 0; 3213 fw.data = bnx_TXP_b06FwData; 3214 3215 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3216 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3217 fw.sbss_index = 0; 3218 fw.sbss = bnx_TXP_b06FwSbss; 3219 3220 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3221 fw.bss_len = bnx_TXP_b06FwBssLen; 3222 fw.bss_index = 0; 3223 fw.bss = bnx_TXP_b06FwBss; 3224 3225 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3226 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3227 fw.rodata_index = 0; 3228 fw.rodata = bnx_TXP_b06FwRodata; 3229 3230 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3231 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3232 3233 /* Initialize the TX Patch-up Processor. */ 3234 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3235 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3236 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3237 cpu_reg.state = BNX_TPAT_CPU_STATE; 3238 cpu_reg.state_value_clear = 0xffffff; 3239 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3240 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3241 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3242 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3243 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3244 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3245 cpu_reg.mips_view_base = 0x8000000; 3246 3247 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3248 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3249 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3250 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3251 3252 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3253 fw.text_len = bnx_TPAT_b06FwTextLen; 3254 fw.text_index = 0; 3255 fw.text = bnx_TPAT_b06FwText; 3256 3257 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3258 fw.data_len = bnx_TPAT_b06FwDataLen; 3259 fw.data_index = 0; 3260 fw.data = bnx_TPAT_b06FwData; 3261 3262 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3263 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3264 fw.sbss_index = 0; 3265 fw.sbss = bnx_TPAT_b06FwSbss; 3266 3267 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3268 fw.bss_len = bnx_TPAT_b06FwBssLen; 3269 fw.bss_index = 0; 3270 fw.bss = bnx_TPAT_b06FwBss; 3271 3272 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3273 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3274 fw.rodata_index = 0; 3275 fw.rodata = bnx_TPAT_b06FwRodata; 3276 3277 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3278 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3279 3280 /* Initialize the Completion Processor. */ 3281 cpu_reg.mode = BNX_COM_CPU_MODE; 3282 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3283 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3284 cpu_reg.state = BNX_COM_CPU_STATE; 3285 cpu_reg.state_value_clear = 0xffffff; 3286 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3287 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3288 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3289 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3290 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3291 cpu_reg.spad_base = BNX_COM_SCRATCH; 3292 cpu_reg.mips_view_base = 0x8000000; 3293 3294 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3295 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3296 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3297 fw.start_addr = bnx_COM_b06FwStartAddr; 3298 3299 fw.text_addr = bnx_COM_b06FwTextAddr; 3300 fw.text_len = bnx_COM_b06FwTextLen; 3301 fw.text_index = 0; 3302 fw.text = bnx_COM_b06FwText; 3303 3304 fw.data_addr = bnx_COM_b06FwDataAddr; 3305 fw.data_len = bnx_COM_b06FwDataLen; 3306 fw.data_index = 0; 3307 fw.data = bnx_COM_b06FwData; 3308 3309 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3310 fw.sbss_len = bnx_COM_b06FwSbssLen; 3311 fw.sbss_index = 0; 3312 fw.sbss = bnx_COM_b06FwSbss; 3313 3314 fw.bss_addr = bnx_COM_b06FwBssAddr; 3315 fw.bss_len = bnx_COM_b06FwBssLen; 3316 fw.bss_index = 0; 3317 fw.bss = bnx_COM_b06FwBss; 3318 3319 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3320 fw.rodata_len = bnx_COM_b06FwRodataLen; 3321 fw.rodata_index = 0; 3322 fw.rodata = bnx_COM_b06FwRodata; 3323 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3324 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3325 break; 3326 } 3327 } 3328 3329 /****************************************************************************/ 3330 /* Initialize context memory. */ 3331 /* */ 3332 /* Clears the memory associated with each Context ID (CID). */ 3333 /* */ 3334 /* Returns: */ 3335 /* Nothing. */ 3336 /****************************************************************************/ 3337 void 3338 bnx_init_context(struct bnx_softc *sc) 3339 { 3340 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3341 /* DRC: Replace this constant value with a #define. */ 3342 int i, retry_cnt = 10; 3343 uint32_t val; 3344 3345 /* 3346 * BCM5709 context memory may be cached 3347 * in host memory so prepare the host memory 3348 * for access. 3349 */ 3350 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3351 | (1 << 12); 3352 val |= (BCM_PAGE_BITS - 8) << 16; 3353 REG_WR(sc, BNX_CTX_COMMAND, val); 3354 3355 /* Wait for mem init command to complete. */ 3356 for (i = 0; i < retry_cnt; i++) { 3357 val = REG_RD(sc, BNX_CTX_COMMAND); 3358 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3359 break; 3360 DELAY(2); 3361 } 3362 3363 /* ToDo: Consider returning an error here. */ 3364 3365 for (i = 0; i < sc->ctx_pages; i++) { 3366 int j; 3367 3368 /* Set the physaddr of the context memory cache. */ 3369 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3370 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3371 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3372 val = (uint32_t) 3373 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3374 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3375 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3376 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3377 3378 /* Verify that the context memory write was successful. */ 3379 for (j = 0; j < retry_cnt; j++) { 3380 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3381 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3382 break; 3383 DELAY(5); 3384 } 3385 3386 /* ToDo: Consider returning an error here. */ 3387 } 3388 } else { 3389 uint32_t vcid_addr, offset; 3390 3391 /* 3392 * For the 5706/5708, context memory is local to the 3393 * controller, so initialize the controller context memory. 3394 */ 3395 3396 vcid_addr = GET_CID_ADDR(96); 3397 while (vcid_addr) { 3398 3399 vcid_addr -= BNX_PHY_CTX_SIZE; 3400 3401 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3402 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3403 3404 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3405 offset += 4) 3406 CTX_WR(sc, 0x00, offset, 0); 3407 3408 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3409 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3410 } 3411 } 3412 } 3413 3414 /****************************************************************************/ 3415 /* Fetch the permanent MAC address of the controller. */ 3416 /* */ 3417 /* Returns: */ 3418 /* Nothing. */ 3419 /****************************************************************************/ 3420 void 3421 bnx_get_mac_addr(struct bnx_softc *sc) 3422 { 3423 uint32_t mac_lo = 0, mac_hi = 0; 3424 3425 /* 3426 * The NetXtreme II bootcode populates various NIC 3427 * power-on and runtime configuration items in a 3428 * shared memory area. The factory configured MAC 3429 * address is available from both NVRAM and the 3430 * shared memory area so we'll read the value from 3431 * shared memory for speed. 3432 */ 3433 3434 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3435 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3436 3437 if ((mac_lo == 0) && (mac_hi == 0)) { 3438 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3439 __FILE__, __LINE__); 3440 } else { 3441 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3442 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3443 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3444 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3445 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3446 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3447 } 3448 3449 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3450 "%s\n", ether_sprintf(sc->eaddr)); 3451 } 3452 3453 /****************************************************************************/ 3454 /* Program the MAC address. */ 3455 /* */ 3456 /* Returns: */ 3457 /* Nothing. */ 3458 /****************************************************************************/ 3459 void 3460 bnx_set_mac_addr(struct bnx_softc *sc) 3461 { 3462 uint32_t val; 3463 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3464 3465 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3466 "%s\n", ether_sprintf(sc->eaddr)); 3467 3468 val = (mac_addr[0] << 8) | mac_addr[1]; 3469 3470 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3471 3472 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3473 (mac_addr[4] << 8) | mac_addr[5]; 3474 3475 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3476 } 3477 3478 /****************************************************************************/ 3479 /* Stop the controller. */ 3480 /* */ 3481 /* Returns: */ 3482 /* Nothing. */ 3483 /****************************************************************************/ 3484 void 3485 bnx_stop(struct ifnet *ifp, int disable) 3486 { 3487 struct bnx_softc *sc = ifp->if_softc; 3488 3489 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3490 3491 if (disable) { 3492 sc->bnx_detaching = 1; 3493 callout_halt(&sc->bnx_timeout, NULL); 3494 } else 3495 callout_stop(&sc->bnx_timeout); 3496 3497 mii_down(&sc->bnx_mii); 3498 3499 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3500 3501 /* Disable the transmit/receive blocks. */ 3502 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3503 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3504 DELAY(20); 3505 3506 bnx_disable_intr(sc); 3507 3508 /* Tell firmware that the driver is going away. */ 3509 if (disable) 3510 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3511 else 3512 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3513 3514 /* Free RX buffers. */ 3515 bnx_free_rx_chain(sc); 3516 3517 /* Free TX buffers. */ 3518 bnx_free_tx_chain(sc); 3519 3520 ifp->if_timer = 0; 3521 3522 sc->bnx_link = 0; 3523 3524 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3525 3526 bnx_mgmt_init(sc); 3527 } 3528 3529 int 3530 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3531 { 3532 struct pci_attach_args *pa = &(sc->bnx_pa); 3533 uint32_t val; 3534 int i, rc = 0; 3535 3536 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3537 3538 /* Wait for pending PCI transactions to complete. */ 3539 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 3540 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) { 3541 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3542 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3543 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3544 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3545 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3546 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3547 DELAY(5); 3548 } else { 3549 /* Disable DMA */ 3550 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3551 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3552 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3553 REG_RD(sc, BNX_MISC_NEW_CORE_CTL); /* barrier */ 3554 3555 for (i = 0; i < 100; i++) { 3556 delay(1 * 1000); 3557 val = REG_RD(sc, BNX_PCICFG_DEVICE_CONTROL); 3558 if ((val & PCIE_DCSR_TRANSACTION_PND) == 0) 3559 break; 3560 } 3561 } 3562 3563 /* Assume bootcode is running. */ 3564 sc->bnx_fw_timed_out = 0; 3565 3566 /* Give the firmware a chance to prepare for the reset. */ 3567 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3568 if (rc) 3569 goto bnx_reset_exit; 3570 3571 /* Set a firmware reminder that this is a soft reset. */ 3572 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3573 BNX_DRV_RESET_SIGNATURE_MAGIC); 3574 3575 /* Dummy read to force the chip to complete all current transactions. */ 3576 val = REG_RD(sc, BNX_MISC_ID); 3577 3578 /* Chip reset. */ 3579 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3580 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3581 REG_RD(sc, BNX_MISC_COMMAND); 3582 DELAY(5); 3583 3584 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3585 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3586 3587 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3588 val); 3589 } else { 3590 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3591 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3592 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3593 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3594 3595 /* Allow up to 30us for reset to complete. */ 3596 for (i = 0; i < 10; i++) { 3597 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3598 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3599 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3600 break; 3601 } 3602 DELAY(10); 3603 } 3604 3605 /* Check that reset completed successfully. */ 3606 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3607 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3608 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3609 __FILE__, __LINE__); 3610 rc = EBUSY; 3611 goto bnx_reset_exit; 3612 } 3613 } 3614 3615 /* Make sure byte swapping is properly configured. */ 3616 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3617 if (val != 0x01020304) { 3618 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3619 __FILE__, __LINE__); 3620 rc = ENODEV; 3621 goto bnx_reset_exit; 3622 } 3623 3624 /* Just completed a reset, assume that firmware is running again. */ 3625 sc->bnx_fw_timed_out = 0; 3626 3627 /* Wait for the firmware to finish its initialization. */ 3628 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3629 if (rc) 3630 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3631 "initialization!\n", __FILE__, __LINE__); 3632 3633 bnx_reset_exit: 3634 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3635 3636 return rc; 3637 } 3638 3639 int 3640 bnx_chipinit(struct bnx_softc *sc) 3641 { 3642 struct pci_attach_args *pa = &(sc->bnx_pa); 3643 uint32_t val; 3644 int rc = 0; 3645 3646 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3647 3648 /* Make sure the interrupt is not active. */ 3649 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3650 3651 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3652 /* channels and PCI clock compensation delay. */ 3653 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3654 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3655 #if BYTE_ORDER == BIG_ENDIAN 3656 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3657 #endif 3658 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3659 DMA_READ_CHANS << 12 | 3660 DMA_WRITE_CHANS << 16; 3661 3662 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3663 3664 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3665 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3666 3667 /* 3668 * This setting resolves a problem observed on certain Intel PCI 3669 * chipsets that cannot handle multiple outstanding DMA operations. 3670 * See errata E9_5706A1_65. 3671 */ 3672 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3673 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3674 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3675 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3676 3677 REG_WR(sc, BNX_DMA_CONFIG, val); 3678 3679 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3680 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3681 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3682 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3683 val & ~0x20000); 3684 } 3685 3686 /* Enable the RX_V2P and Context state machines before access. */ 3687 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3688 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3689 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3690 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3691 3692 /* Initialize context mapping and zero out the quick contexts. */ 3693 bnx_init_context(sc); 3694 3695 /* Initialize the on-boards CPUs */ 3696 bnx_init_cpus(sc); 3697 3698 /* Enable management frames (NC-SI) to flow to the MCP. */ 3699 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3700 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) | 3701 BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3702 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3703 } 3704 3705 /* Prepare NVRAM for access. */ 3706 if (bnx_init_nvram(sc)) { 3707 rc = ENODEV; 3708 goto bnx_chipinit_exit; 3709 } 3710 3711 /* Set the kernel bypass block size */ 3712 val = REG_RD(sc, BNX_MQ_CONFIG); 3713 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3714 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3715 3716 /* Enable bins used on the 5709. */ 3717 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3718 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3719 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3720 val |= BNX_MQ_CONFIG_HALT_DIS; 3721 } 3722 3723 REG_WR(sc, BNX_MQ_CONFIG, val); 3724 3725 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3726 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3727 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3728 3729 val = (BCM_PAGE_BITS - 8) << 24; 3730 REG_WR(sc, BNX_RV2P_CONFIG, val); 3731 3732 /* Configure page size. */ 3733 val = REG_RD(sc, BNX_TBDR_CONFIG); 3734 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3735 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3736 REG_WR(sc, BNX_TBDR_CONFIG, val); 3737 3738 #if 0 3739 /* Set the perfect match control register to default. */ 3740 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3741 #endif 3742 3743 bnx_chipinit_exit: 3744 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3745 3746 return rc; 3747 } 3748 3749 /****************************************************************************/ 3750 /* Initialize the controller in preparation to send/receive traffic. */ 3751 /* */ 3752 /* Returns: */ 3753 /* 0 for success, positive value for failure. */ 3754 /****************************************************************************/ 3755 int 3756 bnx_blockinit(struct bnx_softc *sc) 3757 { 3758 uint32_t reg, val; 3759 int rc = 0; 3760 3761 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3762 3763 /* Load the hardware default MAC address. */ 3764 bnx_set_mac_addr(sc); 3765 3766 /* Set the Ethernet backoff seed value */ 3767 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3768 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3769 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3770 3771 sc->last_status_idx = 0; 3772 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3773 3774 /* Set up link change interrupt generation. */ 3775 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3776 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3777 3778 /* Program the physical address of the status block. */ 3779 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3780 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3781 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3782 3783 /* Program the physical address of the statistics block. */ 3784 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3785 (uint32_t)(sc->stats_block_paddr)); 3786 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3787 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3788 3789 /* Program various host coalescing parameters. */ 3790 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3791 << 16) | sc->bnx_tx_quick_cons_trip); 3792 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3793 << 16) | sc->bnx_rx_quick_cons_trip); 3794 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3795 sc->bnx_comp_prod_trip); 3796 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3797 sc->bnx_tx_ticks); 3798 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3799 sc->bnx_rx_ticks); 3800 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3801 sc->bnx_com_ticks); 3802 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3803 sc->bnx_cmd_ticks); 3804 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3805 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3806 REG_WR(sc, BNX_HC_CONFIG, 3807 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3808 BNX_HC_CONFIG_COLLECT_STATS)); 3809 3810 /* Clear the internal statistics counters. */ 3811 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3812 3813 /* Verify that bootcode is running. */ 3814 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3815 3816 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3817 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3818 __FILE__, __LINE__); reg = 0); 3819 3820 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3821 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3822 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3823 "Expected: 08%08X\n", __FILE__, __LINE__, 3824 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3825 BNX_DEV_INFO_SIGNATURE_MAGIC); 3826 rc = ENODEV; 3827 goto bnx_blockinit_exit; 3828 } 3829 3830 /* Enable DMA */ 3831 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3832 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3833 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3834 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3835 } 3836 3837 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3838 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3839 3840 /* Disable management frames (NC-SI) from flowing to the MCP. */ 3841 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3842 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) & 3843 ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3844 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3845 } 3846 3847 /* Enable all remaining blocks in the MAC. */ 3848 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3849 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3850 BNX_MISC_ENABLE_DEFAULT_XI); 3851 } else 3852 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3853 3854 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3855 DELAY(20); 3856 3857 bnx_blockinit_exit: 3858 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3859 3860 return rc; 3861 } 3862 3863 static int 3864 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3865 uint16_t *chain_prod, uint32_t *prod_bseq) 3866 { 3867 bus_dmamap_t map; 3868 struct rx_bd *rxbd; 3869 uint32_t addr; 3870 int i; 3871 #ifdef BNX_DEBUG 3872 uint16_t debug_chain_prod = *chain_prod; 3873 #endif 3874 uint16_t first_chain_prod; 3875 3876 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3877 3878 /* Map the mbuf cluster into device memory. */ 3879 map = sc->rx_mbuf_map[*chain_prod]; 3880 first_chain_prod = *chain_prod; 3881 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3882 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3883 __FILE__, __LINE__); 3884 3885 m_freem(m_new); 3886 3887 DBRUNIF(1, sc->rx_mbuf_alloc--); 3888 3889 return ENOBUFS; 3890 } 3891 /* Make sure there is room in the receive chain. */ 3892 if (map->dm_nsegs > sc->free_rx_bd) { 3893 bus_dmamap_unload(sc->bnx_dmatag, map); 3894 m_freem(m_new); 3895 return EFBIG; 3896 } 3897 #ifdef BNX_DEBUG 3898 /* Track the distribution of buffer segments. */ 3899 sc->rx_mbuf_segs[map->dm_nsegs]++; 3900 #endif 3901 3902 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3903 BUS_DMASYNC_PREREAD); 3904 3905 /* Update some debug statistics counters */ 3906 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3907 sc->rx_low_watermark = sc->free_rx_bd); 3908 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3909 3910 /* 3911 * Setup the rx_bd for the first segment 3912 */ 3913 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3914 3915 addr = (uint32_t)map->dm_segs[0].ds_addr; 3916 rxbd->rx_bd_haddr_lo = addr; 3917 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3918 rxbd->rx_bd_haddr_hi = addr; 3919 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3920 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3921 *prod_bseq += map->dm_segs[0].ds_len; 3922 bus_dmamap_sync(sc->bnx_dmatag, 3923 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3924 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3926 3927 for (i = 1; i < map->dm_nsegs; i++) { 3928 *prod = NEXT_RX_BD(*prod); 3929 *chain_prod = RX_CHAIN_IDX(*prod); 3930 3931 rxbd = 3932 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3933 3934 addr = (uint32_t)map->dm_segs[i].ds_addr; 3935 rxbd->rx_bd_haddr_lo = addr; 3936 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3937 rxbd->rx_bd_haddr_hi = addr; 3938 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3939 rxbd->rx_bd_flags = 0; 3940 *prod_bseq += map->dm_segs[i].ds_len; 3941 bus_dmamap_sync(sc->bnx_dmatag, 3942 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3943 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3944 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3945 } 3946 3947 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3948 bus_dmamap_sync(sc->bnx_dmatag, 3949 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3950 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3951 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3952 3953 /* 3954 * Save the mbuf, adjust the map pointer (swap map for first and 3955 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3956 * and update our counter. 3957 */ 3958 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3959 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3960 sc->rx_mbuf_map[*chain_prod] = map; 3961 sc->free_rx_bd -= map->dm_nsegs; 3962 3963 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3964 map->dm_nsegs)); 3965 *prod = NEXT_RX_BD(*prod); 3966 *chain_prod = RX_CHAIN_IDX(*prod); 3967 3968 return 0; 3969 } 3970 3971 /****************************************************************************/ 3972 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3973 /* */ 3974 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3975 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3976 /* necessary. */ 3977 /* */ 3978 /* Returns: */ 3979 /* 0 for success, positive value for failure. */ 3980 /****************************************************************************/ 3981 int 3982 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3983 uint16_t *chain_prod, uint32_t *prod_bseq) 3984 { 3985 struct mbuf *m_new = NULL; 3986 int rc = 0; 3987 uint16_t min_free_bd; 3988 3989 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3990 __func__); 3991 3992 /* Make sure the inputs are valid. */ 3993 DBRUNIF((*chain_prod > MAX_RX_BD), 3994 aprint_error_dev(sc->bnx_dev, 3995 "RX producer out of range: 0x%04X > 0x%04X\n", 3996 *chain_prod, (uint16_t)MAX_RX_BD)); 3997 3998 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3999 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 4000 *prod_bseq); 4001 4002 /* try to get in as many mbufs as possible */ 4003 if (sc->mbuf_alloc_size == MCLBYTES) 4004 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 4005 else 4006 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 4007 while (sc->free_rx_bd >= min_free_bd) { 4008 /* Simulate an mbuf allocation failure. */ 4009 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4010 aprint_error_dev(sc->bnx_dev, 4011 "Simulating mbuf allocation failure.\n"); 4012 sc->mbuf_sim_alloc_failed++; 4013 rc = ENOBUFS; 4014 goto bnx_get_buf_exit); 4015 4016 /* This is a new mbuf allocation. */ 4017 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4018 if (m_new == NULL) { 4019 DBPRINT(sc, BNX_WARN, 4020 "%s(%d): RX mbuf header allocation failed!\n", 4021 __FILE__, __LINE__); 4022 4023 sc->mbuf_alloc_failed++; 4024 4025 rc = ENOBUFS; 4026 goto bnx_get_buf_exit; 4027 } 4028 4029 DBRUNIF(1, sc->rx_mbuf_alloc++); 4030 4031 /* Simulate an mbuf cluster allocation failure. */ 4032 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4033 m_freem(m_new); 4034 sc->rx_mbuf_alloc--; 4035 sc->mbuf_alloc_failed++; 4036 sc->mbuf_sim_alloc_failed++; 4037 rc = ENOBUFS; 4038 goto bnx_get_buf_exit); 4039 4040 if (sc->mbuf_alloc_size == MCLBYTES) 4041 MCLGET(m_new, M_DONTWAIT); 4042 else 4043 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 4044 M_DONTWAIT); 4045 if (!(m_new->m_flags & M_EXT)) { 4046 DBPRINT(sc, BNX_WARN, 4047 "%s(%d): RX mbuf chain allocation failed!\n", 4048 __FILE__, __LINE__); 4049 4050 m_freem(m_new); 4051 4052 DBRUNIF(1, sc->rx_mbuf_alloc--); 4053 sc->mbuf_alloc_failed++; 4054 4055 rc = ENOBUFS; 4056 goto bnx_get_buf_exit; 4057 } 4058 4059 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 4060 if (rc != 0) 4061 goto bnx_get_buf_exit; 4062 } 4063 4064 bnx_get_buf_exit: 4065 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 4066 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 4067 *chain_prod, *prod_bseq); 4068 4069 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 4070 __func__); 4071 4072 return rc; 4073 } 4074 4075 void 4076 bnx_alloc_pkts(struct work * unused, void * arg) 4077 { 4078 struct bnx_softc *sc = arg; 4079 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4080 struct bnx_pkt *pkt; 4081 int i, s; 4082 4083 for (i = 0; i < 4; i++) { /* magic! */ 4084 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 4085 if (pkt == NULL) 4086 break; 4087 4088 if (bus_dmamap_create(sc->bnx_dmatag, 4089 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4090 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4091 &pkt->pkt_dmamap) != 0) { 4092 pool_put(bnx_tx_pool, pkt); 4093 break; 4094 } 4095 4096 mutex_enter(&sc->tx_pkt_mtx); 4097 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4098 sc->tx_pkt_count++; 4099 mutex_exit(&sc->tx_pkt_mtx); 4100 } 4101 4102 mutex_enter(&sc->tx_pkt_mtx); 4103 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4104 mutex_exit(&sc->tx_pkt_mtx); 4105 4106 /* fire-up TX now that allocations have been done */ 4107 s = splnet(); 4108 CLR(ifp->if_flags, IFF_OACTIVE); 4109 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4110 bnx_start(ifp); 4111 splx(s); 4112 } 4113 4114 /****************************************************************************/ 4115 /* Initialize the TX context memory. */ 4116 /* */ 4117 /* Returns: */ 4118 /* Nothing */ 4119 /****************************************************************************/ 4120 void 4121 bnx_init_tx_context(struct bnx_softc *sc) 4122 { 4123 uint32_t val; 4124 4125 /* Initialize the context ID for an L2 TX chain. */ 4126 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4127 /* Set the CID type to support an L2 connection. */ 4128 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4129 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4130 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4131 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4132 4133 /* Point the hardware to the first page in the chain. */ 4134 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4135 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4136 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4137 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4138 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4139 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4140 } else { 4141 /* Set the CID type to support an L2 connection. */ 4142 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4143 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4144 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4145 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4146 4147 /* Point the hardware to the first page in the chain. */ 4148 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4149 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4150 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4151 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4152 } 4153 } 4154 4155 4156 /****************************************************************************/ 4157 /* Allocate memory and initialize the TX data structures. */ 4158 /* */ 4159 /* Returns: */ 4160 /* 0 for success, positive value for failure. */ 4161 /****************************************************************************/ 4162 int 4163 bnx_init_tx_chain(struct bnx_softc *sc) 4164 { 4165 struct tx_bd *txbd; 4166 uint32_t addr; 4167 int i, rc = 0; 4168 4169 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4170 4171 /* Set the initial TX producer/consumer indices. */ 4172 sc->tx_prod = 0; 4173 sc->tx_cons = 0; 4174 sc->tx_prod_bseq = 0; 4175 sc->used_tx_bd = 0; 4176 sc->max_tx_bd = USABLE_TX_BD; 4177 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4178 DBRUNIF(1, sc->tx_full_count = 0); 4179 4180 /* 4181 * The NetXtreme II supports a linked-list structure called 4182 * a Buffer Descriptor Chain (or BD chain). A BD chain 4183 * consists of a series of 1 or more chain pages, each of which 4184 * consists of a fixed number of BD entries. 4185 * The last BD entry on each page is a pointer to the next page 4186 * in the chain, and the last pointer in the BD chain 4187 * points back to the beginning of the chain. 4188 */ 4189 4190 /* Set the TX next pointer chain entries. */ 4191 for (i = 0; i < TX_PAGES; i++) { 4192 int j; 4193 4194 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4195 4196 /* Check if we've reached the last page. */ 4197 if (i == (TX_PAGES - 1)) 4198 j = 0; 4199 else 4200 j = i + 1; 4201 4202 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4203 txbd->tx_bd_haddr_lo = addr; 4204 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4205 txbd->tx_bd_haddr_hi = addr; 4206 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4207 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4208 } 4209 4210 /* 4211 * Initialize the context ID for an L2 TX chain. 4212 */ 4213 bnx_init_tx_context(sc); 4214 4215 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4216 4217 return rc; 4218 } 4219 4220 /****************************************************************************/ 4221 /* Free memory and clear the TX data structures. */ 4222 /* */ 4223 /* Returns: */ 4224 /* Nothing. */ 4225 /****************************************************************************/ 4226 void 4227 bnx_free_tx_chain(struct bnx_softc *sc) 4228 { 4229 struct bnx_pkt *pkt; 4230 int i; 4231 4232 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4233 4234 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4235 mutex_enter(&sc->tx_pkt_mtx); 4236 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4237 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4238 mutex_exit(&sc->tx_pkt_mtx); 4239 4240 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4241 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4242 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4243 4244 m_freem(pkt->pkt_mbuf); 4245 DBRUNIF(1, sc->tx_mbuf_alloc--); 4246 4247 mutex_enter(&sc->tx_pkt_mtx); 4248 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4249 } 4250 mutex_exit(&sc->tx_pkt_mtx); 4251 4252 /* Clear each TX chain page. */ 4253 for (i = 0; i < TX_PAGES; i++) { 4254 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4255 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4256 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4257 } 4258 4259 sc->used_tx_bd = 0; 4260 4261 /* Check if we lost any mbufs in the process. */ 4262 DBRUNIF((sc->tx_mbuf_alloc), 4263 aprint_error_dev(sc->bnx_dev, 4264 "Memory leak! Lost %d mbufs from tx chain!\n", 4265 sc->tx_mbuf_alloc)); 4266 4267 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4268 } 4269 4270 /****************************************************************************/ 4271 /* Initialize the RX context memory. */ 4272 /* */ 4273 /* Returns: */ 4274 /* Nothing */ 4275 /****************************************************************************/ 4276 void 4277 bnx_init_rx_context(struct bnx_softc *sc) 4278 { 4279 uint32_t val; 4280 4281 /* Initialize the context ID for an L2 RX chain. */ 4282 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4283 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4284 4285 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4286 val |= 0x000000ff; 4287 4288 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4289 4290 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4291 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4292 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4293 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4294 } 4295 4296 /* Point the hardware to the first page in the chain. */ 4297 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4298 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4299 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4300 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4301 } 4302 4303 /****************************************************************************/ 4304 /* Allocate memory and initialize the RX data structures. */ 4305 /* */ 4306 /* Returns: */ 4307 /* 0 for success, positive value for failure. */ 4308 /****************************************************************************/ 4309 int 4310 bnx_init_rx_chain(struct bnx_softc *sc) 4311 { 4312 struct rx_bd *rxbd; 4313 int i, rc = 0; 4314 uint16_t prod, chain_prod; 4315 uint32_t prod_bseq, addr; 4316 4317 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4318 4319 /* Initialize the RX producer and consumer indices. */ 4320 sc->rx_prod = 0; 4321 sc->rx_cons = 0; 4322 sc->rx_prod_bseq = 0; 4323 sc->free_rx_bd = USABLE_RX_BD; 4324 sc->max_rx_bd = USABLE_RX_BD; 4325 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4326 DBRUNIF(1, sc->rx_empty_count = 0); 4327 4328 /* Initialize the RX next pointer chain entries. */ 4329 for (i = 0; i < RX_PAGES; i++) { 4330 int j; 4331 4332 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4333 4334 /* Check if we've reached the last page. */ 4335 if (i == (RX_PAGES - 1)) 4336 j = 0; 4337 else 4338 j = i + 1; 4339 4340 /* Setup the chain page pointers. */ 4341 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4342 rxbd->rx_bd_haddr_hi = addr; 4343 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4344 rxbd->rx_bd_haddr_lo = addr; 4345 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4346 0, BNX_RX_CHAIN_PAGE_SZ, 4347 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4348 } 4349 4350 /* Allocate mbuf clusters for the rx_bd chain. */ 4351 prod = prod_bseq = 0; 4352 chain_prod = RX_CHAIN_IDX(prod); 4353 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4354 BNX_PRINTF(sc, 4355 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4356 } 4357 4358 /* Save the RX chain producer index. */ 4359 sc->rx_prod = prod; 4360 sc->rx_prod_bseq = prod_bseq; 4361 4362 for (i = 0; i < RX_PAGES; i++) 4363 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4364 sc->rx_bd_chain_map[i]->dm_mapsize, 4365 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4366 4367 /* Tell the chip about the waiting rx_bd's. */ 4368 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4369 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4370 4371 bnx_init_rx_context(sc); 4372 4373 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4374 4375 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4376 4377 return rc; 4378 } 4379 4380 /****************************************************************************/ 4381 /* Free memory and clear the RX data structures. */ 4382 /* */ 4383 /* Returns: */ 4384 /* Nothing. */ 4385 /****************************************************************************/ 4386 void 4387 bnx_free_rx_chain(struct bnx_softc *sc) 4388 { 4389 int i; 4390 4391 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4392 4393 /* Free any mbufs still in the RX mbuf chain. */ 4394 for (i = 0; i < TOTAL_RX_BD; i++) { 4395 if (sc->rx_mbuf_ptr[i] != NULL) { 4396 if (sc->rx_mbuf_map[i] != NULL) { 4397 bus_dmamap_sync(sc->bnx_dmatag, 4398 sc->rx_mbuf_map[i], 0, 4399 sc->rx_mbuf_map[i]->dm_mapsize, 4400 BUS_DMASYNC_POSTREAD); 4401 bus_dmamap_unload(sc->bnx_dmatag, 4402 sc->rx_mbuf_map[i]); 4403 } 4404 m_freem(sc->rx_mbuf_ptr[i]); 4405 sc->rx_mbuf_ptr[i] = NULL; 4406 DBRUNIF(1, sc->rx_mbuf_alloc--); 4407 } 4408 } 4409 4410 /* Clear each RX chain page. */ 4411 for (i = 0; i < RX_PAGES; i++) 4412 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4413 4414 sc->free_rx_bd = sc->max_rx_bd; 4415 4416 /* Check if we lost any mbufs in the process. */ 4417 DBRUNIF((sc->rx_mbuf_alloc), 4418 aprint_error_dev(sc->bnx_dev, 4419 "Memory leak! Lost %d mbufs from rx chain!\n", 4420 sc->rx_mbuf_alloc)); 4421 4422 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4423 } 4424 4425 /****************************************************************************/ 4426 /* Set media options. */ 4427 /* */ 4428 /* Returns: */ 4429 /* 0 for success, positive value for failure. */ 4430 /****************************************************************************/ 4431 int 4432 bnx_ifmedia_upd(struct ifnet *ifp) 4433 { 4434 struct bnx_softc *sc; 4435 struct mii_data *mii; 4436 int rc = 0; 4437 4438 sc = ifp->if_softc; 4439 4440 mii = &sc->bnx_mii; 4441 sc->bnx_link = 0; 4442 if (mii->mii_instance) { 4443 struct mii_softc *miisc; 4444 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4445 mii_phy_reset(miisc); 4446 } 4447 mii_mediachg(mii); 4448 4449 return rc; 4450 } 4451 4452 /****************************************************************************/ 4453 /* Reports current media status. */ 4454 /* */ 4455 /* Returns: */ 4456 /* Nothing. */ 4457 /****************************************************************************/ 4458 void 4459 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4460 { 4461 struct bnx_softc *sc; 4462 struct mii_data *mii; 4463 int s; 4464 4465 sc = ifp->if_softc; 4466 4467 s = splnet(); 4468 4469 mii = &sc->bnx_mii; 4470 4471 mii_pollstat(mii); 4472 ifmr->ifm_status = mii->mii_media_status; 4473 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4474 sc->bnx_flowflags; 4475 4476 splx(s); 4477 } 4478 4479 /****************************************************************************/ 4480 /* Handles PHY generated interrupt events. */ 4481 /* */ 4482 /* Returns: */ 4483 /* Nothing. */ 4484 /****************************************************************************/ 4485 void 4486 bnx_phy_intr(struct bnx_softc *sc) 4487 { 4488 uint32_t new_link_state, old_link_state; 4489 4490 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4491 BUS_DMASYNC_POSTREAD); 4492 new_link_state = sc->status_block->status_attn_bits & 4493 STATUS_ATTN_BITS_LINK_STATE; 4494 old_link_state = sc->status_block->status_attn_bits_ack & 4495 STATUS_ATTN_BITS_LINK_STATE; 4496 4497 /* Handle any changes if the link state has changed. */ 4498 if (new_link_state != old_link_state) { 4499 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4500 4501 sc->bnx_link = 0; 4502 callout_stop(&sc->bnx_timeout); 4503 bnx_tick(sc); 4504 4505 /* Update the status_attn_bits_ack field in the status block. */ 4506 if (new_link_state) { 4507 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4508 STATUS_ATTN_BITS_LINK_STATE); 4509 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4510 } else { 4511 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4512 STATUS_ATTN_BITS_LINK_STATE); 4513 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4514 } 4515 } 4516 4517 /* Acknowledge the link change interrupt. */ 4518 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4519 } 4520 4521 /****************************************************************************/ 4522 /* Handles received frame interrupt events. */ 4523 /* */ 4524 /* Returns: */ 4525 /* Nothing. */ 4526 /****************************************************************************/ 4527 void 4528 bnx_rx_intr(struct bnx_softc *sc) 4529 { 4530 struct status_block *sblk = sc->status_block; 4531 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4532 uint16_t hw_cons, sw_cons, sw_chain_cons; 4533 uint16_t sw_prod, sw_chain_prod; 4534 uint32_t sw_prod_bseq; 4535 struct l2_fhdr *l2fhdr; 4536 int i; 4537 4538 DBRUNIF(1, sc->rx_interrupts++); 4539 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4540 BUS_DMASYNC_POSTREAD); 4541 4542 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4543 for (i = 0; i < RX_PAGES; i++) 4544 bus_dmamap_sync(sc->bnx_dmatag, 4545 sc->rx_bd_chain_map[i], 0, 4546 sc->rx_bd_chain_map[i]->dm_mapsize, 4547 BUS_DMASYNC_POSTWRITE); 4548 4549 /* Get the hardware's view of the RX consumer index. */ 4550 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4551 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4552 hw_cons++; 4553 4554 /* Get working copies of the driver's view of the RX indices. */ 4555 sw_cons = sc->rx_cons; 4556 sw_prod = sc->rx_prod; 4557 sw_prod_bseq = sc->rx_prod_bseq; 4558 4559 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4560 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4561 __func__, sw_prod, sw_cons, sw_prod_bseq); 4562 4563 /* Prevent speculative reads from getting ahead of the status block. */ 4564 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4565 BUS_SPACE_BARRIER_READ); 4566 4567 /* Update some debug statistics counters */ 4568 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4569 sc->rx_low_watermark = sc->free_rx_bd); 4570 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4571 4572 /* 4573 * Scan through the receive chain as long 4574 * as there is work to do. 4575 */ 4576 while (sw_cons != hw_cons) { 4577 struct mbuf *m; 4578 struct rx_bd *rxbd __diagused; 4579 unsigned int len; 4580 uint32_t status; 4581 4582 /* Convert the producer/consumer indices to an actual 4583 * rx_bd index. 4584 */ 4585 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4586 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4587 4588 /* Get the used rx_bd. */ 4589 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4590 sc->free_rx_bd++; 4591 4592 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4593 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4594 4595 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4596 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4597 #ifdef DIAGNOSTIC 4598 /* Validate that this is the last rx_bd. */ 4599 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4600 printf("%s: Unexpected mbuf found in " 4601 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4602 sw_chain_cons); 4603 } 4604 #endif 4605 4606 /* DRC - ToDo: If the received packet is small, say 4607 * less than 128 bytes, allocate a new mbuf 4608 * here, copy the data to that mbuf, and 4609 * recycle the mapped jumbo frame. 4610 */ 4611 4612 /* Unmap the mbuf from DMA space. */ 4613 #ifdef DIAGNOSTIC 4614 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4615 printf("invalid map sw_cons 0x%x " 4616 "sw_prod 0x%x " 4617 "sw_chain_cons 0x%x " 4618 "sw_chain_prod 0x%x " 4619 "hw_cons 0x%x " 4620 "TOTAL_RX_BD_PER_PAGE 0x%x " 4621 "TOTAL_RX_BD 0x%x\n", 4622 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4623 hw_cons, 4624 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4625 } 4626 #endif 4627 bus_dmamap_sync(sc->bnx_dmatag, 4628 sc->rx_mbuf_map[sw_chain_cons], 0, 4629 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4630 BUS_DMASYNC_POSTREAD); 4631 bus_dmamap_unload(sc->bnx_dmatag, 4632 sc->rx_mbuf_map[sw_chain_cons]); 4633 4634 /* Remove the mbuf from the driver's chain. */ 4635 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4636 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4637 4638 /* 4639 * Frames received on the NetXteme II are prepended 4640 * with the l2_fhdr structure which provides status 4641 * information about the received frame (including 4642 * VLAN tags and checksum info) and are also 4643 * automatically adjusted to align the IP header 4644 * (i.e. two null bytes are inserted before the 4645 * Ethernet header). 4646 */ 4647 l2fhdr = mtod(m, struct l2_fhdr *); 4648 4649 len = l2fhdr->l2_fhdr_pkt_len; 4650 status = l2fhdr->l2_fhdr_status; 4651 4652 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4653 aprint_error("Simulating l2_fhdr status error.\n"); 4654 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4655 4656 /* Watch for unusual sized frames. */ 4657 DBRUNIF(((len < BNX_MIN_MTU) || 4658 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4659 aprint_error_dev(sc->bnx_dev, 4660 "Unusual frame size found. " 4661 "Min(%d), Actual(%d), Max(%d)\n", 4662 (int)BNX_MIN_MTU, len, 4663 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4664 4665 bnx_dump_mbuf(sc, m); 4666 bnx_breakpoint(sc)); 4667 4668 len -= ETHER_CRC_LEN; 4669 4670 /* Check the received frame for errors. */ 4671 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4672 L2_FHDR_ERRORS_PHY_DECODE | 4673 L2_FHDR_ERRORS_ALIGNMENT | 4674 L2_FHDR_ERRORS_TOO_SHORT | 4675 L2_FHDR_ERRORS_GIANT_FRAME)) || 4676 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4677 len > 4678 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4679 if_statinc(ifp, if_ierrors); 4680 DBRUNIF(1, sc->l2fhdr_status_errors++); 4681 4682 /* Reuse the mbuf for a new frame. */ 4683 if (bnx_add_buf(sc, m, &sw_prod, 4684 &sw_chain_prod, &sw_prod_bseq)) { 4685 DBRUNIF(1, bnx_breakpoint(sc)); 4686 panic("%s: Can't reuse RX mbuf!\n", 4687 device_xname(sc->bnx_dev)); 4688 } 4689 continue; 4690 } 4691 4692 /* 4693 * Get a new mbuf for the rx_bd. If no new 4694 * mbufs are available then reuse the current mbuf, 4695 * log an ierror on the interface, and generate 4696 * an error in the system log. 4697 */ 4698 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4699 &sw_prod_bseq)) { 4700 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4701 "Failed to allocate " 4702 "new mbuf, incoming frame dropped!\n")); 4703 4704 if_statinc(ifp, if_ierrors); 4705 4706 /* Try and reuse the exisitng mbuf. */ 4707 if (bnx_add_buf(sc, m, &sw_prod, 4708 &sw_chain_prod, &sw_prod_bseq)) { 4709 DBRUNIF(1, bnx_breakpoint(sc)); 4710 panic("%s: Double mbuf allocation " 4711 "failure!", 4712 device_xname(sc->bnx_dev)); 4713 } 4714 continue; 4715 } 4716 4717 /* Skip over the l2_fhdr when passing the data up 4718 * the stack. 4719 */ 4720 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4721 4722 /* Adjust the pckt length to match the received data. */ 4723 m->m_pkthdr.len = m->m_len = len; 4724 4725 /* Send the packet to the appropriate interface. */ 4726 m_set_rcvif(m, ifp); 4727 4728 DBRUN(BNX_VERBOSE_RECV, 4729 struct ether_header *eh; 4730 eh = mtod(m, struct ether_header *); 4731 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4732 __func__, ether_sprintf(eh->ether_dhost), 4733 ether_sprintf(eh->ether_shost), 4734 htons(eh->ether_type))); 4735 4736 /* Validate the checksum. */ 4737 4738 /* Check for an IP datagram. */ 4739 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4740 /* Check if the IP checksum is valid. */ 4741 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4742 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4743 #ifdef BNX_DEBUG 4744 else 4745 DBPRINT(sc, BNX_WARN_SEND, 4746 "%s(): Invalid IP checksum " 4747 "= 0x%04X!\n", 4748 __func__, 4749 l2fhdr->l2_fhdr_ip_xsum 4750 ); 4751 #endif 4752 } 4753 4754 /* Check for a valid TCP/UDP frame. */ 4755 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4756 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4757 /* Check for a good TCP/UDP checksum. */ 4758 if ((status & 4759 (L2_FHDR_ERRORS_TCP_XSUM | 4760 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4761 m->m_pkthdr.csum_flags |= 4762 M_CSUM_TCPv4 | 4763 M_CSUM_UDPv4; 4764 } else { 4765 DBPRINT(sc, BNX_WARN_SEND, 4766 "%s(): Invalid TCP/UDP " 4767 "checksum = 0x%04X!\n", 4768 __func__, 4769 l2fhdr->l2_fhdr_tcp_udp_xsum); 4770 } 4771 } 4772 4773 /* 4774 * If we received a packet with a vlan tag, 4775 * attach that information to the packet. 4776 */ 4777 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4778 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4779 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4780 } 4781 4782 /* Pass the mbuf off to the upper layers. */ 4783 4784 DBPRINT(sc, BNX_VERBOSE_RECV, 4785 "%s(): Passing received frame up.\n", __func__); 4786 if_percpuq_enqueue(ifp->if_percpuq, m); 4787 DBRUNIF(1, sc->rx_mbuf_alloc--); 4788 4789 } 4790 4791 sw_cons = NEXT_RX_BD(sw_cons); 4792 4793 /* Refresh hw_cons to see if there's new work */ 4794 if (sw_cons == hw_cons) { 4795 hw_cons = sc->hw_rx_cons = 4796 sblk->status_rx_quick_consumer_index0; 4797 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4798 USABLE_RX_BD_PER_PAGE) 4799 hw_cons++; 4800 } 4801 4802 /* Prevent speculative reads from getting ahead of 4803 * the status block. 4804 */ 4805 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4806 BUS_SPACE_BARRIER_READ); 4807 } 4808 4809 for (i = 0; i < RX_PAGES; i++) 4810 bus_dmamap_sync(sc->bnx_dmatag, 4811 sc->rx_bd_chain_map[i], 0, 4812 sc->rx_bd_chain_map[i]->dm_mapsize, 4813 BUS_DMASYNC_PREWRITE); 4814 4815 sc->rx_cons = sw_cons; 4816 sc->rx_prod = sw_prod; 4817 sc->rx_prod_bseq = sw_prod_bseq; 4818 4819 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4820 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4821 4822 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4823 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4824 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4825 } 4826 4827 /****************************************************************************/ 4828 /* Handles transmit completion interrupt events. */ 4829 /* */ 4830 /* Returns: */ 4831 /* Nothing. */ 4832 /****************************************************************************/ 4833 void 4834 bnx_tx_intr(struct bnx_softc *sc) 4835 { 4836 struct status_block *sblk = sc->status_block; 4837 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4838 struct bnx_pkt *pkt; 4839 bus_dmamap_t map; 4840 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4841 4842 DBRUNIF(1, sc->tx_interrupts++); 4843 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4844 BUS_DMASYNC_POSTREAD); 4845 4846 /* Get the hardware's view of the TX consumer index. */ 4847 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4848 4849 /* Skip to the next entry if this is a chain page pointer. */ 4850 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4851 hw_tx_cons++; 4852 4853 sw_tx_cons = sc->tx_cons; 4854 4855 /* Prevent speculative reads from getting ahead of the status block. */ 4856 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4857 BUS_SPACE_BARRIER_READ); 4858 4859 /* Cycle through any completed TX chain page entries. */ 4860 while (sw_tx_cons != hw_tx_cons) { 4861 #ifdef BNX_DEBUG 4862 struct tx_bd *txbd = NULL; 4863 #endif 4864 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4865 4866 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4867 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4868 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4869 4870 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4871 aprint_error_dev(sc->bnx_dev, 4872 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4873 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4874 4875 DBRUNIF(1, txbd = &sc->tx_bd_chain 4876 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4877 4878 DBRUNIF((txbd == NULL), 4879 aprint_error_dev(sc->bnx_dev, 4880 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4881 bnx_breakpoint(sc)); 4882 4883 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4884 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4885 4886 4887 mutex_enter(&sc->tx_pkt_mtx); 4888 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4889 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4890 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4891 mutex_exit(&sc->tx_pkt_mtx); 4892 /* 4893 * Free the associated mbuf. Remember 4894 * that only the last tx_bd of a packet 4895 * has an mbuf pointer and DMA map. 4896 */ 4897 map = pkt->pkt_dmamap; 4898 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4899 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4900 bus_dmamap_unload(sc->bnx_dmatag, map); 4901 4902 m_freem(pkt->pkt_mbuf); 4903 DBRUNIF(1, sc->tx_mbuf_alloc--); 4904 4905 if_statinc(ifp, if_opackets); 4906 4907 mutex_enter(&sc->tx_pkt_mtx); 4908 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4909 } 4910 mutex_exit(&sc->tx_pkt_mtx); 4911 4912 sc->used_tx_bd--; 4913 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4914 __FILE__, __LINE__, sc->used_tx_bd); 4915 4916 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4917 4918 /* Refresh hw_cons to see if there's new work. */ 4919 hw_tx_cons = sc->hw_tx_cons = 4920 sblk->status_tx_quick_consumer_index0; 4921 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4922 USABLE_TX_BD_PER_PAGE) 4923 hw_tx_cons++; 4924 4925 /* Prevent speculative reads from getting ahead of 4926 * the status block. 4927 */ 4928 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4929 BUS_SPACE_BARRIER_READ); 4930 } 4931 4932 /* Clear the TX timeout timer. */ 4933 ifp->if_timer = 0; 4934 4935 /* Clear the tx hardware queue full flag. */ 4936 if (sc->used_tx_bd < sc->max_tx_bd) { 4937 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4938 aprint_debug_dev(sc->bnx_dev, 4939 "Open TX chain! %d/%d (used/total)\n", 4940 sc->used_tx_bd, sc->max_tx_bd)); 4941 ifp->if_flags &= ~IFF_OACTIVE; 4942 } 4943 4944 sc->tx_cons = sw_tx_cons; 4945 } 4946 4947 /****************************************************************************/ 4948 /* Disables interrupt generation. */ 4949 /* */ 4950 /* Returns: */ 4951 /* Nothing. */ 4952 /****************************************************************************/ 4953 void 4954 bnx_disable_intr(struct bnx_softc *sc) 4955 { 4956 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4957 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4958 } 4959 4960 /****************************************************************************/ 4961 /* Enables interrupt generation. */ 4962 /* */ 4963 /* Returns: */ 4964 /* Nothing. */ 4965 /****************************************************************************/ 4966 void 4967 bnx_enable_intr(struct bnx_softc *sc) 4968 { 4969 uint32_t val; 4970 4971 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4972 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4973 4974 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4975 sc->last_status_idx); 4976 4977 val = REG_RD(sc, BNX_HC_COMMAND); 4978 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4979 } 4980 4981 /****************************************************************************/ 4982 /* Handles controller initialization. */ 4983 /* */ 4984 /****************************************************************************/ 4985 int 4986 bnx_init(struct ifnet *ifp) 4987 { 4988 struct bnx_softc *sc = ifp->if_softc; 4989 uint32_t ether_mtu; 4990 int s, error = 0; 4991 4992 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4993 4994 s = splnet(); 4995 4996 bnx_stop(ifp, 0); 4997 4998 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4999 aprint_error_dev(sc->bnx_dev, 5000 "Controller reset failed!\n"); 5001 goto bnx_init_exit; 5002 } 5003 5004 if ((error = bnx_chipinit(sc)) != 0) { 5005 aprint_error_dev(sc->bnx_dev, 5006 "Controller initialization failed!\n"); 5007 goto bnx_init_exit; 5008 } 5009 5010 if ((error = bnx_blockinit(sc)) != 0) { 5011 aprint_error_dev(sc->bnx_dev, 5012 "Block initialization failed!\n"); 5013 goto bnx_init_exit; 5014 } 5015 5016 /* Calculate and program the Ethernet MRU size. */ 5017 if (ifp->if_mtu <= ETHERMTU) { 5018 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 5019 sc->mbuf_alloc_size = MCLBYTES; 5020 } else { 5021 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 5022 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 5023 } 5024 5025 5026 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 5027 5028 /* 5029 * Program the MRU and enable Jumbo frame 5030 * support. 5031 */ 5032 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 5033 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 5034 5035 /* Calculate the RX Ethernet frame size for rx_bd's. */ 5036 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 5037 5038 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 5039 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 5040 sc->mbuf_alloc_size, sc->max_frame_size); 5041 5042 /* Program appropriate promiscuous/multicast filtering. */ 5043 bnx_iff(sc); 5044 5045 /* Init RX buffer descriptor chain. */ 5046 bnx_init_rx_chain(sc); 5047 5048 /* Init TX buffer descriptor chain. */ 5049 bnx_init_tx_chain(sc); 5050 5051 /* Enable host interrupts. */ 5052 bnx_enable_intr(sc); 5053 5054 mii_ifmedia_change(&sc->bnx_mii); 5055 5056 SET(ifp->if_flags, IFF_RUNNING); 5057 CLR(ifp->if_flags, IFF_OACTIVE); 5058 5059 callout_schedule(&sc->bnx_timeout, hz); 5060 5061 bnx_init_exit: 5062 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5063 5064 splx(s); 5065 5066 return error; 5067 } 5068 5069 void 5070 bnx_mgmt_init(struct bnx_softc *sc) 5071 { 5072 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5073 uint32_t val; 5074 5075 /* Check if the driver is still running and bail out if it is. */ 5076 if (ifp->if_flags & IFF_RUNNING) 5077 goto bnx_mgmt_init_exit; 5078 5079 /* Initialize the on-boards CPUs */ 5080 bnx_init_cpus(sc); 5081 5082 val = (BCM_PAGE_BITS - 8) << 24; 5083 REG_WR(sc, BNX_RV2P_CONFIG, val); 5084 5085 /* Enable all critical blocks in the MAC. */ 5086 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5087 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5088 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5089 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5090 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5091 DELAY(20); 5092 5093 mii_ifmedia_change(&sc->bnx_mii); 5094 5095 bnx_mgmt_init_exit: 5096 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5097 } 5098 5099 /****************************************************************************/ 5100 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5101 /* memory visible to the controller. */ 5102 /* */ 5103 /* Returns: */ 5104 /* 0 for success, positive value for failure. */ 5105 /****************************************************************************/ 5106 int 5107 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5108 { 5109 struct bnx_pkt *pkt; 5110 bus_dmamap_t map; 5111 struct tx_bd *txbd = NULL; 5112 uint16_t vlan_tag = 0, flags = 0; 5113 uint16_t chain_prod, prod; 5114 #ifdef BNX_DEBUG 5115 uint16_t debug_prod; 5116 #endif 5117 uint32_t addr, prod_bseq; 5118 int i, error; 5119 bool remap = true; 5120 5121 mutex_enter(&sc->tx_pkt_mtx); 5122 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5123 if (pkt == NULL) { 5124 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5125 mutex_exit(&sc->tx_pkt_mtx); 5126 return ENETDOWN; 5127 } 5128 5129 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5130 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5131 workqueue_enqueue(sc->bnx_wq, &sc->bnx_wk, NULL); 5132 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5133 } 5134 5135 mutex_exit(&sc->tx_pkt_mtx); 5136 return ENOMEM; 5137 } 5138 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5139 mutex_exit(&sc->tx_pkt_mtx); 5140 5141 /* Transfer any checksum offload flags to the bd. */ 5142 if (m->m_pkthdr.csum_flags) { 5143 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5144 flags |= TX_BD_FLAGS_IP_CKSUM; 5145 if (m->m_pkthdr.csum_flags & 5146 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5147 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5148 } 5149 5150 /* Transfer any VLAN tags to the bd. */ 5151 if (vlan_has_tag(m)) { 5152 flags |= TX_BD_FLAGS_VLAN_TAG; 5153 vlan_tag = vlan_get_tag(m); 5154 } 5155 5156 /* Map the mbuf into DMAable memory. */ 5157 prod = sc->tx_prod; 5158 chain_prod = TX_CHAIN_IDX(prod); 5159 map = pkt->pkt_dmamap; 5160 5161 /* Map the mbuf into our DMA address space. */ 5162 retry: 5163 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5164 if (__predict_false(error)) { 5165 if (error == EFBIG) { 5166 if (remap == true) { 5167 struct mbuf *newm; 5168 5169 remap = false; 5170 newm = m_defrag(m, M_NOWAIT); 5171 if (newm != NULL) { 5172 m = newm; 5173 goto retry; 5174 } 5175 } 5176 } 5177 sc->tx_dma_map_failures++; 5178 goto maperr; 5179 } 5180 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5181 BUS_DMASYNC_PREWRITE); 5182 /* Make sure there's room in the chain */ 5183 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 5184 error = ENOMEM; 5185 goto nospace; 5186 } 5187 5188 /* prod points to an empty tx_bd at this point. */ 5189 prod_bseq = sc->tx_prod_bseq; 5190 #ifdef BNX_DEBUG 5191 debug_prod = chain_prod; 5192 #endif 5193 DBPRINT(sc, BNX_INFO_SEND, 5194 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5195 "prod_bseq = 0x%08X\n", 5196 __func__, prod, chain_prod, prod_bseq); 5197 5198 /* 5199 * Cycle through each mbuf segment that makes up 5200 * the outgoing frame, gathering the mapping info 5201 * for that segment and creating a tx_bd for the 5202 * mbuf. 5203 */ 5204 for (i = 0; i < map->dm_nsegs ; i++) { 5205 chain_prod = TX_CHAIN_IDX(prod); 5206 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5207 5208 addr = (uint32_t)map->dm_segs[i].ds_addr; 5209 txbd->tx_bd_haddr_lo = addr; 5210 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5211 txbd->tx_bd_haddr_hi = addr; 5212 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5213 txbd->tx_bd_vlan_tag = vlan_tag; 5214 txbd->tx_bd_flags = flags; 5215 prod_bseq += map->dm_segs[i].ds_len; 5216 if (i == 0) 5217 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5218 prod = NEXT_TX_BD(prod); 5219 } 5220 5221 /* Set the END flag on the last TX buffer descriptor. */ 5222 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5223 5224 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5225 5226 DBPRINT(sc, BNX_INFO_SEND, 5227 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5228 "prod_bseq = 0x%08X\n", 5229 __func__, prod, chain_prod, prod_bseq); 5230 5231 pkt->pkt_mbuf = m; 5232 pkt->pkt_end_desc = chain_prod; 5233 5234 mutex_enter(&sc->tx_pkt_mtx); 5235 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5236 mutex_exit(&sc->tx_pkt_mtx); 5237 5238 sc->used_tx_bd += map->dm_nsegs; 5239 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5240 __FILE__, __LINE__, sc->used_tx_bd); 5241 5242 /* Update some debug statistics counters */ 5243 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5244 sc->tx_hi_watermark = sc->used_tx_bd); 5245 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5246 DBRUNIF(1, sc->tx_mbuf_alloc++); 5247 5248 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5249 map->dm_nsegs)); 5250 5251 /* prod points to the next free tx_bd at this point. */ 5252 sc->tx_prod = prod; 5253 sc->tx_prod_bseq = prod_bseq; 5254 5255 return 0; 5256 5257 5258 nospace: 5259 bus_dmamap_unload(sc->bnx_dmatag, map); 5260 maperr: 5261 mutex_enter(&sc->tx_pkt_mtx); 5262 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5263 mutex_exit(&sc->tx_pkt_mtx); 5264 5265 return error; 5266 } 5267 5268 /****************************************************************************/ 5269 /* Main transmit routine. */ 5270 /* */ 5271 /* Returns: */ 5272 /* Nothing. */ 5273 /****************************************************************************/ 5274 void 5275 bnx_start(struct ifnet *ifp) 5276 { 5277 struct bnx_softc *sc = ifp->if_softc; 5278 struct mbuf *m_head = NULL; 5279 int count = 0, error; 5280 #ifdef BNX_DEBUG 5281 uint16_t tx_chain_prod; 5282 #endif 5283 5284 /* If there's no link or the transmit queue is empty then just exit. */ 5285 if (!sc->bnx_link 5286 ||(ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) { 5287 DBPRINT(sc, BNX_INFO_SEND, 5288 "%s(): output active or device not running.\n", __func__); 5289 goto bnx_start_exit; 5290 } 5291 5292 /* prod points to the next free tx_bd. */ 5293 #ifdef BNX_DEBUG 5294 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5295 #endif 5296 5297 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5298 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5299 "used_tx %d max_tx %d\n", 5300 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5301 sc->used_tx_bd, sc->max_tx_bd); 5302 5303 /* 5304 * Keep adding entries while there is space in the ring. 5305 */ 5306 while (sc->used_tx_bd < sc->max_tx_bd) { 5307 /* Check for any frames to send. */ 5308 IFQ_POLL(&ifp->if_snd, m_head); 5309 if (m_head == NULL) 5310 break; 5311 5312 /* 5313 * Pack the data into the transmit ring. If we 5314 * don't have room, set the OACTIVE flag to wait 5315 * for the NIC to drain the chain. 5316 */ 5317 if ((error = bnx_tx_encap(sc, m_head))) { 5318 if (error == ENOMEM) { 5319 ifp->if_flags |= IFF_OACTIVE; 5320 DBPRINT(sc, BNX_INFO_SEND, 5321 "TX chain is closed for " 5322 "business! Total tx_bd used = %d\n", 5323 sc->used_tx_bd); 5324 break; 5325 } else { 5326 /* Permanent error for the mbuf, drop it */ 5327 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5328 m_freem(m_head); 5329 DBPRINT(sc, BNX_INFO_SEND, 5330 "mbuf load error %d, dropped\n", error); 5331 continue; 5332 } 5333 } 5334 5335 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5336 count++; 5337 5338 /* Send a copy of the frame to any BPF listeners. */ 5339 bpf_mtap(ifp, m_head, BPF_D_OUT); 5340 } 5341 5342 if (count == 0) { 5343 /* no packets were dequeued */ 5344 DBPRINT(sc, BNX_VERBOSE_SEND, 5345 "%s(): No packets were dequeued\n", __func__); 5346 goto bnx_start_exit; 5347 } 5348 5349 /* Update the driver's counters. */ 5350 #ifdef BNX_DEBUG 5351 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5352 #endif 5353 5354 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5355 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5356 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5357 5358 /* Start the transmit. */ 5359 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5360 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5361 5362 /* Set the tx timeout. */ 5363 ifp->if_timer = BNX_TX_TIMEOUT; 5364 5365 bnx_start_exit: 5366 return; 5367 } 5368 5369 /****************************************************************************/ 5370 /* Handles any IOCTL calls from the operating system. */ 5371 /* */ 5372 /* Returns: */ 5373 /* 0 for success, positive value for failure. */ 5374 /****************************************************************************/ 5375 int 5376 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5377 { 5378 struct bnx_softc *sc = ifp->if_softc; 5379 struct ifreq *ifr = (struct ifreq *) data; 5380 struct mii_data *mii = &sc->bnx_mii; 5381 int s, error = 0; 5382 5383 s = splnet(); 5384 5385 switch (command) { 5386 case SIOCSIFFLAGS: 5387 if ((error = ifioctl_common(ifp, command, data)) != 0) 5388 break; 5389 /* XXX set an ifflags callback and let ether_ioctl 5390 * handle all of this. 5391 */ 5392 if (ISSET(ifp->if_flags, IFF_UP)) { 5393 if (ifp->if_flags & IFF_RUNNING) 5394 error = ENETRESET; 5395 else 5396 bnx_init(ifp); 5397 } else if (ifp->if_flags & IFF_RUNNING) 5398 bnx_stop(ifp, 1); 5399 break; 5400 5401 case SIOCSIFMEDIA: 5402 /* Flow control requires full-duplex mode. */ 5403 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5404 (ifr->ifr_media & IFM_FDX) == 0) 5405 ifr->ifr_media &= ~IFM_ETH_FMASK; 5406 5407 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5408 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5409 /* We can do both TXPAUSE and RXPAUSE. */ 5410 ifr->ifr_media |= 5411 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5412 } 5413 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5414 } 5415 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5416 sc->bnx_phy_flags); 5417 5418 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5419 break; 5420 5421 default: 5422 error = ether_ioctl(ifp, command, data); 5423 } 5424 5425 if (error == ENETRESET) { 5426 if (ifp->if_flags & IFF_RUNNING) 5427 bnx_iff(sc); 5428 error = 0; 5429 } 5430 5431 splx(s); 5432 return error; 5433 } 5434 5435 /****************************************************************************/ 5436 /* Transmit timeout handler. */ 5437 /* */ 5438 /* Returns: */ 5439 /* Nothing. */ 5440 /****************************************************************************/ 5441 void 5442 bnx_watchdog(struct ifnet *ifp) 5443 { 5444 struct bnx_softc *sc = ifp->if_softc; 5445 5446 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5447 bnx_dump_status_block(sc)); 5448 /* 5449 * If we are in this routine because of pause frames, then 5450 * don't reset the hardware. 5451 */ 5452 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5453 return; 5454 5455 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5456 5457 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5458 5459 bnx_init(ifp); 5460 5461 if_statinc(ifp, if_oerrors); 5462 } 5463 5464 /* 5465 * Interrupt handler. 5466 */ 5467 /****************************************************************************/ 5468 /* Main interrupt entry point. Verifies that the controller generated the */ 5469 /* interrupt and then calls a separate routine for handle the various */ 5470 /* interrupt causes (PHY, TX, RX). */ 5471 /* */ 5472 /* Returns: */ 5473 /* 0 for success, positive value for failure. */ 5474 /****************************************************************************/ 5475 int 5476 bnx_intr(void *xsc) 5477 { 5478 struct bnx_softc *sc = xsc; 5479 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5480 uint32_t status_attn_bits; 5481 uint16_t status_idx; 5482 const struct status_block *sblk; 5483 int rv = 0; 5484 5485 if (!device_is_active(sc->bnx_dev) || 5486 (ifp->if_flags & IFF_RUNNING) == 0) 5487 return 0; 5488 5489 DBRUNIF(1, sc->interrupts_generated++); 5490 5491 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5492 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5493 5494 sblk = sc->status_block; 5495 /* 5496 * If the hardware status block index 5497 * matches the last value read by the 5498 * driver and we haven't asserted our 5499 * interrupt then there's nothing to do. 5500 */ 5501 status_idx = sblk->status_idx; 5502 if ((status_idx != sc->last_status_idx) || 5503 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5504 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5505 rv = 1; 5506 5507 /* Ack the interrupt */ 5508 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5509 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5510 5511 status_attn_bits = sblk->status_attn_bits; 5512 5513 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5514 aprint_debug("Simulating unexpected status attention bit set."); 5515 status_attn_bits = status_attn_bits | 5516 STATUS_ATTN_BITS_PARITY_ERROR); 5517 5518 /* Was it a link change interrupt? */ 5519 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5520 (sblk->status_attn_bits_ack & 5521 STATUS_ATTN_BITS_LINK_STATE)) 5522 bnx_phy_intr(sc); 5523 5524 /* If any other attention is asserted then the chip is toast. */ 5525 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5526 (sblk->status_attn_bits_ack & 5527 ~STATUS_ATTN_BITS_LINK_STATE))) { 5528 DBRUN(sc->unexpected_attentions++); 5529 5530 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5531 sblk->status_attn_bits); 5532 5533 DBRUNIF((bnx_debug_unexpected_attention == 0), 5534 bnx_breakpoint(sc)); 5535 5536 bnx_init(ifp); 5537 goto out; 5538 } 5539 5540 /* Check for any completed RX frames. */ 5541 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5542 bnx_rx_intr(sc); 5543 5544 /* Check for any completed TX frames. */ 5545 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5546 bnx_tx_intr(sc); 5547 5548 /* 5549 * Save the status block index value for use during the 5550 * next interrupt. 5551 */ 5552 sc->last_status_idx = status_idx; 5553 5554 /* Start moving packets again */ 5555 if (ifp->if_flags & IFF_RUNNING) 5556 if_schedule_deferred_start(ifp); 5557 } 5558 5559 out: 5560 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5561 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5562 5563 return rv; 5564 } 5565 5566 /****************************************************************************/ 5567 /* Programs the various packet receive modes (broadcast and multicast). */ 5568 /* */ 5569 /* Returns: */ 5570 /* Nothing. */ 5571 /****************************************************************************/ 5572 void 5573 bnx_iff(struct bnx_softc *sc) 5574 { 5575 struct ethercom *ec = &sc->bnx_ec; 5576 struct ifnet *ifp = &ec->ec_if; 5577 struct ether_multi *enm; 5578 struct ether_multistep step; 5579 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5580 uint32_t rx_mode, sort_mode; 5581 int h, i; 5582 5583 /* Initialize receive mode default settings. */ 5584 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5585 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5586 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5587 ifp->if_flags &= ~IFF_ALLMULTI; 5588 5589 /* 5590 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5591 * be enbled. 5592 */ 5593 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5594 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5595 5596 /* 5597 * Check for promiscuous, all multicast, or selected 5598 * multicast address filtering. 5599 */ 5600 if (ifp->if_flags & IFF_PROMISC) { 5601 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5602 5603 ifp->if_flags |= IFF_ALLMULTI; 5604 /* Enable promiscuous mode. */ 5605 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5606 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5607 } else if (ifp->if_flags & IFF_ALLMULTI) { 5608 allmulti: 5609 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5610 5611 ifp->if_flags |= IFF_ALLMULTI; 5612 /* Enable all multicast addresses. */ 5613 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5614 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5615 0xffffffff); 5616 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5617 } else { 5618 /* Accept one or more multicast(s). */ 5619 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5620 5621 ETHER_LOCK(ec); 5622 ETHER_FIRST_MULTI(step, ec, enm); 5623 while (enm != NULL) { 5624 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5625 ETHER_ADDR_LEN)) { 5626 ETHER_UNLOCK(ec); 5627 goto allmulti; 5628 } 5629 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5630 0xFF; 5631 hashes[(h & 0xE0) >> 5] |= __BIT(h & 0x1F); 5632 ETHER_NEXT_MULTI(step, enm); 5633 } 5634 ETHER_UNLOCK(ec); 5635 5636 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5637 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5638 hashes[i]); 5639 5640 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5641 } 5642 5643 /* Only make changes if the receive mode has actually changed. */ 5644 if (rx_mode != sc->rx_mode) { 5645 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5646 rx_mode); 5647 5648 sc->rx_mode = rx_mode; 5649 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5650 } 5651 5652 /* Disable and clear the exisitng sort before enabling a new sort. */ 5653 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5654 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5655 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5656 } 5657 5658 /****************************************************************************/ 5659 /* Called periodically to updates statistics from the controllers */ 5660 /* statistics block. */ 5661 /* */ 5662 /* Returns: */ 5663 /* Nothing. */ 5664 /****************************************************************************/ 5665 void 5666 bnx_stats_update(struct bnx_softc *sc) 5667 { 5668 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5669 struct statistics_block *stats; 5670 5671 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5672 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5673 BUS_DMASYNC_POSTREAD); 5674 5675 stats = (struct statistics_block *)sc->stats_block; 5676 5677 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 5678 uint64_t value; 5679 5680 /* 5681 * Update the interface statistics from the 5682 * hardware statistics. 5683 */ 5684 value = (u_long)stats->stat_EtherStatsCollisions; 5685 if_statadd_ref(nsr, if_collisions, value - sc->if_stat_collisions); 5686 sc->if_stat_collisions = value; 5687 5688 value = (u_long)stats->stat_EtherStatsUndersizePkts + 5689 (u_long)stats->stat_EtherStatsOverrsizePkts + 5690 (u_long)stats->stat_IfInMBUFDiscards + 5691 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5692 (u_long)stats->stat_Dot3StatsFCSErrors; 5693 if_statadd_ref(nsr, if_ierrors, value - sc->if_stat_ierrors); 5694 sc->if_stat_ierrors = value; 5695 5696 value = (u_long) 5697 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5698 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5699 (u_long)stats->stat_Dot3StatsLateCollisions; 5700 if_statadd_ref(nsr, if_oerrors, value - sc->if_stat_oerrors); 5701 sc->if_stat_oerrors = value; 5702 5703 /* 5704 * Certain controllers don't report 5705 * carrier sense errors correctly. 5706 * See errata E11_5708CA0_1165. 5707 */ 5708 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5709 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) { 5710 if_statadd_ref(nsr, if_oerrors, 5711 (u_long) stats->stat_Dot3StatsCarrierSenseErrors); 5712 } 5713 5714 IF_STAT_PUTREF(ifp); 5715 5716 /* 5717 * Update the sysctl statistics from the 5718 * hardware statistics. 5719 */ 5720 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5721 (uint64_t) stats->stat_IfHCInOctets_lo; 5722 5723 sc->stat_IfHCInBadOctets = 5724 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5725 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5726 5727 sc->stat_IfHCOutOctets = 5728 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5729 (uint64_t) stats->stat_IfHCOutOctets_lo; 5730 5731 sc->stat_IfHCOutBadOctets = 5732 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5733 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5734 5735 sc->stat_IfHCInUcastPkts = 5736 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5737 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5738 5739 sc->stat_IfHCInMulticastPkts = 5740 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5741 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5742 5743 sc->stat_IfHCInBroadcastPkts = 5744 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5745 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5746 5747 sc->stat_IfHCOutUcastPkts = 5748 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5749 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5750 5751 sc->stat_IfHCOutMulticastPkts = 5752 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5753 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5754 5755 sc->stat_IfHCOutBroadcastPkts = 5756 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5757 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5758 5759 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5760 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5761 5762 sc->stat_Dot3StatsCarrierSenseErrors = 5763 stats->stat_Dot3StatsCarrierSenseErrors; 5764 5765 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5766 5767 sc->stat_Dot3StatsAlignmentErrors = 5768 stats->stat_Dot3StatsAlignmentErrors; 5769 5770 sc->stat_Dot3StatsSingleCollisionFrames = 5771 stats->stat_Dot3StatsSingleCollisionFrames; 5772 5773 sc->stat_Dot3StatsMultipleCollisionFrames = 5774 stats->stat_Dot3StatsMultipleCollisionFrames; 5775 5776 sc->stat_Dot3StatsDeferredTransmissions = 5777 stats->stat_Dot3StatsDeferredTransmissions; 5778 5779 sc->stat_Dot3StatsExcessiveCollisions = 5780 stats->stat_Dot3StatsExcessiveCollisions; 5781 5782 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5783 5784 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5785 5786 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5787 5788 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5789 5790 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5791 5792 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5793 5794 sc->stat_EtherStatsPktsRx64Octets = 5795 stats->stat_EtherStatsPktsRx64Octets; 5796 5797 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5798 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5799 5800 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5801 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5802 5803 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5804 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5805 5806 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5807 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5808 5809 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5810 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5811 5812 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5813 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5814 5815 sc->stat_EtherStatsPktsTx64Octets = 5816 stats->stat_EtherStatsPktsTx64Octets; 5817 5818 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5819 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5820 5821 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5822 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5823 5824 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5825 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5826 5827 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5828 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5829 5830 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5831 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5832 5833 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5834 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5835 5836 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5837 5838 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5839 5840 sc->stat_OutXonSent = stats->stat_OutXonSent; 5841 5842 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5843 5844 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5845 5846 sc->stat_MacControlFramesReceived = 5847 stats->stat_MacControlFramesReceived; 5848 5849 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5850 5851 sc->stat_IfInFramesL2FilterDiscards = 5852 stats->stat_IfInFramesL2FilterDiscards; 5853 5854 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5855 5856 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5857 5858 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5859 5860 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5861 5862 sc->stat_CatchupInRuleCheckerDiscards = 5863 stats->stat_CatchupInRuleCheckerDiscards; 5864 5865 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5866 5867 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5868 5869 sc->stat_CatchupInRuleCheckerP4Hit = 5870 stats->stat_CatchupInRuleCheckerP4Hit; 5871 5872 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5873 } 5874 5875 void 5876 bnx_tick(void *xsc) 5877 { 5878 struct bnx_softc *sc = xsc; 5879 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5880 struct mii_data *mii; 5881 uint32_t msg; 5882 uint16_t prod, chain_prod; 5883 uint32_t prod_bseq; 5884 int s = splnet(); 5885 5886 /* Tell the firmware that the driver is still running. */ 5887 #ifdef BNX_DEBUG 5888 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5889 #else 5890 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5891 #endif 5892 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5893 5894 /* Update the statistics from the hardware statistics block. */ 5895 bnx_stats_update(sc); 5896 5897 /* Schedule the next tick. */ 5898 if (!sc->bnx_detaching) 5899 callout_schedule(&sc->bnx_timeout, hz); 5900 5901 if (sc->bnx_link) 5902 goto bnx_tick_exit; 5903 5904 mii = &sc->bnx_mii; 5905 mii_tick(mii); 5906 5907 /* Check if the link has come up. */ 5908 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5909 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5910 sc->bnx_link++; 5911 /* Now that link is up, handle any outstanding TX traffic. */ 5912 if_schedule_deferred_start(ifp); 5913 } 5914 5915 bnx_tick_exit: 5916 /* try to get more RX buffers, just in case */ 5917 prod = sc->rx_prod; 5918 prod_bseq = sc->rx_prod_bseq; 5919 chain_prod = RX_CHAIN_IDX(prod); 5920 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5921 sc->rx_prod = prod; 5922 sc->rx_prod_bseq = prod_bseq; 5923 5924 splx(s); 5925 return; 5926 } 5927 5928 /****************************************************************************/ 5929 /* BNX Debug Routines */ 5930 /****************************************************************************/ 5931 #ifdef BNX_DEBUG 5932 5933 /****************************************************************************/ 5934 /* Prints out information about an mbuf. */ 5935 /* */ 5936 /* Returns: */ 5937 /* Nothing. */ 5938 /****************************************************************************/ 5939 void 5940 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5941 { 5942 struct mbuf *mp = m; 5943 5944 if (m == NULL) { 5945 /* Index out of range. */ 5946 aprint_error("mbuf ptr is null!\n"); 5947 return; 5948 } 5949 5950 while (mp) { 5951 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5952 mp, mp->m_len); 5953 5954 if (mp->m_flags & M_EXT) 5955 aprint_debug("M_EXT "); 5956 if (mp->m_flags & M_PKTHDR) 5957 aprint_debug("M_PKTHDR "); 5958 aprint_debug("\n"); 5959 5960 if (mp->m_flags & M_EXT) 5961 aprint_debug("- m_ext: vaddr = %p, " 5962 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5963 5964 mp = mp->m_next; 5965 } 5966 } 5967 5968 /****************************************************************************/ 5969 /* Prints out the mbufs in the TX mbuf chain. */ 5970 /* */ 5971 /* Returns: */ 5972 /* Nothing. */ 5973 /****************************************************************************/ 5974 void 5975 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5976 { 5977 #if 0 5978 struct mbuf *m; 5979 int i; 5980 5981 aprint_debug_dev(sc->bnx_dev, 5982 "----------------------------" 5983 " tx mbuf data " 5984 "----------------------------\n"); 5985 5986 for (i = 0; i < count; i++) { 5987 m = sc->tx_mbuf_ptr[chain_prod]; 5988 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5989 bnx_dump_mbuf(sc, m); 5990 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5991 } 5992 5993 aprint_debug_dev(sc->bnx_dev, 5994 "--------------------------------------------" 5995 "----------------------------\n"); 5996 #endif 5997 } 5998 5999 /* 6000 * This routine prints the RX mbuf chain. 6001 */ 6002 void 6003 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 6004 { 6005 struct mbuf *m; 6006 int i; 6007 6008 aprint_debug_dev(sc->bnx_dev, 6009 "----------------------------" 6010 " rx mbuf data " 6011 "----------------------------\n"); 6012 6013 for (i = 0; i < count; i++) { 6014 m = sc->rx_mbuf_ptr[chain_prod]; 6015 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6016 bnx_dump_mbuf(sc, m); 6017 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6018 } 6019 6020 6021 aprint_debug_dev(sc->bnx_dev, 6022 "--------------------------------------------" 6023 "----------------------------\n"); 6024 } 6025 6026 void 6027 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 6028 { 6029 if (idx > MAX_TX_BD) 6030 /* Index out of range. */ 6031 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6032 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6033 /* TX Chain page pointer. */ 6034 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 6035 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 6036 txbd->tx_bd_haddr_lo); 6037 else 6038 /* Normal tx_bd entry. */ 6039 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6040 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 6041 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6042 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6043 txbd->tx_bd_flags); 6044 } 6045 6046 void 6047 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 6048 { 6049 if (idx > MAX_RX_BD) 6050 /* Index out of range. */ 6051 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6052 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6053 /* TX Chain page pointer. */ 6054 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 6055 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 6056 rxbd->rx_bd_haddr_lo); 6057 else 6058 /* Normal tx_bd entry. */ 6059 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6060 "0x%08X, flags = 0x%08X\n", idx, 6061 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6062 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6063 } 6064 6065 void 6066 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6067 { 6068 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6069 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6070 "tcp_udp_xsum = 0x%04X\n", idx, 6071 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6072 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6073 l2fhdr->l2_fhdr_tcp_udp_xsum); 6074 } 6075 6076 /* 6077 * This routine prints the TX chain. 6078 */ 6079 void 6080 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 6081 { 6082 struct tx_bd *txbd; 6083 int i; 6084 6085 /* First some info about the tx_bd chain structure. */ 6086 aprint_debug_dev(sc->bnx_dev, 6087 "----------------------------" 6088 " tx_bd chain " 6089 "----------------------------\n"); 6090 6091 BNX_PRINTF(sc, 6092 "page size = 0x%08X, tx chain pages = 0x%08X\n", 6093 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6094 6095 BNX_PRINTF(sc, 6096 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6097 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6098 6099 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6100 6101 aprint_error_dev(sc->bnx_dev, "" 6102 "-----------------------------" 6103 " tx_bd data " 6104 "-----------------------------\n"); 6105 6106 /* Now print out the tx_bd's themselves. */ 6107 for (i = 0; i < count; i++) { 6108 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6109 bnx_dump_txbd(sc, tx_prod, txbd); 6110 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6111 } 6112 6113 aprint_debug_dev(sc->bnx_dev, 6114 "-----------------------------" 6115 "--------------" 6116 "-----------------------------\n"); 6117 } 6118 6119 /* 6120 * This routine prints the RX chain. 6121 */ 6122 void 6123 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6124 { 6125 struct rx_bd *rxbd; 6126 int i; 6127 6128 /* First some info about the tx_bd chain structure. */ 6129 aprint_debug_dev(sc->bnx_dev, 6130 "----------------------------" 6131 " rx_bd chain " 6132 "----------------------------\n"); 6133 6134 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6135 6136 BNX_PRINTF(sc, 6137 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6138 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6139 6140 BNX_PRINTF(sc, 6141 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6142 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6143 6144 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6145 6146 aprint_error_dev(sc->bnx_dev, 6147 "----------------------------" 6148 " rx_bd data " 6149 "----------------------------\n"); 6150 6151 /* Now print out the rx_bd's themselves. */ 6152 for (i = 0; i < count; i++) { 6153 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6154 bnx_dump_rxbd(sc, rx_prod, rxbd); 6155 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6156 } 6157 6158 aprint_debug_dev(sc->bnx_dev, 6159 "----------------------------" 6160 "--------------" 6161 "----------------------------\n"); 6162 } 6163 6164 /* 6165 * This routine prints the status block. 6166 */ 6167 void 6168 bnx_dump_status_block(struct bnx_softc *sc) 6169 { 6170 struct status_block *sblk; 6171 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6172 BUS_DMASYNC_POSTREAD); 6173 6174 sblk = sc->status_block; 6175 6176 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6177 "Status Block -----------------------------\n"); 6178 6179 BNX_PRINTF(sc, 6180 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6181 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6182 sblk->status_idx); 6183 6184 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6185 sblk->status_rx_quick_consumer_index0, 6186 sblk->status_tx_quick_consumer_index0); 6187 6188 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6189 6190 /* Theses indices are not used for normal L2 drivers. */ 6191 if (sblk->status_rx_quick_consumer_index1 || 6192 sblk->status_tx_quick_consumer_index1) 6193 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6194 sblk->status_rx_quick_consumer_index1, 6195 sblk->status_tx_quick_consumer_index1); 6196 6197 if (sblk->status_rx_quick_consumer_index2 || 6198 sblk->status_tx_quick_consumer_index2) 6199 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6200 sblk->status_rx_quick_consumer_index2, 6201 sblk->status_tx_quick_consumer_index2); 6202 6203 if (sblk->status_rx_quick_consumer_index3 || 6204 sblk->status_tx_quick_consumer_index3) 6205 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6206 sblk->status_rx_quick_consumer_index3, 6207 sblk->status_tx_quick_consumer_index3); 6208 6209 if (sblk->status_rx_quick_consumer_index4 || 6210 sblk->status_rx_quick_consumer_index5) 6211 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6212 sblk->status_rx_quick_consumer_index4, 6213 sblk->status_rx_quick_consumer_index5); 6214 6215 if (sblk->status_rx_quick_consumer_index6 || 6216 sblk->status_rx_quick_consumer_index7) 6217 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6218 sblk->status_rx_quick_consumer_index6, 6219 sblk->status_rx_quick_consumer_index7); 6220 6221 if (sblk->status_rx_quick_consumer_index8 || 6222 sblk->status_rx_quick_consumer_index9) 6223 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6224 sblk->status_rx_quick_consumer_index8, 6225 sblk->status_rx_quick_consumer_index9); 6226 6227 if (sblk->status_rx_quick_consumer_index10 || 6228 sblk->status_rx_quick_consumer_index11) 6229 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6230 sblk->status_rx_quick_consumer_index10, 6231 sblk->status_rx_quick_consumer_index11); 6232 6233 if (sblk->status_rx_quick_consumer_index12 || 6234 sblk->status_rx_quick_consumer_index13) 6235 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6236 sblk->status_rx_quick_consumer_index12, 6237 sblk->status_rx_quick_consumer_index13); 6238 6239 if (sblk->status_rx_quick_consumer_index14 || 6240 sblk->status_rx_quick_consumer_index15) 6241 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6242 sblk->status_rx_quick_consumer_index14, 6243 sblk->status_rx_quick_consumer_index15); 6244 6245 if (sblk->status_completion_producer_index || 6246 sblk->status_cmd_consumer_index) 6247 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6248 sblk->status_completion_producer_index, 6249 sblk->status_cmd_consumer_index); 6250 6251 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6252 "-----------------------------\n"); 6253 } 6254 6255 /* 6256 * This routine prints the statistics block. 6257 */ 6258 void 6259 bnx_dump_stats_block(struct bnx_softc *sc) 6260 { 6261 struct statistics_block *sblk; 6262 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6263 BUS_DMASYNC_POSTREAD); 6264 6265 sblk = sc->stats_block; 6266 6267 aprint_debug_dev(sc->bnx_dev, "" 6268 "-----------------------------" 6269 " Stats Block " 6270 "-----------------------------\n"); 6271 6272 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6273 "IfHcInBadOctets = 0x%08X:%08X\n", 6274 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6275 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6276 6277 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6278 "IfHcOutBadOctets = 0x%08X:%08X\n", 6279 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6280 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6281 6282 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6283 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6284 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6285 sblk->stat_IfHCInMulticastPkts_hi, 6286 sblk->stat_IfHCInMulticastPkts_lo); 6287 6288 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6289 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6290 sblk->stat_IfHCInBroadcastPkts_hi, 6291 sblk->stat_IfHCInBroadcastPkts_lo, 6292 sblk->stat_IfHCOutUcastPkts_hi, 6293 sblk->stat_IfHCOutUcastPkts_lo); 6294 6295 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6296 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6297 sblk->stat_IfHCOutMulticastPkts_hi, 6298 sblk->stat_IfHCOutMulticastPkts_lo, 6299 sblk->stat_IfHCOutBroadcastPkts_hi, 6300 sblk->stat_IfHCOutBroadcastPkts_lo); 6301 6302 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6303 BNX_PRINTF(sc, "0x%08X : " 6304 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6305 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6306 6307 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6308 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6309 sblk->stat_Dot3StatsCarrierSenseErrors); 6310 6311 if (sblk->stat_Dot3StatsFCSErrors) 6312 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6313 sblk->stat_Dot3StatsFCSErrors); 6314 6315 if (sblk->stat_Dot3StatsAlignmentErrors) 6316 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6317 sblk->stat_Dot3StatsAlignmentErrors); 6318 6319 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6320 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6321 sblk->stat_Dot3StatsSingleCollisionFrames); 6322 6323 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6324 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6325 sblk->stat_Dot3StatsMultipleCollisionFrames); 6326 6327 if (sblk->stat_Dot3StatsDeferredTransmissions) 6328 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6329 sblk->stat_Dot3StatsDeferredTransmissions); 6330 6331 if (sblk->stat_Dot3StatsExcessiveCollisions) 6332 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6333 sblk->stat_Dot3StatsExcessiveCollisions); 6334 6335 if (sblk->stat_Dot3StatsLateCollisions) 6336 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6337 sblk->stat_Dot3StatsLateCollisions); 6338 6339 if (sblk->stat_EtherStatsCollisions) 6340 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6341 sblk->stat_EtherStatsCollisions); 6342 6343 if (sblk->stat_EtherStatsFragments) 6344 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6345 sblk->stat_EtherStatsFragments); 6346 6347 if (sblk->stat_EtherStatsJabbers) 6348 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6349 sblk->stat_EtherStatsJabbers); 6350 6351 if (sblk->stat_EtherStatsUndersizePkts) 6352 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6353 sblk->stat_EtherStatsUndersizePkts); 6354 6355 if (sblk->stat_EtherStatsOverrsizePkts) 6356 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6357 sblk->stat_EtherStatsOverrsizePkts); 6358 6359 if (sblk->stat_EtherStatsPktsRx64Octets) 6360 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6361 sblk->stat_EtherStatsPktsRx64Octets); 6362 6363 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6364 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6365 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6366 6367 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6368 BNX_PRINTF(sc, "0x%08X : " 6369 "EtherStatsPktsRx128Octetsto255Octets\n", 6370 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6371 6372 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6373 BNX_PRINTF(sc, "0x%08X : " 6374 "EtherStatsPktsRx256Octetsto511Octets\n", 6375 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6376 6377 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6378 BNX_PRINTF(sc, "0x%08X : " 6379 "EtherStatsPktsRx512Octetsto1023Octets\n", 6380 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6381 6382 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6383 BNX_PRINTF(sc, "0x%08X : " 6384 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6385 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6386 6387 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6388 BNX_PRINTF(sc, "0x%08X : " 6389 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6390 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6391 6392 if (sblk->stat_EtherStatsPktsTx64Octets) 6393 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6394 sblk->stat_EtherStatsPktsTx64Octets); 6395 6396 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6397 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6398 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6399 6400 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6401 BNX_PRINTF(sc, "0x%08X : " 6402 "EtherStatsPktsTx128Octetsto255Octets\n", 6403 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6404 6405 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6406 BNX_PRINTF(sc, "0x%08X : " 6407 "EtherStatsPktsTx256Octetsto511Octets\n", 6408 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6409 6410 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6411 BNX_PRINTF(sc, "0x%08X : " 6412 "EtherStatsPktsTx512Octetsto1023Octets\n", 6413 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6414 6415 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6416 BNX_PRINTF(sc, "0x%08X : " 6417 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6418 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6419 6420 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6421 BNX_PRINTF(sc, "0x%08X : " 6422 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6423 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6424 6425 if (sblk->stat_XonPauseFramesReceived) 6426 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6427 sblk->stat_XonPauseFramesReceived); 6428 6429 if (sblk->stat_XoffPauseFramesReceived) 6430 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6431 sblk->stat_XoffPauseFramesReceived); 6432 6433 if (sblk->stat_OutXonSent) 6434 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6435 sblk->stat_OutXonSent); 6436 6437 if (sblk->stat_OutXoffSent) 6438 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6439 sblk->stat_OutXoffSent); 6440 6441 if (sblk->stat_FlowControlDone) 6442 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6443 sblk->stat_FlowControlDone); 6444 6445 if (sblk->stat_MacControlFramesReceived) 6446 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6447 sblk->stat_MacControlFramesReceived); 6448 6449 if (sblk->stat_XoffStateEntered) 6450 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6451 sblk->stat_XoffStateEntered); 6452 6453 if (sblk->stat_IfInFramesL2FilterDiscards) 6454 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6455 sblk->stat_IfInFramesL2FilterDiscards); 6456 6457 if (sblk->stat_IfInRuleCheckerDiscards) 6458 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6459 sblk->stat_IfInRuleCheckerDiscards); 6460 6461 if (sblk->stat_IfInFTQDiscards) 6462 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6463 sblk->stat_IfInFTQDiscards); 6464 6465 if (sblk->stat_IfInMBUFDiscards) 6466 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6467 sblk->stat_IfInMBUFDiscards); 6468 6469 if (sblk->stat_IfInRuleCheckerP4Hit) 6470 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6471 sblk->stat_IfInRuleCheckerP4Hit); 6472 6473 if (sblk->stat_CatchupInRuleCheckerDiscards) 6474 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6475 sblk->stat_CatchupInRuleCheckerDiscards); 6476 6477 if (sblk->stat_CatchupInFTQDiscards) 6478 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6479 sblk->stat_CatchupInFTQDiscards); 6480 6481 if (sblk->stat_CatchupInMBUFDiscards) 6482 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6483 sblk->stat_CatchupInMBUFDiscards); 6484 6485 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6486 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6487 sblk->stat_CatchupInRuleCheckerP4Hit); 6488 6489 aprint_debug_dev(sc->bnx_dev, 6490 "-----------------------------" 6491 "--------------" 6492 "-----------------------------\n"); 6493 } 6494 6495 void 6496 bnx_dump_driver_state(struct bnx_softc *sc) 6497 { 6498 aprint_debug_dev(sc->bnx_dev, 6499 "-----------------------------" 6500 " Driver State " 6501 "-----------------------------\n"); 6502 6503 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6504 "address\n", sc); 6505 6506 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6507 sc->status_block); 6508 6509 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6510 "address\n", sc->stats_block); 6511 6512 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6513 "address\n", sc->tx_bd_chain); 6514 6515 #if 0 6516 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6517 sc->rx_bd_chain); 6518 6519 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6520 sc->tx_mbuf_ptr); 6521 #endif 6522 6523 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6524 sc->rx_mbuf_ptr); 6525 6526 BNX_PRINTF(sc, 6527 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6528 sc->interrupts_generated); 6529 6530 BNX_PRINTF(sc, 6531 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6532 sc->rx_interrupts); 6533 6534 BNX_PRINTF(sc, 6535 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6536 sc->tx_interrupts); 6537 6538 BNX_PRINTF(sc, 6539 " 0x%08X - (sc->last_status_idx) status block index\n", 6540 sc->last_status_idx); 6541 6542 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6543 sc->tx_prod); 6544 6545 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6546 sc->tx_cons); 6547 6548 BNX_PRINTF(sc, 6549 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6550 sc->tx_prod_bseq); 6551 BNX_PRINTF(sc, 6552 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6553 sc->tx_mbuf_alloc); 6554 6555 BNX_PRINTF(sc, 6556 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6557 sc->used_tx_bd); 6558 6559 BNX_PRINTF(sc, 6560 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6561 sc->tx_hi_watermark, sc->max_tx_bd); 6562 6563 6564 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6565 sc->rx_prod); 6566 6567 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6568 sc->rx_cons); 6569 6570 BNX_PRINTF(sc, 6571 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6572 sc->rx_prod_bseq); 6573 6574 BNX_PRINTF(sc, 6575 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6576 sc->rx_mbuf_alloc); 6577 6578 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6579 sc->free_rx_bd); 6580 6581 BNX_PRINTF(sc, 6582 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6583 sc->rx_low_watermark, sc->max_rx_bd); 6584 6585 BNX_PRINTF(sc, 6586 " 0x%08X - (sc->mbuf_alloc_failed) " 6587 "mbuf alloc failures\n", 6588 sc->mbuf_alloc_failed); 6589 6590 BNX_PRINTF(sc, 6591 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6592 "simulated mbuf alloc failures\n", 6593 sc->mbuf_sim_alloc_failed); 6594 6595 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6596 "-----------------------------\n"); 6597 } 6598 6599 void 6600 bnx_dump_hw_state(struct bnx_softc *sc) 6601 { 6602 uint32_t val1; 6603 int i; 6604 6605 aprint_debug_dev(sc->bnx_dev, 6606 "----------------------------" 6607 " Hardware State " 6608 "----------------------------\n"); 6609 6610 val1 = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 6611 BNX_PRINTF(sc, "0x%08X : bootcode version\n", val1); 6612 6613 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6614 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6615 val1, BNX_MISC_ENABLE_STATUS_BITS); 6616 6617 val1 = REG_RD(sc, BNX_DMA_STATUS); 6618 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6619 6620 val1 = REG_RD(sc, BNX_CTX_STATUS); 6621 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6622 6623 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6624 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6625 BNX_EMAC_STATUS); 6626 6627 val1 = REG_RD(sc, BNX_RPM_STATUS); 6628 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6629 6630 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6631 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6632 BNX_TBDR_STATUS); 6633 6634 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6635 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6636 BNX_TDMA_STATUS); 6637 6638 val1 = REG_RD(sc, BNX_HC_STATUS); 6639 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6640 6641 aprint_debug_dev(sc->bnx_dev, 6642 "----------------------------" 6643 "----------------" 6644 "----------------------------\n"); 6645 6646 aprint_debug_dev(sc->bnx_dev, 6647 "----------------------------" 6648 " Register Dump " 6649 "----------------------------\n"); 6650 6651 for (i = 0x400; i < 0x8000; i += 0x10) 6652 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6653 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6654 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6655 6656 aprint_debug_dev(sc->bnx_dev, 6657 "----------------------------" 6658 "----------------" 6659 "----------------------------\n"); 6660 } 6661 6662 void 6663 bnx_breakpoint(struct bnx_softc *sc) 6664 { 6665 /* Unreachable code to shut the compiler up about unused functions. */ 6666 if (0) { 6667 bnx_dump_txbd(sc, 0, NULL); 6668 bnx_dump_rxbd(sc, 0, NULL); 6669 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6670 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6671 bnx_dump_l2fhdr(sc, 0, NULL); 6672 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6673 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6674 bnx_dump_status_block(sc); 6675 bnx_dump_stats_block(sc); 6676 bnx_dump_driver_state(sc); 6677 bnx_dump_hw_state(sc); 6678 } 6679 6680 bnx_dump_driver_state(sc); 6681 /* Print the important status block fields. */ 6682 bnx_dump_status_block(sc); 6683 6684 #if 0 6685 /* Call the debugger. */ 6686 breakpoint(); 6687 #endif 6688 6689 return; 6690 } 6691 #endif 6692
Indexes created Thu Sep 25 02:09:54 GMT 2025