if_bnx.c revision 1.11
1 /* $NetBSD: if_bnx.c,v 1.11 2007/12/04 09:22:05 dyoung Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.43 2007/01/30 03:21:10 krw Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.11 2007/12/04 09:22:05 dyoung Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5708C B1 44 * 45 * The following controllers are not supported by this driver: 46 * (These are not "Production" versions of the controller.) 47 * 48 * BCM5706C A0, A1 49 * BCM5706S A0, A1, A2, A3 50 * BCM5708C A0, B0 51 * BCM5708S A0, B0, B1 52 */ 53 54 #include <sys/callout.h> 55 56 #include <dev/pci/if_bnxreg.h> 57 #include <dev/microcode/bnx/bnxfw.h> 58 59 /****************************************************************************/ 60 /* BNX Driver Version */ 61 /****************************************************************************/ 62 const char bnx_driver_version[] = "v0.9.6"; 63 64 /****************************************************************************/ 65 /* BNX Debug Options */ 66 /****************************************************************************/ 67 #ifdef BNX_DEBUG 68 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 69 70 /* 0 = Never */ 71 /* 1 = 1 in 2,147,483,648 */ 72 /* 256 = 1 in 8,388,608 */ 73 /* 2048 = 1 in 1,048,576 */ 74 /* 65536 = 1 in 32,768 */ 75 /* 1048576 = 1 in 2,048 */ 76 /* 268435456 = 1 in 8 */ 77 /* 536870912 = 1 in 4 */ 78 /* 1073741824 = 1 in 2 */ 79 80 /* Controls how often the l2_fhdr frame error check will fail. */ 81 int bnx_debug_l2fhdr_status_check = 0; 82 83 /* Controls how often the unexpected attention check will fail. */ 84 int bnx_debug_unexpected_attention = 0; 85 86 /* Controls how often to simulate an mbuf allocation failure. */ 87 int bnx_debug_mbuf_allocation_failure = 0; 88 89 /* Controls how often to simulate a DMA mapping failure. */ 90 int bnx_debug_dma_map_addr_failure = 0; 91 92 /* Controls how often to simulate a bootcode failure. */ 93 int bnx_debug_bootcode_running_failure = 0; 94 #endif 95 96 /****************************************************************************/ 97 /* PCI Device ID Table */ 98 /* */ 99 /* Used by bnx_probe() to identify the devices supported by this driver. */ 100 /****************************************************************************/ 101 static const struct bnx_product { 102 pci_vendor_id_t bp_vendor; 103 pci_product_id_t bp_product; 104 pci_vendor_id_t bp_subvendor; 105 pci_product_id_t bp_subproduct; 106 const char *bp_name; 107 } bnx_devices[] = { 108 #ifdef PCI_SUBPRODUCT_HP_NC370T 109 { 110 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 111 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 112 "HP NC370T Multifunction Gigabit Server Adapter" 113 }, 114 #endif 115 #ifdef PCI_SUBPRODUCT_HP_NC370i 116 { 117 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 118 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 119 "HP NC370i Multifunction Gigabit Server Adapter" 120 }, 121 #endif 122 { 123 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 124 0, 0, 125 "Broadcom NetXtreme II BCM5706 1000Base-T" 126 }, 127 #ifdef PCI_SUBPRODUCT_HP_NC370F 128 { 129 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 130 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 131 "HP NC370F Multifunction Gigabit Server Adapter" 132 }, 133 #endif 134 { 135 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 136 0, 0, 137 "Broadcom NetXtreme II BCM5706 1000Base-SX" 138 }, 139 { 140 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 141 0, 0, 142 "Broadcom NetXtreme II BCM5708 1000Base-T" 143 }, 144 { 145 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 146 0, 0, 147 "Broadcom NetXtreme II BCM5708 1000Base-SX" 148 }, 149 }; 150 151 /****************************************************************************/ 152 /* Supported Flash NVRAM device data. */ 153 /****************************************************************************/ 154 static struct flash_spec flash_table[] = 155 { 156 /* Slow EEPROM */ 157 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 158 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 159 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 160 "EEPROM - slow"}, 161 /* Expansion entry 0001 */ 162 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 164 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 165 "Entry 0001"}, 166 /* Saifun SA25F010 (non-buffered flash) */ 167 /* strap, cfg1, & write1 need updates */ 168 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 169 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 171 "Non-buffered flash (128kB)"}, 172 /* Saifun SA25F020 (non-buffered flash) */ 173 /* strap, cfg1, & write1 need updates */ 174 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 175 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 176 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 177 "Non-buffered flash (256kB)"}, 178 /* Expansion entry 0100 */ 179 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 0100"}, 183 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 184 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 185 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 186 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 187 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 188 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 189 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 190 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 191 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 192 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 193 /* Saifun SA25F005 (non-buffered flash) */ 194 /* strap, cfg1, & write1 need updates */ 195 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 196 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 197 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 198 "Non-buffered flash (64kB)"}, 199 /* Fast EEPROM */ 200 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 201 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 202 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 203 "EEPROM - fast"}, 204 /* Expansion entry 1001 */ 205 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 206 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 208 "Entry 1001"}, 209 /* Expansion entry 1010 */ 210 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 211 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 1010"}, 214 /* ATMEL AT45DB011B (buffered flash) */ 215 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 216 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 217 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 218 "Buffered flash (128kB)"}, 219 /* Expansion entry 1100 */ 220 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 221 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 223 "Entry 1100"}, 224 /* Expansion entry 1101 */ 225 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 226 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 228 "Entry 1101"}, 229 /* Ateml Expansion entry 1110 */ 230 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 231 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 232 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 233 "Entry 1110 (Atmel)"}, 234 /* ATMEL AT45DB021B (buffered flash) */ 235 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 236 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 237 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 238 "Buffered flash (256kB)"}, 239 }; 240 241 /****************************************************************************/ 242 /* OpenBSD device entry points. */ 243 /****************************************************************************/ 244 static int bnx_probe(device_t, cfdata_t, void *); 245 void bnx_attach(struct device *, struct device *, void *); 246 #if 0 247 void bnx_detach(void *); 248 #endif 249 void bnx_shutdown(void *); 250 251 /****************************************************************************/ 252 /* BNX Debug Data Structure Dump Routines */ 253 /****************************************************************************/ 254 #ifdef BNX_DEBUG 255 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 256 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 257 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 258 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 259 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 260 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 261 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 262 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 263 void bnx_dump_status_block(struct bnx_softc *); 264 void bnx_dump_stats_block(struct bnx_softc *); 265 void bnx_dump_driver_state(struct bnx_softc *); 266 void bnx_dump_hw_state(struct bnx_softc *); 267 void bnx_breakpoint(struct bnx_softc *); 268 #endif 269 270 /****************************************************************************/ 271 /* BNX Register/Memory Access Routines */ 272 /****************************************************************************/ 273 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 274 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 275 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 276 int bnx_miibus_read_reg(struct device *, int, int); 277 void bnx_miibus_write_reg(struct device *, int, int, int); 278 void bnx_miibus_statchg(struct device *); 279 280 /****************************************************************************/ 281 /* BNX NVRAM Access Routines */ 282 /****************************************************************************/ 283 int bnx_acquire_nvram_lock(struct bnx_softc *); 284 int bnx_release_nvram_lock(struct bnx_softc *); 285 void bnx_enable_nvram_access(struct bnx_softc *); 286 void bnx_disable_nvram_access(struct bnx_softc *); 287 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 288 u_int32_t); 289 int bnx_init_nvram(struct bnx_softc *); 290 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 291 int bnx_nvram_test(struct bnx_softc *); 292 #ifdef BNX_NVRAM_WRITE_SUPPORT 293 int bnx_enable_nvram_write(struct bnx_softc *); 294 void bnx_disable_nvram_write(struct bnx_softc *); 295 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 296 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 297 u_int32_t); 298 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 299 #endif 300 301 /****************************************************************************/ 302 /* */ 303 /****************************************************************************/ 304 int bnx_dma_alloc(struct bnx_softc *); 305 void bnx_dma_free(struct bnx_softc *); 306 void bnx_release_resources(struct bnx_softc *); 307 308 /****************************************************************************/ 309 /* BNX Firmware Synchronization and Load */ 310 /****************************************************************************/ 311 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 312 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 313 u_int32_t); 314 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 315 struct fw_info *); 316 void bnx_init_cpus(struct bnx_softc *); 317 318 void bnx_stop(struct bnx_softc *); 319 int bnx_reset(struct bnx_softc *, u_int32_t); 320 int bnx_chipinit(struct bnx_softc *); 321 int bnx_blockinit(struct bnx_softc *); 322 int bnx_get_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 323 u_int16_t *, u_int32_t *); 324 325 int bnx_init_tx_chain(struct bnx_softc *); 326 int bnx_init_rx_chain(struct bnx_softc *); 327 void bnx_free_rx_chain(struct bnx_softc *); 328 void bnx_free_tx_chain(struct bnx_softc *); 329 330 int bnx_tx_encap(struct bnx_softc *, struct mbuf **); 331 void bnx_start(struct ifnet *); 332 int bnx_ioctl(struct ifnet *, u_long, void *); 333 void bnx_watchdog(struct ifnet *); 334 int bnx_ifmedia_upd(struct ifnet *); 335 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 336 int bnx_init(struct ifnet *); 337 338 void bnx_init_context(struct bnx_softc *); 339 void bnx_get_mac_addr(struct bnx_softc *); 340 void bnx_set_mac_addr(struct bnx_softc *); 341 void bnx_phy_intr(struct bnx_softc *); 342 void bnx_rx_intr(struct bnx_softc *); 343 void bnx_tx_intr(struct bnx_softc *); 344 void bnx_disable_intr(struct bnx_softc *); 345 void bnx_enable_intr(struct bnx_softc *); 346 347 int bnx_intr(void *); 348 void bnx_set_rx_mode(struct bnx_softc *); 349 void bnx_stats_update(struct bnx_softc *); 350 void bnx_tick(void *); 351 352 /****************************************************************************/ 353 /* OpenBSD device dispatch table. */ 354 /****************************************************************************/ 355 CFATTACH_DECL(bnx, sizeof(struct bnx_softc), 356 bnx_probe, bnx_attach, NULL, NULL); 357 358 /****************************************************************************/ 359 /* Device probe function. */ 360 /* */ 361 /* Compares the device to the driver's list of supported devices and */ 362 /* reports back to the OS whether this is the right driver for the device. */ 363 /* */ 364 /* Returns: */ 365 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 366 /****************************************************************************/ 367 static const struct bnx_product * 368 bnx_lookup(const struct pci_attach_args *pa) 369 { 370 int i; 371 pcireg_t subid; 372 373 for (i = 0; i < sizeof(bnx_devices)/sizeof(struct bnx_product); i++) { 374 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 375 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 376 continue; 377 if (!bnx_devices[i].bp_subvendor) 378 return &bnx_devices[i]; 379 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 380 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 381 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 382 return &bnx_devices[i]; 383 } 384 385 return NULL; 386 } 387 static int 388 bnx_probe(device_t parent, cfdata_t match, void *aux) 389 { 390 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 391 392 if (bnx_lookup(pa) != NULL) 393 return (1); 394 395 return (0); 396 } 397 398 /****************************************************************************/ 399 /* Device attach function. */ 400 /* */ 401 /* Allocates device resources, performs secondary chip identification, */ 402 /* resets and initializes the hardware, and initializes driver instance */ 403 /* variables. */ 404 /* */ 405 /* Returns: */ 406 /* 0 on success, positive value on failure. */ 407 /****************************************************************************/ 408 void 409 bnx_attach(struct device *parent, struct device *self, void *aux) 410 { 411 const struct bnx_product *bp; 412 struct bnx_softc *sc = (struct bnx_softc *)self; 413 struct pci_attach_args *pa = aux; 414 pci_chipset_tag_t pc = pa->pa_pc; 415 pci_intr_handle_t ih; 416 const char *intrstr = NULL; 417 u_int32_t command; 418 struct ifnet *ifp; 419 u_int32_t val; 420 pcireg_t memtype; 421 422 bp = bnx_lookup(pa); 423 if (bp == NULL) 424 panic("unknown device"); 425 426 aprint_naive("\n"); 427 aprint_normal(": %s\n", bp->bp_name); 428 429 sc->bnx_pa = *pa; 430 431 /* 432 * Map control/status registers. 433 */ 434 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 435 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 436 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 437 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 438 439 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 440 aprint_error("%s: failed to enable memory mapping!\n", 441 sc->bnx_dev.dv_xname); 442 return; 443 } 444 445 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 446 switch (memtype) { 447 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 448 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 449 if (pci_mapreg_map(pa, BNX_PCI_BAR0, 450 memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, 451 NULL, &sc->bnx_size) == 0) 452 break; 453 default: 454 aprint_error("%s: can't find mem space\n", 455 sc->bnx_dev.dv_xname); 456 return; 457 } 458 459 if (pci_intr_map(pa, &ih)) { 460 aprint_error("%s: couldn't map interrupt\n", 461 sc->bnx_dev.dv_xname); 462 goto bnx_attach_fail; 463 } 464 465 intrstr = pci_intr_string(pc, ih); 466 467 /* 468 * Configure byte swap and enable indirect register access. 469 * Rely on CPU to do target byte swapping on big endian systems. 470 * Access to registers outside of PCI configurtion space are not 471 * valid until this is done. 472 */ 473 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 474 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 475 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 476 477 /* Save ASIC revsion info. */ 478 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 479 480 /* Weed out any non-production controller revisions. */ 481 switch(BNX_CHIP_ID(sc)) { 482 case BNX_CHIP_ID_5706_A0: 483 case BNX_CHIP_ID_5706_A1: 484 case BNX_CHIP_ID_5708_A0: 485 case BNX_CHIP_ID_5708_B0: 486 aprint_error("%s: unsupported controller revision (%c%d)!\n", 487 sc->bnx_dev.dv_xname, 488 ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A', 489 PCI_REVISION(pa->pa_class) & 0x0f); 490 goto bnx_attach_fail; 491 } 492 493 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 494 aprint_error("%s: SerDes controllers are not supported!\n", 495 sc->bnx_dev.dv_xname); 496 goto bnx_attach_fail; 497 } 498 499 /* 500 * Find the base address for shared memory access. 501 * Newer versions of bootcode use a signature and offset 502 * while older versions use a fixed address. 503 */ 504 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 505 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 506 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0); 507 else 508 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 509 510 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 511 512 /* Set initial device and PHY flags */ 513 sc->bnx_flags = 0; 514 sc->bnx_phy_flags = 0; 515 516 /* Get PCI bus information (speed and type). */ 517 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 518 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 519 u_int32_t clkreg; 520 521 sc->bnx_flags |= BNX_PCIX_FLAG; 522 523 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 524 525 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 526 switch (clkreg) { 527 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 528 sc->bus_speed_mhz = 133; 529 break; 530 531 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 532 sc->bus_speed_mhz = 100; 533 break; 534 535 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 536 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 537 sc->bus_speed_mhz = 66; 538 break; 539 540 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 541 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 542 sc->bus_speed_mhz = 50; 543 break; 544 545 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 546 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 547 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 548 sc->bus_speed_mhz = 33; 549 break; 550 } 551 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 552 sc->bus_speed_mhz = 66; 553 else 554 sc->bus_speed_mhz = 33; 555 556 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 557 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 558 559 /* Reset the controller. */ 560 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 561 goto bnx_attach_fail; 562 563 /* Initialize the controller. */ 564 if (bnx_chipinit(sc)) { 565 aprint_error("%s: Controller initialization failed!\n", 566 sc->bnx_dev.dv_xname); 567 goto bnx_attach_fail; 568 } 569 570 /* Perform NVRAM test. */ 571 if (bnx_nvram_test(sc)) { 572 aprint_error("%s: NVRAM test failed!\n", sc->bnx_dev.dv_xname); 573 goto bnx_attach_fail; 574 } 575 576 /* Fetch the permanent Ethernet MAC address. */ 577 bnx_get_mac_addr(sc); 578 aprint_normal("%s: Ethernet address %s\n", sc->bnx_dev.dv_xname, 579 ether_sprintf(sc->eaddr)); 580 581 /* 582 * Trip points control how many BDs 583 * should be ready before generating an 584 * interrupt while ticks control how long 585 * a BD can sit in the chain before 586 * generating an interrupt. Set the default 587 * values for the RX and TX rings. 588 */ 589 590 #ifdef BNX_DEBUG 591 /* Force more frequent interrupts. */ 592 sc->bnx_tx_quick_cons_trip_int = 1; 593 sc->bnx_tx_quick_cons_trip = 1; 594 sc->bnx_tx_ticks_int = 0; 595 sc->bnx_tx_ticks = 0; 596 597 sc->bnx_rx_quick_cons_trip_int = 1; 598 sc->bnx_rx_quick_cons_trip = 1; 599 sc->bnx_rx_ticks_int = 0; 600 sc->bnx_rx_ticks = 0; 601 #else 602 sc->bnx_tx_quick_cons_trip_int = 20; 603 sc->bnx_tx_quick_cons_trip = 20; 604 sc->bnx_tx_ticks_int = 80; 605 sc->bnx_tx_ticks = 80; 606 607 sc->bnx_rx_quick_cons_trip_int = 6; 608 sc->bnx_rx_quick_cons_trip = 6; 609 sc->bnx_rx_ticks_int = 18; 610 sc->bnx_rx_ticks = 18; 611 #endif 612 613 /* Update statistics once every second. */ 614 sc->bnx_stats_ticks = 1000000 & 0xffff00; 615 616 /* 617 * The copper based NetXtreme II controllers 618 * use an integrated PHY at address 1 while 619 * the SerDes controllers use a PHY at 620 * address 2. 621 */ 622 sc->bnx_phy_addr = 1; 623 624 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 625 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 626 sc->bnx_flags |= BNX_NO_WOL_FLAG; 627 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) { 628 sc->bnx_phy_addr = 2; 629 val = REG_RD_IND(sc, sc->bnx_shmem_base + 630 BNX_SHARED_HW_CFG_CONFIG); 631 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) 632 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 633 } 634 } 635 636 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 637 aprint_error("%s: SerDes is not supported by this driver!\n", 638 sc->bnx_dev.dv_xname); 639 goto bnx_attach_fail; 640 } 641 642 /* Allocate DMA memory resources. */ 643 sc->bnx_dmatag = pa->pa_dmat; 644 if (bnx_dma_alloc(sc)) { 645 aprint_error("%s: DMA resource allocation failed!\n", 646 sc->bnx_dev.dv_xname); 647 goto bnx_attach_fail; 648 } 649 650 /* Initialize the ifnet interface. */ 651 ifp = &sc->ethercom.ec_if; 652 ifp->if_softc = sc; 653 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 654 ifp->if_ioctl = bnx_ioctl; 655 ifp->if_start = bnx_start; 656 ifp->if_init = bnx_init; 657 ifp->if_timer = 0; 658 ifp->if_watchdog = bnx_watchdog; 659 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 660 ifp->if_baudrate = IF_Gbps(2.5); 661 else 662 ifp->if_baudrate = IF_Gbps(1); 663 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 664 IFQ_SET_READY(&ifp->if_snd); 665 bcopy(sc->bnx_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 666 667 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU | 668 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 669 670 ifp->if_capabilities |= 671 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 672 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 673 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 674 675 /* Hookup IRQ last. */ 676 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 677 if (sc->bnx_intrhand == NULL) { 678 aprint_error("%s: couldn't establish interrupt", 679 sc->bnx_dev.dv_xname); 680 if (intrstr != NULL) 681 aprint_error(" at %s", intrstr); 682 aprint_error("\n"); 683 goto bnx_attach_fail; 684 } 685 686 sc->bnx_mii.mii_ifp = ifp; 687 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 688 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 689 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 690 691 /* Look for our PHY. */ 692 ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, 693 bnx_ifmedia_sts); 694 mii_attach(&sc->bnx_dev, &sc->bnx_mii, 0xffffffff, 695 MII_PHY_ANY, MII_OFFSET_ANY, 0); 696 697 if (LIST_FIRST(&sc->bnx_mii.mii_phys) == NULL) { 698 aprint_error("%s: no PHY found!\n", sc->bnx_dev.dv_xname); 699 ifmedia_add(&sc->bnx_mii.mii_media, 700 IFM_ETHER|IFM_MANUAL, 0, NULL); 701 ifmedia_set(&sc->bnx_mii.mii_media, 702 IFM_ETHER|IFM_MANUAL); 703 } else { 704 ifmedia_set(&sc->bnx_mii.mii_media, 705 IFM_ETHER|IFM_AUTO); 706 } 707 708 /* Attach to the Ethernet interface list. */ 709 if_attach(ifp); 710 ether_ifattach(ifp,sc->eaddr); 711 712 callout_init(&sc->bnx_timeout, 0); 713 714 /* Print some important debugging info. */ 715 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 716 717 goto bnx_attach_exit; 718 719 bnx_attach_fail: 720 bnx_release_resources(sc); 721 722 bnx_attach_exit: 723 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 724 } 725 726 /****************************************************************************/ 727 /* Device detach function. */ 728 /* */ 729 /* Stops the controller, resets the controller, and releases resources. */ 730 /* */ 731 /* Returns: */ 732 /* 0 on success, positive value on failure. */ 733 /****************************************************************************/ 734 #if 0 735 void 736 bnx_detach(void *xsc) 737 { 738 struct bnx_softc *sc; 739 struct ifnet *ifp = &sc->arpcom.ac_if; 740 741 sc = device_get_softc(dev); 742 743 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 744 745 /* Stop and reset the controller. */ 746 bnx_stop(sc); 747 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 748 749 ether_ifdetach(ifp); 750 751 /* If we have a child device on the MII bus remove it too. */ 752 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 753 ifmedia_removeall(&sc->bnx_ifmedia); 754 } else { 755 bus_generic_detach(dev); 756 device_delete_child(dev, sc->bnx_mii); 757 } 758 759 /* Release all remaining resources. */ 760 bnx_release_resources(sc); 761 762 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 763 764 return(0); 765 } 766 #endif 767 768 /****************************************************************************/ 769 /* Device shutdown function. */ 770 /* */ 771 /* Stops and resets the controller. */ 772 /* */ 773 /* Returns: */ 774 /* Nothing */ 775 /****************************************************************************/ 776 void 777 bnx_shutdown(void *xsc) 778 { 779 struct bnx_softc *sc = (struct bnx_softc *)xsc; 780 781 bnx_stop(sc); 782 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 783 } 784 785 /****************************************************************************/ 786 /* Indirect register read. */ 787 /* */ 788 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 789 /* configuration space. Using this mechanism avoids issues with posted */ 790 /* reads but is much slower than memory-mapped I/O. */ 791 /* */ 792 /* Returns: */ 793 /* The value of the register. */ 794 /****************************************************************************/ 795 u_int32_t 796 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 797 { 798 struct pci_attach_args *pa = &(sc->bnx_pa); 799 800 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 801 offset); 802 #ifdef BNX_DEBUG 803 { 804 u_int32_t val; 805 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 806 BNX_PCICFG_REG_WINDOW); 807 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 808 "val = 0x%08X\n", __FUNCTION__, offset, val); 809 return (val); 810 } 811 #else 812 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 813 #endif 814 } 815 816 /****************************************************************************/ 817 /* Indirect register write. */ 818 /* */ 819 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 820 /* configuration space. Using this mechanism avoids issues with posted */ 821 /* writes but is muchh slower than memory-mapped I/O. */ 822 /* */ 823 /* Returns: */ 824 /* Nothing. */ 825 /****************************************************************************/ 826 void 827 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 828 { 829 struct pci_attach_args *pa = &(sc->bnx_pa); 830 831 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 832 __FUNCTION__, offset, val); 833 834 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 835 offset); 836 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 837 } 838 839 /****************************************************************************/ 840 /* Context memory write. */ 841 /* */ 842 /* The NetXtreme II controller uses context memory to track connection */ 843 /* information for L2 and higher network protocols. */ 844 /* */ 845 /* Returns: */ 846 /* Nothing. */ 847 /****************************************************************************/ 848 void 849 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, 850 u_int32_t val) 851 { 852 853 DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 854 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 855 856 offset += cid_addr; 857 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 858 REG_WR(sc, BNX_CTX_DATA, val); 859 } 860 861 /****************************************************************************/ 862 /* PHY register read. */ 863 /* */ 864 /* Implements register reads on the MII bus. */ 865 /* */ 866 /* Returns: */ 867 /* The value of the register. */ 868 /****************************************************************************/ 869 int 870 bnx_miibus_read_reg(struct device *dev, int phy, int reg) 871 { 872 struct bnx_softc *sc = (struct bnx_softc *)dev; 873 u_int32_t val; 874 int i; 875 876 /* Make sure we are accessing the correct PHY address. */ 877 if (phy != sc->bnx_phy_addr) { 878 DBPRINT(sc, BNX_VERBOSE, 879 "Invalid PHY address %d for PHY read!\n", phy); 880 return(0); 881 } 882 883 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 884 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 885 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 886 887 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 888 REG_RD(sc, BNX_EMAC_MDIO_MODE); 889 890 DELAY(40); 891 } 892 893 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 894 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 895 BNX_EMAC_MDIO_COMM_START_BUSY; 896 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 897 898 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 899 DELAY(10); 900 901 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 902 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 903 DELAY(5); 904 905 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 906 val &= BNX_EMAC_MDIO_COMM_DATA; 907 908 break; 909 } 910 } 911 912 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 913 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 914 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 915 val = 0x0; 916 } else 917 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 918 919 DBPRINT(sc, BNX_EXCESSIVE, 920 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __FUNCTION__, phy, 921 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 922 923 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 924 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 925 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 926 927 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 928 REG_RD(sc, BNX_EMAC_MDIO_MODE); 929 930 DELAY(40); 931 } 932 933 return (val & 0xffff); 934 } 935 936 /****************************************************************************/ 937 /* PHY register write. */ 938 /* */ 939 /* Implements register writes on the MII bus. */ 940 /* */ 941 /* Returns: */ 942 /* The value of the register. */ 943 /****************************************************************************/ 944 void 945 bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val) 946 { 947 struct bnx_softc *sc = (struct bnx_softc *)dev; 948 u_int32_t val1; 949 int i; 950 951 /* Make sure we are accessing the correct PHY address. */ 952 if (phy != sc->bnx_phy_addr) { 953 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 954 phy); 955 return; 956 } 957 958 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 959 "val = 0x%04X\n", __FUNCTION__, 960 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 961 962 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 963 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 964 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 965 966 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 967 REG_RD(sc, BNX_EMAC_MDIO_MODE); 968 969 DELAY(40); 970 } 971 972 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 973 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 974 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 975 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 976 977 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 978 DELAY(10); 979 980 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 981 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 982 DELAY(5); 983 break; 984 } 985 } 986 987 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 988 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 989 __LINE__); 990 } 991 992 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 993 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 994 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 995 996 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 997 REG_RD(sc, BNX_EMAC_MDIO_MODE); 998 999 DELAY(40); 1000 } 1001 } 1002 1003 /****************************************************************************/ 1004 /* MII bus status change. */ 1005 /* */ 1006 /* Called by the MII bus driver when the PHY establishes link to set the */ 1007 /* MAC interface registers. */ 1008 /* */ 1009 /* Returns: */ 1010 /* Nothing. */ 1011 /****************************************************************************/ 1012 void 1013 bnx_miibus_statchg(struct device *dev) 1014 { 1015 struct bnx_softc *sc = (struct bnx_softc *)dev; 1016 struct mii_data *mii = &sc->bnx_mii; 1017 1018 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT); 1019 1020 /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ 1021 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 1022 DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n"); 1023 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII); 1024 } else { 1025 DBPRINT(sc, BNX_INFO, "Setting MII interface.\n"); 1026 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII); 1027 } 1028 1029 /* Set half or full duplex based on the duplicity 1030 * negotiated by the PHY. 1031 */ 1032 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1033 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1034 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1035 } else { 1036 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1037 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1038 } 1039 } 1040 1041 /****************************************************************************/ 1042 /* Acquire NVRAM lock. */ 1043 /* */ 1044 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1045 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1046 /* for use by the driver. */ 1047 /* */ 1048 /* Returns: */ 1049 /* 0 on success, positive value on failure. */ 1050 /****************************************************************************/ 1051 int 1052 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1053 { 1054 u_int32_t val; 1055 int j; 1056 1057 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1058 1059 /* Request access to the flash interface. */ 1060 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1061 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1062 val = REG_RD(sc, BNX_NVM_SW_ARB); 1063 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1064 break; 1065 1066 DELAY(5); 1067 } 1068 1069 if (j >= NVRAM_TIMEOUT_COUNT) { 1070 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1071 return (EBUSY); 1072 } 1073 1074 return (0); 1075 } 1076 1077 /****************************************************************************/ 1078 /* Release NVRAM lock. */ 1079 /* */ 1080 /* When the caller is finished accessing NVRAM the lock must be released. */ 1081 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1082 /* for use by the driver. */ 1083 /* */ 1084 /* Returns: */ 1085 /* 0 on success, positive value on failure. */ 1086 /****************************************************************************/ 1087 int 1088 bnx_release_nvram_lock(struct bnx_softc *sc) 1089 { 1090 int j; 1091 u_int32_t val; 1092 1093 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1094 1095 /* Relinquish nvram interface. */ 1096 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1097 1098 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1099 val = REG_RD(sc, BNX_NVM_SW_ARB); 1100 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1101 break; 1102 1103 DELAY(5); 1104 } 1105 1106 if (j >= NVRAM_TIMEOUT_COUNT) { 1107 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1108 return (EBUSY); 1109 } 1110 1111 return (0); 1112 } 1113 1114 #ifdef BNX_NVRAM_WRITE_SUPPORT 1115 /****************************************************************************/ 1116 /* Enable NVRAM write access. */ 1117 /* */ 1118 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1119 /* */ 1120 /* Returns: */ 1121 /* 0 on success, positive value on failure. */ 1122 /****************************************************************************/ 1123 int 1124 bnx_enable_nvram_write(struct bnx_softc *sc) 1125 { 1126 u_int32_t val; 1127 1128 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1129 1130 val = REG_RD(sc, BNX_MISC_CFG); 1131 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1132 1133 if (!sc->bnx_flash_info->buffered) { 1134 int j; 1135 1136 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1137 REG_WR(sc, BNX_NVM_COMMAND, 1138 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1139 1140 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1141 DELAY(5); 1142 1143 val = REG_RD(sc, BNX_NVM_COMMAND); 1144 if (val & BNX_NVM_COMMAND_DONE) 1145 break; 1146 } 1147 1148 if (j >= NVRAM_TIMEOUT_COUNT) { 1149 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1150 return (EBUSY); 1151 } 1152 } 1153 1154 return (0); 1155 } 1156 1157 /****************************************************************************/ 1158 /* Disable NVRAM write access. */ 1159 /* */ 1160 /* When the caller is finished writing to NVRAM write access must be */ 1161 /* disabled. */ 1162 /* */ 1163 /* Returns: */ 1164 /* Nothing. */ 1165 /****************************************************************************/ 1166 void 1167 bnx_disable_nvram_write(struct bnx_softc *sc) 1168 { 1169 u_int32_t val; 1170 1171 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1172 1173 val = REG_RD(sc, BNX_MISC_CFG); 1174 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1175 } 1176 #endif 1177 1178 /****************************************************************************/ 1179 /* Enable NVRAM access. */ 1180 /* */ 1181 /* Before accessing NVRAM for read or write operations the caller must */ 1182 /* enabled NVRAM access. */ 1183 /* */ 1184 /* Returns: */ 1185 /* Nothing. */ 1186 /****************************************************************************/ 1187 void 1188 bnx_enable_nvram_access(struct bnx_softc *sc) 1189 { 1190 u_int32_t val; 1191 1192 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1193 1194 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1195 /* Enable both bits, even on read. */ 1196 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1197 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1198 } 1199 1200 /****************************************************************************/ 1201 /* Disable NVRAM access. */ 1202 /* */ 1203 /* When the caller is finished accessing NVRAM access must be disabled. */ 1204 /* */ 1205 /* Returns: */ 1206 /* Nothing. */ 1207 /****************************************************************************/ 1208 void 1209 bnx_disable_nvram_access(struct bnx_softc *sc) 1210 { 1211 u_int32_t val; 1212 1213 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1214 1215 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1216 1217 /* Disable both bits, even after read. */ 1218 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1219 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1220 } 1221 1222 #ifdef BNX_NVRAM_WRITE_SUPPORT 1223 /****************************************************************************/ 1224 /* Erase NVRAM page before writing. */ 1225 /* */ 1226 /* Non-buffered flash parts require that a page be erased before it is */ 1227 /* written. */ 1228 /* */ 1229 /* Returns: */ 1230 /* 0 on success, positive value on failure. */ 1231 /****************************************************************************/ 1232 int 1233 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1234 { 1235 u_int32_t cmd; 1236 int j; 1237 1238 /* Buffered flash doesn't require an erase. */ 1239 if (sc->bnx_flash_info->buffered) 1240 return (0); 1241 1242 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1243 1244 /* Build an erase command. */ 1245 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1246 BNX_NVM_COMMAND_DOIT; 1247 1248 /* 1249 * Clear the DONE bit separately, set the NVRAM adress to erase, 1250 * and issue the erase command. 1251 */ 1252 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1253 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1254 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1255 1256 /* Wait for completion. */ 1257 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1258 u_int32_t val; 1259 1260 DELAY(5); 1261 1262 val = REG_RD(sc, BNX_NVM_COMMAND); 1263 if (val & BNX_NVM_COMMAND_DONE) 1264 break; 1265 } 1266 1267 if (j >= NVRAM_TIMEOUT_COUNT) { 1268 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1269 return (EBUSY); 1270 } 1271 1272 return (0); 1273 } 1274 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1275 1276 /****************************************************************************/ 1277 /* Read a dword (32 bits) from NVRAM. */ 1278 /* */ 1279 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1280 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1281 /* */ 1282 /* Returns: */ 1283 /* 0 on success and the 32 bit value read, positive value on failure. */ 1284 /****************************************************************************/ 1285 int 1286 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1287 u_int8_t *ret_val, u_int32_t cmd_flags) 1288 { 1289 u_int32_t cmd; 1290 int i, rc = 0; 1291 1292 /* Build the command word. */ 1293 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1294 1295 /* Calculate the offset for buffered flash. */ 1296 if (sc->bnx_flash_info->buffered) 1297 offset = ((offset / sc->bnx_flash_info->page_size) << 1298 sc->bnx_flash_info->page_bits) + 1299 (offset % sc->bnx_flash_info->page_size); 1300 1301 /* 1302 * Clear the DONE bit separately, set the address to read, 1303 * and issue the read. 1304 */ 1305 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1306 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1307 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1308 1309 /* Wait for completion. */ 1310 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1311 u_int32_t val; 1312 1313 DELAY(5); 1314 1315 val = REG_RD(sc, BNX_NVM_COMMAND); 1316 if (val & BNX_NVM_COMMAND_DONE) { 1317 val = REG_RD(sc, BNX_NVM_READ); 1318 1319 val = bnx_be32toh(val); 1320 memcpy(ret_val, &val, 4); 1321 break; 1322 } 1323 } 1324 1325 /* Check for errors. */ 1326 if (i >= NVRAM_TIMEOUT_COUNT) { 1327 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1328 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1329 rc = EBUSY; 1330 } 1331 1332 return(rc); 1333 } 1334 1335 #ifdef BNX_NVRAM_WRITE_SUPPORT 1336 /****************************************************************************/ 1337 /* Write a dword (32 bits) to NVRAM. */ 1338 /* */ 1339 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1340 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1341 /* enabled NVRAM write access. */ 1342 /* */ 1343 /* Returns: */ 1344 /* 0 on success, positive value on failure. */ 1345 /****************************************************************************/ 1346 int 1347 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1348 u_int32_t cmd_flags) 1349 { 1350 u_int32_t cmd, val32; 1351 int j; 1352 1353 /* Build the command word. */ 1354 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1355 1356 /* Calculate the offset for buffered flash. */ 1357 if (sc->bnx_flash_info->buffered) 1358 offset = ((offset / sc->bnx_flash_info->page_size) << 1359 sc->bnx_flash_info->page_bits) + 1360 (offset % sc->bnx_flash_info->page_size); 1361 1362 /* 1363 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1364 * set the NVRAM address to write, and issue the write command 1365 */ 1366 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1367 memcpy(&val32, val, 4); 1368 val32 = htobe32(val32); 1369 REG_WR(sc, BNX_NVM_WRITE, val32); 1370 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1371 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1372 1373 /* Wait for completion. */ 1374 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1375 DELAY(5); 1376 1377 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1378 break; 1379 } 1380 if (j >= NVRAM_TIMEOUT_COUNT) { 1381 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1382 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1383 return (EBUSY); 1384 } 1385 1386 return (0); 1387 } 1388 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1389 1390 /****************************************************************************/ 1391 /* Initialize NVRAM access. */ 1392 /* */ 1393 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1394 /* access that device. */ 1395 /* */ 1396 /* Returns: */ 1397 /* 0 on success, positive value on failure. */ 1398 /****************************************************************************/ 1399 int 1400 bnx_init_nvram(struct bnx_softc *sc) 1401 { 1402 u_int32_t val; 1403 int j, entry_count, rc; 1404 struct flash_spec *flash; 1405 1406 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1407 1408 /* Determine the selected interface. */ 1409 val = REG_RD(sc, BNX_NVM_CFG1); 1410 1411 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1412 1413 rc = 0; 1414 1415 /* 1416 * Flash reconfiguration is required to support additional 1417 * NVRAM devices not directly supported in hardware. 1418 * Check if the flash interface was reconfigured 1419 * by the bootcode. 1420 */ 1421 1422 if (val & 0x40000000) { 1423 /* Flash interface reconfigured by bootcode. */ 1424 1425 DBPRINT(sc,BNX_INFO_LOAD, 1426 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1427 1428 for (j = 0, flash = &flash_table[0]; j < entry_count; 1429 j++, flash++) { 1430 if ((val & FLASH_BACKUP_STRAP_MASK) == 1431 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1432 sc->bnx_flash_info = flash; 1433 break; 1434 } 1435 } 1436 } else { 1437 /* Flash interface not yet reconfigured. */ 1438 u_int32_t mask; 1439 1440 DBPRINT(sc,BNX_INFO_LOAD, 1441 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1442 1443 if (val & (1 << 23)) 1444 mask = FLASH_BACKUP_STRAP_MASK; 1445 else 1446 mask = FLASH_STRAP_MASK; 1447 1448 /* Look for the matching NVRAM device configuration data. */ 1449 for (j = 0, flash = &flash_table[0]; j < entry_count; 1450 j++, flash++) { 1451 /* Check if the dev matches any of the known devices. */ 1452 if ((val & mask) == (flash->strapping & mask)) { 1453 /* Found a device match. */ 1454 sc->bnx_flash_info = flash; 1455 1456 /* Request access to the flash interface. */ 1457 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1458 return (rc); 1459 1460 /* Reconfigure the flash interface. */ 1461 bnx_enable_nvram_access(sc); 1462 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1463 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1464 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1465 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1466 bnx_disable_nvram_access(sc); 1467 bnx_release_nvram_lock(sc); 1468 1469 break; 1470 } 1471 } 1472 } 1473 1474 /* Check if a matching device was found. */ 1475 if (j == entry_count) { 1476 sc->bnx_flash_info = NULL; 1477 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1478 __FILE__, __LINE__); 1479 rc = ENODEV; 1480 } 1481 1482 /* Write the flash config data to the shared memory interface. */ 1483 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1484 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1485 if (val) 1486 sc->bnx_flash_size = val; 1487 else 1488 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1489 1490 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1491 "0x%08X\n", sc->bnx_flash_info->total_size); 1492 1493 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1494 1495 return (rc); 1496 } 1497 1498 /****************************************************************************/ 1499 /* Read an arbitrary range of data from NVRAM. */ 1500 /* */ 1501 /* Prepares the NVRAM interface for access and reads the requested data */ 1502 /* into the supplied buffer. */ 1503 /* */ 1504 /* Returns: */ 1505 /* 0 on success and the data read, positive value on failure. */ 1506 /****************************************************************************/ 1507 int 1508 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1509 int buf_size) 1510 { 1511 int rc = 0; 1512 u_int32_t cmd_flags, offset32, len32, extra; 1513 1514 if (buf_size == 0) 1515 return (0); 1516 1517 /* Request access to the flash interface. */ 1518 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1519 return (rc); 1520 1521 /* Enable access to flash interface */ 1522 bnx_enable_nvram_access(sc); 1523 1524 len32 = buf_size; 1525 offset32 = offset; 1526 extra = 0; 1527 1528 cmd_flags = 0; 1529 1530 if (offset32 & 3) { 1531 u_int8_t buf[4]; 1532 u_int32_t pre_len; 1533 1534 offset32 &= ~3; 1535 pre_len = 4 - (offset & 3); 1536 1537 if (pre_len >= len32) { 1538 pre_len = len32; 1539 cmd_flags = 1540 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1541 } else 1542 cmd_flags = BNX_NVM_COMMAND_FIRST; 1543 1544 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1545 1546 if (rc) 1547 return (rc); 1548 1549 memcpy(ret_buf, buf + (offset & 3), pre_len); 1550 1551 offset32 += 4; 1552 ret_buf += pre_len; 1553 len32 -= pre_len; 1554 } 1555 1556 if (len32 & 3) { 1557 extra = 4 - (len32 & 3); 1558 len32 = (len32 + 4) & ~3; 1559 } 1560 1561 if (len32 == 4) { 1562 u_int8_t buf[4]; 1563 1564 if (cmd_flags) 1565 cmd_flags = BNX_NVM_COMMAND_LAST; 1566 else 1567 cmd_flags = 1568 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1569 1570 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1571 1572 memcpy(ret_buf, buf, 4 - extra); 1573 } else if (len32 > 0) { 1574 u_int8_t buf[4]; 1575 1576 /* Read the first word. */ 1577 if (cmd_flags) 1578 cmd_flags = 0; 1579 else 1580 cmd_flags = BNX_NVM_COMMAND_FIRST; 1581 1582 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1583 1584 /* Advance to the next dword. */ 1585 offset32 += 4; 1586 ret_buf += 4; 1587 len32 -= 4; 1588 1589 while (len32 > 4 && rc == 0) { 1590 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1591 1592 /* Advance to the next dword. */ 1593 offset32 += 4; 1594 ret_buf += 4; 1595 len32 -= 4; 1596 } 1597 1598 if (rc) 1599 return (rc); 1600 1601 cmd_flags = BNX_NVM_COMMAND_LAST; 1602 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1603 1604 memcpy(ret_buf, buf, 4 - extra); 1605 } 1606 1607 /* Disable access to flash interface and release the lock. */ 1608 bnx_disable_nvram_access(sc); 1609 bnx_release_nvram_lock(sc); 1610 1611 return (rc); 1612 } 1613 1614 #ifdef BNX_NVRAM_WRITE_SUPPORT 1615 /****************************************************************************/ 1616 /* Write an arbitrary range of data from NVRAM. */ 1617 /* */ 1618 /* Prepares the NVRAM interface for write access and writes the requested */ 1619 /* data from the supplied buffer. The caller is responsible for */ 1620 /* calculating any appropriate CRCs. */ 1621 /* */ 1622 /* Returns: */ 1623 /* 0 on success, positive value on failure. */ 1624 /****************************************************************************/ 1625 int 1626 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1627 int buf_size) 1628 { 1629 u_int32_t written, offset32, len32; 1630 u_int8_t *buf, start[4], end[4]; 1631 int rc = 0; 1632 int align_start, align_end; 1633 1634 buf = data_buf; 1635 offset32 = offset; 1636 len32 = buf_size; 1637 align_start = align_end = 0; 1638 1639 if ((align_start = (offset32 & 3))) { 1640 offset32 &= ~3; 1641 len32 += align_start; 1642 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1643 return (rc); 1644 } 1645 1646 if (len32 & 3) { 1647 if ((len32 > 4) || !align_start) { 1648 align_end = 4 - (len32 & 3); 1649 len32 += align_end; 1650 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1651 end, 4))) { 1652 return (rc); 1653 } 1654 } 1655 } 1656 1657 if (align_start || align_end) { 1658 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1659 if (buf == 0) 1660 return (ENOMEM); 1661 1662 if (align_start) 1663 memcpy(buf, start, 4); 1664 1665 if (align_end) 1666 memcpy(buf + len32 - 4, end, 4); 1667 1668 memcpy(buf + align_start, data_buf, buf_size); 1669 } 1670 1671 written = 0; 1672 while ((written < len32) && (rc == 0)) { 1673 u_int32_t page_start, page_end, data_start, data_end; 1674 u_int32_t addr, cmd_flags; 1675 int i; 1676 u_int8_t flash_buffer[264]; 1677 1678 /* Find the page_start addr */ 1679 page_start = offset32 + written; 1680 page_start -= (page_start % sc->bnx_flash_info->page_size); 1681 /* Find the page_end addr */ 1682 page_end = page_start + sc->bnx_flash_info->page_size; 1683 /* Find the data_start addr */ 1684 data_start = (written == 0) ? offset32 : page_start; 1685 /* Find the data_end addr */ 1686 data_end = (page_end > offset32 + len32) ? 1687 (offset32 + len32) : page_end; 1688 1689 /* Request access to the flash interface. */ 1690 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1691 goto nvram_write_end; 1692 1693 /* Enable access to flash interface */ 1694 bnx_enable_nvram_access(sc); 1695 1696 cmd_flags = BNX_NVM_COMMAND_FIRST; 1697 if (sc->bnx_flash_info->buffered == 0) { 1698 int j; 1699 1700 /* Read the whole page into the buffer 1701 * (non-buffer flash only) */ 1702 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1703 if (j == (sc->bnx_flash_info->page_size - 4)) 1704 cmd_flags |= BNX_NVM_COMMAND_LAST; 1705 1706 rc = bnx_nvram_read_dword(sc, 1707 page_start + j, 1708 &flash_buffer[j], 1709 cmd_flags); 1710 1711 if (rc) 1712 goto nvram_write_end; 1713 1714 cmd_flags = 0; 1715 } 1716 } 1717 1718 /* Enable writes to flash interface (unlock write-protect) */ 1719 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1720 goto nvram_write_end; 1721 1722 /* Erase the page */ 1723 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1724 goto nvram_write_end; 1725 1726 /* Re-enable the write again for the actual write */ 1727 bnx_enable_nvram_write(sc); 1728 1729 /* Loop to write back the buffer data from page_start to 1730 * data_start */ 1731 i = 0; 1732 if (sc->bnx_flash_info->buffered == 0) { 1733 for (addr = page_start; addr < data_start; 1734 addr += 4, i += 4) { 1735 1736 rc = bnx_nvram_write_dword(sc, addr, 1737 &flash_buffer[i], cmd_flags); 1738 1739 if (rc != 0) 1740 goto nvram_write_end; 1741 1742 cmd_flags = 0; 1743 } 1744 } 1745 1746 /* Loop to write the new data from data_start to data_end */ 1747 for (addr = data_start; addr < data_end; addr += 4, i++) { 1748 if ((addr == page_end - 4) || 1749 ((sc->bnx_flash_info->buffered) && 1750 (addr == data_end - 4))) { 1751 1752 cmd_flags |= BNX_NVM_COMMAND_LAST; 1753 } 1754 1755 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1756 1757 if (rc != 0) 1758 goto nvram_write_end; 1759 1760 cmd_flags = 0; 1761 buf += 4; 1762 } 1763 1764 /* Loop to write back the buffer data from data_end 1765 * to page_end */ 1766 if (sc->bnx_flash_info->buffered == 0) { 1767 for (addr = data_end; addr < page_end; 1768 addr += 4, i += 4) { 1769 1770 if (addr == page_end-4) 1771 cmd_flags = BNX_NVM_COMMAND_LAST; 1772 1773 rc = bnx_nvram_write_dword(sc, addr, 1774 &flash_buffer[i], cmd_flags); 1775 1776 if (rc != 0) 1777 goto nvram_write_end; 1778 1779 cmd_flags = 0; 1780 } 1781 } 1782 1783 /* Disable writes to flash interface (lock write-protect) */ 1784 bnx_disable_nvram_write(sc); 1785 1786 /* Disable access to flash interface */ 1787 bnx_disable_nvram_access(sc); 1788 bnx_release_nvram_lock(sc); 1789 1790 /* Increment written */ 1791 written += data_end - data_start; 1792 } 1793 1794 nvram_write_end: 1795 if (align_start || align_end) 1796 free(buf, M_DEVBUF); 1797 1798 return (rc); 1799 } 1800 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1801 1802 /****************************************************************************/ 1803 /* Verifies that NVRAM is accessible and contains valid data. */ 1804 /* */ 1805 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1806 /* correct. */ 1807 /* */ 1808 /* Returns: */ 1809 /* 0 on success, positive value on failure. */ 1810 /****************************************************************************/ 1811 int 1812 bnx_nvram_test(struct bnx_softc *sc) 1813 { 1814 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1815 u_int8_t *data = (u_int8_t *) buf; 1816 int rc = 0; 1817 u_int32_t magic, csum; 1818 1819 /* 1820 * Check that the device NVRAM is valid by reading 1821 * the magic value at offset 0. 1822 */ 1823 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1824 goto bnx_nvram_test_done; 1825 1826 magic = bnx_be32toh(buf[0]); 1827 if (magic != BNX_NVRAM_MAGIC) { 1828 rc = ENODEV; 1829 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1830 "Expected: 0x%08X, Found: 0x%08X\n", 1831 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1832 goto bnx_nvram_test_done; 1833 } 1834 1835 /* 1836 * Verify that the device NVRAM includes valid 1837 * configuration data. 1838 */ 1839 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1840 goto bnx_nvram_test_done; 1841 1842 csum = ether_crc32_le(data, 0x100); 1843 if (csum != BNX_CRC32_RESIDUAL) { 1844 rc = ENODEV; 1845 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1846 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1847 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1848 goto bnx_nvram_test_done; 1849 } 1850 1851 csum = ether_crc32_le(data + 0x100, 0x100); 1852 if (csum != BNX_CRC32_RESIDUAL) { 1853 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1854 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1855 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1856 rc = ENODEV; 1857 } 1858 1859 bnx_nvram_test_done: 1860 return (rc); 1861 } 1862 1863 /****************************************************************************/ 1864 /* Free any DMA memory owned by the driver. */ 1865 /* */ 1866 /* Scans through each data structre that requires DMA memory and frees */ 1867 /* the memory if allocated. */ 1868 /* */ 1869 /* Returns: */ 1870 /* Nothing. */ 1871 /****************************************************************************/ 1872 void 1873 bnx_dma_free(struct bnx_softc *sc) 1874 { 1875 int i; 1876 1877 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1878 1879 /* Destroy the status block. */ 1880 if (sc->status_block != NULL && sc->status_map != NULL) { 1881 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 1882 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 1883 BNX_STATUS_BLK_SZ); 1884 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 1885 sc->status_rseg); 1886 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 1887 sc->status_block = NULL; 1888 sc->status_map = NULL; 1889 } 1890 1891 /* Destroy the statistics block. */ 1892 if (sc->stats_block != NULL && sc->stats_map != NULL) { 1893 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 1894 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 1895 BNX_STATS_BLK_SZ); 1896 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 1897 sc->stats_rseg); 1898 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 1899 sc->stats_block = NULL; 1900 sc->stats_map = NULL; 1901 } 1902 1903 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 1904 for (i = 0; i < TX_PAGES; i++ ) { 1905 if (sc->tx_bd_chain[i] != NULL && 1906 sc->tx_bd_chain_map[i] != NULL) { 1907 bus_dmamap_unload(sc->bnx_dmatag, 1908 sc->tx_bd_chain_map[i]); 1909 bus_dmamem_unmap(sc->bnx_dmatag, 1910 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 1911 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 1912 sc->tx_bd_chain_rseg[i]); 1913 bus_dmamap_destroy(sc->bnx_dmatag, 1914 sc->tx_bd_chain_map[i]); 1915 sc->tx_bd_chain[i] = NULL; 1916 sc->tx_bd_chain_map[i] = NULL; 1917 } 1918 } 1919 1920 /* Unload and destroy the TX mbuf maps. */ 1921 for (i = 0; i < TOTAL_TX_BD; i++) { 1922 if (sc->tx_mbuf_map[i] != NULL) { 1923 bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1924 bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1925 } 1926 } 1927 1928 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 1929 for (i = 0; i < RX_PAGES; i++ ) { 1930 if (sc->rx_bd_chain[i] != NULL && 1931 sc->rx_bd_chain_map[i] != NULL) { 1932 bus_dmamap_unload(sc->bnx_dmatag, 1933 sc->rx_bd_chain_map[i]); 1934 bus_dmamem_unmap(sc->bnx_dmatag, 1935 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 1936 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 1937 sc->rx_bd_chain_rseg[i]); 1938 1939 bus_dmamap_destroy(sc->bnx_dmatag, 1940 sc->rx_bd_chain_map[i]); 1941 sc->rx_bd_chain[i] = NULL; 1942 sc->rx_bd_chain_map[i] = NULL; 1943 } 1944 } 1945 1946 /* Unload and destroy the RX mbuf maps. */ 1947 for (i = 0; i < TOTAL_RX_BD; i++) { 1948 if (sc->rx_mbuf_map[i] != NULL) { 1949 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1950 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1951 } 1952 } 1953 1954 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1955 } 1956 1957 /****************************************************************************/ 1958 /* Allocate any DMA memory needed by the driver. */ 1959 /* */ 1960 /* Allocates DMA memory needed for the various global structures needed by */ 1961 /* hardware. */ 1962 /* */ 1963 /* Returns: */ 1964 /* 0 for success, positive value for failure. */ 1965 /****************************************************************************/ 1966 int 1967 bnx_dma_alloc(struct bnx_softc *sc) 1968 { 1969 int i, rc = 0; 1970 1971 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1972 1973 /* 1974 * Allocate DMA memory for the status block, map the memory into DMA 1975 * space, and fetch the physical address of the block. 1976 */ 1977 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 1978 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 1979 aprint_error("%s: Could not create status block DMA map!\n", 1980 sc->bnx_dev.dv_xname); 1981 rc = ENOMEM; 1982 goto bnx_dma_alloc_exit; 1983 } 1984 1985 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1986 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 1987 &sc->status_rseg, BUS_DMA_NOWAIT)) { 1988 aprint_error( 1989 "%s: Could not allocate status block DMA memory!\n", 1990 sc->bnx_dev.dv_xname); 1991 rc = ENOMEM; 1992 goto bnx_dma_alloc_exit; 1993 } 1994 1995 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 1996 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 1997 aprint_error("%s: Could not map status block DMA memory!\n", 1998 sc->bnx_dev.dv_xname); 1999 rc = ENOMEM; 2000 goto bnx_dma_alloc_exit; 2001 } 2002 2003 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2004 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2005 aprint_error("%s: Could not load status block DMA memory!\n", 2006 sc->bnx_dev.dv_xname); 2007 rc = ENOMEM; 2008 goto bnx_dma_alloc_exit; 2009 } 2010 2011 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2012 bzero(sc->status_block, BNX_STATUS_BLK_SZ); 2013 2014 /* DRC - Fix for 64 bit addresses. */ 2015 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2016 (u_int32_t) sc->status_block_paddr); 2017 2018 /* 2019 * Allocate DMA memory for the statistics block, map the memory into 2020 * DMA space, and fetch the physical address of the block. 2021 */ 2022 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2023 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2024 aprint_error("%s: Could not create stats block DMA map!\n", 2025 sc->bnx_dev.dv_xname); 2026 rc = ENOMEM; 2027 goto bnx_dma_alloc_exit; 2028 } 2029 2030 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2031 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2032 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2033 aprint_error("%s: Could not allocate stats block DMA memory!\n", 2034 sc->bnx_dev.dv_xname); 2035 rc = ENOMEM; 2036 goto bnx_dma_alloc_exit; 2037 } 2038 2039 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2040 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2041 aprint_error("%s: Could not map stats block DMA memory!\n", 2042 sc->bnx_dev.dv_xname); 2043 rc = ENOMEM; 2044 goto bnx_dma_alloc_exit; 2045 } 2046 2047 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2048 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2049 aprint_error("%s: Could not load status block DMA memory!\n", 2050 sc->bnx_dev.dv_xname); 2051 rc = ENOMEM; 2052 goto bnx_dma_alloc_exit; 2053 } 2054 2055 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2056 bzero(sc->stats_block, BNX_STATS_BLK_SZ); 2057 2058 /* DRC - Fix for 64 bit address. */ 2059 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2060 (u_int32_t) sc->stats_block_paddr); 2061 2062 /* 2063 * Allocate DMA memory for the TX buffer descriptor chain, 2064 * and fetch the physical address of the block. 2065 */ 2066 for (i = 0; i < TX_PAGES; i++) { 2067 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2068 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2069 &sc->tx_bd_chain_map[i])) { 2070 aprint_error( 2071 "%s: Could not create Tx desc %d DMA map!\n", 2072 sc->bnx_dev.dv_xname, i); 2073 rc = ENOMEM; 2074 goto bnx_dma_alloc_exit; 2075 } 2076 2077 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2078 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2079 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2080 aprint_error( 2081 "%s: Could not allocate TX desc %d DMA memory!\n", 2082 sc->bnx_dev.dv_xname, i); 2083 rc = ENOMEM; 2084 goto bnx_dma_alloc_exit; 2085 } 2086 2087 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2088 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2089 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2090 aprint_error( 2091 "%s: Could not map TX desc %d DMA memory!\n", 2092 sc->bnx_dev.dv_xname, i); 2093 rc = ENOMEM; 2094 goto bnx_dma_alloc_exit; 2095 } 2096 2097 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2098 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2099 BUS_DMA_NOWAIT)) { 2100 aprint_error( 2101 "%s: Could not load TX desc %d DMA memory!\n", 2102 sc->bnx_dev.dv_xname, i); 2103 rc = ENOMEM; 2104 goto bnx_dma_alloc_exit; 2105 } 2106 2107 sc->tx_bd_chain_paddr[i] = 2108 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2109 2110 /* DRC - Fix for 64 bit systems. */ 2111 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2112 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2113 } 2114 2115 /* 2116 * Create DMA maps for the TX buffer mbufs. 2117 */ 2118 for (i = 0; i < TOTAL_TX_BD; i++) { 2119 if (bus_dmamap_create(sc->bnx_dmatag, 2120 MCLBYTES * BNX_MAX_SEGMENTS, 2121 USABLE_TX_BD - BNX_TX_SLACK_SPACE, 2122 MCLBYTES, 0, BUS_DMA_NOWAIT, 2123 &sc->tx_mbuf_map[i])) { 2124 aprint_error( 2125 "%s: Could not create Tx mbuf %d DMA map!\n", 2126 sc->bnx_dev.dv_xname, i); 2127 rc = ENOMEM; 2128 goto bnx_dma_alloc_exit; 2129 } 2130 } 2131 2132 /* 2133 * Allocate DMA memory for the Rx buffer descriptor chain, 2134 * and fetch the physical address of the block. 2135 */ 2136 for (i = 0; i < RX_PAGES; i++) { 2137 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2138 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2139 &sc->rx_bd_chain_map[i])) { 2140 aprint_error( 2141 "%s: Could not create Rx desc %d DMA map!\n", 2142 sc->bnx_dev.dv_xname, i); 2143 rc = ENOMEM; 2144 goto bnx_dma_alloc_exit; 2145 } 2146 2147 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2148 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2149 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2150 aprint_error( 2151 "%s: Could not allocate Rx desc %d DMA memory!\n", 2152 sc->bnx_dev.dv_xname, i); 2153 rc = ENOMEM; 2154 goto bnx_dma_alloc_exit; 2155 } 2156 2157 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2158 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2159 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2160 aprint_error( 2161 "%s: Could not map Rx desc %d DMA memory!\n", 2162 sc->bnx_dev.dv_xname, i); 2163 rc = ENOMEM; 2164 goto bnx_dma_alloc_exit; 2165 } 2166 2167 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2168 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2169 BUS_DMA_NOWAIT)) { 2170 aprint_error( 2171 "%s: Could not load Rx desc %d DMA memory!\n", 2172 sc->bnx_dev.dv_xname, i); 2173 rc = ENOMEM; 2174 goto bnx_dma_alloc_exit; 2175 } 2176 2177 bzero(sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2178 sc->rx_bd_chain_paddr[i] = 2179 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2180 2181 /* DRC - Fix for 64 bit systems. */ 2182 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2183 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2184 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2185 0, BNX_RX_CHAIN_PAGE_SZ, 2186 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2187 } 2188 2189 /* 2190 * Create DMA maps for the Rx buffer mbufs. 2191 */ 2192 for (i = 0; i < TOTAL_RX_BD; i++) { 2193 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU, 2194 BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT, 2195 &sc->rx_mbuf_map[i])) { 2196 aprint_error( 2197 "%s: Could not create Rx mbuf %d DMA map!\n", 2198 sc->bnx_dev.dv_xname, i); 2199 rc = ENOMEM; 2200 goto bnx_dma_alloc_exit; 2201 } 2202 } 2203 2204 bnx_dma_alloc_exit: 2205 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2206 2207 return(rc); 2208 } 2209 2210 /****************************************************************************/ 2211 /* Release all resources used by the driver. */ 2212 /* */ 2213 /* Releases all resources acquired by the driver including interrupts, */ 2214 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2215 /* */ 2216 /* Returns: */ 2217 /* Nothing. */ 2218 /****************************************************************************/ 2219 void 2220 bnx_release_resources(struct bnx_softc *sc) 2221 { 2222 struct pci_attach_args *pa = &(sc->bnx_pa); 2223 2224 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2225 2226 bnx_dma_free(sc); 2227 2228 if (sc->bnx_intrhand != NULL) 2229 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2230 2231 if (sc->bnx_size) 2232 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2233 2234 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2235 } 2236 2237 /****************************************************************************/ 2238 /* Firmware synchronization. */ 2239 /* */ 2240 /* Before performing certain events such as a chip reset, synchronize with */ 2241 /* the firmware first. */ 2242 /* */ 2243 /* Returns: */ 2244 /* 0 for success, positive value for failure. */ 2245 /****************************************************************************/ 2246 int 2247 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2248 { 2249 int i, rc = 0; 2250 u_int32_t val; 2251 2252 /* Don't waste any time if we've timed out before. */ 2253 if (sc->bnx_fw_timed_out) { 2254 rc = EBUSY; 2255 goto bnx_fw_sync_exit; 2256 } 2257 2258 /* Increment the message sequence number. */ 2259 sc->bnx_fw_wr_seq++; 2260 msg_data |= sc->bnx_fw_wr_seq; 2261 2262 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2263 msg_data); 2264 2265 /* Send the message to the bootcode driver mailbox. */ 2266 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2267 2268 /* Wait for the bootcode to acknowledge the message. */ 2269 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2270 /* Check for a response in the bootcode firmware mailbox. */ 2271 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2272 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2273 break; 2274 DELAY(1000); 2275 } 2276 2277 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2278 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2279 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2280 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2281 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2282 2283 msg_data &= ~BNX_DRV_MSG_CODE; 2284 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2285 2286 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2287 2288 sc->bnx_fw_timed_out = 1; 2289 rc = EBUSY; 2290 } 2291 2292 bnx_fw_sync_exit: 2293 return (rc); 2294 } 2295 2296 /****************************************************************************/ 2297 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2298 /* */ 2299 /* Returns: */ 2300 /* Nothing. */ 2301 /****************************************************************************/ 2302 void 2303 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2304 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2305 { 2306 int i; 2307 u_int32_t val; 2308 2309 for (i = 0; i < rv2p_code_len; i += 8) { 2310 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2311 rv2p_code++; 2312 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2313 rv2p_code++; 2314 2315 if (rv2p_proc == RV2P_PROC1) { 2316 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2317 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2318 } 2319 else { 2320 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2321 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2322 } 2323 } 2324 2325 /* Reset the processor, un-stall is done later. */ 2326 if (rv2p_proc == RV2P_PROC1) 2327 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2328 else 2329 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2330 } 2331 2332 /****************************************************************************/ 2333 /* Load RISC processor firmware. */ 2334 /* */ 2335 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2336 /* associated with a particular processor. */ 2337 /* */ 2338 /* Returns: */ 2339 /* Nothing. */ 2340 /****************************************************************************/ 2341 void 2342 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2343 struct fw_info *fw) 2344 { 2345 u_int32_t offset; 2346 u_int32_t val; 2347 2348 /* Halt the CPU. */ 2349 val = REG_RD_IND(sc, cpu_reg->mode); 2350 val |= cpu_reg->mode_value_halt; 2351 REG_WR_IND(sc, cpu_reg->mode, val); 2352 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2353 2354 /* Load the Text area. */ 2355 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2356 if (fw->text) { 2357 int j; 2358 2359 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2360 REG_WR_IND(sc, offset, fw->text[j]); 2361 } 2362 2363 /* Load the Data area. */ 2364 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2365 if (fw->data) { 2366 int j; 2367 2368 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2369 REG_WR_IND(sc, offset, fw->data[j]); 2370 } 2371 2372 /* Load the SBSS area. */ 2373 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2374 if (fw->sbss) { 2375 int j; 2376 2377 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2378 REG_WR_IND(sc, offset, fw->sbss[j]); 2379 } 2380 2381 /* Load the BSS area. */ 2382 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2383 if (fw->bss) { 2384 int j; 2385 2386 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2387 REG_WR_IND(sc, offset, fw->bss[j]); 2388 } 2389 2390 /* Load the Read-Only area. */ 2391 offset = cpu_reg->spad_base + 2392 (fw->rodata_addr - cpu_reg->mips_view_base); 2393 if (fw->rodata) { 2394 int j; 2395 2396 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2397 REG_WR_IND(sc, offset, fw->rodata[j]); 2398 } 2399 2400 /* Clear the pre-fetch instruction. */ 2401 REG_WR_IND(sc, cpu_reg->inst, 0); 2402 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2403 2404 /* Start the CPU. */ 2405 val = REG_RD_IND(sc, cpu_reg->mode); 2406 val &= ~cpu_reg->mode_value_halt; 2407 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2408 REG_WR_IND(sc, cpu_reg->mode, val); 2409 } 2410 2411 /****************************************************************************/ 2412 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2413 /* */ 2414 /* Loads the firmware for each CPU and starts the CPU. */ 2415 /* */ 2416 /* Returns: */ 2417 /* Nothing. */ 2418 /****************************************************************************/ 2419 void 2420 bnx_init_cpus(struct bnx_softc *sc) 2421 { 2422 struct cpu_reg cpu_reg; 2423 struct fw_info fw; 2424 2425 /* Initialize the RV2P processor. */ 2426 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2427 RV2P_PROC1); 2428 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2429 RV2P_PROC2); 2430 2431 /* Initialize the RX Processor. */ 2432 cpu_reg.mode = BNX_RXP_CPU_MODE; 2433 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2434 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2435 cpu_reg.state = BNX_RXP_CPU_STATE; 2436 cpu_reg.state_value_clear = 0xffffff; 2437 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2438 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2439 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2440 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2441 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2442 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2443 cpu_reg.mips_view_base = 0x8000000; 2444 2445 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2446 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2447 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2448 fw.start_addr = bnx_RXP_b06FwStartAddr; 2449 2450 fw.text_addr = bnx_RXP_b06FwTextAddr; 2451 fw.text_len = bnx_RXP_b06FwTextLen; 2452 fw.text_index = 0; 2453 fw.text = bnx_RXP_b06FwText; 2454 2455 fw.data_addr = bnx_RXP_b06FwDataAddr; 2456 fw.data_len = bnx_RXP_b06FwDataLen; 2457 fw.data_index = 0; 2458 fw.data = bnx_RXP_b06FwData; 2459 2460 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2461 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2462 fw.sbss_index = 0; 2463 fw.sbss = bnx_RXP_b06FwSbss; 2464 2465 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2466 fw.bss_len = bnx_RXP_b06FwBssLen; 2467 fw.bss_index = 0; 2468 fw.bss = bnx_RXP_b06FwBss; 2469 2470 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2471 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2472 fw.rodata_index = 0; 2473 fw.rodata = bnx_RXP_b06FwRodata; 2474 2475 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2476 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2477 2478 /* Initialize the TX Processor. */ 2479 cpu_reg.mode = BNX_TXP_CPU_MODE; 2480 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2481 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2482 cpu_reg.state = BNX_TXP_CPU_STATE; 2483 cpu_reg.state_value_clear = 0xffffff; 2484 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2485 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2486 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2487 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2488 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2489 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2490 cpu_reg.mips_view_base = 0x8000000; 2491 2492 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2493 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2494 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2495 fw.start_addr = bnx_TXP_b06FwStartAddr; 2496 2497 fw.text_addr = bnx_TXP_b06FwTextAddr; 2498 fw.text_len = bnx_TXP_b06FwTextLen; 2499 fw.text_index = 0; 2500 fw.text = bnx_TXP_b06FwText; 2501 2502 fw.data_addr = bnx_TXP_b06FwDataAddr; 2503 fw.data_len = bnx_TXP_b06FwDataLen; 2504 fw.data_index = 0; 2505 fw.data = bnx_TXP_b06FwData; 2506 2507 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2508 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2509 fw.sbss_index = 0; 2510 fw.sbss = bnx_TXP_b06FwSbss; 2511 2512 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2513 fw.bss_len = bnx_TXP_b06FwBssLen; 2514 fw.bss_index = 0; 2515 fw.bss = bnx_TXP_b06FwBss; 2516 2517 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 2518 fw.rodata_len = bnx_TXP_b06FwRodataLen; 2519 fw.rodata_index = 0; 2520 fw.rodata = bnx_TXP_b06FwRodata; 2521 2522 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2523 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2524 2525 /* Initialize the TX Patch-up Processor. */ 2526 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2527 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2528 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2529 cpu_reg.state = BNX_TPAT_CPU_STATE; 2530 cpu_reg.state_value_clear = 0xffffff; 2531 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2532 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2533 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2534 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2535 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2536 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2537 cpu_reg.mips_view_base = 0x8000000; 2538 2539 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 2540 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 2541 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 2542 fw.start_addr = bnx_TPAT_b06FwStartAddr; 2543 2544 fw.text_addr = bnx_TPAT_b06FwTextAddr; 2545 fw.text_len = bnx_TPAT_b06FwTextLen; 2546 fw.text_index = 0; 2547 fw.text = bnx_TPAT_b06FwText; 2548 2549 fw.data_addr = bnx_TPAT_b06FwDataAddr; 2550 fw.data_len = bnx_TPAT_b06FwDataLen; 2551 fw.data_index = 0; 2552 fw.data = bnx_TPAT_b06FwData; 2553 2554 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 2555 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 2556 fw.sbss_index = 0; 2557 fw.sbss = bnx_TPAT_b06FwSbss; 2558 2559 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 2560 fw.bss_len = bnx_TPAT_b06FwBssLen; 2561 fw.bss_index = 0; 2562 fw.bss = bnx_TPAT_b06FwBss; 2563 2564 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 2565 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 2566 fw.rodata_index = 0; 2567 fw.rodata = bnx_TPAT_b06FwRodata; 2568 2569 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2570 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2571 2572 /* Initialize the Completion Processor. */ 2573 cpu_reg.mode = BNX_COM_CPU_MODE; 2574 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2575 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2576 cpu_reg.state = BNX_COM_CPU_STATE; 2577 cpu_reg.state_value_clear = 0xffffff; 2578 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2579 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2580 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2581 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2582 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2583 cpu_reg.spad_base = BNX_COM_SCRATCH; 2584 cpu_reg.mips_view_base = 0x8000000; 2585 2586 fw.ver_major = bnx_COM_b06FwReleaseMajor; 2587 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 2588 fw.ver_fix = bnx_COM_b06FwReleaseFix; 2589 fw.start_addr = bnx_COM_b06FwStartAddr; 2590 2591 fw.text_addr = bnx_COM_b06FwTextAddr; 2592 fw.text_len = bnx_COM_b06FwTextLen; 2593 fw.text_index = 0; 2594 fw.text = bnx_COM_b06FwText; 2595 2596 fw.data_addr = bnx_COM_b06FwDataAddr; 2597 fw.data_len = bnx_COM_b06FwDataLen; 2598 fw.data_index = 0; 2599 fw.data = bnx_COM_b06FwData; 2600 2601 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 2602 fw.sbss_len = bnx_COM_b06FwSbssLen; 2603 fw.sbss_index = 0; 2604 fw.sbss = bnx_COM_b06FwSbss; 2605 2606 fw.bss_addr = bnx_COM_b06FwBssAddr; 2607 fw.bss_len = bnx_COM_b06FwBssLen; 2608 fw.bss_index = 0; 2609 fw.bss = bnx_COM_b06FwBss; 2610 2611 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 2612 fw.rodata_len = bnx_COM_b06FwRodataLen; 2613 fw.rodata_index = 0; 2614 fw.rodata = bnx_COM_b06FwRodata; 2615 2616 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2617 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2618 } 2619 2620 /****************************************************************************/ 2621 /* Initialize context memory. */ 2622 /* */ 2623 /* Clears the memory associated with each Context ID (CID). */ 2624 /* */ 2625 /* Returns: */ 2626 /* Nothing. */ 2627 /****************************************************************************/ 2628 void 2629 bnx_init_context(struct bnx_softc *sc) 2630 { 2631 u_int32_t vcid; 2632 2633 vcid = 96; 2634 while (vcid) { 2635 u_int32_t vcid_addr, pcid_addr, offset; 2636 2637 vcid--; 2638 2639 vcid_addr = GET_CID_ADDR(vcid); 2640 pcid_addr = vcid_addr; 2641 2642 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); 2643 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2644 2645 /* Zero out the context. */ 2646 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2647 CTX_WR(sc, 0x00, offset, 0); 2648 2649 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 2650 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2651 } 2652 } 2653 2654 /****************************************************************************/ 2655 /* Fetch the permanent MAC address of the controller. */ 2656 /* */ 2657 /* Returns: */ 2658 /* Nothing. */ 2659 /****************************************************************************/ 2660 void 2661 bnx_get_mac_addr(struct bnx_softc *sc) 2662 { 2663 u_int32_t mac_lo = 0, mac_hi = 0; 2664 2665 /* 2666 * The NetXtreme II bootcode populates various NIC 2667 * power-on and runtime configuration items in a 2668 * shared memory area. The factory configured MAC 2669 * address is available from both NVRAM and the 2670 * shared memory area so we'll read the value from 2671 * shared memory for speed. 2672 */ 2673 2674 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 2675 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 2676 2677 if ((mac_lo == 0) && (mac_hi == 0)) { 2678 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 2679 __FILE__, __LINE__); 2680 } else { 2681 sc->eaddr[0] = (u_char)(mac_hi >> 8); 2682 sc->eaddr[1] = (u_char)(mac_hi >> 0); 2683 sc->eaddr[2] = (u_char)(mac_lo >> 24); 2684 sc->eaddr[3] = (u_char)(mac_lo >> 16); 2685 sc->eaddr[4] = (u_char)(mac_lo >> 8); 2686 sc->eaddr[5] = (u_char)(mac_lo >> 0); 2687 } 2688 2689 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 2690 "%s\n", ether_sprintf(sc->eaddr)); 2691 } 2692 2693 /****************************************************************************/ 2694 /* Program the MAC address. */ 2695 /* */ 2696 /* Returns: */ 2697 /* Nothing. */ 2698 /****************************************************************************/ 2699 void 2700 bnx_set_mac_addr(struct bnx_softc *sc) 2701 { 2702 u_int32_t val; 2703 const u_int8_t *mac_addr = CLLADDR(sc->ethercom.ec_if.if_sadl); 2704 2705 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 2706 "%s\n", ether_sprintf(sc->eaddr)); 2707 2708 val = (mac_addr[0] << 8) | mac_addr[1]; 2709 2710 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 2711 2712 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2713 (mac_addr[4] << 8) | mac_addr[5]; 2714 2715 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 2716 } 2717 2718 /****************************************************************************/ 2719 /* Stop the controller. */ 2720 /* */ 2721 /* Returns: */ 2722 /* Nothing. */ 2723 /****************************************************************************/ 2724 void 2725 bnx_stop(struct bnx_softc *sc) 2726 { 2727 struct ifnet *ifp = &sc->ethercom.ec_if; 2728 struct mii_data *mii = NULL; 2729 2730 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2731 2732 mii = &sc->bnx_mii; 2733 2734 callout_stop(&sc->bnx_timeout); 2735 2736 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2737 2738 /* Disable the transmit/receive blocks. */ 2739 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 2740 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2741 DELAY(20); 2742 2743 bnx_disable_intr(sc); 2744 2745 /* Tell firmware that the driver is going away. */ 2746 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 2747 2748 /* Free the RX lists. */ 2749 bnx_free_rx_chain(sc); 2750 2751 /* Free TX buffers. */ 2752 bnx_free_tx_chain(sc); 2753 2754 ifp->if_timer = 0; 2755 2756 sc->bnx_link = 0; 2757 2758 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2759 2760 } 2761 2762 int 2763 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 2764 { 2765 u_int32_t val; 2766 int i, rc = 0; 2767 2768 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2769 2770 /* Wait for pending PCI transactions to complete. */ 2771 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 2772 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 2773 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 2774 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 2775 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 2776 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2777 DELAY(5); 2778 2779 /* Assume bootcode is running. */ 2780 sc->bnx_fw_timed_out = 0; 2781 2782 /* Give the firmware a chance to prepare for the reset. */ 2783 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 2784 if (rc) 2785 goto bnx_reset_exit; 2786 2787 /* Set a firmware reminder that this is a soft reset. */ 2788 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 2789 BNX_DRV_RESET_SIGNATURE_MAGIC); 2790 2791 /* Dummy read to force the chip to complete all current transactions. */ 2792 val = REG_RD(sc, BNX_MISC_ID); 2793 2794 /* Chip reset. */ 2795 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2796 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 2797 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 2798 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 2799 2800 /* Allow up to 30us for reset to complete. */ 2801 for (i = 0; i < 10; i++) { 2802 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 2803 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2804 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 2805 break; 2806 2807 DELAY(10); 2808 } 2809 2810 /* Check that reset completed successfully. */ 2811 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2812 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 2813 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__); 2814 rc = EBUSY; 2815 goto bnx_reset_exit; 2816 } 2817 2818 /* Make sure byte swapping is properly configured. */ 2819 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 2820 if (val != 0x01020304) { 2821 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 2822 __FILE__, __LINE__); 2823 rc = ENODEV; 2824 goto bnx_reset_exit; 2825 } 2826 2827 /* Just completed a reset, assume that firmware is running again. */ 2828 sc->bnx_fw_timed_out = 0; 2829 2830 /* Wait for the firmware to finish its initialization. */ 2831 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 2832 if (rc) 2833 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 2834 "initialization!\n", __FILE__, __LINE__); 2835 2836 bnx_reset_exit: 2837 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2838 2839 return (rc); 2840 } 2841 2842 int 2843 bnx_chipinit(struct bnx_softc *sc) 2844 { 2845 struct pci_attach_args *pa = &(sc->bnx_pa); 2846 u_int32_t val; 2847 int rc = 0; 2848 2849 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2850 2851 /* Make sure the interrupt is not active. */ 2852 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 2853 2854 /* Initialize DMA byte/word swapping, configure the number of DMA */ 2855 /* channels and PCI clock compensation delay. */ 2856 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 2857 BNX_DMA_CONFIG_DATA_WORD_SWAP | 2858 #if BYTE_ORDER == BIG_ENDIAN 2859 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 2860 #endif 2861 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 2862 DMA_READ_CHANS << 12 | 2863 DMA_WRITE_CHANS << 16; 2864 2865 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 2866 2867 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 2868 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 2869 2870 /* 2871 * This setting resolves a problem observed on certain Intel PCI 2872 * chipsets that cannot handle multiple outstanding DMA operations. 2873 * See errata E9_5706A1_65. 2874 */ 2875 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 2876 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 2877 !(sc->bnx_flags & BNX_PCIX_FLAG)) 2878 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 2879 2880 REG_WR(sc, BNX_DMA_CONFIG, val); 2881 2882 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 2883 if (sc->bnx_flags & BNX_PCIX_FLAG) { 2884 u_int16_t nval; 2885 2886 nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 2887 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 2888 nval & ~0x2); 2889 } 2890 2891 /* Enable the RX_V2P and Context state machines before access. */ 2892 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 2893 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 2894 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 2895 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 2896 2897 /* Initialize context mapping and zero out the quick contexts. */ 2898 bnx_init_context(sc); 2899 2900 /* Initialize the on-boards CPUs */ 2901 bnx_init_cpus(sc); 2902 2903 /* Prepare NVRAM for access. */ 2904 if (bnx_init_nvram(sc)) { 2905 rc = ENODEV; 2906 goto bnx_chipinit_exit; 2907 } 2908 2909 /* Set the kernel bypass block size */ 2910 val = REG_RD(sc, BNX_MQ_CONFIG); 2911 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 2912 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 2913 REG_WR(sc, BNX_MQ_CONFIG, val); 2914 2915 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 2916 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 2917 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 2918 2919 val = (BCM_PAGE_BITS - 8) << 24; 2920 REG_WR(sc, BNX_RV2P_CONFIG, val); 2921 2922 /* Configure page size. */ 2923 val = REG_RD(sc, BNX_TBDR_CONFIG); 2924 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 2925 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 2926 REG_WR(sc, BNX_TBDR_CONFIG, val); 2927 2928 bnx_chipinit_exit: 2929 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2930 2931 return(rc); 2932 } 2933 2934 /****************************************************************************/ 2935 /* Initialize the controller in preparation to send/receive traffic. */ 2936 /* */ 2937 /* Returns: */ 2938 /* 0 for success, positive value for failure. */ 2939 /****************************************************************************/ 2940 int 2941 bnx_blockinit(struct bnx_softc *sc) 2942 { 2943 u_int32_t reg, val; 2944 int rc = 0; 2945 2946 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2947 2948 /* Load the hardware default MAC address. */ 2949 bnx_set_mac_addr(sc); 2950 2951 /* Set the Ethernet backoff seed value */ 2952 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 2953 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 2954 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 2955 2956 sc->last_status_idx = 0; 2957 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 2958 2959 /* Set up link change interrupt generation. */ 2960 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 2961 2962 /* Program the physical address of the status block. */ 2963 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 2964 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 2965 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 2966 2967 /* Program the physical address of the statistics block. */ 2968 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 2969 (u_int32_t)(sc->stats_block_paddr)); 2970 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 2971 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 2972 2973 /* Program various host coalescing parameters. */ 2974 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 2975 << 16) | sc->bnx_tx_quick_cons_trip); 2976 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 2977 << 16) | sc->bnx_rx_quick_cons_trip); 2978 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 2979 sc->bnx_comp_prod_trip); 2980 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 2981 sc->bnx_tx_ticks); 2982 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 2983 sc->bnx_rx_ticks); 2984 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 2985 sc->bnx_com_ticks); 2986 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 2987 sc->bnx_cmd_ticks); 2988 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 2989 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 2990 REG_WR(sc, BNX_HC_CONFIG, 2991 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 2992 BNX_HC_CONFIG_COLLECT_STATS)); 2993 2994 /* Clear the internal statistics counters. */ 2995 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 2996 2997 /* Verify that bootcode is running. */ 2998 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 2999 3000 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3001 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3002 __FILE__, __LINE__); reg = 0); 3003 3004 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3005 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3006 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3007 "Expected: 08%08X\n", __FILE__, __LINE__, 3008 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3009 BNX_DEV_INFO_SIGNATURE_MAGIC); 3010 rc = ENODEV; 3011 goto bnx_blockinit_exit; 3012 } 3013 3014 /* Check if any management firmware is running. */ 3015 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3016 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3017 BNX_PORT_FEATURE_IMD_ENABLED)) { 3018 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3019 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3020 } 3021 3022 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3023 BNX_DEV_INFO_BC_REV); 3024 3025 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3026 3027 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3028 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3029 3030 /* Enable link state change interrupt generation. */ 3031 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3032 3033 /* Enable all remaining blocks in the MAC. */ 3034 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3035 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3036 DELAY(20); 3037 3038 bnx_blockinit_exit: 3039 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3040 3041 return (rc); 3042 } 3043 3044 /****************************************************************************/ 3045 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3046 /* */ 3047 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3048 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3049 /* necessary. */ 3050 /* */ 3051 /* Returns: */ 3052 /* 0 for success, positive value for failure. */ 3053 /****************************************************************************/ 3054 int 3055 bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod, 3056 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3057 { 3058 bus_dmamap_t map; 3059 struct mbuf *m_new = NULL; 3060 struct rx_bd *rxbd; 3061 int i, rc = 0; 3062 u_int32_t addr; 3063 #ifdef BNX_DEBUG 3064 u_int16_t debug_chain_prod = *chain_prod; 3065 #endif 3066 u_int16_t first_chain_prod; 3067 u_int16_t min_free_bd; 3068 3069 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3070 __FUNCTION__); 3071 3072 /* Make sure the inputs are valid. */ 3073 DBRUNIF((*chain_prod > MAX_RX_BD), 3074 aprint_error("%s: RX producer out of range: 0x%04X > 0x%04X\n", 3075 sc->bnx_dev.dv_xname, *chain_prod, (u_int16_t) MAX_RX_BD)); 3076 3077 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3078 "0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, 3079 *prod_bseq); 3080 3081 /* try to get in as many mbufs as possible */ 3082 if (sc->mbuf_alloc_size == MCLBYTES) 3083 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3084 else 3085 min_free_bd = (BNX_MAX_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3086 while (sc->free_rx_bd >= min_free_bd) { 3087 if (m == NULL) { 3088 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3089 BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n"); 3090 3091 sc->mbuf_alloc_failed++; 3092 rc = ENOBUFS; 3093 goto bnx_get_buf_exit); 3094 3095 /* This is a new mbuf allocation. */ 3096 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3097 if (m_new == NULL) { 3098 DBPRINT(sc, BNX_WARN, 3099 "%s(%d): RX mbuf header allocation failed!\n", 3100 __FILE__, __LINE__); 3101 3102 DBRUNIF(1, sc->mbuf_alloc_failed++); 3103 3104 rc = ENOBUFS; 3105 goto bnx_get_buf_exit; 3106 } 3107 3108 DBRUNIF(1, sc->rx_mbuf_alloc++); 3109 if (sc->mbuf_alloc_size == MCLBYTES) 3110 MCLGET(m_new, M_DONTWAIT); 3111 else 3112 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3113 M_DONTWAIT); 3114 if (!(m_new->m_flags & M_EXT)) { 3115 DBPRINT(sc, BNX_WARN, 3116 "%s(%d): RX mbuf chain allocation failed!\n", 3117 __FILE__, __LINE__); 3118 3119 m_freem(m_new); 3120 3121 DBRUNIF(1, sc->rx_mbuf_alloc--); 3122 DBRUNIF(1, sc->mbuf_alloc_failed++); 3123 3124 rc = ENOBUFS; 3125 goto bnx_get_buf_exit; 3126 } 3127 3128 } else { 3129 m_new = m; 3130 m = NULL; 3131 m_new->m_data = m_new->m_ext.ext_buf; 3132 } 3133 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3134 3135 /* Map the mbuf cluster into device memory. */ 3136 map = sc->rx_mbuf_map[*chain_prod]; 3137 first_chain_prod = *chain_prod; 3138 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3139 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3140 __FILE__, __LINE__); 3141 3142 m_freem(m_new); 3143 3144 DBRUNIF(1, sc->rx_mbuf_alloc--); 3145 3146 rc = ENOBUFS; 3147 goto bnx_get_buf_exit; 3148 } 3149 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3150 BUS_DMASYNC_PREREAD); 3151 3152 /* Watch for overflow. */ 3153 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3154 aprint_error("%s: Too many free rx_bd (0x%04X > 0x%04X)!\n", 3155 sc->bnx_dev.dv_xname, 3156 sc->free_rx_bd, (u_int16_t) USABLE_RX_BD)); 3157 3158 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3159 sc->rx_low_watermark = sc->free_rx_bd); 3160 3161 /* 3162 * Setup the rx_bd for the first segment 3163 */ 3164 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3165 3166 addr = (u_int32_t)(map->dm_segs[0].ds_addr); 3167 rxbd->rx_bd_haddr_lo = htole32(addr); 3168 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3169 rxbd->rx_bd_haddr_hi = htole32(addr); 3170 rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); 3171 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3172 *prod_bseq += map->dm_segs[0].ds_len; 3173 bus_dmamap_sync(sc->bnx_dmatag, 3174 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3175 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3176 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3177 3178 for (i = 1; i < map->dm_nsegs; i++) { 3179 *prod = NEXT_RX_BD(*prod); 3180 *chain_prod = RX_CHAIN_IDX(*prod); 3181 3182 rxbd = 3183 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3184 3185 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 3186 rxbd->rx_bd_haddr_lo = htole32(addr); 3187 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3188 rxbd->rx_bd_haddr_hi = htole32(addr); 3189 rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); 3190 rxbd->rx_bd_flags = 0; 3191 *prod_bseq += map->dm_segs[i].ds_len; 3192 bus_dmamap_sync(sc->bnx_dmatag, 3193 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3194 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3195 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3196 } 3197 3198 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3199 bus_dmamap_sync(sc->bnx_dmatag, 3200 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3201 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3202 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3203 3204 /* 3205 * Save the mbuf, ajust the map pointer (swap map for first and 3206 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3207 * and update counter. 3208 */ 3209 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3210 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3211 sc->rx_mbuf_map[*chain_prod] = map; 3212 sc->free_rx_bd -= map->dm_nsegs; 3213 3214 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3215 map->dm_nsegs)); 3216 *prod = NEXT_RX_BD(*prod); 3217 *chain_prod = RX_CHAIN_IDX(*prod); 3218 } 3219 3220 bnx_get_buf_exit: 3221 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3222 "= 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, 3223 *chain_prod, *prod_bseq); 3224 3225 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3226 __FUNCTION__); 3227 3228 return(rc); 3229 } 3230 3231 /****************************************************************************/ 3232 /* Allocate memory and initialize the TX data structures. */ 3233 /* */ 3234 /* Returns: */ 3235 /* 0 for success, positive value for failure. */ 3236 /****************************************************************************/ 3237 int 3238 bnx_init_tx_chain(struct bnx_softc *sc) 3239 { 3240 struct tx_bd *txbd; 3241 u_int32_t val, addr; 3242 int i, rc = 0; 3243 3244 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3245 3246 /* Set the initial TX producer/consumer indices. */ 3247 sc->tx_prod = 0; 3248 sc->tx_cons = 0; 3249 sc->tx_prod_bseq = 0; 3250 sc->used_tx_bd = 0; 3251 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3252 3253 /* 3254 * The NetXtreme II supports a linked-list structure called 3255 * a Buffer Descriptor Chain (or BD chain). A BD chain 3256 * consists of a series of 1 or more chain pages, each of which 3257 * consists of a fixed number of BD entries. 3258 * The last BD entry on each page is a pointer to the next page 3259 * in the chain, and the last pointer in the BD chain 3260 * points back to the beginning of the chain. 3261 */ 3262 3263 /* Set the TX next pointer chain entries. */ 3264 for (i = 0; i < TX_PAGES; i++) { 3265 int j; 3266 3267 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3268 3269 /* Check if we've reached the last page. */ 3270 if (i == (TX_PAGES - 1)) 3271 j = 0; 3272 else 3273 j = i + 1; 3274 3275 addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); 3276 txbd->tx_bd_haddr_lo = htole32(addr); 3277 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3278 txbd->tx_bd_haddr_hi = htole32(addr); 3279 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3280 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3281 } 3282 3283 /* 3284 * Initialize the context ID for an L2 TX chain. 3285 */ 3286 val = BNX_L2CTX_TYPE_TYPE_L2; 3287 val |= BNX_L2CTX_TYPE_SIZE_L2; 3288 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3289 3290 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3291 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3292 3293 /* Point the hardware to the first page in the chain. */ 3294 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3295 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3296 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3297 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3298 3299 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3300 3301 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3302 3303 return(rc); 3304 } 3305 3306 /****************************************************************************/ 3307 /* Free memory and clear the TX data structures. */ 3308 /* */ 3309 /* Returns: */ 3310 /* Nothing. */ 3311 /****************************************************************************/ 3312 void 3313 bnx_free_tx_chain(struct bnx_softc *sc) 3314 { 3315 int i; 3316 3317 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3318 3319 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3320 for (i = 0; i < TOTAL_TX_BD; i++) { 3321 if (sc->tx_mbuf_ptr[i] != NULL) { 3322 if (sc->tx_mbuf_map != NULL) 3323 bus_dmamap_sync(sc->bnx_dmatag, 3324 sc->tx_mbuf_map[i], 0, 3325 sc->tx_mbuf_map[i]->dm_mapsize, 3326 BUS_DMASYNC_POSTWRITE); 3327 m_freem(sc->tx_mbuf_ptr[i]); 3328 sc->tx_mbuf_ptr[i] = NULL; 3329 DBRUNIF(1, sc->tx_mbuf_alloc--); 3330 } 3331 } 3332 3333 /* Clear each TX chain page. */ 3334 for (i = 0; i < TX_PAGES; i++) { 3335 bzero((char *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 3336 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3337 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3338 } 3339 3340 /* Check if we lost any mbufs in the process. */ 3341 DBRUNIF((sc->tx_mbuf_alloc), 3342 aprint_error("%s: Memory leak! Lost %d mbufs from tx chain!\n", 3343 sc->bnx_dev.dv_xname, sc->tx_mbuf_alloc)); 3344 3345 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3346 } 3347 3348 /****************************************************************************/ 3349 /* Allocate memory and initialize the RX data structures. */ 3350 /* */ 3351 /* Returns: */ 3352 /* 0 for success, positive value for failure. */ 3353 /****************************************************************************/ 3354 int 3355 bnx_init_rx_chain(struct bnx_softc *sc) 3356 { 3357 struct rx_bd *rxbd; 3358 int i, rc = 0; 3359 u_int16_t prod, chain_prod; 3360 u_int32_t prod_bseq, val, addr; 3361 3362 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3363 3364 /* Initialize the RX producer and consumer indices. */ 3365 sc->rx_prod = 0; 3366 sc->rx_cons = 0; 3367 sc->rx_prod_bseq = 0; 3368 sc->free_rx_bd = BNX_RX_SLACK_SPACE; 3369 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3370 3371 /* Initialize the RX next pointer chain entries. */ 3372 for (i = 0; i < RX_PAGES; i++) { 3373 int j; 3374 3375 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3376 3377 /* Check if we've reached the last page. */ 3378 if (i == (RX_PAGES - 1)) 3379 j = 0; 3380 else 3381 j = i + 1; 3382 3383 /* Setup the chain page pointers. */ 3384 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 3385 rxbd->rx_bd_haddr_hi = htole32(addr); 3386 addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); 3387 rxbd->rx_bd_haddr_lo = htole32(addr); 3388 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 3389 0, BNX_RX_CHAIN_PAGE_SZ, 3390 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3391 } 3392 3393 /* Initialize the context ID for an L2 RX chain. */ 3394 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3395 val |= BNX_L2CTX_CTX_TYPE_SIZE_L2; 3396 val |= 0x02 << 8; 3397 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 3398 3399 /* Point the hardware to the first page in the chain. */ 3400 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 3401 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 3402 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 3403 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 3404 3405 /* Allocate mbuf clusters for the rx_bd chain. */ 3406 prod = prod_bseq = 0; 3407 chain_prod = RX_CHAIN_IDX(prod); 3408 if (bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3409 BNX_PRINTF(sc, 3410 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 3411 } 3412 3413 /* Save the RX chain producer index. */ 3414 sc->rx_prod = prod; 3415 sc->rx_prod_bseq = prod_bseq; 3416 3417 for (i = 0; i < RX_PAGES; i++) 3418 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 3419 sc->rx_bd_chain_map[i]->dm_mapsize, 3420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3421 3422 /* Tell the chip about the waiting rx_bd's. */ 3423 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3424 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3425 3426 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3427 3428 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3429 3430 return(rc); 3431 } 3432 3433 /****************************************************************************/ 3434 /* Free memory and clear the RX data structures. */ 3435 /* */ 3436 /* Returns: */ 3437 /* Nothing. */ 3438 /****************************************************************************/ 3439 void 3440 bnx_free_rx_chain(struct bnx_softc *sc) 3441 { 3442 int i; 3443 3444 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3445 3446 /* Free any mbufs still in the RX mbuf chain. */ 3447 for (i = 0; i < TOTAL_RX_BD; i++) { 3448 if (sc->rx_mbuf_ptr[i] != NULL) { 3449 if (sc->rx_mbuf_map[i] != NULL) 3450 bus_dmamap_sync(sc->bnx_dmatag, 3451 sc->rx_mbuf_map[i], 0, 3452 sc->rx_mbuf_map[i]->dm_mapsize, 3453 BUS_DMASYNC_POSTREAD); 3454 m_freem(sc->rx_mbuf_ptr[i]); 3455 sc->rx_mbuf_ptr[i] = NULL; 3456 DBRUNIF(1, sc->rx_mbuf_alloc--); 3457 } 3458 } 3459 3460 /* Clear each RX chain page. */ 3461 for (i = 0; i < RX_PAGES; i++) 3462 bzero((char *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 3463 3464 /* Check if we lost any mbufs in the process. */ 3465 DBRUNIF((sc->rx_mbuf_alloc), 3466 aprint_error("%s: Memory leak! Lost %d mbufs from rx chain!\n", 3467 sc->bnx_dev.dv_xname, sc->rx_mbuf_alloc)); 3468 3469 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3470 } 3471 3472 /****************************************************************************/ 3473 /* Set media options. */ 3474 /* */ 3475 /* Returns: */ 3476 /* 0 for success, positive value for failure. */ 3477 /****************************************************************************/ 3478 int 3479 bnx_ifmedia_upd(struct ifnet *ifp) 3480 { 3481 struct bnx_softc *sc; 3482 struct mii_data *mii; 3483 struct ifmedia *ifm; 3484 int rc = 0; 3485 3486 sc = ifp->if_softc; 3487 ifm = &sc->bnx_ifmedia; 3488 3489 /* DRC - ToDo: Add SerDes support. */ 3490 3491 mii = &sc->bnx_mii; 3492 sc->bnx_link = 0; 3493 if (mii->mii_instance) { 3494 struct mii_softc *miisc; 3495 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3496 mii_phy_reset(miisc); 3497 } 3498 mii_mediachg(mii); 3499 3500 return(rc); 3501 } 3502 3503 /****************************************************************************/ 3504 /* Reports current media status. */ 3505 /* */ 3506 /* Returns: */ 3507 /* Nothing. */ 3508 /****************************************************************************/ 3509 void 3510 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3511 { 3512 struct bnx_softc *sc; 3513 struct mii_data *mii; 3514 int s; 3515 3516 sc = ifp->if_softc; 3517 3518 s = splnet(); 3519 3520 mii = &sc->bnx_mii; 3521 3522 /* DRC - ToDo: Add SerDes support. */ 3523 3524 mii_pollstat(mii); 3525 ifmr->ifm_active = mii->mii_media_active; 3526 ifmr->ifm_status = mii->mii_media_status; 3527 3528 splx(s); 3529 } 3530 3531 /****************************************************************************/ 3532 /* Handles PHY generated interrupt events. */ 3533 /* */ 3534 /* Returns: */ 3535 /* Nothing. */ 3536 /****************************************************************************/ 3537 void 3538 bnx_phy_intr(struct bnx_softc *sc) 3539 { 3540 u_int32_t new_link_state, old_link_state; 3541 3542 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3543 BUS_DMASYNC_POSTREAD); 3544 new_link_state = sc->status_block->status_attn_bits & 3545 STATUS_ATTN_BITS_LINK_STATE; 3546 old_link_state = sc->status_block->status_attn_bits_ack & 3547 STATUS_ATTN_BITS_LINK_STATE; 3548 3549 /* Handle any changes if the link state has changed. */ 3550 if (new_link_state != old_link_state) { 3551 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 3552 3553 sc->bnx_link = 0; 3554 callout_stop(&sc->bnx_timeout); 3555 bnx_tick(sc); 3556 3557 /* Update the status_attn_bits_ack field in the status block. */ 3558 if (new_link_state) { 3559 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 3560 STATUS_ATTN_BITS_LINK_STATE); 3561 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 3562 } else { 3563 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 3564 STATUS_ATTN_BITS_LINK_STATE); 3565 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 3566 } 3567 } 3568 3569 /* Acknowledge the link change interrupt. */ 3570 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 3571 } 3572 3573 /****************************************************************************/ 3574 /* Handles received frame interrupt events. */ 3575 /* */ 3576 /* Returns: */ 3577 /* Nothing. */ 3578 /****************************************************************************/ 3579 void 3580 bnx_rx_intr(struct bnx_softc *sc) 3581 { 3582 struct status_block *sblk = sc->status_block; 3583 struct ifnet *ifp = &sc->ethercom.ec_if; 3584 u_int16_t hw_cons, sw_cons, sw_chain_cons; 3585 u_int16_t sw_prod, sw_chain_prod; 3586 u_int32_t sw_prod_bseq; 3587 struct l2_fhdr *l2fhdr; 3588 int i; 3589 3590 DBRUNIF(1, sc->rx_interrupts++); 3591 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3592 BUS_DMASYNC_POSTREAD); 3593 3594 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3595 for (i = 0; i < RX_PAGES; i++) 3596 bus_dmamap_sync(sc->bnx_dmatag, 3597 sc->rx_bd_chain_map[i], 0, 3598 sc->rx_bd_chain_map[i]->dm_mapsize, 3599 BUS_DMASYNC_POSTWRITE); 3600 3601 /* Get the hardware's view of the RX consumer index. */ 3602 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3603 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3604 hw_cons++; 3605 3606 /* Get working copies of the driver's view of the RX indices. */ 3607 sw_cons = sc->rx_cons; 3608 sw_prod = sc->rx_prod; 3609 sw_prod_bseq = sc->rx_prod_bseq; 3610 3611 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3612 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3613 __FUNCTION__, sw_prod, sw_cons, sw_prod_bseq); 3614 3615 /* Prevent speculative reads from getting ahead of the status block. */ 3616 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3617 BUS_SPACE_BARRIER_READ); 3618 3619 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3620 sc->rx_low_watermark = sc->free_rx_bd); 3621 3622 /* 3623 * Scan through the receive chain as long 3624 * as there is work to do. 3625 */ 3626 while (sw_cons != hw_cons) { 3627 struct mbuf *m; 3628 struct rx_bd *rxbd; 3629 unsigned int len; 3630 u_int32_t status; 3631 3632 /* Convert the producer/consumer indices to an actual 3633 * rx_bd index. 3634 */ 3635 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3636 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3637 3638 /* Get the used rx_bd. */ 3639 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3640 sc->free_rx_bd++; 3641 3642 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __FUNCTION__); 3643 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 3644 3645 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3646 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3647 #ifdef DIAGNOSTIC 3648 /* Validate that this is the last rx_bd. */ 3649 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 3650 printf("%s: Unexpected mbuf found in " 3651 "rx_bd[0x%04X]!\n", sc->bnx_dev.dv_xname, 3652 sw_chain_cons); 3653 } 3654 #endif 3655 3656 /* DRC - ToDo: If the received packet is small, say less 3657 * than 128 bytes, allocate a new mbuf here, 3658 * copy the data to that mbuf, and recycle 3659 * the mapped jumbo frame. 3660 */ 3661 3662 /* Unmap the mbuf from DMA space. */ 3663 #ifdef DIAGNOSTIC 3664 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 3665 printf("invalid map sw_cons 0x%x " 3666 "sw_prod 0x%x " 3667 "sw_chain_cons 0x%x " 3668 "sw_chain_prod 0x%x " 3669 "hw_cons 0x%x " 3670 "TOTAL_RX_BD_PER_PAGE 0x%x " 3671 "TOTAL_RX_BD 0x%x\n", 3672 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 3673 hw_cons, 3674 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 3675 } 3676 #endif 3677 bus_dmamap_sync(sc->bnx_dmatag, 3678 sc->rx_mbuf_map[sw_chain_cons], 0, 3679 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 3680 BUS_DMASYNC_POSTREAD); 3681 bus_dmamap_unload(sc->bnx_dmatag, 3682 sc->rx_mbuf_map[sw_chain_cons]); 3683 3684 /* Remove the mbuf from the driver's chain. */ 3685 m = sc->rx_mbuf_ptr[sw_chain_cons]; 3686 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 3687 3688 /* 3689 * Frames received on the NetXteme II are prepended 3690 * with the l2_fhdr structure which provides status 3691 * information about the received frame (including 3692 * VLAN tags and checksum info) and are also 3693 * automatically adjusted to align the IP header 3694 * (i.e. two null bytes are inserted before the 3695 * Ethernet header). 3696 */ 3697 l2fhdr = mtod(m, struct l2_fhdr *); 3698 3699 len = l2fhdr->l2_fhdr_pkt_len; 3700 status = l2fhdr->l2_fhdr_status; 3701 3702 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 3703 aprint_error("Simulating l2_fhdr status error.\n"); 3704 status = status | L2_FHDR_ERRORS_PHY_DECODE); 3705 3706 /* Watch for unusual sized frames. */ 3707 DBRUNIF(((len < BNX_MIN_MTU) || 3708 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 3709 aprint_error("%s: Unusual frame size found. " 3710 "Min(%d), Actual(%d), Max(%d)\n", 3711 sc->bnx_dev.dv_xname, (int)BNX_MIN_MTU, len, 3712 (int) BNX_MAX_JUMBO_ETHER_MTU_VLAN); 3713 3714 bnx_dump_mbuf(sc, m); 3715 bnx_breakpoint(sc)); 3716 3717 len -= ETHER_CRC_LEN; 3718 3719 /* Check the received frame for errors. */ 3720 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 3721 L2_FHDR_ERRORS_PHY_DECODE | 3722 L2_FHDR_ERRORS_ALIGNMENT | 3723 L2_FHDR_ERRORS_TOO_SHORT | 3724 L2_FHDR_ERRORS_GIANT_FRAME)) || 3725 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 3726 len > 3727 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 3728 ifp->if_ierrors++; 3729 DBRUNIF(1, sc->l2fhdr_status_errors++); 3730 3731 /* Reuse the mbuf for a new frame. */ 3732 if (bnx_get_buf(sc, m, &sw_prod, 3733 &sw_chain_prod, &sw_prod_bseq)) { 3734 DBRUNIF(1, bnx_breakpoint(sc)); 3735 panic("%s: Can't reuse RX mbuf!\n", 3736 sc->bnx_dev.dv_xname); 3737 } 3738 continue; 3739 } 3740 3741 /* 3742 * Get a new mbuf for the rx_bd. If no new 3743 * mbufs are available then reuse the current mbuf, 3744 * log an ierror on the interface, and generate 3745 * an error in the system log. 3746 */ 3747 if (bnx_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, 3748 &sw_prod_bseq)) { 3749 DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate " 3750 "new mbuf, incoming frame dropped!\n")); 3751 3752 ifp->if_ierrors++; 3753 3754 /* Try and reuse the exisitng mbuf. */ 3755 if (bnx_get_buf(sc, m, &sw_prod, 3756 &sw_chain_prod, &sw_prod_bseq)) { 3757 DBRUNIF(1, bnx_breakpoint(sc)); 3758 panic("%s: Double mbuf allocation " 3759 "failure!", sc->bnx_dev.dv_xname); 3760 } 3761 continue; 3762 } 3763 3764 /* Skip over the l2_fhdr when passing the data up 3765 * the stack. 3766 */ 3767 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 3768 3769 /* Adjust the pckt length to match the received data. */ 3770 m->m_pkthdr.len = m->m_len = len; 3771 3772 /* Send the packet to the appropriate interface. */ 3773 m->m_pkthdr.rcvif = ifp; 3774 3775 DBRUN(BNX_VERBOSE_RECV, 3776 struct ether_header *eh; 3777 eh = mtod(m, struct ether_header *); 3778 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 3779 __FUNCTION__, ether_sprintf(eh->ether_dhost), 3780 ether_sprintf(eh->ether_shost), 3781 htons(eh->ether_type))); 3782 3783 /* Validate the checksum. */ 3784 3785 /* Check for an IP datagram. */ 3786 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 3787 /* Check if the IP checksum is valid. */ 3788 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 3789 == 0) 3790 m->m_pkthdr.csum_flags |= 3791 M_CSUM_IPv4; 3792 #ifdef BNX_DEBUG 3793 else 3794 DBPRINT(sc, BNX_WARN_SEND, 3795 "%s(): Invalid IP checksum " 3796 "= 0x%04X!\n", 3797 __FUNCTION__, 3798 l2fhdr->l2_fhdr_ip_xsum 3799 ); 3800 #endif 3801 } 3802 3803 /* Check for a valid TCP/UDP frame. */ 3804 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3805 L2_FHDR_STATUS_UDP_DATAGRAM)) { 3806 /* Check for a good TCP/UDP checksum. */ 3807 if ((status & 3808 (L2_FHDR_ERRORS_TCP_XSUM | 3809 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 3810 m->m_pkthdr.csum_flags |= 3811 M_CSUM_TCPv4 | 3812 M_CSUM_UDPv4; 3813 } else { 3814 DBPRINT(sc, BNX_WARN_SEND, 3815 "%s(): Invalid TCP/UDP " 3816 "checksum = 0x%04X!\n", 3817 __FUNCTION__, 3818 l2fhdr->l2_fhdr_tcp_udp_xsum); 3819 } 3820 } 3821 3822 /* 3823 * If we received a packet with a vlan tag, 3824 * attach that information to the packet. 3825 */ 3826 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 3827 #if 0 3828 struct ether_vlan_header vh; 3829 3830 DBPRINT(sc, BNX_VERBOSE_SEND, 3831 "%s(): VLAN tag = 0x%04X\n", 3832 __FUNCTION__, 3833 l2fhdr->l2_fhdr_vlan_tag); 3834 3835 if (m->m_pkthdr.len < ETHER_HDR_LEN) { 3836 m_freem(m); 3837 continue; 3838 } 3839 m_copydata(m, 0, ETHER_HDR_LEN, (void *)&vh); 3840 vh.evl_proto = vh.evl_encap_proto; 3841 vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag; 3842 vh.evl_encap_proto = htons(ETHERTYPE_VLAN); 3843 m_adj(m, ETHER_HDR_LEN); 3844 if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL) 3845 continue; 3846 m->m_pkthdr.len += sizeof(vh); 3847 if (m->m_len < sizeof(vh) && 3848 (m = m_pullup(m, sizeof(vh))) == NULL) 3849 goto bnx_rx_int_next_rx; 3850 m_copyback(m, 0, sizeof(vh), &vh); 3851 #else 3852 VLAN_INPUT_TAG(ifp, m, 3853 l2fhdr->l2_fhdr_vlan_tag, 3854 continue); 3855 #endif 3856 } 3857 3858 #if NBPFILTER > 0 3859 /* 3860 * Handle BPF listeners. Let the BPF 3861 * user see the packet. 3862 */ 3863 if (ifp->if_bpf) 3864 bpf_mtap(ifp->if_bpf, m); 3865 #endif 3866 3867 /* Pass the mbuf off to the upper layers. */ 3868 ifp->if_ipackets++; 3869 DBPRINT(sc, BNX_VERBOSE_RECV, 3870 "%s(): Passing received frame up.\n", __FUNCTION__); 3871 (*ifp->if_input)(ifp, m); 3872 DBRUNIF(1, sc->rx_mbuf_alloc--); 3873 3874 } 3875 3876 sw_cons = NEXT_RX_BD(sw_cons); 3877 3878 /* Refresh hw_cons to see if there's new work */ 3879 if (sw_cons == hw_cons) { 3880 hw_cons = sc->hw_rx_cons = 3881 sblk->status_rx_quick_consumer_index0; 3882 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 3883 USABLE_RX_BD_PER_PAGE) 3884 hw_cons++; 3885 } 3886 3887 /* Prevent speculative reads from getting ahead of 3888 * the status block. 3889 */ 3890 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3891 BUS_SPACE_BARRIER_READ); 3892 } 3893 3894 for (i = 0; i < RX_PAGES; i++) 3895 bus_dmamap_sync(sc->bnx_dmatag, 3896 sc->rx_bd_chain_map[i], 0, 3897 sc->rx_bd_chain_map[i]->dm_mapsize, 3898 BUS_DMASYNC_PREWRITE); 3899 3900 sc->rx_cons = sw_cons; 3901 sc->rx_prod = sw_prod; 3902 sc->rx_prod_bseq = sw_prod_bseq; 3903 3904 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3905 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3906 3907 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 3908 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 3909 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 3910 } 3911 3912 /****************************************************************************/ 3913 /* Handles transmit completion interrupt events. */ 3914 /* */ 3915 /* Returns: */ 3916 /* Nothing. */ 3917 /****************************************************************************/ 3918 void 3919 bnx_tx_intr(struct bnx_softc *sc) 3920 { 3921 struct status_block *sblk = sc->status_block; 3922 struct ifnet *ifp = &sc->ethercom.ec_if; 3923 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 3924 3925 DBRUNIF(1, sc->tx_interrupts++); 3926 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3927 BUS_DMASYNC_POSTREAD); 3928 3929 /* Get the hardware's view of the TX consumer index. */ 3930 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 3931 3932 /* Skip to the next entry if this is a chain page pointer. */ 3933 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 3934 hw_tx_cons++; 3935 3936 sw_tx_cons = sc->tx_cons; 3937 3938 /* Prevent speculative reads from getting ahead of the status block. */ 3939 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3940 BUS_SPACE_BARRIER_READ); 3941 3942 /* Cycle through any completed TX chain page entries. */ 3943 while (sw_tx_cons != hw_tx_cons) { 3944 #ifdef BNX_DEBUG 3945 struct tx_bd *txbd = NULL; 3946 #endif 3947 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 3948 3949 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 3950 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 3951 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 3952 3953 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 3954 aprint_error("%s: TX chain consumer out of range! " 3955 " 0x%04X > 0x%04X\n", sc->bnx_dev.dv_xname, 3956 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 3957 3958 DBRUNIF(1, txbd = &sc->tx_bd_chain 3959 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 3960 3961 DBRUNIF((txbd == NULL), 3962 aprint_error("%s: Unexpected NULL tx_bd[0x%04X]!\n", 3963 sc->bnx_dev.dv_xname, sw_tx_chain_cons); 3964 bnx_breakpoint(sc)); 3965 3966 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __FUNCTION__); 3967 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 3968 3969 /* 3970 * Free the associated mbuf. Remember 3971 * that only the last tx_bd of a packet 3972 * has an mbuf pointer and DMA map. 3973 */ 3974 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 3975 /* Validate that this is the last tx_bd. */ 3976 DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & 3977 TX_BD_FLAGS_END)), 3978 aprint_error("%s: tx_bd END flag not set but " 3979 "txmbuf == NULL!\n", sc->bnx_dev.dv_xname); 3980 bnx_breakpoint(sc)); 3981 3982 DBRUN(BNX_INFO_SEND, 3983 aprint_debug("%s: Unloading map/freeing mbuf " 3984 "from tx_bd[0x%04X]\n", 3985 __FUNCTION__, sw_tx_chain_cons)); 3986 3987 /* Unmap the mbuf. */ 3988 bus_dmamap_unload(sc->bnx_dmatag, 3989 sc->tx_mbuf_map[sw_tx_chain_cons]); 3990 3991 /* Free the mbuf. */ 3992 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 3993 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 3994 DBRUNIF(1, sc->tx_mbuf_alloc--); 3995 3996 ifp->if_opackets++; 3997 } 3998 3999 sc->used_tx_bd--; 4000 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4001 4002 /* Refresh hw_cons to see if there's new work. */ 4003 hw_tx_cons = sc->hw_tx_cons = 4004 sblk->status_tx_quick_consumer_index0; 4005 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4006 USABLE_TX_BD_PER_PAGE) 4007 hw_tx_cons++; 4008 4009 /* Prevent speculative reads from getting ahead of 4010 * the status block. 4011 */ 4012 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4013 BUS_SPACE_BARRIER_READ); 4014 } 4015 4016 /* Clear the TX timeout timer. */ 4017 ifp->if_timer = 0; 4018 4019 /* Clear the tx hardware queue full flag. */ 4020 if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) { 4021 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4022 aprint_debug("%s: TX chain is open for business! Used " 4023 "tx_bd = %d\n", sc->bnx_dev.dv_xname, 4024 sc->used_tx_bd)); 4025 ifp->if_flags &= ~IFF_OACTIVE; 4026 } 4027 4028 sc->tx_cons = sw_tx_cons; 4029 } 4030 4031 /****************************************************************************/ 4032 /* Disables interrupt generation. */ 4033 /* */ 4034 /* Returns: */ 4035 /* Nothing. */ 4036 /****************************************************************************/ 4037 void 4038 bnx_disable_intr(struct bnx_softc *sc) 4039 { 4040 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4041 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4042 } 4043 4044 /****************************************************************************/ 4045 /* Enables interrupt generation. */ 4046 /* */ 4047 /* Returns: */ 4048 /* Nothing. */ 4049 /****************************************************************************/ 4050 void 4051 bnx_enable_intr(struct bnx_softc *sc) 4052 { 4053 u_int32_t val; 4054 4055 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4056 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4057 4058 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4059 sc->last_status_idx); 4060 4061 val = REG_RD(sc, BNX_HC_COMMAND); 4062 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4063 } 4064 4065 /****************************************************************************/ 4066 /* Handles controller initialization. */ 4067 /* */ 4068 /****************************************************************************/ 4069 int 4070 bnx_init(struct ifnet *ifp) 4071 { 4072 struct bnx_softc *sc = ifp->if_softc; 4073 u_int32_t ether_mtu; 4074 int s, error = 0; 4075 4076 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4077 4078 s = splnet(); 4079 4080 bnx_stop(sc); 4081 4082 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4083 aprint_error("bnx: Controller reset failed!\n"); 4084 goto bnx_init_exit; 4085 } 4086 4087 if ((error = bnx_chipinit(sc)) != 0) { 4088 aprint_error("bnx: Controller initialization failed!\n"); 4089 goto bnx_init_exit; 4090 } 4091 4092 if ((error = bnx_blockinit(sc)) != 0) { 4093 aprint_error("bnx: Block initialization failed!\n"); 4094 goto bnx_init_exit; 4095 } 4096 4097 /* Calculate and program the Ethernet MRU size. */ 4098 if (ifp->if_mtu <= ETHERMTU) { 4099 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4100 sc->mbuf_alloc_size = MCLBYTES; 4101 } else { 4102 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4103 sc->mbuf_alloc_size = BNX_MAX_MRU; 4104 } 4105 4106 4107 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4108 __FUNCTION__, ether_mtu); 4109 4110 /* 4111 * Program the MRU and enable Jumbo frame 4112 * support. 4113 */ 4114 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4115 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4116 4117 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4118 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4119 4120 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4121 "max_frame_size = %d\n", __FUNCTION__, (int)MCLBYTES, 4122 sc->mbuf_alloc_size, sc->max_frame_size); 4123 4124 /* Program appropriate promiscuous/multicast filtering. */ 4125 bnx_set_rx_mode(sc); 4126 4127 /* Init RX buffer descriptor chain. */ 4128 bnx_init_rx_chain(sc); 4129 4130 /* Init TX buffer descriptor chain. */ 4131 bnx_init_tx_chain(sc); 4132 4133 /* Enable host interrupts. */ 4134 bnx_enable_intr(sc); 4135 4136 bnx_ifmedia_upd(ifp); 4137 4138 ifp->if_flags |= IFF_RUNNING; 4139 ifp->if_flags &= ~IFF_OACTIVE; 4140 4141 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4142 4143 bnx_init_exit: 4144 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4145 4146 splx(s); 4147 4148 return(error); 4149 } 4150 4151 /****************************************************************************/ 4152 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4153 /* memory visible to the controller. */ 4154 /* */ 4155 /* Returns: */ 4156 /* 0 for success, positive value for failure. */ 4157 /****************************************************************************/ 4158 int 4159 bnx_tx_encap(struct bnx_softc *sc, struct mbuf **m_head) 4160 { 4161 bus_dmamap_t map; 4162 struct tx_bd *txbd = NULL; 4163 struct mbuf *m0; 4164 u_int16_t vlan_tag = 0, flags = 0; 4165 u_int16_t chain_prod, prod; 4166 #ifdef BNX_DEBUG 4167 u_int16_t debug_prod; 4168 #endif 4169 u_int32_t addr, prod_bseq; 4170 int i, error, rc = 0; 4171 struct m_tag *mtag; 4172 4173 m0 = *m_head; 4174 4175 /* Transfer any checksum offload flags to the bd. */ 4176 if (m0->m_pkthdr.csum_flags) { 4177 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 4178 flags |= TX_BD_FLAGS_IP_CKSUM; 4179 if (m0->m_pkthdr.csum_flags & 4180 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4181 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4182 } 4183 4184 /* Transfer any VLAN tags to the bd. */ 4185 mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m0); 4186 if (mtag != NULL) { 4187 flags |= TX_BD_FLAGS_VLAN_TAG; 4188 vlan_tag = VLAN_TAG_VALUE(mtag); 4189 } 4190 4191 /* Map the mbuf into DMAable memory. */ 4192 prod = sc->tx_prod; 4193 chain_prod = TX_CHAIN_IDX(prod); 4194 map = sc->tx_mbuf_map[chain_prod]; 4195 4196 /* Map the mbuf into our DMA address space. */ 4197 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m0, BUS_DMA_NOWAIT); 4198 if (error != 0) { 4199 aprint_error("%s: Error mapping mbuf into TX chain!\n", 4200 sc->bnx_dev.dv_xname); 4201 m_freem(m0); 4202 *m_head = NULL; 4203 return (error); 4204 } 4205 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4206 BUS_DMASYNC_PREWRITE); 4207 /* 4208 * The chip seems to require that at least 16 descriptors be kept 4209 * empty at all times. Make sure we honor that. 4210 * XXX Would it be faster to assume worst case scenario for 4211 * map->dm_nsegs and do this calculation higher up? 4212 */ 4213 if (map->dm_nsegs > (USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE)) { 4214 bus_dmamap_unload(sc->bnx_dmatag, map); 4215 return (ENOBUFS); 4216 } 4217 4218 /* prod points to an empty tx_bd at this point. */ 4219 prod_bseq = sc->tx_prod_bseq; 4220 #ifdef BNX_DEBUG 4221 debug_prod = chain_prod; 4222 #endif 4223 DBPRINT(sc, BNX_INFO_SEND, 4224 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4225 "prod_bseq = 0x%08X\n", 4226 __FUNCTION__, *prod, chain_prod, prod_bseq); 4227 4228 /* 4229 * Cycle through each mbuf segment that makes up 4230 * the outgoing frame, gathering the mapping info 4231 * for that segment and creating a tx_bd for the 4232 * mbuf. 4233 */ 4234 for (i = 0; i < map->dm_nsegs ; i++) { 4235 chain_prod = TX_CHAIN_IDX(prod); 4236 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4237 4238 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 4239 txbd->tx_bd_haddr_lo = htole32(addr); 4240 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4241 txbd->tx_bd_haddr_hi = htole32(addr); 4242 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 4243 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4244 txbd->tx_bd_flags = htole16(flags); 4245 prod_bseq += map->dm_segs[i].ds_len; 4246 if (i == 0) 4247 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4248 prod = NEXT_TX_BD(prod); 4249 } 4250 /* Set the END flag on the last TX buffer descriptor. */ 4251 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4252 4253 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg)); 4254 4255 DBPRINT(sc, BNX_INFO_SEND, 4256 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4257 "prod_bseq = 0x%08X\n", 4258 __FUNCTION__, prod, chain_prod, prod_bseq); 4259 4260 /* 4261 * Ensure that the mbuf pointer for this 4262 * transmission is placed at the array 4263 * index of the last descriptor in this 4264 * chain. This is done because a single 4265 * map is used for all segments of the mbuf 4266 * and we don't want to unload the map before 4267 * all of the segments have been freed. 4268 */ 4269 sc->tx_mbuf_ptr[chain_prod] = m0; 4270 sc->used_tx_bd += map->dm_nsegs; 4271 4272 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4273 sc->tx_hi_watermark = sc->used_tx_bd); 4274 4275 DBRUNIF(1, sc->tx_mbuf_alloc++); 4276 4277 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4278 map_arg.maxsegs)); 4279 4280 /* prod points to the next free tx_bd at this point. */ 4281 sc->tx_prod = prod; 4282 sc->tx_prod_bseq = prod_bseq; 4283 4284 return (rc); 4285 } 4286 4287 /****************************************************************************/ 4288 /* Main transmit routine. */ 4289 /* */ 4290 /* Returns: */ 4291 /* Nothing. */ 4292 /****************************************************************************/ 4293 void 4294 bnx_start(struct ifnet *ifp) 4295 { 4296 struct bnx_softc *sc = ifp->if_softc; 4297 struct mbuf *m_head = NULL; 4298 int count = 0; 4299 u_int16_t tx_prod, tx_chain_prod; 4300 4301 /* If there's no link or the transmit queue is empty then just exit. */ 4302 if (!sc->bnx_link || IFQ_IS_EMPTY(&ifp->if_snd)) { 4303 DBPRINT(sc, BNX_INFO_SEND, 4304 "%s(): No link or transmit queue empty.\n", __FUNCTION__); 4305 goto bnx_start_exit; 4306 } 4307 4308 /* prod points to the next free tx_bd. */ 4309 tx_prod = sc->tx_prod; 4310 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4311 4312 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 4313 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n", 4314 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4315 4316 /* 4317 * Keep adding entries while there is space in the ring. We keep 4318 * BNX_TX_SLACK_SPACE entries unused at all times. 4319 */ 4320 while (sc->used_tx_bd < USABLE_TX_BD - BNX_TX_SLACK_SPACE) { 4321 /* Check for any frames to send. */ 4322 IFQ_POLL(&ifp->if_snd, m_head); 4323 if (m_head == NULL) 4324 break; 4325 4326 /* 4327 * Pack the data into the transmit ring. If we 4328 * don't have room, set the OACTIVE flag to wait 4329 * for the NIC to drain the chain. 4330 */ 4331 if (bnx_tx_encap(sc, &m_head)) { 4332 ifp->if_flags |= IFF_OACTIVE; 4333 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 4334 "business! Total tx_bd used = %d\n", 4335 sc->used_tx_bd); 4336 break; 4337 } 4338 4339 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4340 count++; 4341 4342 #if NBPFILTER > 0 4343 /* Send a copy of the frame to any BPF listeners. */ 4344 if (ifp->if_bpf) 4345 bpf_mtap(ifp->if_bpf, m_head); 4346 #endif 4347 } 4348 4349 if (count == 0) { 4350 /* no packets were dequeued */ 4351 DBPRINT(sc, BNX_VERBOSE_SEND, 4352 "%s(): No packets were dequeued\n", __FUNCTION__); 4353 goto bnx_start_exit; 4354 } 4355 4356 /* Update the driver's counters. */ 4357 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4358 4359 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 4360 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __FUNCTION__, tx_prod, 4361 tx_chain_prod, sc->tx_prod_bseq); 4362 4363 /* Start the transmit. */ 4364 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4365 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4366 4367 /* Set the tx timeout. */ 4368 ifp->if_timer = BNX_TX_TIMEOUT; 4369 4370 bnx_start_exit: 4371 return; 4372 } 4373 4374 /****************************************************************************/ 4375 /* Handles any IOCTL calls from the operating system. */ 4376 /* */ 4377 /* Returns: */ 4378 /* 0 for success, positive value for failure. */ 4379 /****************************************************************************/ 4380 int 4381 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 4382 { 4383 struct bnx_softc *sc = ifp->if_softc; 4384 struct ifreq *ifr = (struct ifreq *) data; 4385 struct mii_data *mii; 4386 int s, error = 0; 4387 4388 s = splnet(); 4389 4390 switch (command) { 4391 case SIOCSIFFLAGS: 4392 if (ifp->if_flags & IFF_UP) { 4393 if ((ifp->if_flags & IFF_RUNNING) && 4394 ((ifp->if_flags ^ sc->bnx_if_flags) & 4395 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 4396 bnx_set_rx_mode(sc); 4397 } else if (!(ifp->if_flags & IFF_RUNNING)) 4398 bnx_init(ifp); 4399 4400 } else if (ifp->if_flags & IFF_RUNNING) 4401 bnx_stop(sc); 4402 4403 sc->bnx_if_flags = ifp->if_flags; 4404 break; 4405 4406 case SIOCSIFMEDIA: 4407 case SIOCGIFMEDIA: 4408 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 4409 sc->bnx_phy_flags); 4410 4411 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 4412 error = ifmedia_ioctl(ifp, ifr, 4413 &sc->bnx_ifmedia, command); 4414 else { 4415 mii = &sc->bnx_mii; 4416 error = ifmedia_ioctl(ifp, ifr, 4417 &mii->mii_media, command); 4418 } 4419 break; 4420 4421 default: 4422 error = ether_ioctl(ifp, command, data); 4423 if (error != ENETRESET) 4424 break; 4425 error = 0; 4426 if (command == SIOCADDMULTI || command == SIOCDELMULTI) { 4427 /* reload packet filter if running */ 4428 if (ifp->if_flags & IFF_RUNNING) 4429 bnx_set_rx_mode(sc); 4430 } 4431 break; 4432 } 4433 4434 splx(s); 4435 4436 return (error); 4437 } 4438 4439 /****************************************************************************/ 4440 /* Transmit timeout handler. */ 4441 /* */ 4442 /* Returns: */ 4443 /* Nothing. */ 4444 /****************************************************************************/ 4445 void 4446 bnx_watchdog(struct ifnet *ifp) 4447 { 4448 struct bnx_softc *sc = ifp->if_softc; 4449 4450 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 4451 bnx_dump_status_block(sc)); 4452 4453 aprint_error("%s: Watchdog timeout -- resetting!\n", 4454 sc->bnx_dev.dv_xname); 4455 4456 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 4457 4458 bnx_init(ifp); 4459 4460 ifp->if_oerrors++; 4461 } 4462 4463 /* 4464 * Interrupt handler. 4465 */ 4466 /****************************************************************************/ 4467 /* Main interrupt entry point. Verifies that the controller generated the */ 4468 /* interrupt and then calls a separate routine for handle the various */ 4469 /* interrupt causes (PHY, TX, RX). */ 4470 /* */ 4471 /* Returns: */ 4472 /* 0 for success, positive value for failure. */ 4473 /****************************************************************************/ 4474 int 4475 bnx_intr(void *xsc) 4476 { 4477 struct bnx_softc *sc; 4478 struct ifnet *ifp; 4479 u_int32_t status_attn_bits; 4480 4481 sc = xsc; 4482 ifp = &sc->ethercom.ec_if; 4483 4484 DBRUNIF(1, sc->interrupts_generated++); 4485 4486 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4487 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4488 4489 /* 4490 * If the hardware status block index 4491 * matches the last value read by the 4492 * driver and we haven't asserted our 4493 * interrupt then there's nothing to do. 4494 */ 4495 if ((sc->status_block->status_idx == sc->last_status_idx) && 4496 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 4497 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 4498 return (0); 4499 4500 /* Ack the interrupt and stop others from occuring. */ 4501 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4502 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 4503 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4504 4505 /* Keep processing data as long as there is work to do. */ 4506 for (;;) { 4507 status_attn_bits = sc->status_block->status_attn_bits; 4508 4509 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 4510 aprint_debug("Simulating unexpected status attention bit set."); 4511 status_attn_bits = status_attn_bits | 4512 STATUS_ATTN_BITS_PARITY_ERROR); 4513 4514 /* Was it a link change interrupt? */ 4515 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 4516 (sc->status_block->status_attn_bits_ack & 4517 STATUS_ATTN_BITS_LINK_STATE)) 4518 bnx_phy_intr(sc); 4519 4520 /* If any other attention is asserted then the chip is toast. */ 4521 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 4522 (sc->status_block->status_attn_bits_ack & 4523 ~STATUS_ATTN_BITS_LINK_STATE))) { 4524 DBRUN(1, sc->unexpected_attentions++); 4525 4526 aprint_error("%s: Fatal attention detected: 0x%08X\n", 4527 sc->bnx_dev.dv_xname, 4528 sc->status_block->status_attn_bits); 4529 4530 DBRUN(BNX_FATAL, 4531 if (bnx_debug_unexpected_attention == 0) 4532 bnx_breakpoint(sc)); 4533 4534 bnx_init(ifp); 4535 return (1); 4536 } 4537 4538 /* Check for any completed RX frames. */ 4539 if (sc->status_block->status_rx_quick_consumer_index0 != 4540 sc->hw_rx_cons) 4541 bnx_rx_intr(sc); 4542 4543 /* Check for any completed TX frames. */ 4544 if (sc->status_block->status_tx_quick_consumer_index0 != 4545 sc->hw_tx_cons) 4546 bnx_tx_intr(sc); 4547 4548 /* Save the status block index value for use during the 4549 * next interrupt. 4550 */ 4551 sc->last_status_idx = sc->status_block->status_idx; 4552 4553 /* Prevent speculative reads from getting ahead of the 4554 * status block. 4555 */ 4556 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4557 BUS_SPACE_BARRIER_READ); 4558 4559 /* If there's no work left then exit the isr. */ 4560 if ((sc->status_block->status_rx_quick_consumer_index0 == 4561 sc->hw_rx_cons) && 4562 (sc->status_block->status_tx_quick_consumer_index0 == 4563 sc->hw_tx_cons)) 4564 break; 4565 } 4566 4567 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4568 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 4569 4570 /* Re-enable interrupts. */ 4571 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4572 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 4573 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4574 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4575 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4576 4577 /* Handle any frames that arrived while handling the interrupt. */ 4578 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4579 bnx_start(ifp); 4580 4581 return (1); 4582 } 4583 4584 /****************************************************************************/ 4585 /* Programs the various packet receive modes (broadcast and multicast). */ 4586 /* */ 4587 /* Returns: */ 4588 /* Nothing. */ 4589 /****************************************************************************/ 4590 void 4591 bnx_set_rx_mode(struct bnx_softc *sc) 4592 { 4593 struct ethercom *ec = &sc->ethercom; 4594 struct ifnet *ifp = &ec->ec_if; 4595 struct ether_multi *enm; 4596 struct ether_multistep step; 4597 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 4598 u_int32_t rx_mode, sort_mode; 4599 int h, i; 4600 4601 /* Initialize receive mode default settings. */ 4602 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 4603 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 4604 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 4605 4606 /* 4607 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 4608 * be enbled. 4609 */ 4610 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 4611 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 4612 4613 /* 4614 * Check for promiscuous, all multicast, or selected 4615 * multicast address filtering. 4616 */ 4617 if (ifp->if_flags & IFF_PROMISC) { 4618 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 4619 4620 /* Enable promiscuous mode. */ 4621 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 4622 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 4623 } else if (ifp->if_flags & IFF_ALLMULTI) { 4624 allmulti: 4625 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 4626 4627 /* Enable all multicast addresses. */ 4628 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4629 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4630 0xffffffff); 4631 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 4632 } else { 4633 /* Accept one or more multicast(s). */ 4634 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 4635 4636 ETHER_FIRST_MULTI(step, ec, enm); 4637 while (enm != NULL) { 4638 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 4639 ETHER_ADDR_LEN)) { 4640 ifp->if_flags |= IFF_ALLMULTI; 4641 goto allmulti; 4642 } 4643 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 4644 0xFF; 4645 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 4646 ETHER_NEXT_MULTI(step, enm); 4647 } 4648 4649 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4650 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4651 hashes[i]); 4652 4653 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 4654 } 4655 4656 /* Only make changes if the recive mode has actually changed. */ 4657 if (rx_mode != sc->rx_mode) { 4658 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 4659 rx_mode); 4660 4661 sc->rx_mode = rx_mode; 4662 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 4663 } 4664 4665 /* Disable and clear the exisitng sort before enabling a new sort. */ 4666 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 4667 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 4668 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 4669 } 4670 4671 /****************************************************************************/ 4672 /* Called periodically to updates statistics from the controllers */ 4673 /* statistics block. */ 4674 /* */ 4675 /* Returns: */ 4676 /* Nothing. */ 4677 /****************************************************************************/ 4678 void 4679 bnx_stats_update(struct bnx_softc *sc) 4680 { 4681 struct ifnet *ifp = &sc->ethercom.ec_if; 4682 struct statistics_block *stats; 4683 4684 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 4685 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4686 BUS_DMASYNC_POSTREAD); 4687 4688 stats = (struct statistics_block *)sc->stats_block; 4689 4690 /* 4691 * Update the interface statistics from the 4692 * hardware statistics. 4693 */ 4694 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 4695 4696 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 4697 (u_long)stats->stat_EtherStatsOverrsizePkts + 4698 (u_long)stats->stat_IfInMBUFDiscards + 4699 (u_long)stats->stat_Dot3StatsAlignmentErrors + 4700 (u_long)stats->stat_Dot3StatsFCSErrors; 4701 4702 ifp->if_oerrors = (u_long) 4703 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 4704 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 4705 (u_long)stats->stat_Dot3StatsLateCollisions; 4706 4707 /* 4708 * Certain controllers don't report 4709 * carrier sense errors correctly. 4710 * See errata E11_5708CA0_1165. 4711 */ 4712 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 4713 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 4714 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 4715 4716 /* 4717 * Update the sysctl statistics from the 4718 * hardware statistics. 4719 */ 4720 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 4721 (u_int64_t) stats->stat_IfHCInOctets_lo; 4722 4723 sc->stat_IfHCInBadOctets = 4724 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 4725 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 4726 4727 sc->stat_IfHCOutOctets = 4728 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 4729 (u_int64_t) stats->stat_IfHCOutOctets_lo; 4730 4731 sc->stat_IfHCOutBadOctets = 4732 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 4733 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 4734 4735 sc->stat_IfHCInUcastPkts = 4736 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 4737 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 4738 4739 sc->stat_IfHCInMulticastPkts = 4740 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 4741 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 4742 4743 sc->stat_IfHCInBroadcastPkts = 4744 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 4745 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 4746 4747 sc->stat_IfHCOutUcastPkts = 4748 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 4749 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 4750 4751 sc->stat_IfHCOutMulticastPkts = 4752 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 4753 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 4754 4755 sc->stat_IfHCOutBroadcastPkts = 4756 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 4757 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 4758 4759 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 4760 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4761 4762 sc->stat_Dot3StatsCarrierSenseErrors = 4763 stats->stat_Dot3StatsCarrierSenseErrors; 4764 4765 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 4766 4767 sc->stat_Dot3StatsAlignmentErrors = 4768 stats->stat_Dot3StatsAlignmentErrors; 4769 4770 sc->stat_Dot3StatsSingleCollisionFrames = 4771 stats->stat_Dot3StatsSingleCollisionFrames; 4772 4773 sc->stat_Dot3StatsMultipleCollisionFrames = 4774 stats->stat_Dot3StatsMultipleCollisionFrames; 4775 4776 sc->stat_Dot3StatsDeferredTransmissions = 4777 stats->stat_Dot3StatsDeferredTransmissions; 4778 4779 sc->stat_Dot3StatsExcessiveCollisions = 4780 stats->stat_Dot3StatsExcessiveCollisions; 4781 4782 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 4783 4784 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 4785 4786 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 4787 4788 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 4789 4790 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 4791 4792 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 4793 4794 sc->stat_EtherStatsPktsRx64Octets = 4795 stats->stat_EtherStatsPktsRx64Octets; 4796 4797 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 4798 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 4799 4800 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 4801 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 4802 4803 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 4804 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 4805 4806 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 4807 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 4808 4809 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 4810 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 4811 4812 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 4813 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 4814 4815 sc->stat_EtherStatsPktsTx64Octets = 4816 stats->stat_EtherStatsPktsTx64Octets; 4817 4818 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 4819 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 4820 4821 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 4822 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 4823 4824 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 4825 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 4826 4827 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 4828 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 4829 4830 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 4831 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 4832 4833 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 4834 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 4835 4836 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 4837 4838 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 4839 4840 sc->stat_OutXonSent = stats->stat_OutXonSent; 4841 4842 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 4843 4844 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 4845 4846 sc->stat_MacControlFramesReceived = 4847 stats->stat_MacControlFramesReceived; 4848 4849 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 4850 4851 sc->stat_IfInFramesL2FilterDiscards = 4852 stats->stat_IfInFramesL2FilterDiscards; 4853 4854 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 4855 4856 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 4857 4858 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 4859 4860 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 4861 4862 sc->stat_CatchupInRuleCheckerDiscards = 4863 stats->stat_CatchupInRuleCheckerDiscards; 4864 4865 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 4866 4867 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 4868 4869 sc->stat_CatchupInRuleCheckerP4Hit = 4870 stats->stat_CatchupInRuleCheckerP4Hit; 4871 4872 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 4873 } 4874 4875 void 4876 bnx_tick(void *xsc) 4877 { 4878 struct bnx_softc *sc = xsc; 4879 struct ifnet *ifp = &sc->ethercom.ec_if; 4880 struct mii_data *mii = NULL; 4881 u_int32_t msg; 4882 u_int16_t prod, chain_prod; 4883 u_int32_t prod_bseq; 4884 int s = splnet(); 4885 4886 /* Tell the firmware that the driver is still running. */ 4887 #ifdef BNX_DEBUG 4888 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 4889 #else 4890 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 4891 #endif 4892 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 4893 4894 /* Update the statistics from the hardware statistics block. */ 4895 bnx_stats_update(sc); 4896 4897 /* Schedule the next tick. */ 4898 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4899 4900 /* If link is up already up then we're done. */ 4901 if (sc->bnx_link) 4902 goto bnx_tick_exit; 4903 4904 /* DRC - ToDo: Add SerDes support and check SerDes link here. */ 4905 4906 mii = &sc->bnx_mii; 4907 mii_tick(mii); 4908 4909 /* Check if the link has come up. */ 4910 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 4911 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4912 sc->bnx_link++; 4913 /* Now that link is up, handle any outstanding TX traffic. */ 4914 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4915 bnx_start(ifp); 4916 } 4917 4918 bnx_tick_exit: 4919 /* try to get more RX buffers, just in case */ 4920 prod = sc->rx_prod; 4921 prod_bseq = sc->rx_prod_bseq; 4922 chain_prod = RX_CHAIN_IDX(prod); 4923 bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq); 4924 sc->rx_prod = prod; 4925 sc->rx_prod_bseq = prod_bseq; 4926 splx(s); 4927 return; 4928 } 4929 4930 /****************************************************************************/ 4931 /* BNX Debug Routines */ 4932 /****************************************************************************/ 4933 #ifdef BNX_DEBUG 4934 4935 /****************************************************************************/ 4936 /* Prints out information about an mbuf. */ 4937 /* */ 4938 /* Returns: */ 4939 /* Nothing. */ 4940 /****************************************************************************/ 4941 void 4942 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 4943 { 4944 struct mbuf *mp = m; 4945 4946 if (m == NULL) { 4947 /* Index out of range. */ 4948 aprint_error("mbuf ptr is null!\n"); 4949 return; 4950 } 4951 4952 while (mp) { 4953 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 4954 mp, mp->m_len); 4955 4956 if (mp->m_flags & M_EXT) 4957 aprint_debug("M_EXT "); 4958 if (mp->m_flags & M_PKTHDR) 4959 aprint_debug("M_PKTHDR "); 4960 aprint_debug("\n"); 4961 4962 if (mp->m_flags & M_EXT) 4963 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 4964 mp, mp->m_ext.ext_size); 4965 4966 mp = mp->m_next; 4967 } 4968 } 4969 4970 /****************************************************************************/ 4971 /* Prints out the mbufs in the TX mbuf chain. */ 4972 /* */ 4973 /* Returns: */ 4974 /* Nothing. */ 4975 /****************************************************************************/ 4976 void 4977 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4978 { 4979 struct mbuf *m; 4980 int i; 4981 4982 BNX_PRINTF(sc, 4983 "----------------------------" 4984 " tx mbuf data " 4985 "----------------------------\n"); 4986 4987 for (i = 0; i < count; i++) { 4988 m = sc->tx_mbuf_ptr[chain_prod]; 4989 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 4990 bnx_dump_mbuf(sc, m); 4991 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 4992 } 4993 4994 BNX_PRINTF(sc, 4995 "--------------------------------------------" 4996 "----------------------------\n"); 4997 } 4998 4999 /* 5000 * This routine prints the RX mbuf chain. 5001 */ 5002 void 5003 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5004 { 5005 struct mbuf *m; 5006 int i; 5007 5008 BNX_PRINTF(sc, 5009 "----------------------------" 5010 " rx mbuf data " 5011 "----------------------------\n"); 5012 5013 for (i = 0; i < count; i++) { 5014 m = sc->rx_mbuf_ptr[chain_prod]; 5015 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5016 bnx_dump_mbuf(sc, m); 5017 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5018 } 5019 5020 5021 BNX_PRINTF(sc, 5022 "--------------------------------------------" 5023 "----------------------------\n"); 5024 } 5025 5026 void 5027 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5028 { 5029 if (idx > MAX_TX_BD) 5030 /* Index out of range. */ 5031 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5032 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5033 /* TX Chain page pointer. */ 5034 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5035 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5036 txbd->tx_bd_haddr_lo); 5037 else 5038 /* Normal tx_bd entry. */ 5039 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5040 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5041 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5042 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5043 txbd->tx_bd_flags); 5044 } 5045 5046 void 5047 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5048 { 5049 if (idx > MAX_RX_BD) 5050 /* Index out of range. */ 5051 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5052 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5053 /* TX Chain page pointer. */ 5054 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5055 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5056 rxbd->rx_bd_haddr_lo); 5057 else 5058 /* Normal tx_bd entry. */ 5059 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5060 "0x%08X, flags = 0x%08X\n", idx, 5061 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5062 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5063 } 5064 5065 void 5066 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5067 { 5068 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5069 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5070 "tcp_udp_xsum = 0x%04X\n", idx, 5071 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5072 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5073 l2fhdr->l2_fhdr_tcp_udp_xsum); 5074 } 5075 5076 /* 5077 * This routine prints the TX chain. 5078 */ 5079 void 5080 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5081 { 5082 struct tx_bd *txbd; 5083 int i; 5084 5085 /* First some info about the tx_bd chain structure. */ 5086 BNX_PRINTF(sc, 5087 "----------------------------" 5088 " tx_bd chain " 5089 "----------------------------\n"); 5090 5091 BNX_PRINTF(sc, 5092 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5093 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5094 5095 BNX_PRINTF(sc, 5096 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5097 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5098 5099 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD); 5100 5101 BNX_PRINTF(sc, "" 5102 "-----------------------------" 5103 " tx_bd data " 5104 "-----------------------------\n"); 5105 5106 /* Now print out the tx_bd's themselves. */ 5107 for (i = 0; i < count; i++) { 5108 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5109 bnx_dump_txbd(sc, tx_prod, txbd); 5110 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5111 } 5112 5113 BNX_PRINTF(sc, 5114 "-----------------------------" 5115 "--------------" 5116 "-----------------------------\n"); 5117 } 5118 5119 /* 5120 * This routine prints the RX chain. 5121 */ 5122 void 5123 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5124 { 5125 struct rx_bd *rxbd; 5126 int i; 5127 5128 /* First some info about the tx_bd chain structure. */ 5129 BNX_PRINTF(sc, 5130 "----------------------------" 5131 " rx_bd chain " 5132 "----------------------------\n"); 5133 5134 BNX_PRINTF(sc, "----- RX_BD Chain -----\n"); 5135 5136 BNX_PRINTF(sc, 5137 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5138 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5139 5140 BNX_PRINTF(sc, 5141 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5142 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5143 5144 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD); 5145 5146 BNX_PRINTF(sc, 5147 "----------------------------" 5148 " rx_bd data " 5149 "----------------------------\n"); 5150 5151 /* Now print out the rx_bd's themselves. */ 5152 for (i = 0; i < count; i++) { 5153 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5154 bnx_dump_rxbd(sc, rx_prod, rxbd); 5155 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5156 } 5157 5158 BNX_PRINTF(sc, 5159 "----------------------------" 5160 "--------------" 5161 "----------------------------\n"); 5162 } 5163 5164 /* 5165 * This routine prints the status block. 5166 */ 5167 void 5168 bnx_dump_status_block(struct bnx_softc *sc) 5169 { 5170 struct status_block *sblk; 5171 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5172 BUS_DMASYNC_POSTREAD); 5173 5174 sblk = sc->status_block; 5175 5176 BNX_PRINTF(sc, "----------------------------- Status Block " 5177 "-----------------------------\n"); 5178 5179 BNX_PRINTF(sc, 5180 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5181 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5182 sblk->status_idx); 5183 5184 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5185 sblk->status_rx_quick_consumer_index0, 5186 sblk->status_tx_quick_consumer_index0); 5187 5188 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5189 5190 /* Theses indices are not used for normal L2 drivers. */ 5191 if (sblk->status_rx_quick_consumer_index1 || 5192 sblk->status_tx_quick_consumer_index1) 5193 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5194 sblk->status_rx_quick_consumer_index1, 5195 sblk->status_tx_quick_consumer_index1); 5196 5197 if (sblk->status_rx_quick_consumer_index2 || 5198 sblk->status_tx_quick_consumer_index2) 5199 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5200 sblk->status_rx_quick_consumer_index2, 5201 sblk->status_tx_quick_consumer_index2); 5202 5203 if (sblk->status_rx_quick_consumer_index3 || 5204 sblk->status_tx_quick_consumer_index3) 5205 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5206 sblk->status_rx_quick_consumer_index3, 5207 sblk->status_tx_quick_consumer_index3); 5208 5209 if (sblk->status_rx_quick_consumer_index4 || 5210 sblk->status_rx_quick_consumer_index5) 5211 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5212 sblk->status_rx_quick_consumer_index4, 5213 sblk->status_rx_quick_consumer_index5); 5214 5215 if (sblk->status_rx_quick_consumer_index6 || 5216 sblk->status_rx_quick_consumer_index7) 5217 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5218 sblk->status_rx_quick_consumer_index6, 5219 sblk->status_rx_quick_consumer_index7); 5220 5221 if (sblk->status_rx_quick_consumer_index8 || 5222 sblk->status_rx_quick_consumer_index9) 5223 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5224 sblk->status_rx_quick_consumer_index8, 5225 sblk->status_rx_quick_consumer_index9); 5226 5227 if (sblk->status_rx_quick_consumer_index10 || 5228 sblk->status_rx_quick_consumer_index11) 5229 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5230 sblk->status_rx_quick_consumer_index10, 5231 sblk->status_rx_quick_consumer_index11); 5232 5233 if (sblk->status_rx_quick_consumer_index12 || 5234 sblk->status_rx_quick_consumer_index13) 5235 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5236 sblk->status_rx_quick_consumer_index12, 5237 sblk->status_rx_quick_consumer_index13); 5238 5239 if (sblk->status_rx_quick_consumer_index14 || 5240 sblk->status_rx_quick_consumer_index15) 5241 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5242 sblk->status_rx_quick_consumer_index14, 5243 sblk->status_rx_quick_consumer_index15); 5244 5245 if (sblk->status_completion_producer_index || 5246 sblk->status_cmd_consumer_index) 5247 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5248 sblk->status_completion_producer_index, 5249 sblk->status_cmd_consumer_index); 5250 5251 BNX_PRINTF(sc, "-------------------------------------------" 5252 "-----------------------------\n"); 5253 } 5254 5255 /* 5256 * This routine prints the statistics block. 5257 */ 5258 void 5259 bnx_dump_stats_block(struct bnx_softc *sc) 5260 { 5261 struct statistics_block *sblk; 5262 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5263 BUS_DMASYNC_POSTREAD); 5264 5265 sblk = sc->stats_block; 5266 5267 BNX_PRINTF(sc, "" 5268 "-----------------------------" 5269 " Stats Block " 5270 "-----------------------------\n"); 5271 5272 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5273 "IfHcInBadOctets = 0x%08X:%08X\n", 5274 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5275 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5276 5277 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5278 "IfHcOutBadOctets = 0x%08X:%08X\n", 5279 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5280 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5281 5282 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5283 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5284 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5285 sblk->stat_IfHCInMulticastPkts_hi, 5286 sblk->stat_IfHCInMulticastPkts_lo); 5287 5288 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5289 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5290 sblk->stat_IfHCInBroadcastPkts_hi, 5291 sblk->stat_IfHCInBroadcastPkts_lo, 5292 sblk->stat_IfHCOutUcastPkts_hi, 5293 sblk->stat_IfHCOutUcastPkts_lo); 5294 5295 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5296 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5297 sblk->stat_IfHCOutMulticastPkts_hi, 5298 sblk->stat_IfHCOutMulticastPkts_lo, 5299 sblk->stat_IfHCOutBroadcastPkts_hi, 5300 sblk->stat_IfHCOutBroadcastPkts_lo); 5301 5302 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5303 BNX_PRINTF(sc, "0x%08X : " 5304 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5305 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5306 5307 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5308 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5309 sblk->stat_Dot3StatsCarrierSenseErrors); 5310 5311 if (sblk->stat_Dot3StatsFCSErrors) 5312 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5313 sblk->stat_Dot3StatsFCSErrors); 5314 5315 if (sblk->stat_Dot3StatsAlignmentErrors) 5316 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5317 sblk->stat_Dot3StatsAlignmentErrors); 5318 5319 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5320 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5321 sblk->stat_Dot3StatsSingleCollisionFrames); 5322 5323 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5324 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 5325 sblk->stat_Dot3StatsMultipleCollisionFrames); 5326 5327 if (sblk->stat_Dot3StatsDeferredTransmissions) 5328 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 5329 sblk->stat_Dot3StatsDeferredTransmissions); 5330 5331 if (sblk->stat_Dot3StatsExcessiveCollisions) 5332 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 5333 sblk->stat_Dot3StatsExcessiveCollisions); 5334 5335 if (sblk->stat_Dot3StatsLateCollisions) 5336 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 5337 sblk->stat_Dot3StatsLateCollisions); 5338 5339 if (sblk->stat_EtherStatsCollisions) 5340 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 5341 sblk->stat_EtherStatsCollisions); 5342 5343 if (sblk->stat_EtherStatsFragments) 5344 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 5345 sblk->stat_EtherStatsFragments); 5346 5347 if (sblk->stat_EtherStatsJabbers) 5348 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 5349 sblk->stat_EtherStatsJabbers); 5350 5351 if (sblk->stat_EtherStatsUndersizePkts) 5352 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 5353 sblk->stat_EtherStatsUndersizePkts); 5354 5355 if (sblk->stat_EtherStatsOverrsizePkts) 5356 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 5357 sblk->stat_EtherStatsOverrsizePkts); 5358 5359 if (sblk->stat_EtherStatsPktsRx64Octets) 5360 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 5361 sblk->stat_EtherStatsPktsRx64Octets); 5362 5363 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 5364 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 5365 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 5366 5367 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 5368 BNX_PRINTF(sc, "0x%08X : " 5369 "EtherStatsPktsRx128Octetsto255Octets\n", 5370 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 5371 5372 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 5373 BNX_PRINTF(sc, "0x%08X : " 5374 "EtherStatsPktsRx256Octetsto511Octets\n", 5375 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 5376 5377 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 5378 BNX_PRINTF(sc, "0x%08X : " 5379 "EtherStatsPktsRx512Octetsto1023Octets\n", 5380 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 5381 5382 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 5383 BNX_PRINTF(sc, "0x%08X : " 5384 "EtherStatsPktsRx1024Octetsto1522Octets\n", 5385 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 5386 5387 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 5388 BNX_PRINTF(sc, "0x%08X : " 5389 "EtherStatsPktsRx1523Octetsto9022Octets\n", 5390 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 5391 5392 if (sblk->stat_EtherStatsPktsTx64Octets) 5393 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 5394 sblk->stat_EtherStatsPktsTx64Octets); 5395 5396 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 5397 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 5398 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 5399 5400 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 5401 BNX_PRINTF(sc, "0x%08X : " 5402 "EtherStatsPktsTx128Octetsto255Octets\n", 5403 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 5404 5405 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 5406 BNX_PRINTF(sc, "0x%08X : " 5407 "EtherStatsPktsTx256Octetsto511Octets\n", 5408 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 5409 5410 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 5411 BNX_PRINTF(sc, "0x%08X : " 5412 "EtherStatsPktsTx512Octetsto1023Octets\n", 5413 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 5414 5415 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 5416 BNX_PRINTF(sc, "0x%08X : " 5417 "EtherStatsPktsTx1024Octetsto1522Octets\n", 5418 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 5419 5420 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 5421 BNX_PRINTF(sc, "0x%08X : " 5422 "EtherStatsPktsTx1523Octetsto9022Octets\n", 5423 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 5424 5425 if (sblk->stat_XonPauseFramesReceived) 5426 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 5427 sblk->stat_XonPauseFramesReceived); 5428 5429 if (sblk->stat_XoffPauseFramesReceived) 5430 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 5431 sblk->stat_XoffPauseFramesReceived); 5432 5433 if (sblk->stat_OutXonSent) 5434 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 5435 sblk->stat_OutXonSent); 5436 5437 if (sblk->stat_OutXoffSent) 5438 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 5439 sblk->stat_OutXoffSent); 5440 5441 if (sblk->stat_FlowControlDone) 5442 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 5443 sblk->stat_FlowControlDone); 5444 5445 if (sblk->stat_MacControlFramesReceived) 5446 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 5447 sblk->stat_MacControlFramesReceived); 5448 5449 if (sblk->stat_XoffStateEntered) 5450 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 5451 sblk->stat_XoffStateEntered); 5452 5453 if (sblk->stat_IfInFramesL2FilterDiscards) 5454 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 5455 sblk->stat_IfInFramesL2FilterDiscards); 5456 5457 if (sblk->stat_IfInRuleCheckerDiscards) 5458 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 5459 sblk->stat_IfInRuleCheckerDiscards); 5460 5461 if (sblk->stat_IfInFTQDiscards) 5462 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 5463 sblk->stat_IfInFTQDiscards); 5464 5465 if (sblk->stat_IfInMBUFDiscards) 5466 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 5467 sblk->stat_IfInMBUFDiscards); 5468 5469 if (sblk->stat_IfInRuleCheckerP4Hit) 5470 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 5471 sblk->stat_IfInRuleCheckerP4Hit); 5472 5473 if (sblk->stat_CatchupInRuleCheckerDiscards) 5474 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 5475 sblk->stat_CatchupInRuleCheckerDiscards); 5476 5477 if (sblk->stat_CatchupInFTQDiscards) 5478 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 5479 sblk->stat_CatchupInFTQDiscards); 5480 5481 if (sblk->stat_CatchupInMBUFDiscards) 5482 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 5483 sblk->stat_CatchupInMBUFDiscards); 5484 5485 if (sblk->stat_CatchupInRuleCheckerP4Hit) 5486 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 5487 sblk->stat_CatchupInRuleCheckerP4Hit); 5488 5489 BNX_PRINTF(sc, 5490 "-----------------------------" 5491 "--------------" 5492 "-----------------------------\n"); 5493 } 5494 5495 void 5496 bnx_dump_driver_state(struct bnx_softc *sc) 5497 { 5498 BNX_PRINTF(sc, 5499 "-----------------------------" 5500 " Driver State " 5501 "-----------------------------\n"); 5502 5503 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 5504 "address\n", sc); 5505 5506 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 5507 sc->status_block); 5508 5509 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 5510 "address\n", sc->stats_block); 5511 5512 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 5513 "adddress\n", sc->tx_bd_chain); 5514 5515 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 5516 sc->rx_bd_chain); 5517 5518 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 5519 sc->tx_mbuf_ptr); 5520 5521 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 5522 sc->rx_mbuf_ptr); 5523 5524 BNX_PRINTF(sc, 5525 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 5526 sc->interrupts_generated); 5527 5528 BNX_PRINTF(sc, 5529 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 5530 sc->rx_interrupts); 5531 5532 BNX_PRINTF(sc, 5533 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 5534 sc->tx_interrupts); 5535 5536 BNX_PRINTF(sc, 5537 " 0x%08X - (sc->last_status_idx) status block index\n", 5538 sc->last_status_idx); 5539 5540 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 5541 sc->tx_prod); 5542 5543 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 5544 sc->tx_cons); 5545 5546 BNX_PRINTF(sc, 5547 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 5548 sc->tx_prod_bseq); 5549 5550 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 5551 sc->rx_prod); 5552 5553 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 5554 sc->rx_cons); 5555 5556 BNX_PRINTF(sc, 5557 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 5558 sc->rx_prod_bseq); 5559 5560 BNX_PRINTF(sc, 5561 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5562 sc->rx_mbuf_alloc); 5563 5564 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 5565 sc->free_rx_bd); 5566 5567 BNX_PRINTF(sc, 5568 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 5569 sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD); 5570 5571 BNX_PRINTF(sc, 5572 " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 5573 sc->tx_mbuf_alloc); 5574 5575 BNX_PRINTF(sc, 5576 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5577 sc->rx_mbuf_alloc); 5578 5579 BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 5580 sc->used_tx_bd); 5581 5582 BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 5583 sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD); 5584 5585 BNX_PRINTF(sc, 5586 " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 5587 sc->mbuf_alloc_failed); 5588 5589 BNX_PRINTF(sc, "-------------------------------------------" 5590 "-----------------------------\n"); 5591 } 5592 5593 void 5594 bnx_dump_hw_state(struct bnx_softc *sc) 5595 { 5596 u_int32_t val1; 5597 int i; 5598 5599 BNX_PRINTF(sc, 5600 "----------------------------" 5601 " Hardware State " 5602 "----------------------------\n"); 5603 5604 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 5605 5606 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 5607 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 5608 val1, BNX_MISC_ENABLE_STATUS_BITS); 5609 5610 val1 = REG_RD(sc, BNX_DMA_STATUS); 5611 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 5612 5613 val1 = REG_RD(sc, BNX_CTX_STATUS); 5614 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 5615 5616 val1 = REG_RD(sc, BNX_EMAC_STATUS); 5617 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 5618 BNX_EMAC_STATUS); 5619 5620 val1 = REG_RD(sc, BNX_RPM_STATUS); 5621 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 5622 5623 val1 = REG_RD(sc, BNX_TBDR_STATUS); 5624 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 5625 BNX_TBDR_STATUS); 5626 5627 val1 = REG_RD(sc, BNX_TDMA_STATUS); 5628 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 5629 BNX_TDMA_STATUS); 5630 5631 val1 = REG_RD(sc, BNX_HC_STATUS); 5632 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 5633 5634 BNX_PRINTF(sc, 5635 "----------------------------" 5636 "----------------" 5637 "----------------------------\n"); 5638 5639 BNX_PRINTF(sc, 5640 "----------------------------" 5641 " Register Dump " 5642 "----------------------------\n"); 5643 5644 for (i = 0x400; i < 0x8000; i += 0x10) 5645 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 5646 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 5647 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 5648 5649 BNX_PRINTF(sc, 5650 "----------------------------" 5651 "----------------" 5652 "----------------------------\n"); 5653 } 5654 5655 void 5656 bnx_breakpoint(struct bnx_softc *sc) 5657 { 5658 /* Unreachable code to shut the compiler up about unused functions. */ 5659 if (0) { 5660 bnx_dump_txbd(sc, 0, NULL); 5661 bnx_dump_rxbd(sc, 0, NULL); 5662 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 5663 bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 5664 bnx_dump_l2fhdr(sc, 0, NULL); 5665 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 5666 bnx_dump_rx_chain(sc, 0, USABLE_RX_BD); 5667 bnx_dump_status_block(sc); 5668 bnx_dump_stats_block(sc); 5669 bnx_dump_driver_state(sc); 5670 bnx_dump_hw_state(sc); 5671 } 5672 5673 bnx_dump_driver_state(sc); 5674 /* Print the important status block fields. */ 5675 bnx_dump_status_block(sc); 5676 5677 #if 0 5678 /* Call the debugger. */ 5679 breakpoint(); 5680 #endif 5681 5682 return; 5683 } 5684 #endif 5685
Indexes created Mon Sep 22 13:09:51 GMT 2025