if_bnx.c revision 1.13
1 /* $NetBSD: if_bnx.c,v 1.13 2007/12/26 04:06:29 dyoung Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.43 2007/01/30 03:21:10 krw Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.13 2007/12/26 04:06:29 dyoung Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5708C B1 44 * 45 * The following controllers are not supported by this driver: 46 * (These are not "Production" versions of the controller.) 47 * 48 * BCM5706C A0, A1 49 * BCM5706S A0, A1, A2, A3 50 * BCM5708C A0, B0 51 * BCM5708S A0, B0, B1 52 */ 53 54 #include <sys/callout.h> 55 56 #include <dev/pci/if_bnxreg.h> 57 #include <dev/microcode/bnx/bnxfw.h> 58 59 /****************************************************************************/ 60 /* BNX Driver Version */ 61 /****************************************************************************/ 62 const char bnx_driver_version[] = "v0.9.6"; 63 64 /****************************************************************************/ 65 /* BNX Debug Options */ 66 /****************************************************************************/ 67 #ifdef BNX_DEBUG 68 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 69 70 /* 0 = Never */ 71 /* 1 = 1 in 2,147,483,648 */ 72 /* 256 = 1 in 8,388,608 */ 73 /* 2048 = 1 in 1,048,576 */ 74 /* 65536 = 1 in 32,768 */ 75 /* 1048576 = 1 in 2,048 */ 76 /* 268435456 = 1 in 8 */ 77 /* 536870912 = 1 in 4 */ 78 /* 1073741824 = 1 in 2 */ 79 80 /* Controls how often the l2_fhdr frame error check will fail. */ 81 int bnx_debug_l2fhdr_status_check = 0; 82 83 /* Controls how often the unexpected attention check will fail. */ 84 int bnx_debug_unexpected_attention = 0; 85 86 /* Controls how often to simulate an mbuf allocation failure. */ 87 int bnx_debug_mbuf_allocation_failure = 0; 88 89 /* Controls how often to simulate a DMA mapping failure. */ 90 int bnx_debug_dma_map_addr_failure = 0; 91 92 /* Controls how often to simulate a bootcode failure. */ 93 int bnx_debug_bootcode_running_failure = 0; 94 #endif 95 96 /****************************************************************************/ 97 /* PCI Device ID Table */ 98 /* */ 99 /* Used by bnx_probe() to identify the devices supported by this driver. */ 100 /****************************************************************************/ 101 static const struct bnx_product { 102 pci_vendor_id_t bp_vendor; 103 pci_product_id_t bp_product; 104 pci_vendor_id_t bp_subvendor; 105 pci_product_id_t bp_subproduct; 106 const char *bp_name; 107 } bnx_devices[] = { 108 #ifdef PCI_SUBPRODUCT_HP_NC370T 109 { 110 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 111 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 112 "HP NC370T Multifunction Gigabit Server Adapter" 113 }, 114 #endif 115 #ifdef PCI_SUBPRODUCT_HP_NC370i 116 { 117 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 118 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 119 "HP NC370i Multifunction Gigabit Server Adapter" 120 }, 121 #endif 122 { 123 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 124 0, 0, 125 "Broadcom NetXtreme II BCM5706 1000Base-T" 126 }, 127 #ifdef PCI_SUBPRODUCT_HP_NC370F 128 { 129 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 130 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 131 "HP NC370F Multifunction Gigabit Server Adapter" 132 }, 133 #endif 134 { 135 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 136 0, 0, 137 "Broadcom NetXtreme II BCM5706 1000Base-SX" 138 }, 139 { 140 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 141 0, 0, 142 "Broadcom NetXtreme II BCM5708 1000Base-T" 143 }, 144 { 145 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 146 0, 0, 147 "Broadcom NetXtreme II BCM5708 1000Base-SX" 148 }, 149 }; 150 151 /****************************************************************************/ 152 /* Supported Flash NVRAM device data. */ 153 /****************************************************************************/ 154 static struct flash_spec flash_table[] = 155 { 156 /* Slow EEPROM */ 157 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 158 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 159 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 160 "EEPROM - slow"}, 161 /* Expansion entry 0001 */ 162 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 164 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 165 "Entry 0001"}, 166 /* Saifun SA25F010 (non-buffered flash) */ 167 /* strap, cfg1, & write1 need updates */ 168 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 169 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 171 "Non-buffered flash (128kB)"}, 172 /* Saifun SA25F020 (non-buffered flash) */ 173 /* strap, cfg1, & write1 need updates */ 174 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 175 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 176 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 177 "Non-buffered flash (256kB)"}, 178 /* Expansion entry 0100 */ 179 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 0100"}, 183 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 184 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 185 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 186 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 187 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 188 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 189 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 190 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 191 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 192 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 193 /* Saifun SA25F005 (non-buffered flash) */ 194 /* strap, cfg1, & write1 need updates */ 195 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 196 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 197 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 198 "Non-buffered flash (64kB)"}, 199 /* Fast EEPROM */ 200 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 201 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 202 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 203 "EEPROM - fast"}, 204 /* Expansion entry 1001 */ 205 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 206 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 208 "Entry 1001"}, 209 /* Expansion entry 1010 */ 210 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 211 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 1010"}, 214 /* ATMEL AT45DB011B (buffered flash) */ 215 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 216 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 217 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 218 "Buffered flash (128kB)"}, 219 /* Expansion entry 1100 */ 220 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 221 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 223 "Entry 1100"}, 224 /* Expansion entry 1101 */ 225 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 226 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 228 "Entry 1101"}, 229 /* Ateml Expansion entry 1110 */ 230 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 231 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 232 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 233 "Entry 1110 (Atmel)"}, 234 /* ATMEL AT45DB021B (buffered flash) */ 235 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 236 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 237 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 238 "Buffered flash (256kB)"}, 239 }; 240 241 /****************************************************************************/ 242 /* OpenBSD device entry points. */ 243 /****************************************************************************/ 244 static int bnx_probe(device_t, cfdata_t, void *); 245 bool bnx_suspend_resume(device_t); 246 void bnx_attach(device_t, device_t, void *); 247 int bnx_detach(device_t, int); 248 249 /****************************************************************************/ 250 /* BNX Debug Data Structure Dump Routines */ 251 /****************************************************************************/ 252 #ifdef BNX_DEBUG 253 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 254 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 255 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 256 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 257 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 258 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 259 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 260 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 261 void bnx_dump_status_block(struct bnx_softc *); 262 void bnx_dump_stats_block(struct bnx_softc *); 263 void bnx_dump_driver_state(struct bnx_softc *); 264 void bnx_dump_hw_state(struct bnx_softc *); 265 void bnx_breakpoint(struct bnx_softc *); 266 #endif 267 268 /****************************************************************************/ 269 /* BNX Register/Memory Access Routines */ 270 /****************************************************************************/ 271 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 272 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 273 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 274 int bnx_miibus_read_reg(device_t, int, int); 275 void bnx_miibus_write_reg(device_t, int, int, int); 276 void bnx_miibus_statchg(device_t); 277 278 /****************************************************************************/ 279 /* BNX NVRAM Access Routines */ 280 /****************************************************************************/ 281 int bnx_acquire_nvram_lock(struct bnx_softc *); 282 int bnx_release_nvram_lock(struct bnx_softc *); 283 void bnx_enable_nvram_access(struct bnx_softc *); 284 void bnx_disable_nvram_access(struct bnx_softc *); 285 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 286 u_int32_t); 287 int bnx_init_nvram(struct bnx_softc *); 288 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 289 int bnx_nvram_test(struct bnx_softc *); 290 #ifdef BNX_NVRAM_WRITE_SUPPORT 291 int bnx_enable_nvram_write(struct bnx_softc *); 292 void bnx_disable_nvram_write(struct bnx_softc *); 293 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 294 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 295 u_int32_t); 296 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 297 #endif 298 299 /****************************************************************************/ 300 /* */ 301 /****************************************************************************/ 302 int bnx_dma_alloc(struct bnx_softc *); 303 void bnx_dma_free(struct bnx_softc *); 304 void bnx_release_resources(struct bnx_softc *); 305 306 /****************************************************************************/ 307 /* BNX Firmware Synchronization and Load */ 308 /****************************************************************************/ 309 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 310 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 311 u_int32_t); 312 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 313 struct fw_info *); 314 void bnx_init_cpus(struct bnx_softc *); 315 316 void bnx_if_stop(struct ifnet *, int); 317 void bnx_stop(struct bnx_softc *); 318 int bnx_reset(struct bnx_softc *, u_int32_t); 319 int bnx_chipinit(struct bnx_softc *); 320 int bnx_blockinit(struct bnx_softc *); 321 int bnx_get_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 322 u_int16_t *, u_int32_t *); 323 324 int bnx_init_tx_chain(struct bnx_softc *); 325 int bnx_init_rx_chain(struct bnx_softc *); 326 void bnx_free_rx_chain(struct bnx_softc *); 327 void bnx_free_tx_chain(struct bnx_softc *); 328 329 int bnx_tx_encap(struct bnx_softc *, struct mbuf **); 330 void bnx_start(struct ifnet *); 331 int bnx_ioctl(struct ifnet *, u_long, void *); 332 void bnx_watchdog(struct ifnet *); 333 int bnx_ifmedia_upd(struct ifnet *); 334 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 335 int bnx_init(struct ifnet *); 336 337 void bnx_init_context(struct bnx_softc *); 338 void bnx_get_mac_addr(struct bnx_softc *); 339 void bnx_set_mac_addr(struct bnx_softc *); 340 void bnx_phy_intr(struct bnx_softc *); 341 void bnx_rx_intr(struct bnx_softc *); 342 void bnx_tx_intr(struct bnx_softc *); 343 void bnx_disable_intr(struct bnx_softc *); 344 void bnx_enable_intr(struct bnx_softc *); 345 346 int bnx_intr(void *); 347 void bnx_set_rx_mode(struct bnx_softc *); 348 void bnx_stats_update(struct bnx_softc *); 349 void bnx_tick(void *); 350 351 /****************************************************************************/ 352 /* OpenBSD device dispatch table. */ 353 /****************************************************************************/ 354 CFATTACH_DECL_NEW(bnx, sizeof(struct bnx_softc), 355 bnx_probe, bnx_attach, bnx_detach, NULL); 356 357 /****************************************************************************/ 358 /* Device probe function. */ 359 /* */ 360 /* Compares the device to the driver's list of supported devices and */ 361 /* reports back to the OS whether this is the right driver for the device. */ 362 /* */ 363 /* Returns: */ 364 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 365 /****************************************************************************/ 366 static const struct bnx_product * 367 bnx_lookup(const struct pci_attach_args *pa) 368 { 369 int i; 370 pcireg_t subid; 371 372 for (i = 0; i < __arraycount(bnx_devices); i++) { 373 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 374 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 375 continue; 376 if (!bnx_devices[i].bp_subvendor) 377 return &bnx_devices[i]; 378 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 379 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 380 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 381 return &bnx_devices[i]; 382 } 383 384 return NULL; 385 } 386 static int 387 bnx_probe(device_t parent, cfdata_t match, void *aux) 388 { 389 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 390 391 if (bnx_lookup(pa) != NULL) 392 return (1); 393 394 return (0); 395 } 396 397 bool 398 bnx_suspend_resume(device_t dev) 399 { 400 struct bnx_softc *sc = device_private(dev); 401 402 return bnx_reset(sc, BNX_DRV_MSG_CODE_RESET) == 0; 403 } 404 405 /****************************************************************************/ 406 /* Device attach function. */ 407 /* */ 408 /* Allocates device resources, performs secondary chip identification, */ 409 /* resets and initializes the hardware, and initializes driver instance */ 410 /* variables. */ 411 /* */ 412 /* Returns: */ 413 /* 0 on success, positive value on failure. */ 414 /****************************************************************************/ 415 void 416 bnx_attach(device_t parent, device_t self, void *aux) 417 { 418 const struct bnx_product *bp; 419 struct bnx_softc *sc = device_private(self); 420 struct pci_attach_args *pa = aux; 421 pci_chipset_tag_t pc = pa->pa_pc; 422 pci_intr_handle_t ih; 423 const char *intrstr = NULL; 424 u_int32_t command; 425 struct ifnet *ifp; 426 u_int32_t val; 427 pcireg_t memtype; 428 429 bp = bnx_lookup(pa); 430 if (bp == NULL) 431 panic("unknown device"); 432 433 sc->bnx_dev = self; 434 435 aprint_naive("\n"); 436 aprint_normal(": %s\n", bp->bp_name); 437 438 sc->bnx_pa = *pa; 439 440 /* 441 * Map control/status registers. 442 */ 443 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 444 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 445 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 446 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 447 448 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 449 aprint_error_dev(sc->bnx_dev, 450 "failed to enable memory mapping!\n"); 451 return; 452 } 453 454 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 455 switch (memtype) { 456 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 457 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 458 if (pci_mapreg_map(pa, BNX_PCI_BAR0, 459 memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, 460 NULL, &sc->bnx_size) == 0) 461 break; 462 default: 463 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 464 return; 465 } 466 467 if (pci_intr_map(pa, &ih)) { 468 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 469 goto bnx_attach_fail; 470 } 471 472 intrstr = pci_intr_string(pc, ih); 473 474 /* 475 * Configure byte swap and enable indirect register access. 476 * Rely on CPU to do target byte swapping on big endian systems. 477 * Access to registers outside of PCI configurtion space are not 478 * valid until this is done. 479 */ 480 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 481 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 482 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 483 484 /* Save ASIC revsion info. */ 485 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 486 487 /* Weed out any non-production controller revisions. */ 488 switch(BNX_CHIP_ID(sc)) { 489 case BNX_CHIP_ID_5706_A0: 490 case BNX_CHIP_ID_5706_A1: 491 case BNX_CHIP_ID_5708_A0: 492 case BNX_CHIP_ID_5708_B0: 493 aprint_error_dev(sc->bnx_dev, 494 "unsupported controller revision (%c%d)!\n", 495 ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A', 496 PCI_REVISION(pa->pa_class) & 0x0f); 497 goto bnx_attach_fail; 498 } 499 500 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 501 aprint_error_dev(sc->bnx_dev, 502 "SerDes controllers are not supported!\n"); 503 goto bnx_attach_fail; 504 } 505 506 /* 507 * Find the base address for shared memory access. 508 * Newer versions of bootcode use a signature and offset 509 * while older versions use a fixed address. 510 */ 511 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 512 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 513 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0); 514 else 515 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 516 517 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 518 519 /* Set initial device and PHY flags */ 520 sc->bnx_flags = 0; 521 sc->bnx_phy_flags = 0; 522 523 /* Get PCI bus information (speed and type). */ 524 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 525 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 526 u_int32_t clkreg; 527 528 sc->bnx_flags |= BNX_PCIX_FLAG; 529 530 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 531 532 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 533 switch (clkreg) { 534 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 535 sc->bus_speed_mhz = 133; 536 break; 537 538 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 539 sc->bus_speed_mhz = 100; 540 break; 541 542 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 543 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 544 sc->bus_speed_mhz = 66; 545 break; 546 547 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 548 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 549 sc->bus_speed_mhz = 50; 550 break; 551 552 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 553 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 554 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 555 sc->bus_speed_mhz = 33; 556 break; 557 } 558 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 559 sc->bus_speed_mhz = 66; 560 else 561 sc->bus_speed_mhz = 33; 562 563 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 564 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 565 566 /* Reset the controller. */ 567 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 568 goto bnx_attach_fail; 569 570 /* Initialize the controller. */ 571 if (bnx_chipinit(sc)) { 572 aprint_error_dev(sc->bnx_dev, 573 "Controller initialization failed!\n"); 574 goto bnx_attach_fail; 575 } 576 577 /* Perform NVRAM test. */ 578 if (bnx_nvram_test(sc)) { 579 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 580 goto bnx_attach_fail; 581 } 582 583 /* Fetch the permanent Ethernet MAC address. */ 584 bnx_get_mac_addr(sc); 585 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 586 ether_sprintf(sc->eaddr)); 587 588 /* 589 * Trip points control how many BDs 590 * should be ready before generating an 591 * interrupt while ticks control how long 592 * a BD can sit in the chain before 593 * generating an interrupt. Set the default 594 * values for the RX and TX rings. 595 */ 596 597 #ifdef BNX_DEBUG 598 /* Force more frequent interrupts. */ 599 sc->bnx_tx_quick_cons_trip_int = 1; 600 sc->bnx_tx_quick_cons_trip = 1; 601 sc->bnx_tx_ticks_int = 0; 602 sc->bnx_tx_ticks = 0; 603 604 sc->bnx_rx_quick_cons_trip_int = 1; 605 sc->bnx_rx_quick_cons_trip = 1; 606 sc->bnx_rx_ticks_int = 0; 607 sc->bnx_rx_ticks = 0; 608 #else 609 sc->bnx_tx_quick_cons_trip_int = 20; 610 sc->bnx_tx_quick_cons_trip = 20; 611 sc->bnx_tx_ticks_int = 80; 612 sc->bnx_tx_ticks = 80; 613 614 sc->bnx_rx_quick_cons_trip_int = 6; 615 sc->bnx_rx_quick_cons_trip = 6; 616 sc->bnx_rx_ticks_int = 18; 617 sc->bnx_rx_ticks = 18; 618 #endif 619 620 /* Update statistics once every second. */ 621 sc->bnx_stats_ticks = 1000000 & 0xffff00; 622 623 /* 624 * The copper based NetXtreme II controllers 625 * use an integrated PHY at address 1 while 626 * the SerDes controllers use a PHY at 627 * address 2. 628 */ 629 sc->bnx_phy_addr = 1; 630 631 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 632 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 633 sc->bnx_flags |= BNX_NO_WOL_FLAG; 634 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) { 635 sc->bnx_phy_addr = 2; 636 val = REG_RD_IND(sc, sc->bnx_shmem_base + 637 BNX_SHARED_HW_CFG_CONFIG); 638 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) 639 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 640 } 641 } 642 643 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 644 aprint_error_dev(sc->bnx_dev, 645 "SerDes is not supported by this driver!\n"); 646 goto bnx_attach_fail; 647 } 648 649 /* Allocate DMA memory resources. */ 650 sc->bnx_dmatag = pa->pa_dmat; 651 if (bnx_dma_alloc(sc)) { 652 aprint_error_dev(sc->bnx_dev, 653 "DMA resource allocation failed!\n"); 654 goto bnx_attach_fail; 655 } 656 657 /* Initialize the ifnet interface. */ 658 ifp = &sc->ethercom.ec_if; 659 ifp->if_softc = sc; 660 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 661 ifp->if_ioctl = bnx_ioctl; 662 ifp->if_stop = bnx_if_stop; 663 ifp->if_start = bnx_start; 664 ifp->if_init = bnx_init; 665 ifp->if_timer = 0; 666 ifp->if_watchdog = bnx_watchdog; 667 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 668 ifp->if_baudrate = IF_Gbps(2.5); 669 else 670 ifp->if_baudrate = IF_Gbps(1); 671 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 672 IFQ_SET_READY(&ifp->if_snd); 673 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 674 675 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU | 676 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 677 678 ifp->if_capabilities |= 679 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 680 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 681 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 682 683 /* Hookup IRQ last. */ 684 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 685 if (sc->bnx_intrhand == NULL) { 686 aprint_error_dev(self, "couldn't establish interrupt"); 687 if (intrstr != NULL) 688 aprint_error(" at %s", intrstr); 689 aprint_error("\n"); 690 goto bnx_attach_fail; 691 } 692 693 sc->bnx_mii.mii_ifp = ifp; 694 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 695 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 696 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 697 698 /* Look for our PHY. */ 699 ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, 700 bnx_ifmedia_sts); 701 mii_attach(self, &sc->bnx_mii, 0xffffffff, 702 MII_PHY_ANY, MII_OFFSET_ANY, 0); 703 704 if (LIST_FIRST(&sc->bnx_mii.mii_phys) == NULL) { 705 aprint_error_dev(self, "no PHY found!\n"); 706 ifmedia_add(&sc->bnx_mii.mii_media, 707 IFM_ETHER|IFM_MANUAL, 0, NULL); 708 ifmedia_set(&sc->bnx_mii.mii_media, 709 IFM_ETHER|IFM_MANUAL); 710 } else { 711 ifmedia_set(&sc->bnx_mii.mii_media, 712 IFM_ETHER|IFM_AUTO); 713 } 714 715 /* Attach to the Ethernet interface list. */ 716 if_attach(ifp); 717 ether_ifattach(ifp,sc->eaddr); 718 719 callout_init(&sc->bnx_timeout, 0); 720 721 if (!pmf_device_register(self, bnx_suspend_resume, bnx_suspend_resume)) 722 aprint_error_dev(self, "couldn't establish power handler\n"); 723 else 724 pmf_class_network_register(self, ifp); 725 726 /* Print some important debugging info. */ 727 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 728 729 goto bnx_attach_exit; 730 731 bnx_attach_fail: 732 bnx_release_resources(sc); 733 734 bnx_attach_exit: 735 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 736 } 737 738 /****************************************************************************/ 739 /* Device detach function. */ 740 /* */ 741 /* Stops the controller, resets the controller, and releases resources. */ 742 /* */ 743 /* Returns: */ 744 /* 0 on success, positive value on failure. */ 745 /****************************************************************************/ 746 int 747 bnx_detach(device_t dev, int flags) 748 { 749 struct bnx_softc *sc; 750 struct ifnet *ifp; 751 752 sc = device_private(dev); 753 ifp = &sc->ethercom.ec_if; 754 755 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 756 757 /* Stop and reset the controller. */ 758 bnx_stop(sc); 759 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 760 761 pmf_device_deregister(dev); 762 ether_ifdetach(ifp); 763 if_detach(ifp); 764 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 765 766 /* Release all remaining resources. */ 767 bnx_release_resources(sc); 768 769 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 770 771 return(0); 772 } 773 774 /****************************************************************************/ 775 /* Indirect register read. */ 776 /* */ 777 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 778 /* configuration space. Using this mechanism avoids issues with posted */ 779 /* reads but is much slower than memory-mapped I/O. */ 780 /* */ 781 /* Returns: */ 782 /* The value of the register. */ 783 /****************************************************************************/ 784 u_int32_t 785 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 786 { 787 struct pci_attach_args *pa = &(sc->bnx_pa); 788 789 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 790 offset); 791 #ifdef BNX_DEBUG 792 { 793 u_int32_t val; 794 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 795 BNX_PCICFG_REG_WINDOW); 796 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 797 "val = 0x%08X\n", __func__, offset, val); 798 return (val); 799 } 800 #else 801 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 802 #endif 803 } 804 805 /****************************************************************************/ 806 /* Indirect register write. */ 807 /* */ 808 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 809 /* configuration space. Using this mechanism avoids issues with posted */ 810 /* writes but is muchh slower than memory-mapped I/O. */ 811 /* */ 812 /* Returns: */ 813 /* Nothing. */ 814 /****************************************************************************/ 815 void 816 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 817 { 818 struct pci_attach_args *pa = &(sc->bnx_pa); 819 820 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 821 __func__, offset, val); 822 823 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 824 offset); 825 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 826 } 827 828 /****************************************************************************/ 829 /* Context memory write. */ 830 /* */ 831 /* The NetXtreme II controller uses context memory to track connection */ 832 /* information for L2 and higher network protocols. */ 833 /* */ 834 /* Returns: */ 835 /* Nothing. */ 836 /****************************************************************************/ 837 void 838 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, 839 u_int32_t val) 840 { 841 842 DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 843 "val = 0x%08X\n", __func__, cid_addr, offset, val); 844 845 offset += cid_addr; 846 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 847 REG_WR(sc, BNX_CTX_DATA, val); 848 } 849 850 /****************************************************************************/ 851 /* PHY register read. */ 852 /* */ 853 /* Implements register reads on the MII bus. */ 854 /* */ 855 /* Returns: */ 856 /* The value of the register. */ 857 /****************************************************************************/ 858 int 859 bnx_miibus_read_reg(device_t dev, int phy, int reg) 860 { 861 struct bnx_softc *sc = device_private(dev); 862 u_int32_t val; 863 int i; 864 865 /* Make sure we are accessing the correct PHY address. */ 866 if (phy != sc->bnx_phy_addr) { 867 DBPRINT(sc, BNX_VERBOSE, 868 "Invalid PHY address %d for PHY read!\n", phy); 869 return(0); 870 } 871 872 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 873 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 874 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 875 876 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 877 REG_RD(sc, BNX_EMAC_MDIO_MODE); 878 879 DELAY(40); 880 } 881 882 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 883 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 884 BNX_EMAC_MDIO_COMM_START_BUSY; 885 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 886 887 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 888 DELAY(10); 889 890 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 891 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 892 DELAY(5); 893 894 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 895 val &= BNX_EMAC_MDIO_COMM_DATA; 896 897 break; 898 } 899 } 900 901 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 902 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 903 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 904 val = 0x0; 905 } else 906 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 907 908 DBPRINT(sc, BNX_EXCESSIVE, 909 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 910 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 911 912 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 913 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 914 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 915 916 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 917 REG_RD(sc, BNX_EMAC_MDIO_MODE); 918 919 DELAY(40); 920 } 921 922 return (val & 0xffff); 923 } 924 925 /****************************************************************************/ 926 /* PHY register write. */ 927 /* */ 928 /* Implements register writes on the MII bus. */ 929 /* */ 930 /* Returns: */ 931 /* The value of the register. */ 932 /****************************************************************************/ 933 void 934 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 935 { 936 struct bnx_softc *sc = device_private(dev); 937 u_int32_t val1; 938 int i; 939 940 /* Make sure we are accessing the correct PHY address. */ 941 if (phy != sc->bnx_phy_addr) { 942 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 943 phy); 944 return; 945 } 946 947 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 948 "val = 0x%04X\n", __func__, 949 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 950 951 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 952 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 953 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 954 955 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 956 REG_RD(sc, BNX_EMAC_MDIO_MODE); 957 958 DELAY(40); 959 } 960 961 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 962 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 963 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 964 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 965 966 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 967 DELAY(10); 968 969 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 970 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 971 DELAY(5); 972 break; 973 } 974 } 975 976 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 977 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 978 __LINE__); 979 } 980 981 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 982 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 983 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 984 985 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 986 REG_RD(sc, BNX_EMAC_MDIO_MODE); 987 988 DELAY(40); 989 } 990 } 991 992 /****************************************************************************/ 993 /* MII bus status change. */ 994 /* */ 995 /* Called by the MII bus driver when the PHY establishes link to set the */ 996 /* MAC interface registers. */ 997 /* */ 998 /* Returns: */ 999 /* Nothing. */ 1000 /****************************************************************************/ 1001 void 1002 bnx_miibus_statchg(device_t dev) 1003 { 1004 struct bnx_softc *sc = device_private(dev); 1005 struct mii_data *mii = &sc->bnx_mii; 1006 1007 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT); 1008 1009 /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ 1010 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 1011 DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n"); 1012 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII); 1013 } else { 1014 DBPRINT(sc, BNX_INFO, "Setting MII interface.\n"); 1015 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII); 1016 } 1017 1018 /* Set half or full duplex based on the duplicity 1019 * negotiated by the PHY. 1020 */ 1021 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1022 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1023 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1024 } else { 1025 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1026 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1027 } 1028 } 1029 1030 /****************************************************************************/ 1031 /* Acquire NVRAM lock. */ 1032 /* */ 1033 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1034 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1035 /* for use by the driver. */ 1036 /* */ 1037 /* Returns: */ 1038 /* 0 on success, positive value on failure. */ 1039 /****************************************************************************/ 1040 int 1041 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1042 { 1043 u_int32_t val; 1044 int j; 1045 1046 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1047 1048 /* Request access to the flash interface. */ 1049 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1050 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1051 val = REG_RD(sc, BNX_NVM_SW_ARB); 1052 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1053 break; 1054 1055 DELAY(5); 1056 } 1057 1058 if (j >= NVRAM_TIMEOUT_COUNT) { 1059 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1060 return (EBUSY); 1061 } 1062 1063 return (0); 1064 } 1065 1066 /****************************************************************************/ 1067 /* Release NVRAM lock. */ 1068 /* */ 1069 /* When the caller is finished accessing NVRAM the lock must be released. */ 1070 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1071 /* for use by the driver. */ 1072 /* */ 1073 /* Returns: */ 1074 /* 0 on success, positive value on failure. */ 1075 /****************************************************************************/ 1076 int 1077 bnx_release_nvram_lock(struct bnx_softc *sc) 1078 { 1079 int j; 1080 u_int32_t val; 1081 1082 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1083 1084 /* Relinquish nvram interface. */ 1085 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1086 1087 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1088 val = REG_RD(sc, BNX_NVM_SW_ARB); 1089 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1090 break; 1091 1092 DELAY(5); 1093 } 1094 1095 if (j >= NVRAM_TIMEOUT_COUNT) { 1096 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1097 return (EBUSY); 1098 } 1099 1100 return (0); 1101 } 1102 1103 #ifdef BNX_NVRAM_WRITE_SUPPORT 1104 /****************************************************************************/ 1105 /* Enable NVRAM write access. */ 1106 /* */ 1107 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1108 /* */ 1109 /* Returns: */ 1110 /* 0 on success, positive value on failure. */ 1111 /****************************************************************************/ 1112 int 1113 bnx_enable_nvram_write(struct bnx_softc *sc) 1114 { 1115 u_int32_t val; 1116 1117 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1118 1119 val = REG_RD(sc, BNX_MISC_CFG); 1120 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1121 1122 if (!sc->bnx_flash_info->buffered) { 1123 int j; 1124 1125 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1126 REG_WR(sc, BNX_NVM_COMMAND, 1127 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1128 1129 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1130 DELAY(5); 1131 1132 val = REG_RD(sc, BNX_NVM_COMMAND); 1133 if (val & BNX_NVM_COMMAND_DONE) 1134 break; 1135 } 1136 1137 if (j >= NVRAM_TIMEOUT_COUNT) { 1138 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1139 return (EBUSY); 1140 } 1141 } 1142 1143 return (0); 1144 } 1145 1146 /****************************************************************************/ 1147 /* Disable NVRAM write access. */ 1148 /* */ 1149 /* When the caller is finished writing to NVRAM write access must be */ 1150 /* disabled. */ 1151 /* */ 1152 /* Returns: */ 1153 /* Nothing. */ 1154 /****************************************************************************/ 1155 void 1156 bnx_disable_nvram_write(struct bnx_softc *sc) 1157 { 1158 u_int32_t val; 1159 1160 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1161 1162 val = REG_RD(sc, BNX_MISC_CFG); 1163 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1164 } 1165 #endif 1166 1167 /****************************************************************************/ 1168 /* Enable NVRAM access. */ 1169 /* */ 1170 /* Before accessing NVRAM for read or write operations the caller must */ 1171 /* enabled NVRAM access. */ 1172 /* */ 1173 /* Returns: */ 1174 /* Nothing. */ 1175 /****************************************************************************/ 1176 void 1177 bnx_enable_nvram_access(struct bnx_softc *sc) 1178 { 1179 u_int32_t val; 1180 1181 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1182 1183 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1184 /* Enable both bits, even on read. */ 1185 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1186 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1187 } 1188 1189 /****************************************************************************/ 1190 /* Disable NVRAM access. */ 1191 /* */ 1192 /* When the caller is finished accessing NVRAM access must be disabled. */ 1193 /* */ 1194 /* Returns: */ 1195 /* Nothing. */ 1196 /****************************************************************************/ 1197 void 1198 bnx_disable_nvram_access(struct bnx_softc *sc) 1199 { 1200 u_int32_t val; 1201 1202 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1203 1204 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1205 1206 /* Disable both bits, even after read. */ 1207 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1208 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1209 } 1210 1211 #ifdef BNX_NVRAM_WRITE_SUPPORT 1212 /****************************************************************************/ 1213 /* Erase NVRAM page before writing. */ 1214 /* */ 1215 /* Non-buffered flash parts require that a page be erased before it is */ 1216 /* written. */ 1217 /* */ 1218 /* Returns: */ 1219 /* 0 on success, positive value on failure. */ 1220 /****************************************************************************/ 1221 int 1222 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1223 { 1224 u_int32_t cmd; 1225 int j; 1226 1227 /* Buffered flash doesn't require an erase. */ 1228 if (sc->bnx_flash_info->buffered) 1229 return (0); 1230 1231 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1232 1233 /* Build an erase command. */ 1234 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1235 BNX_NVM_COMMAND_DOIT; 1236 1237 /* 1238 * Clear the DONE bit separately, set the NVRAM adress to erase, 1239 * and issue the erase command. 1240 */ 1241 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1242 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1243 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1244 1245 /* Wait for completion. */ 1246 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1247 u_int32_t val; 1248 1249 DELAY(5); 1250 1251 val = REG_RD(sc, BNX_NVM_COMMAND); 1252 if (val & BNX_NVM_COMMAND_DONE) 1253 break; 1254 } 1255 1256 if (j >= NVRAM_TIMEOUT_COUNT) { 1257 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1258 return (EBUSY); 1259 } 1260 1261 return (0); 1262 } 1263 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1264 1265 /****************************************************************************/ 1266 /* Read a dword (32 bits) from NVRAM. */ 1267 /* */ 1268 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1269 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1270 /* */ 1271 /* Returns: */ 1272 /* 0 on success and the 32 bit value read, positive value on failure. */ 1273 /****************************************************************************/ 1274 int 1275 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1276 u_int8_t *ret_val, u_int32_t cmd_flags) 1277 { 1278 u_int32_t cmd; 1279 int i, rc = 0; 1280 1281 /* Build the command word. */ 1282 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1283 1284 /* Calculate the offset for buffered flash. */ 1285 if (sc->bnx_flash_info->buffered) 1286 offset = ((offset / sc->bnx_flash_info->page_size) << 1287 sc->bnx_flash_info->page_bits) + 1288 (offset % sc->bnx_flash_info->page_size); 1289 1290 /* 1291 * Clear the DONE bit separately, set the address to read, 1292 * and issue the read. 1293 */ 1294 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1295 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1296 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1297 1298 /* Wait for completion. */ 1299 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1300 u_int32_t val; 1301 1302 DELAY(5); 1303 1304 val = REG_RD(sc, BNX_NVM_COMMAND); 1305 if (val & BNX_NVM_COMMAND_DONE) { 1306 val = REG_RD(sc, BNX_NVM_READ); 1307 1308 val = bnx_be32toh(val); 1309 memcpy(ret_val, &val, 4); 1310 break; 1311 } 1312 } 1313 1314 /* Check for errors. */ 1315 if (i >= NVRAM_TIMEOUT_COUNT) { 1316 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1317 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1318 rc = EBUSY; 1319 } 1320 1321 return(rc); 1322 } 1323 1324 #ifdef BNX_NVRAM_WRITE_SUPPORT 1325 /****************************************************************************/ 1326 /* Write a dword (32 bits) to NVRAM. */ 1327 /* */ 1328 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1329 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1330 /* enabled NVRAM write access. */ 1331 /* */ 1332 /* Returns: */ 1333 /* 0 on success, positive value on failure. */ 1334 /****************************************************************************/ 1335 int 1336 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1337 u_int32_t cmd_flags) 1338 { 1339 u_int32_t cmd, val32; 1340 int j; 1341 1342 /* Build the command word. */ 1343 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1344 1345 /* Calculate the offset for buffered flash. */ 1346 if (sc->bnx_flash_info->buffered) 1347 offset = ((offset / sc->bnx_flash_info->page_size) << 1348 sc->bnx_flash_info->page_bits) + 1349 (offset % sc->bnx_flash_info->page_size); 1350 1351 /* 1352 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1353 * set the NVRAM address to write, and issue the write command 1354 */ 1355 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1356 memcpy(&val32, val, 4); 1357 val32 = htobe32(val32); 1358 REG_WR(sc, BNX_NVM_WRITE, val32); 1359 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1360 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1361 1362 /* Wait for completion. */ 1363 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1364 DELAY(5); 1365 1366 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1367 break; 1368 } 1369 if (j >= NVRAM_TIMEOUT_COUNT) { 1370 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1371 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1372 return (EBUSY); 1373 } 1374 1375 return (0); 1376 } 1377 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1378 1379 /****************************************************************************/ 1380 /* Initialize NVRAM access. */ 1381 /* */ 1382 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1383 /* access that device. */ 1384 /* */ 1385 /* Returns: */ 1386 /* 0 on success, positive value on failure. */ 1387 /****************************************************************************/ 1388 int 1389 bnx_init_nvram(struct bnx_softc *sc) 1390 { 1391 u_int32_t val; 1392 int j, entry_count, rc; 1393 struct flash_spec *flash; 1394 1395 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1396 1397 /* Determine the selected interface. */ 1398 val = REG_RD(sc, BNX_NVM_CFG1); 1399 1400 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1401 1402 rc = 0; 1403 1404 /* 1405 * Flash reconfiguration is required to support additional 1406 * NVRAM devices not directly supported in hardware. 1407 * Check if the flash interface was reconfigured 1408 * by the bootcode. 1409 */ 1410 1411 if (val & 0x40000000) { 1412 /* Flash interface reconfigured by bootcode. */ 1413 1414 DBPRINT(sc,BNX_INFO_LOAD, 1415 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1416 1417 for (j = 0, flash = &flash_table[0]; j < entry_count; 1418 j++, flash++) { 1419 if ((val & FLASH_BACKUP_STRAP_MASK) == 1420 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1421 sc->bnx_flash_info = flash; 1422 break; 1423 } 1424 } 1425 } else { 1426 /* Flash interface not yet reconfigured. */ 1427 u_int32_t mask; 1428 1429 DBPRINT(sc,BNX_INFO_LOAD, 1430 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1431 1432 if (val & (1 << 23)) 1433 mask = FLASH_BACKUP_STRAP_MASK; 1434 else 1435 mask = FLASH_STRAP_MASK; 1436 1437 /* Look for the matching NVRAM device configuration data. */ 1438 for (j = 0, flash = &flash_table[0]; j < entry_count; 1439 j++, flash++) { 1440 /* Check if the dev matches any of the known devices. */ 1441 if ((val & mask) == (flash->strapping & mask)) { 1442 /* Found a device match. */ 1443 sc->bnx_flash_info = flash; 1444 1445 /* Request access to the flash interface. */ 1446 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1447 return (rc); 1448 1449 /* Reconfigure the flash interface. */ 1450 bnx_enable_nvram_access(sc); 1451 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1452 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1453 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1454 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1455 bnx_disable_nvram_access(sc); 1456 bnx_release_nvram_lock(sc); 1457 1458 break; 1459 } 1460 } 1461 } 1462 1463 /* Check if a matching device was found. */ 1464 if (j == entry_count) { 1465 sc->bnx_flash_info = NULL; 1466 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1467 __FILE__, __LINE__); 1468 rc = ENODEV; 1469 } 1470 1471 /* Write the flash config data to the shared memory interface. */ 1472 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1473 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1474 if (val) 1475 sc->bnx_flash_size = val; 1476 else 1477 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1478 1479 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1480 "0x%08X\n", sc->bnx_flash_info->total_size); 1481 1482 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1483 1484 return (rc); 1485 } 1486 1487 /****************************************************************************/ 1488 /* Read an arbitrary range of data from NVRAM. */ 1489 /* */ 1490 /* Prepares the NVRAM interface for access and reads the requested data */ 1491 /* into the supplied buffer. */ 1492 /* */ 1493 /* Returns: */ 1494 /* 0 on success and the data read, positive value on failure. */ 1495 /****************************************************************************/ 1496 int 1497 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1498 int buf_size) 1499 { 1500 int rc = 0; 1501 u_int32_t cmd_flags, offset32, len32, extra; 1502 1503 if (buf_size == 0) 1504 return (0); 1505 1506 /* Request access to the flash interface. */ 1507 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1508 return (rc); 1509 1510 /* Enable access to flash interface */ 1511 bnx_enable_nvram_access(sc); 1512 1513 len32 = buf_size; 1514 offset32 = offset; 1515 extra = 0; 1516 1517 cmd_flags = 0; 1518 1519 if (offset32 & 3) { 1520 u_int8_t buf[4]; 1521 u_int32_t pre_len; 1522 1523 offset32 &= ~3; 1524 pre_len = 4 - (offset & 3); 1525 1526 if (pre_len >= len32) { 1527 pre_len = len32; 1528 cmd_flags = 1529 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1530 } else 1531 cmd_flags = BNX_NVM_COMMAND_FIRST; 1532 1533 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1534 1535 if (rc) 1536 return (rc); 1537 1538 memcpy(ret_buf, buf + (offset & 3), pre_len); 1539 1540 offset32 += 4; 1541 ret_buf += pre_len; 1542 len32 -= pre_len; 1543 } 1544 1545 if (len32 & 3) { 1546 extra = 4 - (len32 & 3); 1547 len32 = (len32 + 4) & ~3; 1548 } 1549 1550 if (len32 == 4) { 1551 u_int8_t buf[4]; 1552 1553 if (cmd_flags) 1554 cmd_flags = BNX_NVM_COMMAND_LAST; 1555 else 1556 cmd_flags = 1557 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1558 1559 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1560 1561 memcpy(ret_buf, buf, 4 - extra); 1562 } else if (len32 > 0) { 1563 u_int8_t buf[4]; 1564 1565 /* Read the first word. */ 1566 if (cmd_flags) 1567 cmd_flags = 0; 1568 else 1569 cmd_flags = BNX_NVM_COMMAND_FIRST; 1570 1571 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1572 1573 /* Advance to the next dword. */ 1574 offset32 += 4; 1575 ret_buf += 4; 1576 len32 -= 4; 1577 1578 while (len32 > 4 && rc == 0) { 1579 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1580 1581 /* Advance to the next dword. */ 1582 offset32 += 4; 1583 ret_buf += 4; 1584 len32 -= 4; 1585 } 1586 1587 if (rc) 1588 return (rc); 1589 1590 cmd_flags = BNX_NVM_COMMAND_LAST; 1591 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1592 1593 memcpy(ret_buf, buf, 4 - extra); 1594 } 1595 1596 /* Disable access to flash interface and release the lock. */ 1597 bnx_disable_nvram_access(sc); 1598 bnx_release_nvram_lock(sc); 1599 1600 return (rc); 1601 } 1602 1603 #ifdef BNX_NVRAM_WRITE_SUPPORT 1604 /****************************************************************************/ 1605 /* Write an arbitrary range of data from NVRAM. */ 1606 /* */ 1607 /* Prepares the NVRAM interface for write access and writes the requested */ 1608 /* data from the supplied buffer. The caller is responsible for */ 1609 /* calculating any appropriate CRCs. */ 1610 /* */ 1611 /* Returns: */ 1612 /* 0 on success, positive value on failure. */ 1613 /****************************************************************************/ 1614 int 1615 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1616 int buf_size) 1617 { 1618 u_int32_t written, offset32, len32; 1619 u_int8_t *buf, start[4], end[4]; 1620 int rc = 0; 1621 int align_start, align_end; 1622 1623 buf = data_buf; 1624 offset32 = offset; 1625 len32 = buf_size; 1626 align_start = align_end = 0; 1627 1628 if ((align_start = (offset32 & 3))) { 1629 offset32 &= ~3; 1630 len32 += align_start; 1631 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1632 return (rc); 1633 } 1634 1635 if (len32 & 3) { 1636 if ((len32 > 4) || !align_start) { 1637 align_end = 4 - (len32 & 3); 1638 len32 += align_end; 1639 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1640 end, 4))) { 1641 return (rc); 1642 } 1643 } 1644 } 1645 1646 if (align_start || align_end) { 1647 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1648 if (buf == 0) 1649 return (ENOMEM); 1650 1651 if (align_start) 1652 memcpy(buf, start, 4); 1653 1654 if (align_end) 1655 memcpy(buf + len32 - 4, end, 4); 1656 1657 memcpy(buf + align_start, data_buf, buf_size); 1658 } 1659 1660 written = 0; 1661 while ((written < len32) && (rc == 0)) { 1662 u_int32_t page_start, page_end, data_start, data_end; 1663 u_int32_t addr, cmd_flags; 1664 int i; 1665 u_int8_t flash_buffer[264]; 1666 1667 /* Find the page_start addr */ 1668 page_start = offset32 + written; 1669 page_start -= (page_start % sc->bnx_flash_info->page_size); 1670 /* Find the page_end addr */ 1671 page_end = page_start + sc->bnx_flash_info->page_size; 1672 /* Find the data_start addr */ 1673 data_start = (written == 0) ? offset32 : page_start; 1674 /* Find the data_end addr */ 1675 data_end = (page_end > offset32 + len32) ? 1676 (offset32 + len32) : page_end; 1677 1678 /* Request access to the flash interface. */ 1679 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1680 goto nvram_write_end; 1681 1682 /* Enable access to flash interface */ 1683 bnx_enable_nvram_access(sc); 1684 1685 cmd_flags = BNX_NVM_COMMAND_FIRST; 1686 if (sc->bnx_flash_info->buffered == 0) { 1687 int j; 1688 1689 /* Read the whole page into the buffer 1690 * (non-buffer flash only) */ 1691 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1692 if (j == (sc->bnx_flash_info->page_size - 4)) 1693 cmd_flags |= BNX_NVM_COMMAND_LAST; 1694 1695 rc = bnx_nvram_read_dword(sc, 1696 page_start + j, 1697 &flash_buffer[j], 1698 cmd_flags); 1699 1700 if (rc) 1701 goto nvram_write_end; 1702 1703 cmd_flags = 0; 1704 } 1705 } 1706 1707 /* Enable writes to flash interface (unlock write-protect) */ 1708 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1709 goto nvram_write_end; 1710 1711 /* Erase the page */ 1712 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1713 goto nvram_write_end; 1714 1715 /* Re-enable the write again for the actual write */ 1716 bnx_enable_nvram_write(sc); 1717 1718 /* Loop to write back the buffer data from page_start to 1719 * data_start */ 1720 i = 0; 1721 if (sc->bnx_flash_info->buffered == 0) { 1722 for (addr = page_start; addr < data_start; 1723 addr += 4, i += 4) { 1724 1725 rc = bnx_nvram_write_dword(sc, addr, 1726 &flash_buffer[i], cmd_flags); 1727 1728 if (rc != 0) 1729 goto nvram_write_end; 1730 1731 cmd_flags = 0; 1732 } 1733 } 1734 1735 /* Loop to write the new data from data_start to data_end */ 1736 for (addr = data_start; addr < data_end; addr += 4, i++) { 1737 if ((addr == page_end - 4) || 1738 ((sc->bnx_flash_info->buffered) && 1739 (addr == data_end - 4))) { 1740 1741 cmd_flags |= BNX_NVM_COMMAND_LAST; 1742 } 1743 1744 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1745 1746 if (rc != 0) 1747 goto nvram_write_end; 1748 1749 cmd_flags = 0; 1750 buf += 4; 1751 } 1752 1753 /* Loop to write back the buffer data from data_end 1754 * to page_end */ 1755 if (sc->bnx_flash_info->buffered == 0) { 1756 for (addr = data_end; addr < page_end; 1757 addr += 4, i += 4) { 1758 1759 if (addr == page_end-4) 1760 cmd_flags = BNX_NVM_COMMAND_LAST; 1761 1762 rc = bnx_nvram_write_dword(sc, addr, 1763 &flash_buffer[i], cmd_flags); 1764 1765 if (rc != 0) 1766 goto nvram_write_end; 1767 1768 cmd_flags = 0; 1769 } 1770 } 1771 1772 /* Disable writes to flash interface (lock write-protect) */ 1773 bnx_disable_nvram_write(sc); 1774 1775 /* Disable access to flash interface */ 1776 bnx_disable_nvram_access(sc); 1777 bnx_release_nvram_lock(sc); 1778 1779 /* Increment written */ 1780 written += data_end - data_start; 1781 } 1782 1783 nvram_write_end: 1784 if (align_start || align_end) 1785 free(buf, M_DEVBUF); 1786 1787 return (rc); 1788 } 1789 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1790 1791 /****************************************************************************/ 1792 /* Verifies that NVRAM is accessible and contains valid data. */ 1793 /* */ 1794 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1795 /* correct. */ 1796 /* */ 1797 /* Returns: */ 1798 /* 0 on success, positive value on failure. */ 1799 /****************************************************************************/ 1800 int 1801 bnx_nvram_test(struct bnx_softc *sc) 1802 { 1803 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1804 u_int8_t *data = (u_int8_t *) buf; 1805 int rc = 0; 1806 u_int32_t magic, csum; 1807 1808 /* 1809 * Check that the device NVRAM is valid by reading 1810 * the magic value at offset 0. 1811 */ 1812 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1813 goto bnx_nvram_test_done; 1814 1815 magic = bnx_be32toh(buf[0]); 1816 if (magic != BNX_NVRAM_MAGIC) { 1817 rc = ENODEV; 1818 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1819 "Expected: 0x%08X, Found: 0x%08X\n", 1820 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1821 goto bnx_nvram_test_done; 1822 } 1823 1824 /* 1825 * Verify that the device NVRAM includes valid 1826 * configuration data. 1827 */ 1828 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1829 goto bnx_nvram_test_done; 1830 1831 csum = ether_crc32_le(data, 0x100); 1832 if (csum != BNX_CRC32_RESIDUAL) { 1833 rc = ENODEV; 1834 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1835 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1836 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1837 goto bnx_nvram_test_done; 1838 } 1839 1840 csum = ether_crc32_le(data + 0x100, 0x100); 1841 if (csum != BNX_CRC32_RESIDUAL) { 1842 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1843 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1844 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1845 rc = ENODEV; 1846 } 1847 1848 bnx_nvram_test_done: 1849 return (rc); 1850 } 1851 1852 /****************************************************************************/ 1853 /* Free any DMA memory owned by the driver. */ 1854 /* */ 1855 /* Scans through each data structre that requires DMA memory and frees */ 1856 /* the memory if allocated. */ 1857 /* */ 1858 /* Returns: */ 1859 /* Nothing. */ 1860 /****************************************************************************/ 1861 void 1862 bnx_dma_free(struct bnx_softc *sc) 1863 { 1864 int i; 1865 1866 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1867 1868 /* Destroy the status block. */ 1869 if (sc->status_block != NULL && sc->status_map != NULL) { 1870 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 1871 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 1872 BNX_STATUS_BLK_SZ); 1873 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 1874 sc->status_rseg); 1875 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 1876 sc->status_block = NULL; 1877 sc->status_map = NULL; 1878 } 1879 1880 /* Destroy the statistics block. */ 1881 if (sc->stats_block != NULL && sc->stats_map != NULL) { 1882 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 1883 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 1884 BNX_STATS_BLK_SZ); 1885 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 1886 sc->stats_rseg); 1887 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 1888 sc->stats_block = NULL; 1889 sc->stats_map = NULL; 1890 } 1891 1892 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 1893 for (i = 0; i < TX_PAGES; i++ ) { 1894 if (sc->tx_bd_chain[i] != NULL && 1895 sc->tx_bd_chain_map[i] != NULL) { 1896 bus_dmamap_unload(sc->bnx_dmatag, 1897 sc->tx_bd_chain_map[i]); 1898 bus_dmamem_unmap(sc->bnx_dmatag, 1899 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 1900 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 1901 sc->tx_bd_chain_rseg[i]); 1902 bus_dmamap_destroy(sc->bnx_dmatag, 1903 sc->tx_bd_chain_map[i]); 1904 sc->tx_bd_chain[i] = NULL; 1905 sc->tx_bd_chain_map[i] = NULL; 1906 } 1907 } 1908 1909 /* Unload and destroy the TX mbuf maps. */ 1910 for (i = 0; i < TOTAL_TX_BD; i++) { 1911 if (sc->tx_mbuf_map[i] != NULL) { 1912 bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1913 bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1914 } 1915 } 1916 1917 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 1918 for (i = 0; i < RX_PAGES; i++ ) { 1919 if (sc->rx_bd_chain[i] != NULL && 1920 sc->rx_bd_chain_map[i] != NULL) { 1921 bus_dmamap_unload(sc->bnx_dmatag, 1922 sc->rx_bd_chain_map[i]); 1923 bus_dmamem_unmap(sc->bnx_dmatag, 1924 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 1925 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 1926 sc->rx_bd_chain_rseg[i]); 1927 1928 bus_dmamap_destroy(sc->bnx_dmatag, 1929 sc->rx_bd_chain_map[i]); 1930 sc->rx_bd_chain[i] = NULL; 1931 sc->rx_bd_chain_map[i] = NULL; 1932 } 1933 } 1934 1935 /* Unload and destroy the RX mbuf maps. */ 1936 for (i = 0; i < TOTAL_RX_BD; i++) { 1937 if (sc->rx_mbuf_map[i] != NULL) { 1938 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1939 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1940 } 1941 } 1942 1943 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1944 } 1945 1946 /****************************************************************************/ 1947 /* Allocate any DMA memory needed by the driver. */ 1948 /* */ 1949 /* Allocates DMA memory needed for the various global structures needed by */ 1950 /* hardware. */ 1951 /* */ 1952 /* Returns: */ 1953 /* 0 for success, positive value for failure. */ 1954 /****************************************************************************/ 1955 int 1956 bnx_dma_alloc(struct bnx_softc *sc) 1957 { 1958 int i, rc = 0; 1959 1960 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1961 1962 /* 1963 * Allocate DMA memory for the status block, map the memory into DMA 1964 * space, and fetch the physical address of the block. 1965 */ 1966 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 1967 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 1968 aprint_error_dev(sc->bnx_dev, 1969 "Could not create status block DMA map!\n"); 1970 rc = ENOMEM; 1971 goto bnx_dma_alloc_exit; 1972 } 1973 1974 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1975 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 1976 &sc->status_rseg, BUS_DMA_NOWAIT)) { 1977 aprint_error_dev(sc->bnx_dev, 1978 "Could not allocate status block DMA memory!\n"); 1979 rc = ENOMEM; 1980 goto bnx_dma_alloc_exit; 1981 } 1982 1983 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 1984 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 1985 aprint_error_dev(sc->bnx_dev, 1986 "Could not map status block DMA memory!\n"); 1987 rc = ENOMEM; 1988 goto bnx_dma_alloc_exit; 1989 } 1990 1991 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 1992 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 1993 aprint_error_dev(sc->bnx_dev, 1994 "Could not load status block DMA memory!\n"); 1995 rc = ENOMEM; 1996 goto bnx_dma_alloc_exit; 1997 } 1998 1999 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2000 bzero(sc->status_block, BNX_STATUS_BLK_SZ); 2001 2002 /* DRC - Fix for 64 bit addresses. */ 2003 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2004 (u_int32_t) sc->status_block_paddr); 2005 2006 /* 2007 * Allocate DMA memory for the statistics block, map the memory into 2008 * DMA space, and fetch the physical address of the block. 2009 */ 2010 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2011 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2012 aprint_error_dev(sc->bnx_dev, 2013 "Could not create stats block DMA map!\n"); 2014 rc = ENOMEM; 2015 goto bnx_dma_alloc_exit; 2016 } 2017 2018 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2019 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2020 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2021 aprint_error_dev(sc->bnx_dev, 2022 "Could not allocate stats block DMA memory!\n"); 2023 rc = ENOMEM; 2024 goto bnx_dma_alloc_exit; 2025 } 2026 2027 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2028 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2029 aprint_error_dev(sc->bnx_dev, 2030 "Could not map stats block DMA memory!\n"); 2031 rc = ENOMEM; 2032 goto bnx_dma_alloc_exit; 2033 } 2034 2035 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2036 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2037 aprint_error_dev(sc->bnx_dev, 2038 "Could not load status block DMA memory!\n"); 2039 rc = ENOMEM; 2040 goto bnx_dma_alloc_exit; 2041 } 2042 2043 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2044 bzero(sc->stats_block, BNX_STATS_BLK_SZ); 2045 2046 /* DRC - Fix for 64 bit address. */ 2047 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2048 (u_int32_t) sc->stats_block_paddr); 2049 2050 /* 2051 * Allocate DMA memory for the TX buffer descriptor chain, 2052 * and fetch the physical address of the block. 2053 */ 2054 for (i = 0; i < TX_PAGES; i++) { 2055 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2056 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2057 &sc->tx_bd_chain_map[i])) { 2058 aprint_error_dev(sc->bnx_dev, 2059 "Could not create Tx desc %d DMA map!\n", i); 2060 rc = ENOMEM; 2061 goto bnx_dma_alloc_exit; 2062 } 2063 2064 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2065 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2066 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2067 aprint_error_dev(sc->bnx_dev, 2068 "Could not allocate TX desc %d DMA memory!\n", 2069 i); 2070 rc = ENOMEM; 2071 goto bnx_dma_alloc_exit; 2072 } 2073 2074 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2075 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2076 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2077 aprint_error_dev(sc->bnx_dev, 2078 "Could not map TX desc %d DMA memory!\n", i); 2079 rc = ENOMEM; 2080 goto bnx_dma_alloc_exit; 2081 } 2082 2083 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2084 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2085 BUS_DMA_NOWAIT)) { 2086 aprint_error_dev(sc->bnx_dev, 2087 "Could not load TX desc %d DMA memory!\n", i); 2088 rc = ENOMEM; 2089 goto bnx_dma_alloc_exit; 2090 } 2091 2092 sc->tx_bd_chain_paddr[i] = 2093 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2094 2095 /* DRC - Fix for 64 bit systems. */ 2096 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2097 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2098 } 2099 2100 /* 2101 * Create DMA maps for the TX buffer mbufs. 2102 */ 2103 for (i = 0; i < TOTAL_TX_BD; i++) { 2104 if (bus_dmamap_create(sc->bnx_dmatag, 2105 MCLBYTES * BNX_MAX_SEGMENTS, 2106 USABLE_TX_BD - BNX_TX_SLACK_SPACE, 2107 MCLBYTES, 0, BUS_DMA_NOWAIT, 2108 &sc->tx_mbuf_map[i])) { 2109 aprint_error_dev(sc->bnx_dev, 2110 "Could not create Tx mbuf %d DMA map!\n", i); 2111 rc = ENOMEM; 2112 goto bnx_dma_alloc_exit; 2113 } 2114 } 2115 2116 /* 2117 * Allocate DMA memory for the Rx buffer descriptor chain, 2118 * and fetch the physical address of the block. 2119 */ 2120 for (i = 0; i < RX_PAGES; i++) { 2121 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2122 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2123 &sc->rx_bd_chain_map[i])) { 2124 aprint_error_dev(sc->bnx_dev, 2125 "Could not create Rx desc %d DMA map!\n", i); 2126 rc = ENOMEM; 2127 goto bnx_dma_alloc_exit; 2128 } 2129 2130 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2131 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2132 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2133 aprint_error_dev(sc->bnx_dev, 2134 "Could not allocate Rx desc %d DMA memory!\n", i); 2135 rc = ENOMEM; 2136 goto bnx_dma_alloc_exit; 2137 } 2138 2139 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2140 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2141 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2142 aprint_error_dev(sc->bnx_dev, 2143 "Could not map Rx desc %d DMA memory!\n", i); 2144 rc = ENOMEM; 2145 goto bnx_dma_alloc_exit; 2146 } 2147 2148 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2149 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2150 BUS_DMA_NOWAIT)) { 2151 aprint_error_dev(sc->bnx_dev, 2152 "Could not load Rx desc %d DMA memory!\n", i); 2153 rc = ENOMEM; 2154 goto bnx_dma_alloc_exit; 2155 } 2156 2157 bzero(sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2158 sc->rx_bd_chain_paddr[i] = 2159 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2160 2161 /* DRC - Fix for 64 bit systems. */ 2162 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2163 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2164 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2165 0, BNX_RX_CHAIN_PAGE_SZ, 2166 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2167 } 2168 2169 /* 2170 * Create DMA maps for the Rx buffer mbufs. 2171 */ 2172 for (i = 0; i < TOTAL_RX_BD; i++) { 2173 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU, 2174 BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT, 2175 &sc->rx_mbuf_map[i])) { 2176 aprint_error_dev(sc->bnx_dev, 2177 "Could not create Rx mbuf %d DMA map!\n", i); 2178 rc = ENOMEM; 2179 goto bnx_dma_alloc_exit; 2180 } 2181 } 2182 2183 bnx_dma_alloc_exit: 2184 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2185 2186 return(rc); 2187 } 2188 2189 /****************************************************************************/ 2190 /* Release all resources used by the driver. */ 2191 /* */ 2192 /* Releases all resources acquired by the driver including interrupts, */ 2193 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2194 /* */ 2195 /* Returns: */ 2196 /* Nothing. */ 2197 /****************************************************************************/ 2198 void 2199 bnx_release_resources(struct bnx_softc *sc) 2200 { 2201 int i; 2202 struct pci_attach_args *pa = &(sc->bnx_pa); 2203 2204 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2205 2206 bnx_dma_free(sc); 2207 2208 if (sc->bnx_intrhand != NULL) 2209 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2210 2211 if (sc->bnx_size) 2212 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2213 2214 for (i = 0; i < TOTAL_RX_BD; i++) 2215 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2216 2217 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2218 } 2219 2220 /****************************************************************************/ 2221 /* Firmware synchronization. */ 2222 /* */ 2223 /* Before performing certain events such as a chip reset, synchronize with */ 2224 /* the firmware first. */ 2225 /* */ 2226 /* Returns: */ 2227 /* 0 for success, positive value for failure. */ 2228 /****************************************************************************/ 2229 int 2230 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2231 { 2232 int i, rc = 0; 2233 u_int32_t val; 2234 2235 /* Don't waste any time if we've timed out before. */ 2236 if (sc->bnx_fw_timed_out) { 2237 rc = EBUSY; 2238 goto bnx_fw_sync_exit; 2239 } 2240 2241 /* Increment the message sequence number. */ 2242 sc->bnx_fw_wr_seq++; 2243 msg_data |= sc->bnx_fw_wr_seq; 2244 2245 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2246 msg_data); 2247 2248 /* Send the message to the bootcode driver mailbox. */ 2249 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2250 2251 /* Wait for the bootcode to acknowledge the message. */ 2252 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2253 /* Check for a response in the bootcode firmware mailbox. */ 2254 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2255 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2256 break; 2257 DELAY(1000); 2258 } 2259 2260 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2261 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2262 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2263 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2264 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2265 2266 msg_data &= ~BNX_DRV_MSG_CODE; 2267 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2268 2269 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2270 2271 sc->bnx_fw_timed_out = 1; 2272 rc = EBUSY; 2273 } 2274 2275 bnx_fw_sync_exit: 2276 return (rc); 2277 } 2278 2279 /****************************************************************************/ 2280 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2281 /* */ 2282 /* Returns: */ 2283 /* Nothing. */ 2284 /****************************************************************************/ 2285 void 2286 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2287 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2288 { 2289 int i; 2290 u_int32_t val; 2291 2292 for (i = 0; i < rv2p_code_len; i += 8) { 2293 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2294 rv2p_code++; 2295 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2296 rv2p_code++; 2297 2298 if (rv2p_proc == RV2P_PROC1) { 2299 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2300 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2301 } 2302 else { 2303 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2304 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2305 } 2306 } 2307 2308 /* Reset the processor, un-stall is done later. */ 2309 if (rv2p_proc == RV2P_PROC1) 2310 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2311 else 2312 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2313 } 2314 2315 /****************************************************************************/ 2316 /* Load RISC processor firmware. */ 2317 /* */ 2318 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2319 /* associated with a particular processor. */ 2320 /* */ 2321 /* Returns: */ 2322 /* Nothing. */ 2323 /****************************************************************************/ 2324 void 2325 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2326 struct fw_info *fw) 2327 { 2328 u_int32_t offset; 2329 u_int32_t val; 2330 2331 /* Halt the CPU. */ 2332 val = REG_RD_IND(sc, cpu_reg->mode); 2333 val |= cpu_reg->mode_value_halt; 2334 REG_WR_IND(sc, cpu_reg->mode, val); 2335 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2336 2337 /* Load the Text area. */ 2338 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2339 if (fw->text) { 2340 int j; 2341 2342 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2343 REG_WR_IND(sc, offset, fw->text[j]); 2344 } 2345 2346 /* Load the Data area. */ 2347 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2348 if (fw->data) { 2349 int j; 2350 2351 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2352 REG_WR_IND(sc, offset, fw->data[j]); 2353 } 2354 2355 /* Load the SBSS area. */ 2356 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2357 if (fw->sbss) { 2358 int j; 2359 2360 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2361 REG_WR_IND(sc, offset, fw->sbss[j]); 2362 } 2363 2364 /* Load the BSS area. */ 2365 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2366 if (fw->bss) { 2367 int j; 2368 2369 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2370 REG_WR_IND(sc, offset, fw->bss[j]); 2371 } 2372 2373 /* Load the Read-Only area. */ 2374 offset = cpu_reg->spad_base + 2375 (fw->rodata_addr - cpu_reg->mips_view_base); 2376 if (fw->rodata) { 2377 int j; 2378 2379 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2380 REG_WR_IND(sc, offset, fw->rodata[j]); 2381 } 2382 2383 /* Clear the pre-fetch instruction. */ 2384 REG_WR_IND(sc, cpu_reg->inst, 0); 2385 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2386 2387 /* Start the CPU. */ 2388 val = REG_RD_IND(sc, cpu_reg->mode); 2389 val &= ~cpu_reg->mode_value_halt; 2390 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2391 REG_WR_IND(sc, cpu_reg->mode, val); 2392 } 2393 2394 /****************************************************************************/ 2395 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2396 /* */ 2397 /* Loads the firmware for each CPU and starts the CPU. */ 2398 /* */ 2399 /* Returns: */ 2400 /* Nothing. */ 2401 /****************************************************************************/ 2402 void 2403 bnx_init_cpus(struct bnx_softc *sc) 2404 { 2405 struct cpu_reg cpu_reg; 2406 struct fw_info fw; 2407 2408 /* Initialize the RV2P processor. */ 2409 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2410 RV2P_PROC1); 2411 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2412 RV2P_PROC2); 2413 2414 /* Initialize the RX Processor. */ 2415 cpu_reg.mode = BNX_RXP_CPU_MODE; 2416 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2417 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2418 cpu_reg.state = BNX_RXP_CPU_STATE; 2419 cpu_reg.state_value_clear = 0xffffff; 2420 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2421 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2422 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2423 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2424 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2425 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2426 cpu_reg.mips_view_base = 0x8000000; 2427 2428 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2429 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2430 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2431 fw.start_addr = bnx_RXP_b06FwStartAddr; 2432 2433 fw.text_addr = bnx_RXP_b06FwTextAddr; 2434 fw.text_len = bnx_RXP_b06FwTextLen; 2435 fw.text_index = 0; 2436 fw.text = bnx_RXP_b06FwText; 2437 2438 fw.data_addr = bnx_RXP_b06FwDataAddr; 2439 fw.data_len = bnx_RXP_b06FwDataLen; 2440 fw.data_index = 0; 2441 fw.data = bnx_RXP_b06FwData; 2442 2443 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2444 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2445 fw.sbss_index = 0; 2446 fw.sbss = bnx_RXP_b06FwSbss; 2447 2448 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2449 fw.bss_len = bnx_RXP_b06FwBssLen; 2450 fw.bss_index = 0; 2451 fw.bss = bnx_RXP_b06FwBss; 2452 2453 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2454 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2455 fw.rodata_index = 0; 2456 fw.rodata = bnx_RXP_b06FwRodata; 2457 2458 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2459 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2460 2461 /* Initialize the TX Processor. */ 2462 cpu_reg.mode = BNX_TXP_CPU_MODE; 2463 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2464 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2465 cpu_reg.state = BNX_TXP_CPU_STATE; 2466 cpu_reg.state_value_clear = 0xffffff; 2467 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2468 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2469 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2470 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2471 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2472 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2473 cpu_reg.mips_view_base = 0x8000000; 2474 2475 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2476 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2477 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2478 fw.start_addr = bnx_TXP_b06FwStartAddr; 2479 2480 fw.text_addr = bnx_TXP_b06FwTextAddr; 2481 fw.text_len = bnx_TXP_b06FwTextLen; 2482 fw.text_index = 0; 2483 fw.text = bnx_TXP_b06FwText; 2484 2485 fw.data_addr = bnx_TXP_b06FwDataAddr; 2486 fw.data_len = bnx_TXP_b06FwDataLen; 2487 fw.data_index = 0; 2488 fw.data = bnx_TXP_b06FwData; 2489 2490 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2491 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2492 fw.sbss_index = 0; 2493 fw.sbss = bnx_TXP_b06FwSbss; 2494 2495 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2496 fw.bss_len = bnx_TXP_b06FwBssLen; 2497 fw.bss_index = 0; 2498 fw.bss = bnx_TXP_b06FwBss; 2499 2500 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 2501 fw.rodata_len = bnx_TXP_b06FwRodataLen; 2502 fw.rodata_index = 0; 2503 fw.rodata = bnx_TXP_b06FwRodata; 2504 2505 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2506 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2507 2508 /* Initialize the TX Patch-up Processor. */ 2509 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2510 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2511 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2512 cpu_reg.state = BNX_TPAT_CPU_STATE; 2513 cpu_reg.state_value_clear = 0xffffff; 2514 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2515 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2516 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2517 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2518 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2519 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2520 cpu_reg.mips_view_base = 0x8000000; 2521 2522 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 2523 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 2524 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 2525 fw.start_addr = bnx_TPAT_b06FwStartAddr; 2526 2527 fw.text_addr = bnx_TPAT_b06FwTextAddr; 2528 fw.text_len = bnx_TPAT_b06FwTextLen; 2529 fw.text_index = 0; 2530 fw.text = bnx_TPAT_b06FwText; 2531 2532 fw.data_addr = bnx_TPAT_b06FwDataAddr; 2533 fw.data_len = bnx_TPAT_b06FwDataLen; 2534 fw.data_index = 0; 2535 fw.data = bnx_TPAT_b06FwData; 2536 2537 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 2538 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 2539 fw.sbss_index = 0; 2540 fw.sbss = bnx_TPAT_b06FwSbss; 2541 2542 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 2543 fw.bss_len = bnx_TPAT_b06FwBssLen; 2544 fw.bss_index = 0; 2545 fw.bss = bnx_TPAT_b06FwBss; 2546 2547 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 2548 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 2549 fw.rodata_index = 0; 2550 fw.rodata = bnx_TPAT_b06FwRodata; 2551 2552 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2553 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2554 2555 /* Initialize the Completion Processor. */ 2556 cpu_reg.mode = BNX_COM_CPU_MODE; 2557 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2558 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2559 cpu_reg.state = BNX_COM_CPU_STATE; 2560 cpu_reg.state_value_clear = 0xffffff; 2561 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2562 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2563 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2564 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2565 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2566 cpu_reg.spad_base = BNX_COM_SCRATCH; 2567 cpu_reg.mips_view_base = 0x8000000; 2568 2569 fw.ver_major = bnx_COM_b06FwReleaseMajor; 2570 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 2571 fw.ver_fix = bnx_COM_b06FwReleaseFix; 2572 fw.start_addr = bnx_COM_b06FwStartAddr; 2573 2574 fw.text_addr = bnx_COM_b06FwTextAddr; 2575 fw.text_len = bnx_COM_b06FwTextLen; 2576 fw.text_index = 0; 2577 fw.text = bnx_COM_b06FwText; 2578 2579 fw.data_addr = bnx_COM_b06FwDataAddr; 2580 fw.data_len = bnx_COM_b06FwDataLen; 2581 fw.data_index = 0; 2582 fw.data = bnx_COM_b06FwData; 2583 2584 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 2585 fw.sbss_len = bnx_COM_b06FwSbssLen; 2586 fw.sbss_index = 0; 2587 fw.sbss = bnx_COM_b06FwSbss; 2588 2589 fw.bss_addr = bnx_COM_b06FwBssAddr; 2590 fw.bss_len = bnx_COM_b06FwBssLen; 2591 fw.bss_index = 0; 2592 fw.bss = bnx_COM_b06FwBss; 2593 2594 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 2595 fw.rodata_len = bnx_COM_b06FwRodataLen; 2596 fw.rodata_index = 0; 2597 fw.rodata = bnx_COM_b06FwRodata; 2598 2599 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2600 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2601 } 2602 2603 /****************************************************************************/ 2604 /* Initialize context memory. */ 2605 /* */ 2606 /* Clears the memory associated with each Context ID (CID). */ 2607 /* */ 2608 /* Returns: */ 2609 /* Nothing. */ 2610 /****************************************************************************/ 2611 void 2612 bnx_init_context(struct bnx_softc *sc) 2613 { 2614 u_int32_t vcid; 2615 2616 vcid = 96; 2617 while (vcid) { 2618 u_int32_t vcid_addr, pcid_addr, offset; 2619 2620 vcid--; 2621 2622 vcid_addr = GET_CID_ADDR(vcid); 2623 pcid_addr = vcid_addr; 2624 2625 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); 2626 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2627 2628 /* Zero out the context. */ 2629 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2630 CTX_WR(sc, 0x00, offset, 0); 2631 2632 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 2633 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2634 } 2635 } 2636 2637 /****************************************************************************/ 2638 /* Fetch the permanent MAC address of the controller. */ 2639 /* */ 2640 /* Returns: */ 2641 /* Nothing. */ 2642 /****************************************************************************/ 2643 void 2644 bnx_get_mac_addr(struct bnx_softc *sc) 2645 { 2646 u_int32_t mac_lo = 0, mac_hi = 0; 2647 2648 /* 2649 * The NetXtreme II bootcode populates various NIC 2650 * power-on and runtime configuration items in a 2651 * shared memory area. The factory configured MAC 2652 * address is available from both NVRAM and the 2653 * shared memory area so we'll read the value from 2654 * shared memory for speed. 2655 */ 2656 2657 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 2658 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 2659 2660 if ((mac_lo == 0) && (mac_hi == 0)) { 2661 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 2662 __FILE__, __LINE__); 2663 } else { 2664 sc->eaddr[0] = (u_char)(mac_hi >> 8); 2665 sc->eaddr[1] = (u_char)(mac_hi >> 0); 2666 sc->eaddr[2] = (u_char)(mac_lo >> 24); 2667 sc->eaddr[3] = (u_char)(mac_lo >> 16); 2668 sc->eaddr[4] = (u_char)(mac_lo >> 8); 2669 sc->eaddr[5] = (u_char)(mac_lo >> 0); 2670 } 2671 2672 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 2673 "%s\n", ether_sprintf(sc->eaddr)); 2674 } 2675 2676 /****************************************************************************/ 2677 /* Program the MAC address. */ 2678 /* */ 2679 /* Returns: */ 2680 /* Nothing. */ 2681 /****************************************************************************/ 2682 void 2683 bnx_set_mac_addr(struct bnx_softc *sc) 2684 { 2685 u_int32_t val; 2686 const u_int8_t *mac_addr = CLLADDR(sc->ethercom.ec_if.if_sadl); 2687 2688 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 2689 "%s\n", ether_sprintf(sc->eaddr)); 2690 2691 val = (mac_addr[0] << 8) | mac_addr[1]; 2692 2693 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 2694 2695 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2696 (mac_addr[4] << 8) | mac_addr[5]; 2697 2698 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 2699 } 2700 2701 void 2702 bnx_if_stop(struct ifnet *ifp, int disable) 2703 { 2704 struct bnx_softc *sc = ifp->if_softc; 2705 2706 bnx_stop(sc); 2707 } 2708 2709 /****************************************************************************/ 2710 /* Stop the controller. */ 2711 /* */ 2712 /* Returns: */ 2713 /* Nothing. */ 2714 /****************************************************************************/ 2715 void 2716 bnx_stop(struct bnx_softc *sc) 2717 { 2718 struct ifnet *ifp = &sc->ethercom.ec_if; 2719 struct mii_data *mii = NULL; 2720 2721 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2722 2723 mii = &sc->bnx_mii; 2724 2725 callout_stop(&sc->bnx_timeout); 2726 2727 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2728 2729 /* Disable the transmit/receive blocks. */ 2730 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 2731 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2732 DELAY(20); 2733 2734 bnx_disable_intr(sc); 2735 2736 /* Tell firmware that the driver is going away. */ 2737 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 2738 2739 /* Free the RX lists. */ 2740 bnx_free_rx_chain(sc); 2741 2742 /* Free TX buffers. */ 2743 bnx_free_tx_chain(sc); 2744 2745 ifp->if_timer = 0; 2746 2747 sc->bnx_link = 0; 2748 2749 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2750 2751 } 2752 2753 int 2754 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 2755 { 2756 u_int32_t val; 2757 int i, rc = 0; 2758 2759 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2760 2761 /* Wait for pending PCI transactions to complete. */ 2762 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 2763 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 2764 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 2765 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 2766 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 2767 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2768 DELAY(5); 2769 2770 /* Assume bootcode is running. */ 2771 sc->bnx_fw_timed_out = 0; 2772 2773 /* Give the firmware a chance to prepare for the reset. */ 2774 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 2775 if (rc) 2776 goto bnx_reset_exit; 2777 2778 /* Set a firmware reminder that this is a soft reset. */ 2779 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 2780 BNX_DRV_RESET_SIGNATURE_MAGIC); 2781 2782 /* Dummy read to force the chip to complete all current transactions. */ 2783 val = REG_RD(sc, BNX_MISC_ID); 2784 2785 /* Chip reset. */ 2786 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2787 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 2788 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 2789 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 2790 2791 /* Allow up to 30us for reset to complete. */ 2792 for (i = 0; i < 10; i++) { 2793 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 2794 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2795 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 2796 break; 2797 2798 DELAY(10); 2799 } 2800 2801 /* Check that reset completed successfully. */ 2802 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2803 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 2804 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__); 2805 rc = EBUSY; 2806 goto bnx_reset_exit; 2807 } 2808 2809 /* Make sure byte swapping is properly configured. */ 2810 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 2811 if (val != 0x01020304) { 2812 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 2813 __FILE__, __LINE__); 2814 rc = ENODEV; 2815 goto bnx_reset_exit; 2816 } 2817 2818 /* Just completed a reset, assume that firmware is running again. */ 2819 sc->bnx_fw_timed_out = 0; 2820 2821 /* Wait for the firmware to finish its initialization. */ 2822 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 2823 if (rc) 2824 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 2825 "initialization!\n", __FILE__, __LINE__); 2826 2827 bnx_reset_exit: 2828 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2829 2830 return (rc); 2831 } 2832 2833 int 2834 bnx_chipinit(struct bnx_softc *sc) 2835 { 2836 struct pci_attach_args *pa = &(sc->bnx_pa); 2837 u_int32_t val; 2838 int rc = 0; 2839 2840 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2841 2842 /* Make sure the interrupt is not active. */ 2843 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 2844 2845 /* Initialize DMA byte/word swapping, configure the number of DMA */ 2846 /* channels and PCI clock compensation delay. */ 2847 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 2848 BNX_DMA_CONFIG_DATA_WORD_SWAP | 2849 #if BYTE_ORDER == BIG_ENDIAN 2850 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 2851 #endif 2852 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 2853 DMA_READ_CHANS << 12 | 2854 DMA_WRITE_CHANS << 16; 2855 2856 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 2857 2858 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 2859 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 2860 2861 /* 2862 * This setting resolves a problem observed on certain Intel PCI 2863 * chipsets that cannot handle multiple outstanding DMA operations. 2864 * See errata E9_5706A1_65. 2865 */ 2866 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 2867 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 2868 !(sc->bnx_flags & BNX_PCIX_FLAG)) 2869 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 2870 2871 REG_WR(sc, BNX_DMA_CONFIG, val); 2872 2873 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 2874 if (sc->bnx_flags & BNX_PCIX_FLAG) { 2875 u_int16_t nval; 2876 2877 nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 2878 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 2879 nval & ~0x2); 2880 } 2881 2882 /* Enable the RX_V2P and Context state machines before access. */ 2883 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 2884 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 2885 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 2886 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 2887 2888 /* Initialize context mapping and zero out the quick contexts. */ 2889 bnx_init_context(sc); 2890 2891 /* Initialize the on-boards CPUs */ 2892 bnx_init_cpus(sc); 2893 2894 /* Prepare NVRAM for access. */ 2895 if (bnx_init_nvram(sc)) { 2896 rc = ENODEV; 2897 goto bnx_chipinit_exit; 2898 } 2899 2900 /* Set the kernel bypass block size */ 2901 val = REG_RD(sc, BNX_MQ_CONFIG); 2902 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 2903 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 2904 REG_WR(sc, BNX_MQ_CONFIG, val); 2905 2906 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 2907 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 2908 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 2909 2910 val = (BCM_PAGE_BITS - 8) << 24; 2911 REG_WR(sc, BNX_RV2P_CONFIG, val); 2912 2913 /* Configure page size. */ 2914 val = REG_RD(sc, BNX_TBDR_CONFIG); 2915 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 2916 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 2917 REG_WR(sc, BNX_TBDR_CONFIG, val); 2918 2919 bnx_chipinit_exit: 2920 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2921 2922 return(rc); 2923 } 2924 2925 /****************************************************************************/ 2926 /* Initialize the controller in preparation to send/receive traffic. */ 2927 /* */ 2928 /* Returns: */ 2929 /* 0 for success, positive value for failure. */ 2930 /****************************************************************************/ 2931 int 2932 bnx_blockinit(struct bnx_softc *sc) 2933 { 2934 u_int32_t reg, val; 2935 int rc = 0; 2936 2937 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2938 2939 /* Load the hardware default MAC address. */ 2940 bnx_set_mac_addr(sc); 2941 2942 /* Set the Ethernet backoff seed value */ 2943 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 2944 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 2945 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 2946 2947 sc->last_status_idx = 0; 2948 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 2949 2950 /* Set up link change interrupt generation. */ 2951 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 2952 2953 /* Program the physical address of the status block. */ 2954 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 2955 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 2956 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 2957 2958 /* Program the physical address of the statistics block. */ 2959 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 2960 (u_int32_t)(sc->stats_block_paddr)); 2961 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 2962 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 2963 2964 /* Program various host coalescing parameters. */ 2965 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 2966 << 16) | sc->bnx_tx_quick_cons_trip); 2967 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 2968 << 16) | sc->bnx_rx_quick_cons_trip); 2969 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 2970 sc->bnx_comp_prod_trip); 2971 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 2972 sc->bnx_tx_ticks); 2973 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 2974 sc->bnx_rx_ticks); 2975 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 2976 sc->bnx_com_ticks); 2977 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 2978 sc->bnx_cmd_ticks); 2979 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 2980 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 2981 REG_WR(sc, BNX_HC_CONFIG, 2982 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 2983 BNX_HC_CONFIG_COLLECT_STATS)); 2984 2985 /* Clear the internal statistics counters. */ 2986 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 2987 2988 /* Verify that bootcode is running. */ 2989 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 2990 2991 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 2992 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 2993 __FILE__, __LINE__); reg = 0); 2994 2995 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 2996 BNX_DEV_INFO_SIGNATURE_MAGIC) { 2997 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 2998 "Expected: 08%08X\n", __FILE__, __LINE__, 2999 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3000 BNX_DEV_INFO_SIGNATURE_MAGIC); 3001 rc = ENODEV; 3002 goto bnx_blockinit_exit; 3003 } 3004 3005 /* Check if any management firmware is running. */ 3006 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3007 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3008 BNX_PORT_FEATURE_IMD_ENABLED)) { 3009 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3010 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3011 } 3012 3013 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3014 BNX_DEV_INFO_BC_REV); 3015 3016 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3017 3018 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3019 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3020 3021 /* Enable link state change interrupt generation. */ 3022 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3023 3024 /* Enable all remaining blocks in the MAC. */ 3025 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3026 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3027 DELAY(20); 3028 3029 bnx_blockinit_exit: 3030 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3031 3032 return (rc); 3033 } 3034 3035 /****************************************************************************/ 3036 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3037 /* */ 3038 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3039 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3040 /* necessary. */ 3041 /* */ 3042 /* Returns: */ 3043 /* 0 for success, positive value for failure. */ 3044 /****************************************************************************/ 3045 int 3046 bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod, 3047 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3048 { 3049 bus_dmamap_t map; 3050 struct mbuf *m_new = NULL; 3051 struct rx_bd *rxbd; 3052 int i, rc = 0; 3053 u_int32_t addr; 3054 #ifdef BNX_DEBUG 3055 u_int16_t debug_chain_prod = *chain_prod; 3056 #endif 3057 u_int16_t first_chain_prod; 3058 u_int16_t min_free_bd; 3059 3060 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3061 __func__); 3062 3063 /* Make sure the inputs are valid. */ 3064 DBRUNIF((*chain_prod > MAX_RX_BD), 3065 aprint_error_dev(sc->bnx_dev, 3066 "RX producer out of range: 0x%04X > 0x%04X\n", 3067 *chain_prod, (u_int16_t)MAX_RX_BD)); 3068 3069 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3070 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3071 *prod_bseq); 3072 3073 /* try to get in as many mbufs as possible */ 3074 if (sc->mbuf_alloc_size == MCLBYTES) 3075 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3076 else 3077 min_free_bd = (BNX_MAX_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3078 while (sc->free_rx_bd >= min_free_bd) { 3079 if (m == NULL) { 3080 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3081 BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n"); 3082 3083 sc->mbuf_alloc_failed++; 3084 rc = ENOBUFS; 3085 goto bnx_get_buf_exit); 3086 3087 /* This is a new mbuf allocation. */ 3088 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3089 if (m_new == NULL) { 3090 DBPRINT(sc, BNX_WARN, 3091 "%s(%d): RX mbuf header allocation failed!\n", 3092 __FILE__, __LINE__); 3093 3094 DBRUNIF(1, sc->mbuf_alloc_failed++); 3095 3096 rc = ENOBUFS; 3097 goto bnx_get_buf_exit; 3098 } 3099 3100 DBRUNIF(1, sc->rx_mbuf_alloc++); 3101 if (sc->mbuf_alloc_size == MCLBYTES) 3102 MCLGET(m_new, M_DONTWAIT); 3103 else 3104 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3105 M_DONTWAIT); 3106 if (!(m_new->m_flags & M_EXT)) { 3107 DBPRINT(sc, BNX_WARN, 3108 "%s(%d): RX mbuf chain allocation failed!\n", 3109 __FILE__, __LINE__); 3110 3111 m_freem(m_new); 3112 3113 DBRUNIF(1, sc->rx_mbuf_alloc--); 3114 DBRUNIF(1, sc->mbuf_alloc_failed++); 3115 3116 rc = ENOBUFS; 3117 goto bnx_get_buf_exit; 3118 } 3119 3120 } else { 3121 m_new = m; 3122 m = NULL; 3123 m_new->m_data = m_new->m_ext.ext_buf; 3124 } 3125 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3126 3127 /* Map the mbuf cluster into device memory. */ 3128 map = sc->rx_mbuf_map[*chain_prod]; 3129 first_chain_prod = *chain_prod; 3130 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3131 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3132 __FILE__, __LINE__); 3133 3134 m_freem(m_new); 3135 3136 DBRUNIF(1, sc->rx_mbuf_alloc--); 3137 3138 rc = ENOBUFS; 3139 goto bnx_get_buf_exit; 3140 } 3141 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3142 BUS_DMASYNC_PREREAD); 3143 3144 /* Watch for overflow. */ 3145 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3146 aprint_error_dev(sc->bnx_dev, 3147 "Too many free rx_bd (0x%04X > 0x%04X)!\n", 3148 sc->free_rx_bd, (u_int16_t)USABLE_RX_BD)); 3149 3150 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3151 sc->rx_low_watermark = sc->free_rx_bd); 3152 3153 /* 3154 * Setup the rx_bd for the first segment 3155 */ 3156 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3157 3158 addr = (u_int32_t)(map->dm_segs[0].ds_addr); 3159 rxbd->rx_bd_haddr_lo = htole32(addr); 3160 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3161 rxbd->rx_bd_haddr_hi = htole32(addr); 3162 rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); 3163 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3164 *prod_bseq += map->dm_segs[0].ds_len; 3165 bus_dmamap_sync(sc->bnx_dmatag, 3166 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3167 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3169 3170 for (i = 1; i < map->dm_nsegs; i++) { 3171 *prod = NEXT_RX_BD(*prod); 3172 *chain_prod = RX_CHAIN_IDX(*prod); 3173 3174 rxbd = 3175 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3176 3177 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 3178 rxbd->rx_bd_haddr_lo = htole32(addr); 3179 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3180 rxbd->rx_bd_haddr_hi = htole32(addr); 3181 rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); 3182 rxbd->rx_bd_flags = 0; 3183 *prod_bseq += map->dm_segs[i].ds_len; 3184 bus_dmamap_sync(sc->bnx_dmatag, 3185 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3186 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3187 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3188 } 3189 3190 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3191 bus_dmamap_sync(sc->bnx_dmatag, 3192 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3193 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3194 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3195 3196 /* 3197 * Save the mbuf, ajust the map pointer (swap map for first and 3198 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3199 * and update counter. 3200 */ 3201 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3202 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3203 sc->rx_mbuf_map[*chain_prod] = map; 3204 sc->free_rx_bd -= map->dm_nsegs; 3205 3206 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3207 map->dm_nsegs)); 3208 *prod = NEXT_RX_BD(*prod); 3209 *chain_prod = RX_CHAIN_IDX(*prod); 3210 } 3211 3212 bnx_get_buf_exit: 3213 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3214 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3215 *chain_prod, *prod_bseq); 3216 3217 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3218 __func__); 3219 3220 return(rc); 3221 } 3222 3223 /****************************************************************************/ 3224 /* Allocate memory and initialize the TX data structures. */ 3225 /* */ 3226 /* Returns: */ 3227 /* 0 for success, positive value for failure. */ 3228 /****************************************************************************/ 3229 int 3230 bnx_init_tx_chain(struct bnx_softc *sc) 3231 { 3232 struct tx_bd *txbd; 3233 u_int32_t val, addr; 3234 int i, rc = 0; 3235 3236 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3237 3238 /* Set the initial TX producer/consumer indices. */ 3239 sc->tx_prod = 0; 3240 sc->tx_cons = 0; 3241 sc->tx_prod_bseq = 0; 3242 sc->used_tx_bd = 0; 3243 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3244 3245 /* 3246 * The NetXtreme II supports a linked-list structure called 3247 * a Buffer Descriptor Chain (or BD chain). A BD chain 3248 * consists of a series of 1 or more chain pages, each of which 3249 * consists of a fixed number of BD entries. 3250 * The last BD entry on each page is a pointer to the next page 3251 * in the chain, and the last pointer in the BD chain 3252 * points back to the beginning of the chain. 3253 */ 3254 3255 /* Set the TX next pointer chain entries. */ 3256 for (i = 0; i < TX_PAGES; i++) { 3257 int j; 3258 3259 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3260 3261 /* Check if we've reached the last page. */ 3262 if (i == (TX_PAGES - 1)) 3263 j = 0; 3264 else 3265 j = i + 1; 3266 3267 addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); 3268 txbd->tx_bd_haddr_lo = htole32(addr); 3269 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3270 txbd->tx_bd_haddr_hi = htole32(addr); 3271 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3272 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3273 } 3274 3275 /* 3276 * Initialize the context ID for an L2 TX chain. 3277 */ 3278 val = BNX_L2CTX_TYPE_TYPE_L2; 3279 val |= BNX_L2CTX_TYPE_SIZE_L2; 3280 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3281 3282 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3283 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3284 3285 /* Point the hardware to the first page in the chain. */ 3286 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3287 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3288 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3289 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3290 3291 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3292 3293 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3294 3295 return(rc); 3296 } 3297 3298 /****************************************************************************/ 3299 /* Free memory and clear the TX data structures. */ 3300 /* */ 3301 /* Returns: */ 3302 /* Nothing. */ 3303 /****************************************************************************/ 3304 void 3305 bnx_free_tx_chain(struct bnx_softc *sc) 3306 { 3307 int i; 3308 3309 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3310 3311 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3312 for (i = 0; i < TOTAL_TX_BD; i++) { 3313 if (sc->tx_mbuf_ptr[i] != NULL) { 3314 if (sc->tx_mbuf_map != NULL) 3315 bus_dmamap_sync(sc->bnx_dmatag, 3316 sc->tx_mbuf_map[i], 0, 3317 sc->tx_mbuf_map[i]->dm_mapsize, 3318 BUS_DMASYNC_POSTWRITE); 3319 m_freem(sc->tx_mbuf_ptr[i]); 3320 sc->tx_mbuf_ptr[i] = NULL; 3321 DBRUNIF(1, sc->tx_mbuf_alloc--); 3322 } 3323 } 3324 3325 /* Clear each TX chain page. */ 3326 for (i = 0; i < TX_PAGES; i++) { 3327 bzero((char *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 3328 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3329 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3330 } 3331 3332 /* Check if we lost any mbufs in the process. */ 3333 DBRUNIF((sc->tx_mbuf_alloc), 3334 aprint_error_dev(sc->bnx_dev, 3335 "Memory leak! Lost %d mbufs from tx chain!\n", 3336 sc->tx_mbuf_alloc)); 3337 3338 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3339 } 3340 3341 /****************************************************************************/ 3342 /* Allocate memory and initialize the RX data structures. */ 3343 /* */ 3344 /* Returns: */ 3345 /* 0 for success, positive value for failure. */ 3346 /****************************************************************************/ 3347 int 3348 bnx_init_rx_chain(struct bnx_softc *sc) 3349 { 3350 struct rx_bd *rxbd; 3351 int i, rc = 0; 3352 u_int16_t prod, chain_prod; 3353 u_int32_t prod_bseq, val, addr; 3354 3355 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3356 3357 /* Initialize the RX producer and consumer indices. */ 3358 sc->rx_prod = 0; 3359 sc->rx_cons = 0; 3360 sc->rx_prod_bseq = 0; 3361 sc->free_rx_bd = BNX_RX_SLACK_SPACE; 3362 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3363 3364 /* Initialize the RX next pointer chain entries. */ 3365 for (i = 0; i < RX_PAGES; i++) { 3366 int j; 3367 3368 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3369 3370 /* Check if we've reached the last page. */ 3371 if (i == (RX_PAGES - 1)) 3372 j = 0; 3373 else 3374 j = i + 1; 3375 3376 /* Setup the chain page pointers. */ 3377 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 3378 rxbd->rx_bd_haddr_hi = htole32(addr); 3379 addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); 3380 rxbd->rx_bd_haddr_lo = htole32(addr); 3381 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 3382 0, BNX_RX_CHAIN_PAGE_SZ, 3383 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3384 } 3385 3386 /* Initialize the context ID for an L2 RX chain. */ 3387 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3388 val |= BNX_L2CTX_CTX_TYPE_SIZE_L2; 3389 val |= 0x02 << 8; 3390 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 3391 3392 /* Point the hardware to the first page in the chain. */ 3393 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 3394 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 3395 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 3396 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 3397 3398 /* Allocate mbuf clusters for the rx_bd chain. */ 3399 prod = prod_bseq = 0; 3400 chain_prod = RX_CHAIN_IDX(prod); 3401 if (bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3402 BNX_PRINTF(sc, 3403 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 3404 } 3405 3406 /* Save the RX chain producer index. */ 3407 sc->rx_prod = prod; 3408 sc->rx_prod_bseq = prod_bseq; 3409 3410 for (i = 0; i < RX_PAGES; i++) 3411 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 3412 sc->rx_bd_chain_map[i]->dm_mapsize, 3413 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3414 3415 /* Tell the chip about the waiting rx_bd's. */ 3416 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3417 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3418 3419 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3420 3421 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3422 3423 return(rc); 3424 } 3425 3426 /****************************************************************************/ 3427 /* Free memory and clear the RX data structures. */ 3428 /* */ 3429 /* Returns: */ 3430 /* Nothing. */ 3431 /****************************************************************************/ 3432 void 3433 bnx_free_rx_chain(struct bnx_softc *sc) 3434 { 3435 int i; 3436 3437 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3438 3439 /* Free any mbufs still in the RX mbuf chain. */ 3440 for (i = 0; i < TOTAL_RX_BD; i++) { 3441 if (sc->rx_mbuf_ptr[i] != NULL) { 3442 if (sc->rx_mbuf_map[i] != NULL) 3443 bus_dmamap_sync(sc->bnx_dmatag, 3444 sc->rx_mbuf_map[i], 0, 3445 sc->rx_mbuf_map[i]->dm_mapsize, 3446 BUS_DMASYNC_POSTREAD); 3447 m_freem(sc->rx_mbuf_ptr[i]); 3448 sc->rx_mbuf_ptr[i] = NULL; 3449 DBRUNIF(1, sc->rx_mbuf_alloc--); 3450 } 3451 } 3452 3453 /* Clear each RX chain page. */ 3454 for (i = 0; i < RX_PAGES; i++) 3455 bzero((char *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 3456 3457 /* Check if we lost any mbufs in the process. */ 3458 DBRUNIF((sc->rx_mbuf_alloc), 3459 aprint_error_dev(sc->bnx_dev, 3460 "Memory leak! Lost %d mbufs from rx chain!\n", 3461 sc->rx_mbuf_alloc)); 3462 3463 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3464 } 3465 3466 /****************************************************************************/ 3467 /* Set media options. */ 3468 /* */ 3469 /* Returns: */ 3470 /* 0 for success, positive value for failure. */ 3471 /****************************************************************************/ 3472 int 3473 bnx_ifmedia_upd(struct ifnet *ifp) 3474 { 3475 struct bnx_softc *sc; 3476 struct mii_data *mii; 3477 struct ifmedia *ifm; 3478 int rc = 0; 3479 3480 sc = ifp->if_softc; 3481 ifm = &sc->bnx_ifmedia; 3482 3483 /* DRC - ToDo: Add SerDes support. */ 3484 3485 mii = &sc->bnx_mii; 3486 sc->bnx_link = 0; 3487 if (mii->mii_instance) { 3488 struct mii_softc *miisc; 3489 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3490 mii_phy_reset(miisc); 3491 } 3492 mii_mediachg(mii); 3493 3494 return(rc); 3495 } 3496 3497 /****************************************************************************/ 3498 /* Reports current media status. */ 3499 /* */ 3500 /* Returns: */ 3501 /* Nothing. */ 3502 /****************************************************************************/ 3503 void 3504 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3505 { 3506 struct bnx_softc *sc; 3507 struct mii_data *mii; 3508 int s; 3509 3510 sc = ifp->if_softc; 3511 3512 s = splnet(); 3513 3514 mii = &sc->bnx_mii; 3515 3516 /* DRC - ToDo: Add SerDes support. */ 3517 3518 mii_pollstat(mii); 3519 ifmr->ifm_active = mii->mii_media_active; 3520 ifmr->ifm_status = mii->mii_media_status; 3521 3522 splx(s); 3523 } 3524 3525 /****************************************************************************/ 3526 /* Handles PHY generated interrupt events. */ 3527 /* */ 3528 /* Returns: */ 3529 /* Nothing. */ 3530 /****************************************************************************/ 3531 void 3532 bnx_phy_intr(struct bnx_softc *sc) 3533 { 3534 u_int32_t new_link_state, old_link_state; 3535 3536 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3537 BUS_DMASYNC_POSTREAD); 3538 new_link_state = sc->status_block->status_attn_bits & 3539 STATUS_ATTN_BITS_LINK_STATE; 3540 old_link_state = sc->status_block->status_attn_bits_ack & 3541 STATUS_ATTN_BITS_LINK_STATE; 3542 3543 /* Handle any changes if the link state has changed. */ 3544 if (new_link_state != old_link_state) { 3545 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 3546 3547 sc->bnx_link = 0; 3548 callout_stop(&sc->bnx_timeout); 3549 bnx_tick(sc); 3550 3551 /* Update the status_attn_bits_ack field in the status block. */ 3552 if (new_link_state) { 3553 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 3554 STATUS_ATTN_BITS_LINK_STATE); 3555 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 3556 } else { 3557 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 3558 STATUS_ATTN_BITS_LINK_STATE); 3559 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 3560 } 3561 } 3562 3563 /* Acknowledge the link change interrupt. */ 3564 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 3565 } 3566 3567 /****************************************************************************/ 3568 /* Handles received frame interrupt events. */ 3569 /* */ 3570 /* Returns: */ 3571 /* Nothing. */ 3572 /****************************************************************************/ 3573 void 3574 bnx_rx_intr(struct bnx_softc *sc) 3575 { 3576 struct status_block *sblk = sc->status_block; 3577 struct ifnet *ifp = &sc->ethercom.ec_if; 3578 u_int16_t hw_cons, sw_cons, sw_chain_cons; 3579 u_int16_t sw_prod, sw_chain_prod; 3580 u_int32_t sw_prod_bseq; 3581 struct l2_fhdr *l2fhdr; 3582 int i; 3583 3584 DBRUNIF(1, sc->rx_interrupts++); 3585 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3586 BUS_DMASYNC_POSTREAD); 3587 3588 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3589 for (i = 0; i < RX_PAGES; i++) 3590 bus_dmamap_sync(sc->bnx_dmatag, 3591 sc->rx_bd_chain_map[i], 0, 3592 sc->rx_bd_chain_map[i]->dm_mapsize, 3593 BUS_DMASYNC_POSTWRITE); 3594 3595 /* Get the hardware's view of the RX consumer index. */ 3596 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3597 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3598 hw_cons++; 3599 3600 /* Get working copies of the driver's view of the RX indices. */ 3601 sw_cons = sc->rx_cons; 3602 sw_prod = sc->rx_prod; 3603 sw_prod_bseq = sc->rx_prod_bseq; 3604 3605 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3606 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3607 __func__, sw_prod, sw_cons, sw_prod_bseq); 3608 3609 /* Prevent speculative reads from getting ahead of the status block. */ 3610 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3611 BUS_SPACE_BARRIER_READ); 3612 3613 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3614 sc->rx_low_watermark = sc->free_rx_bd); 3615 3616 /* 3617 * Scan through the receive chain as long 3618 * as there is work to do. 3619 */ 3620 while (sw_cons != hw_cons) { 3621 struct mbuf *m; 3622 struct rx_bd *rxbd; 3623 unsigned int len; 3624 u_int32_t status; 3625 3626 /* Convert the producer/consumer indices to an actual 3627 * rx_bd index. 3628 */ 3629 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3630 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3631 3632 /* Get the used rx_bd. */ 3633 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3634 sc->free_rx_bd++; 3635 3636 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 3637 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 3638 3639 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3640 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3641 #ifdef DIAGNOSTIC 3642 /* Validate that this is the last rx_bd. */ 3643 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 3644 printf("%s: Unexpected mbuf found in " 3645 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 3646 sw_chain_cons); 3647 } 3648 #endif 3649 3650 /* DRC - ToDo: If the received packet is small, say less 3651 * than 128 bytes, allocate a new mbuf here, 3652 * copy the data to that mbuf, and recycle 3653 * the mapped jumbo frame. 3654 */ 3655 3656 /* Unmap the mbuf from DMA space. */ 3657 #ifdef DIAGNOSTIC 3658 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 3659 printf("invalid map sw_cons 0x%x " 3660 "sw_prod 0x%x " 3661 "sw_chain_cons 0x%x " 3662 "sw_chain_prod 0x%x " 3663 "hw_cons 0x%x " 3664 "TOTAL_RX_BD_PER_PAGE 0x%x " 3665 "TOTAL_RX_BD 0x%x\n", 3666 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 3667 hw_cons, 3668 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 3669 } 3670 #endif 3671 bus_dmamap_sync(sc->bnx_dmatag, 3672 sc->rx_mbuf_map[sw_chain_cons], 0, 3673 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 3674 BUS_DMASYNC_POSTREAD); 3675 bus_dmamap_unload(sc->bnx_dmatag, 3676 sc->rx_mbuf_map[sw_chain_cons]); 3677 3678 /* Remove the mbuf from the driver's chain. */ 3679 m = sc->rx_mbuf_ptr[sw_chain_cons]; 3680 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 3681 3682 /* 3683 * Frames received on the NetXteme II are prepended 3684 * with the l2_fhdr structure which provides status 3685 * information about the received frame (including 3686 * VLAN tags and checksum info) and are also 3687 * automatically adjusted to align the IP header 3688 * (i.e. two null bytes are inserted before the 3689 * Ethernet header). 3690 */ 3691 l2fhdr = mtod(m, struct l2_fhdr *); 3692 3693 len = l2fhdr->l2_fhdr_pkt_len; 3694 status = l2fhdr->l2_fhdr_status; 3695 3696 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 3697 aprint_error("Simulating l2_fhdr status error.\n"); 3698 status = status | L2_FHDR_ERRORS_PHY_DECODE); 3699 3700 /* Watch for unusual sized frames. */ 3701 DBRUNIF(((len < BNX_MIN_MTU) || 3702 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 3703 aprint_error_dev(sc->bnx_dev, 3704 "Unusual frame size found. " 3705 "Min(%d), Actual(%d), Max(%d)\n", 3706 (int)BNX_MIN_MTU, len, 3707 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 3708 3709 bnx_dump_mbuf(sc, m); 3710 bnx_breakpoint(sc)); 3711 3712 len -= ETHER_CRC_LEN; 3713 3714 /* Check the received frame for errors. */ 3715 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 3716 L2_FHDR_ERRORS_PHY_DECODE | 3717 L2_FHDR_ERRORS_ALIGNMENT | 3718 L2_FHDR_ERRORS_TOO_SHORT | 3719 L2_FHDR_ERRORS_GIANT_FRAME)) || 3720 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 3721 len > 3722 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 3723 ifp->if_ierrors++; 3724 DBRUNIF(1, sc->l2fhdr_status_errors++); 3725 3726 /* Reuse the mbuf for a new frame. */ 3727 if (bnx_get_buf(sc, m, &sw_prod, 3728 &sw_chain_prod, &sw_prod_bseq)) { 3729 DBRUNIF(1, bnx_breakpoint(sc)); 3730 panic("%s: Can't reuse RX mbuf!\n", 3731 device_xname(sc->bnx_dev)); 3732 } 3733 continue; 3734 } 3735 3736 /* 3737 * Get a new mbuf for the rx_bd. If no new 3738 * mbufs are available then reuse the current mbuf, 3739 * log an ierror on the interface, and generate 3740 * an error in the system log. 3741 */ 3742 if (bnx_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, 3743 &sw_prod_bseq)) { 3744 DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate " 3745 "new mbuf, incoming frame dropped!\n")); 3746 3747 ifp->if_ierrors++; 3748 3749 /* Try and reuse the exisitng mbuf. */ 3750 if (bnx_get_buf(sc, m, &sw_prod, 3751 &sw_chain_prod, &sw_prod_bseq)) { 3752 DBRUNIF(1, bnx_breakpoint(sc)); 3753 panic("%s: Double mbuf allocation " 3754 "failure!", 3755 device_xname(sc->bnx_dev)); 3756 } 3757 continue; 3758 } 3759 3760 /* Skip over the l2_fhdr when passing the data up 3761 * the stack. 3762 */ 3763 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 3764 3765 /* Adjust the pckt length to match the received data. */ 3766 m->m_pkthdr.len = m->m_len = len; 3767 3768 /* Send the packet to the appropriate interface. */ 3769 m->m_pkthdr.rcvif = ifp; 3770 3771 DBRUN(BNX_VERBOSE_RECV, 3772 struct ether_header *eh; 3773 eh = mtod(m, struct ether_header *); 3774 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 3775 __func__, ether_sprintf(eh->ether_dhost), 3776 ether_sprintf(eh->ether_shost), 3777 htons(eh->ether_type))); 3778 3779 /* Validate the checksum. */ 3780 3781 /* Check for an IP datagram. */ 3782 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 3783 /* Check if the IP checksum is valid. */ 3784 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 3785 == 0) 3786 m->m_pkthdr.csum_flags |= 3787 M_CSUM_IPv4; 3788 #ifdef BNX_DEBUG 3789 else 3790 DBPRINT(sc, BNX_WARN_SEND, 3791 "%s(): Invalid IP checksum " 3792 "= 0x%04X!\n", 3793 __func__, 3794 l2fhdr->l2_fhdr_ip_xsum 3795 ); 3796 #endif 3797 } 3798 3799 /* Check for a valid TCP/UDP frame. */ 3800 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3801 L2_FHDR_STATUS_UDP_DATAGRAM)) { 3802 /* Check for a good TCP/UDP checksum. */ 3803 if ((status & 3804 (L2_FHDR_ERRORS_TCP_XSUM | 3805 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 3806 m->m_pkthdr.csum_flags |= 3807 M_CSUM_TCPv4 | 3808 M_CSUM_UDPv4; 3809 } else { 3810 DBPRINT(sc, BNX_WARN_SEND, 3811 "%s(): Invalid TCP/UDP " 3812 "checksum = 0x%04X!\n", 3813 __func__, 3814 l2fhdr->l2_fhdr_tcp_udp_xsum); 3815 } 3816 } 3817 3818 /* 3819 * If we received a packet with a vlan tag, 3820 * attach that information to the packet. 3821 */ 3822 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 3823 #if 0 3824 struct ether_vlan_header vh; 3825 3826 DBPRINT(sc, BNX_VERBOSE_SEND, 3827 "%s(): VLAN tag = 0x%04X\n", 3828 __func__, 3829 l2fhdr->l2_fhdr_vlan_tag); 3830 3831 if (m->m_pkthdr.len < ETHER_HDR_LEN) { 3832 m_freem(m); 3833 continue; 3834 } 3835 m_copydata(m, 0, ETHER_HDR_LEN, (void *)&vh); 3836 vh.evl_proto = vh.evl_encap_proto; 3837 vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag; 3838 vh.evl_encap_proto = htons(ETHERTYPE_VLAN); 3839 m_adj(m, ETHER_HDR_LEN); 3840 if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL) 3841 continue; 3842 m->m_pkthdr.len += sizeof(vh); 3843 if (m->m_len < sizeof(vh) && 3844 (m = m_pullup(m, sizeof(vh))) == NULL) 3845 goto bnx_rx_int_next_rx; 3846 m_copyback(m, 0, sizeof(vh), &vh); 3847 #else 3848 VLAN_INPUT_TAG(ifp, m, 3849 l2fhdr->l2_fhdr_vlan_tag, 3850 continue); 3851 #endif 3852 } 3853 3854 #if NBPFILTER > 0 3855 /* 3856 * Handle BPF listeners. Let the BPF 3857 * user see the packet. 3858 */ 3859 if (ifp->if_bpf) 3860 bpf_mtap(ifp->if_bpf, m); 3861 #endif 3862 3863 /* Pass the mbuf off to the upper layers. */ 3864 ifp->if_ipackets++; 3865 DBPRINT(sc, BNX_VERBOSE_RECV, 3866 "%s(): Passing received frame up.\n", __func__); 3867 (*ifp->if_input)(ifp, m); 3868 DBRUNIF(1, sc->rx_mbuf_alloc--); 3869 3870 } 3871 3872 sw_cons = NEXT_RX_BD(sw_cons); 3873 3874 /* Refresh hw_cons to see if there's new work */ 3875 if (sw_cons == hw_cons) { 3876 hw_cons = sc->hw_rx_cons = 3877 sblk->status_rx_quick_consumer_index0; 3878 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 3879 USABLE_RX_BD_PER_PAGE) 3880 hw_cons++; 3881 } 3882 3883 /* Prevent speculative reads from getting ahead of 3884 * the status block. 3885 */ 3886 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3887 BUS_SPACE_BARRIER_READ); 3888 } 3889 3890 for (i = 0; i < RX_PAGES; i++) 3891 bus_dmamap_sync(sc->bnx_dmatag, 3892 sc->rx_bd_chain_map[i], 0, 3893 sc->rx_bd_chain_map[i]->dm_mapsize, 3894 BUS_DMASYNC_PREWRITE); 3895 3896 sc->rx_cons = sw_cons; 3897 sc->rx_prod = sw_prod; 3898 sc->rx_prod_bseq = sw_prod_bseq; 3899 3900 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3901 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3902 3903 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 3904 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 3905 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 3906 } 3907 3908 /****************************************************************************/ 3909 /* Handles transmit completion interrupt events. */ 3910 /* */ 3911 /* Returns: */ 3912 /* Nothing. */ 3913 /****************************************************************************/ 3914 void 3915 bnx_tx_intr(struct bnx_softc *sc) 3916 { 3917 struct status_block *sblk = sc->status_block; 3918 struct ifnet *ifp = &sc->ethercom.ec_if; 3919 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 3920 3921 DBRUNIF(1, sc->tx_interrupts++); 3922 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3923 BUS_DMASYNC_POSTREAD); 3924 3925 /* Get the hardware's view of the TX consumer index. */ 3926 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 3927 3928 /* Skip to the next entry if this is a chain page pointer. */ 3929 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 3930 hw_tx_cons++; 3931 3932 sw_tx_cons = sc->tx_cons; 3933 3934 /* Prevent speculative reads from getting ahead of the status block. */ 3935 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3936 BUS_SPACE_BARRIER_READ); 3937 3938 /* Cycle through any completed TX chain page entries. */ 3939 while (sw_tx_cons != hw_tx_cons) { 3940 #ifdef BNX_DEBUG 3941 struct tx_bd *txbd = NULL; 3942 #endif 3943 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 3944 3945 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 3946 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 3947 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 3948 3949 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 3950 aprint_error_dev(sc->bnx_dev, 3951 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 3952 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 3953 3954 DBRUNIF(1, txbd = &sc->tx_bd_chain 3955 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 3956 3957 DBRUNIF((txbd == NULL), 3958 aprint_error_dev(sc->bnx_dev, 3959 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 3960 bnx_breakpoint(sc)); 3961 3962 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 3963 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 3964 3965 /* 3966 * Free the associated mbuf. Remember 3967 * that only the last tx_bd of a packet 3968 * has an mbuf pointer and DMA map. 3969 */ 3970 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 3971 /* Validate that this is the last tx_bd. */ 3972 DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & 3973 TX_BD_FLAGS_END)), 3974 aprint_error_dev(sc->bnx_dev, 3975 "tx_bd END flag not set but txmbuf == NULL!\n"); 3976 bnx_breakpoint(sc)); 3977 3978 DBRUN(BNX_INFO_SEND, 3979 aprint_debug("%s: Unloading map/freeing mbuf " 3980 "from tx_bd[0x%04X]\n", 3981 __func__, sw_tx_chain_cons)); 3982 3983 /* Unmap the mbuf. */ 3984 bus_dmamap_unload(sc->bnx_dmatag, 3985 sc->tx_mbuf_map[sw_tx_chain_cons]); 3986 3987 /* Free the mbuf. */ 3988 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 3989 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 3990 DBRUNIF(1, sc->tx_mbuf_alloc--); 3991 3992 ifp->if_opackets++; 3993 } 3994 3995 sc->used_tx_bd--; 3996 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 3997 3998 /* Refresh hw_cons to see if there's new work. */ 3999 hw_tx_cons = sc->hw_tx_cons = 4000 sblk->status_tx_quick_consumer_index0; 4001 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4002 USABLE_TX_BD_PER_PAGE) 4003 hw_tx_cons++; 4004 4005 /* Prevent speculative reads from getting ahead of 4006 * the status block. 4007 */ 4008 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4009 BUS_SPACE_BARRIER_READ); 4010 } 4011 4012 /* Clear the TX timeout timer. */ 4013 ifp->if_timer = 0; 4014 4015 /* Clear the tx hardware queue full flag. */ 4016 if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) { 4017 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4018 aprint_debug_dev(sc->bnx_dev, 4019 "TX chain is open for business! Used tx_bd = %d\n", 4020 sc->used_tx_bd)); 4021 ifp->if_flags &= ~IFF_OACTIVE; 4022 } 4023 4024 sc->tx_cons = sw_tx_cons; 4025 } 4026 4027 /****************************************************************************/ 4028 /* Disables interrupt generation. */ 4029 /* */ 4030 /* Returns: */ 4031 /* Nothing. */ 4032 /****************************************************************************/ 4033 void 4034 bnx_disable_intr(struct bnx_softc *sc) 4035 { 4036 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4037 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4038 } 4039 4040 /****************************************************************************/ 4041 /* Enables interrupt generation. */ 4042 /* */ 4043 /* Returns: */ 4044 /* Nothing. */ 4045 /****************************************************************************/ 4046 void 4047 bnx_enable_intr(struct bnx_softc *sc) 4048 { 4049 u_int32_t val; 4050 4051 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4052 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4053 4054 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4055 sc->last_status_idx); 4056 4057 val = REG_RD(sc, BNX_HC_COMMAND); 4058 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4059 } 4060 4061 /****************************************************************************/ 4062 /* Handles controller initialization. */ 4063 /* */ 4064 /****************************************************************************/ 4065 int 4066 bnx_init(struct ifnet *ifp) 4067 { 4068 struct bnx_softc *sc = ifp->if_softc; 4069 u_int32_t ether_mtu; 4070 int s, error = 0; 4071 4072 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4073 4074 s = splnet(); 4075 4076 bnx_stop(sc); 4077 4078 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4079 aprint_error("bnx: Controller reset failed!\n"); 4080 goto bnx_init_exit; 4081 } 4082 4083 if ((error = bnx_chipinit(sc)) != 0) { 4084 aprint_error("bnx: Controller initialization failed!\n"); 4085 goto bnx_init_exit; 4086 } 4087 4088 if ((error = bnx_blockinit(sc)) != 0) { 4089 aprint_error("bnx: Block initialization failed!\n"); 4090 goto bnx_init_exit; 4091 } 4092 4093 /* Calculate and program the Ethernet MRU size. */ 4094 if (ifp->if_mtu <= ETHERMTU) { 4095 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4096 sc->mbuf_alloc_size = MCLBYTES; 4097 } else { 4098 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4099 sc->mbuf_alloc_size = BNX_MAX_MRU; 4100 } 4101 4102 4103 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4104 __func__, ether_mtu); 4105 4106 /* 4107 * Program the MRU and enable Jumbo frame 4108 * support. 4109 */ 4110 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4111 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4112 4113 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4114 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4115 4116 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4117 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4118 sc->mbuf_alloc_size, sc->max_frame_size); 4119 4120 /* Program appropriate promiscuous/multicast filtering. */ 4121 bnx_set_rx_mode(sc); 4122 4123 /* Init RX buffer descriptor chain. */ 4124 bnx_init_rx_chain(sc); 4125 4126 /* Init TX buffer descriptor chain. */ 4127 bnx_init_tx_chain(sc); 4128 4129 /* Enable host interrupts. */ 4130 bnx_enable_intr(sc); 4131 4132 bnx_ifmedia_upd(ifp); 4133 4134 ifp->if_flags |= IFF_RUNNING; 4135 ifp->if_flags &= ~IFF_OACTIVE; 4136 4137 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4138 4139 bnx_init_exit: 4140 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4141 4142 splx(s); 4143 4144 return(error); 4145 } 4146 4147 /****************************************************************************/ 4148 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4149 /* memory visible to the controller. */ 4150 /* */ 4151 /* Returns: */ 4152 /* 0 for success, positive value for failure. */ 4153 /****************************************************************************/ 4154 int 4155 bnx_tx_encap(struct bnx_softc *sc, struct mbuf **m_head) 4156 { 4157 bus_dmamap_t map; 4158 struct tx_bd *txbd = NULL; 4159 struct mbuf *m0; 4160 u_int16_t vlan_tag = 0, flags = 0; 4161 u_int16_t chain_prod, prod; 4162 #ifdef BNX_DEBUG 4163 u_int16_t debug_prod; 4164 #endif 4165 u_int32_t addr, prod_bseq; 4166 int i, error, rc = 0; 4167 struct m_tag *mtag; 4168 4169 m0 = *m_head; 4170 4171 /* Transfer any checksum offload flags to the bd. */ 4172 if (m0->m_pkthdr.csum_flags) { 4173 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 4174 flags |= TX_BD_FLAGS_IP_CKSUM; 4175 if (m0->m_pkthdr.csum_flags & 4176 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4177 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4178 } 4179 4180 /* Transfer any VLAN tags to the bd. */ 4181 mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m0); 4182 if (mtag != NULL) { 4183 flags |= TX_BD_FLAGS_VLAN_TAG; 4184 vlan_tag = VLAN_TAG_VALUE(mtag); 4185 } 4186 4187 /* Map the mbuf into DMAable memory. */ 4188 prod = sc->tx_prod; 4189 chain_prod = TX_CHAIN_IDX(prod); 4190 map = sc->tx_mbuf_map[chain_prod]; 4191 4192 /* Map the mbuf into our DMA address space. */ 4193 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m0, BUS_DMA_NOWAIT); 4194 if (error != 0) { 4195 aprint_error_dev(sc->bnx_dev, 4196 "Error mapping mbuf into TX chain!\n"); 4197 m_freem(m0); 4198 *m_head = NULL; 4199 return (error); 4200 } 4201 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4202 BUS_DMASYNC_PREWRITE); 4203 /* 4204 * The chip seems to require that at least 16 descriptors be kept 4205 * empty at all times. Make sure we honor that. 4206 * XXX Would it be faster to assume worst case scenario for 4207 * map->dm_nsegs and do this calculation higher up? 4208 */ 4209 if (map->dm_nsegs > (USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE)) { 4210 bus_dmamap_unload(sc->bnx_dmatag, map); 4211 return (ENOBUFS); 4212 } 4213 4214 /* prod points to an empty tx_bd at this point. */ 4215 prod_bseq = sc->tx_prod_bseq; 4216 #ifdef BNX_DEBUG 4217 debug_prod = chain_prod; 4218 #endif 4219 DBPRINT(sc, BNX_INFO_SEND, 4220 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4221 "prod_bseq = 0x%08X\n", 4222 __func__, *prod, chain_prod, prod_bseq); 4223 4224 /* 4225 * Cycle through each mbuf segment that makes up 4226 * the outgoing frame, gathering the mapping info 4227 * for that segment and creating a tx_bd for the 4228 * mbuf. 4229 */ 4230 for (i = 0; i < map->dm_nsegs ; i++) { 4231 chain_prod = TX_CHAIN_IDX(prod); 4232 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4233 4234 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 4235 txbd->tx_bd_haddr_lo = htole32(addr); 4236 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4237 txbd->tx_bd_haddr_hi = htole32(addr); 4238 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 4239 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4240 txbd->tx_bd_flags = htole16(flags); 4241 prod_bseq += map->dm_segs[i].ds_len; 4242 if (i == 0) 4243 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4244 prod = NEXT_TX_BD(prod); 4245 } 4246 /* Set the END flag on the last TX buffer descriptor. */ 4247 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4248 4249 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg)); 4250 4251 DBPRINT(sc, BNX_INFO_SEND, 4252 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4253 "prod_bseq = 0x%08X\n", 4254 __func__, prod, chain_prod, prod_bseq); 4255 4256 /* 4257 * Ensure that the mbuf pointer for this 4258 * transmission is placed at the array 4259 * index of the last descriptor in this 4260 * chain. This is done because a single 4261 * map is used for all segments of the mbuf 4262 * and we don't want to unload the map before 4263 * all of the segments have been freed. 4264 */ 4265 sc->tx_mbuf_ptr[chain_prod] = m0; 4266 sc->used_tx_bd += map->dm_nsegs; 4267 4268 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4269 sc->tx_hi_watermark = sc->used_tx_bd); 4270 4271 DBRUNIF(1, sc->tx_mbuf_alloc++); 4272 4273 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4274 map_arg.maxsegs)); 4275 4276 /* prod points to the next free tx_bd at this point. */ 4277 sc->tx_prod = prod; 4278 sc->tx_prod_bseq = prod_bseq; 4279 4280 return (rc); 4281 } 4282 4283 /****************************************************************************/ 4284 /* Main transmit routine. */ 4285 /* */ 4286 /* Returns: */ 4287 /* Nothing. */ 4288 /****************************************************************************/ 4289 void 4290 bnx_start(struct ifnet *ifp) 4291 { 4292 struct bnx_softc *sc = ifp->if_softc; 4293 struct mbuf *m_head = NULL; 4294 int count = 0; 4295 u_int16_t tx_prod, tx_chain_prod; 4296 4297 /* If there's no link or the transmit queue is empty then just exit. */ 4298 if (!sc->bnx_link || IFQ_IS_EMPTY(&ifp->if_snd)) { 4299 DBPRINT(sc, BNX_INFO_SEND, 4300 "%s(): No link or transmit queue empty.\n", __func__); 4301 goto bnx_start_exit; 4302 } 4303 4304 /* prod points to the next free tx_bd. */ 4305 tx_prod = sc->tx_prod; 4306 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4307 4308 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 4309 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n", 4310 __func__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4311 4312 /* 4313 * Keep adding entries while there is space in the ring. We keep 4314 * BNX_TX_SLACK_SPACE entries unused at all times. 4315 */ 4316 while (sc->used_tx_bd < USABLE_TX_BD - BNX_TX_SLACK_SPACE) { 4317 /* Check for any frames to send. */ 4318 IFQ_POLL(&ifp->if_snd, m_head); 4319 if (m_head == NULL) 4320 break; 4321 4322 /* 4323 * Pack the data into the transmit ring. If we 4324 * don't have room, set the OACTIVE flag to wait 4325 * for the NIC to drain the chain. 4326 */ 4327 if (bnx_tx_encap(sc, &m_head)) { 4328 ifp->if_flags |= IFF_OACTIVE; 4329 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 4330 "business! Total tx_bd used = %d\n", 4331 sc->used_tx_bd); 4332 break; 4333 } 4334 4335 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4336 count++; 4337 4338 #if NBPFILTER > 0 4339 /* Send a copy of the frame to any BPF listeners. */ 4340 if (ifp->if_bpf) 4341 bpf_mtap(ifp->if_bpf, m_head); 4342 #endif 4343 } 4344 4345 if (count == 0) { 4346 /* no packets were dequeued */ 4347 DBPRINT(sc, BNX_VERBOSE_SEND, 4348 "%s(): No packets were dequeued\n", __func__); 4349 goto bnx_start_exit; 4350 } 4351 4352 /* Update the driver's counters. */ 4353 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4354 4355 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 4356 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, tx_prod, 4357 tx_chain_prod, sc->tx_prod_bseq); 4358 4359 /* Start the transmit. */ 4360 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4361 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4362 4363 /* Set the tx timeout. */ 4364 ifp->if_timer = BNX_TX_TIMEOUT; 4365 4366 bnx_start_exit: 4367 return; 4368 } 4369 4370 /****************************************************************************/ 4371 /* Handles any IOCTL calls from the operating system. */ 4372 /* */ 4373 /* Returns: */ 4374 /* 0 for success, positive value for failure. */ 4375 /****************************************************************************/ 4376 int 4377 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 4378 { 4379 struct bnx_softc *sc = ifp->if_softc; 4380 struct ifreq *ifr = (struct ifreq *) data; 4381 struct mii_data *mii; 4382 int s, error = 0; 4383 4384 s = splnet(); 4385 4386 switch (command) { 4387 case SIOCSIFFLAGS: 4388 if (ifp->if_flags & IFF_UP) { 4389 if ((ifp->if_flags & IFF_RUNNING) && 4390 ((ifp->if_flags ^ sc->bnx_if_flags) & 4391 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 4392 bnx_set_rx_mode(sc); 4393 } else if (!(ifp->if_flags & IFF_RUNNING)) 4394 bnx_init(ifp); 4395 4396 } else if (ifp->if_flags & IFF_RUNNING) 4397 bnx_stop(sc); 4398 4399 sc->bnx_if_flags = ifp->if_flags; 4400 break; 4401 4402 case SIOCSIFMEDIA: 4403 case SIOCGIFMEDIA: 4404 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 4405 sc->bnx_phy_flags); 4406 4407 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 4408 error = ifmedia_ioctl(ifp, ifr, 4409 &sc->bnx_ifmedia, command); 4410 else { 4411 mii = &sc->bnx_mii; 4412 error = ifmedia_ioctl(ifp, ifr, 4413 &mii->mii_media, command); 4414 } 4415 break; 4416 4417 default: 4418 error = ether_ioctl(ifp, command, data); 4419 if (error != ENETRESET) 4420 break; 4421 error = 0; 4422 if (command == SIOCADDMULTI || command == SIOCDELMULTI) { 4423 /* reload packet filter if running */ 4424 if (ifp->if_flags & IFF_RUNNING) 4425 bnx_set_rx_mode(sc); 4426 } 4427 break; 4428 } 4429 4430 splx(s); 4431 4432 return (error); 4433 } 4434 4435 /****************************************************************************/ 4436 /* Transmit timeout handler. */ 4437 /* */ 4438 /* Returns: */ 4439 /* Nothing. */ 4440 /****************************************************************************/ 4441 void 4442 bnx_watchdog(struct ifnet *ifp) 4443 { 4444 struct bnx_softc *sc = ifp->if_softc; 4445 4446 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 4447 bnx_dump_status_block(sc)); 4448 4449 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 4450 4451 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 4452 4453 bnx_init(ifp); 4454 4455 ifp->if_oerrors++; 4456 } 4457 4458 /* 4459 * Interrupt handler. 4460 */ 4461 /****************************************************************************/ 4462 /* Main interrupt entry point. Verifies that the controller generated the */ 4463 /* interrupt and then calls a separate routine for handle the various */ 4464 /* interrupt causes (PHY, TX, RX). */ 4465 /* */ 4466 /* Returns: */ 4467 /* 0 for success, positive value for failure. */ 4468 /****************************************************************************/ 4469 int 4470 bnx_intr(void *xsc) 4471 { 4472 struct bnx_softc *sc; 4473 struct ifnet *ifp; 4474 u_int32_t status_attn_bits; 4475 4476 sc = xsc; 4477 if (!device_is_active(sc->bnx_dev)) 4478 return 0; 4479 4480 ifp = &sc->ethercom.ec_if; 4481 4482 DBRUNIF(1, sc->interrupts_generated++); 4483 4484 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4485 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4486 4487 /* 4488 * If the hardware status block index 4489 * matches the last value read by the 4490 * driver and we haven't asserted our 4491 * interrupt then there's nothing to do. 4492 */ 4493 if ((sc->status_block->status_idx == sc->last_status_idx) && 4494 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 4495 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 4496 return (0); 4497 4498 /* Ack the interrupt and stop others from occuring. */ 4499 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4500 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 4501 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4502 4503 /* Keep processing data as long as there is work to do. */ 4504 for (;;) { 4505 status_attn_bits = sc->status_block->status_attn_bits; 4506 4507 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 4508 aprint_debug("Simulating unexpected status attention bit set."); 4509 status_attn_bits = status_attn_bits | 4510 STATUS_ATTN_BITS_PARITY_ERROR); 4511 4512 /* Was it a link change interrupt? */ 4513 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 4514 (sc->status_block->status_attn_bits_ack & 4515 STATUS_ATTN_BITS_LINK_STATE)) 4516 bnx_phy_intr(sc); 4517 4518 /* If any other attention is asserted then the chip is toast. */ 4519 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 4520 (sc->status_block->status_attn_bits_ack & 4521 ~STATUS_ATTN_BITS_LINK_STATE))) { 4522 DBRUN(1, sc->unexpected_attentions++); 4523 4524 aprint_error_dev(sc->bnx_dev, 4525 "Fatal attention detected: 0x%08X\n", 4526 sc->status_block->status_attn_bits); 4527 4528 DBRUN(BNX_FATAL, 4529 if (bnx_debug_unexpected_attention == 0) 4530 bnx_breakpoint(sc)); 4531 4532 bnx_init(ifp); 4533 return (1); 4534 } 4535 4536 /* Check for any completed RX frames. */ 4537 if (sc->status_block->status_rx_quick_consumer_index0 != 4538 sc->hw_rx_cons) 4539 bnx_rx_intr(sc); 4540 4541 /* Check for any completed TX frames. */ 4542 if (sc->status_block->status_tx_quick_consumer_index0 != 4543 sc->hw_tx_cons) 4544 bnx_tx_intr(sc); 4545 4546 /* Save the status block index value for use during the 4547 * next interrupt. 4548 */ 4549 sc->last_status_idx = sc->status_block->status_idx; 4550 4551 /* Prevent speculative reads from getting ahead of the 4552 * status block. 4553 */ 4554 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4555 BUS_SPACE_BARRIER_READ); 4556 4557 /* If there's no work left then exit the isr. */ 4558 if ((sc->status_block->status_rx_quick_consumer_index0 == 4559 sc->hw_rx_cons) && 4560 (sc->status_block->status_tx_quick_consumer_index0 == 4561 sc->hw_tx_cons)) 4562 break; 4563 } 4564 4565 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4566 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 4567 4568 /* Re-enable interrupts. */ 4569 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4570 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 4571 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4572 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4573 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4574 4575 /* Handle any frames that arrived while handling the interrupt. */ 4576 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4577 bnx_start(ifp); 4578 4579 return (1); 4580 } 4581 4582 /****************************************************************************/ 4583 /* Programs the various packet receive modes (broadcast and multicast). */ 4584 /* */ 4585 /* Returns: */ 4586 /* Nothing. */ 4587 /****************************************************************************/ 4588 void 4589 bnx_set_rx_mode(struct bnx_softc *sc) 4590 { 4591 struct ethercom *ec = &sc->ethercom; 4592 struct ifnet *ifp = &ec->ec_if; 4593 struct ether_multi *enm; 4594 struct ether_multistep step; 4595 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 4596 u_int32_t rx_mode, sort_mode; 4597 int h, i; 4598 4599 /* Initialize receive mode default settings. */ 4600 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 4601 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 4602 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 4603 4604 /* 4605 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 4606 * be enbled. 4607 */ 4608 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 4609 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 4610 4611 /* 4612 * Check for promiscuous, all multicast, or selected 4613 * multicast address filtering. 4614 */ 4615 if (ifp->if_flags & IFF_PROMISC) { 4616 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 4617 4618 /* Enable promiscuous mode. */ 4619 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 4620 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 4621 } else if (ifp->if_flags & IFF_ALLMULTI) { 4622 allmulti: 4623 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 4624 4625 /* Enable all multicast addresses. */ 4626 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4627 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4628 0xffffffff); 4629 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 4630 } else { 4631 /* Accept one or more multicast(s). */ 4632 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 4633 4634 ETHER_FIRST_MULTI(step, ec, enm); 4635 while (enm != NULL) { 4636 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 4637 ETHER_ADDR_LEN)) { 4638 ifp->if_flags |= IFF_ALLMULTI; 4639 goto allmulti; 4640 } 4641 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 4642 0xFF; 4643 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 4644 ETHER_NEXT_MULTI(step, enm); 4645 } 4646 4647 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4648 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4649 hashes[i]); 4650 4651 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 4652 } 4653 4654 /* Only make changes if the recive mode has actually changed. */ 4655 if (rx_mode != sc->rx_mode) { 4656 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 4657 rx_mode); 4658 4659 sc->rx_mode = rx_mode; 4660 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 4661 } 4662 4663 /* Disable and clear the exisitng sort before enabling a new sort. */ 4664 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 4665 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 4666 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 4667 } 4668 4669 /****************************************************************************/ 4670 /* Called periodically to updates statistics from the controllers */ 4671 /* statistics block. */ 4672 /* */ 4673 /* Returns: */ 4674 /* Nothing. */ 4675 /****************************************************************************/ 4676 void 4677 bnx_stats_update(struct bnx_softc *sc) 4678 { 4679 struct ifnet *ifp = &sc->ethercom.ec_if; 4680 struct statistics_block *stats; 4681 4682 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 4683 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4684 BUS_DMASYNC_POSTREAD); 4685 4686 stats = (struct statistics_block *)sc->stats_block; 4687 4688 /* 4689 * Update the interface statistics from the 4690 * hardware statistics. 4691 */ 4692 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 4693 4694 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 4695 (u_long)stats->stat_EtherStatsOverrsizePkts + 4696 (u_long)stats->stat_IfInMBUFDiscards + 4697 (u_long)stats->stat_Dot3StatsAlignmentErrors + 4698 (u_long)stats->stat_Dot3StatsFCSErrors; 4699 4700 ifp->if_oerrors = (u_long) 4701 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 4702 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 4703 (u_long)stats->stat_Dot3StatsLateCollisions; 4704 4705 /* 4706 * Certain controllers don't report 4707 * carrier sense errors correctly. 4708 * See errata E11_5708CA0_1165. 4709 */ 4710 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 4711 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 4712 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 4713 4714 /* 4715 * Update the sysctl statistics from the 4716 * hardware statistics. 4717 */ 4718 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 4719 (u_int64_t) stats->stat_IfHCInOctets_lo; 4720 4721 sc->stat_IfHCInBadOctets = 4722 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 4723 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 4724 4725 sc->stat_IfHCOutOctets = 4726 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 4727 (u_int64_t) stats->stat_IfHCOutOctets_lo; 4728 4729 sc->stat_IfHCOutBadOctets = 4730 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 4731 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 4732 4733 sc->stat_IfHCInUcastPkts = 4734 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 4735 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 4736 4737 sc->stat_IfHCInMulticastPkts = 4738 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 4739 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 4740 4741 sc->stat_IfHCInBroadcastPkts = 4742 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 4743 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 4744 4745 sc->stat_IfHCOutUcastPkts = 4746 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 4747 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 4748 4749 sc->stat_IfHCOutMulticastPkts = 4750 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 4751 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 4752 4753 sc->stat_IfHCOutBroadcastPkts = 4754 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 4755 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 4756 4757 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 4758 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4759 4760 sc->stat_Dot3StatsCarrierSenseErrors = 4761 stats->stat_Dot3StatsCarrierSenseErrors; 4762 4763 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 4764 4765 sc->stat_Dot3StatsAlignmentErrors = 4766 stats->stat_Dot3StatsAlignmentErrors; 4767 4768 sc->stat_Dot3StatsSingleCollisionFrames = 4769 stats->stat_Dot3StatsSingleCollisionFrames; 4770 4771 sc->stat_Dot3StatsMultipleCollisionFrames = 4772 stats->stat_Dot3StatsMultipleCollisionFrames; 4773 4774 sc->stat_Dot3StatsDeferredTransmissions = 4775 stats->stat_Dot3StatsDeferredTransmissions; 4776 4777 sc->stat_Dot3StatsExcessiveCollisions = 4778 stats->stat_Dot3StatsExcessiveCollisions; 4779 4780 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 4781 4782 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 4783 4784 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 4785 4786 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 4787 4788 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 4789 4790 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 4791 4792 sc->stat_EtherStatsPktsRx64Octets = 4793 stats->stat_EtherStatsPktsRx64Octets; 4794 4795 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 4796 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 4797 4798 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 4799 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 4800 4801 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 4802 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 4803 4804 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 4805 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 4806 4807 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 4808 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 4809 4810 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 4811 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 4812 4813 sc->stat_EtherStatsPktsTx64Octets = 4814 stats->stat_EtherStatsPktsTx64Octets; 4815 4816 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 4817 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 4818 4819 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 4820 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 4821 4822 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 4823 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 4824 4825 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 4826 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 4827 4828 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 4829 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 4830 4831 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 4832 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 4833 4834 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 4835 4836 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 4837 4838 sc->stat_OutXonSent = stats->stat_OutXonSent; 4839 4840 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 4841 4842 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 4843 4844 sc->stat_MacControlFramesReceived = 4845 stats->stat_MacControlFramesReceived; 4846 4847 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 4848 4849 sc->stat_IfInFramesL2FilterDiscards = 4850 stats->stat_IfInFramesL2FilterDiscards; 4851 4852 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 4853 4854 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 4855 4856 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 4857 4858 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 4859 4860 sc->stat_CatchupInRuleCheckerDiscards = 4861 stats->stat_CatchupInRuleCheckerDiscards; 4862 4863 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 4864 4865 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 4866 4867 sc->stat_CatchupInRuleCheckerP4Hit = 4868 stats->stat_CatchupInRuleCheckerP4Hit; 4869 4870 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 4871 } 4872 4873 void 4874 bnx_tick(void *xsc) 4875 { 4876 struct bnx_softc *sc = xsc; 4877 struct ifnet *ifp = &sc->ethercom.ec_if; 4878 struct mii_data *mii = NULL; 4879 u_int32_t msg; 4880 u_int16_t prod, chain_prod; 4881 u_int32_t prod_bseq; 4882 int s = splnet(); 4883 4884 /* Tell the firmware that the driver is still running. */ 4885 #ifdef BNX_DEBUG 4886 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 4887 #else 4888 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 4889 #endif 4890 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 4891 4892 /* Update the statistics from the hardware statistics block. */ 4893 bnx_stats_update(sc); 4894 4895 /* Schedule the next tick. */ 4896 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4897 4898 /* If link is up already up then we're done. */ 4899 if (sc->bnx_link) 4900 goto bnx_tick_exit; 4901 4902 /* DRC - ToDo: Add SerDes support and check SerDes link here. */ 4903 4904 mii = &sc->bnx_mii; 4905 mii_tick(mii); 4906 4907 /* Check if the link has come up. */ 4908 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 4909 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4910 sc->bnx_link++; 4911 /* Now that link is up, handle any outstanding TX traffic. */ 4912 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4913 bnx_start(ifp); 4914 } 4915 4916 bnx_tick_exit: 4917 /* try to get more RX buffers, just in case */ 4918 prod = sc->rx_prod; 4919 prod_bseq = sc->rx_prod_bseq; 4920 chain_prod = RX_CHAIN_IDX(prod); 4921 bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq); 4922 sc->rx_prod = prod; 4923 sc->rx_prod_bseq = prod_bseq; 4924 splx(s); 4925 return; 4926 } 4927 4928 /****************************************************************************/ 4929 /* BNX Debug Routines */ 4930 /****************************************************************************/ 4931 #ifdef BNX_DEBUG 4932 4933 /****************************************************************************/ 4934 /* Prints out information about an mbuf. */ 4935 /* */ 4936 /* Returns: */ 4937 /* Nothing. */ 4938 /****************************************************************************/ 4939 void 4940 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 4941 { 4942 struct mbuf *mp = m; 4943 4944 if (m == NULL) { 4945 /* Index out of range. */ 4946 aprint_error("mbuf ptr is null!\n"); 4947 return; 4948 } 4949 4950 while (mp) { 4951 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 4952 mp, mp->m_len); 4953 4954 if (mp->m_flags & M_EXT) 4955 aprint_debug("M_EXT "); 4956 if (mp->m_flags & M_PKTHDR) 4957 aprint_debug("M_PKTHDR "); 4958 aprint_debug("\n"); 4959 4960 if (mp->m_flags & M_EXT) 4961 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 4962 mp, mp->m_ext.ext_size); 4963 4964 mp = mp->m_next; 4965 } 4966 } 4967 4968 /****************************************************************************/ 4969 /* Prints out the mbufs in the TX mbuf chain. */ 4970 /* */ 4971 /* Returns: */ 4972 /* Nothing. */ 4973 /****************************************************************************/ 4974 void 4975 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4976 { 4977 struct mbuf *m; 4978 int i; 4979 4980 BNX_PRINTF(sc, 4981 "----------------------------" 4982 " tx mbuf data " 4983 "----------------------------\n"); 4984 4985 for (i = 0; i < count; i++) { 4986 m = sc->tx_mbuf_ptr[chain_prod]; 4987 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 4988 bnx_dump_mbuf(sc, m); 4989 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 4990 } 4991 4992 BNX_PRINTF(sc, 4993 "--------------------------------------------" 4994 "----------------------------\n"); 4995 } 4996 4997 /* 4998 * This routine prints the RX mbuf chain. 4999 */ 5000 void 5001 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5002 { 5003 struct mbuf *m; 5004 int i; 5005 5006 BNX_PRINTF(sc, 5007 "----------------------------" 5008 " rx mbuf data " 5009 "----------------------------\n"); 5010 5011 for (i = 0; i < count; i++) { 5012 m = sc->rx_mbuf_ptr[chain_prod]; 5013 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5014 bnx_dump_mbuf(sc, m); 5015 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5016 } 5017 5018 5019 BNX_PRINTF(sc, 5020 "--------------------------------------------" 5021 "----------------------------\n"); 5022 } 5023 5024 void 5025 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5026 { 5027 if (idx > MAX_TX_BD) 5028 /* Index out of range. */ 5029 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5030 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5031 /* TX Chain page pointer. */ 5032 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5033 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5034 txbd->tx_bd_haddr_lo); 5035 else 5036 /* Normal tx_bd entry. */ 5037 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5038 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5039 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5040 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5041 txbd->tx_bd_flags); 5042 } 5043 5044 void 5045 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5046 { 5047 if (idx > MAX_RX_BD) 5048 /* Index out of range. */ 5049 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5050 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5051 /* TX Chain page pointer. */ 5052 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5053 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5054 rxbd->rx_bd_haddr_lo); 5055 else 5056 /* Normal tx_bd entry. */ 5057 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5058 "0x%08X, flags = 0x%08X\n", idx, 5059 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5060 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5061 } 5062 5063 void 5064 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5065 { 5066 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5067 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5068 "tcp_udp_xsum = 0x%04X\n", idx, 5069 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5070 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5071 l2fhdr->l2_fhdr_tcp_udp_xsum); 5072 } 5073 5074 /* 5075 * This routine prints the TX chain. 5076 */ 5077 void 5078 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5079 { 5080 struct tx_bd *txbd; 5081 int i; 5082 5083 /* First some info about the tx_bd chain structure. */ 5084 BNX_PRINTF(sc, 5085 "----------------------------" 5086 " tx_bd chain " 5087 "----------------------------\n"); 5088 5089 BNX_PRINTF(sc, 5090 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5091 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5092 5093 BNX_PRINTF(sc, 5094 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5095 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5096 5097 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD); 5098 5099 BNX_PRINTF(sc, "" 5100 "-----------------------------" 5101 " tx_bd data " 5102 "-----------------------------\n"); 5103 5104 /* Now print out the tx_bd's themselves. */ 5105 for (i = 0; i < count; i++) { 5106 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5107 bnx_dump_txbd(sc, tx_prod, txbd); 5108 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5109 } 5110 5111 BNX_PRINTF(sc, 5112 "-----------------------------" 5113 "--------------" 5114 "-----------------------------\n"); 5115 } 5116 5117 /* 5118 * This routine prints the RX chain. 5119 */ 5120 void 5121 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5122 { 5123 struct rx_bd *rxbd; 5124 int i; 5125 5126 /* First some info about the tx_bd chain structure. */ 5127 BNX_PRINTF(sc, 5128 "----------------------------" 5129 " rx_bd chain " 5130 "----------------------------\n"); 5131 5132 BNX_PRINTF(sc, "----- RX_BD Chain -----\n"); 5133 5134 BNX_PRINTF(sc, 5135 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5136 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5137 5138 BNX_PRINTF(sc, 5139 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5140 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5141 5142 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD); 5143 5144 BNX_PRINTF(sc, 5145 "----------------------------" 5146 " rx_bd data " 5147 "----------------------------\n"); 5148 5149 /* Now print out the rx_bd's themselves. */ 5150 for (i = 0; i < count; i++) { 5151 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5152 bnx_dump_rxbd(sc, rx_prod, rxbd); 5153 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5154 } 5155 5156 BNX_PRINTF(sc, 5157 "----------------------------" 5158 "--------------" 5159 "----------------------------\n"); 5160 } 5161 5162 /* 5163 * This routine prints the status block. 5164 */ 5165 void 5166 bnx_dump_status_block(struct bnx_softc *sc) 5167 { 5168 struct status_block *sblk; 5169 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5170 BUS_DMASYNC_POSTREAD); 5171 5172 sblk = sc->status_block; 5173 5174 BNX_PRINTF(sc, "----------------------------- Status Block " 5175 "-----------------------------\n"); 5176 5177 BNX_PRINTF(sc, 5178 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5179 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5180 sblk->status_idx); 5181 5182 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5183 sblk->status_rx_quick_consumer_index0, 5184 sblk->status_tx_quick_consumer_index0); 5185 5186 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5187 5188 /* Theses indices are not used for normal L2 drivers. */ 5189 if (sblk->status_rx_quick_consumer_index1 || 5190 sblk->status_tx_quick_consumer_index1) 5191 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5192 sblk->status_rx_quick_consumer_index1, 5193 sblk->status_tx_quick_consumer_index1); 5194 5195 if (sblk->status_rx_quick_consumer_index2 || 5196 sblk->status_tx_quick_consumer_index2) 5197 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5198 sblk->status_rx_quick_consumer_index2, 5199 sblk->status_tx_quick_consumer_index2); 5200 5201 if (sblk->status_rx_quick_consumer_index3 || 5202 sblk->status_tx_quick_consumer_index3) 5203 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5204 sblk->status_rx_quick_consumer_index3, 5205 sblk->status_tx_quick_consumer_index3); 5206 5207 if (sblk->status_rx_quick_consumer_index4 || 5208 sblk->status_rx_quick_consumer_index5) 5209 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5210 sblk->status_rx_quick_consumer_index4, 5211 sblk->status_rx_quick_consumer_index5); 5212 5213 if (sblk->status_rx_quick_consumer_index6 || 5214 sblk->status_rx_quick_consumer_index7) 5215 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5216 sblk->status_rx_quick_consumer_index6, 5217 sblk->status_rx_quick_consumer_index7); 5218 5219 if (sblk->status_rx_quick_consumer_index8 || 5220 sblk->status_rx_quick_consumer_index9) 5221 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5222 sblk->status_rx_quick_consumer_index8, 5223 sblk->status_rx_quick_consumer_index9); 5224 5225 if (sblk->status_rx_quick_consumer_index10 || 5226 sblk->status_rx_quick_consumer_index11) 5227 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5228 sblk->status_rx_quick_consumer_index10, 5229 sblk->status_rx_quick_consumer_index11); 5230 5231 if (sblk->status_rx_quick_consumer_index12 || 5232 sblk->status_rx_quick_consumer_index13) 5233 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5234 sblk->status_rx_quick_consumer_index12, 5235 sblk->status_rx_quick_consumer_index13); 5236 5237 if (sblk->status_rx_quick_consumer_index14 || 5238 sblk->status_rx_quick_consumer_index15) 5239 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5240 sblk->status_rx_quick_consumer_index14, 5241 sblk->status_rx_quick_consumer_index15); 5242 5243 if (sblk->status_completion_producer_index || 5244 sblk->status_cmd_consumer_index) 5245 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5246 sblk->status_completion_producer_index, 5247 sblk->status_cmd_consumer_index); 5248 5249 BNX_PRINTF(sc, "-------------------------------------------" 5250 "-----------------------------\n"); 5251 } 5252 5253 /* 5254 * This routine prints the statistics block. 5255 */ 5256 void 5257 bnx_dump_stats_block(struct bnx_softc *sc) 5258 { 5259 struct statistics_block *sblk; 5260 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5261 BUS_DMASYNC_POSTREAD); 5262 5263 sblk = sc->stats_block; 5264 5265 BNX_PRINTF(sc, "" 5266 "-----------------------------" 5267 " Stats Block " 5268 "-----------------------------\n"); 5269 5270 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5271 "IfHcInBadOctets = 0x%08X:%08X\n", 5272 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5273 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5274 5275 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5276 "IfHcOutBadOctets = 0x%08X:%08X\n", 5277 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5278 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5279 5280 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5281 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5282 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5283 sblk->stat_IfHCInMulticastPkts_hi, 5284 sblk->stat_IfHCInMulticastPkts_lo); 5285 5286 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5287 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5288 sblk->stat_IfHCInBroadcastPkts_hi, 5289 sblk->stat_IfHCInBroadcastPkts_lo, 5290 sblk->stat_IfHCOutUcastPkts_hi, 5291 sblk->stat_IfHCOutUcastPkts_lo); 5292 5293 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5294 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5295 sblk->stat_IfHCOutMulticastPkts_hi, 5296 sblk->stat_IfHCOutMulticastPkts_lo, 5297 sblk->stat_IfHCOutBroadcastPkts_hi, 5298 sblk->stat_IfHCOutBroadcastPkts_lo); 5299 5300 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5301 BNX_PRINTF(sc, "0x%08X : " 5302 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5303 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5304 5305 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5306 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5307 sblk->stat_Dot3StatsCarrierSenseErrors); 5308 5309 if (sblk->stat_Dot3StatsFCSErrors) 5310 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5311 sblk->stat_Dot3StatsFCSErrors); 5312 5313 if (sblk->stat_Dot3StatsAlignmentErrors) 5314 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5315 sblk->stat_Dot3StatsAlignmentErrors); 5316 5317 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5318 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5319 sblk->stat_Dot3StatsSingleCollisionFrames); 5320 5321 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5322 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 5323 sblk->stat_Dot3StatsMultipleCollisionFrames); 5324 5325 if (sblk->stat_Dot3StatsDeferredTransmissions) 5326 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 5327 sblk->stat_Dot3StatsDeferredTransmissions); 5328 5329 if (sblk->stat_Dot3StatsExcessiveCollisions) 5330 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 5331 sblk->stat_Dot3StatsExcessiveCollisions); 5332 5333 if (sblk->stat_Dot3StatsLateCollisions) 5334 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 5335 sblk->stat_Dot3StatsLateCollisions); 5336 5337 if (sblk->stat_EtherStatsCollisions) 5338 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 5339 sblk->stat_EtherStatsCollisions); 5340 5341 if (sblk->stat_EtherStatsFragments) 5342 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 5343 sblk->stat_EtherStatsFragments); 5344 5345 if (sblk->stat_EtherStatsJabbers) 5346 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 5347 sblk->stat_EtherStatsJabbers); 5348 5349 if (sblk->stat_EtherStatsUndersizePkts) 5350 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 5351 sblk->stat_EtherStatsUndersizePkts); 5352 5353 if (sblk->stat_EtherStatsOverrsizePkts) 5354 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 5355 sblk->stat_EtherStatsOverrsizePkts); 5356 5357 if (sblk->stat_EtherStatsPktsRx64Octets) 5358 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 5359 sblk->stat_EtherStatsPktsRx64Octets); 5360 5361 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 5362 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 5363 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 5364 5365 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 5366 BNX_PRINTF(sc, "0x%08X : " 5367 "EtherStatsPktsRx128Octetsto255Octets\n", 5368 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 5369 5370 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 5371 BNX_PRINTF(sc, "0x%08X : " 5372 "EtherStatsPktsRx256Octetsto511Octets\n", 5373 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 5374 5375 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 5376 BNX_PRINTF(sc, "0x%08X : " 5377 "EtherStatsPktsRx512Octetsto1023Octets\n", 5378 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 5379 5380 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 5381 BNX_PRINTF(sc, "0x%08X : " 5382 "EtherStatsPktsRx1024Octetsto1522Octets\n", 5383 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 5384 5385 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 5386 BNX_PRINTF(sc, "0x%08X : " 5387 "EtherStatsPktsRx1523Octetsto9022Octets\n", 5388 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 5389 5390 if (sblk->stat_EtherStatsPktsTx64Octets) 5391 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 5392 sblk->stat_EtherStatsPktsTx64Octets); 5393 5394 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 5395 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 5396 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 5397 5398 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 5399 BNX_PRINTF(sc, "0x%08X : " 5400 "EtherStatsPktsTx128Octetsto255Octets\n", 5401 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 5402 5403 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 5404 BNX_PRINTF(sc, "0x%08X : " 5405 "EtherStatsPktsTx256Octetsto511Octets\n", 5406 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 5407 5408 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 5409 BNX_PRINTF(sc, "0x%08X : " 5410 "EtherStatsPktsTx512Octetsto1023Octets\n", 5411 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 5412 5413 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 5414 BNX_PRINTF(sc, "0x%08X : " 5415 "EtherStatsPktsTx1024Octetsto1522Octets\n", 5416 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 5417 5418 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 5419 BNX_PRINTF(sc, "0x%08X : " 5420 "EtherStatsPktsTx1523Octetsto9022Octets\n", 5421 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 5422 5423 if (sblk->stat_XonPauseFramesReceived) 5424 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 5425 sblk->stat_XonPauseFramesReceived); 5426 5427 if (sblk->stat_XoffPauseFramesReceived) 5428 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 5429 sblk->stat_XoffPauseFramesReceived); 5430 5431 if (sblk->stat_OutXonSent) 5432 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 5433 sblk->stat_OutXonSent); 5434 5435 if (sblk->stat_OutXoffSent) 5436 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 5437 sblk->stat_OutXoffSent); 5438 5439 if (sblk->stat_FlowControlDone) 5440 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 5441 sblk->stat_FlowControlDone); 5442 5443 if (sblk->stat_MacControlFramesReceived) 5444 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 5445 sblk->stat_MacControlFramesReceived); 5446 5447 if (sblk->stat_XoffStateEntered) 5448 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 5449 sblk->stat_XoffStateEntered); 5450 5451 if (sblk->stat_IfInFramesL2FilterDiscards) 5452 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 5453 sblk->stat_IfInFramesL2FilterDiscards); 5454 5455 if (sblk->stat_IfInRuleCheckerDiscards) 5456 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 5457 sblk->stat_IfInRuleCheckerDiscards); 5458 5459 if (sblk->stat_IfInFTQDiscards) 5460 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 5461 sblk->stat_IfInFTQDiscards); 5462 5463 if (sblk->stat_IfInMBUFDiscards) 5464 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 5465 sblk->stat_IfInMBUFDiscards); 5466 5467 if (sblk->stat_IfInRuleCheckerP4Hit) 5468 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 5469 sblk->stat_IfInRuleCheckerP4Hit); 5470 5471 if (sblk->stat_CatchupInRuleCheckerDiscards) 5472 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 5473 sblk->stat_CatchupInRuleCheckerDiscards); 5474 5475 if (sblk->stat_CatchupInFTQDiscards) 5476 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 5477 sblk->stat_CatchupInFTQDiscards); 5478 5479 if (sblk->stat_CatchupInMBUFDiscards) 5480 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 5481 sblk->stat_CatchupInMBUFDiscards); 5482 5483 if (sblk->stat_CatchupInRuleCheckerP4Hit) 5484 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 5485 sblk->stat_CatchupInRuleCheckerP4Hit); 5486 5487 BNX_PRINTF(sc, 5488 "-----------------------------" 5489 "--------------" 5490 "-----------------------------\n"); 5491 } 5492 5493 void 5494 bnx_dump_driver_state(struct bnx_softc *sc) 5495 { 5496 BNX_PRINTF(sc, 5497 "-----------------------------" 5498 " Driver State " 5499 "-----------------------------\n"); 5500 5501 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 5502 "address\n", sc); 5503 5504 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 5505 sc->status_block); 5506 5507 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 5508 "address\n", sc->stats_block); 5509 5510 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 5511 "adddress\n", sc->tx_bd_chain); 5512 5513 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 5514 sc->rx_bd_chain); 5515 5516 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 5517 sc->tx_mbuf_ptr); 5518 5519 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 5520 sc->rx_mbuf_ptr); 5521 5522 BNX_PRINTF(sc, 5523 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 5524 sc->interrupts_generated); 5525 5526 BNX_PRINTF(sc, 5527 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 5528 sc->rx_interrupts); 5529 5530 BNX_PRINTF(sc, 5531 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 5532 sc->tx_interrupts); 5533 5534 BNX_PRINTF(sc, 5535 " 0x%08X - (sc->last_status_idx) status block index\n", 5536 sc->last_status_idx); 5537 5538 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 5539 sc->tx_prod); 5540 5541 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 5542 sc->tx_cons); 5543 5544 BNX_PRINTF(sc, 5545 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 5546 sc->tx_prod_bseq); 5547 5548 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 5549 sc->rx_prod); 5550 5551 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 5552 sc->rx_cons); 5553 5554 BNX_PRINTF(sc, 5555 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 5556 sc->rx_prod_bseq); 5557 5558 BNX_PRINTF(sc, 5559 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5560 sc->rx_mbuf_alloc); 5561 5562 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 5563 sc->free_rx_bd); 5564 5565 BNX_PRINTF(sc, 5566 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 5567 sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD); 5568 5569 BNX_PRINTF(sc, 5570 " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 5571 sc->tx_mbuf_alloc); 5572 5573 BNX_PRINTF(sc, 5574 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5575 sc->rx_mbuf_alloc); 5576 5577 BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 5578 sc->used_tx_bd); 5579 5580 BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 5581 sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD); 5582 5583 BNX_PRINTF(sc, 5584 " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 5585 sc->mbuf_alloc_failed); 5586 5587 BNX_PRINTF(sc, "-------------------------------------------" 5588 "-----------------------------\n"); 5589 } 5590 5591 void 5592 bnx_dump_hw_state(struct bnx_softc *sc) 5593 { 5594 u_int32_t val1; 5595 int i; 5596 5597 BNX_PRINTF(sc, 5598 "----------------------------" 5599 " Hardware State " 5600 "----------------------------\n"); 5601 5602 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 5603 5604 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 5605 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 5606 val1, BNX_MISC_ENABLE_STATUS_BITS); 5607 5608 val1 = REG_RD(sc, BNX_DMA_STATUS); 5609 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 5610 5611 val1 = REG_RD(sc, BNX_CTX_STATUS); 5612 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 5613 5614 val1 = REG_RD(sc, BNX_EMAC_STATUS); 5615 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 5616 BNX_EMAC_STATUS); 5617 5618 val1 = REG_RD(sc, BNX_RPM_STATUS); 5619 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 5620 5621 val1 = REG_RD(sc, BNX_TBDR_STATUS); 5622 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 5623 BNX_TBDR_STATUS); 5624 5625 val1 = REG_RD(sc, BNX_TDMA_STATUS); 5626 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 5627 BNX_TDMA_STATUS); 5628 5629 val1 = REG_RD(sc, BNX_HC_STATUS); 5630 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 5631 5632 BNX_PRINTF(sc, 5633 "----------------------------" 5634 "----------------" 5635 "----------------------------\n"); 5636 5637 BNX_PRINTF(sc, 5638 "----------------------------" 5639 " Register Dump " 5640 "----------------------------\n"); 5641 5642 for (i = 0x400; i < 0x8000; i += 0x10) 5643 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 5644 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 5645 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 5646 5647 BNX_PRINTF(sc, 5648 "----------------------------" 5649 "----------------" 5650 "----------------------------\n"); 5651 } 5652 5653 void 5654 bnx_breakpoint(struct bnx_softc *sc) 5655 { 5656 /* Unreachable code to shut the compiler up about unused functions. */ 5657 if (0) { 5658 bnx_dump_txbd(sc, 0, NULL); 5659 bnx_dump_rxbd(sc, 0, NULL); 5660 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 5661 bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 5662 bnx_dump_l2fhdr(sc, 0, NULL); 5663 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 5664 bnx_dump_rx_chain(sc, 0, USABLE_RX_BD); 5665 bnx_dump_status_block(sc); 5666 bnx_dump_stats_block(sc); 5667 bnx_dump_driver_state(sc); 5668 bnx_dump_hw_state(sc); 5669 } 5670 5671 bnx_dump_driver_state(sc); 5672 /* Print the important status block fields. */ 5673 bnx_dump_status_block(sc); 5674 5675 #if 0 5676 /* Call the debugger. */ 5677 breakpoint(); 5678 #endif 5679 5680 return; 5681 } 5682 #endif 5683
Indexes created Wed Sep 24 05:09:52 GMT 2025