if_bnx.c revision 1.15
1 /* $NetBSD: if_bnx.c,v 1.15 2007/12/30 00:56:45 dyoung Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.43 2007/01/30 03:21:10 krw Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.15 2007/12/30 00:56:45 dyoung Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5708C B1 44 * 45 * The following controllers are not supported by this driver: 46 * (These are not "Production" versions of the controller.) 47 * 48 * BCM5706C A0, A1 49 * BCM5706S A0, A1, A2, A3 50 * BCM5708C A0, B0 51 * BCM5708S A0, B0, B1 52 */ 53 54 #include <sys/callout.h> 55 56 #include <dev/pci/if_bnxreg.h> 57 #include <dev/microcode/bnx/bnxfw.h> 58 59 /****************************************************************************/ 60 /* BNX Driver Version */ 61 /****************************************************************************/ 62 const char bnx_driver_version[] = "v0.9.6"; 63 64 /****************************************************************************/ 65 /* BNX Debug Options */ 66 /****************************************************************************/ 67 #ifdef BNX_DEBUG 68 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 69 70 /* 0 = Never */ 71 /* 1 = 1 in 2,147,483,648 */ 72 /* 256 = 1 in 8,388,608 */ 73 /* 2048 = 1 in 1,048,576 */ 74 /* 65536 = 1 in 32,768 */ 75 /* 1048576 = 1 in 2,048 */ 76 /* 268435456 = 1 in 8 */ 77 /* 536870912 = 1 in 4 */ 78 /* 1073741824 = 1 in 2 */ 79 80 /* Controls how often the l2_fhdr frame error check will fail. */ 81 int bnx_debug_l2fhdr_status_check = 0; 82 83 /* Controls how often the unexpected attention check will fail. */ 84 int bnx_debug_unexpected_attention = 0; 85 86 /* Controls how often to simulate an mbuf allocation failure. */ 87 int bnx_debug_mbuf_allocation_failure = 0; 88 89 /* Controls how often to simulate a DMA mapping failure. */ 90 int bnx_debug_dma_map_addr_failure = 0; 91 92 /* Controls how often to simulate a bootcode failure. */ 93 int bnx_debug_bootcode_running_failure = 0; 94 #endif 95 96 /****************************************************************************/ 97 /* PCI Device ID Table */ 98 /* */ 99 /* Used by bnx_probe() to identify the devices supported by this driver. */ 100 /****************************************************************************/ 101 static const struct bnx_product { 102 pci_vendor_id_t bp_vendor; 103 pci_product_id_t bp_product; 104 pci_vendor_id_t bp_subvendor; 105 pci_product_id_t bp_subproduct; 106 const char *bp_name; 107 } bnx_devices[] = { 108 #ifdef PCI_SUBPRODUCT_HP_NC370T 109 { 110 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 111 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 112 "HP NC370T Multifunction Gigabit Server Adapter" 113 }, 114 #endif 115 #ifdef PCI_SUBPRODUCT_HP_NC370i 116 { 117 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 118 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 119 "HP NC370i Multifunction Gigabit Server Adapter" 120 }, 121 #endif 122 { 123 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 124 0, 0, 125 "Broadcom NetXtreme II BCM5706 1000Base-T" 126 }, 127 #ifdef PCI_SUBPRODUCT_HP_NC370F 128 { 129 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 130 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 131 "HP NC370F Multifunction Gigabit Server Adapter" 132 }, 133 #endif 134 { 135 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 136 0, 0, 137 "Broadcom NetXtreme II BCM5706 1000Base-SX" 138 }, 139 { 140 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 141 0, 0, 142 "Broadcom NetXtreme II BCM5708 1000Base-T" 143 }, 144 { 145 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 146 0, 0, 147 "Broadcom NetXtreme II BCM5708 1000Base-SX" 148 }, 149 }; 150 151 /****************************************************************************/ 152 /* Supported Flash NVRAM device data. */ 153 /****************************************************************************/ 154 static struct flash_spec flash_table[] = 155 { 156 /* Slow EEPROM */ 157 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 158 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 159 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 160 "EEPROM - slow"}, 161 /* Expansion entry 0001 */ 162 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 164 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 165 "Entry 0001"}, 166 /* Saifun SA25F010 (non-buffered flash) */ 167 /* strap, cfg1, & write1 need updates */ 168 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 169 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 171 "Non-buffered flash (128kB)"}, 172 /* Saifun SA25F020 (non-buffered flash) */ 173 /* strap, cfg1, & write1 need updates */ 174 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 175 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 176 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 177 "Non-buffered flash (256kB)"}, 178 /* Expansion entry 0100 */ 179 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 0100"}, 183 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 184 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 185 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 186 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 187 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 188 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 189 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 190 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 191 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 192 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 193 /* Saifun SA25F005 (non-buffered flash) */ 194 /* strap, cfg1, & write1 need updates */ 195 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 196 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 197 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 198 "Non-buffered flash (64kB)"}, 199 /* Fast EEPROM */ 200 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 201 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 202 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 203 "EEPROM - fast"}, 204 /* Expansion entry 1001 */ 205 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 206 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 208 "Entry 1001"}, 209 /* Expansion entry 1010 */ 210 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 211 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 1010"}, 214 /* ATMEL AT45DB011B (buffered flash) */ 215 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 216 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 217 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 218 "Buffered flash (128kB)"}, 219 /* Expansion entry 1100 */ 220 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 221 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 223 "Entry 1100"}, 224 /* Expansion entry 1101 */ 225 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 226 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 228 "Entry 1101"}, 229 /* Ateml Expansion entry 1110 */ 230 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 231 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 232 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 233 "Entry 1110 (Atmel)"}, 234 /* ATMEL AT45DB021B (buffered flash) */ 235 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 236 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 237 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 238 "Buffered flash (256kB)"}, 239 }; 240 241 /****************************************************************************/ 242 /* OpenBSD device entry points. */ 243 /****************************************************************************/ 244 static int bnx_probe(device_t, cfdata_t, void *); 245 void bnx_attach(device_t, device_t, void *); 246 int bnx_detach(device_t, int); 247 248 /****************************************************************************/ 249 /* BNX Debug Data Structure Dump Routines */ 250 /****************************************************************************/ 251 #ifdef BNX_DEBUG 252 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 253 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 254 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 255 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 256 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 257 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 258 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 259 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 260 void bnx_dump_status_block(struct bnx_softc *); 261 void bnx_dump_stats_block(struct bnx_softc *); 262 void bnx_dump_driver_state(struct bnx_softc *); 263 void bnx_dump_hw_state(struct bnx_softc *); 264 void bnx_breakpoint(struct bnx_softc *); 265 #endif 266 267 /****************************************************************************/ 268 /* BNX Register/Memory Access Routines */ 269 /****************************************************************************/ 270 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 271 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 272 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 273 int bnx_miibus_read_reg(device_t, int, int); 274 void bnx_miibus_write_reg(device_t, int, int, int); 275 void bnx_miibus_statchg(device_t); 276 277 /****************************************************************************/ 278 /* BNX NVRAM Access Routines */ 279 /****************************************************************************/ 280 int bnx_acquire_nvram_lock(struct bnx_softc *); 281 int bnx_release_nvram_lock(struct bnx_softc *); 282 void bnx_enable_nvram_access(struct bnx_softc *); 283 void bnx_disable_nvram_access(struct bnx_softc *); 284 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 285 u_int32_t); 286 int bnx_init_nvram(struct bnx_softc *); 287 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 288 int bnx_nvram_test(struct bnx_softc *); 289 #ifdef BNX_NVRAM_WRITE_SUPPORT 290 int bnx_enable_nvram_write(struct bnx_softc *); 291 void bnx_disable_nvram_write(struct bnx_softc *); 292 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 293 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 294 u_int32_t); 295 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 296 #endif 297 298 /****************************************************************************/ 299 /* */ 300 /****************************************************************************/ 301 int bnx_dma_alloc(struct bnx_softc *); 302 void bnx_dma_free(struct bnx_softc *); 303 void bnx_release_resources(struct bnx_softc *); 304 305 /****************************************************************************/ 306 /* BNX Firmware Synchronization and Load */ 307 /****************************************************************************/ 308 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 309 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 310 u_int32_t); 311 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 312 struct fw_info *); 313 void bnx_init_cpus(struct bnx_softc *); 314 315 void bnx_stop(struct ifnet *, int); 316 int bnx_reset(struct bnx_softc *, u_int32_t); 317 int bnx_chipinit(struct bnx_softc *); 318 int bnx_blockinit(struct bnx_softc *); 319 int bnx_get_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 320 u_int16_t *, u_int32_t *); 321 322 int bnx_init_tx_chain(struct bnx_softc *); 323 int bnx_init_rx_chain(struct bnx_softc *); 324 void bnx_free_rx_chain(struct bnx_softc *); 325 void bnx_free_tx_chain(struct bnx_softc *); 326 327 int bnx_tx_encap(struct bnx_softc *, struct mbuf **); 328 void bnx_start(struct ifnet *); 329 int bnx_ioctl(struct ifnet *, u_long, void *); 330 void bnx_watchdog(struct ifnet *); 331 int bnx_ifmedia_upd(struct ifnet *); 332 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 333 int bnx_init(struct ifnet *); 334 335 void bnx_init_context(struct bnx_softc *); 336 void bnx_get_mac_addr(struct bnx_softc *); 337 void bnx_set_mac_addr(struct bnx_softc *); 338 void bnx_phy_intr(struct bnx_softc *); 339 void bnx_rx_intr(struct bnx_softc *); 340 void bnx_tx_intr(struct bnx_softc *); 341 void bnx_disable_intr(struct bnx_softc *); 342 void bnx_enable_intr(struct bnx_softc *); 343 344 int bnx_intr(void *); 345 void bnx_set_rx_mode(struct bnx_softc *); 346 void bnx_stats_update(struct bnx_softc *); 347 void bnx_tick(void *); 348 349 /****************************************************************************/ 350 /* OpenBSD device dispatch table. */ 351 /****************************************************************************/ 352 CFATTACH_DECL_NEW(bnx, sizeof(struct bnx_softc), 353 bnx_probe, bnx_attach, bnx_detach, NULL); 354 355 /****************************************************************************/ 356 /* Device probe function. */ 357 /* */ 358 /* Compares the device to the driver's list of supported devices and */ 359 /* reports back to the OS whether this is the right driver for the device. */ 360 /* */ 361 /* Returns: */ 362 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 363 /****************************************************************************/ 364 static const struct bnx_product * 365 bnx_lookup(const struct pci_attach_args *pa) 366 { 367 int i; 368 pcireg_t subid; 369 370 for (i = 0; i < __arraycount(bnx_devices); i++) { 371 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 372 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 373 continue; 374 if (!bnx_devices[i].bp_subvendor) 375 return &bnx_devices[i]; 376 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 377 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 378 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 379 return &bnx_devices[i]; 380 } 381 382 return NULL; 383 } 384 static int 385 bnx_probe(device_t parent, cfdata_t match, void *aux) 386 { 387 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 388 389 if (bnx_lookup(pa) != NULL) 390 return (1); 391 392 return (0); 393 } 394 395 /****************************************************************************/ 396 /* Device attach function. */ 397 /* */ 398 /* Allocates device resources, performs secondary chip identification, */ 399 /* resets and initializes the hardware, and initializes driver instance */ 400 /* variables. */ 401 /* */ 402 /* Returns: */ 403 /* 0 on success, positive value on failure. */ 404 /****************************************************************************/ 405 void 406 bnx_attach(device_t parent, device_t self, void *aux) 407 { 408 const struct bnx_product *bp; 409 struct bnx_softc *sc = device_private(self); 410 struct pci_attach_args *pa = aux; 411 pci_chipset_tag_t pc = pa->pa_pc; 412 pci_intr_handle_t ih; 413 const char *intrstr = NULL; 414 u_int32_t command; 415 struct ifnet *ifp; 416 u_int32_t val; 417 pcireg_t memtype; 418 419 bp = bnx_lookup(pa); 420 if (bp == NULL) 421 panic("unknown device"); 422 423 sc->bnx_dev = self; 424 425 aprint_naive("\n"); 426 aprint_normal(": %s\n", bp->bp_name); 427 428 sc->bnx_pa = *pa; 429 430 /* 431 * Map control/status registers. 432 */ 433 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 434 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 435 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 436 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 437 438 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 439 aprint_error_dev(sc->bnx_dev, 440 "failed to enable memory mapping!\n"); 441 return; 442 } 443 444 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 445 switch (memtype) { 446 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 447 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 448 if (pci_mapreg_map(pa, BNX_PCI_BAR0, 449 memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, 450 NULL, &sc->bnx_size) == 0) 451 break; 452 default: 453 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 454 return; 455 } 456 457 if (pci_intr_map(pa, &ih)) { 458 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 459 goto bnx_attach_fail; 460 } 461 462 intrstr = pci_intr_string(pc, ih); 463 464 /* 465 * Configure byte swap and enable indirect register access. 466 * Rely on CPU to do target byte swapping on big endian systems. 467 * Access to registers outside of PCI configurtion space are not 468 * valid until this is done. 469 */ 470 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 471 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 472 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 473 474 /* Save ASIC revsion info. */ 475 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 476 477 /* Weed out any non-production controller revisions. */ 478 switch(BNX_CHIP_ID(sc)) { 479 case BNX_CHIP_ID_5706_A0: 480 case BNX_CHIP_ID_5706_A1: 481 case BNX_CHIP_ID_5708_A0: 482 case BNX_CHIP_ID_5708_B0: 483 aprint_error_dev(sc->bnx_dev, 484 "unsupported controller revision (%c%d)!\n", 485 ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A', 486 PCI_REVISION(pa->pa_class) & 0x0f); 487 goto bnx_attach_fail; 488 } 489 490 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 491 aprint_error_dev(sc->bnx_dev, 492 "SerDes controllers are not supported!\n"); 493 goto bnx_attach_fail; 494 } 495 496 /* 497 * Find the base address for shared memory access. 498 * Newer versions of bootcode use a signature and offset 499 * while older versions use a fixed address. 500 */ 501 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 502 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 503 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0); 504 else 505 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 506 507 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 508 509 /* Set initial device and PHY flags */ 510 sc->bnx_flags = 0; 511 sc->bnx_phy_flags = 0; 512 513 /* Get PCI bus information (speed and type). */ 514 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 515 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 516 u_int32_t clkreg; 517 518 sc->bnx_flags |= BNX_PCIX_FLAG; 519 520 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 521 522 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 523 switch (clkreg) { 524 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 525 sc->bus_speed_mhz = 133; 526 break; 527 528 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 529 sc->bus_speed_mhz = 100; 530 break; 531 532 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 533 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 534 sc->bus_speed_mhz = 66; 535 break; 536 537 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 538 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 539 sc->bus_speed_mhz = 50; 540 break; 541 542 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 543 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 544 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 545 sc->bus_speed_mhz = 33; 546 break; 547 } 548 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 549 sc->bus_speed_mhz = 66; 550 else 551 sc->bus_speed_mhz = 33; 552 553 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 554 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 555 556 /* Reset the controller. */ 557 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 558 goto bnx_attach_fail; 559 560 /* Initialize the controller. */ 561 if (bnx_chipinit(sc)) { 562 aprint_error_dev(sc->bnx_dev, 563 "Controller initialization failed!\n"); 564 goto bnx_attach_fail; 565 } 566 567 /* Perform NVRAM test. */ 568 if (bnx_nvram_test(sc)) { 569 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 570 goto bnx_attach_fail; 571 } 572 573 /* Fetch the permanent Ethernet MAC address. */ 574 bnx_get_mac_addr(sc); 575 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 576 ether_sprintf(sc->eaddr)); 577 578 /* 579 * Trip points control how many BDs 580 * should be ready before generating an 581 * interrupt while ticks control how long 582 * a BD can sit in the chain before 583 * generating an interrupt. Set the default 584 * values for the RX and TX rings. 585 */ 586 587 #ifdef BNX_DEBUG 588 /* Force more frequent interrupts. */ 589 sc->bnx_tx_quick_cons_trip_int = 1; 590 sc->bnx_tx_quick_cons_trip = 1; 591 sc->bnx_tx_ticks_int = 0; 592 sc->bnx_tx_ticks = 0; 593 594 sc->bnx_rx_quick_cons_trip_int = 1; 595 sc->bnx_rx_quick_cons_trip = 1; 596 sc->bnx_rx_ticks_int = 0; 597 sc->bnx_rx_ticks = 0; 598 #else 599 sc->bnx_tx_quick_cons_trip_int = 20; 600 sc->bnx_tx_quick_cons_trip = 20; 601 sc->bnx_tx_ticks_int = 80; 602 sc->bnx_tx_ticks = 80; 603 604 sc->bnx_rx_quick_cons_trip_int = 6; 605 sc->bnx_rx_quick_cons_trip = 6; 606 sc->bnx_rx_ticks_int = 18; 607 sc->bnx_rx_ticks = 18; 608 #endif 609 610 /* Update statistics once every second. */ 611 sc->bnx_stats_ticks = 1000000 & 0xffff00; 612 613 /* 614 * The copper based NetXtreme II controllers 615 * use an integrated PHY at address 1 while 616 * the SerDes controllers use a PHY at 617 * address 2. 618 */ 619 sc->bnx_phy_addr = 1; 620 621 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 622 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 623 sc->bnx_flags |= BNX_NO_WOL_FLAG; 624 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) { 625 sc->bnx_phy_addr = 2; 626 val = REG_RD_IND(sc, sc->bnx_shmem_base + 627 BNX_SHARED_HW_CFG_CONFIG); 628 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) 629 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 630 } 631 } 632 633 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 634 aprint_error_dev(sc->bnx_dev, 635 "SerDes is not supported by this driver!\n"); 636 goto bnx_attach_fail; 637 } 638 639 /* Allocate DMA memory resources. */ 640 sc->bnx_dmatag = pa->pa_dmat; 641 if (bnx_dma_alloc(sc)) { 642 aprint_error_dev(sc->bnx_dev, 643 "DMA resource allocation failed!\n"); 644 goto bnx_attach_fail; 645 } 646 647 /* Initialize the ifnet interface. */ 648 ifp = &sc->bnx_ec.ec_if; 649 ifp->if_softc = sc; 650 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 651 ifp->if_ioctl = bnx_ioctl; 652 ifp->if_stop = bnx_stop; 653 ifp->if_start = bnx_start; 654 ifp->if_init = bnx_init; 655 ifp->if_timer = 0; 656 ifp->if_watchdog = bnx_watchdog; 657 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 658 ifp->if_baudrate = IF_Gbps(2.5); 659 else 660 ifp->if_baudrate = IF_Gbps(1); 661 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 662 IFQ_SET_READY(&ifp->if_snd); 663 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 664 665 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 666 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 667 668 ifp->if_capabilities |= 669 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 670 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 671 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 672 673 /* Hookup IRQ last. */ 674 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 675 if (sc->bnx_intrhand == NULL) { 676 aprint_error_dev(self, "couldn't establish interrupt"); 677 if (intrstr != NULL) 678 aprint_error(" at %s", intrstr); 679 aprint_error("\n"); 680 goto bnx_attach_fail; 681 } 682 683 sc->bnx_mii.mii_ifp = ifp; 684 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 685 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 686 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 687 688 /* Look for our PHY. */ 689 ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, 690 bnx_ifmedia_sts); 691 mii_attach(self, &sc->bnx_mii, 0xffffffff, 692 MII_PHY_ANY, MII_OFFSET_ANY, 0); 693 694 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 695 aprint_error_dev(self, "no PHY found!\n"); 696 ifmedia_add(&sc->bnx_mii.mii_media, 697 IFM_ETHER|IFM_MANUAL, 0, NULL); 698 ifmedia_set(&sc->bnx_mii.mii_media, 699 IFM_ETHER|IFM_MANUAL); 700 } else { 701 ifmedia_set(&sc->bnx_mii.mii_media, 702 IFM_ETHER|IFM_AUTO); 703 } 704 705 /* Attach to the Ethernet interface list. */ 706 if_attach(ifp); 707 ether_ifattach(ifp,sc->eaddr); 708 709 callout_init(&sc->bnx_timeout, 0); 710 711 if (!pmf_device_register(self, NULL, NULL)) 712 aprint_error_dev(self, "couldn't establish power handler\n"); 713 else 714 pmf_class_network_register(self, ifp); 715 716 /* Print some important debugging info. */ 717 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 718 719 goto bnx_attach_exit; 720 721 bnx_attach_fail: 722 bnx_release_resources(sc); 723 724 bnx_attach_exit: 725 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 726 } 727 728 /****************************************************************************/ 729 /* Device detach function. */ 730 /* */ 731 /* Stops the controller, resets the controller, and releases resources. */ 732 /* */ 733 /* Returns: */ 734 /* 0 on success, positive value on failure. */ 735 /****************************************************************************/ 736 int 737 bnx_detach(device_t dev, int flags) 738 { 739 int s; 740 struct bnx_softc *sc; 741 struct ifnet *ifp; 742 743 sc = device_private(dev); 744 ifp = &sc->bnx_ec.ec_if; 745 746 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 747 748 /* Stop and reset the controller. */ 749 s = splnet(); 750 if (ifp->if_flags & IFF_RUNNING) 751 bnx_stop(ifp, 1); 752 splx(s); 753 754 pmf_device_deregister(dev); 755 ether_ifdetach(ifp); 756 if_detach(ifp); 757 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 758 759 /* Release all remaining resources. */ 760 bnx_release_resources(sc); 761 762 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 763 764 return(0); 765 } 766 767 /****************************************************************************/ 768 /* Indirect register read. */ 769 /* */ 770 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 771 /* configuration space. Using this mechanism avoids issues with posted */ 772 /* reads but is much slower than memory-mapped I/O. */ 773 /* */ 774 /* Returns: */ 775 /* The value of the register. */ 776 /****************************************************************************/ 777 u_int32_t 778 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 779 { 780 struct pci_attach_args *pa = &(sc->bnx_pa); 781 782 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 783 offset); 784 #ifdef BNX_DEBUG 785 { 786 u_int32_t val; 787 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 788 BNX_PCICFG_REG_WINDOW); 789 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 790 "val = 0x%08X\n", __func__, offset, val); 791 return (val); 792 } 793 #else 794 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 795 #endif 796 } 797 798 /****************************************************************************/ 799 /* Indirect register write. */ 800 /* */ 801 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 802 /* configuration space. Using this mechanism avoids issues with posted */ 803 /* writes but is muchh slower than memory-mapped I/O. */ 804 /* */ 805 /* Returns: */ 806 /* Nothing. */ 807 /****************************************************************************/ 808 void 809 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 810 { 811 struct pci_attach_args *pa = &(sc->bnx_pa); 812 813 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 814 __func__, offset, val); 815 816 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 817 offset); 818 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 819 } 820 821 /****************************************************************************/ 822 /* Context memory write. */ 823 /* */ 824 /* The NetXtreme II controller uses context memory to track connection */ 825 /* information for L2 and higher network protocols. */ 826 /* */ 827 /* Returns: */ 828 /* Nothing. */ 829 /****************************************************************************/ 830 void 831 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, 832 u_int32_t val) 833 { 834 835 DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 836 "val = 0x%08X\n", __func__, cid_addr, offset, val); 837 838 offset += cid_addr; 839 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 840 REG_WR(sc, BNX_CTX_DATA, val); 841 } 842 843 /****************************************************************************/ 844 /* PHY register read. */ 845 /* */ 846 /* Implements register reads on the MII bus. */ 847 /* */ 848 /* Returns: */ 849 /* The value of the register. */ 850 /****************************************************************************/ 851 int 852 bnx_miibus_read_reg(device_t dev, int phy, int reg) 853 { 854 struct bnx_softc *sc = device_private(dev); 855 u_int32_t val; 856 int i; 857 858 /* Make sure we are accessing the correct PHY address. */ 859 if (phy != sc->bnx_phy_addr) { 860 DBPRINT(sc, BNX_VERBOSE, 861 "Invalid PHY address %d for PHY read!\n", phy); 862 return(0); 863 } 864 865 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 866 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 867 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 868 869 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 870 REG_RD(sc, BNX_EMAC_MDIO_MODE); 871 872 DELAY(40); 873 } 874 875 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 876 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 877 BNX_EMAC_MDIO_COMM_START_BUSY; 878 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 879 880 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 881 DELAY(10); 882 883 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 884 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 885 DELAY(5); 886 887 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 888 val &= BNX_EMAC_MDIO_COMM_DATA; 889 890 break; 891 } 892 } 893 894 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 895 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 896 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 897 val = 0x0; 898 } else 899 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 900 901 DBPRINT(sc, BNX_EXCESSIVE, 902 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 903 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 904 905 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 906 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 907 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 908 909 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 910 REG_RD(sc, BNX_EMAC_MDIO_MODE); 911 912 DELAY(40); 913 } 914 915 return (val & 0xffff); 916 } 917 918 /****************************************************************************/ 919 /* PHY register write. */ 920 /* */ 921 /* Implements register writes on the MII bus. */ 922 /* */ 923 /* Returns: */ 924 /* The value of the register. */ 925 /****************************************************************************/ 926 void 927 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 928 { 929 struct bnx_softc *sc = device_private(dev); 930 u_int32_t val1; 931 int i; 932 933 /* Make sure we are accessing the correct PHY address. */ 934 if (phy != sc->bnx_phy_addr) { 935 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 936 phy); 937 return; 938 } 939 940 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 941 "val = 0x%04X\n", __func__, 942 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 943 944 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 945 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 946 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 947 948 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 949 REG_RD(sc, BNX_EMAC_MDIO_MODE); 950 951 DELAY(40); 952 } 953 954 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 955 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 956 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 957 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 958 959 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 960 DELAY(10); 961 962 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 963 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 964 DELAY(5); 965 break; 966 } 967 } 968 969 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 970 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 971 __LINE__); 972 } 973 974 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 975 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 976 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 977 978 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 979 REG_RD(sc, BNX_EMAC_MDIO_MODE); 980 981 DELAY(40); 982 } 983 } 984 985 /****************************************************************************/ 986 /* MII bus status change. */ 987 /* */ 988 /* Called by the MII bus driver when the PHY establishes link to set the */ 989 /* MAC interface registers. */ 990 /* */ 991 /* Returns: */ 992 /* Nothing. */ 993 /****************************************************************************/ 994 void 995 bnx_miibus_statchg(device_t dev) 996 { 997 struct bnx_softc *sc = device_private(dev); 998 struct mii_data *mii = &sc->bnx_mii; 999 1000 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT); 1001 1002 /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ 1003 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 1004 DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n"); 1005 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII); 1006 } else { 1007 DBPRINT(sc, BNX_INFO, "Setting MII interface.\n"); 1008 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII); 1009 } 1010 1011 /* Set half or full duplex based on the duplicity 1012 * negotiated by the PHY. 1013 */ 1014 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1015 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1016 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1017 } else { 1018 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1019 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1020 } 1021 } 1022 1023 /****************************************************************************/ 1024 /* Acquire NVRAM lock. */ 1025 /* */ 1026 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1027 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1028 /* for use by the driver. */ 1029 /* */ 1030 /* Returns: */ 1031 /* 0 on success, positive value on failure. */ 1032 /****************************************************************************/ 1033 int 1034 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1035 { 1036 u_int32_t val; 1037 int j; 1038 1039 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1040 1041 /* Request access to the flash interface. */ 1042 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1043 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1044 val = REG_RD(sc, BNX_NVM_SW_ARB); 1045 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1046 break; 1047 1048 DELAY(5); 1049 } 1050 1051 if (j >= NVRAM_TIMEOUT_COUNT) { 1052 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1053 return (EBUSY); 1054 } 1055 1056 return (0); 1057 } 1058 1059 /****************************************************************************/ 1060 /* Release NVRAM lock. */ 1061 /* */ 1062 /* When the caller is finished accessing NVRAM the lock must be released. */ 1063 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1064 /* for use by the driver. */ 1065 /* */ 1066 /* Returns: */ 1067 /* 0 on success, positive value on failure. */ 1068 /****************************************************************************/ 1069 int 1070 bnx_release_nvram_lock(struct bnx_softc *sc) 1071 { 1072 int j; 1073 u_int32_t val; 1074 1075 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1076 1077 /* Relinquish nvram interface. */ 1078 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1079 1080 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1081 val = REG_RD(sc, BNX_NVM_SW_ARB); 1082 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1083 break; 1084 1085 DELAY(5); 1086 } 1087 1088 if (j >= NVRAM_TIMEOUT_COUNT) { 1089 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1090 return (EBUSY); 1091 } 1092 1093 return (0); 1094 } 1095 1096 #ifdef BNX_NVRAM_WRITE_SUPPORT 1097 /****************************************************************************/ 1098 /* Enable NVRAM write access. */ 1099 /* */ 1100 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1101 /* */ 1102 /* Returns: */ 1103 /* 0 on success, positive value on failure. */ 1104 /****************************************************************************/ 1105 int 1106 bnx_enable_nvram_write(struct bnx_softc *sc) 1107 { 1108 u_int32_t val; 1109 1110 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1111 1112 val = REG_RD(sc, BNX_MISC_CFG); 1113 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1114 1115 if (!sc->bnx_flash_info->buffered) { 1116 int j; 1117 1118 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1119 REG_WR(sc, BNX_NVM_COMMAND, 1120 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1121 1122 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1123 DELAY(5); 1124 1125 val = REG_RD(sc, BNX_NVM_COMMAND); 1126 if (val & BNX_NVM_COMMAND_DONE) 1127 break; 1128 } 1129 1130 if (j >= NVRAM_TIMEOUT_COUNT) { 1131 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1132 return (EBUSY); 1133 } 1134 } 1135 1136 return (0); 1137 } 1138 1139 /****************************************************************************/ 1140 /* Disable NVRAM write access. */ 1141 /* */ 1142 /* When the caller is finished writing to NVRAM write access must be */ 1143 /* disabled. */ 1144 /* */ 1145 /* Returns: */ 1146 /* Nothing. */ 1147 /****************************************************************************/ 1148 void 1149 bnx_disable_nvram_write(struct bnx_softc *sc) 1150 { 1151 u_int32_t val; 1152 1153 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1154 1155 val = REG_RD(sc, BNX_MISC_CFG); 1156 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1157 } 1158 #endif 1159 1160 /****************************************************************************/ 1161 /* Enable NVRAM access. */ 1162 /* */ 1163 /* Before accessing NVRAM for read or write operations the caller must */ 1164 /* enabled NVRAM access. */ 1165 /* */ 1166 /* Returns: */ 1167 /* Nothing. */ 1168 /****************************************************************************/ 1169 void 1170 bnx_enable_nvram_access(struct bnx_softc *sc) 1171 { 1172 u_int32_t val; 1173 1174 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1175 1176 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1177 /* Enable both bits, even on read. */ 1178 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1179 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1180 } 1181 1182 /****************************************************************************/ 1183 /* Disable NVRAM access. */ 1184 /* */ 1185 /* When the caller is finished accessing NVRAM access must be disabled. */ 1186 /* */ 1187 /* Returns: */ 1188 /* Nothing. */ 1189 /****************************************************************************/ 1190 void 1191 bnx_disable_nvram_access(struct bnx_softc *sc) 1192 { 1193 u_int32_t val; 1194 1195 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1196 1197 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1198 1199 /* Disable both bits, even after read. */ 1200 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1201 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1202 } 1203 1204 #ifdef BNX_NVRAM_WRITE_SUPPORT 1205 /****************************************************************************/ 1206 /* Erase NVRAM page before writing. */ 1207 /* */ 1208 /* Non-buffered flash parts require that a page be erased before it is */ 1209 /* written. */ 1210 /* */ 1211 /* Returns: */ 1212 /* 0 on success, positive value on failure. */ 1213 /****************************************************************************/ 1214 int 1215 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1216 { 1217 u_int32_t cmd; 1218 int j; 1219 1220 /* Buffered flash doesn't require an erase. */ 1221 if (sc->bnx_flash_info->buffered) 1222 return (0); 1223 1224 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1225 1226 /* Build an erase command. */ 1227 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1228 BNX_NVM_COMMAND_DOIT; 1229 1230 /* 1231 * Clear the DONE bit separately, set the NVRAM adress to erase, 1232 * and issue the erase command. 1233 */ 1234 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1235 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1236 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1237 1238 /* Wait for completion. */ 1239 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1240 u_int32_t val; 1241 1242 DELAY(5); 1243 1244 val = REG_RD(sc, BNX_NVM_COMMAND); 1245 if (val & BNX_NVM_COMMAND_DONE) 1246 break; 1247 } 1248 1249 if (j >= NVRAM_TIMEOUT_COUNT) { 1250 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1251 return (EBUSY); 1252 } 1253 1254 return (0); 1255 } 1256 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1257 1258 /****************************************************************************/ 1259 /* Read a dword (32 bits) from NVRAM. */ 1260 /* */ 1261 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1262 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1263 /* */ 1264 /* Returns: */ 1265 /* 0 on success and the 32 bit value read, positive value on failure. */ 1266 /****************************************************************************/ 1267 int 1268 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1269 u_int8_t *ret_val, u_int32_t cmd_flags) 1270 { 1271 u_int32_t cmd; 1272 int i, rc = 0; 1273 1274 /* Build the command word. */ 1275 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1276 1277 /* Calculate the offset for buffered flash. */ 1278 if (sc->bnx_flash_info->buffered) 1279 offset = ((offset / sc->bnx_flash_info->page_size) << 1280 sc->bnx_flash_info->page_bits) + 1281 (offset % sc->bnx_flash_info->page_size); 1282 1283 /* 1284 * Clear the DONE bit separately, set the address to read, 1285 * and issue the read. 1286 */ 1287 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1288 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1289 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1290 1291 /* Wait for completion. */ 1292 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1293 u_int32_t val; 1294 1295 DELAY(5); 1296 1297 val = REG_RD(sc, BNX_NVM_COMMAND); 1298 if (val & BNX_NVM_COMMAND_DONE) { 1299 val = REG_RD(sc, BNX_NVM_READ); 1300 1301 val = bnx_be32toh(val); 1302 memcpy(ret_val, &val, 4); 1303 break; 1304 } 1305 } 1306 1307 /* Check for errors. */ 1308 if (i >= NVRAM_TIMEOUT_COUNT) { 1309 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1310 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1311 rc = EBUSY; 1312 } 1313 1314 return(rc); 1315 } 1316 1317 #ifdef BNX_NVRAM_WRITE_SUPPORT 1318 /****************************************************************************/ 1319 /* Write a dword (32 bits) to NVRAM. */ 1320 /* */ 1321 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1322 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1323 /* enabled NVRAM write access. */ 1324 /* */ 1325 /* Returns: */ 1326 /* 0 on success, positive value on failure. */ 1327 /****************************************************************************/ 1328 int 1329 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1330 u_int32_t cmd_flags) 1331 { 1332 u_int32_t cmd, val32; 1333 int j; 1334 1335 /* Build the command word. */ 1336 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1337 1338 /* Calculate the offset for buffered flash. */ 1339 if (sc->bnx_flash_info->buffered) 1340 offset = ((offset / sc->bnx_flash_info->page_size) << 1341 sc->bnx_flash_info->page_bits) + 1342 (offset % sc->bnx_flash_info->page_size); 1343 1344 /* 1345 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1346 * set the NVRAM address to write, and issue the write command 1347 */ 1348 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1349 memcpy(&val32, val, 4); 1350 val32 = htobe32(val32); 1351 REG_WR(sc, BNX_NVM_WRITE, val32); 1352 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1353 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1354 1355 /* Wait for completion. */ 1356 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1357 DELAY(5); 1358 1359 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1360 break; 1361 } 1362 if (j >= NVRAM_TIMEOUT_COUNT) { 1363 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1364 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1365 return (EBUSY); 1366 } 1367 1368 return (0); 1369 } 1370 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1371 1372 /****************************************************************************/ 1373 /* Initialize NVRAM access. */ 1374 /* */ 1375 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1376 /* access that device. */ 1377 /* */ 1378 /* Returns: */ 1379 /* 0 on success, positive value on failure. */ 1380 /****************************************************************************/ 1381 int 1382 bnx_init_nvram(struct bnx_softc *sc) 1383 { 1384 u_int32_t val; 1385 int j, entry_count, rc; 1386 struct flash_spec *flash; 1387 1388 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1389 1390 /* Determine the selected interface. */ 1391 val = REG_RD(sc, BNX_NVM_CFG1); 1392 1393 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1394 1395 rc = 0; 1396 1397 /* 1398 * Flash reconfiguration is required to support additional 1399 * NVRAM devices not directly supported in hardware. 1400 * Check if the flash interface was reconfigured 1401 * by the bootcode. 1402 */ 1403 1404 if (val & 0x40000000) { 1405 /* Flash interface reconfigured by bootcode. */ 1406 1407 DBPRINT(sc,BNX_INFO_LOAD, 1408 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1409 1410 for (j = 0, flash = &flash_table[0]; j < entry_count; 1411 j++, flash++) { 1412 if ((val & FLASH_BACKUP_STRAP_MASK) == 1413 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1414 sc->bnx_flash_info = flash; 1415 break; 1416 } 1417 } 1418 } else { 1419 /* Flash interface not yet reconfigured. */ 1420 u_int32_t mask; 1421 1422 DBPRINT(sc,BNX_INFO_LOAD, 1423 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1424 1425 if (val & (1 << 23)) 1426 mask = FLASH_BACKUP_STRAP_MASK; 1427 else 1428 mask = FLASH_STRAP_MASK; 1429 1430 /* Look for the matching NVRAM device configuration data. */ 1431 for (j = 0, flash = &flash_table[0]; j < entry_count; 1432 j++, flash++) { 1433 /* Check if the dev matches any of the known devices. */ 1434 if ((val & mask) == (flash->strapping & mask)) { 1435 /* Found a device match. */ 1436 sc->bnx_flash_info = flash; 1437 1438 /* Request access to the flash interface. */ 1439 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1440 return (rc); 1441 1442 /* Reconfigure the flash interface. */ 1443 bnx_enable_nvram_access(sc); 1444 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1445 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1446 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1447 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1448 bnx_disable_nvram_access(sc); 1449 bnx_release_nvram_lock(sc); 1450 1451 break; 1452 } 1453 } 1454 } 1455 1456 /* Check if a matching device was found. */ 1457 if (j == entry_count) { 1458 sc->bnx_flash_info = NULL; 1459 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1460 __FILE__, __LINE__); 1461 rc = ENODEV; 1462 } 1463 1464 /* Write the flash config data to the shared memory interface. */ 1465 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1466 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1467 if (val) 1468 sc->bnx_flash_size = val; 1469 else 1470 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1471 1472 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1473 "0x%08X\n", sc->bnx_flash_info->total_size); 1474 1475 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1476 1477 return (rc); 1478 } 1479 1480 /****************************************************************************/ 1481 /* Read an arbitrary range of data from NVRAM. */ 1482 /* */ 1483 /* Prepares the NVRAM interface for access and reads the requested data */ 1484 /* into the supplied buffer. */ 1485 /* */ 1486 /* Returns: */ 1487 /* 0 on success and the data read, positive value on failure. */ 1488 /****************************************************************************/ 1489 int 1490 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1491 int buf_size) 1492 { 1493 int rc = 0; 1494 u_int32_t cmd_flags, offset32, len32, extra; 1495 1496 if (buf_size == 0) 1497 return (0); 1498 1499 /* Request access to the flash interface. */ 1500 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1501 return (rc); 1502 1503 /* Enable access to flash interface */ 1504 bnx_enable_nvram_access(sc); 1505 1506 len32 = buf_size; 1507 offset32 = offset; 1508 extra = 0; 1509 1510 cmd_flags = 0; 1511 1512 if (offset32 & 3) { 1513 u_int8_t buf[4]; 1514 u_int32_t pre_len; 1515 1516 offset32 &= ~3; 1517 pre_len = 4 - (offset & 3); 1518 1519 if (pre_len >= len32) { 1520 pre_len = len32; 1521 cmd_flags = 1522 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1523 } else 1524 cmd_flags = BNX_NVM_COMMAND_FIRST; 1525 1526 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1527 1528 if (rc) 1529 return (rc); 1530 1531 memcpy(ret_buf, buf + (offset & 3), pre_len); 1532 1533 offset32 += 4; 1534 ret_buf += pre_len; 1535 len32 -= pre_len; 1536 } 1537 1538 if (len32 & 3) { 1539 extra = 4 - (len32 & 3); 1540 len32 = (len32 + 4) & ~3; 1541 } 1542 1543 if (len32 == 4) { 1544 u_int8_t buf[4]; 1545 1546 if (cmd_flags) 1547 cmd_flags = BNX_NVM_COMMAND_LAST; 1548 else 1549 cmd_flags = 1550 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1551 1552 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1553 1554 memcpy(ret_buf, buf, 4 - extra); 1555 } else if (len32 > 0) { 1556 u_int8_t buf[4]; 1557 1558 /* Read the first word. */ 1559 if (cmd_flags) 1560 cmd_flags = 0; 1561 else 1562 cmd_flags = BNX_NVM_COMMAND_FIRST; 1563 1564 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1565 1566 /* Advance to the next dword. */ 1567 offset32 += 4; 1568 ret_buf += 4; 1569 len32 -= 4; 1570 1571 while (len32 > 4 && rc == 0) { 1572 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1573 1574 /* Advance to the next dword. */ 1575 offset32 += 4; 1576 ret_buf += 4; 1577 len32 -= 4; 1578 } 1579 1580 if (rc) 1581 return (rc); 1582 1583 cmd_flags = BNX_NVM_COMMAND_LAST; 1584 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1585 1586 memcpy(ret_buf, buf, 4 - extra); 1587 } 1588 1589 /* Disable access to flash interface and release the lock. */ 1590 bnx_disable_nvram_access(sc); 1591 bnx_release_nvram_lock(sc); 1592 1593 return (rc); 1594 } 1595 1596 #ifdef BNX_NVRAM_WRITE_SUPPORT 1597 /****************************************************************************/ 1598 /* Write an arbitrary range of data from NVRAM. */ 1599 /* */ 1600 /* Prepares the NVRAM interface for write access and writes the requested */ 1601 /* data from the supplied buffer. The caller is responsible for */ 1602 /* calculating any appropriate CRCs. */ 1603 /* */ 1604 /* Returns: */ 1605 /* 0 on success, positive value on failure. */ 1606 /****************************************************************************/ 1607 int 1608 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1609 int buf_size) 1610 { 1611 u_int32_t written, offset32, len32; 1612 u_int8_t *buf, start[4], end[4]; 1613 int rc = 0; 1614 int align_start, align_end; 1615 1616 buf = data_buf; 1617 offset32 = offset; 1618 len32 = buf_size; 1619 align_start = align_end = 0; 1620 1621 if ((align_start = (offset32 & 3))) { 1622 offset32 &= ~3; 1623 len32 += align_start; 1624 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1625 return (rc); 1626 } 1627 1628 if (len32 & 3) { 1629 if ((len32 > 4) || !align_start) { 1630 align_end = 4 - (len32 & 3); 1631 len32 += align_end; 1632 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1633 end, 4))) { 1634 return (rc); 1635 } 1636 } 1637 } 1638 1639 if (align_start || align_end) { 1640 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1641 if (buf == 0) 1642 return (ENOMEM); 1643 1644 if (align_start) 1645 memcpy(buf, start, 4); 1646 1647 if (align_end) 1648 memcpy(buf + len32 - 4, end, 4); 1649 1650 memcpy(buf + align_start, data_buf, buf_size); 1651 } 1652 1653 written = 0; 1654 while ((written < len32) && (rc == 0)) { 1655 u_int32_t page_start, page_end, data_start, data_end; 1656 u_int32_t addr, cmd_flags; 1657 int i; 1658 u_int8_t flash_buffer[264]; 1659 1660 /* Find the page_start addr */ 1661 page_start = offset32 + written; 1662 page_start -= (page_start % sc->bnx_flash_info->page_size); 1663 /* Find the page_end addr */ 1664 page_end = page_start + sc->bnx_flash_info->page_size; 1665 /* Find the data_start addr */ 1666 data_start = (written == 0) ? offset32 : page_start; 1667 /* Find the data_end addr */ 1668 data_end = (page_end > offset32 + len32) ? 1669 (offset32 + len32) : page_end; 1670 1671 /* Request access to the flash interface. */ 1672 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1673 goto nvram_write_end; 1674 1675 /* Enable access to flash interface */ 1676 bnx_enable_nvram_access(sc); 1677 1678 cmd_flags = BNX_NVM_COMMAND_FIRST; 1679 if (sc->bnx_flash_info->buffered == 0) { 1680 int j; 1681 1682 /* Read the whole page into the buffer 1683 * (non-buffer flash only) */ 1684 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1685 if (j == (sc->bnx_flash_info->page_size - 4)) 1686 cmd_flags |= BNX_NVM_COMMAND_LAST; 1687 1688 rc = bnx_nvram_read_dword(sc, 1689 page_start + j, 1690 &flash_buffer[j], 1691 cmd_flags); 1692 1693 if (rc) 1694 goto nvram_write_end; 1695 1696 cmd_flags = 0; 1697 } 1698 } 1699 1700 /* Enable writes to flash interface (unlock write-protect) */ 1701 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1702 goto nvram_write_end; 1703 1704 /* Erase the page */ 1705 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1706 goto nvram_write_end; 1707 1708 /* Re-enable the write again for the actual write */ 1709 bnx_enable_nvram_write(sc); 1710 1711 /* Loop to write back the buffer data from page_start to 1712 * data_start */ 1713 i = 0; 1714 if (sc->bnx_flash_info->buffered == 0) { 1715 for (addr = page_start; addr < data_start; 1716 addr += 4, i += 4) { 1717 1718 rc = bnx_nvram_write_dword(sc, addr, 1719 &flash_buffer[i], cmd_flags); 1720 1721 if (rc != 0) 1722 goto nvram_write_end; 1723 1724 cmd_flags = 0; 1725 } 1726 } 1727 1728 /* Loop to write the new data from data_start to data_end */ 1729 for (addr = data_start; addr < data_end; addr += 4, i++) { 1730 if ((addr == page_end - 4) || 1731 ((sc->bnx_flash_info->buffered) && 1732 (addr == data_end - 4))) { 1733 1734 cmd_flags |= BNX_NVM_COMMAND_LAST; 1735 } 1736 1737 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1738 1739 if (rc != 0) 1740 goto nvram_write_end; 1741 1742 cmd_flags = 0; 1743 buf += 4; 1744 } 1745 1746 /* Loop to write back the buffer data from data_end 1747 * to page_end */ 1748 if (sc->bnx_flash_info->buffered == 0) { 1749 for (addr = data_end; addr < page_end; 1750 addr += 4, i += 4) { 1751 1752 if (addr == page_end-4) 1753 cmd_flags = BNX_NVM_COMMAND_LAST; 1754 1755 rc = bnx_nvram_write_dword(sc, addr, 1756 &flash_buffer[i], cmd_flags); 1757 1758 if (rc != 0) 1759 goto nvram_write_end; 1760 1761 cmd_flags = 0; 1762 } 1763 } 1764 1765 /* Disable writes to flash interface (lock write-protect) */ 1766 bnx_disable_nvram_write(sc); 1767 1768 /* Disable access to flash interface */ 1769 bnx_disable_nvram_access(sc); 1770 bnx_release_nvram_lock(sc); 1771 1772 /* Increment written */ 1773 written += data_end - data_start; 1774 } 1775 1776 nvram_write_end: 1777 if (align_start || align_end) 1778 free(buf, M_DEVBUF); 1779 1780 return (rc); 1781 } 1782 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1783 1784 /****************************************************************************/ 1785 /* Verifies that NVRAM is accessible and contains valid data. */ 1786 /* */ 1787 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1788 /* correct. */ 1789 /* */ 1790 /* Returns: */ 1791 /* 0 on success, positive value on failure. */ 1792 /****************************************************************************/ 1793 int 1794 bnx_nvram_test(struct bnx_softc *sc) 1795 { 1796 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1797 u_int8_t *data = (u_int8_t *) buf; 1798 int rc = 0; 1799 u_int32_t magic, csum; 1800 1801 /* 1802 * Check that the device NVRAM is valid by reading 1803 * the magic value at offset 0. 1804 */ 1805 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1806 goto bnx_nvram_test_done; 1807 1808 magic = bnx_be32toh(buf[0]); 1809 if (magic != BNX_NVRAM_MAGIC) { 1810 rc = ENODEV; 1811 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1812 "Expected: 0x%08X, Found: 0x%08X\n", 1813 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1814 goto bnx_nvram_test_done; 1815 } 1816 1817 /* 1818 * Verify that the device NVRAM includes valid 1819 * configuration data. 1820 */ 1821 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1822 goto bnx_nvram_test_done; 1823 1824 csum = ether_crc32_le(data, 0x100); 1825 if (csum != BNX_CRC32_RESIDUAL) { 1826 rc = ENODEV; 1827 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1828 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1829 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1830 goto bnx_nvram_test_done; 1831 } 1832 1833 csum = ether_crc32_le(data + 0x100, 0x100); 1834 if (csum != BNX_CRC32_RESIDUAL) { 1835 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1836 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1837 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1838 rc = ENODEV; 1839 } 1840 1841 bnx_nvram_test_done: 1842 return (rc); 1843 } 1844 1845 /****************************************************************************/ 1846 /* Free any DMA memory owned by the driver. */ 1847 /* */ 1848 /* Scans through each data structre that requires DMA memory and frees */ 1849 /* the memory if allocated. */ 1850 /* */ 1851 /* Returns: */ 1852 /* Nothing. */ 1853 /****************************************************************************/ 1854 void 1855 bnx_dma_free(struct bnx_softc *sc) 1856 { 1857 int i; 1858 1859 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1860 1861 /* Destroy the status block. */ 1862 if (sc->status_block != NULL && sc->status_map != NULL) { 1863 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 1864 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 1865 BNX_STATUS_BLK_SZ); 1866 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 1867 sc->status_rseg); 1868 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 1869 sc->status_block = NULL; 1870 sc->status_map = NULL; 1871 } 1872 1873 /* Destroy the statistics block. */ 1874 if (sc->stats_block != NULL && sc->stats_map != NULL) { 1875 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 1876 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 1877 BNX_STATS_BLK_SZ); 1878 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 1879 sc->stats_rseg); 1880 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 1881 sc->stats_block = NULL; 1882 sc->stats_map = NULL; 1883 } 1884 1885 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 1886 for (i = 0; i < TX_PAGES; i++ ) { 1887 if (sc->tx_bd_chain[i] != NULL && 1888 sc->tx_bd_chain_map[i] != NULL) { 1889 bus_dmamap_unload(sc->bnx_dmatag, 1890 sc->tx_bd_chain_map[i]); 1891 bus_dmamem_unmap(sc->bnx_dmatag, 1892 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 1893 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 1894 sc->tx_bd_chain_rseg[i]); 1895 bus_dmamap_destroy(sc->bnx_dmatag, 1896 sc->tx_bd_chain_map[i]); 1897 sc->tx_bd_chain[i] = NULL; 1898 sc->tx_bd_chain_map[i] = NULL; 1899 } 1900 } 1901 1902 /* Unload and destroy the TX mbuf maps. */ 1903 for (i = 0; i < TOTAL_TX_BD; i++) { 1904 if (sc->tx_mbuf_map[i] != NULL) { 1905 bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1906 bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1907 } 1908 } 1909 1910 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 1911 for (i = 0; i < RX_PAGES; i++ ) { 1912 if (sc->rx_bd_chain[i] != NULL && 1913 sc->rx_bd_chain_map[i] != NULL) { 1914 bus_dmamap_unload(sc->bnx_dmatag, 1915 sc->rx_bd_chain_map[i]); 1916 bus_dmamem_unmap(sc->bnx_dmatag, 1917 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 1918 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 1919 sc->rx_bd_chain_rseg[i]); 1920 1921 bus_dmamap_destroy(sc->bnx_dmatag, 1922 sc->rx_bd_chain_map[i]); 1923 sc->rx_bd_chain[i] = NULL; 1924 sc->rx_bd_chain_map[i] = NULL; 1925 } 1926 } 1927 1928 /* Unload and destroy the RX mbuf maps. */ 1929 for (i = 0; i < TOTAL_RX_BD; i++) { 1930 if (sc->rx_mbuf_map[i] != NULL) { 1931 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1932 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1933 } 1934 } 1935 1936 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1937 } 1938 1939 /****************************************************************************/ 1940 /* Allocate any DMA memory needed by the driver. */ 1941 /* */ 1942 /* Allocates DMA memory needed for the various global structures needed by */ 1943 /* hardware. */ 1944 /* */ 1945 /* Returns: */ 1946 /* 0 for success, positive value for failure. */ 1947 /****************************************************************************/ 1948 int 1949 bnx_dma_alloc(struct bnx_softc *sc) 1950 { 1951 int i, rc = 0; 1952 1953 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1954 1955 /* 1956 * Allocate DMA memory for the status block, map the memory into DMA 1957 * space, and fetch the physical address of the block. 1958 */ 1959 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 1960 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 1961 aprint_error_dev(sc->bnx_dev, 1962 "Could not create status block DMA map!\n"); 1963 rc = ENOMEM; 1964 goto bnx_dma_alloc_exit; 1965 } 1966 1967 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1968 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 1969 &sc->status_rseg, BUS_DMA_NOWAIT)) { 1970 aprint_error_dev(sc->bnx_dev, 1971 "Could not allocate status block DMA memory!\n"); 1972 rc = ENOMEM; 1973 goto bnx_dma_alloc_exit; 1974 } 1975 1976 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 1977 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 1978 aprint_error_dev(sc->bnx_dev, 1979 "Could not map status block DMA memory!\n"); 1980 rc = ENOMEM; 1981 goto bnx_dma_alloc_exit; 1982 } 1983 1984 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 1985 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 1986 aprint_error_dev(sc->bnx_dev, 1987 "Could not load status block DMA memory!\n"); 1988 rc = ENOMEM; 1989 goto bnx_dma_alloc_exit; 1990 } 1991 1992 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 1993 bzero(sc->status_block, BNX_STATUS_BLK_SZ); 1994 1995 /* DRC - Fix for 64 bit addresses. */ 1996 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 1997 (u_int32_t) sc->status_block_paddr); 1998 1999 /* 2000 * Allocate DMA memory for the statistics block, map the memory into 2001 * DMA space, and fetch the physical address of the block. 2002 */ 2003 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2004 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2005 aprint_error_dev(sc->bnx_dev, 2006 "Could not create stats block DMA map!\n"); 2007 rc = ENOMEM; 2008 goto bnx_dma_alloc_exit; 2009 } 2010 2011 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2012 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2013 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2014 aprint_error_dev(sc->bnx_dev, 2015 "Could not allocate stats block DMA memory!\n"); 2016 rc = ENOMEM; 2017 goto bnx_dma_alloc_exit; 2018 } 2019 2020 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2021 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2022 aprint_error_dev(sc->bnx_dev, 2023 "Could not map stats block DMA memory!\n"); 2024 rc = ENOMEM; 2025 goto bnx_dma_alloc_exit; 2026 } 2027 2028 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2029 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2030 aprint_error_dev(sc->bnx_dev, 2031 "Could not load status block DMA memory!\n"); 2032 rc = ENOMEM; 2033 goto bnx_dma_alloc_exit; 2034 } 2035 2036 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2037 bzero(sc->stats_block, BNX_STATS_BLK_SZ); 2038 2039 /* DRC - Fix for 64 bit address. */ 2040 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2041 (u_int32_t) sc->stats_block_paddr); 2042 2043 /* 2044 * Allocate DMA memory for the TX buffer descriptor chain, 2045 * and fetch the physical address of the block. 2046 */ 2047 for (i = 0; i < TX_PAGES; i++) { 2048 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2049 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2050 &sc->tx_bd_chain_map[i])) { 2051 aprint_error_dev(sc->bnx_dev, 2052 "Could not create Tx desc %d DMA map!\n", i); 2053 rc = ENOMEM; 2054 goto bnx_dma_alloc_exit; 2055 } 2056 2057 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2058 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2059 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2060 aprint_error_dev(sc->bnx_dev, 2061 "Could not allocate TX desc %d DMA memory!\n", 2062 i); 2063 rc = ENOMEM; 2064 goto bnx_dma_alloc_exit; 2065 } 2066 2067 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2068 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2069 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2070 aprint_error_dev(sc->bnx_dev, 2071 "Could not map TX desc %d DMA memory!\n", i); 2072 rc = ENOMEM; 2073 goto bnx_dma_alloc_exit; 2074 } 2075 2076 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2077 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2078 BUS_DMA_NOWAIT)) { 2079 aprint_error_dev(sc->bnx_dev, 2080 "Could not load TX desc %d DMA memory!\n", i); 2081 rc = ENOMEM; 2082 goto bnx_dma_alloc_exit; 2083 } 2084 2085 sc->tx_bd_chain_paddr[i] = 2086 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2087 2088 /* DRC - Fix for 64 bit systems. */ 2089 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2090 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2091 } 2092 2093 /* 2094 * Create DMA maps for the TX buffer mbufs. 2095 */ 2096 for (i = 0; i < TOTAL_TX_BD; i++) { 2097 if (bus_dmamap_create(sc->bnx_dmatag, 2098 MCLBYTES * BNX_MAX_SEGMENTS, 2099 USABLE_TX_BD - BNX_TX_SLACK_SPACE, 2100 MCLBYTES, 0, BUS_DMA_NOWAIT, 2101 &sc->tx_mbuf_map[i])) { 2102 aprint_error_dev(sc->bnx_dev, 2103 "Could not create Tx mbuf %d DMA map!\n", i); 2104 rc = ENOMEM; 2105 goto bnx_dma_alloc_exit; 2106 } 2107 } 2108 2109 /* 2110 * Allocate DMA memory for the Rx buffer descriptor chain, 2111 * and fetch the physical address of the block. 2112 */ 2113 for (i = 0; i < RX_PAGES; i++) { 2114 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2115 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2116 &sc->rx_bd_chain_map[i])) { 2117 aprint_error_dev(sc->bnx_dev, 2118 "Could not create Rx desc %d DMA map!\n", i); 2119 rc = ENOMEM; 2120 goto bnx_dma_alloc_exit; 2121 } 2122 2123 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2124 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2125 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2126 aprint_error_dev(sc->bnx_dev, 2127 "Could not allocate Rx desc %d DMA memory!\n", i); 2128 rc = ENOMEM; 2129 goto bnx_dma_alloc_exit; 2130 } 2131 2132 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2133 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2134 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2135 aprint_error_dev(sc->bnx_dev, 2136 "Could not map Rx desc %d DMA memory!\n", i); 2137 rc = ENOMEM; 2138 goto bnx_dma_alloc_exit; 2139 } 2140 2141 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2142 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2143 BUS_DMA_NOWAIT)) { 2144 aprint_error_dev(sc->bnx_dev, 2145 "Could not load Rx desc %d DMA memory!\n", i); 2146 rc = ENOMEM; 2147 goto bnx_dma_alloc_exit; 2148 } 2149 2150 bzero(sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2151 sc->rx_bd_chain_paddr[i] = 2152 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2153 2154 /* DRC - Fix for 64 bit systems. */ 2155 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2156 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2157 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2158 0, BNX_RX_CHAIN_PAGE_SZ, 2159 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2160 } 2161 2162 /* 2163 * Create DMA maps for the Rx buffer mbufs. 2164 */ 2165 for (i = 0; i < TOTAL_RX_BD; i++) { 2166 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU, 2167 BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT, 2168 &sc->rx_mbuf_map[i])) { 2169 aprint_error_dev(sc->bnx_dev, 2170 "Could not create Rx mbuf %d DMA map!\n", i); 2171 rc = ENOMEM; 2172 goto bnx_dma_alloc_exit; 2173 } 2174 } 2175 2176 bnx_dma_alloc_exit: 2177 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2178 2179 return(rc); 2180 } 2181 2182 /****************************************************************************/ 2183 /* Release all resources used by the driver. */ 2184 /* */ 2185 /* Releases all resources acquired by the driver including interrupts, */ 2186 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2187 /* */ 2188 /* Returns: */ 2189 /* Nothing. */ 2190 /****************************************************************************/ 2191 void 2192 bnx_release_resources(struct bnx_softc *sc) 2193 { 2194 int i; 2195 struct pci_attach_args *pa = &(sc->bnx_pa); 2196 2197 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2198 2199 bnx_dma_free(sc); 2200 2201 if (sc->bnx_intrhand != NULL) 2202 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2203 2204 if (sc->bnx_size) 2205 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2206 2207 for (i = 0; i < TOTAL_RX_BD; i++) 2208 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2209 2210 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2211 } 2212 2213 /****************************************************************************/ 2214 /* Firmware synchronization. */ 2215 /* */ 2216 /* Before performing certain events such as a chip reset, synchronize with */ 2217 /* the firmware first. */ 2218 /* */ 2219 /* Returns: */ 2220 /* 0 for success, positive value for failure. */ 2221 /****************************************************************************/ 2222 int 2223 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2224 { 2225 int i, rc = 0; 2226 u_int32_t val; 2227 2228 /* Don't waste any time if we've timed out before. */ 2229 if (sc->bnx_fw_timed_out) { 2230 rc = EBUSY; 2231 goto bnx_fw_sync_exit; 2232 } 2233 2234 /* Increment the message sequence number. */ 2235 sc->bnx_fw_wr_seq++; 2236 msg_data |= sc->bnx_fw_wr_seq; 2237 2238 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2239 msg_data); 2240 2241 /* Send the message to the bootcode driver mailbox. */ 2242 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2243 2244 /* Wait for the bootcode to acknowledge the message. */ 2245 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2246 /* Check for a response in the bootcode firmware mailbox. */ 2247 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2248 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2249 break; 2250 DELAY(1000); 2251 } 2252 2253 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2254 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2255 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2256 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2257 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2258 2259 msg_data &= ~BNX_DRV_MSG_CODE; 2260 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2261 2262 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2263 2264 sc->bnx_fw_timed_out = 1; 2265 rc = EBUSY; 2266 } 2267 2268 bnx_fw_sync_exit: 2269 return (rc); 2270 } 2271 2272 /****************************************************************************/ 2273 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2274 /* */ 2275 /* Returns: */ 2276 /* Nothing. */ 2277 /****************************************************************************/ 2278 void 2279 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2280 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2281 { 2282 int i; 2283 u_int32_t val; 2284 2285 for (i = 0; i < rv2p_code_len; i += 8) { 2286 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2287 rv2p_code++; 2288 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2289 rv2p_code++; 2290 2291 if (rv2p_proc == RV2P_PROC1) { 2292 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2293 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2294 } 2295 else { 2296 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2297 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2298 } 2299 } 2300 2301 /* Reset the processor, un-stall is done later. */ 2302 if (rv2p_proc == RV2P_PROC1) 2303 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2304 else 2305 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2306 } 2307 2308 /****************************************************************************/ 2309 /* Load RISC processor firmware. */ 2310 /* */ 2311 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2312 /* associated with a particular processor. */ 2313 /* */ 2314 /* Returns: */ 2315 /* Nothing. */ 2316 /****************************************************************************/ 2317 void 2318 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2319 struct fw_info *fw) 2320 { 2321 u_int32_t offset; 2322 u_int32_t val; 2323 2324 /* Halt the CPU. */ 2325 val = REG_RD_IND(sc, cpu_reg->mode); 2326 val |= cpu_reg->mode_value_halt; 2327 REG_WR_IND(sc, cpu_reg->mode, val); 2328 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2329 2330 /* Load the Text area. */ 2331 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2332 if (fw->text) { 2333 int j; 2334 2335 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2336 REG_WR_IND(sc, offset, fw->text[j]); 2337 } 2338 2339 /* Load the Data area. */ 2340 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2341 if (fw->data) { 2342 int j; 2343 2344 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2345 REG_WR_IND(sc, offset, fw->data[j]); 2346 } 2347 2348 /* Load the SBSS area. */ 2349 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2350 if (fw->sbss) { 2351 int j; 2352 2353 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2354 REG_WR_IND(sc, offset, fw->sbss[j]); 2355 } 2356 2357 /* Load the BSS area. */ 2358 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2359 if (fw->bss) { 2360 int j; 2361 2362 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2363 REG_WR_IND(sc, offset, fw->bss[j]); 2364 } 2365 2366 /* Load the Read-Only area. */ 2367 offset = cpu_reg->spad_base + 2368 (fw->rodata_addr - cpu_reg->mips_view_base); 2369 if (fw->rodata) { 2370 int j; 2371 2372 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2373 REG_WR_IND(sc, offset, fw->rodata[j]); 2374 } 2375 2376 /* Clear the pre-fetch instruction. */ 2377 REG_WR_IND(sc, cpu_reg->inst, 0); 2378 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2379 2380 /* Start the CPU. */ 2381 val = REG_RD_IND(sc, cpu_reg->mode); 2382 val &= ~cpu_reg->mode_value_halt; 2383 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2384 REG_WR_IND(sc, cpu_reg->mode, val); 2385 } 2386 2387 /****************************************************************************/ 2388 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2389 /* */ 2390 /* Loads the firmware for each CPU and starts the CPU. */ 2391 /* */ 2392 /* Returns: */ 2393 /* Nothing. */ 2394 /****************************************************************************/ 2395 void 2396 bnx_init_cpus(struct bnx_softc *sc) 2397 { 2398 struct cpu_reg cpu_reg; 2399 struct fw_info fw; 2400 2401 /* Initialize the RV2P processor. */ 2402 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2403 RV2P_PROC1); 2404 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2405 RV2P_PROC2); 2406 2407 /* Initialize the RX Processor. */ 2408 cpu_reg.mode = BNX_RXP_CPU_MODE; 2409 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2410 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2411 cpu_reg.state = BNX_RXP_CPU_STATE; 2412 cpu_reg.state_value_clear = 0xffffff; 2413 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2414 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2415 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2416 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2417 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2418 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2419 cpu_reg.mips_view_base = 0x8000000; 2420 2421 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2422 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2423 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2424 fw.start_addr = bnx_RXP_b06FwStartAddr; 2425 2426 fw.text_addr = bnx_RXP_b06FwTextAddr; 2427 fw.text_len = bnx_RXP_b06FwTextLen; 2428 fw.text_index = 0; 2429 fw.text = bnx_RXP_b06FwText; 2430 2431 fw.data_addr = bnx_RXP_b06FwDataAddr; 2432 fw.data_len = bnx_RXP_b06FwDataLen; 2433 fw.data_index = 0; 2434 fw.data = bnx_RXP_b06FwData; 2435 2436 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2437 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2438 fw.sbss_index = 0; 2439 fw.sbss = bnx_RXP_b06FwSbss; 2440 2441 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2442 fw.bss_len = bnx_RXP_b06FwBssLen; 2443 fw.bss_index = 0; 2444 fw.bss = bnx_RXP_b06FwBss; 2445 2446 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2447 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2448 fw.rodata_index = 0; 2449 fw.rodata = bnx_RXP_b06FwRodata; 2450 2451 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2452 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2453 2454 /* Initialize the TX Processor. */ 2455 cpu_reg.mode = BNX_TXP_CPU_MODE; 2456 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2457 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2458 cpu_reg.state = BNX_TXP_CPU_STATE; 2459 cpu_reg.state_value_clear = 0xffffff; 2460 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2461 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2462 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2463 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2464 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2465 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2466 cpu_reg.mips_view_base = 0x8000000; 2467 2468 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2469 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2470 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2471 fw.start_addr = bnx_TXP_b06FwStartAddr; 2472 2473 fw.text_addr = bnx_TXP_b06FwTextAddr; 2474 fw.text_len = bnx_TXP_b06FwTextLen; 2475 fw.text_index = 0; 2476 fw.text = bnx_TXP_b06FwText; 2477 2478 fw.data_addr = bnx_TXP_b06FwDataAddr; 2479 fw.data_len = bnx_TXP_b06FwDataLen; 2480 fw.data_index = 0; 2481 fw.data = bnx_TXP_b06FwData; 2482 2483 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2484 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2485 fw.sbss_index = 0; 2486 fw.sbss = bnx_TXP_b06FwSbss; 2487 2488 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2489 fw.bss_len = bnx_TXP_b06FwBssLen; 2490 fw.bss_index = 0; 2491 fw.bss = bnx_TXP_b06FwBss; 2492 2493 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 2494 fw.rodata_len = bnx_TXP_b06FwRodataLen; 2495 fw.rodata_index = 0; 2496 fw.rodata = bnx_TXP_b06FwRodata; 2497 2498 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2499 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2500 2501 /* Initialize the TX Patch-up Processor. */ 2502 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2503 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2504 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2505 cpu_reg.state = BNX_TPAT_CPU_STATE; 2506 cpu_reg.state_value_clear = 0xffffff; 2507 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2508 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2509 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2510 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2511 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2512 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2513 cpu_reg.mips_view_base = 0x8000000; 2514 2515 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 2516 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 2517 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 2518 fw.start_addr = bnx_TPAT_b06FwStartAddr; 2519 2520 fw.text_addr = bnx_TPAT_b06FwTextAddr; 2521 fw.text_len = bnx_TPAT_b06FwTextLen; 2522 fw.text_index = 0; 2523 fw.text = bnx_TPAT_b06FwText; 2524 2525 fw.data_addr = bnx_TPAT_b06FwDataAddr; 2526 fw.data_len = bnx_TPAT_b06FwDataLen; 2527 fw.data_index = 0; 2528 fw.data = bnx_TPAT_b06FwData; 2529 2530 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 2531 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 2532 fw.sbss_index = 0; 2533 fw.sbss = bnx_TPAT_b06FwSbss; 2534 2535 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 2536 fw.bss_len = bnx_TPAT_b06FwBssLen; 2537 fw.bss_index = 0; 2538 fw.bss = bnx_TPAT_b06FwBss; 2539 2540 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 2541 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 2542 fw.rodata_index = 0; 2543 fw.rodata = bnx_TPAT_b06FwRodata; 2544 2545 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2546 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2547 2548 /* Initialize the Completion Processor. */ 2549 cpu_reg.mode = BNX_COM_CPU_MODE; 2550 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2551 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2552 cpu_reg.state = BNX_COM_CPU_STATE; 2553 cpu_reg.state_value_clear = 0xffffff; 2554 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2555 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2556 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2557 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2558 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2559 cpu_reg.spad_base = BNX_COM_SCRATCH; 2560 cpu_reg.mips_view_base = 0x8000000; 2561 2562 fw.ver_major = bnx_COM_b06FwReleaseMajor; 2563 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 2564 fw.ver_fix = bnx_COM_b06FwReleaseFix; 2565 fw.start_addr = bnx_COM_b06FwStartAddr; 2566 2567 fw.text_addr = bnx_COM_b06FwTextAddr; 2568 fw.text_len = bnx_COM_b06FwTextLen; 2569 fw.text_index = 0; 2570 fw.text = bnx_COM_b06FwText; 2571 2572 fw.data_addr = bnx_COM_b06FwDataAddr; 2573 fw.data_len = bnx_COM_b06FwDataLen; 2574 fw.data_index = 0; 2575 fw.data = bnx_COM_b06FwData; 2576 2577 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 2578 fw.sbss_len = bnx_COM_b06FwSbssLen; 2579 fw.sbss_index = 0; 2580 fw.sbss = bnx_COM_b06FwSbss; 2581 2582 fw.bss_addr = bnx_COM_b06FwBssAddr; 2583 fw.bss_len = bnx_COM_b06FwBssLen; 2584 fw.bss_index = 0; 2585 fw.bss = bnx_COM_b06FwBss; 2586 2587 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 2588 fw.rodata_len = bnx_COM_b06FwRodataLen; 2589 fw.rodata_index = 0; 2590 fw.rodata = bnx_COM_b06FwRodata; 2591 2592 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2593 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2594 } 2595 2596 /****************************************************************************/ 2597 /* Initialize context memory. */ 2598 /* */ 2599 /* Clears the memory associated with each Context ID (CID). */ 2600 /* */ 2601 /* Returns: */ 2602 /* Nothing. */ 2603 /****************************************************************************/ 2604 void 2605 bnx_init_context(struct bnx_softc *sc) 2606 { 2607 u_int32_t vcid; 2608 2609 vcid = 96; 2610 while (vcid) { 2611 u_int32_t vcid_addr, pcid_addr, offset; 2612 2613 vcid--; 2614 2615 vcid_addr = GET_CID_ADDR(vcid); 2616 pcid_addr = vcid_addr; 2617 2618 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); 2619 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2620 2621 /* Zero out the context. */ 2622 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2623 CTX_WR(sc, 0x00, offset, 0); 2624 2625 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 2626 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2627 } 2628 } 2629 2630 /****************************************************************************/ 2631 /* Fetch the permanent MAC address of the controller. */ 2632 /* */ 2633 /* Returns: */ 2634 /* Nothing. */ 2635 /****************************************************************************/ 2636 void 2637 bnx_get_mac_addr(struct bnx_softc *sc) 2638 { 2639 u_int32_t mac_lo = 0, mac_hi = 0; 2640 2641 /* 2642 * The NetXtreme II bootcode populates various NIC 2643 * power-on and runtime configuration items in a 2644 * shared memory area. The factory configured MAC 2645 * address is available from both NVRAM and the 2646 * shared memory area so we'll read the value from 2647 * shared memory for speed. 2648 */ 2649 2650 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 2651 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 2652 2653 if ((mac_lo == 0) && (mac_hi == 0)) { 2654 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 2655 __FILE__, __LINE__); 2656 } else { 2657 sc->eaddr[0] = (u_char)(mac_hi >> 8); 2658 sc->eaddr[1] = (u_char)(mac_hi >> 0); 2659 sc->eaddr[2] = (u_char)(mac_lo >> 24); 2660 sc->eaddr[3] = (u_char)(mac_lo >> 16); 2661 sc->eaddr[4] = (u_char)(mac_lo >> 8); 2662 sc->eaddr[5] = (u_char)(mac_lo >> 0); 2663 } 2664 2665 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 2666 "%s\n", ether_sprintf(sc->eaddr)); 2667 } 2668 2669 /****************************************************************************/ 2670 /* Program the MAC address. */ 2671 /* */ 2672 /* Returns: */ 2673 /* Nothing. */ 2674 /****************************************************************************/ 2675 void 2676 bnx_set_mac_addr(struct bnx_softc *sc) 2677 { 2678 u_int32_t val; 2679 const u_int8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 2680 2681 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 2682 "%s\n", ether_sprintf(sc->eaddr)); 2683 2684 val = (mac_addr[0] << 8) | mac_addr[1]; 2685 2686 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 2687 2688 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2689 (mac_addr[4] << 8) | mac_addr[5]; 2690 2691 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 2692 } 2693 2694 /****************************************************************************/ 2695 /* Stop the controller. */ 2696 /* */ 2697 /* Returns: */ 2698 /* Nothing. */ 2699 /****************************************************************************/ 2700 void 2701 bnx_stop(struct ifnet *ifp, int disable) 2702 { 2703 struct bnx_softc *sc = ifp->if_softc; 2704 2705 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2706 2707 if ((ifp->if_flags & IFF_RUNNING) == 0) 2708 return; 2709 2710 callout_stop(&sc->bnx_timeout); 2711 2712 mii_down(&sc->bnx_mii); 2713 2714 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2715 2716 /* Disable the transmit/receive blocks. */ 2717 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 2718 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2719 DELAY(20); 2720 2721 bnx_disable_intr(sc); 2722 2723 /* Tell firmware that the driver is going away. */ 2724 if (disable) 2725 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 2726 else 2727 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 2728 2729 /* Free the RX lists. */ 2730 bnx_free_rx_chain(sc); 2731 2732 /* Free TX buffers. */ 2733 bnx_free_tx_chain(sc); 2734 2735 ifp->if_timer = 0; 2736 2737 sc->bnx_link = 0; 2738 2739 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2740 2741 } 2742 2743 int 2744 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 2745 { 2746 u_int32_t val; 2747 int i, rc = 0; 2748 2749 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2750 2751 /* Wait for pending PCI transactions to complete. */ 2752 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 2753 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 2754 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 2755 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 2756 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 2757 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2758 DELAY(5); 2759 2760 /* Assume bootcode is running. */ 2761 sc->bnx_fw_timed_out = 0; 2762 2763 /* Give the firmware a chance to prepare for the reset. */ 2764 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 2765 if (rc) 2766 goto bnx_reset_exit; 2767 2768 /* Set a firmware reminder that this is a soft reset. */ 2769 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 2770 BNX_DRV_RESET_SIGNATURE_MAGIC); 2771 2772 /* Dummy read to force the chip to complete all current transactions. */ 2773 val = REG_RD(sc, BNX_MISC_ID); 2774 2775 /* Chip reset. */ 2776 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2777 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 2778 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 2779 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 2780 2781 /* Allow up to 30us for reset to complete. */ 2782 for (i = 0; i < 10; i++) { 2783 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 2784 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2785 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 2786 break; 2787 2788 DELAY(10); 2789 } 2790 2791 /* Check that reset completed successfully. */ 2792 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2793 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 2794 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__); 2795 rc = EBUSY; 2796 goto bnx_reset_exit; 2797 } 2798 2799 /* Make sure byte swapping is properly configured. */ 2800 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 2801 if (val != 0x01020304) { 2802 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 2803 __FILE__, __LINE__); 2804 rc = ENODEV; 2805 goto bnx_reset_exit; 2806 } 2807 2808 /* Just completed a reset, assume that firmware is running again. */ 2809 sc->bnx_fw_timed_out = 0; 2810 2811 /* Wait for the firmware to finish its initialization. */ 2812 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 2813 if (rc) 2814 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 2815 "initialization!\n", __FILE__, __LINE__); 2816 2817 bnx_reset_exit: 2818 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2819 2820 return (rc); 2821 } 2822 2823 int 2824 bnx_chipinit(struct bnx_softc *sc) 2825 { 2826 struct pci_attach_args *pa = &(sc->bnx_pa); 2827 u_int32_t val; 2828 int rc = 0; 2829 2830 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2831 2832 /* Make sure the interrupt is not active. */ 2833 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 2834 2835 /* Initialize DMA byte/word swapping, configure the number of DMA */ 2836 /* channels and PCI clock compensation delay. */ 2837 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 2838 BNX_DMA_CONFIG_DATA_WORD_SWAP | 2839 #if BYTE_ORDER == BIG_ENDIAN 2840 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 2841 #endif 2842 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 2843 DMA_READ_CHANS << 12 | 2844 DMA_WRITE_CHANS << 16; 2845 2846 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 2847 2848 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 2849 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 2850 2851 /* 2852 * This setting resolves a problem observed on certain Intel PCI 2853 * chipsets that cannot handle multiple outstanding DMA operations. 2854 * See errata E9_5706A1_65. 2855 */ 2856 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 2857 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 2858 !(sc->bnx_flags & BNX_PCIX_FLAG)) 2859 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 2860 2861 REG_WR(sc, BNX_DMA_CONFIG, val); 2862 2863 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 2864 if (sc->bnx_flags & BNX_PCIX_FLAG) { 2865 u_int16_t nval; 2866 2867 nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 2868 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 2869 nval & ~0x2); 2870 } 2871 2872 /* Enable the RX_V2P and Context state machines before access. */ 2873 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 2874 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 2875 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 2876 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 2877 2878 /* Initialize context mapping and zero out the quick contexts. */ 2879 bnx_init_context(sc); 2880 2881 /* Initialize the on-boards CPUs */ 2882 bnx_init_cpus(sc); 2883 2884 /* Prepare NVRAM for access. */ 2885 if (bnx_init_nvram(sc)) { 2886 rc = ENODEV; 2887 goto bnx_chipinit_exit; 2888 } 2889 2890 /* Set the kernel bypass block size */ 2891 val = REG_RD(sc, BNX_MQ_CONFIG); 2892 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 2893 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 2894 REG_WR(sc, BNX_MQ_CONFIG, val); 2895 2896 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 2897 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 2898 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 2899 2900 val = (BCM_PAGE_BITS - 8) << 24; 2901 REG_WR(sc, BNX_RV2P_CONFIG, val); 2902 2903 /* Configure page size. */ 2904 val = REG_RD(sc, BNX_TBDR_CONFIG); 2905 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 2906 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 2907 REG_WR(sc, BNX_TBDR_CONFIG, val); 2908 2909 bnx_chipinit_exit: 2910 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2911 2912 return(rc); 2913 } 2914 2915 /****************************************************************************/ 2916 /* Initialize the controller in preparation to send/receive traffic. */ 2917 /* */ 2918 /* Returns: */ 2919 /* 0 for success, positive value for failure. */ 2920 /****************************************************************************/ 2921 int 2922 bnx_blockinit(struct bnx_softc *sc) 2923 { 2924 u_int32_t reg, val; 2925 int rc = 0; 2926 2927 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2928 2929 /* Load the hardware default MAC address. */ 2930 bnx_set_mac_addr(sc); 2931 2932 /* Set the Ethernet backoff seed value */ 2933 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 2934 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 2935 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 2936 2937 sc->last_status_idx = 0; 2938 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 2939 2940 /* Set up link change interrupt generation. */ 2941 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 2942 2943 /* Program the physical address of the status block. */ 2944 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 2945 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 2946 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 2947 2948 /* Program the physical address of the statistics block. */ 2949 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 2950 (u_int32_t)(sc->stats_block_paddr)); 2951 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 2952 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 2953 2954 /* Program various host coalescing parameters. */ 2955 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 2956 << 16) | sc->bnx_tx_quick_cons_trip); 2957 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 2958 << 16) | sc->bnx_rx_quick_cons_trip); 2959 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 2960 sc->bnx_comp_prod_trip); 2961 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 2962 sc->bnx_tx_ticks); 2963 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 2964 sc->bnx_rx_ticks); 2965 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 2966 sc->bnx_com_ticks); 2967 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 2968 sc->bnx_cmd_ticks); 2969 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 2970 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 2971 REG_WR(sc, BNX_HC_CONFIG, 2972 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 2973 BNX_HC_CONFIG_COLLECT_STATS)); 2974 2975 /* Clear the internal statistics counters. */ 2976 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 2977 2978 /* Verify that bootcode is running. */ 2979 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 2980 2981 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 2982 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 2983 __FILE__, __LINE__); reg = 0); 2984 2985 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 2986 BNX_DEV_INFO_SIGNATURE_MAGIC) { 2987 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 2988 "Expected: 08%08X\n", __FILE__, __LINE__, 2989 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 2990 BNX_DEV_INFO_SIGNATURE_MAGIC); 2991 rc = ENODEV; 2992 goto bnx_blockinit_exit; 2993 } 2994 2995 /* Check if any management firmware is running. */ 2996 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 2997 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 2998 BNX_PORT_FEATURE_IMD_ENABLED)) { 2999 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3000 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3001 } 3002 3003 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3004 BNX_DEV_INFO_BC_REV); 3005 3006 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3007 3008 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3009 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3010 3011 /* Enable link state change interrupt generation. */ 3012 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3013 3014 /* Enable all remaining blocks in the MAC. */ 3015 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3016 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3017 DELAY(20); 3018 3019 bnx_blockinit_exit: 3020 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3021 3022 return (rc); 3023 } 3024 3025 /****************************************************************************/ 3026 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3027 /* */ 3028 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3029 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3030 /* necessary. */ 3031 /* */ 3032 /* Returns: */ 3033 /* 0 for success, positive value for failure. */ 3034 /****************************************************************************/ 3035 int 3036 bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod, 3037 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3038 { 3039 bus_dmamap_t map; 3040 struct mbuf *m_new = NULL; 3041 struct rx_bd *rxbd; 3042 int i, rc = 0; 3043 u_int32_t addr; 3044 #ifdef BNX_DEBUG 3045 u_int16_t debug_chain_prod = *chain_prod; 3046 #endif 3047 u_int16_t first_chain_prod; 3048 u_int16_t min_free_bd; 3049 3050 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3051 __func__); 3052 3053 /* Make sure the inputs are valid. */ 3054 DBRUNIF((*chain_prod > MAX_RX_BD), 3055 aprint_error_dev(sc->bnx_dev, 3056 "RX producer out of range: 0x%04X > 0x%04X\n", 3057 *chain_prod, (u_int16_t)MAX_RX_BD)); 3058 3059 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3060 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3061 *prod_bseq); 3062 3063 /* try to get in as many mbufs as possible */ 3064 if (sc->mbuf_alloc_size == MCLBYTES) 3065 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3066 else 3067 min_free_bd = (BNX_MAX_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3068 while (sc->free_rx_bd >= min_free_bd) { 3069 if (m == NULL) { 3070 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3071 BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n"); 3072 3073 sc->mbuf_alloc_failed++; 3074 rc = ENOBUFS; 3075 goto bnx_get_buf_exit); 3076 3077 /* This is a new mbuf allocation. */ 3078 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3079 if (m_new == NULL) { 3080 DBPRINT(sc, BNX_WARN, 3081 "%s(%d): RX mbuf header allocation failed!\n", 3082 __FILE__, __LINE__); 3083 3084 DBRUNIF(1, sc->mbuf_alloc_failed++); 3085 3086 rc = ENOBUFS; 3087 goto bnx_get_buf_exit; 3088 } 3089 3090 DBRUNIF(1, sc->rx_mbuf_alloc++); 3091 if (sc->mbuf_alloc_size == MCLBYTES) 3092 MCLGET(m_new, M_DONTWAIT); 3093 else 3094 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3095 M_DONTWAIT); 3096 if (!(m_new->m_flags & M_EXT)) { 3097 DBPRINT(sc, BNX_WARN, 3098 "%s(%d): RX mbuf chain allocation failed!\n", 3099 __FILE__, __LINE__); 3100 3101 m_freem(m_new); 3102 3103 DBRUNIF(1, sc->rx_mbuf_alloc--); 3104 DBRUNIF(1, sc->mbuf_alloc_failed++); 3105 3106 rc = ENOBUFS; 3107 goto bnx_get_buf_exit; 3108 } 3109 3110 } else { 3111 m_new = m; 3112 m = NULL; 3113 m_new->m_data = m_new->m_ext.ext_buf; 3114 } 3115 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3116 3117 /* Map the mbuf cluster into device memory. */ 3118 map = sc->rx_mbuf_map[*chain_prod]; 3119 first_chain_prod = *chain_prod; 3120 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3121 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3122 __FILE__, __LINE__); 3123 3124 m_freem(m_new); 3125 3126 DBRUNIF(1, sc->rx_mbuf_alloc--); 3127 3128 rc = ENOBUFS; 3129 goto bnx_get_buf_exit; 3130 } 3131 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3132 BUS_DMASYNC_PREREAD); 3133 3134 /* Watch for overflow. */ 3135 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3136 aprint_error_dev(sc->bnx_dev, 3137 "Too many free rx_bd (0x%04X > 0x%04X)!\n", 3138 sc->free_rx_bd, (u_int16_t)USABLE_RX_BD)); 3139 3140 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3141 sc->rx_low_watermark = sc->free_rx_bd); 3142 3143 /* 3144 * Setup the rx_bd for the first segment 3145 */ 3146 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3147 3148 addr = (u_int32_t)(map->dm_segs[0].ds_addr); 3149 rxbd->rx_bd_haddr_lo = htole32(addr); 3150 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3151 rxbd->rx_bd_haddr_hi = htole32(addr); 3152 rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); 3153 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3154 *prod_bseq += map->dm_segs[0].ds_len; 3155 bus_dmamap_sync(sc->bnx_dmatag, 3156 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3157 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3158 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3159 3160 for (i = 1; i < map->dm_nsegs; i++) { 3161 *prod = NEXT_RX_BD(*prod); 3162 *chain_prod = RX_CHAIN_IDX(*prod); 3163 3164 rxbd = 3165 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3166 3167 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 3168 rxbd->rx_bd_haddr_lo = htole32(addr); 3169 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3170 rxbd->rx_bd_haddr_hi = htole32(addr); 3171 rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); 3172 rxbd->rx_bd_flags = 0; 3173 *prod_bseq += map->dm_segs[i].ds_len; 3174 bus_dmamap_sync(sc->bnx_dmatag, 3175 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3176 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3177 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3178 } 3179 3180 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3181 bus_dmamap_sync(sc->bnx_dmatag, 3182 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3183 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3184 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3185 3186 /* 3187 * Save the mbuf, ajust the map pointer (swap map for first and 3188 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3189 * and update counter. 3190 */ 3191 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3192 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3193 sc->rx_mbuf_map[*chain_prod] = map; 3194 sc->free_rx_bd -= map->dm_nsegs; 3195 3196 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3197 map->dm_nsegs)); 3198 *prod = NEXT_RX_BD(*prod); 3199 *chain_prod = RX_CHAIN_IDX(*prod); 3200 } 3201 3202 bnx_get_buf_exit: 3203 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3204 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3205 *chain_prod, *prod_bseq); 3206 3207 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3208 __func__); 3209 3210 return(rc); 3211 } 3212 3213 /****************************************************************************/ 3214 /* Allocate memory and initialize the TX data structures. */ 3215 /* */ 3216 /* Returns: */ 3217 /* 0 for success, positive value for failure. */ 3218 /****************************************************************************/ 3219 int 3220 bnx_init_tx_chain(struct bnx_softc *sc) 3221 { 3222 struct tx_bd *txbd; 3223 u_int32_t val, addr; 3224 int i, rc = 0; 3225 3226 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3227 3228 /* Set the initial TX producer/consumer indices. */ 3229 sc->tx_prod = 0; 3230 sc->tx_cons = 0; 3231 sc->tx_prod_bseq = 0; 3232 sc->used_tx_bd = 0; 3233 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3234 3235 /* 3236 * The NetXtreme II supports a linked-list structure called 3237 * a Buffer Descriptor Chain (or BD chain). A BD chain 3238 * consists of a series of 1 or more chain pages, each of which 3239 * consists of a fixed number of BD entries. 3240 * The last BD entry on each page is a pointer to the next page 3241 * in the chain, and the last pointer in the BD chain 3242 * points back to the beginning of the chain. 3243 */ 3244 3245 /* Set the TX next pointer chain entries. */ 3246 for (i = 0; i < TX_PAGES; i++) { 3247 int j; 3248 3249 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3250 3251 /* Check if we've reached the last page. */ 3252 if (i == (TX_PAGES - 1)) 3253 j = 0; 3254 else 3255 j = i + 1; 3256 3257 addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); 3258 txbd->tx_bd_haddr_lo = htole32(addr); 3259 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3260 txbd->tx_bd_haddr_hi = htole32(addr); 3261 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3262 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3263 } 3264 3265 /* 3266 * Initialize the context ID for an L2 TX chain. 3267 */ 3268 val = BNX_L2CTX_TYPE_TYPE_L2; 3269 val |= BNX_L2CTX_TYPE_SIZE_L2; 3270 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3271 3272 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3273 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3274 3275 /* Point the hardware to the first page in the chain. */ 3276 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3277 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3278 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3279 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3280 3281 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3282 3283 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3284 3285 return(rc); 3286 } 3287 3288 /****************************************************************************/ 3289 /* Free memory and clear the TX data structures. */ 3290 /* */ 3291 /* Returns: */ 3292 /* Nothing. */ 3293 /****************************************************************************/ 3294 void 3295 bnx_free_tx_chain(struct bnx_softc *sc) 3296 { 3297 int i; 3298 3299 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3300 3301 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3302 for (i = 0; i < TOTAL_TX_BD; i++) { 3303 if (sc->tx_mbuf_ptr[i] != NULL) { 3304 if (sc->tx_mbuf_map != NULL) 3305 bus_dmamap_sync(sc->bnx_dmatag, 3306 sc->tx_mbuf_map[i], 0, 3307 sc->tx_mbuf_map[i]->dm_mapsize, 3308 BUS_DMASYNC_POSTWRITE); 3309 m_freem(sc->tx_mbuf_ptr[i]); 3310 sc->tx_mbuf_ptr[i] = NULL; 3311 DBRUNIF(1, sc->tx_mbuf_alloc--); 3312 } 3313 } 3314 3315 /* Clear each TX chain page. */ 3316 for (i = 0; i < TX_PAGES; i++) { 3317 bzero((char *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 3318 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3319 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3320 } 3321 3322 /* Check if we lost any mbufs in the process. */ 3323 DBRUNIF((sc->tx_mbuf_alloc), 3324 aprint_error_dev(sc->bnx_dev, 3325 "Memory leak! Lost %d mbufs from tx chain!\n", 3326 sc->tx_mbuf_alloc)); 3327 3328 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3329 } 3330 3331 /****************************************************************************/ 3332 /* Allocate memory and initialize the RX data structures. */ 3333 /* */ 3334 /* Returns: */ 3335 /* 0 for success, positive value for failure. */ 3336 /****************************************************************************/ 3337 int 3338 bnx_init_rx_chain(struct bnx_softc *sc) 3339 { 3340 struct rx_bd *rxbd; 3341 int i, rc = 0; 3342 u_int16_t prod, chain_prod; 3343 u_int32_t prod_bseq, val, addr; 3344 3345 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3346 3347 /* Initialize the RX producer and consumer indices. */ 3348 sc->rx_prod = 0; 3349 sc->rx_cons = 0; 3350 sc->rx_prod_bseq = 0; 3351 sc->free_rx_bd = BNX_RX_SLACK_SPACE; 3352 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3353 3354 /* Initialize the RX next pointer chain entries. */ 3355 for (i = 0; i < RX_PAGES; i++) { 3356 int j; 3357 3358 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3359 3360 /* Check if we've reached the last page. */ 3361 if (i == (RX_PAGES - 1)) 3362 j = 0; 3363 else 3364 j = i + 1; 3365 3366 /* Setup the chain page pointers. */ 3367 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 3368 rxbd->rx_bd_haddr_hi = htole32(addr); 3369 addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); 3370 rxbd->rx_bd_haddr_lo = htole32(addr); 3371 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 3372 0, BNX_RX_CHAIN_PAGE_SZ, 3373 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3374 } 3375 3376 /* Initialize the context ID for an L2 RX chain. */ 3377 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3378 val |= BNX_L2CTX_CTX_TYPE_SIZE_L2; 3379 val |= 0x02 << 8; 3380 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 3381 3382 /* Point the hardware to the first page in the chain. */ 3383 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 3384 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 3385 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 3386 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 3387 3388 /* Allocate mbuf clusters for the rx_bd chain. */ 3389 prod = prod_bseq = 0; 3390 chain_prod = RX_CHAIN_IDX(prod); 3391 if (bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3392 BNX_PRINTF(sc, 3393 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 3394 } 3395 3396 /* Save the RX chain producer index. */ 3397 sc->rx_prod = prod; 3398 sc->rx_prod_bseq = prod_bseq; 3399 3400 for (i = 0; i < RX_PAGES; i++) 3401 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 3402 sc->rx_bd_chain_map[i]->dm_mapsize, 3403 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3404 3405 /* Tell the chip about the waiting rx_bd's. */ 3406 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3407 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3408 3409 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3410 3411 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3412 3413 return(rc); 3414 } 3415 3416 /****************************************************************************/ 3417 /* Free memory and clear the RX data structures. */ 3418 /* */ 3419 /* Returns: */ 3420 /* Nothing. */ 3421 /****************************************************************************/ 3422 void 3423 bnx_free_rx_chain(struct bnx_softc *sc) 3424 { 3425 int i; 3426 3427 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3428 3429 /* Free any mbufs still in the RX mbuf chain. */ 3430 for (i = 0; i < TOTAL_RX_BD; i++) { 3431 if (sc->rx_mbuf_ptr[i] != NULL) { 3432 if (sc->rx_mbuf_map[i] != NULL) 3433 bus_dmamap_sync(sc->bnx_dmatag, 3434 sc->rx_mbuf_map[i], 0, 3435 sc->rx_mbuf_map[i]->dm_mapsize, 3436 BUS_DMASYNC_POSTREAD); 3437 m_freem(sc->rx_mbuf_ptr[i]); 3438 sc->rx_mbuf_ptr[i] = NULL; 3439 DBRUNIF(1, sc->rx_mbuf_alloc--); 3440 } 3441 } 3442 3443 /* Clear each RX chain page. */ 3444 for (i = 0; i < RX_PAGES; i++) 3445 bzero((char *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 3446 3447 /* Check if we lost any mbufs in the process. */ 3448 DBRUNIF((sc->rx_mbuf_alloc), 3449 aprint_error_dev(sc->bnx_dev, 3450 "Memory leak! Lost %d mbufs from rx chain!\n", 3451 sc->rx_mbuf_alloc)); 3452 3453 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3454 } 3455 3456 /****************************************************************************/ 3457 /* Set media options. */ 3458 /* */ 3459 /* Returns: */ 3460 /* 0 for success, positive value for failure. */ 3461 /****************************************************************************/ 3462 int 3463 bnx_ifmedia_upd(struct ifnet *ifp) 3464 { 3465 struct bnx_softc *sc; 3466 struct mii_data *mii; 3467 struct ifmedia *ifm; 3468 int rc; 3469 3470 sc = ifp->if_softc; 3471 ifm = &sc->bnx_ifmedia; 3472 3473 /* DRC - ToDo: Add SerDes support. */ 3474 3475 mii = &sc->bnx_mii; 3476 sc->bnx_link = 0; 3477 if ((rc = mii_mediachg(mii)) == ENXIO) 3478 return 0; 3479 return rc; 3480 } 3481 3482 /****************************************************************************/ 3483 /* Reports current media status. */ 3484 /* */ 3485 /* Returns: */ 3486 /* Nothing. */ 3487 /****************************************************************************/ 3488 void 3489 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3490 { 3491 struct bnx_softc *sc; 3492 struct mii_data *mii; 3493 int s; 3494 3495 sc = ifp->if_softc; 3496 3497 s = splnet(); 3498 3499 mii = &sc->bnx_mii; 3500 3501 /* DRC - ToDo: Add SerDes support. */ 3502 3503 mii_pollstat(mii); 3504 ifmr->ifm_active = mii->mii_media_active; 3505 ifmr->ifm_status = mii->mii_media_status; 3506 3507 splx(s); 3508 } 3509 3510 /****************************************************************************/ 3511 /* Handles PHY generated interrupt events. */ 3512 /* */ 3513 /* Returns: */ 3514 /* Nothing. */ 3515 /****************************************************************************/ 3516 void 3517 bnx_phy_intr(struct bnx_softc *sc) 3518 { 3519 u_int32_t new_link_state, old_link_state; 3520 3521 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3522 BUS_DMASYNC_POSTREAD); 3523 new_link_state = sc->status_block->status_attn_bits & 3524 STATUS_ATTN_BITS_LINK_STATE; 3525 old_link_state = sc->status_block->status_attn_bits_ack & 3526 STATUS_ATTN_BITS_LINK_STATE; 3527 3528 /* Handle any changes if the link state has changed. */ 3529 if (new_link_state != old_link_state) { 3530 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 3531 3532 sc->bnx_link = 0; 3533 callout_stop(&sc->bnx_timeout); 3534 bnx_tick(sc); 3535 3536 /* Update the status_attn_bits_ack field in the status block. */ 3537 if (new_link_state) { 3538 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 3539 STATUS_ATTN_BITS_LINK_STATE); 3540 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 3541 } else { 3542 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 3543 STATUS_ATTN_BITS_LINK_STATE); 3544 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 3545 } 3546 } 3547 3548 /* Acknowledge the link change interrupt. */ 3549 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 3550 } 3551 3552 /****************************************************************************/ 3553 /* Handles received frame interrupt events. */ 3554 /* */ 3555 /* Returns: */ 3556 /* Nothing. */ 3557 /****************************************************************************/ 3558 void 3559 bnx_rx_intr(struct bnx_softc *sc) 3560 { 3561 struct status_block *sblk = sc->status_block; 3562 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3563 u_int16_t hw_cons, sw_cons, sw_chain_cons; 3564 u_int16_t sw_prod, sw_chain_prod; 3565 u_int32_t sw_prod_bseq; 3566 struct l2_fhdr *l2fhdr; 3567 int i; 3568 3569 DBRUNIF(1, sc->rx_interrupts++); 3570 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3571 BUS_DMASYNC_POSTREAD); 3572 3573 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3574 for (i = 0; i < RX_PAGES; i++) 3575 bus_dmamap_sync(sc->bnx_dmatag, 3576 sc->rx_bd_chain_map[i], 0, 3577 sc->rx_bd_chain_map[i]->dm_mapsize, 3578 BUS_DMASYNC_POSTWRITE); 3579 3580 /* Get the hardware's view of the RX consumer index. */ 3581 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3582 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3583 hw_cons++; 3584 3585 /* Get working copies of the driver's view of the RX indices. */ 3586 sw_cons = sc->rx_cons; 3587 sw_prod = sc->rx_prod; 3588 sw_prod_bseq = sc->rx_prod_bseq; 3589 3590 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3591 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3592 __func__, sw_prod, sw_cons, sw_prod_bseq); 3593 3594 /* Prevent speculative reads from getting ahead of the status block. */ 3595 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3596 BUS_SPACE_BARRIER_READ); 3597 3598 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3599 sc->rx_low_watermark = sc->free_rx_bd); 3600 3601 /* 3602 * Scan through the receive chain as long 3603 * as there is work to do. 3604 */ 3605 while (sw_cons != hw_cons) { 3606 struct mbuf *m; 3607 struct rx_bd *rxbd; 3608 unsigned int len; 3609 u_int32_t status; 3610 3611 /* Convert the producer/consumer indices to an actual 3612 * rx_bd index. 3613 */ 3614 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3615 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3616 3617 /* Get the used rx_bd. */ 3618 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3619 sc->free_rx_bd++; 3620 3621 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 3622 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 3623 3624 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3625 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3626 #ifdef DIAGNOSTIC 3627 /* Validate that this is the last rx_bd. */ 3628 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 3629 printf("%s: Unexpected mbuf found in " 3630 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 3631 sw_chain_cons); 3632 } 3633 #endif 3634 3635 /* DRC - ToDo: If the received packet is small, say less 3636 * than 128 bytes, allocate a new mbuf here, 3637 * copy the data to that mbuf, and recycle 3638 * the mapped jumbo frame. 3639 */ 3640 3641 /* Unmap the mbuf from DMA space. */ 3642 #ifdef DIAGNOSTIC 3643 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 3644 printf("invalid map sw_cons 0x%x " 3645 "sw_prod 0x%x " 3646 "sw_chain_cons 0x%x " 3647 "sw_chain_prod 0x%x " 3648 "hw_cons 0x%x " 3649 "TOTAL_RX_BD_PER_PAGE 0x%x " 3650 "TOTAL_RX_BD 0x%x\n", 3651 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 3652 hw_cons, 3653 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 3654 } 3655 #endif 3656 bus_dmamap_sync(sc->bnx_dmatag, 3657 sc->rx_mbuf_map[sw_chain_cons], 0, 3658 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 3659 BUS_DMASYNC_POSTREAD); 3660 bus_dmamap_unload(sc->bnx_dmatag, 3661 sc->rx_mbuf_map[sw_chain_cons]); 3662 3663 /* Remove the mbuf from the driver's chain. */ 3664 m = sc->rx_mbuf_ptr[sw_chain_cons]; 3665 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 3666 3667 /* 3668 * Frames received on the NetXteme II are prepended 3669 * with the l2_fhdr structure which provides status 3670 * information about the received frame (including 3671 * VLAN tags and checksum info) and are also 3672 * automatically adjusted to align the IP header 3673 * (i.e. two null bytes are inserted before the 3674 * Ethernet header). 3675 */ 3676 l2fhdr = mtod(m, struct l2_fhdr *); 3677 3678 len = l2fhdr->l2_fhdr_pkt_len; 3679 status = l2fhdr->l2_fhdr_status; 3680 3681 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 3682 aprint_error("Simulating l2_fhdr status error.\n"); 3683 status = status | L2_FHDR_ERRORS_PHY_DECODE); 3684 3685 /* Watch for unusual sized frames. */ 3686 DBRUNIF(((len < BNX_MIN_MTU) || 3687 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 3688 aprint_error_dev(sc->bnx_dev, 3689 "Unusual frame size found. " 3690 "Min(%d), Actual(%d), Max(%d)\n", 3691 (int)BNX_MIN_MTU, len, 3692 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 3693 3694 bnx_dump_mbuf(sc, m); 3695 bnx_breakpoint(sc)); 3696 3697 len -= ETHER_CRC_LEN; 3698 3699 /* Check the received frame for errors. */ 3700 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 3701 L2_FHDR_ERRORS_PHY_DECODE | 3702 L2_FHDR_ERRORS_ALIGNMENT | 3703 L2_FHDR_ERRORS_TOO_SHORT | 3704 L2_FHDR_ERRORS_GIANT_FRAME)) || 3705 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 3706 len > 3707 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 3708 ifp->if_ierrors++; 3709 DBRUNIF(1, sc->l2fhdr_status_errors++); 3710 3711 /* Reuse the mbuf for a new frame. */ 3712 if (bnx_get_buf(sc, m, &sw_prod, 3713 &sw_chain_prod, &sw_prod_bseq)) { 3714 DBRUNIF(1, bnx_breakpoint(sc)); 3715 panic("%s: Can't reuse RX mbuf!\n", 3716 device_xname(sc->bnx_dev)); 3717 } 3718 continue; 3719 } 3720 3721 /* 3722 * Get a new mbuf for the rx_bd. If no new 3723 * mbufs are available then reuse the current mbuf, 3724 * log an ierror on the interface, and generate 3725 * an error in the system log. 3726 */ 3727 if (bnx_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, 3728 &sw_prod_bseq)) { 3729 DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate " 3730 "new mbuf, incoming frame dropped!\n")); 3731 3732 ifp->if_ierrors++; 3733 3734 /* Try and reuse the exisitng mbuf. */ 3735 if (bnx_get_buf(sc, m, &sw_prod, 3736 &sw_chain_prod, &sw_prod_bseq)) { 3737 DBRUNIF(1, bnx_breakpoint(sc)); 3738 panic("%s: Double mbuf allocation " 3739 "failure!", 3740 device_xname(sc->bnx_dev)); 3741 } 3742 continue; 3743 } 3744 3745 /* Skip over the l2_fhdr when passing the data up 3746 * the stack. 3747 */ 3748 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 3749 3750 /* Adjust the pckt length to match the received data. */ 3751 m->m_pkthdr.len = m->m_len = len; 3752 3753 /* Send the packet to the appropriate interface. */ 3754 m->m_pkthdr.rcvif = ifp; 3755 3756 DBRUN(BNX_VERBOSE_RECV, 3757 struct ether_header *eh; 3758 eh = mtod(m, struct ether_header *); 3759 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 3760 __func__, ether_sprintf(eh->ether_dhost), 3761 ether_sprintf(eh->ether_shost), 3762 htons(eh->ether_type))); 3763 3764 /* Validate the checksum. */ 3765 3766 /* Check for an IP datagram. */ 3767 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 3768 /* Check if the IP checksum is valid. */ 3769 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 3770 == 0) 3771 m->m_pkthdr.csum_flags |= 3772 M_CSUM_IPv4; 3773 #ifdef BNX_DEBUG 3774 else 3775 DBPRINT(sc, BNX_WARN_SEND, 3776 "%s(): Invalid IP checksum " 3777 "= 0x%04X!\n", 3778 __func__, 3779 l2fhdr->l2_fhdr_ip_xsum 3780 ); 3781 #endif 3782 } 3783 3784 /* Check for a valid TCP/UDP frame. */ 3785 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3786 L2_FHDR_STATUS_UDP_DATAGRAM)) { 3787 /* Check for a good TCP/UDP checksum. */ 3788 if ((status & 3789 (L2_FHDR_ERRORS_TCP_XSUM | 3790 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 3791 m->m_pkthdr.csum_flags |= 3792 M_CSUM_TCPv4 | 3793 M_CSUM_UDPv4; 3794 } else { 3795 DBPRINT(sc, BNX_WARN_SEND, 3796 "%s(): Invalid TCP/UDP " 3797 "checksum = 0x%04X!\n", 3798 __func__, 3799 l2fhdr->l2_fhdr_tcp_udp_xsum); 3800 } 3801 } 3802 3803 /* 3804 * If we received a packet with a vlan tag, 3805 * attach that information to the packet. 3806 */ 3807 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 3808 #if 0 3809 struct ether_vlan_header vh; 3810 3811 DBPRINT(sc, BNX_VERBOSE_SEND, 3812 "%s(): VLAN tag = 0x%04X\n", 3813 __func__, 3814 l2fhdr->l2_fhdr_vlan_tag); 3815 3816 if (m->m_pkthdr.len < ETHER_HDR_LEN) { 3817 m_freem(m); 3818 continue; 3819 } 3820 m_copydata(m, 0, ETHER_HDR_LEN, (void *)&vh); 3821 vh.evl_proto = vh.evl_encap_proto; 3822 vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag; 3823 vh.evl_encap_proto = htons(ETHERTYPE_VLAN); 3824 m_adj(m, ETHER_HDR_LEN); 3825 if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL) 3826 continue; 3827 m->m_pkthdr.len += sizeof(vh); 3828 if (m->m_len < sizeof(vh) && 3829 (m = m_pullup(m, sizeof(vh))) == NULL) 3830 goto bnx_rx_int_next_rx; 3831 m_copyback(m, 0, sizeof(vh), &vh); 3832 #else 3833 VLAN_INPUT_TAG(ifp, m, 3834 l2fhdr->l2_fhdr_vlan_tag, 3835 continue); 3836 #endif 3837 } 3838 3839 #if NBPFILTER > 0 3840 /* 3841 * Handle BPF listeners. Let the BPF 3842 * user see the packet. 3843 */ 3844 if (ifp->if_bpf) 3845 bpf_mtap(ifp->if_bpf, m); 3846 #endif 3847 3848 /* Pass the mbuf off to the upper layers. */ 3849 ifp->if_ipackets++; 3850 DBPRINT(sc, BNX_VERBOSE_RECV, 3851 "%s(): Passing received frame up.\n", __func__); 3852 (*ifp->if_input)(ifp, m); 3853 DBRUNIF(1, sc->rx_mbuf_alloc--); 3854 3855 } 3856 3857 sw_cons = NEXT_RX_BD(sw_cons); 3858 3859 /* Refresh hw_cons to see if there's new work */ 3860 if (sw_cons == hw_cons) { 3861 hw_cons = sc->hw_rx_cons = 3862 sblk->status_rx_quick_consumer_index0; 3863 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 3864 USABLE_RX_BD_PER_PAGE) 3865 hw_cons++; 3866 } 3867 3868 /* Prevent speculative reads from getting ahead of 3869 * the status block. 3870 */ 3871 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3872 BUS_SPACE_BARRIER_READ); 3873 } 3874 3875 for (i = 0; i < RX_PAGES; i++) 3876 bus_dmamap_sync(sc->bnx_dmatag, 3877 sc->rx_bd_chain_map[i], 0, 3878 sc->rx_bd_chain_map[i]->dm_mapsize, 3879 BUS_DMASYNC_PREWRITE); 3880 3881 sc->rx_cons = sw_cons; 3882 sc->rx_prod = sw_prod; 3883 sc->rx_prod_bseq = sw_prod_bseq; 3884 3885 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3886 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3887 3888 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 3889 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 3890 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 3891 } 3892 3893 /****************************************************************************/ 3894 /* Handles transmit completion interrupt events. */ 3895 /* */ 3896 /* Returns: */ 3897 /* Nothing. */ 3898 /****************************************************************************/ 3899 void 3900 bnx_tx_intr(struct bnx_softc *sc) 3901 { 3902 struct status_block *sblk = sc->status_block; 3903 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3904 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 3905 3906 DBRUNIF(1, sc->tx_interrupts++); 3907 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3908 BUS_DMASYNC_POSTREAD); 3909 3910 /* Get the hardware's view of the TX consumer index. */ 3911 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 3912 3913 /* Skip to the next entry if this is a chain page pointer. */ 3914 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 3915 hw_tx_cons++; 3916 3917 sw_tx_cons = sc->tx_cons; 3918 3919 /* Prevent speculative reads from getting ahead of the status block. */ 3920 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3921 BUS_SPACE_BARRIER_READ); 3922 3923 /* Cycle through any completed TX chain page entries. */ 3924 while (sw_tx_cons != hw_tx_cons) { 3925 #ifdef BNX_DEBUG 3926 struct tx_bd *txbd = NULL; 3927 #endif 3928 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 3929 3930 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 3931 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 3932 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 3933 3934 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 3935 aprint_error_dev(sc->bnx_dev, 3936 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 3937 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 3938 3939 DBRUNIF(1, txbd = &sc->tx_bd_chain 3940 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 3941 3942 DBRUNIF((txbd == NULL), 3943 aprint_error_dev(sc->bnx_dev, 3944 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 3945 bnx_breakpoint(sc)); 3946 3947 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 3948 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 3949 3950 /* 3951 * Free the associated mbuf. Remember 3952 * that only the last tx_bd of a packet 3953 * has an mbuf pointer and DMA map. 3954 */ 3955 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 3956 /* Validate that this is the last tx_bd. */ 3957 DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & 3958 TX_BD_FLAGS_END)), 3959 aprint_error_dev(sc->bnx_dev, 3960 "tx_bd END flag not set but txmbuf == NULL!\n"); 3961 bnx_breakpoint(sc)); 3962 3963 DBRUN(BNX_INFO_SEND, 3964 aprint_debug("%s: Unloading map/freeing mbuf " 3965 "from tx_bd[0x%04X]\n", 3966 __func__, sw_tx_chain_cons)); 3967 3968 /* Unmap the mbuf. */ 3969 bus_dmamap_unload(sc->bnx_dmatag, 3970 sc->tx_mbuf_map[sw_tx_chain_cons]); 3971 3972 /* Free the mbuf. */ 3973 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 3974 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 3975 DBRUNIF(1, sc->tx_mbuf_alloc--); 3976 3977 ifp->if_opackets++; 3978 } 3979 3980 sc->used_tx_bd--; 3981 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 3982 3983 /* Refresh hw_cons to see if there's new work. */ 3984 hw_tx_cons = sc->hw_tx_cons = 3985 sblk->status_tx_quick_consumer_index0; 3986 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 3987 USABLE_TX_BD_PER_PAGE) 3988 hw_tx_cons++; 3989 3990 /* Prevent speculative reads from getting ahead of 3991 * the status block. 3992 */ 3993 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3994 BUS_SPACE_BARRIER_READ); 3995 } 3996 3997 /* Clear the TX timeout timer. */ 3998 ifp->if_timer = 0; 3999 4000 /* Clear the tx hardware queue full flag. */ 4001 if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) { 4002 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4003 aprint_debug_dev(sc->bnx_dev, 4004 "TX chain is open for business! Used tx_bd = %d\n", 4005 sc->used_tx_bd)); 4006 ifp->if_flags &= ~IFF_OACTIVE; 4007 } 4008 4009 sc->tx_cons = sw_tx_cons; 4010 } 4011 4012 /****************************************************************************/ 4013 /* Disables interrupt generation. */ 4014 /* */ 4015 /* Returns: */ 4016 /* Nothing. */ 4017 /****************************************************************************/ 4018 void 4019 bnx_disable_intr(struct bnx_softc *sc) 4020 { 4021 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4022 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4023 } 4024 4025 /****************************************************************************/ 4026 /* Enables interrupt generation. */ 4027 /* */ 4028 /* Returns: */ 4029 /* Nothing. */ 4030 /****************************************************************************/ 4031 void 4032 bnx_enable_intr(struct bnx_softc *sc) 4033 { 4034 u_int32_t val; 4035 4036 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4037 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4038 4039 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4040 sc->last_status_idx); 4041 4042 val = REG_RD(sc, BNX_HC_COMMAND); 4043 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4044 } 4045 4046 /****************************************************************************/ 4047 /* Handles controller initialization. */ 4048 /* */ 4049 /****************************************************************************/ 4050 int 4051 bnx_init(struct ifnet *ifp) 4052 { 4053 struct bnx_softc *sc = ifp->if_softc; 4054 u_int32_t ether_mtu; 4055 int s, error = 0; 4056 4057 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4058 4059 s = splnet(); 4060 4061 bnx_stop(ifp, 0); 4062 4063 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4064 aprint_error("bnx: Controller reset failed!\n"); 4065 goto bnx_init_exit; 4066 } 4067 4068 if ((error = bnx_chipinit(sc)) != 0) { 4069 aprint_error("bnx: Controller initialization failed!\n"); 4070 goto bnx_init_exit; 4071 } 4072 4073 if ((error = bnx_blockinit(sc)) != 0) { 4074 aprint_error("bnx: Block initialization failed!\n"); 4075 goto bnx_init_exit; 4076 } 4077 4078 /* Calculate and program the Ethernet MRU size. */ 4079 if (ifp->if_mtu <= ETHERMTU) { 4080 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4081 sc->mbuf_alloc_size = MCLBYTES; 4082 } else { 4083 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4084 sc->mbuf_alloc_size = BNX_MAX_MRU; 4085 } 4086 4087 4088 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4089 __func__, ether_mtu); 4090 4091 /* 4092 * Program the MRU and enable Jumbo frame 4093 * support. 4094 */ 4095 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4096 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4097 4098 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4099 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4100 4101 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4102 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4103 sc->mbuf_alloc_size, sc->max_frame_size); 4104 4105 /* Program appropriate promiscuous/multicast filtering. */ 4106 bnx_set_rx_mode(sc); 4107 4108 /* Init RX buffer descriptor chain. */ 4109 bnx_init_rx_chain(sc); 4110 4111 /* Init TX buffer descriptor chain. */ 4112 bnx_init_tx_chain(sc); 4113 4114 /* Enable host interrupts. */ 4115 bnx_enable_intr(sc); 4116 4117 if ((error = bnx_ifmedia_upd(ifp)) != 0) 4118 goto bnx_init_exit; 4119 4120 ifp->if_flags |= IFF_RUNNING; 4121 ifp->if_flags &= ~IFF_OACTIVE; 4122 4123 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4124 4125 bnx_init_exit: 4126 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4127 4128 splx(s); 4129 4130 return(error); 4131 } 4132 4133 /****************************************************************************/ 4134 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4135 /* memory visible to the controller. */ 4136 /* */ 4137 /* Returns: */ 4138 /* 0 for success, positive value for failure. */ 4139 /****************************************************************************/ 4140 int 4141 bnx_tx_encap(struct bnx_softc *sc, struct mbuf **m_head) 4142 { 4143 bus_dmamap_t map; 4144 struct tx_bd *txbd = NULL; 4145 struct mbuf *m0; 4146 u_int16_t vlan_tag = 0, flags = 0; 4147 u_int16_t chain_prod, prod; 4148 #ifdef BNX_DEBUG 4149 u_int16_t debug_prod; 4150 #endif 4151 u_int32_t addr, prod_bseq; 4152 int i, error, rc = 0; 4153 struct m_tag *mtag; 4154 4155 m0 = *m_head; 4156 4157 /* Transfer any checksum offload flags to the bd. */ 4158 if (m0->m_pkthdr.csum_flags) { 4159 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 4160 flags |= TX_BD_FLAGS_IP_CKSUM; 4161 if (m0->m_pkthdr.csum_flags & 4162 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4163 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4164 } 4165 4166 /* Transfer any VLAN tags to the bd. */ 4167 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m0); 4168 if (mtag != NULL) { 4169 flags |= TX_BD_FLAGS_VLAN_TAG; 4170 vlan_tag = VLAN_TAG_VALUE(mtag); 4171 } 4172 4173 /* Map the mbuf into DMAable memory. */ 4174 prod = sc->tx_prod; 4175 chain_prod = TX_CHAIN_IDX(prod); 4176 map = sc->tx_mbuf_map[chain_prod]; 4177 4178 /* Map the mbuf into our DMA address space. */ 4179 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m0, BUS_DMA_NOWAIT); 4180 if (error != 0) { 4181 aprint_error_dev(sc->bnx_dev, 4182 "Error mapping mbuf into TX chain!\n"); 4183 m_freem(m0); 4184 *m_head = NULL; 4185 return (error); 4186 } 4187 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4188 BUS_DMASYNC_PREWRITE); 4189 /* 4190 * The chip seems to require that at least 16 descriptors be kept 4191 * empty at all times. Make sure we honor that. 4192 * XXX Would it be faster to assume worst case scenario for 4193 * map->dm_nsegs and do this calculation higher up? 4194 */ 4195 if (map->dm_nsegs > (USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE)) { 4196 bus_dmamap_unload(sc->bnx_dmatag, map); 4197 return (ENOBUFS); 4198 } 4199 4200 /* prod points to an empty tx_bd at this point. */ 4201 prod_bseq = sc->tx_prod_bseq; 4202 #ifdef BNX_DEBUG 4203 debug_prod = chain_prod; 4204 #endif 4205 DBPRINT(sc, BNX_INFO_SEND, 4206 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4207 "prod_bseq = 0x%08X\n", 4208 __func__, *prod, chain_prod, prod_bseq); 4209 4210 /* 4211 * Cycle through each mbuf segment that makes up 4212 * the outgoing frame, gathering the mapping info 4213 * for that segment and creating a tx_bd for the 4214 * mbuf. 4215 */ 4216 for (i = 0; i < map->dm_nsegs ; i++) { 4217 chain_prod = TX_CHAIN_IDX(prod); 4218 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4219 4220 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 4221 txbd->tx_bd_haddr_lo = htole32(addr); 4222 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4223 txbd->tx_bd_haddr_hi = htole32(addr); 4224 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 4225 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4226 txbd->tx_bd_flags = htole16(flags); 4227 prod_bseq += map->dm_segs[i].ds_len; 4228 if (i == 0) 4229 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4230 prod = NEXT_TX_BD(prod); 4231 } 4232 /* Set the END flag on the last TX buffer descriptor. */ 4233 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4234 4235 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg)); 4236 4237 DBPRINT(sc, BNX_INFO_SEND, 4238 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4239 "prod_bseq = 0x%08X\n", 4240 __func__, prod, chain_prod, prod_bseq); 4241 4242 /* 4243 * Ensure that the mbuf pointer for this 4244 * transmission is placed at the array 4245 * index of the last descriptor in this 4246 * chain. This is done because a single 4247 * map is used for all segments of the mbuf 4248 * and we don't want to unload the map before 4249 * all of the segments have been freed. 4250 */ 4251 sc->tx_mbuf_ptr[chain_prod] = m0; 4252 sc->used_tx_bd += map->dm_nsegs; 4253 4254 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4255 sc->tx_hi_watermark = sc->used_tx_bd); 4256 4257 DBRUNIF(1, sc->tx_mbuf_alloc++); 4258 4259 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4260 map_arg.maxsegs)); 4261 4262 /* prod points to the next free tx_bd at this point. */ 4263 sc->tx_prod = prod; 4264 sc->tx_prod_bseq = prod_bseq; 4265 4266 return (rc); 4267 } 4268 4269 /****************************************************************************/ 4270 /* Main transmit routine. */ 4271 /* */ 4272 /* Returns: */ 4273 /* Nothing. */ 4274 /****************************************************************************/ 4275 void 4276 bnx_start(struct ifnet *ifp) 4277 { 4278 struct bnx_softc *sc = ifp->if_softc; 4279 struct mbuf *m_head = NULL; 4280 int count = 0; 4281 u_int16_t tx_prod, tx_chain_prod; 4282 4283 /* If there's no link or the transmit queue is empty then just exit. */ 4284 if (!sc->bnx_link || IFQ_IS_EMPTY(&ifp->if_snd)) { 4285 DBPRINT(sc, BNX_INFO_SEND, 4286 "%s(): No link or transmit queue empty.\n", __func__); 4287 goto bnx_start_exit; 4288 } 4289 4290 /* prod points to the next free tx_bd. */ 4291 tx_prod = sc->tx_prod; 4292 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4293 4294 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 4295 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n", 4296 __func__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4297 4298 /* 4299 * Keep adding entries while there is space in the ring. We keep 4300 * BNX_TX_SLACK_SPACE entries unused at all times. 4301 */ 4302 while (sc->used_tx_bd < USABLE_TX_BD - BNX_TX_SLACK_SPACE) { 4303 /* Check for any frames to send. */ 4304 IFQ_POLL(&ifp->if_snd, m_head); 4305 if (m_head == NULL) 4306 break; 4307 4308 /* 4309 * Pack the data into the transmit ring. If we 4310 * don't have room, set the OACTIVE flag to wait 4311 * for the NIC to drain the chain. 4312 */ 4313 if (bnx_tx_encap(sc, &m_head)) { 4314 ifp->if_flags |= IFF_OACTIVE; 4315 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 4316 "business! Total tx_bd used = %d\n", 4317 sc->used_tx_bd); 4318 break; 4319 } 4320 4321 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4322 count++; 4323 4324 #if NBPFILTER > 0 4325 /* Send a copy of the frame to any BPF listeners. */ 4326 if (ifp->if_bpf) 4327 bpf_mtap(ifp->if_bpf, m_head); 4328 #endif 4329 } 4330 4331 if (count == 0) { 4332 /* no packets were dequeued */ 4333 DBPRINT(sc, BNX_VERBOSE_SEND, 4334 "%s(): No packets were dequeued\n", __func__); 4335 goto bnx_start_exit; 4336 } 4337 4338 /* Update the driver's counters. */ 4339 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4340 4341 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 4342 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, tx_prod, 4343 tx_chain_prod, sc->tx_prod_bseq); 4344 4345 /* Start the transmit. */ 4346 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4347 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4348 4349 /* Set the tx timeout. */ 4350 ifp->if_timer = BNX_TX_TIMEOUT; 4351 4352 bnx_start_exit: 4353 return; 4354 } 4355 4356 /****************************************************************************/ 4357 /* Handles any IOCTL calls from the operating system. */ 4358 /* */ 4359 /* Returns: */ 4360 /* 0 for success, positive value for failure. */ 4361 /****************************************************************************/ 4362 int 4363 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 4364 { 4365 struct bnx_softc *sc = ifp->if_softc; 4366 struct ifreq *ifr = (struct ifreq *) data; 4367 struct mii_data *mii; 4368 int s, error = 0; 4369 4370 s = splnet(); 4371 4372 switch (command) { 4373 case SIOCSIFFLAGS: 4374 if (ifp->if_flags & IFF_UP) { 4375 if ((ifp->if_flags & IFF_RUNNING) && 4376 ((ifp->if_flags ^ sc->bnx_if_flags) & 4377 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 4378 bnx_set_rx_mode(sc); 4379 } else if (!(ifp->if_flags & IFF_RUNNING)) 4380 bnx_init(ifp); 4381 4382 } else if (ifp->if_flags & IFF_RUNNING) 4383 bnx_stop(ifp, 1); 4384 4385 sc->bnx_if_flags = ifp->if_flags; 4386 break; 4387 4388 case SIOCSIFMEDIA: 4389 case SIOCGIFMEDIA: 4390 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 4391 sc->bnx_phy_flags); 4392 4393 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 4394 error = ifmedia_ioctl(ifp, ifr, 4395 &sc->bnx_ifmedia, command); 4396 else { 4397 mii = &sc->bnx_mii; 4398 error = ifmedia_ioctl(ifp, ifr, 4399 &mii->mii_media, command); 4400 } 4401 break; 4402 4403 default: 4404 error = ether_ioctl(ifp, command, data); 4405 if (error != ENETRESET) 4406 break; 4407 error = 0; 4408 if (command == SIOCADDMULTI || command == SIOCDELMULTI) { 4409 /* reload packet filter if running */ 4410 if (ifp->if_flags & IFF_RUNNING) 4411 bnx_set_rx_mode(sc); 4412 } 4413 break; 4414 } 4415 4416 splx(s); 4417 4418 return (error); 4419 } 4420 4421 /****************************************************************************/ 4422 /* Transmit timeout handler. */ 4423 /* */ 4424 /* Returns: */ 4425 /* Nothing. */ 4426 /****************************************************************************/ 4427 void 4428 bnx_watchdog(struct ifnet *ifp) 4429 { 4430 struct bnx_softc *sc = ifp->if_softc; 4431 4432 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 4433 bnx_dump_status_block(sc)); 4434 4435 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 4436 4437 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 4438 4439 bnx_init(ifp); 4440 4441 ifp->if_oerrors++; 4442 } 4443 4444 /* 4445 * Interrupt handler. 4446 */ 4447 /****************************************************************************/ 4448 /* Main interrupt entry point. Verifies that the controller generated the */ 4449 /* interrupt and then calls a separate routine for handle the various */ 4450 /* interrupt causes (PHY, TX, RX). */ 4451 /* */ 4452 /* Returns: */ 4453 /* 0 for success, positive value for failure. */ 4454 /****************************************************************************/ 4455 int 4456 bnx_intr(void *xsc) 4457 { 4458 struct bnx_softc *sc; 4459 struct ifnet *ifp; 4460 u_int32_t status_attn_bits; 4461 const struct status_block *sblk; 4462 4463 sc = xsc; 4464 if (!device_is_active(sc->bnx_dev)) 4465 return 0; 4466 4467 ifp = &sc->bnx_ec.ec_if; 4468 4469 DBRUNIF(1, sc->interrupts_generated++); 4470 4471 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4472 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4473 4474 /* 4475 * If the hardware status block index 4476 * matches the last value read by the 4477 * driver and we haven't asserted our 4478 * interrupt then there's nothing to do. 4479 */ 4480 if ((sc->status_block->status_idx == sc->last_status_idx) && 4481 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 4482 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 4483 return (0); 4484 4485 /* Ack the interrupt and stop others from occuring. */ 4486 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4487 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 4488 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4489 4490 /* Keep processing data as long as there is work to do. */ 4491 for (;;) { 4492 sblk = sc->status_block; 4493 status_attn_bits = sblk->status_attn_bits; 4494 4495 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 4496 aprint_debug("Simulating unexpected status attention bit set."); 4497 status_attn_bits = status_attn_bits | 4498 STATUS_ATTN_BITS_PARITY_ERROR); 4499 4500 /* Was it a link change interrupt? */ 4501 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 4502 (sblk->status_attn_bits_ack & 4503 STATUS_ATTN_BITS_LINK_STATE)) 4504 bnx_phy_intr(sc); 4505 4506 /* If any other attention is asserted then the chip is toast. */ 4507 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 4508 (sblk->status_attn_bits_ack & 4509 ~STATUS_ATTN_BITS_LINK_STATE))) { 4510 DBRUN(1, sc->unexpected_attentions++); 4511 4512 aprint_error_dev(sc->bnx_dev, 4513 "Fatal attention detected: 0x%08X\n", 4514 sblk->status_attn_bits); 4515 4516 DBRUN(BNX_FATAL, 4517 if (bnx_debug_unexpected_attention == 0) 4518 bnx_breakpoint(sc)); 4519 4520 bnx_init(ifp); 4521 return (1); 4522 } 4523 4524 /* Check for any completed RX frames. */ 4525 if (sblk->status_rx_quick_consumer_index0 != 4526 sc->hw_rx_cons) 4527 bnx_rx_intr(sc); 4528 4529 /* Check for any completed TX frames. */ 4530 if (sblk->status_tx_quick_consumer_index0 != 4531 sc->hw_tx_cons) 4532 bnx_tx_intr(sc); 4533 4534 /* Save the status block index value for use during the 4535 * next interrupt. 4536 */ 4537 sc->last_status_idx = sblk->status_idx; 4538 4539 /* Prevent speculative reads from getting ahead of the 4540 * status block. 4541 */ 4542 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4543 BUS_SPACE_BARRIER_READ); 4544 4545 /* If there's no work left then exit the isr. */ 4546 if ((sblk->status_rx_quick_consumer_index0 == 4547 sc->hw_rx_cons) && 4548 (sblk->status_tx_quick_consumer_index0 == 4549 sc->hw_tx_cons)) 4550 break; 4551 } 4552 4553 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4554 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 4555 4556 /* Re-enable interrupts. */ 4557 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4558 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 4559 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4560 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4561 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4562 4563 /* Handle any frames that arrived while handling the interrupt. */ 4564 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4565 bnx_start(ifp); 4566 4567 return (1); 4568 } 4569 4570 /****************************************************************************/ 4571 /* Programs the various packet receive modes (broadcast and multicast). */ 4572 /* */ 4573 /* Returns: */ 4574 /* Nothing. */ 4575 /****************************************************************************/ 4576 void 4577 bnx_set_rx_mode(struct bnx_softc *sc) 4578 { 4579 struct ethercom *ec = &sc->bnx_ec; 4580 struct ifnet *ifp = &ec->ec_if; 4581 struct ether_multi *enm; 4582 struct ether_multistep step; 4583 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 4584 u_int32_t rx_mode, sort_mode; 4585 int h, i; 4586 4587 /* Initialize receive mode default settings. */ 4588 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 4589 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 4590 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 4591 4592 /* 4593 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 4594 * be enbled. 4595 */ 4596 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 4597 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 4598 4599 /* 4600 * Check for promiscuous, all multicast, or selected 4601 * multicast address filtering. 4602 */ 4603 if (ifp->if_flags & IFF_PROMISC) { 4604 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 4605 4606 /* Enable promiscuous mode. */ 4607 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 4608 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 4609 } else if (ifp->if_flags & IFF_ALLMULTI) { 4610 allmulti: 4611 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 4612 4613 /* Enable all multicast addresses. */ 4614 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4615 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4616 0xffffffff); 4617 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 4618 } else { 4619 /* Accept one or more multicast(s). */ 4620 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 4621 4622 ETHER_FIRST_MULTI(step, ec, enm); 4623 while (enm != NULL) { 4624 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 4625 ETHER_ADDR_LEN)) { 4626 ifp->if_flags |= IFF_ALLMULTI; 4627 goto allmulti; 4628 } 4629 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 4630 0xFF; 4631 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 4632 ETHER_NEXT_MULTI(step, enm); 4633 } 4634 4635 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4636 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4637 hashes[i]); 4638 4639 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 4640 } 4641 4642 /* Only make changes if the recive mode has actually changed. */ 4643 if (rx_mode != sc->rx_mode) { 4644 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 4645 rx_mode); 4646 4647 sc->rx_mode = rx_mode; 4648 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 4649 } 4650 4651 /* Disable and clear the exisitng sort before enabling a new sort. */ 4652 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 4653 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 4654 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 4655 } 4656 4657 /****************************************************************************/ 4658 /* Called periodically to updates statistics from the controllers */ 4659 /* statistics block. */ 4660 /* */ 4661 /* Returns: */ 4662 /* Nothing. */ 4663 /****************************************************************************/ 4664 void 4665 bnx_stats_update(struct bnx_softc *sc) 4666 { 4667 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4668 struct statistics_block *stats; 4669 4670 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 4671 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4672 BUS_DMASYNC_POSTREAD); 4673 4674 stats = (struct statistics_block *)sc->stats_block; 4675 4676 /* 4677 * Update the interface statistics from the 4678 * hardware statistics. 4679 */ 4680 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 4681 4682 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 4683 (u_long)stats->stat_EtherStatsOverrsizePkts + 4684 (u_long)stats->stat_IfInMBUFDiscards + 4685 (u_long)stats->stat_Dot3StatsAlignmentErrors + 4686 (u_long)stats->stat_Dot3StatsFCSErrors; 4687 4688 ifp->if_oerrors = (u_long) 4689 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 4690 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 4691 (u_long)stats->stat_Dot3StatsLateCollisions; 4692 4693 /* 4694 * Certain controllers don't report 4695 * carrier sense errors correctly. 4696 * See errata E11_5708CA0_1165. 4697 */ 4698 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 4699 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 4700 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 4701 4702 /* 4703 * Update the sysctl statistics from the 4704 * hardware statistics. 4705 */ 4706 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 4707 (u_int64_t) stats->stat_IfHCInOctets_lo; 4708 4709 sc->stat_IfHCInBadOctets = 4710 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 4711 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 4712 4713 sc->stat_IfHCOutOctets = 4714 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 4715 (u_int64_t) stats->stat_IfHCOutOctets_lo; 4716 4717 sc->stat_IfHCOutBadOctets = 4718 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 4719 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 4720 4721 sc->stat_IfHCInUcastPkts = 4722 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 4723 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 4724 4725 sc->stat_IfHCInMulticastPkts = 4726 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 4727 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 4728 4729 sc->stat_IfHCInBroadcastPkts = 4730 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 4731 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 4732 4733 sc->stat_IfHCOutUcastPkts = 4734 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 4735 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 4736 4737 sc->stat_IfHCOutMulticastPkts = 4738 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 4739 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 4740 4741 sc->stat_IfHCOutBroadcastPkts = 4742 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 4743 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 4744 4745 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 4746 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4747 4748 sc->stat_Dot3StatsCarrierSenseErrors = 4749 stats->stat_Dot3StatsCarrierSenseErrors; 4750 4751 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 4752 4753 sc->stat_Dot3StatsAlignmentErrors = 4754 stats->stat_Dot3StatsAlignmentErrors; 4755 4756 sc->stat_Dot3StatsSingleCollisionFrames = 4757 stats->stat_Dot3StatsSingleCollisionFrames; 4758 4759 sc->stat_Dot3StatsMultipleCollisionFrames = 4760 stats->stat_Dot3StatsMultipleCollisionFrames; 4761 4762 sc->stat_Dot3StatsDeferredTransmissions = 4763 stats->stat_Dot3StatsDeferredTransmissions; 4764 4765 sc->stat_Dot3StatsExcessiveCollisions = 4766 stats->stat_Dot3StatsExcessiveCollisions; 4767 4768 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 4769 4770 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 4771 4772 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 4773 4774 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 4775 4776 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 4777 4778 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 4779 4780 sc->stat_EtherStatsPktsRx64Octets = 4781 stats->stat_EtherStatsPktsRx64Octets; 4782 4783 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 4784 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 4785 4786 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 4787 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 4788 4789 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 4790 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 4791 4792 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 4793 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 4794 4795 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 4796 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 4797 4798 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 4799 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 4800 4801 sc->stat_EtherStatsPktsTx64Octets = 4802 stats->stat_EtherStatsPktsTx64Octets; 4803 4804 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 4805 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 4806 4807 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 4808 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 4809 4810 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 4811 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 4812 4813 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 4814 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 4815 4816 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 4817 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 4818 4819 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 4820 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 4821 4822 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 4823 4824 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 4825 4826 sc->stat_OutXonSent = stats->stat_OutXonSent; 4827 4828 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 4829 4830 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 4831 4832 sc->stat_MacControlFramesReceived = 4833 stats->stat_MacControlFramesReceived; 4834 4835 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 4836 4837 sc->stat_IfInFramesL2FilterDiscards = 4838 stats->stat_IfInFramesL2FilterDiscards; 4839 4840 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 4841 4842 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 4843 4844 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 4845 4846 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 4847 4848 sc->stat_CatchupInRuleCheckerDiscards = 4849 stats->stat_CatchupInRuleCheckerDiscards; 4850 4851 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 4852 4853 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 4854 4855 sc->stat_CatchupInRuleCheckerP4Hit = 4856 stats->stat_CatchupInRuleCheckerP4Hit; 4857 4858 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 4859 } 4860 4861 void 4862 bnx_tick(void *xsc) 4863 { 4864 struct bnx_softc *sc = xsc; 4865 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4866 struct mii_data *mii; 4867 u_int32_t msg; 4868 u_int16_t prod, chain_prod; 4869 u_int32_t prod_bseq; 4870 int s = splnet(); 4871 4872 /* Tell the firmware that the driver is still running. */ 4873 #ifdef BNX_DEBUG 4874 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 4875 #else 4876 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 4877 #endif 4878 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 4879 4880 /* Update the statistics from the hardware statistics block. */ 4881 bnx_stats_update(sc); 4882 4883 /* Schedule the next tick. */ 4884 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4885 4886 /* DRC - ToDo: Add SerDes support and check SerDes link here. */ 4887 4888 mii = &sc->bnx_mii; 4889 mii_tick(mii); 4890 4891 /* If link is up already up then we're done. */ 4892 if (sc->bnx_link) 4893 goto bnx_tick_exit; 4894 4895 /* Check if the link has come up. */ 4896 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 4897 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4898 sc->bnx_link++; 4899 /* Now that link is up, handle any outstanding TX traffic. */ 4900 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4901 bnx_start(ifp); 4902 } 4903 4904 bnx_tick_exit: 4905 /* try to get more RX buffers, just in case */ 4906 prod = sc->rx_prod; 4907 prod_bseq = sc->rx_prod_bseq; 4908 chain_prod = RX_CHAIN_IDX(prod); 4909 bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq); 4910 sc->rx_prod = prod; 4911 sc->rx_prod_bseq = prod_bseq; 4912 splx(s); 4913 return; 4914 } 4915 4916 /****************************************************************************/ 4917 /* BNX Debug Routines */ 4918 /****************************************************************************/ 4919 #ifdef BNX_DEBUG 4920 4921 /****************************************************************************/ 4922 /* Prints out information about an mbuf. */ 4923 /* */ 4924 /* Returns: */ 4925 /* Nothing. */ 4926 /****************************************************************************/ 4927 void 4928 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 4929 { 4930 struct mbuf *mp = m; 4931 4932 if (m == NULL) { 4933 /* Index out of range. */ 4934 aprint_error("mbuf ptr is null!\n"); 4935 return; 4936 } 4937 4938 while (mp) { 4939 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 4940 mp, mp->m_len); 4941 4942 if (mp->m_flags & M_EXT) 4943 aprint_debug("M_EXT "); 4944 if (mp->m_flags & M_PKTHDR) 4945 aprint_debug("M_PKTHDR "); 4946 aprint_debug("\n"); 4947 4948 if (mp->m_flags & M_EXT) 4949 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 4950 mp, mp->m_ext.ext_size); 4951 4952 mp = mp->m_next; 4953 } 4954 } 4955 4956 /****************************************************************************/ 4957 /* Prints out the mbufs in the TX mbuf chain. */ 4958 /* */ 4959 /* Returns: */ 4960 /* Nothing. */ 4961 /****************************************************************************/ 4962 void 4963 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4964 { 4965 struct mbuf *m; 4966 int i; 4967 4968 BNX_PRINTF(sc, 4969 "----------------------------" 4970 " tx mbuf data " 4971 "----------------------------\n"); 4972 4973 for (i = 0; i < count; i++) { 4974 m = sc->tx_mbuf_ptr[chain_prod]; 4975 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 4976 bnx_dump_mbuf(sc, m); 4977 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 4978 } 4979 4980 BNX_PRINTF(sc, 4981 "--------------------------------------------" 4982 "----------------------------\n"); 4983 } 4984 4985 /* 4986 * This routine prints the RX mbuf chain. 4987 */ 4988 void 4989 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4990 { 4991 struct mbuf *m; 4992 int i; 4993 4994 BNX_PRINTF(sc, 4995 "----------------------------" 4996 " rx mbuf data " 4997 "----------------------------\n"); 4998 4999 for (i = 0; i < count; i++) { 5000 m = sc->rx_mbuf_ptr[chain_prod]; 5001 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5002 bnx_dump_mbuf(sc, m); 5003 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5004 } 5005 5006 5007 BNX_PRINTF(sc, 5008 "--------------------------------------------" 5009 "----------------------------\n"); 5010 } 5011 5012 void 5013 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5014 { 5015 if (idx > MAX_TX_BD) 5016 /* Index out of range. */ 5017 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5018 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5019 /* TX Chain page pointer. */ 5020 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5021 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5022 txbd->tx_bd_haddr_lo); 5023 else 5024 /* Normal tx_bd entry. */ 5025 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5026 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5027 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5028 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5029 txbd->tx_bd_flags); 5030 } 5031 5032 void 5033 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5034 { 5035 if (idx > MAX_RX_BD) 5036 /* Index out of range. */ 5037 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5038 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5039 /* TX Chain page pointer. */ 5040 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5041 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5042 rxbd->rx_bd_haddr_lo); 5043 else 5044 /* Normal tx_bd entry. */ 5045 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5046 "0x%08X, flags = 0x%08X\n", idx, 5047 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5048 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5049 } 5050 5051 void 5052 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5053 { 5054 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5055 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5056 "tcp_udp_xsum = 0x%04X\n", idx, 5057 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5058 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5059 l2fhdr->l2_fhdr_tcp_udp_xsum); 5060 } 5061 5062 /* 5063 * This routine prints the TX chain. 5064 */ 5065 void 5066 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5067 { 5068 struct tx_bd *txbd; 5069 int i; 5070 5071 /* First some info about the tx_bd chain structure. */ 5072 BNX_PRINTF(sc, 5073 "----------------------------" 5074 " tx_bd chain " 5075 "----------------------------\n"); 5076 5077 BNX_PRINTF(sc, 5078 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5079 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5080 5081 BNX_PRINTF(sc, 5082 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5083 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5084 5085 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD); 5086 5087 BNX_PRINTF(sc, "" 5088 "-----------------------------" 5089 " tx_bd data " 5090 "-----------------------------\n"); 5091 5092 /* Now print out the tx_bd's themselves. */ 5093 for (i = 0; i < count; i++) { 5094 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5095 bnx_dump_txbd(sc, tx_prod, txbd); 5096 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5097 } 5098 5099 BNX_PRINTF(sc, 5100 "-----------------------------" 5101 "--------------" 5102 "-----------------------------\n"); 5103 } 5104 5105 /* 5106 * This routine prints the RX chain. 5107 */ 5108 void 5109 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5110 { 5111 struct rx_bd *rxbd; 5112 int i; 5113 5114 /* First some info about the tx_bd chain structure. */ 5115 BNX_PRINTF(sc, 5116 "----------------------------" 5117 " rx_bd chain " 5118 "----------------------------\n"); 5119 5120 BNX_PRINTF(sc, "----- RX_BD Chain -----\n"); 5121 5122 BNX_PRINTF(sc, 5123 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5124 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5125 5126 BNX_PRINTF(sc, 5127 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5128 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5129 5130 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD); 5131 5132 BNX_PRINTF(sc, 5133 "----------------------------" 5134 " rx_bd data " 5135 "----------------------------\n"); 5136 5137 /* Now print out the rx_bd's themselves. */ 5138 for (i = 0; i < count; i++) { 5139 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5140 bnx_dump_rxbd(sc, rx_prod, rxbd); 5141 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5142 } 5143 5144 BNX_PRINTF(sc, 5145 "----------------------------" 5146 "--------------" 5147 "----------------------------\n"); 5148 } 5149 5150 /* 5151 * This routine prints the status block. 5152 */ 5153 void 5154 bnx_dump_status_block(struct bnx_softc *sc) 5155 { 5156 struct status_block *sblk; 5157 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5158 BUS_DMASYNC_POSTREAD); 5159 5160 sblk = sc->status_block; 5161 5162 BNX_PRINTF(sc, "----------------------------- Status Block " 5163 "-----------------------------\n"); 5164 5165 BNX_PRINTF(sc, 5166 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5167 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5168 sblk->status_idx); 5169 5170 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5171 sblk->status_rx_quick_consumer_index0, 5172 sblk->status_tx_quick_consumer_index0); 5173 5174 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5175 5176 /* Theses indices are not used for normal L2 drivers. */ 5177 if (sblk->status_rx_quick_consumer_index1 || 5178 sblk->status_tx_quick_consumer_index1) 5179 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5180 sblk->status_rx_quick_consumer_index1, 5181 sblk->status_tx_quick_consumer_index1); 5182 5183 if (sblk->status_rx_quick_consumer_index2 || 5184 sblk->status_tx_quick_consumer_index2) 5185 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5186 sblk->status_rx_quick_consumer_index2, 5187 sblk->status_tx_quick_consumer_index2); 5188 5189 if (sblk->status_rx_quick_consumer_index3 || 5190 sblk->status_tx_quick_consumer_index3) 5191 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5192 sblk->status_rx_quick_consumer_index3, 5193 sblk->status_tx_quick_consumer_index3); 5194 5195 if (sblk->status_rx_quick_consumer_index4 || 5196 sblk->status_rx_quick_consumer_index5) 5197 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5198 sblk->status_rx_quick_consumer_index4, 5199 sblk->status_rx_quick_consumer_index5); 5200 5201 if (sblk->status_rx_quick_consumer_index6 || 5202 sblk->status_rx_quick_consumer_index7) 5203 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5204 sblk->status_rx_quick_consumer_index6, 5205 sblk->status_rx_quick_consumer_index7); 5206 5207 if (sblk->status_rx_quick_consumer_index8 || 5208 sblk->status_rx_quick_consumer_index9) 5209 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5210 sblk->status_rx_quick_consumer_index8, 5211 sblk->status_rx_quick_consumer_index9); 5212 5213 if (sblk->status_rx_quick_consumer_index10 || 5214 sblk->status_rx_quick_consumer_index11) 5215 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5216 sblk->status_rx_quick_consumer_index10, 5217 sblk->status_rx_quick_consumer_index11); 5218 5219 if (sblk->status_rx_quick_consumer_index12 || 5220 sblk->status_rx_quick_consumer_index13) 5221 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5222 sblk->status_rx_quick_consumer_index12, 5223 sblk->status_rx_quick_consumer_index13); 5224 5225 if (sblk->status_rx_quick_consumer_index14 || 5226 sblk->status_rx_quick_consumer_index15) 5227 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5228 sblk->status_rx_quick_consumer_index14, 5229 sblk->status_rx_quick_consumer_index15); 5230 5231 if (sblk->status_completion_producer_index || 5232 sblk->status_cmd_consumer_index) 5233 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5234 sblk->status_completion_producer_index, 5235 sblk->status_cmd_consumer_index); 5236 5237 BNX_PRINTF(sc, "-------------------------------------------" 5238 "-----------------------------\n"); 5239 } 5240 5241 /* 5242 * This routine prints the statistics block. 5243 */ 5244 void 5245 bnx_dump_stats_block(struct bnx_softc *sc) 5246 { 5247 struct statistics_block *sblk; 5248 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5249 BUS_DMASYNC_POSTREAD); 5250 5251 sblk = sc->stats_block; 5252 5253 BNX_PRINTF(sc, "" 5254 "-----------------------------" 5255 " Stats Block " 5256 "-----------------------------\n"); 5257 5258 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5259 "IfHcInBadOctets = 0x%08X:%08X\n", 5260 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5261 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5262 5263 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5264 "IfHcOutBadOctets = 0x%08X:%08X\n", 5265 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5266 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5267 5268 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5269 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5270 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5271 sblk->stat_IfHCInMulticastPkts_hi, 5272 sblk->stat_IfHCInMulticastPkts_lo); 5273 5274 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5275 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5276 sblk->stat_IfHCInBroadcastPkts_hi, 5277 sblk->stat_IfHCInBroadcastPkts_lo, 5278 sblk->stat_IfHCOutUcastPkts_hi, 5279 sblk->stat_IfHCOutUcastPkts_lo); 5280 5281 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5282 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5283 sblk->stat_IfHCOutMulticastPkts_hi, 5284 sblk->stat_IfHCOutMulticastPkts_lo, 5285 sblk->stat_IfHCOutBroadcastPkts_hi, 5286 sblk->stat_IfHCOutBroadcastPkts_lo); 5287 5288 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5289 BNX_PRINTF(sc, "0x%08X : " 5290 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5291 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5292 5293 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5294 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5295 sblk->stat_Dot3StatsCarrierSenseErrors); 5296 5297 if (sblk->stat_Dot3StatsFCSErrors) 5298 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5299 sblk->stat_Dot3StatsFCSErrors); 5300 5301 if (sblk->stat_Dot3StatsAlignmentErrors) 5302 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5303 sblk->stat_Dot3StatsAlignmentErrors); 5304 5305 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5306 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5307 sblk->stat_Dot3StatsSingleCollisionFrames); 5308 5309 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5310 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 5311 sblk->stat_Dot3StatsMultipleCollisionFrames); 5312 5313 if (sblk->stat_Dot3StatsDeferredTransmissions) 5314 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 5315 sblk->stat_Dot3StatsDeferredTransmissions); 5316 5317 if (sblk->stat_Dot3StatsExcessiveCollisions) 5318 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 5319 sblk->stat_Dot3StatsExcessiveCollisions); 5320 5321 if (sblk->stat_Dot3StatsLateCollisions) 5322 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 5323 sblk->stat_Dot3StatsLateCollisions); 5324 5325 if (sblk->stat_EtherStatsCollisions) 5326 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 5327 sblk->stat_EtherStatsCollisions); 5328 5329 if (sblk->stat_EtherStatsFragments) 5330 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 5331 sblk->stat_EtherStatsFragments); 5332 5333 if (sblk->stat_EtherStatsJabbers) 5334 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 5335 sblk->stat_EtherStatsJabbers); 5336 5337 if (sblk->stat_EtherStatsUndersizePkts) 5338 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 5339 sblk->stat_EtherStatsUndersizePkts); 5340 5341 if (sblk->stat_EtherStatsOverrsizePkts) 5342 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 5343 sblk->stat_EtherStatsOverrsizePkts); 5344 5345 if (sblk->stat_EtherStatsPktsRx64Octets) 5346 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 5347 sblk->stat_EtherStatsPktsRx64Octets); 5348 5349 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 5350 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 5351 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 5352 5353 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 5354 BNX_PRINTF(sc, "0x%08X : " 5355 "EtherStatsPktsRx128Octetsto255Octets\n", 5356 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 5357 5358 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 5359 BNX_PRINTF(sc, "0x%08X : " 5360 "EtherStatsPktsRx256Octetsto511Octets\n", 5361 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 5362 5363 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 5364 BNX_PRINTF(sc, "0x%08X : " 5365 "EtherStatsPktsRx512Octetsto1023Octets\n", 5366 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 5367 5368 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 5369 BNX_PRINTF(sc, "0x%08X : " 5370 "EtherStatsPktsRx1024Octetsto1522Octets\n", 5371 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 5372 5373 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 5374 BNX_PRINTF(sc, "0x%08X : " 5375 "EtherStatsPktsRx1523Octetsto9022Octets\n", 5376 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 5377 5378 if (sblk->stat_EtherStatsPktsTx64Octets) 5379 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 5380 sblk->stat_EtherStatsPktsTx64Octets); 5381 5382 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 5383 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 5384 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 5385 5386 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 5387 BNX_PRINTF(sc, "0x%08X : " 5388 "EtherStatsPktsTx128Octetsto255Octets\n", 5389 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 5390 5391 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 5392 BNX_PRINTF(sc, "0x%08X : " 5393 "EtherStatsPktsTx256Octetsto511Octets\n", 5394 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 5395 5396 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 5397 BNX_PRINTF(sc, "0x%08X : " 5398 "EtherStatsPktsTx512Octetsto1023Octets\n", 5399 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 5400 5401 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 5402 BNX_PRINTF(sc, "0x%08X : " 5403 "EtherStatsPktsTx1024Octetsto1522Octets\n", 5404 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 5405 5406 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 5407 BNX_PRINTF(sc, "0x%08X : " 5408 "EtherStatsPktsTx1523Octetsto9022Octets\n", 5409 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 5410 5411 if (sblk->stat_XonPauseFramesReceived) 5412 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 5413 sblk->stat_XonPauseFramesReceived); 5414 5415 if (sblk->stat_XoffPauseFramesReceived) 5416 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 5417 sblk->stat_XoffPauseFramesReceived); 5418 5419 if (sblk->stat_OutXonSent) 5420 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 5421 sblk->stat_OutXonSent); 5422 5423 if (sblk->stat_OutXoffSent) 5424 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 5425 sblk->stat_OutXoffSent); 5426 5427 if (sblk->stat_FlowControlDone) 5428 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 5429 sblk->stat_FlowControlDone); 5430 5431 if (sblk->stat_MacControlFramesReceived) 5432 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 5433 sblk->stat_MacControlFramesReceived); 5434 5435 if (sblk->stat_XoffStateEntered) 5436 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 5437 sblk->stat_XoffStateEntered); 5438 5439 if (sblk->stat_IfInFramesL2FilterDiscards) 5440 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 5441 sblk->stat_IfInFramesL2FilterDiscards); 5442 5443 if (sblk->stat_IfInRuleCheckerDiscards) 5444 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 5445 sblk->stat_IfInRuleCheckerDiscards); 5446 5447 if (sblk->stat_IfInFTQDiscards) 5448 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 5449 sblk->stat_IfInFTQDiscards); 5450 5451 if (sblk->stat_IfInMBUFDiscards) 5452 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 5453 sblk->stat_IfInMBUFDiscards); 5454 5455 if (sblk->stat_IfInRuleCheckerP4Hit) 5456 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 5457 sblk->stat_IfInRuleCheckerP4Hit); 5458 5459 if (sblk->stat_CatchupInRuleCheckerDiscards) 5460 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 5461 sblk->stat_CatchupInRuleCheckerDiscards); 5462 5463 if (sblk->stat_CatchupInFTQDiscards) 5464 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 5465 sblk->stat_CatchupInFTQDiscards); 5466 5467 if (sblk->stat_CatchupInMBUFDiscards) 5468 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 5469 sblk->stat_CatchupInMBUFDiscards); 5470 5471 if (sblk->stat_CatchupInRuleCheckerP4Hit) 5472 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 5473 sblk->stat_CatchupInRuleCheckerP4Hit); 5474 5475 BNX_PRINTF(sc, 5476 "-----------------------------" 5477 "--------------" 5478 "-----------------------------\n"); 5479 } 5480 5481 void 5482 bnx_dump_driver_state(struct bnx_softc *sc) 5483 { 5484 BNX_PRINTF(sc, 5485 "-----------------------------" 5486 " Driver State " 5487 "-----------------------------\n"); 5488 5489 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 5490 "address\n", sc); 5491 5492 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 5493 sc->status_block); 5494 5495 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 5496 "address\n", sc->stats_block); 5497 5498 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 5499 "adddress\n", sc->tx_bd_chain); 5500 5501 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 5502 sc->rx_bd_chain); 5503 5504 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 5505 sc->tx_mbuf_ptr); 5506 5507 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 5508 sc->rx_mbuf_ptr); 5509 5510 BNX_PRINTF(sc, 5511 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 5512 sc->interrupts_generated); 5513 5514 BNX_PRINTF(sc, 5515 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 5516 sc->rx_interrupts); 5517 5518 BNX_PRINTF(sc, 5519 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 5520 sc->tx_interrupts); 5521 5522 BNX_PRINTF(sc, 5523 " 0x%08X - (sc->last_status_idx) status block index\n", 5524 sc->last_status_idx); 5525 5526 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 5527 sc->tx_prod); 5528 5529 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 5530 sc->tx_cons); 5531 5532 BNX_PRINTF(sc, 5533 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 5534 sc->tx_prod_bseq); 5535 5536 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 5537 sc->rx_prod); 5538 5539 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 5540 sc->rx_cons); 5541 5542 BNX_PRINTF(sc, 5543 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 5544 sc->rx_prod_bseq); 5545 5546 BNX_PRINTF(sc, 5547 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5548 sc->rx_mbuf_alloc); 5549 5550 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 5551 sc->free_rx_bd); 5552 5553 BNX_PRINTF(sc, 5554 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 5555 sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD); 5556 5557 BNX_PRINTF(sc, 5558 " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 5559 sc->tx_mbuf_alloc); 5560 5561 BNX_PRINTF(sc, 5562 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5563 sc->rx_mbuf_alloc); 5564 5565 BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 5566 sc->used_tx_bd); 5567 5568 BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 5569 sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD); 5570 5571 BNX_PRINTF(sc, 5572 " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 5573 sc->mbuf_alloc_failed); 5574 5575 BNX_PRINTF(sc, "-------------------------------------------" 5576 "-----------------------------\n"); 5577 } 5578 5579 void 5580 bnx_dump_hw_state(struct bnx_softc *sc) 5581 { 5582 u_int32_t val1; 5583 int i; 5584 5585 BNX_PRINTF(sc, 5586 "----------------------------" 5587 " Hardware State " 5588 "----------------------------\n"); 5589 5590 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 5591 5592 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 5593 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 5594 val1, BNX_MISC_ENABLE_STATUS_BITS); 5595 5596 val1 = REG_RD(sc, BNX_DMA_STATUS); 5597 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 5598 5599 val1 = REG_RD(sc, BNX_CTX_STATUS); 5600 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 5601 5602 val1 = REG_RD(sc, BNX_EMAC_STATUS); 5603 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 5604 BNX_EMAC_STATUS); 5605 5606 val1 = REG_RD(sc, BNX_RPM_STATUS); 5607 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 5608 5609 val1 = REG_RD(sc, BNX_TBDR_STATUS); 5610 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 5611 BNX_TBDR_STATUS); 5612 5613 val1 = REG_RD(sc, BNX_TDMA_STATUS); 5614 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 5615 BNX_TDMA_STATUS); 5616 5617 val1 = REG_RD(sc, BNX_HC_STATUS); 5618 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 5619 5620 BNX_PRINTF(sc, 5621 "----------------------------" 5622 "----------------" 5623 "----------------------------\n"); 5624 5625 BNX_PRINTF(sc, 5626 "----------------------------" 5627 " Register Dump " 5628 "----------------------------\n"); 5629 5630 for (i = 0x400; i < 0x8000; i += 0x10) 5631 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 5632 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 5633 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 5634 5635 BNX_PRINTF(sc, 5636 "----------------------------" 5637 "----------------" 5638 "----------------------------\n"); 5639 } 5640 5641 void 5642 bnx_breakpoint(struct bnx_softc *sc) 5643 { 5644 /* Unreachable code to shut the compiler up about unused functions. */ 5645 if (0) { 5646 bnx_dump_txbd(sc, 0, NULL); 5647 bnx_dump_rxbd(sc, 0, NULL); 5648 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 5649 bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 5650 bnx_dump_l2fhdr(sc, 0, NULL); 5651 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 5652 bnx_dump_rx_chain(sc, 0, USABLE_RX_BD); 5653 bnx_dump_status_block(sc); 5654 bnx_dump_stats_block(sc); 5655 bnx_dump_driver_state(sc); 5656 bnx_dump_hw_state(sc); 5657 } 5658 5659 bnx_dump_driver_state(sc); 5660 /* Print the important status block fields. */ 5661 bnx_dump_status_block(sc); 5662 5663 #if 0 5664 /* Call the debugger. */ 5665 breakpoint(); 5666 #endif 5667 5668 return; 5669 } 5670 #endif 5671
Indexes created Wed Sep 24 05:09:52 GMT 2025