if_bnx.c revision 1.27
1 /* $NetBSD: if_bnx.c,v 1.27 2009/05/05 10:21:22 cegger Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.43 2007/01/30 03:21:10 krw Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.27 2009/05/05 10:21:22 cegger Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5708C B1, B2 44 * 45 * The following controllers are not supported by this driver: 46 * (These are not "Production" versions of the controller.) 47 * 48 * BCM5706C A0, A1 49 * BCM5706S A0, A1, A2, A3 50 * BCM5708C A0, B0 51 * BCM5708S A0, B0, B1 52 */ 53 54 #include <sys/callout.h> 55 56 #include <dev/pci/if_bnxreg.h> 57 #include <dev/microcode/bnx/bnxfw.h> 58 59 /****************************************************************************/ 60 /* BNX Driver Version */ 61 /****************************************************************************/ 62 const char bnx_driver_version[] = "v0.9.6"; 63 64 /****************************************************************************/ 65 /* BNX Debug Options */ 66 /****************************************************************************/ 67 #ifdef BNX_DEBUG 68 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 69 70 /* 0 = Never */ 71 /* 1 = 1 in 2,147,483,648 */ 72 /* 256 = 1 in 8,388,608 */ 73 /* 2048 = 1 in 1,048,576 */ 74 /* 65536 = 1 in 32,768 */ 75 /* 1048576 = 1 in 2,048 */ 76 /* 268435456 = 1 in 8 */ 77 /* 536870912 = 1 in 4 */ 78 /* 1073741824 = 1 in 2 */ 79 80 /* Controls how often the l2_fhdr frame error check will fail. */ 81 int bnx_debug_l2fhdr_status_check = 0; 82 83 /* Controls how often the unexpected attention check will fail. */ 84 int bnx_debug_unexpected_attention = 0; 85 86 /* Controls how often to simulate an mbuf allocation failure. */ 87 int bnx_debug_mbuf_allocation_failure = 0; 88 89 /* Controls how often to simulate a DMA mapping failure. */ 90 int bnx_debug_dma_map_addr_failure = 0; 91 92 /* Controls how often to simulate a bootcode failure. */ 93 int bnx_debug_bootcode_running_failure = 0; 94 #endif 95 96 /****************************************************************************/ 97 /* PCI Device ID Table */ 98 /* */ 99 /* Used by bnx_probe() to identify the devices supported by this driver. */ 100 /****************************************************************************/ 101 static const struct bnx_product { 102 pci_vendor_id_t bp_vendor; 103 pci_product_id_t bp_product; 104 pci_vendor_id_t bp_subvendor; 105 pci_product_id_t bp_subproduct; 106 const char *bp_name; 107 } bnx_devices[] = { 108 #ifdef PCI_SUBPRODUCT_HP_NC370T 109 { 110 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 111 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 112 "HP NC370T Multifunction Gigabit Server Adapter" 113 }, 114 #endif 115 #ifdef PCI_SUBPRODUCT_HP_NC370i 116 { 117 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 118 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 119 "HP NC370i Multifunction Gigabit Server Adapter" 120 }, 121 #endif 122 { 123 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 124 0, 0, 125 "Broadcom NetXtreme II BCM5706 1000Base-T" 126 }, 127 #ifdef PCI_SUBPRODUCT_HP_NC370F 128 { 129 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 130 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 131 "HP NC370F Multifunction Gigabit Server Adapter" 132 }, 133 #endif 134 { 135 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 136 0, 0, 137 "Broadcom NetXtreme II BCM5706 1000Base-SX" 138 }, 139 { 140 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 141 0, 0, 142 "Broadcom NetXtreme II BCM5708 1000Base-T" 143 }, 144 { 145 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 146 0, 0, 147 "Broadcom NetXtreme II BCM5708 1000Base-SX" 148 }, 149 { 150 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 151 0, 0, 152 "Broadcom NetXtreme II BCM5709 1000Base-SX" 153 }, 154 }; 155 156 /****************************************************************************/ 157 /* Supported Flash NVRAM device data. */ 158 /****************************************************************************/ 159 static struct flash_spec flash_table[] = 160 { 161 /* Slow EEPROM */ 162 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 163 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 164 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 165 "EEPROM - slow"}, 166 /* Expansion entry 0001 */ 167 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 168 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 169 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 170 "Entry 0001"}, 171 /* Saifun SA25F010 (non-buffered flash) */ 172 /* strap, cfg1, & write1 need updates */ 173 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 174 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 175 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 176 "Non-buffered flash (128kB)"}, 177 /* Saifun SA25F020 (non-buffered flash) */ 178 /* strap, cfg1, & write1 need updates */ 179 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 182 "Non-buffered flash (256kB)"}, 183 /* Expansion entry 0100 */ 184 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 185 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 186 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 187 "Entry 0100"}, 188 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 189 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 190 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 191 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 192 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 193 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 194 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 195 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 196 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 197 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 198 /* Saifun SA25F005 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 201 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 203 "Non-buffered flash (64kB)"}, 204 /* Fast EEPROM */ 205 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 206 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 207 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 208 "EEPROM - fast"}, 209 /* Expansion entry 1001 */ 210 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 211 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 1001"}, 214 /* Expansion entry 1010 */ 215 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 216 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 217 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 218 "Entry 1010"}, 219 /* ATMEL AT45DB011B (buffered flash) */ 220 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 221 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 222 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 223 "Buffered flash (128kB)"}, 224 /* Expansion entry 1100 */ 225 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 226 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 228 "Entry 1100"}, 229 /* Expansion entry 1101 */ 230 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 231 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 232 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 233 "Entry 1101"}, 234 /* Ateml Expansion entry 1110 */ 235 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 236 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 237 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 238 "Entry 1110 (Atmel)"}, 239 /* ATMEL AT45DB021B (buffered flash) */ 240 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 241 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 242 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 243 "Buffered flash (256kB)"}, 244 }; 245 246 /****************************************************************************/ 247 /* OpenBSD device entry points. */ 248 /****************************************************************************/ 249 static int bnx_probe(device_t, cfdata_t, void *); 250 void bnx_attach(device_t, device_t, void *); 251 int bnx_detach(device_t, int); 252 253 /****************************************************************************/ 254 /* BNX Debug Data Structure Dump Routines */ 255 /****************************************************************************/ 256 #ifdef BNX_DEBUG 257 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 258 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 259 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 260 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 261 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 262 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 263 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 264 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 265 void bnx_dump_status_block(struct bnx_softc *); 266 void bnx_dump_stats_block(struct bnx_softc *); 267 void bnx_dump_driver_state(struct bnx_softc *); 268 void bnx_dump_hw_state(struct bnx_softc *); 269 void bnx_breakpoint(struct bnx_softc *); 270 #endif 271 272 /****************************************************************************/ 273 /* BNX Register/Memory Access Routines */ 274 /****************************************************************************/ 275 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 276 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 277 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 278 int bnx_miibus_read_reg(device_t, int, int); 279 void bnx_miibus_write_reg(device_t, int, int, int); 280 void bnx_miibus_statchg(device_t); 281 282 /****************************************************************************/ 283 /* BNX NVRAM Access Routines */ 284 /****************************************************************************/ 285 int bnx_acquire_nvram_lock(struct bnx_softc *); 286 int bnx_release_nvram_lock(struct bnx_softc *); 287 void bnx_enable_nvram_access(struct bnx_softc *); 288 void bnx_disable_nvram_access(struct bnx_softc *); 289 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 290 u_int32_t); 291 int bnx_init_nvram(struct bnx_softc *); 292 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 293 int bnx_nvram_test(struct bnx_softc *); 294 #ifdef BNX_NVRAM_WRITE_SUPPORT 295 int bnx_enable_nvram_write(struct bnx_softc *); 296 void bnx_disable_nvram_write(struct bnx_softc *); 297 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 298 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 299 u_int32_t); 300 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 301 #endif 302 303 /****************************************************************************/ 304 /* */ 305 /****************************************************************************/ 306 int bnx_dma_alloc(struct bnx_softc *); 307 void bnx_dma_free(struct bnx_softc *); 308 void bnx_release_resources(struct bnx_softc *); 309 310 /****************************************************************************/ 311 /* BNX Firmware Synchronization and Load */ 312 /****************************************************************************/ 313 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 314 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 315 u_int32_t); 316 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 317 struct fw_info *); 318 void bnx_init_cpus(struct bnx_softc *); 319 320 void bnx_stop(struct ifnet *, int); 321 int bnx_reset(struct bnx_softc *, u_int32_t); 322 int bnx_chipinit(struct bnx_softc *); 323 int bnx_blockinit(struct bnx_softc *); 324 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 325 u_int16_t *, u_int32_t *); 326 int bnx_get_buf(struct bnx_softc *, u_int16_t *, u_int16_t *, u_int32_t *); 327 328 int bnx_init_tx_chain(struct bnx_softc *); 329 int bnx_init_rx_chain(struct bnx_softc *); 330 void bnx_free_rx_chain(struct bnx_softc *); 331 void bnx_free_tx_chain(struct bnx_softc *); 332 333 int bnx_tx_encap(struct bnx_softc *, struct mbuf **); 334 void bnx_start(struct ifnet *); 335 int bnx_ioctl(struct ifnet *, u_long, void *); 336 void bnx_watchdog(struct ifnet *); 337 int bnx_init(struct ifnet *); 338 339 void bnx_init_context(struct bnx_softc *); 340 void bnx_get_mac_addr(struct bnx_softc *); 341 void bnx_set_mac_addr(struct bnx_softc *); 342 void bnx_phy_intr(struct bnx_softc *); 343 void bnx_rx_intr(struct bnx_softc *); 344 void bnx_tx_intr(struct bnx_softc *); 345 void bnx_disable_intr(struct bnx_softc *); 346 void bnx_enable_intr(struct bnx_softc *); 347 348 int bnx_intr(void *); 349 void bnx_set_rx_mode(struct bnx_softc *); 350 void bnx_stats_update(struct bnx_softc *); 351 void bnx_tick(void *); 352 353 /****************************************************************************/ 354 /* OpenBSD device dispatch table. */ 355 /****************************************************************************/ 356 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 357 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 358 359 /****************************************************************************/ 360 /* Device probe function. */ 361 /* */ 362 /* Compares the device to the driver's list of supported devices and */ 363 /* reports back to the OS whether this is the right driver for the device. */ 364 /* */ 365 /* Returns: */ 366 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 367 /****************************************************************************/ 368 static const struct bnx_product * 369 bnx_lookup(const struct pci_attach_args *pa) 370 { 371 int i; 372 pcireg_t subid; 373 374 for (i = 0; i < __arraycount(bnx_devices); i++) { 375 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 376 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 377 continue; 378 if (!bnx_devices[i].bp_subvendor) 379 return &bnx_devices[i]; 380 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 381 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 382 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 383 return &bnx_devices[i]; 384 } 385 386 return NULL; 387 } 388 static int 389 bnx_probe(device_t parent, cfdata_t match, void *aux) 390 { 391 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 392 393 if (bnx_lookup(pa) != NULL) 394 return (1); 395 396 return (0); 397 } 398 399 /****************************************************************************/ 400 /* Device attach function. */ 401 /* */ 402 /* Allocates device resources, performs secondary chip identification, */ 403 /* resets and initializes the hardware, and initializes driver instance */ 404 /* variables. */ 405 /* */ 406 /* Returns: */ 407 /* 0 on success, positive value on failure. */ 408 /****************************************************************************/ 409 void 410 bnx_attach(device_t parent, device_t self, void *aux) 411 { 412 const struct bnx_product *bp; 413 struct bnx_softc *sc = device_private(self); 414 struct pci_attach_args *pa = aux; 415 pci_chipset_tag_t pc = pa->pa_pc; 416 pci_intr_handle_t ih; 417 const char *intrstr = NULL; 418 u_int32_t command; 419 struct ifnet *ifp; 420 u_int32_t val; 421 int mii_flags = MIIF_FORCEANEG; 422 pcireg_t memtype; 423 424 bp = bnx_lookup(pa); 425 if (bp == NULL) 426 panic("unknown device"); 427 428 sc->bnx_dev = self; 429 430 aprint_naive("\n"); 431 aprint_normal(": %s\n", bp->bp_name); 432 433 sc->bnx_pa = *pa; 434 435 /* 436 * Map control/status registers. 437 */ 438 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 439 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 440 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 441 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 442 443 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 444 aprint_error_dev(sc->bnx_dev, 445 "failed to enable memory mapping!\n"); 446 return; 447 } 448 449 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 450 switch (memtype) { 451 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 452 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 453 if (pci_mapreg_map(pa, BNX_PCI_BAR0, 454 memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, 455 NULL, &sc->bnx_size) == 0) 456 break; 457 default: 458 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 459 return; 460 } 461 462 if (pci_intr_map(pa, &ih)) { 463 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 464 goto bnx_attach_fail; 465 } 466 467 intrstr = pci_intr_string(pc, ih); 468 469 /* 470 * Configure byte swap and enable indirect register access. 471 * Rely on CPU to do target byte swapping on big endian systems. 472 * Access to registers outside of PCI configurtion space are not 473 * valid until this is done. 474 */ 475 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 476 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 477 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 478 479 /* Save ASIC revsion info. */ 480 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 481 482 /* Weed out any non-production controller revisions. */ 483 switch(BNX_CHIP_ID(sc)) { 484 case BNX_CHIP_ID_5706_A0: 485 case BNX_CHIP_ID_5706_A1: 486 case BNX_CHIP_ID_5708_A0: 487 case BNX_CHIP_ID_5708_B0: 488 aprint_error_dev(sc->bnx_dev, 489 "unsupported controller revision (%c%d)!\n", 490 ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A', 491 PCI_REVISION(pa->pa_class) & 0x0f); 492 goto bnx_attach_fail; 493 } 494 495 /* 496 * Find the base address for shared memory access. 497 * Newer versions of bootcode use a signature and offset 498 * while older versions use a fixed address. 499 */ 500 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 501 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 502 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0); 503 else 504 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 505 506 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 507 508 /* Set initial device and PHY flags */ 509 sc->bnx_flags = 0; 510 sc->bnx_phy_flags = 0; 511 512 /* Get PCI bus information (speed and type). */ 513 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 514 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 515 u_int32_t clkreg; 516 517 sc->bnx_flags |= BNX_PCIX_FLAG; 518 519 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 520 521 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 522 switch (clkreg) { 523 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 524 sc->bus_speed_mhz = 133; 525 break; 526 527 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 528 sc->bus_speed_mhz = 100; 529 break; 530 531 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 532 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 533 sc->bus_speed_mhz = 66; 534 break; 535 536 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 537 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 538 sc->bus_speed_mhz = 50; 539 break; 540 541 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 542 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 543 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 544 sc->bus_speed_mhz = 33; 545 break; 546 } 547 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 548 sc->bus_speed_mhz = 66; 549 else 550 sc->bus_speed_mhz = 33; 551 552 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 553 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 554 555 /* Reset the controller. */ 556 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 557 goto bnx_attach_fail; 558 559 /* Initialize the controller. */ 560 if (bnx_chipinit(sc)) { 561 aprint_error_dev(sc->bnx_dev, 562 "Controller initialization failed!\n"); 563 goto bnx_attach_fail; 564 } 565 566 /* Perform NVRAM test. */ 567 if (bnx_nvram_test(sc)) { 568 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 569 goto bnx_attach_fail; 570 } 571 572 /* Fetch the permanent Ethernet MAC address. */ 573 bnx_get_mac_addr(sc); 574 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 575 ether_sprintf(sc->eaddr)); 576 577 /* 578 * Trip points control how many BDs 579 * should be ready before generating an 580 * interrupt while ticks control how long 581 * a BD can sit in the chain before 582 * generating an interrupt. Set the default 583 * values for the RX and TX rings. 584 */ 585 586 #ifdef BNX_DEBUG 587 /* Force more frequent interrupts. */ 588 sc->bnx_tx_quick_cons_trip_int = 1; 589 sc->bnx_tx_quick_cons_trip = 1; 590 sc->bnx_tx_ticks_int = 0; 591 sc->bnx_tx_ticks = 0; 592 593 sc->bnx_rx_quick_cons_trip_int = 1; 594 sc->bnx_rx_quick_cons_trip = 1; 595 sc->bnx_rx_ticks_int = 0; 596 sc->bnx_rx_ticks = 0; 597 #else 598 sc->bnx_tx_quick_cons_trip_int = 20; 599 sc->bnx_tx_quick_cons_trip = 20; 600 sc->bnx_tx_ticks_int = 80; 601 sc->bnx_tx_ticks = 80; 602 603 sc->bnx_rx_quick_cons_trip_int = 6; 604 sc->bnx_rx_quick_cons_trip = 6; 605 sc->bnx_rx_ticks_int = 18; 606 sc->bnx_rx_ticks = 18; 607 #endif 608 609 /* Update statistics once every second. */ 610 sc->bnx_stats_ticks = 1000000 & 0xffff00; 611 612 /* 613 * The copper based NetXtreme II controllers 614 * that support 2.5Gb operation (currently 615 * 5708S) use a PHY at address 2, otherwise 616 * the PHY is present at address 1. 617 */ 618 sc->bnx_phy_addr = 1; 619 620 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 621 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 622 sc->bnx_flags |= BNX_NO_WOL_FLAG; 623 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 624 sc->bnx_phy_addr = 2; 625 val = REG_RD_IND(sc, sc->bnx_shmem_base + 626 BNX_SHARED_HW_CFG_CONFIG); 627 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) 628 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 629 } 630 } 631 632 /* Allocate DMA memory resources. */ 633 sc->bnx_dmatag = pa->pa_dmat; 634 if (bnx_dma_alloc(sc)) { 635 aprint_error_dev(sc->bnx_dev, 636 "DMA resource allocation failed!\n"); 637 goto bnx_attach_fail; 638 } 639 640 /* Initialize the ifnet interface. */ 641 ifp = &sc->bnx_ec.ec_if; 642 ifp->if_softc = sc; 643 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 644 ifp->if_ioctl = bnx_ioctl; 645 ifp->if_stop = bnx_stop; 646 ifp->if_start = bnx_start; 647 ifp->if_init = bnx_init; 648 ifp->if_timer = 0; 649 ifp->if_watchdog = bnx_watchdog; 650 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 651 IFQ_SET_READY(&ifp->if_snd); 652 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 653 654 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 655 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 656 657 ifp->if_capabilities |= 658 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 659 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 660 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 661 662 /* Hookup IRQ last. */ 663 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 664 if (sc->bnx_intrhand == NULL) { 665 aprint_error_dev(self, "couldn't establish interrupt"); 666 if (intrstr != NULL) 667 aprint_error(" at %s", intrstr); 668 aprint_error("\n"); 669 goto bnx_attach_fail; 670 } 671 672 sc->bnx_mii.mii_ifp = ifp; 673 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 674 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 675 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 676 677 sc->bnx_ec.ec_mii = &sc->bnx_mii; 678 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 679 ether_mediastatus); 680 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 681 mii_flags |= MIIF_HAVEFIBER; 682 mii_attach(self, &sc->bnx_mii, 0xffffffff, 683 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 684 685 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 686 aprint_error_dev(self, "no PHY found!\n"); 687 ifmedia_add(&sc->bnx_mii.mii_media, 688 IFM_ETHER|IFM_MANUAL, 0, NULL); 689 ifmedia_set(&sc->bnx_mii.mii_media, 690 IFM_ETHER|IFM_MANUAL); 691 } else { 692 ifmedia_set(&sc->bnx_mii.mii_media, 693 IFM_ETHER|IFM_AUTO); 694 } 695 696 /* Attach to the Ethernet interface list. */ 697 if_attach(ifp); 698 ether_ifattach(ifp,sc->eaddr); 699 700 callout_init(&sc->bnx_timeout, 0); 701 702 if (!pmf_device_register(self, NULL, NULL)) 703 aprint_error_dev(self, "couldn't establish power handler\n"); 704 else 705 pmf_class_network_register(self, ifp); 706 707 /* Print some important debugging info. */ 708 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 709 710 goto bnx_attach_exit; 711 712 bnx_attach_fail: 713 bnx_release_resources(sc); 714 715 bnx_attach_exit: 716 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 717 } 718 719 /****************************************************************************/ 720 /* Device detach function. */ 721 /* */ 722 /* Stops the controller, resets the controller, and releases resources. */ 723 /* */ 724 /* Returns: */ 725 /* 0 on success, positive value on failure. */ 726 /****************************************************************************/ 727 int 728 bnx_detach(device_t dev, int flags) 729 { 730 int s; 731 struct bnx_softc *sc; 732 struct ifnet *ifp; 733 734 sc = device_private(dev); 735 ifp = &sc->bnx_ec.ec_if; 736 737 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 738 739 /* Stop and reset the controller. */ 740 s = splnet(); 741 if (ifp->if_flags & IFF_RUNNING) 742 bnx_stop(ifp, 1); 743 splx(s); 744 745 pmf_device_deregister(dev); 746 callout_destroy(&sc->bnx_timeout); 747 ether_ifdetach(ifp); 748 if_detach(ifp); 749 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 750 751 /* Release all remaining resources. */ 752 bnx_release_resources(sc); 753 754 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 755 756 return(0); 757 } 758 759 /****************************************************************************/ 760 /* Indirect register read. */ 761 /* */ 762 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 763 /* configuration space. Using this mechanism avoids issues with posted */ 764 /* reads but is much slower than memory-mapped I/O. */ 765 /* */ 766 /* Returns: */ 767 /* The value of the register. */ 768 /****************************************************************************/ 769 u_int32_t 770 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 771 { 772 struct pci_attach_args *pa = &(sc->bnx_pa); 773 774 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 775 offset); 776 #ifdef BNX_DEBUG 777 { 778 u_int32_t val; 779 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 780 BNX_PCICFG_REG_WINDOW); 781 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 782 "val = 0x%08X\n", __func__, offset, val); 783 return (val); 784 } 785 #else 786 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 787 #endif 788 } 789 790 /****************************************************************************/ 791 /* Indirect register write. */ 792 /* */ 793 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 794 /* configuration space. Using this mechanism avoids issues with posted */ 795 /* writes but is muchh slower than memory-mapped I/O. */ 796 /* */ 797 /* Returns: */ 798 /* Nothing. */ 799 /****************************************************************************/ 800 void 801 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 802 { 803 struct pci_attach_args *pa = &(sc->bnx_pa); 804 805 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 806 __func__, offset, val); 807 808 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 809 offset); 810 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 811 } 812 813 /****************************************************************************/ 814 /* Context memory write. */ 815 /* */ 816 /* The NetXtreme II controller uses context memory to track connection */ 817 /* information for L2 and higher network protocols. */ 818 /* */ 819 /* Returns: */ 820 /* Nothing. */ 821 /****************************************************************************/ 822 void 823 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, 824 u_int32_t val) 825 { 826 827 DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 828 "val = 0x%08X\n", __func__, cid_addr, offset, val); 829 830 offset += cid_addr; 831 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 832 REG_WR(sc, BNX_CTX_DATA, val); 833 } 834 835 /****************************************************************************/ 836 /* PHY register read. */ 837 /* */ 838 /* Implements register reads on the MII bus. */ 839 /* */ 840 /* Returns: */ 841 /* The value of the register. */ 842 /****************************************************************************/ 843 int 844 bnx_miibus_read_reg(device_t dev, int phy, int reg) 845 { 846 struct bnx_softc *sc = device_private(dev); 847 u_int32_t val; 848 int i; 849 850 /* Make sure we are accessing the correct PHY address. */ 851 if (phy != sc->bnx_phy_addr) { 852 DBPRINT(sc, BNX_VERBOSE, 853 "Invalid PHY address %d for PHY read!\n", phy); 854 return(0); 855 } 856 857 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 858 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 859 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 860 861 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 862 REG_RD(sc, BNX_EMAC_MDIO_MODE); 863 864 DELAY(40); 865 } 866 867 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 868 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 869 BNX_EMAC_MDIO_COMM_START_BUSY; 870 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 871 872 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 873 DELAY(10); 874 875 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 876 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 877 DELAY(5); 878 879 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 880 val &= BNX_EMAC_MDIO_COMM_DATA; 881 882 break; 883 } 884 } 885 886 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 887 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 888 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 889 val = 0x0; 890 } else 891 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 892 893 DBPRINT(sc, BNX_EXCESSIVE, 894 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 895 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 896 897 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 898 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 899 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 900 901 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 902 REG_RD(sc, BNX_EMAC_MDIO_MODE); 903 904 DELAY(40); 905 } 906 907 return (val & 0xffff); 908 } 909 910 /****************************************************************************/ 911 /* PHY register write. */ 912 /* */ 913 /* Implements register writes on the MII bus. */ 914 /* */ 915 /* Returns: */ 916 /* The value of the register. */ 917 /****************************************************************************/ 918 void 919 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 920 { 921 struct bnx_softc *sc = device_private(dev); 922 u_int32_t val1; 923 int i; 924 925 /* Make sure we are accessing the correct PHY address. */ 926 if (phy != sc->bnx_phy_addr) { 927 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 928 phy); 929 return; 930 } 931 932 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 933 "val = 0x%04X\n", __func__, 934 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 935 936 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 937 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 938 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 939 940 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 941 REG_RD(sc, BNX_EMAC_MDIO_MODE); 942 943 DELAY(40); 944 } 945 946 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 947 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 948 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 949 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 950 951 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 952 DELAY(10); 953 954 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 955 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 956 DELAY(5); 957 break; 958 } 959 } 960 961 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 962 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 963 __LINE__); 964 } 965 966 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 967 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 968 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 969 970 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 971 REG_RD(sc, BNX_EMAC_MDIO_MODE); 972 973 DELAY(40); 974 } 975 } 976 977 /****************************************************************************/ 978 /* MII bus status change. */ 979 /* */ 980 /* Called by the MII bus driver when the PHY establishes link to set the */ 981 /* MAC interface registers. */ 982 /* */ 983 /* Returns: */ 984 /* Nothing. */ 985 /****************************************************************************/ 986 void 987 bnx_miibus_statchg(device_t dev) 988 { 989 struct bnx_softc *sc = device_private(dev); 990 struct mii_data *mii = &sc->bnx_mii; 991 int val; 992 993 val = REG_RD(sc, BNX_EMAC_MODE); 994 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 995 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 996 BNX_EMAC_MODE_25G); 997 998 /* Set MII or GMII interface based on the speed 999 * negotiated by the PHY. 1000 */ 1001 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1002 case IFM_10_T: 1003 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1004 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1005 val |= BNX_EMAC_MODE_PORT_MII_10; 1006 break; 1007 } 1008 /* FALLTHROUGH */ 1009 case IFM_100_TX: 1010 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1011 val |= BNX_EMAC_MODE_PORT_MII; 1012 break; 1013 case IFM_2500_SX: 1014 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1015 val |= BNX_EMAC_MODE_25G; 1016 /* FALLTHROUGH */ 1017 case IFM_1000_T: 1018 case IFM_1000_SX: 1019 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1020 val |= BNX_EMAC_MODE_PORT_GMII; 1021 break; 1022 default: 1023 val |= BNX_EMAC_MODE_PORT_GMII; 1024 break; 1025 } 1026 1027 /* Set half or full duplex based on the duplicity 1028 * negotiated by the PHY. 1029 */ 1030 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1031 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1032 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1033 } else { 1034 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1035 } 1036 1037 REG_WR(sc, BNX_EMAC_MODE, val); 1038 } 1039 1040 /****************************************************************************/ 1041 /* Acquire NVRAM lock. */ 1042 /* */ 1043 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1044 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1045 /* for use by the driver. */ 1046 /* */ 1047 /* Returns: */ 1048 /* 0 on success, positive value on failure. */ 1049 /****************************************************************************/ 1050 int 1051 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1052 { 1053 u_int32_t val; 1054 int j; 1055 1056 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1057 1058 /* Request access to the flash interface. */ 1059 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1060 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1061 val = REG_RD(sc, BNX_NVM_SW_ARB); 1062 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1063 break; 1064 1065 DELAY(5); 1066 } 1067 1068 if (j >= NVRAM_TIMEOUT_COUNT) { 1069 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1070 return (EBUSY); 1071 } 1072 1073 return (0); 1074 } 1075 1076 /****************************************************************************/ 1077 /* Release NVRAM lock. */ 1078 /* */ 1079 /* When the caller is finished accessing NVRAM the lock must be released. */ 1080 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1081 /* for use by the driver. */ 1082 /* */ 1083 /* Returns: */ 1084 /* 0 on success, positive value on failure. */ 1085 /****************************************************************************/ 1086 int 1087 bnx_release_nvram_lock(struct bnx_softc *sc) 1088 { 1089 int j; 1090 u_int32_t val; 1091 1092 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1093 1094 /* Relinquish nvram interface. */ 1095 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1096 1097 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1098 val = REG_RD(sc, BNX_NVM_SW_ARB); 1099 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1100 break; 1101 1102 DELAY(5); 1103 } 1104 1105 if (j >= NVRAM_TIMEOUT_COUNT) { 1106 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1107 return (EBUSY); 1108 } 1109 1110 return (0); 1111 } 1112 1113 #ifdef BNX_NVRAM_WRITE_SUPPORT 1114 /****************************************************************************/ 1115 /* Enable NVRAM write access. */ 1116 /* */ 1117 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1118 /* */ 1119 /* Returns: */ 1120 /* 0 on success, positive value on failure. */ 1121 /****************************************************************************/ 1122 int 1123 bnx_enable_nvram_write(struct bnx_softc *sc) 1124 { 1125 u_int32_t val; 1126 1127 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1128 1129 val = REG_RD(sc, BNX_MISC_CFG); 1130 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1131 1132 if (!sc->bnx_flash_info->buffered) { 1133 int j; 1134 1135 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1136 REG_WR(sc, BNX_NVM_COMMAND, 1137 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1138 1139 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1140 DELAY(5); 1141 1142 val = REG_RD(sc, BNX_NVM_COMMAND); 1143 if (val & BNX_NVM_COMMAND_DONE) 1144 break; 1145 } 1146 1147 if (j >= NVRAM_TIMEOUT_COUNT) { 1148 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1149 return (EBUSY); 1150 } 1151 } 1152 1153 return (0); 1154 } 1155 1156 /****************************************************************************/ 1157 /* Disable NVRAM write access. */ 1158 /* */ 1159 /* When the caller is finished writing to NVRAM write access must be */ 1160 /* disabled. */ 1161 /* */ 1162 /* Returns: */ 1163 /* Nothing. */ 1164 /****************************************************************************/ 1165 void 1166 bnx_disable_nvram_write(struct bnx_softc *sc) 1167 { 1168 u_int32_t val; 1169 1170 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1171 1172 val = REG_RD(sc, BNX_MISC_CFG); 1173 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1174 } 1175 #endif 1176 1177 /****************************************************************************/ 1178 /* Enable NVRAM access. */ 1179 /* */ 1180 /* Before accessing NVRAM for read or write operations the caller must */ 1181 /* enabled NVRAM access. */ 1182 /* */ 1183 /* Returns: */ 1184 /* Nothing. */ 1185 /****************************************************************************/ 1186 void 1187 bnx_enable_nvram_access(struct bnx_softc *sc) 1188 { 1189 u_int32_t val; 1190 1191 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1192 1193 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1194 /* Enable both bits, even on read. */ 1195 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1196 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1197 } 1198 1199 /****************************************************************************/ 1200 /* Disable NVRAM access. */ 1201 /* */ 1202 /* When the caller is finished accessing NVRAM access must be disabled. */ 1203 /* */ 1204 /* Returns: */ 1205 /* Nothing. */ 1206 /****************************************************************************/ 1207 void 1208 bnx_disable_nvram_access(struct bnx_softc *sc) 1209 { 1210 u_int32_t val; 1211 1212 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1213 1214 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1215 1216 /* Disable both bits, even after read. */ 1217 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1218 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1219 } 1220 1221 #ifdef BNX_NVRAM_WRITE_SUPPORT 1222 /****************************************************************************/ 1223 /* Erase NVRAM page before writing. */ 1224 /* */ 1225 /* Non-buffered flash parts require that a page be erased before it is */ 1226 /* written. */ 1227 /* */ 1228 /* Returns: */ 1229 /* 0 on success, positive value on failure. */ 1230 /****************************************************************************/ 1231 int 1232 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1233 { 1234 u_int32_t cmd; 1235 int j; 1236 1237 /* Buffered flash doesn't require an erase. */ 1238 if (sc->bnx_flash_info->buffered) 1239 return (0); 1240 1241 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1242 1243 /* Build an erase command. */ 1244 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1245 BNX_NVM_COMMAND_DOIT; 1246 1247 /* 1248 * Clear the DONE bit separately, set the NVRAM adress to erase, 1249 * and issue the erase command. 1250 */ 1251 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1252 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1253 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1254 1255 /* Wait for completion. */ 1256 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1257 u_int32_t val; 1258 1259 DELAY(5); 1260 1261 val = REG_RD(sc, BNX_NVM_COMMAND); 1262 if (val & BNX_NVM_COMMAND_DONE) 1263 break; 1264 } 1265 1266 if (j >= NVRAM_TIMEOUT_COUNT) { 1267 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1268 return (EBUSY); 1269 } 1270 1271 return (0); 1272 } 1273 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1274 1275 /****************************************************************************/ 1276 /* Read a dword (32 bits) from NVRAM. */ 1277 /* */ 1278 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1279 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1280 /* */ 1281 /* Returns: */ 1282 /* 0 on success and the 32 bit value read, positive value on failure. */ 1283 /****************************************************************************/ 1284 int 1285 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1286 u_int8_t *ret_val, u_int32_t cmd_flags) 1287 { 1288 u_int32_t cmd; 1289 int i, rc = 0; 1290 1291 /* Build the command word. */ 1292 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1293 1294 /* Calculate the offset for buffered flash. */ 1295 if (sc->bnx_flash_info->buffered) 1296 offset = ((offset / sc->bnx_flash_info->page_size) << 1297 sc->bnx_flash_info->page_bits) + 1298 (offset % sc->bnx_flash_info->page_size); 1299 1300 /* 1301 * Clear the DONE bit separately, set the address to read, 1302 * and issue the read. 1303 */ 1304 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1305 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1306 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1307 1308 /* Wait for completion. */ 1309 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1310 u_int32_t val; 1311 1312 DELAY(5); 1313 1314 val = REG_RD(sc, BNX_NVM_COMMAND); 1315 if (val & BNX_NVM_COMMAND_DONE) { 1316 val = REG_RD(sc, BNX_NVM_READ); 1317 1318 val = bnx_be32toh(val); 1319 memcpy(ret_val, &val, 4); 1320 break; 1321 } 1322 } 1323 1324 /* Check for errors. */ 1325 if (i >= NVRAM_TIMEOUT_COUNT) { 1326 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1327 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1328 rc = EBUSY; 1329 } 1330 1331 return(rc); 1332 } 1333 1334 #ifdef BNX_NVRAM_WRITE_SUPPORT 1335 /****************************************************************************/ 1336 /* Write a dword (32 bits) to NVRAM. */ 1337 /* */ 1338 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1339 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1340 /* enabled NVRAM write access. */ 1341 /* */ 1342 /* Returns: */ 1343 /* 0 on success, positive value on failure. */ 1344 /****************************************************************************/ 1345 int 1346 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1347 u_int32_t cmd_flags) 1348 { 1349 u_int32_t cmd, val32; 1350 int j; 1351 1352 /* Build the command word. */ 1353 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1354 1355 /* Calculate the offset for buffered flash. */ 1356 if (sc->bnx_flash_info->buffered) 1357 offset = ((offset / sc->bnx_flash_info->page_size) << 1358 sc->bnx_flash_info->page_bits) + 1359 (offset % sc->bnx_flash_info->page_size); 1360 1361 /* 1362 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1363 * set the NVRAM address to write, and issue the write command 1364 */ 1365 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1366 memcpy(&val32, val, 4); 1367 val32 = htobe32(val32); 1368 REG_WR(sc, BNX_NVM_WRITE, val32); 1369 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1370 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1371 1372 /* Wait for completion. */ 1373 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1374 DELAY(5); 1375 1376 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1377 break; 1378 } 1379 if (j >= NVRAM_TIMEOUT_COUNT) { 1380 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1381 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1382 return (EBUSY); 1383 } 1384 1385 return (0); 1386 } 1387 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1388 1389 /****************************************************************************/ 1390 /* Initialize NVRAM access. */ 1391 /* */ 1392 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1393 /* access that device. */ 1394 /* */ 1395 /* Returns: */ 1396 /* 0 on success, positive value on failure. */ 1397 /****************************************************************************/ 1398 int 1399 bnx_init_nvram(struct bnx_softc *sc) 1400 { 1401 u_int32_t val; 1402 int j, entry_count, rc; 1403 struct flash_spec *flash; 1404 1405 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1406 1407 /* Determine the selected interface. */ 1408 val = REG_RD(sc, BNX_NVM_CFG1); 1409 1410 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1411 1412 rc = 0; 1413 1414 /* 1415 * Flash reconfiguration is required to support additional 1416 * NVRAM devices not directly supported in hardware. 1417 * Check if the flash interface was reconfigured 1418 * by the bootcode. 1419 */ 1420 1421 if (val & 0x40000000) { 1422 /* Flash interface reconfigured by bootcode. */ 1423 1424 DBPRINT(sc,BNX_INFO_LOAD, 1425 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1426 1427 for (j = 0, flash = &flash_table[0]; j < entry_count; 1428 j++, flash++) { 1429 if ((val & FLASH_BACKUP_STRAP_MASK) == 1430 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1431 sc->bnx_flash_info = flash; 1432 break; 1433 } 1434 } 1435 } else { 1436 /* Flash interface not yet reconfigured. */ 1437 u_int32_t mask; 1438 1439 DBPRINT(sc,BNX_INFO_LOAD, 1440 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1441 1442 if (val & (1 << 23)) 1443 mask = FLASH_BACKUP_STRAP_MASK; 1444 else 1445 mask = FLASH_STRAP_MASK; 1446 1447 /* Look for the matching NVRAM device configuration data. */ 1448 for (j = 0, flash = &flash_table[0]; j < entry_count; 1449 j++, flash++) { 1450 /* Check if the dev matches any of the known devices. */ 1451 if ((val & mask) == (flash->strapping & mask)) { 1452 /* Found a device match. */ 1453 sc->bnx_flash_info = flash; 1454 1455 /* Request access to the flash interface. */ 1456 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1457 return (rc); 1458 1459 /* Reconfigure the flash interface. */ 1460 bnx_enable_nvram_access(sc); 1461 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1462 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1463 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1464 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1465 bnx_disable_nvram_access(sc); 1466 bnx_release_nvram_lock(sc); 1467 1468 break; 1469 } 1470 } 1471 } 1472 1473 /* Check if a matching device was found. */ 1474 if (j == entry_count) { 1475 sc->bnx_flash_info = NULL; 1476 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1477 __FILE__, __LINE__); 1478 rc = ENODEV; 1479 } 1480 1481 /* Write the flash config data to the shared memory interface. */ 1482 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1483 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1484 if (val) 1485 sc->bnx_flash_size = val; 1486 else 1487 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1488 1489 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1490 "0x%08X\n", sc->bnx_flash_info->total_size); 1491 1492 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1493 1494 return (rc); 1495 } 1496 1497 /****************************************************************************/ 1498 /* Read an arbitrary range of data from NVRAM. */ 1499 /* */ 1500 /* Prepares the NVRAM interface for access and reads the requested data */ 1501 /* into the supplied buffer. */ 1502 /* */ 1503 /* Returns: */ 1504 /* 0 on success and the data read, positive value on failure. */ 1505 /****************************************************************************/ 1506 int 1507 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1508 int buf_size) 1509 { 1510 int rc = 0; 1511 u_int32_t cmd_flags, offset32, len32, extra; 1512 1513 if (buf_size == 0) 1514 return (0); 1515 1516 /* Request access to the flash interface. */ 1517 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1518 return (rc); 1519 1520 /* Enable access to flash interface */ 1521 bnx_enable_nvram_access(sc); 1522 1523 len32 = buf_size; 1524 offset32 = offset; 1525 extra = 0; 1526 1527 cmd_flags = 0; 1528 1529 if (offset32 & 3) { 1530 u_int8_t buf[4]; 1531 u_int32_t pre_len; 1532 1533 offset32 &= ~3; 1534 pre_len = 4 - (offset & 3); 1535 1536 if (pre_len >= len32) { 1537 pre_len = len32; 1538 cmd_flags = 1539 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1540 } else 1541 cmd_flags = BNX_NVM_COMMAND_FIRST; 1542 1543 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1544 1545 if (rc) 1546 return (rc); 1547 1548 memcpy(ret_buf, buf + (offset & 3), pre_len); 1549 1550 offset32 += 4; 1551 ret_buf += pre_len; 1552 len32 -= pre_len; 1553 } 1554 1555 if (len32 & 3) { 1556 extra = 4 - (len32 & 3); 1557 len32 = (len32 + 4) & ~3; 1558 } 1559 1560 if (len32 == 4) { 1561 u_int8_t buf[4]; 1562 1563 if (cmd_flags) 1564 cmd_flags = BNX_NVM_COMMAND_LAST; 1565 else 1566 cmd_flags = 1567 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1568 1569 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1570 1571 memcpy(ret_buf, buf, 4 - extra); 1572 } else if (len32 > 0) { 1573 u_int8_t buf[4]; 1574 1575 /* Read the first word. */ 1576 if (cmd_flags) 1577 cmd_flags = 0; 1578 else 1579 cmd_flags = BNX_NVM_COMMAND_FIRST; 1580 1581 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1582 1583 /* Advance to the next dword. */ 1584 offset32 += 4; 1585 ret_buf += 4; 1586 len32 -= 4; 1587 1588 while (len32 > 4 && rc == 0) { 1589 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1590 1591 /* Advance to the next dword. */ 1592 offset32 += 4; 1593 ret_buf += 4; 1594 len32 -= 4; 1595 } 1596 1597 if (rc) 1598 return (rc); 1599 1600 cmd_flags = BNX_NVM_COMMAND_LAST; 1601 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1602 1603 memcpy(ret_buf, buf, 4 - extra); 1604 } 1605 1606 /* Disable access to flash interface and release the lock. */ 1607 bnx_disable_nvram_access(sc); 1608 bnx_release_nvram_lock(sc); 1609 1610 return (rc); 1611 } 1612 1613 #ifdef BNX_NVRAM_WRITE_SUPPORT 1614 /****************************************************************************/ 1615 /* Write an arbitrary range of data from NVRAM. */ 1616 /* */ 1617 /* Prepares the NVRAM interface for write access and writes the requested */ 1618 /* data from the supplied buffer. The caller is responsible for */ 1619 /* calculating any appropriate CRCs. */ 1620 /* */ 1621 /* Returns: */ 1622 /* 0 on success, positive value on failure. */ 1623 /****************************************************************************/ 1624 int 1625 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1626 int buf_size) 1627 { 1628 u_int32_t written, offset32, len32; 1629 u_int8_t *buf, start[4], end[4]; 1630 int rc = 0; 1631 int align_start, align_end; 1632 1633 buf = data_buf; 1634 offset32 = offset; 1635 len32 = buf_size; 1636 align_start = align_end = 0; 1637 1638 if ((align_start = (offset32 & 3))) { 1639 offset32 &= ~3; 1640 len32 += align_start; 1641 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1642 return (rc); 1643 } 1644 1645 if (len32 & 3) { 1646 if ((len32 > 4) || !align_start) { 1647 align_end = 4 - (len32 & 3); 1648 len32 += align_end; 1649 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1650 end, 4))) { 1651 return (rc); 1652 } 1653 } 1654 } 1655 1656 if (align_start || align_end) { 1657 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1658 if (buf == 0) 1659 return (ENOMEM); 1660 1661 if (align_start) 1662 memcpy(buf, start, 4); 1663 1664 if (align_end) 1665 memcpy(buf + len32 - 4, end, 4); 1666 1667 memcpy(buf + align_start, data_buf, buf_size); 1668 } 1669 1670 written = 0; 1671 while ((written < len32) && (rc == 0)) { 1672 u_int32_t page_start, page_end, data_start, data_end; 1673 u_int32_t addr, cmd_flags; 1674 int i; 1675 u_int8_t flash_buffer[264]; 1676 1677 /* Find the page_start addr */ 1678 page_start = offset32 + written; 1679 page_start -= (page_start % sc->bnx_flash_info->page_size); 1680 /* Find the page_end addr */ 1681 page_end = page_start + sc->bnx_flash_info->page_size; 1682 /* Find the data_start addr */ 1683 data_start = (written == 0) ? offset32 : page_start; 1684 /* Find the data_end addr */ 1685 data_end = (page_end > offset32 + len32) ? 1686 (offset32 + len32) : page_end; 1687 1688 /* Request access to the flash interface. */ 1689 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1690 goto nvram_write_end; 1691 1692 /* Enable access to flash interface */ 1693 bnx_enable_nvram_access(sc); 1694 1695 cmd_flags = BNX_NVM_COMMAND_FIRST; 1696 if (sc->bnx_flash_info->buffered == 0) { 1697 int j; 1698 1699 /* Read the whole page into the buffer 1700 * (non-buffer flash only) */ 1701 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1702 if (j == (sc->bnx_flash_info->page_size - 4)) 1703 cmd_flags |= BNX_NVM_COMMAND_LAST; 1704 1705 rc = bnx_nvram_read_dword(sc, 1706 page_start + j, 1707 &flash_buffer[j], 1708 cmd_flags); 1709 1710 if (rc) 1711 goto nvram_write_end; 1712 1713 cmd_flags = 0; 1714 } 1715 } 1716 1717 /* Enable writes to flash interface (unlock write-protect) */ 1718 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1719 goto nvram_write_end; 1720 1721 /* Erase the page */ 1722 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1723 goto nvram_write_end; 1724 1725 /* Re-enable the write again for the actual write */ 1726 bnx_enable_nvram_write(sc); 1727 1728 /* Loop to write back the buffer data from page_start to 1729 * data_start */ 1730 i = 0; 1731 if (sc->bnx_flash_info->buffered == 0) { 1732 for (addr = page_start; addr < data_start; 1733 addr += 4, i += 4) { 1734 1735 rc = bnx_nvram_write_dword(sc, addr, 1736 &flash_buffer[i], cmd_flags); 1737 1738 if (rc != 0) 1739 goto nvram_write_end; 1740 1741 cmd_flags = 0; 1742 } 1743 } 1744 1745 /* Loop to write the new data from data_start to data_end */ 1746 for (addr = data_start; addr < data_end; addr += 4, i++) { 1747 if ((addr == page_end - 4) || 1748 ((sc->bnx_flash_info->buffered) && 1749 (addr == data_end - 4))) { 1750 1751 cmd_flags |= BNX_NVM_COMMAND_LAST; 1752 } 1753 1754 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1755 1756 if (rc != 0) 1757 goto nvram_write_end; 1758 1759 cmd_flags = 0; 1760 buf += 4; 1761 } 1762 1763 /* Loop to write back the buffer data from data_end 1764 * to page_end */ 1765 if (sc->bnx_flash_info->buffered == 0) { 1766 for (addr = data_end; addr < page_end; 1767 addr += 4, i += 4) { 1768 1769 if (addr == page_end-4) 1770 cmd_flags = BNX_NVM_COMMAND_LAST; 1771 1772 rc = bnx_nvram_write_dword(sc, addr, 1773 &flash_buffer[i], cmd_flags); 1774 1775 if (rc != 0) 1776 goto nvram_write_end; 1777 1778 cmd_flags = 0; 1779 } 1780 } 1781 1782 /* Disable writes to flash interface (lock write-protect) */ 1783 bnx_disable_nvram_write(sc); 1784 1785 /* Disable access to flash interface */ 1786 bnx_disable_nvram_access(sc); 1787 bnx_release_nvram_lock(sc); 1788 1789 /* Increment written */ 1790 written += data_end - data_start; 1791 } 1792 1793 nvram_write_end: 1794 if (align_start || align_end) 1795 free(buf, M_DEVBUF); 1796 1797 return (rc); 1798 } 1799 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1800 1801 /****************************************************************************/ 1802 /* Verifies that NVRAM is accessible and contains valid data. */ 1803 /* */ 1804 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1805 /* correct. */ 1806 /* */ 1807 /* Returns: */ 1808 /* 0 on success, positive value on failure. */ 1809 /****************************************************************************/ 1810 int 1811 bnx_nvram_test(struct bnx_softc *sc) 1812 { 1813 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1814 u_int8_t *data = (u_int8_t *) buf; 1815 int rc = 0; 1816 u_int32_t magic, csum; 1817 1818 /* 1819 * Check that the device NVRAM is valid by reading 1820 * the magic value at offset 0. 1821 */ 1822 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1823 goto bnx_nvram_test_done; 1824 1825 magic = bnx_be32toh(buf[0]); 1826 if (magic != BNX_NVRAM_MAGIC) { 1827 rc = ENODEV; 1828 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1829 "Expected: 0x%08X, Found: 0x%08X\n", 1830 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1831 goto bnx_nvram_test_done; 1832 } 1833 1834 /* 1835 * Verify that the device NVRAM includes valid 1836 * configuration data. 1837 */ 1838 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1839 goto bnx_nvram_test_done; 1840 1841 csum = ether_crc32_le(data, 0x100); 1842 if (csum != BNX_CRC32_RESIDUAL) { 1843 rc = ENODEV; 1844 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1845 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1846 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1847 goto bnx_nvram_test_done; 1848 } 1849 1850 csum = ether_crc32_le(data + 0x100, 0x100); 1851 if (csum != BNX_CRC32_RESIDUAL) { 1852 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1853 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1854 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1855 rc = ENODEV; 1856 } 1857 1858 bnx_nvram_test_done: 1859 return (rc); 1860 } 1861 1862 /****************************************************************************/ 1863 /* Free any DMA memory owned by the driver. */ 1864 /* */ 1865 /* Scans through each data structre that requires DMA memory and frees */ 1866 /* the memory if allocated. */ 1867 /* */ 1868 /* Returns: */ 1869 /* Nothing. */ 1870 /****************************************************************************/ 1871 void 1872 bnx_dma_free(struct bnx_softc *sc) 1873 { 1874 int i; 1875 1876 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1877 1878 /* Destroy the status block. */ 1879 if (sc->status_block != NULL && sc->status_map != NULL) { 1880 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 1881 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 1882 BNX_STATUS_BLK_SZ); 1883 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 1884 sc->status_rseg); 1885 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 1886 sc->status_block = NULL; 1887 sc->status_map = NULL; 1888 } 1889 1890 /* Destroy the statistics block. */ 1891 if (sc->stats_block != NULL && sc->stats_map != NULL) { 1892 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 1893 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 1894 BNX_STATS_BLK_SZ); 1895 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 1896 sc->stats_rseg); 1897 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 1898 sc->stats_block = NULL; 1899 sc->stats_map = NULL; 1900 } 1901 1902 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 1903 for (i = 0; i < TX_PAGES; i++ ) { 1904 if (sc->tx_bd_chain[i] != NULL && 1905 sc->tx_bd_chain_map[i] != NULL) { 1906 bus_dmamap_unload(sc->bnx_dmatag, 1907 sc->tx_bd_chain_map[i]); 1908 bus_dmamem_unmap(sc->bnx_dmatag, 1909 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 1910 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 1911 sc->tx_bd_chain_rseg[i]); 1912 bus_dmamap_destroy(sc->bnx_dmatag, 1913 sc->tx_bd_chain_map[i]); 1914 sc->tx_bd_chain[i] = NULL; 1915 sc->tx_bd_chain_map[i] = NULL; 1916 } 1917 } 1918 1919 /* Unload and destroy the TX mbuf maps. */ 1920 for (i = 0; i < TOTAL_TX_BD; i++) { 1921 if (sc->tx_mbuf_map[i] != NULL) { 1922 bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1923 bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1924 } 1925 } 1926 1927 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 1928 for (i = 0; i < RX_PAGES; i++ ) { 1929 if (sc->rx_bd_chain[i] != NULL && 1930 sc->rx_bd_chain_map[i] != NULL) { 1931 bus_dmamap_unload(sc->bnx_dmatag, 1932 sc->rx_bd_chain_map[i]); 1933 bus_dmamem_unmap(sc->bnx_dmatag, 1934 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 1935 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 1936 sc->rx_bd_chain_rseg[i]); 1937 1938 bus_dmamap_destroy(sc->bnx_dmatag, 1939 sc->rx_bd_chain_map[i]); 1940 sc->rx_bd_chain[i] = NULL; 1941 sc->rx_bd_chain_map[i] = NULL; 1942 } 1943 } 1944 1945 /* Unload and destroy the RX mbuf maps. */ 1946 for (i = 0; i < TOTAL_RX_BD; i++) { 1947 if (sc->rx_mbuf_map[i] != NULL) { 1948 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1949 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1950 } 1951 } 1952 1953 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1954 } 1955 1956 /****************************************************************************/ 1957 /* Allocate any DMA memory needed by the driver. */ 1958 /* */ 1959 /* Allocates DMA memory needed for the various global structures needed by */ 1960 /* hardware. */ 1961 /* */ 1962 /* Returns: */ 1963 /* 0 for success, positive value for failure. */ 1964 /****************************************************************************/ 1965 int 1966 bnx_dma_alloc(struct bnx_softc *sc) 1967 { 1968 int i, rc = 0; 1969 1970 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1971 1972 /* 1973 * Allocate DMA memory for the status block, map the memory into DMA 1974 * space, and fetch the physical address of the block. 1975 */ 1976 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 1977 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 1978 aprint_error_dev(sc->bnx_dev, 1979 "Could not create status block DMA map!\n"); 1980 rc = ENOMEM; 1981 goto bnx_dma_alloc_exit; 1982 } 1983 1984 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1985 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 1986 &sc->status_rseg, BUS_DMA_NOWAIT)) { 1987 aprint_error_dev(sc->bnx_dev, 1988 "Could not allocate status block DMA memory!\n"); 1989 rc = ENOMEM; 1990 goto bnx_dma_alloc_exit; 1991 } 1992 1993 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 1994 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 1995 aprint_error_dev(sc->bnx_dev, 1996 "Could not map status block DMA memory!\n"); 1997 rc = ENOMEM; 1998 goto bnx_dma_alloc_exit; 1999 } 2000 2001 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2002 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2003 aprint_error_dev(sc->bnx_dev, 2004 "Could not load status block DMA memory!\n"); 2005 rc = ENOMEM; 2006 goto bnx_dma_alloc_exit; 2007 } 2008 2009 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2010 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2011 2012 /* DRC - Fix for 64 bit addresses. */ 2013 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2014 (u_int32_t) sc->status_block_paddr); 2015 2016 /* 2017 * Allocate DMA memory for the statistics block, map the memory into 2018 * DMA space, and fetch the physical address of the block. 2019 */ 2020 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2021 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2022 aprint_error_dev(sc->bnx_dev, 2023 "Could not create stats block DMA map!\n"); 2024 rc = ENOMEM; 2025 goto bnx_dma_alloc_exit; 2026 } 2027 2028 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2029 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2030 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2031 aprint_error_dev(sc->bnx_dev, 2032 "Could not allocate stats block DMA memory!\n"); 2033 rc = ENOMEM; 2034 goto bnx_dma_alloc_exit; 2035 } 2036 2037 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2038 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2039 aprint_error_dev(sc->bnx_dev, 2040 "Could not map stats block DMA memory!\n"); 2041 rc = ENOMEM; 2042 goto bnx_dma_alloc_exit; 2043 } 2044 2045 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2046 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2047 aprint_error_dev(sc->bnx_dev, 2048 "Could not load status block DMA memory!\n"); 2049 rc = ENOMEM; 2050 goto bnx_dma_alloc_exit; 2051 } 2052 2053 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2054 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2055 2056 /* DRC - Fix for 64 bit address. */ 2057 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2058 (u_int32_t) sc->stats_block_paddr); 2059 2060 /* 2061 * Allocate DMA memory for the TX buffer descriptor chain, 2062 * and fetch the physical address of the block. 2063 */ 2064 for (i = 0; i < TX_PAGES; i++) { 2065 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2066 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2067 &sc->tx_bd_chain_map[i])) { 2068 aprint_error_dev(sc->bnx_dev, 2069 "Could not create Tx desc %d DMA map!\n", i); 2070 rc = ENOMEM; 2071 goto bnx_dma_alloc_exit; 2072 } 2073 2074 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2075 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2076 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2077 aprint_error_dev(sc->bnx_dev, 2078 "Could not allocate TX desc %d DMA memory!\n", 2079 i); 2080 rc = ENOMEM; 2081 goto bnx_dma_alloc_exit; 2082 } 2083 2084 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2085 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2086 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2087 aprint_error_dev(sc->bnx_dev, 2088 "Could not map TX desc %d DMA memory!\n", i); 2089 rc = ENOMEM; 2090 goto bnx_dma_alloc_exit; 2091 } 2092 2093 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2094 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2095 BUS_DMA_NOWAIT)) { 2096 aprint_error_dev(sc->bnx_dev, 2097 "Could not load TX desc %d DMA memory!\n", i); 2098 rc = ENOMEM; 2099 goto bnx_dma_alloc_exit; 2100 } 2101 2102 sc->tx_bd_chain_paddr[i] = 2103 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2104 2105 /* DRC - Fix for 64 bit systems. */ 2106 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2107 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2108 } 2109 2110 /* 2111 * Create DMA maps for the TX buffer mbufs. 2112 */ 2113 for (i = 0; i < TOTAL_TX_BD; i++) { 2114 if (bus_dmamap_create(sc->bnx_dmatag, 2115 MCLBYTES * BNX_MAX_SEGMENTS, 2116 USABLE_TX_BD - BNX_TX_SLACK_SPACE, 2117 MCLBYTES, 0, BUS_DMA_NOWAIT, 2118 &sc->tx_mbuf_map[i])) { 2119 aprint_error_dev(sc->bnx_dev, 2120 "Could not create Tx mbuf %d DMA map!\n", i); 2121 rc = ENOMEM; 2122 goto bnx_dma_alloc_exit; 2123 } 2124 } 2125 2126 /* 2127 * Allocate DMA memory for the Rx buffer descriptor chain, 2128 * and fetch the physical address of the block. 2129 */ 2130 for (i = 0; i < RX_PAGES; i++) { 2131 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2132 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2133 &sc->rx_bd_chain_map[i])) { 2134 aprint_error_dev(sc->bnx_dev, 2135 "Could not create Rx desc %d DMA map!\n", i); 2136 rc = ENOMEM; 2137 goto bnx_dma_alloc_exit; 2138 } 2139 2140 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2141 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2142 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2143 aprint_error_dev(sc->bnx_dev, 2144 "Could not allocate Rx desc %d DMA memory!\n", i); 2145 rc = ENOMEM; 2146 goto bnx_dma_alloc_exit; 2147 } 2148 2149 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2150 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2151 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2152 aprint_error_dev(sc->bnx_dev, 2153 "Could not map Rx desc %d DMA memory!\n", i); 2154 rc = ENOMEM; 2155 goto bnx_dma_alloc_exit; 2156 } 2157 2158 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2159 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2160 BUS_DMA_NOWAIT)) { 2161 aprint_error_dev(sc->bnx_dev, 2162 "Could not load Rx desc %d DMA memory!\n", i); 2163 rc = ENOMEM; 2164 goto bnx_dma_alloc_exit; 2165 } 2166 2167 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2168 sc->rx_bd_chain_paddr[i] = 2169 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2170 2171 /* DRC - Fix for 64 bit systems. */ 2172 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2173 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2174 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2175 0, BNX_RX_CHAIN_PAGE_SZ, 2176 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2177 } 2178 2179 /* 2180 * Create DMA maps for the Rx buffer mbufs. 2181 */ 2182 for (i = 0; i < TOTAL_RX_BD; i++) { 2183 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU, 2184 BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT, 2185 &sc->rx_mbuf_map[i])) { 2186 aprint_error_dev(sc->bnx_dev, 2187 "Could not create Rx mbuf %d DMA map!\n", i); 2188 rc = ENOMEM; 2189 goto bnx_dma_alloc_exit; 2190 } 2191 } 2192 2193 bnx_dma_alloc_exit: 2194 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2195 2196 return(rc); 2197 } 2198 2199 /****************************************************************************/ 2200 /* Release all resources used by the driver. */ 2201 /* */ 2202 /* Releases all resources acquired by the driver including interrupts, */ 2203 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2204 /* */ 2205 /* Returns: */ 2206 /* Nothing. */ 2207 /****************************************************************************/ 2208 void 2209 bnx_release_resources(struct bnx_softc *sc) 2210 { 2211 struct pci_attach_args *pa = &(sc->bnx_pa); 2212 2213 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2214 2215 bnx_dma_free(sc); 2216 2217 if (sc->bnx_intrhand != NULL) 2218 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2219 2220 if (sc->bnx_size) 2221 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2222 2223 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2224 } 2225 2226 /****************************************************************************/ 2227 /* Firmware synchronization. */ 2228 /* */ 2229 /* Before performing certain events such as a chip reset, synchronize with */ 2230 /* the firmware first. */ 2231 /* */ 2232 /* Returns: */ 2233 /* 0 for success, positive value for failure. */ 2234 /****************************************************************************/ 2235 int 2236 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2237 { 2238 int i, rc = 0; 2239 u_int32_t val; 2240 2241 /* Don't waste any time if we've timed out before. */ 2242 if (sc->bnx_fw_timed_out) { 2243 rc = EBUSY; 2244 goto bnx_fw_sync_exit; 2245 } 2246 2247 /* Increment the message sequence number. */ 2248 sc->bnx_fw_wr_seq++; 2249 msg_data |= sc->bnx_fw_wr_seq; 2250 2251 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2252 msg_data); 2253 2254 /* Send the message to the bootcode driver mailbox. */ 2255 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2256 2257 /* Wait for the bootcode to acknowledge the message. */ 2258 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2259 /* Check for a response in the bootcode firmware mailbox. */ 2260 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2261 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2262 break; 2263 DELAY(1000); 2264 } 2265 2266 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2267 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2268 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2269 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2270 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2271 2272 msg_data &= ~BNX_DRV_MSG_CODE; 2273 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2274 2275 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2276 2277 sc->bnx_fw_timed_out = 1; 2278 rc = EBUSY; 2279 } 2280 2281 bnx_fw_sync_exit: 2282 return (rc); 2283 } 2284 2285 /****************************************************************************/ 2286 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2287 /* */ 2288 /* Returns: */ 2289 /* Nothing. */ 2290 /****************************************************************************/ 2291 void 2292 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2293 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2294 { 2295 int i; 2296 u_int32_t val; 2297 2298 for (i = 0; i < rv2p_code_len; i += 8) { 2299 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2300 rv2p_code++; 2301 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2302 rv2p_code++; 2303 2304 if (rv2p_proc == RV2P_PROC1) { 2305 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2306 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2307 } 2308 else { 2309 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2310 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2311 } 2312 } 2313 2314 /* Reset the processor, un-stall is done later. */ 2315 if (rv2p_proc == RV2P_PROC1) 2316 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2317 else 2318 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2319 } 2320 2321 /****************************************************************************/ 2322 /* Load RISC processor firmware. */ 2323 /* */ 2324 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2325 /* associated with a particular processor. */ 2326 /* */ 2327 /* Returns: */ 2328 /* Nothing. */ 2329 /****************************************************************************/ 2330 void 2331 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2332 struct fw_info *fw) 2333 { 2334 u_int32_t offset; 2335 u_int32_t val; 2336 2337 /* Halt the CPU. */ 2338 val = REG_RD_IND(sc, cpu_reg->mode); 2339 val |= cpu_reg->mode_value_halt; 2340 REG_WR_IND(sc, cpu_reg->mode, val); 2341 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2342 2343 /* Load the Text area. */ 2344 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2345 if (fw->text) { 2346 int j; 2347 2348 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2349 REG_WR_IND(sc, offset, fw->text[j]); 2350 } 2351 2352 /* Load the Data area. */ 2353 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2354 if (fw->data) { 2355 int j; 2356 2357 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2358 REG_WR_IND(sc, offset, fw->data[j]); 2359 } 2360 2361 /* Load the SBSS area. */ 2362 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2363 if (fw->sbss) { 2364 int j; 2365 2366 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2367 REG_WR_IND(sc, offset, fw->sbss[j]); 2368 } 2369 2370 /* Load the BSS area. */ 2371 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2372 if (fw->bss) { 2373 int j; 2374 2375 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2376 REG_WR_IND(sc, offset, fw->bss[j]); 2377 } 2378 2379 /* Load the Read-Only area. */ 2380 offset = cpu_reg->spad_base + 2381 (fw->rodata_addr - cpu_reg->mips_view_base); 2382 if (fw->rodata) { 2383 int j; 2384 2385 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2386 REG_WR_IND(sc, offset, fw->rodata[j]); 2387 } 2388 2389 /* Clear the pre-fetch instruction. */ 2390 REG_WR_IND(sc, cpu_reg->inst, 0); 2391 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2392 2393 /* Start the CPU. */ 2394 val = REG_RD_IND(sc, cpu_reg->mode); 2395 val &= ~cpu_reg->mode_value_halt; 2396 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2397 REG_WR_IND(sc, cpu_reg->mode, val); 2398 } 2399 2400 /****************************************************************************/ 2401 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2402 /* */ 2403 /* Loads the firmware for each CPU and starts the CPU. */ 2404 /* */ 2405 /* Returns: */ 2406 /* Nothing. */ 2407 /****************************************************************************/ 2408 void 2409 bnx_init_cpus(struct bnx_softc *sc) 2410 { 2411 struct cpu_reg cpu_reg; 2412 struct fw_info fw; 2413 2414 /* Initialize the RV2P processor. */ 2415 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2416 RV2P_PROC1); 2417 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2418 RV2P_PROC2); 2419 2420 /* Initialize the RX Processor. */ 2421 cpu_reg.mode = BNX_RXP_CPU_MODE; 2422 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2423 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2424 cpu_reg.state = BNX_RXP_CPU_STATE; 2425 cpu_reg.state_value_clear = 0xffffff; 2426 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2427 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2428 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2429 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2430 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2431 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2432 cpu_reg.mips_view_base = 0x8000000; 2433 2434 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2435 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2436 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2437 fw.start_addr = bnx_RXP_b06FwStartAddr; 2438 2439 fw.text_addr = bnx_RXP_b06FwTextAddr; 2440 fw.text_len = bnx_RXP_b06FwTextLen; 2441 fw.text_index = 0; 2442 fw.text = bnx_RXP_b06FwText; 2443 2444 fw.data_addr = bnx_RXP_b06FwDataAddr; 2445 fw.data_len = bnx_RXP_b06FwDataLen; 2446 fw.data_index = 0; 2447 fw.data = bnx_RXP_b06FwData; 2448 2449 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2450 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2451 fw.sbss_index = 0; 2452 fw.sbss = bnx_RXP_b06FwSbss; 2453 2454 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2455 fw.bss_len = bnx_RXP_b06FwBssLen; 2456 fw.bss_index = 0; 2457 fw.bss = bnx_RXP_b06FwBss; 2458 2459 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2460 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2461 fw.rodata_index = 0; 2462 fw.rodata = bnx_RXP_b06FwRodata; 2463 2464 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2465 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2466 2467 /* Initialize the TX Processor. */ 2468 cpu_reg.mode = BNX_TXP_CPU_MODE; 2469 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2470 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2471 cpu_reg.state = BNX_TXP_CPU_STATE; 2472 cpu_reg.state_value_clear = 0xffffff; 2473 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2474 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2475 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2476 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2477 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2478 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2479 cpu_reg.mips_view_base = 0x8000000; 2480 2481 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2482 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2483 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2484 fw.start_addr = bnx_TXP_b06FwStartAddr; 2485 2486 fw.text_addr = bnx_TXP_b06FwTextAddr; 2487 fw.text_len = bnx_TXP_b06FwTextLen; 2488 fw.text_index = 0; 2489 fw.text = bnx_TXP_b06FwText; 2490 2491 fw.data_addr = bnx_TXP_b06FwDataAddr; 2492 fw.data_len = bnx_TXP_b06FwDataLen; 2493 fw.data_index = 0; 2494 fw.data = bnx_TXP_b06FwData; 2495 2496 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2497 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2498 fw.sbss_index = 0; 2499 fw.sbss = bnx_TXP_b06FwSbss; 2500 2501 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2502 fw.bss_len = bnx_TXP_b06FwBssLen; 2503 fw.bss_index = 0; 2504 fw.bss = bnx_TXP_b06FwBss; 2505 2506 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 2507 fw.rodata_len = bnx_TXP_b06FwRodataLen; 2508 fw.rodata_index = 0; 2509 fw.rodata = bnx_TXP_b06FwRodata; 2510 2511 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2512 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2513 2514 /* Initialize the TX Patch-up Processor. */ 2515 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2516 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2517 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2518 cpu_reg.state = BNX_TPAT_CPU_STATE; 2519 cpu_reg.state_value_clear = 0xffffff; 2520 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2521 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2522 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2523 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2524 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2525 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2526 cpu_reg.mips_view_base = 0x8000000; 2527 2528 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 2529 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 2530 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 2531 fw.start_addr = bnx_TPAT_b06FwStartAddr; 2532 2533 fw.text_addr = bnx_TPAT_b06FwTextAddr; 2534 fw.text_len = bnx_TPAT_b06FwTextLen; 2535 fw.text_index = 0; 2536 fw.text = bnx_TPAT_b06FwText; 2537 2538 fw.data_addr = bnx_TPAT_b06FwDataAddr; 2539 fw.data_len = bnx_TPAT_b06FwDataLen; 2540 fw.data_index = 0; 2541 fw.data = bnx_TPAT_b06FwData; 2542 2543 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 2544 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 2545 fw.sbss_index = 0; 2546 fw.sbss = bnx_TPAT_b06FwSbss; 2547 2548 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 2549 fw.bss_len = bnx_TPAT_b06FwBssLen; 2550 fw.bss_index = 0; 2551 fw.bss = bnx_TPAT_b06FwBss; 2552 2553 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 2554 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 2555 fw.rodata_index = 0; 2556 fw.rodata = bnx_TPAT_b06FwRodata; 2557 2558 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2559 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2560 2561 /* Initialize the Completion Processor. */ 2562 cpu_reg.mode = BNX_COM_CPU_MODE; 2563 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2564 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2565 cpu_reg.state = BNX_COM_CPU_STATE; 2566 cpu_reg.state_value_clear = 0xffffff; 2567 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2568 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2569 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2570 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2571 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2572 cpu_reg.spad_base = BNX_COM_SCRATCH; 2573 cpu_reg.mips_view_base = 0x8000000; 2574 2575 fw.ver_major = bnx_COM_b06FwReleaseMajor; 2576 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 2577 fw.ver_fix = bnx_COM_b06FwReleaseFix; 2578 fw.start_addr = bnx_COM_b06FwStartAddr; 2579 2580 fw.text_addr = bnx_COM_b06FwTextAddr; 2581 fw.text_len = bnx_COM_b06FwTextLen; 2582 fw.text_index = 0; 2583 fw.text = bnx_COM_b06FwText; 2584 2585 fw.data_addr = bnx_COM_b06FwDataAddr; 2586 fw.data_len = bnx_COM_b06FwDataLen; 2587 fw.data_index = 0; 2588 fw.data = bnx_COM_b06FwData; 2589 2590 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 2591 fw.sbss_len = bnx_COM_b06FwSbssLen; 2592 fw.sbss_index = 0; 2593 fw.sbss = bnx_COM_b06FwSbss; 2594 2595 fw.bss_addr = bnx_COM_b06FwBssAddr; 2596 fw.bss_len = bnx_COM_b06FwBssLen; 2597 fw.bss_index = 0; 2598 fw.bss = bnx_COM_b06FwBss; 2599 2600 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 2601 fw.rodata_len = bnx_COM_b06FwRodataLen; 2602 fw.rodata_index = 0; 2603 fw.rodata = bnx_COM_b06FwRodata; 2604 2605 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2606 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2607 } 2608 2609 /****************************************************************************/ 2610 /* Initialize context memory. */ 2611 /* */ 2612 /* Clears the memory associated with each Context ID (CID). */ 2613 /* */ 2614 /* Returns: */ 2615 /* Nothing. */ 2616 /****************************************************************************/ 2617 void 2618 bnx_init_context(struct bnx_softc *sc) 2619 { 2620 u_int32_t vcid; 2621 2622 vcid = 96; 2623 while (vcid) { 2624 u_int32_t vcid_addr, pcid_addr, offset; 2625 2626 vcid--; 2627 2628 vcid_addr = GET_CID_ADDR(vcid); 2629 pcid_addr = vcid_addr; 2630 2631 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); 2632 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2633 2634 /* Zero out the context. */ 2635 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2636 CTX_WR(sc, 0x00, offset, 0); 2637 2638 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 2639 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2640 } 2641 } 2642 2643 /****************************************************************************/ 2644 /* Fetch the permanent MAC address of the controller. */ 2645 /* */ 2646 /* Returns: */ 2647 /* Nothing. */ 2648 /****************************************************************************/ 2649 void 2650 bnx_get_mac_addr(struct bnx_softc *sc) 2651 { 2652 u_int32_t mac_lo = 0, mac_hi = 0; 2653 2654 /* 2655 * The NetXtreme II bootcode populates various NIC 2656 * power-on and runtime configuration items in a 2657 * shared memory area. The factory configured MAC 2658 * address is available from both NVRAM and the 2659 * shared memory area so we'll read the value from 2660 * shared memory for speed. 2661 */ 2662 2663 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 2664 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 2665 2666 if ((mac_lo == 0) && (mac_hi == 0)) { 2667 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 2668 __FILE__, __LINE__); 2669 } else { 2670 sc->eaddr[0] = (u_char)(mac_hi >> 8); 2671 sc->eaddr[1] = (u_char)(mac_hi >> 0); 2672 sc->eaddr[2] = (u_char)(mac_lo >> 24); 2673 sc->eaddr[3] = (u_char)(mac_lo >> 16); 2674 sc->eaddr[4] = (u_char)(mac_lo >> 8); 2675 sc->eaddr[5] = (u_char)(mac_lo >> 0); 2676 } 2677 2678 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 2679 "%s\n", ether_sprintf(sc->eaddr)); 2680 } 2681 2682 /****************************************************************************/ 2683 /* Program the MAC address. */ 2684 /* */ 2685 /* Returns: */ 2686 /* Nothing. */ 2687 /****************************************************************************/ 2688 void 2689 bnx_set_mac_addr(struct bnx_softc *sc) 2690 { 2691 u_int32_t val; 2692 const u_int8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 2693 2694 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 2695 "%s\n", ether_sprintf(sc->eaddr)); 2696 2697 val = (mac_addr[0] << 8) | mac_addr[1]; 2698 2699 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 2700 2701 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2702 (mac_addr[4] << 8) | mac_addr[5]; 2703 2704 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 2705 } 2706 2707 /****************************************************************************/ 2708 /* Stop the controller. */ 2709 /* */ 2710 /* Returns: */ 2711 /* Nothing. */ 2712 /****************************************************************************/ 2713 void 2714 bnx_stop(struct ifnet *ifp, int disable) 2715 { 2716 struct bnx_softc *sc = ifp->if_softc; 2717 2718 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2719 2720 if ((ifp->if_flags & IFF_RUNNING) == 0) 2721 return; 2722 2723 callout_stop(&sc->bnx_timeout); 2724 2725 mii_down(&sc->bnx_mii); 2726 2727 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2728 2729 /* Disable the transmit/receive blocks. */ 2730 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 2731 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2732 DELAY(20); 2733 2734 bnx_disable_intr(sc); 2735 2736 /* Tell firmware that the driver is going away. */ 2737 if (disable) 2738 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 2739 else 2740 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 2741 2742 /* Free the RX lists. */ 2743 bnx_free_rx_chain(sc); 2744 2745 /* Free TX buffers. */ 2746 bnx_free_tx_chain(sc); 2747 2748 ifp->if_timer = 0; 2749 2750 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2751 2752 } 2753 2754 int 2755 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 2756 { 2757 u_int32_t val; 2758 int i, rc = 0; 2759 2760 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2761 2762 /* Wait for pending PCI transactions to complete. */ 2763 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 2764 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 2765 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 2766 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 2767 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 2768 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2769 DELAY(5); 2770 2771 /* Assume bootcode is running. */ 2772 sc->bnx_fw_timed_out = 0; 2773 2774 /* Give the firmware a chance to prepare for the reset. */ 2775 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 2776 if (rc) 2777 goto bnx_reset_exit; 2778 2779 /* Set a firmware reminder that this is a soft reset. */ 2780 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 2781 BNX_DRV_RESET_SIGNATURE_MAGIC); 2782 2783 /* Dummy read to force the chip to complete all current transactions. */ 2784 val = REG_RD(sc, BNX_MISC_ID); 2785 2786 /* Chip reset. */ 2787 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2788 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 2789 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 2790 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 2791 2792 /* Allow up to 30us for reset to complete. */ 2793 for (i = 0; i < 10; i++) { 2794 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 2795 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2796 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 2797 break; 2798 2799 DELAY(10); 2800 } 2801 2802 /* Check that reset completed successfully. */ 2803 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2804 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 2805 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__); 2806 rc = EBUSY; 2807 goto bnx_reset_exit; 2808 } 2809 2810 /* Make sure byte swapping is properly configured. */ 2811 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 2812 if (val != 0x01020304) { 2813 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 2814 __FILE__, __LINE__); 2815 rc = ENODEV; 2816 goto bnx_reset_exit; 2817 } 2818 2819 /* Just completed a reset, assume that firmware is running again. */ 2820 sc->bnx_fw_timed_out = 0; 2821 2822 /* Wait for the firmware to finish its initialization. */ 2823 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 2824 if (rc) 2825 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 2826 "initialization!\n", __FILE__, __LINE__); 2827 2828 bnx_reset_exit: 2829 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2830 2831 return (rc); 2832 } 2833 2834 int 2835 bnx_chipinit(struct bnx_softc *sc) 2836 { 2837 struct pci_attach_args *pa = &(sc->bnx_pa); 2838 u_int32_t val; 2839 int rc = 0; 2840 2841 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2842 2843 /* Make sure the interrupt is not active. */ 2844 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 2845 2846 /* Initialize DMA byte/word swapping, configure the number of DMA */ 2847 /* channels and PCI clock compensation delay. */ 2848 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 2849 BNX_DMA_CONFIG_DATA_WORD_SWAP | 2850 #if BYTE_ORDER == BIG_ENDIAN 2851 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 2852 #endif 2853 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 2854 DMA_READ_CHANS << 12 | 2855 DMA_WRITE_CHANS << 16; 2856 2857 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 2858 2859 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 2860 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 2861 2862 /* 2863 * This setting resolves a problem observed on certain Intel PCI 2864 * chipsets that cannot handle multiple outstanding DMA operations. 2865 * See errata E9_5706A1_65. 2866 */ 2867 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 2868 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 2869 !(sc->bnx_flags & BNX_PCIX_FLAG)) 2870 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 2871 2872 REG_WR(sc, BNX_DMA_CONFIG, val); 2873 2874 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 2875 if (sc->bnx_flags & BNX_PCIX_FLAG) { 2876 u_int16_t nval; 2877 2878 nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 2879 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 2880 nval & ~0x20000); 2881 } 2882 2883 /* Enable the RX_V2P and Context state machines before access. */ 2884 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 2885 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 2886 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 2887 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 2888 2889 /* Initialize context mapping and zero out the quick contexts. */ 2890 bnx_init_context(sc); 2891 2892 /* Initialize the on-boards CPUs */ 2893 bnx_init_cpus(sc); 2894 2895 /* Prepare NVRAM for access. */ 2896 if (bnx_init_nvram(sc)) { 2897 rc = ENODEV; 2898 goto bnx_chipinit_exit; 2899 } 2900 2901 /* Set the kernel bypass block size */ 2902 val = REG_RD(sc, BNX_MQ_CONFIG); 2903 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 2904 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 2905 REG_WR(sc, BNX_MQ_CONFIG, val); 2906 2907 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 2908 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 2909 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 2910 2911 val = (BCM_PAGE_BITS - 8) << 24; 2912 REG_WR(sc, BNX_RV2P_CONFIG, val); 2913 2914 /* Configure page size. */ 2915 val = REG_RD(sc, BNX_TBDR_CONFIG); 2916 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 2917 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 2918 REG_WR(sc, BNX_TBDR_CONFIG, val); 2919 2920 bnx_chipinit_exit: 2921 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2922 2923 return(rc); 2924 } 2925 2926 /****************************************************************************/ 2927 /* Initialize the controller in preparation to send/receive traffic. */ 2928 /* */ 2929 /* Returns: */ 2930 /* 0 for success, positive value for failure. */ 2931 /****************************************************************************/ 2932 int 2933 bnx_blockinit(struct bnx_softc *sc) 2934 { 2935 u_int32_t reg, val; 2936 int rc = 0; 2937 2938 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2939 2940 /* Load the hardware default MAC address. */ 2941 bnx_set_mac_addr(sc); 2942 2943 /* Set the Ethernet backoff seed value */ 2944 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 2945 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 2946 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 2947 2948 sc->last_status_idx = 0; 2949 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 2950 2951 /* Set up link change interrupt generation. */ 2952 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 2953 2954 /* Program the physical address of the status block. */ 2955 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 2956 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 2957 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 2958 2959 /* Program the physical address of the statistics block. */ 2960 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 2961 (u_int32_t)(sc->stats_block_paddr)); 2962 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 2963 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 2964 2965 /* Program various host coalescing parameters. */ 2966 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 2967 << 16) | sc->bnx_tx_quick_cons_trip); 2968 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 2969 << 16) | sc->bnx_rx_quick_cons_trip); 2970 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 2971 sc->bnx_comp_prod_trip); 2972 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 2973 sc->bnx_tx_ticks); 2974 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 2975 sc->bnx_rx_ticks); 2976 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 2977 sc->bnx_com_ticks); 2978 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 2979 sc->bnx_cmd_ticks); 2980 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 2981 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 2982 REG_WR(sc, BNX_HC_CONFIG, 2983 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 2984 BNX_HC_CONFIG_COLLECT_STATS)); 2985 2986 /* Clear the internal statistics counters. */ 2987 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 2988 2989 /* Verify that bootcode is running. */ 2990 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 2991 2992 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 2993 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 2994 __FILE__, __LINE__); reg = 0); 2995 2996 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 2997 BNX_DEV_INFO_SIGNATURE_MAGIC) { 2998 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 2999 "Expected: 08%08X\n", __FILE__, __LINE__, 3000 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3001 BNX_DEV_INFO_SIGNATURE_MAGIC); 3002 rc = ENODEV; 3003 goto bnx_blockinit_exit; 3004 } 3005 3006 /* Check if any management firmware is running. */ 3007 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3008 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3009 BNX_PORT_FEATURE_IMD_ENABLED)) { 3010 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3011 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3012 } 3013 3014 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3015 BNX_DEV_INFO_BC_REV); 3016 3017 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3018 3019 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3020 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3021 3022 /* Enable link state change interrupt generation. */ 3023 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3024 3025 /* Enable all remaining blocks in the MAC. */ 3026 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3027 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3028 DELAY(20); 3029 3030 bnx_blockinit_exit: 3031 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3032 3033 return (rc); 3034 } 3035 3036 static int 3037 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, u_int16_t *prod, 3038 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3039 { 3040 bus_dmamap_t map; 3041 struct rx_bd *rxbd; 3042 u_int32_t addr; 3043 int i; 3044 #ifdef BNX_DEBUG 3045 u_int16_t debug_chain_prod = *chain_prod; 3046 #endif 3047 u_int16_t first_chain_prod; 3048 3049 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3050 3051 /* Map the mbuf cluster into device memory. */ 3052 map = sc->rx_mbuf_map[*chain_prod]; 3053 first_chain_prod = *chain_prod; 3054 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3055 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3056 __FILE__, __LINE__); 3057 3058 m_freem(m_new); 3059 3060 DBRUNIF(1, sc->rx_mbuf_alloc--); 3061 3062 return ENOBUFS; 3063 } 3064 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3065 BUS_DMASYNC_PREREAD); 3066 3067 /* Watch for overflow. */ 3068 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3069 aprint_error_dev(sc->bnx_dev, 3070 "Too many free rx_bd (0x%04X > 0x%04X)!\n", 3071 sc->free_rx_bd, (u_int16_t)USABLE_RX_BD)); 3072 3073 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3074 sc->rx_low_watermark = sc->free_rx_bd); 3075 3076 /* 3077 * Setup the rx_bd for the first segment 3078 */ 3079 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3080 3081 addr = (u_int32_t)(map->dm_segs[0].ds_addr); 3082 rxbd->rx_bd_haddr_lo = htole32(addr); 3083 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3084 rxbd->rx_bd_haddr_hi = htole32(addr); 3085 rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); 3086 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3087 *prod_bseq += map->dm_segs[0].ds_len; 3088 bus_dmamap_sync(sc->bnx_dmatag, 3089 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3090 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3092 3093 for (i = 1; i < map->dm_nsegs; i++) { 3094 *prod = NEXT_RX_BD(*prod); 3095 *chain_prod = RX_CHAIN_IDX(*prod); 3096 3097 rxbd = 3098 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3099 3100 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 3101 rxbd->rx_bd_haddr_lo = htole32(addr); 3102 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3103 rxbd->rx_bd_haddr_hi = htole32(addr); 3104 rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); 3105 rxbd->rx_bd_flags = 0; 3106 *prod_bseq += map->dm_segs[i].ds_len; 3107 bus_dmamap_sync(sc->bnx_dmatag, 3108 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3109 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3110 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3111 } 3112 3113 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3114 bus_dmamap_sync(sc->bnx_dmatag, 3115 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3116 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3117 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3118 3119 /* 3120 * Save the mbuf, ajust the map pointer (swap map for first and 3121 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3122 * and update counter. 3123 */ 3124 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3125 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3126 sc->rx_mbuf_map[*chain_prod] = map; 3127 sc->free_rx_bd -= map->dm_nsegs; 3128 3129 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3130 map->dm_nsegs)); 3131 *prod = NEXT_RX_BD(*prod); 3132 *chain_prod = RX_CHAIN_IDX(*prod); 3133 3134 return 0; 3135 } 3136 3137 /****************************************************************************/ 3138 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3139 /* */ 3140 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3141 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3142 /* necessary. */ 3143 /* */ 3144 /* Returns: */ 3145 /* 0 for success, positive value for failure. */ 3146 /****************************************************************************/ 3147 int 3148 bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, 3149 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3150 { 3151 struct mbuf *m_new = NULL; 3152 int rc = 0; 3153 u_int16_t min_free_bd; 3154 3155 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3156 __func__); 3157 3158 /* Make sure the inputs are valid. */ 3159 DBRUNIF((*chain_prod > MAX_RX_BD), 3160 aprint_error_dev(sc->bnx_dev, 3161 "RX producer out of range: 0x%04X > 0x%04X\n", 3162 *chain_prod, (u_int16_t)MAX_RX_BD)); 3163 3164 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3165 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3166 *prod_bseq); 3167 3168 /* try to get in as many mbufs as possible */ 3169 if (sc->mbuf_alloc_size == MCLBYTES) 3170 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3171 else 3172 min_free_bd = (BNX_MAX_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3173 while (sc->free_rx_bd >= min_free_bd) { 3174 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3175 BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n"); 3176 3177 sc->mbuf_alloc_failed++; 3178 rc = ENOBUFS; 3179 goto bnx_get_buf_exit); 3180 3181 /* This is a new mbuf allocation. */ 3182 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3183 if (m_new == NULL) { 3184 DBPRINT(sc, BNX_WARN, 3185 "%s(%d): RX mbuf header allocation failed!\n", 3186 __FILE__, __LINE__); 3187 3188 DBRUNIF(1, sc->mbuf_alloc_failed++); 3189 3190 rc = ENOBUFS; 3191 goto bnx_get_buf_exit; 3192 } 3193 3194 DBRUNIF(1, sc->rx_mbuf_alloc++); 3195 if (sc->mbuf_alloc_size == MCLBYTES) 3196 MCLGET(m_new, M_DONTWAIT); 3197 else 3198 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3199 M_DONTWAIT); 3200 if (!(m_new->m_flags & M_EXT)) { 3201 DBPRINT(sc, BNX_WARN, 3202 "%s(%d): RX mbuf chain allocation failed!\n", 3203 __FILE__, __LINE__); 3204 3205 m_freem(m_new); 3206 3207 DBRUNIF(1, sc->rx_mbuf_alloc--); 3208 DBRUNIF(1, sc->mbuf_alloc_failed++); 3209 3210 rc = ENOBUFS; 3211 goto bnx_get_buf_exit; 3212 } 3213 3214 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3215 if (rc != 0) 3216 goto bnx_get_buf_exit; 3217 } 3218 3219 bnx_get_buf_exit: 3220 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3221 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3222 *chain_prod, *prod_bseq); 3223 3224 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3225 __func__); 3226 3227 return(rc); 3228 } 3229 3230 /****************************************************************************/ 3231 /* Allocate memory and initialize the TX data structures. */ 3232 /* */ 3233 /* Returns: */ 3234 /* 0 for success, positive value for failure. */ 3235 /****************************************************************************/ 3236 int 3237 bnx_init_tx_chain(struct bnx_softc *sc) 3238 { 3239 struct tx_bd *txbd; 3240 u_int32_t val, addr; 3241 int i, rc = 0; 3242 3243 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3244 3245 /* Set the initial TX producer/consumer indices. */ 3246 sc->tx_prod = 0; 3247 sc->tx_cons = 0; 3248 sc->tx_prod_bseq = 0; 3249 sc->used_tx_bd = 0; 3250 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3251 3252 /* 3253 * The NetXtreme II supports a linked-list structure called 3254 * a Buffer Descriptor Chain (or BD chain). A BD chain 3255 * consists of a series of 1 or more chain pages, each of which 3256 * consists of a fixed number of BD entries. 3257 * The last BD entry on each page is a pointer to the next page 3258 * in the chain, and the last pointer in the BD chain 3259 * points back to the beginning of the chain. 3260 */ 3261 3262 /* Set the TX next pointer chain entries. */ 3263 for (i = 0; i < TX_PAGES; i++) { 3264 int j; 3265 3266 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3267 3268 /* Check if we've reached the last page. */ 3269 if (i == (TX_PAGES - 1)) 3270 j = 0; 3271 else 3272 j = i + 1; 3273 3274 addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); 3275 txbd->tx_bd_haddr_lo = htole32(addr); 3276 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3277 txbd->tx_bd_haddr_hi = htole32(addr); 3278 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3279 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3280 } 3281 3282 /* 3283 * Initialize the context ID for an L2 TX chain. 3284 */ 3285 val = BNX_L2CTX_TYPE_TYPE_L2; 3286 val |= BNX_L2CTX_TYPE_SIZE_L2; 3287 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3288 3289 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3290 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3291 3292 /* Point the hardware to the first page in the chain. */ 3293 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3294 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3295 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3296 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3297 3298 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3299 3300 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3301 3302 return(rc); 3303 } 3304 3305 /****************************************************************************/ 3306 /* Free memory and clear the TX data structures. */ 3307 /* */ 3308 /* Returns: */ 3309 /* Nothing. */ 3310 /****************************************************************************/ 3311 void 3312 bnx_free_tx_chain(struct bnx_softc *sc) 3313 { 3314 int i; 3315 3316 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3317 3318 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3319 for (i = 0; i < TOTAL_TX_BD; i++) { 3320 if (sc->tx_mbuf_ptr[i] != NULL) { 3321 if (sc->tx_mbuf_map != NULL) 3322 bus_dmamap_sync(sc->bnx_dmatag, 3323 sc->tx_mbuf_map[i], 0, 3324 sc->tx_mbuf_map[i]->dm_mapsize, 3325 BUS_DMASYNC_POSTWRITE); 3326 m_freem(sc->tx_mbuf_ptr[i]); 3327 sc->tx_mbuf_ptr[i] = NULL; 3328 DBRUNIF(1, sc->tx_mbuf_alloc--); 3329 } 3330 } 3331 3332 /* Clear each TX chain page. */ 3333 for (i = 0; i < TX_PAGES; i++) { 3334 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 3335 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3336 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3337 } 3338 3339 /* Check if we lost any mbufs in the process. */ 3340 DBRUNIF((sc->tx_mbuf_alloc), 3341 aprint_error_dev(sc->bnx_dev, 3342 "Memory leak! Lost %d mbufs from tx chain!\n", 3343 sc->tx_mbuf_alloc)); 3344 3345 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3346 } 3347 3348 /****************************************************************************/ 3349 /* Allocate memory and initialize the RX data structures. */ 3350 /* */ 3351 /* Returns: */ 3352 /* 0 for success, positive value for failure. */ 3353 /****************************************************************************/ 3354 int 3355 bnx_init_rx_chain(struct bnx_softc *sc) 3356 { 3357 struct rx_bd *rxbd; 3358 int i, rc = 0; 3359 u_int16_t prod, chain_prod; 3360 u_int32_t prod_bseq, val, addr; 3361 3362 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3363 3364 /* Initialize the RX producer and consumer indices. */ 3365 sc->rx_prod = 0; 3366 sc->rx_cons = 0; 3367 sc->rx_prod_bseq = 0; 3368 sc->free_rx_bd = BNX_RX_SLACK_SPACE; 3369 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3370 3371 /* Initialize the RX next pointer chain entries. */ 3372 for (i = 0; i < RX_PAGES; i++) { 3373 int j; 3374 3375 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3376 3377 /* Check if we've reached the last page. */ 3378 if (i == (RX_PAGES - 1)) 3379 j = 0; 3380 else 3381 j = i + 1; 3382 3383 /* Setup the chain page pointers. */ 3384 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 3385 rxbd->rx_bd_haddr_hi = htole32(addr); 3386 addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); 3387 rxbd->rx_bd_haddr_lo = htole32(addr); 3388 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 3389 0, BNX_RX_CHAIN_PAGE_SZ, 3390 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3391 } 3392 3393 /* Initialize the context ID for an L2 RX chain. */ 3394 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3395 val |= BNX_L2CTX_CTX_TYPE_SIZE_L2; 3396 val |= 0x02 << 8; 3397 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 3398 3399 /* Point the hardware to the first page in the chain. */ 3400 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 3401 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 3402 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 3403 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 3404 3405 /* Allocate mbuf clusters for the rx_bd chain. */ 3406 prod = prod_bseq = 0; 3407 chain_prod = RX_CHAIN_IDX(prod); 3408 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 3409 BNX_PRINTF(sc, 3410 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 3411 } 3412 3413 /* Save the RX chain producer index. */ 3414 sc->rx_prod = prod; 3415 sc->rx_prod_bseq = prod_bseq; 3416 3417 for (i = 0; i < RX_PAGES; i++) 3418 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 3419 sc->rx_bd_chain_map[i]->dm_mapsize, 3420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3421 3422 /* Tell the chip about the waiting rx_bd's. */ 3423 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3424 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3425 3426 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3427 3428 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3429 3430 return(rc); 3431 } 3432 3433 /****************************************************************************/ 3434 /* Free memory and clear the RX data structures. */ 3435 /* */ 3436 /* Returns: */ 3437 /* Nothing. */ 3438 /****************************************************************************/ 3439 void 3440 bnx_free_rx_chain(struct bnx_softc *sc) 3441 { 3442 int i; 3443 3444 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3445 3446 /* Free any mbufs still in the RX mbuf chain. */ 3447 for (i = 0; i < TOTAL_RX_BD; i++) { 3448 if (sc->rx_mbuf_ptr[i] != NULL) { 3449 if (sc->rx_mbuf_map[i] != NULL) 3450 bus_dmamap_sync(sc->bnx_dmatag, 3451 sc->rx_mbuf_map[i], 0, 3452 sc->rx_mbuf_map[i]->dm_mapsize, 3453 BUS_DMASYNC_POSTREAD); 3454 m_freem(sc->rx_mbuf_ptr[i]); 3455 sc->rx_mbuf_ptr[i] = NULL; 3456 DBRUNIF(1, sc->rx_mbuf_alloc--); 3457 } 3458 } 3459 3460 /* Clear each RX chain page. */ 3461 for (i = 0; i < RX_PAGES; i++) 3462 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 3463 3464 /* Check if we lost any mbufs in the process. */ 3465 DBRUNIF((sc->rx_mbuf_alloc), 3466 aprint_error_dev(sc->bnx_dev, 3467 "Memory leak! Lost %d mbufs from rx chain!\n", 3468 sc->rx_mbuf_alloc)); 3469 3470 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3471 } 3472 3473 /****************************************************************************/ 3474 /* Handles PHY generated interrupt events. */ 3475 /* */ 3476 /* Returns: */ 3477 /* Nothing. */ 3478 /****************************************************************************/ 3479 void 3480 bnx_phy_intr(struct bnx_softc *sc) 3481 { 3482 u_int32_t new_link_state, old_link_state; 3483 3484 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3485 BUS_DMASYNC_POSTREAD); 3486 new_link_state = sc->status_block->status_attn_bits & 3487 STATUS_ATTN_BITS_LINK_STATE; 3488 old_link_state = sc->status_block->status_attn_bits_ack & 3489 STATUS_ATTN_BITS_LINK_STATE; 3490 3491 /* Handle any changes if the link state has changed. */ 3492 if (new_link_state != old_link_state) { 3493 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 3494 3495 callout_stop(&sc->bnx_timeout); 3496 bnx_tick(sc); 3497 3498 /* Update the status_attn_bits_ack field in the status block. */ 3499 if (new_link_state) { 3500 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 3501 STATUS_ATTN_BITS_LINK_STATE); 3502 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 3503 } else { 3504 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 3505 STATUS_ATTN_BITS_LINK_STATE); 3506 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 3507 } 3508 } 3509 3510 /* Acknowledge the link change interrupt. */ 3511 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 3512 } 3513 3514 /****************************************************************************/ 3515 /* Handles received frame interrupt events. */ 3516 /* */ 3517 /* Returns: */ 3518 /* Nothing. */ 3519 /****************************************************************************/ 3520 void 3521 bnx_rx_intr(struct bnx_softc *sc) 3522 { 3523 struct status_block *sblk = sc->status_block; 3524 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3525 u_int16_t hw_cons, sw_cons, sw_chain_cons; 3526 u_int16_t sw_prod, sw_chain_prod; 3527 u_int32_t sw_prod_bseq; 3528 struct l2_fhdr *l2fhdr; 3529 int i; 3530 3531 DBRUNIF(1, sc->rx_interrupts++); 3532 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3533 BUS_DMASYNC_POSTREAD); 3534 3535 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3536 for (i = 0; i < RX_PAGES; i++) 3537 bus_dmamap_sync(sc->bnx_dmatag, 3538 sc->rx_bd_chain_map[i], 0, 3539 sc->rx_bd_chain_map[i]->dm_mapsize, 3540 BUS_DMASYNC_POSTWRITE); 3541 3542 /* Get the hardware's view of the RX consumer index. */ 3543 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3544 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3545 hw_cons++; 3546 3547 /* Get working copies of the driver's view of the RX indices. */ 3548 sw_cons = sc->rx_cons; 3549 sw_prod = sc->rx_prod; 3550 sw_prod_bseq = sc->rx_prod_bseq; 3551 3552 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3553 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3554 __func__, sw_prod, sw_cons, sw_prod_bseq); 3555 3556 /* Prevent speculative reads from getting ahead of the status block. */ 3557 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3558 BUS_SPACE_BARRIER_READ); 3559 3560 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3561 sc->rx_low_watermark = sc->free_rx_bd); 3562 3563 /* 3564 * Scan through the receive chain as long 3565 * as there is work to do. 3566 */ 3567 while (sw_cons != hw_cons) { 3568 struct mbuf *m; 3569 struct rx_bd *rxbd; 3570 unsigned int len; 3571 u_int32_t status; 3572 3573 /* Convert the producer/consumer indices to an actual 3574 * rx_bd index. 3575 */ 3576 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3577 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3578 3579 /* Get the used rx_bd. */ 3580 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3581 sc->free_rx_bd++; 3582 3583 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 3584 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 3585 3586 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3587 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3588 #ifdef DIAGNOSTIC 3589 /* Validate that this is the last rx_bd. */ 3590 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 3591 printf("%s: Unexpected mbuf found in " 3592 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 3593 sw_chain_cons); 3594 } 3595 #endif 3596 3597 /* DRC - ToDo: If the received packet is small, say less 3598 * than 128 bytes, allocate a new mbuf here, 3599 * copy the data to that mbuf, and recycle 3600 * the mapped jumbo frame. 3601 */ 3602 3603 /* Unmap the mbuf from DMA space. */ 3604 #ifdef DIAGNOSTIC 3605 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 3606 printf("invalid map sw_cons 0x%x " 3607 "sw_prod 0x%x " 3608 "sw_chain_cons 0x%x " 3609 "sw_chain_prod 0x%x " 3610 "hw_cons 0x%x " 3611 "TOTAL_RX_BD_PER_PAGE 0x%x " 3612 "TOTAL_RX_BD 0x%x\n", 3613 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 3614 hw_cons, 3615 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 3616 } 3617 #endif 3618 bus_dmamap_sync(sc->bnx_dmatag, 3619 sc->rx_mbuf_map[sw_chain_cons], 0, 3620 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 3621 BUS_DMASYNC_POSTREAD); 3622 bus_dmamap_unload(sc->bnx_dmatag, 3623 sc->rx_mbuf_map[sw_chain_cons]); 3624 3625 /* Remove the mbuf from the driver's chain. */ 3626 m = sc->rx_mbuf_ptr[sw_chain_cons]; 3627 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 3628 3629 /* 3630 * Frames received on the NetXteme II are prepended 3631 * with the l2_fhdr structure which provides status 3632 * information about the received frame (including 3633 * VLAN tags and checksum info) and are also 3634 * automatically adjusted to align the IP header 3635 * (i.e. two null bytes are inserted before the 3636 * Ethernet header). 3637 */ 3638 l2fhdr = mtod(m, struct l2_fhdr *); 3639 3640 len = l2fhdr->l2_fhdr_pkt_len; 3641 status = l2fhdr->l2_fhdr_status; 3642 3643 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 3644 aprint_error("Simulating l2_fhdr status error.\n"); 3645 status = status | L2_FHDR_ERRORS_PHY_DECODE); 3646 3647 /* Watch for unusual sized frames. */ 3648 DBRUNIF(((len < BNX_MIN_MTU) || 3649 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 3650 aprint_error_dev(sc->bnx_dev, 3651 "Unusual frame size found. " 3652 "Min(%d), Actual(%d), Max(%d)\n", 3653 (int)BNX_MIN_MTU, len, 3654 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 3655 3656 bnx_dump_mbuf(sc, m); 3657 bnx_breakpoint(sc)); 3658 3659 len -= ETHER_CRC_LEN; 3660 3661 /* Check the received frame for errors. */ 3662 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 3663 L2_FHDR_ERRORS_PHY_DECODE | 3664 L2_FHDR_ERRORS_ALIGNMENT | 3665 L2_FHDR_ERRORS_TOO_SHORT | 3666 L2_FHDR_ERRORS_GIANT_FRAME)) || 3667 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 3668 len > 3669 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 3670 ifp->if_ierrors++; 3671 DBRUNIF(1, sc->l2fhdr_status_errors++); 3672 3673 /* Reuse the mbuf for a new frame. */ 3674 if (bnx_add_buf(sc, m, &sw_prod, 3675 &sw_chain_prod, &sw_prod_bseq)) { 3676 DBRUNIF(1, bnx_breakpoint(sc)); 3677 panic("%s: Can't reuse RX mbuf!\n", 3678 device_xname(sc->bnx_dev)); 3679 } 3680 continue; 3681 } 3682 3683 /* 3684 * Get a new mbuf for the rx_bd. If no new 3685 * mbufs are available then reuse the current mbuf, 3686 * log an ierror on the interface, and generate 3687 * an error in the system log. 3688 */ 3689 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 3690 &sw_prod_bseq)) { 3691 DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate " 3692 "new mbuf, incoming frame dropped!\n")); 3693 3694 ifp->if_ierrors++; 3695 3696 /* Try and reuse the exisitng mbuf. */ 3697 if (bnx_add_buf(sc, m, &sw_prod, 3698 &sw_chain_prod, &sw_prod_bseq)) { 3699 DBRUNIF(1, bnx_breakpoint(sc)); 3700 panic("%s: Double mbuf allocation " 3701 "failure!", 3702 device_xname(sc->bnx_dev)); 3703 } 3704 continue; 3705 } 3706 3707 /* Skip over the l2_fhdr when passing the data up 3708 * the stack. 3709 */ 3710 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 3711 3712 /* Adjust the pckt length to match the received data. */ 3713 m->m_pkthdr.len = m->m_len = len; 3714 3715 /* Send the packet to the appropriate interface. */ 3716 m->m_pkthdr.rcvif = ifp; 3717 3718 DBRUN(BNX_VERBOSE_RECV, 3719 struct ether_header *eh; 3720 eh = mtod(m, struct ether_header *); 3721 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 3722 __func__, ether_sprintf(eh->ether_dhost), 3723 ether_sprintf(eh->ether_shost), 3724 htons(eh->ether_type))); 3725 3726 /* Validate the checksum. */ 3727 3728 /* Check for an IP datagram. */ 3729 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 3730 /* Check if the IP checksum is valid. */ 3731 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 3732 == 0) 3733 m->m_pkthdr.csum_flags |= 3734 M_CSUM_IPv4; 3735 #ifdef BNX_DEBUG 3736 else 3737 DBPRINT(sc, BNX_WARN_SEND, 3738 "%s(): Invalid IP checksum " 3739 "= 0x%04X!\n", 3740 __func__, 3741 l2fhdr->l2_fhdr_ip_xsum 3742 ); 3743 #endif 3744 } 3745 3746 /* Check for a valid TCP/UDP frame. */ 3747 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3748 L2_FHDR_STATUS_UDP_DATAGRAM)) { 3749 /* Check for a good TCP/UDP checksum. */ 3750 if ((status & 3751 (L2_FHDR_ERRORS_TCP_XSUM | 3752 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 3753 m->m_pkthdr.csum_flags |= 3754 M_CSUM_TCPv4 | 3755 M_CSUM_UDPv4; 3756 } else { 3757 DBPRINT(sc, BNX_WARN_SEND, 3758 "%s(): Invalid TCP/UDP " 3759 "checksum = 0x%04X!\n", 3760 __func__, 3761 l2fhdr->l2_fhdr_tcp_udp_xsum); 3762 } 3763 } 3764 3765 /* 3766 * If we received a packet with a vlan tag, 3767 * attach that information to the packet. 3768 */ 3769 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 3770 #if 0 3771 struct ether_vlan_header vh; 3772 3773 DBPRINT(sc, BNX_VERBOSE_SEND, 3774 "%s(): VLAN tag = 0x%04X\n", 3775 __func__, 3776 l2fhdr->l2_fhdr_vlan_tag); 3777 3778 if (m->m_pkthdr.len < ETHER_HDR_LEN) { 3779 m_freem(m); 3780 continue; 3781 } 3782 m_copydata(m, 0, ETHER_HDR_LEN, (void *)&vh); 3783 vh.evl_proto = vh.evl_encap_proto; 3784 vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag; 3785 vh.evl_encap_proto = htons(ETHERTYPE_VLAN); 3786 m_adj(m, ETHER_HDR_LEN); 3787 if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL) 3788 continue; 3789 m->m_pkthdr.len += sizeof(vh); 3790 if (m->m_len < sizeof(vh) && 3791 (m = m_pullup(m, sizeof(vh))) == NULL) 3792 goto bnx_rx_int_next_rx; 3793 m_copyback(m, 0, sizeof(vh), &vh); 3794 #else 3795 VLAN_INPUT_TAG(ifp, m, 3796 l2fhdr->l2_fhdr_vlan_tag, 3797 continue); 3798 #endif 3799 } 3800 3801 #if NBPFILTER > 0 3802 /* 3803 * Handle BPF listeners. Let the BPF 3804 * user see the packet. 3805 */ 3806 if (ifp->if_bpf) 3807 bpf_mtap(ifp->if_bpf, m); 3808 #endif 3809 3810 /* Pass the mbuf off to the upper layers. */ 3811 ifp->if_ipackets++; 3812 DBPRINT(sc, BNX_VERBOSE_RECV, 3813 "%s(): Passing received frame up.\n", __func__); 3814 (*ifp->if_input)(ifp, m); 3815 DBRUNIF(1, sc->rx_mbuf_alloc--); 3816 3817 } 3818 3819 sw_cons = NEXT_RX_BD(sw_cons); 3820 3821 /* Refresh hw_cons to see if there's new work */ 3822 if (sw_cons == hw_cons) { 3823 hw_cons = sc->hw_rx_cons = 3824 sblk->status_rx_quick_consumer_index0; 3825 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 3826 USABLE_RX_BD_PER_PAGE) 3827 hw_cons++; 3828 } 3829 3830 /* Prevent speculative reads from getting ahead of 3831 * the status block. 3832 */ 3833 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3834 BUS_SPACE_BARRIER_READ); 3835 } 3836 3837 for (i = 0; i < RX_PAGES; i++) 3838 bus_dmamap_sync(sc->bnx_dmatag, 3839 sc->rx_bd_chain_map[i], 0, 3840 sc->rx_bd_chain_map[i]->dm_mapsize, 3841 BUS_DMASYNC_PREWRITE); 3842 3843 sc->rx_cons = sw_cons; 3844 sc->rx_prod = sw_prod; 3845 sc->rx_prod_bseq = sw_prod_bseq; 3846 3847 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3848 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3849 3850 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 3851 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 3852 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 3853 } 3854 3855 /****************************************************************************/ 3856 /* Handles transmit completion interrupt events. */ 3857 /* */ 3858 /* Returns: */ 3859 /* Nothing. */ 3860 /****************************************************************************/ 3861 void 3862 bnx_tx_intr(struct bnx_softc *sc) 3863 { 3864 struct status_block *sblk = sc->status_block; 3865 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3866 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 3867 3868 DBRUNIF(1, sc->tx_interrupts++); 3869 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3870 BUS_DMASYNC_POSTREAD); 3871 3872 /* Get the hardware's view of the TX consumer index. */ 3873 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 3874 3875 /* Skip to the next entry if this is a chain page pointer. */ 3876 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 3877 hw_tx_cons++; 3878 3879 sw_tx_cons = sc->tx_cons; 3880 3881 /* Prevent speculative reads from getting ahead of the status block. */ 3882 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3883 BUS_SPACE_BARRIER_READ); 3884 3885 /* Cycle through any completed TX chain page entries. */ 3886 while (sw_tx_cons != hw_tx_cons) { 3887 #ifdef BNX_DEBUG 3888 struct tx_bd *txbd = NULL; 3889 #endif 3890 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 3891 3892 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 3893 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 3894 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 3895 3896 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 3897 aprint_error_dev(sc->bnx_dev, 3898 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 3899 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 3900 3901 DBRUNIF(1, txbd = &sc->tx_bd_chain 3902 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 3903 3904 DBRUNIF((txbd == NULL), 3905 aprint_error_dev(sc->bnx_dev, 3906 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 3907 bnx_breakpoint(sc)); 3908 3909 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 3910 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 3911 3912 /* 3913 * Free the associated mbuf. Remember 3914 * that only the last tx_bd of a packet 3915 * has an mbuf pointer and DMA map. 3916 */ 3917 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 3918 /* Validate that this is the last tx_bd. */ 3919 DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & 3920 TX_BD_FLAGS_END)), 3921 aprint_error_dev(sc->bnx_dev, 3922 "tx_bd END flag not set but txmbuf == NULL!\n"); 3923 bnx_breakpoint(sc)); 3924 3925 DBRUN(BNX_INFO_SEND, 3926 aprint_debug("%s: Unloading map/freeing mbuf " 3927 "from tx_bd[0x%04X]\n", 3928 __func__, sw_tx_chain_cons)); 3929 3930 /* Unmap the mbuf. */ 3931 bus_dmamap_unload(sc->bnx_dmatag, 3932 sc->tx_mbuf_map[sw_tx_chain_cons]); 3933 3934 /* Free the mbuf. */ 3935 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 3936 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 3937 DBRUNIF(1, sc->tx_mbuf_alloc--); 3938 3939 ifp->if_opackets++; 3940 } 3941 3942 sc->used_tx_bd--; 3943 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 3944 3945 /* Refresh hw_cons to see if there's new work. */ 3946 hw_tx_cons = sc->hw_tx_cons = 3947 sblk->status_tx_quick_consumer_index0; 3948 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 3949 USABLE_TX_BD_PER_PAGE) 3950 hw_tx_cons++; 3951 3952 /* Prevent speculative reads from getting ahead of 3953 * the status block. 3954 */ 3955 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3956 BUS_SPACE_BARRIER_READ); 3957 } 3958 3959 /* Clear the TX timeout timer. */ 3960 ifp->if_timer = 0; 3961 3962 /* Clear the tx hardware queue full flag. */ 3963 if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) { 3964 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 3965 aprint_debug_dev(sc->bnx_dev, 3966 "TX chain is open for business! Used tx_bd = %d\n", 3967 sc->used_tx_bd)); 3968 ifp->if_flags &= ~IFF_OACTIVE; 3969 } 3970 3971 sc->tx_cons = sw_tx_cons; 3972 } 3973 3974 /****************************************************************************/ 3975 /* Disables interrupt generation. */ 3976 /* */ 3977 /* Returns: */ 3978 /* Nothing. */ 3979 /****************************************************************************/ 3980 void 3981 bnx_disable_intr(struct bnx_softc *sc) 3982 { 3983 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3984 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 3985 } 3986 3987 /****************************************************************************/ 3988 /* Enables interrupt generation. */ 3989 /* */ 3990 /* Returns: */ 3991 /* Nothing. */ 3992 /****************************************************************************/ 3993 void 3994 bnx_enable_intr(struct bnx_softc *sc) 3995 { 3996 u_int32_t val; 3997 3998 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 3999 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4000 4001 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4002 sc->last_status_idx); 4003 4004 val = REG_RD(sc, BNX_HC_COMMAND); 4005 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4006 } 4007 4008 /****************************************************************************/ 4009 /* Handles controller initialization. */ 4010 /* */ 4011 /****************************************************************************/ 4012 int 4013 bnx_init(struct ifnet *ifp) 4014 { 4015 struct bnx_softc *sc = ifp->if_softc; 4016 u_int32_t ether_mtu; 4017 int s, error = 0; 4018 4019 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4020 4021 s = splnet(); 4022 4023 bnx_stop(ifp, 0); 4024 4025 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4026 aprint_error("bnx: Controller reset failed!\n"); 4027 goto bnx_init_exit; 4028 } 4029 4030 if ((error = bnx_chipinit(sc)) != 0) { 4031 aprint_error("bnx: Controller initialization failed!\n"); 4032 goto bnx_init_exit; 4033 } 4034 4035 if ((error = bnx_blockinit(sc)) != 0) { 4036 aprint_error("bnx: Block initialization failed!\n"); 4037 goto bnx_init_exit; 4038 } 4039 4040 /* Calculate and program the Ethernet MRU size. */ 4041 if (ifp->if_mtu <= ETHERMTU) { 4042 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4043 sc->mbuf_alloc_size = MCLBYTES; 4044 } else { 4045 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4046 sc->mbuf_alloc_size = BNX_MAX_MRU; 4047 } 4048 4049 4050 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4051 __func__, ether_mtu); 4052 4053 /* 4054 * Program the MRU and enable Jumbo frame 4055 * support. 4056 */ 4057 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4058 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4059 4060 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4061 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4062 4063 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4064 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4065 sc->mbuf_alloc_size, sc->max_frame_size); 4066 4067 /* Program appropriate promiscuous/multicast filtering. */ 4068 bnx_set_rx_mode(sc); 4069 4070 /* Init RX buffer descriptor chain. */ 4071 bnx_init_rx_chain(sc); 4072 4073 /* Init TX buffer descriptor chain. */ 4074 bnx_init_tx_chain(sc); 4075 4076 /* Enable host interrupts. */ 4077 bnx_enable_intr(sc); 4078 4079 if ((error = ether_mediachange(ifp)) != 0) 4080 goto bnx_init_exit; 4081 4082 ifp->if_flags |= IFF_RUNNING; 4083 ifp->if_flags &= ~IFF_OACTIVE; 4084 4085 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4086 4087 bnx_init_exit: 4088 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4089 4090 splx(s); 4091 4092 return(error); 4093 } 4094 4095 /****************************************************************************/ 4096 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4097 /* memory visible to the controller. */ 4098 /* */ 4099 /* Returns: */ 4100 /* 0 for success, positive value for failure. */ 4101 /****************************************************************************/ 4102 int 4103 bnx_tx_encap(struct bnx_softc *sc, struct mbuf **m_head) 4104 { 4105 bus_dmamap_t map; 4106 struct tx_bd *txbd = NULL; 4107 struct mbuf *m0; 4108 u_int16_t vlan_tag = 0, flags = 0; 4109 u_int16_t chain_prod, prod; 4110 #ifdef BNX_DEBUG 4111 u_int16_t debug_prod; 4112 #endif 4113 u_int32_t addr, prod_bseq; 4114 int i, error, rc = 0; 4115 struct m_tag *mtag; 4116 4117 m0 = *m_head; 4118 4119 /* Transfer any checksum offload flags to the bd. */ 4120 if (m0->m_pkthdr.csum_flags) { 4121 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 4122 flags |= TX_BD_FLAGS_IP_CKSUM; 4123 if (m0->m_pkthdr.csum_flags & 4124 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4125 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4126 } 4127 4128 /* Transfer any VLAN tags to the bd. */ 4129 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m0); 4130 if (mtag != NULL) { 4131 flags |= TX_BD_FLAGS_VLAN_TAG; 4132 vlan_tag = VLAN_TAG_VALUE(mtag); 4133 } 4134 4135 /* Map the mbuf into DMAable memory. */ 4136 prod = sc->tx_prod; 4137 chain_prod = TX_CHAIN_IDX(prod); 4138 map = sc->tx_mbuf_map[chain_prod]; 4139 4140 /* Map the mbuf into our DMA address space. */ 4141 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m0, BUS_DMA_NOWAIT); 4142 if (error != 0) { 4143 aprint_error_dev(sc->bnx_dev, 4144 "Error mapping mbuf into TX chain!\n"); 4145 m_freem(m0); 4146 *m_head = NULL; 4147 return (error); 4148 } 4149 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4150 BUS_DMASYNC_PREWRITE); 4151 /* 4152 * The chip seems to require that at least 16 descriptors be kept 4153 * empty at all times. Make sure we honor that. 4154 * XXX Would it be faster to assume worst case scenario for 4155 * map->dm_nsegs and do this calculation higher up? 4156 */ 4157 if (map->dm_nsegs > (USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE)) { 4158 bus_dmamap_unload(sc->bnx_dmatag, map); 4159 return (ENOBUFS); 4160 } 4161 4162 /* prod points to an empty tx_bd at this point. */ 4163 prod_bseq = sc->tx_prod_bseq; 4164 #ifdef BNX_DEBUG 4165 debug_prod = chain_prod; 4166 #endif 4167 DBPRINT(sc, BNX_INFO_SEND, 4168 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4169 "prod_bseq = 0x%08X\n", 4170 __func__, *prod, chain_prod, prod_bseq); 4171 4172 /* 4173 * Cycle through each mbuf segment that makes up 4174 * the outgoing frame, gathering the mapping info 4175 * for that segment and creating a tx_bd for the 4176 * mbuf. 4177 */ 4178 for (i = 0; i < map->dm_nsegs ; i++) { 4179 chain_prod = TX_CHAIN_IDX(prod); 4180 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4181 4182 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 4183 txbd->tx_bd_haddr_lo = htole32(addr); 4184 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4185 txbd->tx_bd_haddr_hi = htole32(addr); 4186 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 4187 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4188 txbd->tx_bd_flags = htole16(flags); 4189 prod_bseq += map->dm_segs[i].ds_len; 4190 if (i == 0) 4191 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4192 prod = NEXT_TX_BD(prod); 4193 } 4194 /* Set the END flag on the last TX buffer descriptor. */ 4195 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4196 4197 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg)); 4198 4199 DBPRINT(sc, BNX_INFO_SEND, 4200 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4201 "prod_bseq = 0x%08X\n", 4202 __func__, prod, chain_prod, prod_bseq); 4203 4204 /* 4205 * Ensure that the mbuf pointer for this 4206 * transmission is placed at the array 4207 * index of the last descriptor in this 4208 * chain. This is done because a single 4209 * map is used for all segments of the mbuf 4210 * and we don't want to unload the map before 4211 * all of the segments have been freed. 4212 */ 4213 sc->tx_mbuf_ptr[chain_prod] = m0; 4214 sc->used_tx_bd += map->dm_nsegs; 4215 4216 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4217 sc->tx_hi_watermark = sc->used_tx_bd); 4218 4219 DBRUNIF(1, sc->tx_mbuf_alloc++); 4220 4221 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4222 map_arg.maxsegs)); 4223 4224 /* prod points to the next free tx_bd at this point. */ 4225 sc->tx_prod = prod; 4226 sc->tx_prod_bseq = prod_bseq; 4227 4228 return (rc); 4229 } 4230 4231 /****************************************************************************/ 4232 /* Main transmit routine. */ 4233 /* */ 4234 /* Returns: */ 4235 /* Nothing. */ 4236 /****************************************************************************/ 4237 void 4238 bnx_start(struct ifnet *ifp) 4239 { 4240 struct bnx_softc *sc = ifp->if_softc; 4241 struct mbuf *m_head = NULL; 4242 int count = 0; 4243 u_int16_t tx_prod, tx_chain_prod; 4244 4245 /* If there's no link or the transmit queue is empty then just exit. */ 4246 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 4247 DBPRINT(sc, BNX_INFO_SEND, 4248 "%s(): output active or device not running.\n", __func__); 4249 goto bnx_start_exit; 4250 } 4251 4252 /* prod points to the next free tx_bd. */ 4253 tx_prod = sc->tx_prod; 4254 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4255 4256 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 4257 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n", 4258 __func__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4259 4260 /* 4261 * Keep adding entries while there is space in the ring. We keep 4262 * BNX_TX_SLACK_SPACE entries unused at all times. 4263 */ 4264 while (sc->used_tx_bd < USABLE_TX_BD - BNX_TX_SLACK_SPACE) { 4265 /* Check for any frames to send. */ 4266 IFQ_POLL(&ifp->if_snd, m_head); 4267 if (m_head == NULL) 4268 break; 4269 4270 /* 4271 * Pack the data into the transmit ring. If we 4272 * don't have room, set the OACTIVE flag to wait 4273 * for the NIC to drain the chain. 4274 */ 4275 if (bnx_tx_encap(sc, &m_head)) { 4276 ifp->if_flags |= IFF_OACTIVE; 4277 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 4278 "business! Total tx_bd used = %d\n", 4279 sc->used_tx_bd); 4280 break; 4281 } 4282 4283 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4284 count++; 4285 4286 #if NBPFILTER > 0 4287 /* Send a copy of the frame to any BPF listeners. */ 4288 if (ifp->if_bpf) 4289 bpf_mtap(ifp->if_bpf, m_head); 4290 #endif 4291 } 4292 4293 if (count == 0) { 4294 /* no packets were dequeued */ 4295 DBPRINT(sc, BNX_VERBOSE_SEND, 4296 "%s(): No packets were dequeued\n", __func__); 4297 goto bnx_start_exit; 4298 } 4299 4300 /* Update the driver's counters. */ 4301 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4302 4303 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 4304 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, tx_prod, 4305 tx_chain_prod, sc->tx_prod_bseq); 4306 4307 /* Start the transmit. */ 4308 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4309 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4310 4311 /* Set the tx timeout. */ 4312 ifp->if_timer = BNX_TX_TIMEOUT; 4313 4314 bnx_start_exit: 4315 return; 4316 } 4317 4318 /****************************************************************************/ 4319 /* Handles any IOCTL calls from the operating system. */ 4320 /* */ 4321 /* Returns: */ 4322 /* 0 for success, positive value for failure. */ 4323 /****************************************************************************/ 4324 int 4325 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 4326 { 4327 struct bnx_softc *sc = ifp->if_softc; 4328 struct ifreq *ifr = (struct ifreq *) data; 4329 struct mii_data *mii = &sc->bnx_mii; 4330 int s, error = 0; 4331 4332 s = splnet(); 4333 4334 switch (command) { 4335 case SIOCSIFFLAGS: 4336 if ((error = ifioctl_common(ifp, command, data)) != 0) 4337 break; 4338 /* XXX set an ifflags callback and let ether_ioctl 4339 * handle all of this. 4340 */ 4341 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 4342 case IFF_UP|IFF_RUNNING: 4343 if (((ifp->if_flags ^ sc->bnx_if_flags) & 4344 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 4345 bnx_set_rx_mode(sc); 4346 break; 4347 case IFF_UP: 4348 bnx_init(ifp); 4349 break; 4350 case IFF_RUNNING: 4351 bnx_stop(ifp, 1); 4352 break; 4353 case 0: 4354 break; 4355 } 4356 4357 sc->bnx_if_flags = ifp->if_flags; 4358 break; 4359 4360 case SIOCSIFMEDIA: 4361 case SIOCGIFMEDIA: 4362 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 4363 sc->bnx_phy_flags); 4364 4365 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 4366 break; 4367 4368 default: 4369 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4370 break; 4371 4372 error = 0; 4373 4374 if (command != SIOCADDMULTI && command && SIOCDELMULTI) 4375 ; 4376 else if (ifp->if_flags & IFF_RUNNING) { 4377 /* reload packet filter if running */ 4378 bnx_set_rx_mode(sc); 4379 } 4380 break; 4381 } 4382 4383 splx(s); 4384 4385 return (error); 4386 } 4387 4388 /****************************************************************************/ 4389 /* Transmit timeout handler. */ 4390 /* */ 4391 /* Returns: */ 4392 /* Nothing. */ 4393 /****************************************************************************/ 4394 void 4395 bnx_watchdog(struct ifnet *ifp) 4396 { 4397 struct bnx_softc *sc = ifp->if_softc; 4398 4399 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 4400 bnx_dump_status_block(sc)); 4401 4402 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 4403 4404 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 4405 4406 bnx_init(ifp); 4407 4408 ifp->if_oerrors++; 4409 } 4410 4411 /* 4412 * Interrupt handler. 4413 */ 4414 /****************************************************************************/ 4415 /* Main interrupt entry point. Verifies that the controller generated the */ 4416 /* interrupt and then calls a separate routine for handle the various */ 4417 /* interrupt causes (PHY, TX, RX). */ 4418 /* */ 4419 /* Returns: */ 4420 /* 0 for success, positive value for failure. */ 4421 /****************************************************************************/ 4422 int 4423 bnx_intr(void *xsc) 4424 { 4425 struct bnx_softc *sc; 4426 struct ifnet *ifp; 4427 u_int32_t status_attn_bits; 4428 const struct status_block *sblk; 4429 4430 sc = xsc; 4431 if (!device_is_active(sc->bnx_dev)) 4432 return 0; 4433 4434 ifp = &sc->bnx_ec.ec_if; 4435 4436 DBRUNIF(1, sc->interrupts_generated++); 4437 4438 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4439 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4440 4441 /* 4442 * If the hardware status block index 4443 * matches the last value read by the 4444 * driver and we haven't asserted our 4445 * interrupt then there's nothing to do. 4446 */ 4447 if ((sc->status_block->status_idx == sc->last_status_idx) && 4448 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 4449 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 4450 return (0); 4451 4452 /* Ack the interrupt and stop others from occuring. */ 4453 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4454 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 4455 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4456 4457 /* Keep processing data as long as there is work to do. */ 4458 for (;;) { 4459 sblk = sc->status_block; 4460 status_attn_bits = sblk->status_attn_bits; 4461 4462 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 4463 aprint_debug("Simulating unexpected status attention bit set."); 4464 status_attn_bits = status_attn_bits | 4465 STATUS_ATTN_BITS_PARITY_ERROR); 4466 4467 /* Was it a link change interrupt? */ 4468 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 4469 (sblk->status_attn_bits_ack & 4470 STATUS_ATTN_BITS_LINK_STATE)) 4471 bnx_phy_intr(sc); 4472 4473 /* If any other attention is asserted then the chip is toast. */ 4474 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 4475 (sblk->status_attn_bits_ack & 4476 ~STATUS_ATTN_BITS_LINK_STATE))) { 4477 DBRUN(1, sc->unexpected_attentions++); 4478 4479 aprint_error_dev(sc->bnx_dev, 4480 "Fatal attention detected: 0x%08X\n", 4481 sblk->status_attn_bits); 4482 4483 DBRUN(BNX_FATAL, 4484 if (bnx_debug_unexpected_attention == 0) 4485 bnx_breakpoint(sc)); 4486 4487 bnx_init(ifp); 4488 return (1); 4489 } 4490 4491 /* Check for any completed RX frames. */ 4492 if (sblk->status_rx_quick_consumer_index0 != 4493 sc->hw_rx_cons) 4494 bnx_rx_intr(sc); 4495 4496 /* Check for any completed TX frames. */ 4497 if (sblk->status_tx_quick_consumer_index0 != 4498 sc->hw_tx_cons) 4499 bnx_tx_intr(sc); 4500 4501 /* Save the status block index value for use during the 4502 * next interrupt. 4503 */ 4504 sc->last_status_idx = sblk->status_idx; 4505 4506 /* Prevent speculative reads from getting ahead of the 4507 * status block. 4508 */ 4509 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4510 BUS_SPACE_BARRIER_READ); 4511 4512 /* If there's no work left then exit the isr. */ 4513 if ((sblk->status_rx_quick_consumer_index0 == 4514 sc->hw_rx_cons) && 4515 (sblk->status_tx_quick_consumer_index0 == 4516 sc->hw_tx_cons)) 4517 break; 4518 } 4519 4520 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4521 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 4522 4523 /* Re-enable interrupts. */ 4524 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4525 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 4526 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4527 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4528 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4529 4530 /* Handle any frames that arrived while handling the interrupt. */ 4531 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4532 bnx_start(ifp); 4533 4534 return (1); 4535 } 4536 4537 /****************************************************************************/ 4538 /* Programs the various packet receive modes (broadcast and multicast). */ 4539 /* */ 4540 /* Returns: */ 4541 /* Nothing. */ 4542 /****************************************************************************/ 4543 void 4544 bnx_set_rx_mode(struct bnx_softc *sc) 4545 { 4546 struct ethercom *ec = &sc->bnx_ec; 4547 struct ifnet *ifp = &ec->ec_if; 4548 struct ether_multi *enm; 4549 struct ether_multistep step; 4550 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 4551 u_int32_t rx_mode, sort_mode; 4552 int h, i; 4553 4554 /* Initialize receive mode default settings. */ 4555 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 4556 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 4557 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 4558 4559 /* 4560 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 4561 * be enbled. 4562 */ 4563 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 4564 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 4565 4566 /* 4567 * Check for promiscuous, all multicast, or selected 4568 * multicast address filtering. 4569 */ 4570 if (ifp->if_flags & IFF_PROMISC) { 4571 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 4572 4573 /* Enable promiscuous mode. */ 4574 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 4575 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 4576 } else if (ifp->if_flags & IFF_ALLMULTI) { 4577 allmulti: 4578 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 4579 4580 /* Enable all multicast addresses. */ 4581 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4582 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4583 0xffffffff); 4584 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 4585 } else { 4586 /* Accept one or more multicast(s). */ 4587 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 4588 4589 ETHER_FIRST_MULTI(step, ec, enm); 4590 while (enm != NULL) { 4591 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 4592 ETHER_ADDR_LEN)) { 4593 ifp->if_flags |= IFF_ALLMULTI; 4594 goto allmulti; 4595 } 4596 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 4597 0xFF; 4598 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 4599 ETHER_NEXT_MULTI(step, enm); 4600 } 4601 4602 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4603 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4604 hashes[i]); 4605 4606 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 4607 } 4608 4609 /* Only make changes if the recive mode has actually changed. */ 4610 if (rx_mode != sc->rx_mode) { 4611 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 4612 rx_mode); 4613 4614 sc->rx_mode = rx_mode; 4615 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 4616 } 4617 4618 /* Disable and clear the exisitng sort before enabling a new sort. */ 4619 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 4620 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 4621 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 4622 } 4623 4624 /****************************************************************************/ 4625 /* Called periodically to updates statistics from the controllers */ 4626 /* statistics block. */ 4627 /* */ 4628 /* Returns: */ 4629 /* Nothing. */ 4630 /****************************************************************************/ 4631 void 4632 bnx_stats_update(struct bnx_softc *sc) 4633 { 4634 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4635 struct statistics_block *stats; 4636 4637 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 4638 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4639 BUS_DMASYNC_POSTREAD); 4640 4641 stats = (struct statistics_block *)sc->stats_block; 4642 4643 /* 4644 * Update the interface statistics from the 4645 * hardware statistics. 4646 */ 4647 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 4648 4649 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 4650 (u_long)stats->stat_EtherStatsOverrsizePkts + 4651 (u_long)stats->stat_IfInMBUFDiscards + 4652 (u_long)stats->stat_Dot3StatsAlignmentErrors + 4653 (u_long)stats->stat_Dot3StatsFCSErrors; 4654 4655 ifp->if_oerrors = (u_long) 4656 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 4657 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 4658 (u_long)stats->stat_Dot3StatsLateCollisions; 4659 4660 /* 4661 * Certain controllers don't report 4662 * carrier sense errors correctly. 4663 * See errata E11_5708CA0_1165. 4664 */ 4665 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 4666 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 4667 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 4668 4669 /* 4670 * Update the sysctl statistics from the 4671 * hardware statistics. 4672 */ 4673 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 4674 (u_int64_t) stats->stat_IfHCInOctets_lo; 4675 4676 sc->stat_IfHCInBadOctets = 4677 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 4678 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 4679 4680 sc->stat_IfHCOutOctets = 4681 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 4682 (u_int64_t) stats->stat_IfHCOutOctets_lo; 4683 4684 sc->stat_IfHCOutBadOctets = 4685 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 4686 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 4687 4688 sc->stat_IfHCInUcastPkts = 4689 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 4690 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 4691 4692 sc->stat_IfHCInMulticastPkts = 4693 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 4694 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 4695 4696 sc->stat_IfHCInBroadcastPkts = 4697 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 4698 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 4699 4700 sc->stat_IfHCOutUcastPkts = 4701 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 4702 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 4703 4704 sc->stat_IfHCOutMulticastPkts = 4705 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 4706 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 4707 4708 sc->stat_IfHCOutBroadcastPkts = 4709 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 4710 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 4711 4712 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 4713 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4714 4715 sc->stat_Dot3StatsCarrierSenseErrors = 4716 stats->stat_Dot3StatsCarrierSenseErrors; 4717 4718 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 4719 4720 sc->stat_Dot3StatsAlignmentErrors = 4721 stats->stat_Dot3StatsAlignmentErrors; 4722 4723 sc->stat_Dot3StatsSingleCollisionFrames = 4724 stats->stat_Dot3StatsSingleCollisionFrames; 4725 4726 sc->stat_Dot3StatsMultipleCollisionFrames = 4727 stats->stat_Dot3StatsMultipleCollisionFrames; 4728 4729 sc->stat_Dot3StatsDeferredTransmissions = 4730 stats->stat_Dot3StatsDeferredTransmissions; 4731 4732 sc->stat_Dot3StatsExcessiveCollisions = 4733 stats->stat_Dot3StatsExcessiveCollisions; 4734 4735 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 4736 4737 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 4738 4739 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 4740 4741 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 4742 4743 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 4744 4745 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 4746 4747 sc->stat_EtherStatsPktsRx64Octets = 4748 stats->stat_EtherStatsPktsRx64Octets; 4749 4750 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 4751 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 4752 4753 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 4754 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 4755 4756 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 4757 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 4758 4759 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 4760 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 4761 4762 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 4763 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 4764 4765 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 4766 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 4767 4768 sc->stat_EtherStatsPktsTx64Octets = 4769 stats->stat_EtherStatsPktsTx64Octets; 4770 4771 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 4772 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 4773 4774 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 4775 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 4776 4777 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 4778 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 4779 4780 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 4781 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 4782 4783 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 4784 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 4785 4786 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 4787 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 4788 4789 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 4790 4791 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 4792 4793 sc->stat_OutXonSent = stats->stat_OutXonSent; 4794 4795 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 4796 4797 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 4798 4799 sc->stat_MacControlFramesReceived = 4800 stats->stat_MacControlFramesReceived; 4801 4802 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 4803 4804 sc->stat_IfInFramesL2FilterDiscards = 4805 stats->stat_IfInFramesL2FilterDiscards; 4806 4807 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 4808 4809 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 4810 4811 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 4812 4813 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 4814 4815 sc->stat_CatchupInRuleCheckerDiscards = 4816 stats->stat_CatchupInRuleCheckerDiscards; 4817 4818 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 4819 4820 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 4821 4822 sc->stat_CatchupInRuleCheckerP4Hit = 4823 stats->stat_CatchupInRuleCheckerP4Hit; 4824 4825 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 4826 } 4827 4828 void 4829 bnx_tick(void *xsc) 4830 { 4831 struct bnx_softc *sc = xsc; 4832 struct mii_data *mii; 4833 u_int32_t msg; 4834 u_int16_t prod, chain_prod; 4835 u_int32_t prod_bseq; 4836 int s = splnet(); 4837 4838 /* Tell the firmware that the driver is still running. */ 4839 #ifdef BNX_DEBUG 4840 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 4841 #else 4842 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 4843 #endif 4844 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 4845 4846 /* Update the statistics from the hardware statistics block. */ 4847 bnx_stats_update(sc); 4848 4849 /* Schedule the next tick. */ 4850 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4851 4852 mii = &sc->bnx_mii; 4853 mii_tick(mii); 4854 4855 /* try to get more RX buffers, just in case */ 4856 prod = sc->rx_prod; 4857 prod_bseq = sc->rx_prod_bseq; 4858 chain_prod = RX_CHAIN_IDX(prod); 4859 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 4860 sc->rx_prod = prod; 4861 sc->rx_prod_bseq = prod_bseq; 4862 splx(s); 4863 return; 4864 } 4865 4866 /****************************************************************************/ 4867 /* BNX Debug Routines */ 4868 /****************************************************************************/ 4869 #ifdef BNX_DEBUG 4870 4871 /****************************************************************************/ 4872 /* Prints out information about an mbuf. */ 4873 /* */ 4874 /* Returns: */ 4875 /* Nothing. */ 4876 /****************************************************************************/ 4877 void 4878 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 4879 { 4880 struct mbuf *mp = m; 4881 4882 if (m == NULL) { 4883 /* Index out of range. */ 4884 aprint_error("mbuf ptr is null!\n"); 4885 return; 4886 } 4887 4888 while (mp) { 4889 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 4890 mp, mp->m_len); 4891 4892 if (mp->m_flags & M_EXT) 4893 aprint_debug("M_EXT "); 4894 if (mp->m_flags & M_PKTHDR) 4895 aprint_debug("M_PKTHDR "); 4896 aprint_debug("\n"); 4897 4898 if (mp->m_flags & M_EXT) 4899 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 4900 mp, mp->m_ext.ext_size); 4901 4902 mp = mp->m_next; 4903 } 4904 } 4905 4906 /****************************************************************************/ 4907 /* Prints out the mbufs in the TX mbuf chain. */ 4908 /* */ 4909 /* Returns: */ 4910 /* Nothing. */ 4911 /****************************************************************************/ 4912 void 4913 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4914 { 4915 struct mbuf *m; 4916 int i; 4917 4918 BNX_PRINTF(sc, 4919 "----------------------------" 4920 " tx mbuf data " 4921 "----------------------------\n"); 4922 4923 for (i = 0; i < count; i++) { 4924 m = sc->tx_mbuf_ptr[chain_prod]; 4925 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 4926 bnx_dump_mbuf(sc, m); 4927 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 4928 } 4929 4930 BNX_PRINTF(sc, 4931 "--------------------------------------------" 4932 "----------------------------\n"); 4933 } 4934 4935 /* 4936 * This routine prints the RX mbuf chain. 4937 */ 4938 void 4939 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4940 { 4941 struct mbuf *m; 4942 int i; 4943 4944 BNX_PRINTF(sc, 4945 "----------------------------" 4946 " rx mbuf data " 4947 "----------------------------\n"); 4948 4949 for (i = 0; i < count; i++) { 4950 m = sc->rx_mbuf_ptr[chain_prod]; 4951 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 4952 bnx_dump_mbuf(sc, m); 4953 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 4954 } 4955 4956 4957 BNX_PRINTF(sc, 4958 "--------------------------------------------" 4959 "----------------------------\n"); 4960 } 4961 4962 void 4963 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 4964 { 4965 if (idx > MAX_TX_BD) 4966 /* Index out of range. */ 4967 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 4968 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4969 /* TX Chain page pointer. */ 4970 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 4971 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 4972 txbd->tx_bd_haddr_lo); 4973 else 4974 /* Normal tx_bd entry. */ 4975 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 4976 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 4977 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 4978 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 4979 txbd->tx_bd_flags); 4980 } 4981 4982 void 4983 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 4984 { 4985 if (idx > MAX_RX_BD) 4986 /* Index out of range. */ 4987 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 4988 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4989 /* TX Chain page pointer. */ 4990 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 4991 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 4992 rxbd->rx_bd_haddr_lo); 4993 else 4994 /* Normal tx_bd entry. */ 4995 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 4996 "0x%08X, flags = 0x%08X\n", idx, 4997 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 4998 rxbd->rx_bd_len, rxbd->rx_bd_flags); 4999 } 5000 5001 void 5002 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5003 { 5004 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5005 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5006 "tcp_udp_xsum = 0x%04X\n", idx, 5007 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5008 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5009 l2fhdr->l2_fhdr_tcp_udp_xsum); 5010 } 5011 5012 /* 5013 * This routine prints the TX chain. 5014 */ 5015 void 5016 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5017 { 5018 struct tx_bd *txbd; 5019 int i; 5020 5021 /* First some info about the tx_bd chain structure. */ 5022 BNX_PRINTF(sc, 5023 "----------------------------" 5024 " tx_bd chain " 5025 "----------------------------\n"); 5026 5027 BNX_PRINTF(sc, 5028 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5029 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5030 5031 BNX_PRINTF(sc, 5032 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5033 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5034 5035 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD); 5036 5037 BNX_PRINTF(sc, "" 5038 "-----------------------------" 5039 " tx_bd data " 5040 "-----------------------------\n"); 5041 5042 /* Now print out the tx_bd's themselves. */ 5043 for (i = 0; i < count; i++) { 5044 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5045 bnx_dump_txbd(sc, tx_prod, txbd); 5046 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5047 } 5048 5049 BNX_PRINTF(sc, 5050 "-----------------------------" 5051 "--------------" 5052 "-----------------------------\n"); 5053 } 5054 5055 /* 5056 * This routine prints the RX chain. 5057 */ 5058 void 5059 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5060 { 5061 struct rx_bd *rxbd; 5062 int i; 5063 5064 /* First some info about the tx_bd chain structure. */ 5065 BNX_PRINTF(sc, 5066 "----------------------------" 5067 " rx_bd chain " 5068 "----------------------------\n"); 5069 5070 BNX_PRINTF(sc, "----- RX_BD Chain -----\n"); 5071 5072 BNX_PRINTF(sc, 5073 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5074 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5075 5076 BNX_PRINTF(sc, 5077 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5078 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5079 5080 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD); 5081 5082 BNX_PRINTF(sc, 5083 "----------------------------" 5084 " rx_bd data " 5085 "----------------------------\n"); 5086 5087 /* Now print out the rx_bd's themselves. */ 5088 for (i = 0; i < count; i++) { 5089 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5090 bnx_dump_rxbd(sc, rx_prod, rxbd); 5091 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5092 } 5093 5094 BNX_PRINTF(sc, 5095 "----------------------------" 5096 "--------------" 5097 "----------------------------\n"); 5098 } 5099 5100 /* 5101 * This routine prints the status block. 5102 */ 5103 void 5104 bnx_dump_status_block(struct bnx_softc *sc) 5105 { 5106 struct status_block *sblk; 5107 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5108 BUS_DMASYNC_POSTREAD); 5109 5110 sblk = sc->status_block; 5111 5112 BNX_PRINTF(sc, "----------------------------- Status Block " 5113 "-----------------------------\n"); 5114 5115 BNX_PRINTF(sc, 5116 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5117 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5118 sblk->status_idx); 5119 5120 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5121 sblk->status_rx_quick_consumer_index0, 5122 sblk->status_tx_quick_consumer_index0); 5123 5124 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5125 5126 /* Theses indices are not used for normal L2 drivers. */ 5127 if (sblk->status_rx_quick_consumer_index1 || 5128 sblk->status_tx_quick_consumer_index1) 5129 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5130 sblk->status_rx_quick_consumer_index1, 5131 sblk->status_tx_quick_consumer_index1); 5132 5133 if (sblk->status_rx_quick_consumer_index2 || 5134 sblk->status_tx_quick_consumer_index2) 5135 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5136 sblk->status_rx_quick_consumer_index2, 5137 sblk->status_tx_quick_consumer_index2); 5138 5139 if (sblk->status_rx_quick_consumer_index3 || 5140 sblk->status_tx_quick_consumer_index3) 5141 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5142 sblk->status_rx_quick_consumer_index3, 5143 sblk->status_tx_quick_consumer_index3); 5144 5145 if (sblk->status_rx_quick_consumer_index4 || 5146 sblk->status_rx_quick_consumer_index5) 5147 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5148 sblk->status_rx_quick_consumer_index4, 5149 sblk->status_rx_quick_consumer_index5); 5150 5151 if (sblk->status_rx_quick_consumer_index6 || 5152 sblk->status_rx_quick_consumer_index7) 5153 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5154 sblk->status_rx_quick_consumer_index6, 5155 sblk->status_rx_quick_consumer_index7); 5156 5157 if (sblk->status_rx_quick_consumer_index8 || 5158 sblk->status_rx_quick_consumer_index9) 5159 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5160 sblk->status_rx_quick_consumer_index8, 5161 sblk->status_rx_quick_consumer_index9); 5162 5163 if (sblk->status_rx_quick_consumer_index10 || 5164 sblk->status_rx_quick_consumer_index11) 5165 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5166 sblk->status_rx_quick_consumer_index10, 5167 sblk->status_rx_quick_consumer_index11); 5168 5169 if (sblk->status_rx_quick_consumer_index12 || 5170 sblk->status_rx_quick_consumer_index13) 5171 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5172 sblk->status_rx_quick_consumer_index12, 5173 sblk->status_rx_quick_consumer_index13); 5174 5175 if (sblk->status_rx_quick_consumer_index14 || 5176 sblk->status_rx_quick_consumer_index15) 5177 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5178 sblk->status_rx_quick_consumer_index14, 5179 sblk->status_rx_quick_consumer_index15); 5180 5181 if (sblk->status_completion_producer_index || 5182 sblk->status_cmd_consumer_index) 5183 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5184 sblk->status_completion_producer_index, 5185 sblk->status_cmd_consumer_index); 5186 5187 BNX_PRINTF(sc, "-------------------------------------------" 5188 "-----------------------------\n"); 5189 } 5190 5191 /* 5192 * This routine prints the statistics block. 5193 */ 5194 void 5195 bnx_dump_stats_block(struct bnx_softc *sc) 5196 { 5197 struct statistics_block *sblk; 5198 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5199 BUS_DMASYNC_POSTREAD); 5200 5201 sblk = sc->stats_block; 5202 5203 BNX_PRINTF(sc, "" 5204 "-----------------------------" 5205 " Stats Block " 5206 "-----------------------------\n"); 5207 5208 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5209 "IfHcInBadOctets = 0x%08X:%08X\n", 5210 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5211 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5212 5213 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5214 "IfHcOutBadOctets = 0x%08X:%08X\n", 5215 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5216 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5217 5218 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5219 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5220 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5221 sblk->stat_IfHCInMulticastPkts_hi, 5222 sblk->stat_IfHCInMulticastPkts_lo); 5223 5224 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5225 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5226 sblk->stat_IfHCInBroadcastPkts_hi, 5227 sblk->stat_IfHCInBroadcastPkts_lo, 5228 sblk->stat_IfHCOutUcastPkts_hi, 5229 sblk->stat_IfHCOutUcastPkts_lo); 5230 5231 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5232 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5233 sblk->stat_IfHCOutMulticastPkts_hi, 5234 sblk->stat_IfHCOutMulticastPkts_lo, 5235 sblk->stat_IfHCOutBroadcastPkts_hi, 5236 sblk->stat_IfHCOutBroadcastPkts_lo); 5237 5238 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5239 BNX_PRINTF(sc, "0x%08X : " 5240 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5241 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5242 5243 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5244 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5245 sblk->stat_Dot3StatsCarrierSenseErrors); 5246 5247 if (sblk->stat_Dot3StatsFCSErrors) 5248 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5249 sblk->stat_Dot3StatsFCSErrors); 5250 5251 if (sblk->stat_Dot3StatsAlignmentErrors) 5252 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5253 sblk->stat_Dot3StatsAlignmentErrors); 5254 5255 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5256 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5257 sblk->stat_Dot3StatsSingleCollisionFrames); 5258 5259 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5260 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 5261 sblk->stat_Dot3StatsMultipleCollisionFrames); 5262 5263 if (sblk->stat_Dot3StatsDeferredTransmissions) 5264 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 5265 sblk->stat_Dot3StatsDeferredTransmissions); 5266 5267 if (sblk->stat_Dot3StatsExcessiveCollisions) 5268 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 5269 sblk->stat_Dot3StatsExcessiveCollisions); 5270 5271 if (sblk->stat_Dot3StatsLateCollisions) 5272 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 5273 sblk->stat_Dot3StatsLateCollisions); 5274 5275 if (sblk->stat_EtherStatsCollisions) 5276 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 5277 sblk->stat_EtherStatsCollisions); 5278 5279 if (sblk->stat_EtherStatsFragments) 5280 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 5281 sblk->stat_EtherStatsFragments); 5282 5283 if (sblk->stat_EtherStatsJabbers) 5284 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 5285 sblk->stat_EtherStatsJabbers); 5286 5287 if (sblk->stat_EtherStatsUndersizePkts) 5288 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 5289 sblk->stat_EtherStatsUndersizePkts); 5290 5291 if (sblk->stat_EtherStatsOverrsizePkts) 5292 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 5293 sblk->stat_EtherStatsOverrsizePkts); 5294 5295 if (sblk->stat_EtherStatsPktsRx64Octets) 5296 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 5297 sblk->stat_EtherStatsPktsRx64Octets); 5298 5299 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 5300 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 5301 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 5302 5303 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 5304 BNX_PRINTF(sc, "0x%08X : " 5305 "EtherStatsPktsRx128Octetsto255Octets\n", 5306 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 5307 5308 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 5309 BNX_PRINTF(sc, "0x%08X : " 5310 "EtherStatsPktsRx256Octetsto511Octets\n", 5311 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 5312 5313 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 5314 BNX_PRINTF(sc, "0x%08X : " 5315 "EtherStatsPktsRx512Octetsto1023Octets\n", 5316 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 5317 5318 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 5319 BNX_PRINTF(sc, "0x%08X : " 5320 "EtherStatsPktsRx1024Octetsto1522Octets\n", 5321 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 5322 5323 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 5324 BNX_PRINTF(sc, "0x%08X : " 5325 "EtherStatsPktsRx1523Octetsto9022Octets\n", 5326 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 5327 5328 if (sblk->stat_EtherStatsPktsTx64Octets) 5329 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 5330 sblk->stat_EtherStatsPktsTx64Octets); 5331 5332 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 5333 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 5334 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 5335 5336 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 5337 BNX_PRINTF(sc, "0x%08X : " 5338 "EtherStatsPktsTx128Octetsto255Octets\n", 5339 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 5340 5341 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 5342 BNX_PRINTF(sc, "0x%08X : " 5343 "EtherStatsPktsTx256Octetsto511Octets\n", 5344 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 5345 5346 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 5347 BNX_PRINTF(sc, "0x%08X : " 5348 "EtherStatsPktsTx512Octetsto1023Octets\n", 5349 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 5350 5351 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 5352 BNX_PRINTF(sc, "0x%08X : " 5353 "EtherStatsPktsTx1024Octetsto1522Octets\n", 5354 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 5355 5356 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 5357 BNX_PRINTF(sc, "0x%08X : " 5358 "EtherStatsPktsTx1523Octetsto9022Octets\n", 5359 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 5360 5361 if (sblk->stat_XonPauseFramesReceived) 5362 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 5363 sblk->stat_XonPauseFramesReceived); 5364 5365 if (sblk->stat_XoffPauseFramesReceived) 5366 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 5367 sblk->stat_XoffPauseFramesReceived); 5368 5369 if (sblk->stat_OutXonSent) 5370 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 5371 sblk->stat_OutXonSent); 5372 5373 if (sblk->stat_OutXoffSent) 5374 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 5375 sblk->stat_OutXoffSent); 5376 5377 if (sblk->stat_FlowControlDone) 5378 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 5379 sblk->stat_FlowControlDone); 5380 5381 if (sblk->stat_MacControlFramesReceived) 5382 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 5383 sblk->stat_MacControlFramesReceived); 5384 5385 if (sblk->stat_XoffStateEntered) 5386 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 5387 sblk->stat_XoffStateEntered); 5388 5389 if (sblk->stat_IfInFramesL2FilterDiscards) 5390 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 5391 sblk->stat_IfInFramesL2FilterDiscards); 5392 5393 if (sblk->stat_IfInRuleCheckerDiscards) 5394 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 5395 sblk->stat_IfInRuleCheckerDiscards); 5396 5397 if (sblk->stat_IfInFTQDiscards) 5398 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 5399 sblk->stat_IfInFTQDiscards); 5400 5401 if (sblk->stat_IfInMBUFDiscards) 5402 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 5403 sblk->stat_IfInMBUFDiscards); 5404 5405 if (sblk->stat_IfInRuleCheckerP4Hit) 5406 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 5407 sblk->stat_IfInRuleCheckerP4Hit); 5408 5409 if (sblk->stat_CatchupInRuleCheckerDiscards) 5410 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 5411 sblk->stat_CatchupInRuleCheckerDiscards); 5412 5413 if (sblk->stat_CatchupInFTQDiscards) 5414 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 5415 sblk->stat_CatchupInFTQDiscards); 5416 5417 if (sblk->stat_CatchupInMBUFDiscards) 5418 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 5419 sblk->stat_CatchupInMBUFDiscards); 5420 5421 if (sblk->stat_CatchupInRuleCheckerP4Hit) 5422 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 5423 sblk->stat_CatchupInRuleCheckerP4Hit); 5424 5425 BNX_PRINTF(sc, 5426 "-----------------------------" 5427 "--------------" 5428 "-----------------------------\n"); 5429 } 5430 5431 void 5432 bnx_dump_driver_state(struct bnx_softc *sc) 5433 { 5434 BNX_PRINTF(sc, 5435 "-----------------------------" 5436 " Driver State " 5437 "-----------------------------\n"); 5438 5439 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 5440 "address\n", sc); 5441 5442 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 5443 sc->status_block); 5444 5445 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 5446 "address\n", sc->stats_block); 5447 5448 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 5449 "adddress\n", sc->tx_bd_chain); 5450 5451 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 5452 sc->rx_bd_chain); 5453 5454 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 5455 sc->tx_mbuf_ptr); 5456 5457 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 5458 sc->rx_mbuf_ptr); 5459 5460 BNX_PRINTF(sc, 5461 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 5462 sc->interrupts_generated); 5463 5464 BNX_PRINTF(sc, 5465 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 5466 sc->rx_interrupts); 5467 5468 BNX_PRINTF(sc, 5469 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 5470 sc->tx_interrupts); 5471 5472 BNX_PRINTF(sc, 5473 " 0x%08X - (sc->last_status_idx) status block index\n", 5474 sc->last_status_idx); 5475 5476 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 5477 sc->tx_prod); 5478 5479 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 5480 sc->tx_cons); 5481 5482 BNX_PRINTF(sc, 5483 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 5484 sc->tx_prod_bseq); 5485 5486 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 5487 sc->rx_prod); 5488 5489 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 5490 sc->rx_cons); 5491 5492 BNX_PRINTF(sc, 5493 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 5494 sc->rx_prod_bseq); 5495 5496 BNX_PRINTF(sc, 5497 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5498 sc->rx_mbuf_alloc); 5499 5500 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 5501 sc->free_rx_bd); 5502 5503 BNX_PRINTF(sc, 5504 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 5505 sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD); 5506 5507 BNX_PRINTF(sc, 5508 " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 5509 sc->tx_mbuf_alloc); 5510 5511 BNX_PRINTF(sc, 5512 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5513 sc->rx_mbuf_alloc); 5514 5515 BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 5516 sc->used_tx_bd); 5517 5518 BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 5519 sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD); 5520 5521 BNX_PRINTF(sc, 5522 " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 5523 sc->mbuf_alloc_failed); 5524 5525 BNX_PRINTF(sc, "-------------------------------------------" 5526 "-----------------------------\n"); 5527 } 5528 5529 void 5530 bnx_dump_hw_state(struct bnx_softc *sc) 5531 { 5532 u_int32_t val1; 5533 int i; 5534 5535 BNX_PRINTF(sc, 5536 "----------------------------" 5537 " Hardware State " 5538 "----------------------------\n"); 5539 5540 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 5541 5542 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 5543 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 5544 val1, BNX_MISC_ENABLE_STATUS_BITS); 5545 5546 val1 = REG_RD(sc, BNX_DMA_STATUS); 5547 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 5548 5549 val1 = REG_RD(sc, BNX_CTX_STATUS); 5550 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 5551 5552 val1 = REG_RD(sc, BNX_EMAC_STATUS); 5553 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 5554 BNX_EMAC_STATUS); 5555 5556 val1 = REG_RD(sc, BNX_RPM_STATUS); 5557 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 5558 5559 val1 = REG_RD(sc, BNX_TBDR_STATUS); 5560 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 5561 BNX_TBDR_STATUS); 5562 5563 val1 = REG_RD(sc, BNX_TDMA_STATUS); 5564 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 5565 BNX_TDMA_STATUS); 5566 5567 val1 = REG_RD(sc, BNX_HC_STATUS); 5568 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 5569 5570 BNX_PRINTF(sc, 5571 "----------------------------" 5572 "----------------" 5573 "----------------------------\n"); 5574 5575 BNX_PRINTF(sc, 5576 "----------------------------" 5577 " Register Dump " 5578 "----------------------------\n"); 5579 5580 for (i = 0x400; i < 0x8000; i += 0x10) 5581 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 5582 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 5583 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 5584 5585 BNX_PRINTF(sc, 5586 "----------------------------" 5587 "----------------" 5588 "----------------------------\n"); 5589 } 5590 5591 void 5592 bnx_breakpoint(struct bnx_softc *sc) 5593 { 5594 /* Unreachable code to shut the compiler up about unused functions. */ 5595 if (0) { 5596 bnx_dump_txbd(sc, 0, NULL); 5597 bnx_dump_rxbd(sc, 0, NULL); 5598 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 5599 bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 5600 bnx_dump_l2fhdr(sc, 0, NULL); 5601 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 5602 bnx_dump_rx_chain(sc, 0, USABLE_RX_BD); 5603 bnx_dump_status_block(sc); 5604 bnx_dump_stats_block(sc); 5605 bnx_dump_driver_state(sc); 5606 bnx_dump_hw_state(sc); 5607 } 5608 5609 bnx_dump_driver_state(sc); 5610 /* Print the important status block fields. */ 5611 bnx_dump_status_block(sc); 5612 5613 #if 0 5614 /* Call the debugger. */ 5615 breakpoint(); 5616 #endif 5617 5618 return; 5619 } 5620 #endif 5621
Indexes created Mon Sep 22 21:09:42 GMT 2025