if_bnx.c revision 1.36
1 /* $NetBSD: if_bnx.c,v 1.36 2010/12/09 22:34:37 jym Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.36 2010/12/09 22:34:37 jym Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5716 C0 48 * 49 * The following controllers are not supported by this driver: 50 * 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, A1, B0, B1, B2, C0 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 /****************************************************************************/ 180 /* Supported Flash NVRAM device data. */ 181 /****************************************************************************/ 182 static struct flash_spec flash_table[] = 183 { 184 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 185 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 186 /* Slow EEPROM */ 187 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 188 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 189 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 190 "EEPROM - slow"}, 191 /* Expansion entry 0001 */ 192 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0001"}, 196 /* Saifun SA25F010 (non-buffered flash) */ 197 /* strap, cfg1, & write1 need updates */ 198 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 201 "Non-buffered flash (128kB)"}, 202 /* Saifun SA25F020 (non-buffered flash) */ 203 /* strap, cfg1, & write1 need updates */ 204 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 205 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 206 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 207 "Non-buffered flash (256kB)"}, 208 /* Expansion entry 0100 */ 209 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 210 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 211 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 212 "Entry 0100"}, 213 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 214 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 216 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 217 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 218 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 219 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 221 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 222 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 223 /* Saifun SA25F005 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 228 "Non-buffered flash (64kB)"}, 229 /* Fast EEPROM */ 230 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 231 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 232 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 233 "EEPROM - fast"}, 234 /* Expansion entry 1001 */ 235 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 236 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 237 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 238 "Entry 1001"}, 239 /* Expansion entry 1010 */ 240 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 241 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 242 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 243 "Entry 1010"}, 244 /* ATMEL AT45DB011B (buffered flash) */ 245 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 246 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 247 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 248 "Buffered flash (128kB)"}, 249 /* Expansion entry 1100 */ 250 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 251 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 252 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 253 "Entry 1100"}, 254 /* Expansion entry 1101 */ 255 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 256 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 257 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 258 "Entry 1101"}, 259 /* Ateml Expansion entry 1110 */ 260 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 261 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 262 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 263 "Entry 1110 (Atmel)"}, 264 /* ATMEL AT45DB021B (buffered flash) */ 265 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 266 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 267 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 268 "Buffered flash (256kB)"}, 269 }; 270 271 /* 272 * The BCM5709 controllers transparently handle the 273 * differences between Atmel 264 byte pages and all 274 * flash devices which use 256 byte pages, so no 275 * logical-to-physical mapping is required in the 276 * driver. 277 */ 278 static struct flash_spec flash_5709 = { 279 .flags = BNX_NV_BUFFERED, 280 .page_bits = BCM5709_FLASH_PAGE_BITS, 281 .page_size = BCM5709_FLASH_PAGE_SIZE, 282 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 283 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 284 .name = "5709 buffered flash (256kB)", 285 }; 286 287 /****************************************************************************/ 288 /* OpenBSD device entry points. */ 289 /****************************************************************************/ 290 static int bnx_probe(device_t, cfdata_t, void *); 291 void bnx_attach(device_t, device_t, void *); 292 int bnx_detach(device_t, int); 293 294 /****************************************************************************/ 295 /* BNX Debug Data Structure Dump Routines */ 296 /****************************************************************************/ 297 #ifdef BNX_DEBUG 298 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 299 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 300 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 302 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 303 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 304 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 305 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_status_block(struct bnx_softc *); 307 void bnx_dump_stats_block(struct bnx_softc *); 308 void bnx_dump_driver_state(struct bnx_softc *); 309 void bnx_dump_hw_state(struct bnx_softc *); 310 void bnx_breakpoint(struct bnx_softc *); 311 #endif 312 313 /****************************************************************************/ 314 /* BNX Register/Memory Access Routines */ 315 /****************************************************************************/ 316 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 317 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 318 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 319 int bnx_miibus_read_reg(device_t, int, int); 320 void bnx_miibus_write_reg(device_t, int, int, int); 321 void bnx_miibus_statchg(device_t); 322 323 /****************************************************************************/ 324 /* BNX NVRAM Access Routines */ 325 /****************************************************************************/ 326 int bnx_acquire_nvram_lock(struct bnx_softc *); 327 int bnx_release_nvram_lock(struct bnx_softc *); 328 void bnx_enable_nvram_access(struct bnx_softc *); 329 void bnx_disable_nvram_access(struct bnx_softc *); 330 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 331 u_int32_t); 332 int bnx_init_nvram(struct bnx_softc *); 333 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 334 int bnx_nvram_test(struct bnx_softc *); 335 #ifdef BNX_NVRAM_WRITE_SUPPORT 336 int bnx_enable_nvram_write(struct bnx_softc *); 337 void bnx_disable_nvram_write(struct bnx_softc *); 338 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 339 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 340 u_int32_t); 341 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 342 #endif 343 344 /****************************************************************************/ 345 /* */ 346 /****************************************************************************/ 347 void bnx_get_media(struct bnx_softc *); 348 int bnx_dma_alloc(struct bnx_softc *); 349 void bnx_dma_free(struct bnx_softc *); 350 void bnx_release_resources(struct bnx_softc *); 351 352 /****************************************************************************/ 353 /* BNX Firmware Synchronization and Load */ 354 /****************************************************************************/ 355 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 356 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 357 u_int32_t); 358 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 359 struct fw_info *); 360 void bnx_init_cpus(struct bnx_softc *); 361 362 void bnx_stop(struct ifnet *, int); 363 int bnx_reset(struct bnx_softc *, u_int32_t); 364 int bnx_chipinit(struct bnx_softc *); 365 int bnx_blockinit(struct bnx_softc *); 366 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 367 u_int16_t *, u_int32_t *); 368 int bnx_get_buf(struct bnx_softc *, u_int16_t *, u_int16_t *, u_int32_t *); 369 370 int bnx_init_tx_chain(struct bnx_softc *); 371 void bnx_init_tx_context(struct bnx_softc *); 372 int bnx_init_rx_chain(struct bnx_softc *); 373 void bnx_init_rx_context(struct bnx_softc *); 374 void bnx_free_rx_chain(struct bnx_softc *); 375 void bnx_free_tx_chain(struct bnx_softc *); 376 377 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 378 void bnx_start(struct ifnet *); 379 int bnx_ioctl(struct ifnet *, u_long, void *); 380 void bnx_watchdog(struct ifnet *); 381 int bnx_init(struct ifnet *); 382 383 void bnx_init_context(struct bnx_softc *); 384 void bnx_get_mac_addr(struct bnx_softc *); 385 void bnx_set_mac_addr(struct bnx_softc *); 386 void bnx_phy_intr(struct bnx_softc *); 387 void bnx_rx_intr(struct bnx_softc *); 388 void bnx_tx_intr(struct bnx_softc *); 389 void bnx_disable_intr(struct bnx_softc *); 390 void bnx_enable_intr(struct bnx_softc *); 391 392 int bnx_intr(void *); 393 void bnx_iff(struct bnx_softc *); 394 void bnx_stats_update(struct bnx_softc *); 395 void bnx_tick(void *); 396 397 struct pool *bnx_tx_pool = NULL; 398 int bnx_alloc_pkts(struct bnx_softc *); 399 400 /****************************************************************************/ 401 /* OpenBSD device dispatch table. */ 402 /****************************************************************************/ 403 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 404 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 405 406 /****************************************************************************/ 407 /* Device probe function. */ 408 /* */ 409 /* Compares the device to the driver's list of supported devices and */ 410 /* reports back to the OS whether this is the right driver for the device. */ 411 /* */ 412 /* Returns: */ 413 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 414 /****************************************************************************/ 415 static const struct bnx_product * 416 bnx_lookup(const struct pci_attach_args *pa) 417 { 418 int i; 419 pcireg_t subid; 420 421 for (i = 0; i < __arraycount(bnx_devices); i++) { 422 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 423 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 424 continue; 425 if (!bnx_devices[i].bp_subvendor) 426 return &bnx_devices[i]; 427 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 428 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 429 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 430 return &bnx_devices[i]; 431 } 432 433 return NULL; 434 } 435 static int 436 bnx_probe(device_t parent, cfdata_t match, void *aux) 437 { 438 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 439 440 if (bnx_lookup(pa) != NULL) 441 return (1); 442 443 return (0); 444 } 445 446 /****************************************************************************/ 447 /* Device attach function. */ 448 /* */ 449 /* Allocates device resources, performs secondary chip identification, */ 450 /* resets and initializes the hardware, and initializes driver instance */ 451 /* variables. */ 452 /* */ 453 /* Returns: */ 454 /* 0 on success, positive value on failure. */ 455 /****************************************************************************/ 456 void 457 bnx_attach(device_t parent, device_t self, void *aux) 458 { 459 const struct bnx_product *bp; 460 struct bnx_softc *sc = device_private(self); 461 struct pci_attach_args *pa = aux; 462 pci_chipset_tag_t pc = pa->pa_pc; 463 pci_intr_handle_t ih; 464 const char *intrstr = NULL; 465 u_int32_t command; 466 struct ifnet *ifp; 467 u_int32_t val; 468 int mii_flags = MIIF_FORCEANEG; 469 pcireg_t memtype; 470 471 if (bnx_tx_pool == NULL) { 472 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 473 if (bnx_tx_pool != NULL) { 474 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 475 0, 0, 0, "bnxpkts", NULL, IPL_NET); 476 } else { 477 aprint_error(": can't alloc bnx_tx_pool\n"); 478 return; 479 } 480 } 481 482 bp = bnx_lookup(pa); 483 if (bp == NULL) 484 panic("unknown device"); 485 486 sc->bnx_dev = self; 487 488 aprint_naive("\n"); 489 aprint_normal(": %s\n", bp->bp_name); 490 491 sc->bnx_pa = *pa; 492 493 /* 494 * Map control/status registers. 495 */ 496 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 497 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 498 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 499 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 501 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 502 aprint_error_dev(sc->bnx_dev, 503 "failed to enable memory mapping!\n"); 504 return; 505 } 506 507 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 508 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 509 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 510 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 511 return; 512 } 513 514 if (pci_intr_map(pa, &ih)) { 515 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 516 goto bnx_attach_fail; 517 } 518 519 intrstr = pci_intr_string(pc, ih); 520 521 /* 522 * Configure byte swap and enable indirect register access. 523 * Rely on CPU to do target byte swapping on big endian systems. 524 * Access to registers outside of PCI configurtion space are not 525 * valid until this is done. 526 */ 527 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 528 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 529 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 530 531 /* Save ASIC revsion info. */ 532 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 533 534 /* 535 * Find the base address for shared memory access. 536 * Newer versions of bootcode use a signature and offset 537 * while older versions use a fixed address. 538 */ 539 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 540 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 541 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 542 (sc->bnx_pa.pa_function << 2)); 543 else 544 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 545 546 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 547 548 /* Set initial device and PHY flags */ 549 sc->bnx_flags = 0; 550 sc->bnx_phy_flags = 0; 551 552 /* Get PCI bus information (speed and type). */ 553 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 554 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 555 u_int32_t clkreg; 556 557 sc->bnx_flags |= BNX_PCIX_FLAG; 558 559 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 560 561 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 562 switch (clkreg) { 563 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 564 sc->bus_speed_mhz = 133; 565 break; 566 567 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 568 sc->bus_speed_mhz = 100; 569 break; 570 571 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 572 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 573 sc->bus_speed_mhz = 66; 574 break; 575 576 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 577 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 578 sc->bus_speed_mhz = 50; 579 break; 580 581 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 582 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 583 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 584 sc->bus_speed_mhz = 33; 585 break; 586 } 587 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 588 sc->bus_speed_mhz = 66; 589 else 590 sc->bus_speed_mhz = 33; 591 592 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 593 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 594 595 /* Reset the controller. */ 596 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 597 goto bnx_attach_fail; 598 599 /* Initialize the controller. */ 600 if (bnx_chipinit(sc)) { 601 aprint_error_dev(sc->bnx_dev, 602 "Controller initialization failed!\n"); 603 goto bnx_attach_fail; 604 } 605 606 /* Perform NVRAM test. */ 607 if (bnx_nvram_test(sc)) { 608 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 609 goto bnx_attach_fail; 610 } 611 612 /* Fetch the permanent Ethernet MAC address. */ 613 bnx_get_mac_addr(sc); 614 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 615 ether_sprintf(sc->eaddr)); 616 617 /* 618 * Trip points control how many BDs 619 * should be ready before generating an 620 * interrupt while ticks control how long 621 * a BD can sit in the chain before 622 * generating an interrupt. Set the default 623 * values for the RX and TX rings. 624 */ 625 626 #ifdef BNX_DEBUG 627 /* Force more frequent interrupts. */ 628 sc->bnx_tx_quick_cons_trip_int = 1; 629 sc->bnx_tx_quick_cons_trip = 1; 630 sc->bnx_tx_ticks_int = 0; 631 sc->bnx_tx_ticks = 0; 632 633 sc->bnx_rx_quick_cons_trip_int = 1; 634 sc->bnx_rx_quick_cons_trip = 1; 635 sc->bnx_rx_ticks_int = 0; 636 sc->bnx_rx_ticks = 0; 637 #else 638 sc->bnx_tx_quick_cons_trip_int = 20; 639 sc->bnx_tx_quick_cons_trip = 20; 640 sc->bnx_tx_ticks_int = 80; 641 sc->bnx_tx_ticks = 80; 642 643 sc->bnx_rx_quick_cons_trip_int = 6; 644 sc->bnx_rx_quick_cons_trip = 6; 645 sc->bnx_rx_ticks_int = 18; 646 sc->bnx_rx_ticks = 18; 647 #endif 648 649 /* Update statistics once every second. */ 650 sc->bnx_stats_ticks = 1000000 & 0xffff00; 651 652 /* Find the media type for the adapter. */ 653 bnx_get_media(sc); 654 655 /* 656 * Store config data needed by the PHY driver for 657 * backplane applications 658 */ 659 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 660 BNX_SHARED_HW_CFG_CONFIG); 661 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 662 BNX_PORT_HW_CFG_CONFIG); 663 664 /* Allocate DMA memory resources. */ 665 sc->bnx_dmatag = pa->pa_dmat; 666 if (bnx_dma_alloc(sc)) { 667 aprint_error_dev(sc->bnx_dev, 668 "DMA resource allocation failed!\n"); 669 goto bnx_attach_fail; 670 } 671 672 /* Initialize the ifnet interface. */ 673 ifp = &sc->bnx_ec.ec_if; 674 ifp->if_softc = sc; 675 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 676 ifp->if_ioctl = bnx_ioctl; 677 ifp->if_stop = bnx_stop; 678 ifp->if_start = bnx_start; 679 ifp->if_init = bnx_init; 680 ifp->if_timer = 0; 681 ifp->if_watchdog = bnx_watchdog; 682 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 683 IFQ_SET_READY(&ifp->if_snd); 684 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 685 686 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 687 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 688 689 ifp->if_capabilities |= 690 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 691 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 692 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 693 694 /* Hookup IRQ last. */ 695 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 696 if (sc->bnx_intrhand == NULL) { 697 aprint_error_dev(self, "couldn't establish interrupt"); 698 if (intrstr != NULL) 699 aprint_error(" at %s", intrstr); 700 aprint_error("\n"); 701 goto bnx_attach_fail; 702 } 703 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 704 705 sc->bnx_mii.mii_ifp = ifp; 706 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 707 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 708 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 709 710 sc->bnx_ec.ec_mii = &sc->bnx_mii; 711 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 712 ether_mediastatus); 713 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 714 mii_flags |= MIIF_HAVEFIBER; 715 mii_attach(self, &sc->bnx_mii, 0xffffffff, 716 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 717 718 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 719 aprint_error_dev(self, "no PHY found!\n"); 720 ifmedia_add(&sc->bnx_mii.mii_media, 721 IFM_ETHER|IFM_MANUAL, 0, NULL); 722 ifmedia_set(&sc->bnx_mii.mii_media, 723 IFM_ETHER|IFM_MANUAL); 724 } else { 725 ifmedia_set(&sc->bnx_mii.mii_media, 726 IFM_ETHER|IFM_AUTO); 727 } 728 729 /* Attach to the Ethernet interface list. */ 730 if_attach(ifp); 731 ether_ifattach(ifp,sc->eaddr); 732 733 callout_init(&sc->bnx_timeout, 0); 734 735 if (pmf_device_register(self, NULL, NULL)) 736 pmf_class_network_register(self, ifp); 737 else 738 aprint_error_dev(self, "couldn't establish power handler\n"); 739 740 /* Print some important debugging info. */ 741 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 742 743 goto bnx_attach_exit; 744 745 bnx_attach_fail: 746 bnx_release_resources(sc); 747 748 bnx_attach_exit: 749 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 750 } 751 752 /****************************************************************************/ 753 /* Device detach function. */ 754 /* */ 755 /* Stops the controller, resets the controller, and releases resources. */ 756 /* */ 757 /* Returns: */ 758 /* 0 on success, positive value on failure. */ 759 /****************************************************************************/ 760 int 761 bnx_detach(device_t dev, int flags) 762 { 763 int s; 764 struct bnx_softc *sc; 765 struct ifnet *ifp; 766 767 sc = device_private(dev); 768 ifp = &sc->bnx_ec.ec_if; 769 770 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 771 772 /* Stop and reset the controller. */ 773 s = splnet(); 774 if (ifp->if_flags & IFF_RUNNING) 775 bnx_stop(ifp, 1); 776 else { 777 /* Disable the transmit/receive blocks. */ 778 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 779 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 780 DELAY(20); 781 bnx_disable_intr(sc); 782 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 783 } 784 785 splx(s); 786 787 pmf_device_deregister(dev); 788 callout_destroy(&sc->bnx_timeout); 789 ether_ifdetach(ifp); 790 791 /* Delete all remaining media. */ 792 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 793 794 if_detach(ifp); 795 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 796 797 /* Release all remaining resources. */ 798 bnx_release_resources(sc); 799 800 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 801 802 return(0); 803 } 804 805 /****************************************************************************/ 806 /* Indirect register read. */ 807 /* */ 808 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 809 /* configuration space. Using this mechanism avoids issues with posted */ 810 /* reads but is much slower than memory-mapped I/O. */ 811 /* */ 812 /* Returns: */ 813 /* The value of the register. */ 814 /****************************************************************************/ 815 u_int32_t 816 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 817 { 818 struct pci_attach_args *pa = &(sc->bnx_pa); 819 820 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 821 offset); 822 #ifdef BNX_DEBUG 823 { 824 u_int32_t val; 825 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 826 BNX_PCICFG_REG_WINDOW); 827 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 828 "val = 0x%08X\n", __func__, offset, val); 829 return (val); 830 } 831 #else 832 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 833 #endif 834 } 835 836 /****************************************************************************/ 837 /* Indirect register write. */ 838 /* */ 839 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 840 /* configuration space. Using this mechanism avoids issues with posted */ 841 /* writes but is muchh slower than memory-mapped I/O. */ 842 /* */ 843 /* Returns: */ 844 /* Nothing. */ 845 /****************************************************************************/ 846 void 847 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 848 { 849 struct pci_attach_args *pa = &(sc->bnx_pa); 850 851 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 852 __func__, offset, val); 853 854 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 855 offset); 856 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 857 } 858 859 /****************************************************************************/ 860 /* Context memory write. */ 861 /* */ 862 /* The NetXtreme II controller uses context memory to track connection */ 863 /* information for L2 and higher network protocols. */ 864 /* */ 865 /* Returns: */ 866 /* Nothing. */ 867 /****************************************************************************/ 868 void 869 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t ctx_offset, 870 u_int32_t ctx_val) 871 { 872 u_int32_t idx, offset = ctx_offset + cid_addr; 873 u_int32_t val, retry_cnt = 5; 874 875 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 876 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 877 REG_WR(sc, BNX_CTX_CTX_CTRL, 878 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 879 880 for (idx = 0; idx < retry_cnt; idx++) { 881 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 882 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 883 break; 884 DELAY(5); 885 } 886 887 #if 0 888 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 889 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 890 "cid_addr = 0x%08X, offset = 0x%08X!\n", 891 __FILE__, __LINE__, cid_addr, ctx_offset); 892 #endif 893 894 } else { 895 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 896 REG_WR(sc, BNX_CTX_DATA, ctx_val); 897 } 898 } 899 900 /****************************************************************************/ 901 /* PHY register read. */ 902 /* */ 903 /* Implements register reads on the MII bus. */ 904 /* */ 905 /* Returns: */ 906 /* The value of the register. */ 907 /****************************************************************************/ 908 int 909 bnx_miibus_read_reg(device_t dev, int phy, int reg) 910 { 911 struct bnx_softc *sc = device_private(dev); 912 u_int32_t val; 913 int i; 914 915 /* Make sure we are accessing the correct PHY address. */ 916 if (phy != sc->bnx_phy_addr) { 917 DBPRINT(sc, BNX_VERBOSE, 918 "Invalid PHY address %d for PHY read!\n", phy); 919 return(0); 920 } 921 922 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 923 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 924 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 925 926 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 927 REG_RD(sc, BNX_EMAC_MDIO_MODE); 928 929 DELAY(40); 930 } 931 932 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 933 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 934 BNX_EMAC_MDIO_COMM_START_BUSY; 935 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 936 937 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 938 DELAY(10); 939 940 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 941 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 942 DELAY(5); 943 944 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 945 val &= BNX_EMAC_MDIO_COMM_DATA; 946 947 break; 948 } 949 } 950 951 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 952 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 953 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 954 val = 0x0; 955 } else 956 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 957 958 DBPRINT(sc, BNX_EXCESSIVE, 959 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 960 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 961 962 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 963 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 964 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 965 966 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 967 REG_RD(sc, BNX_EMAC_MDIO_MODE); 968 969 DELAY(40); 970 } 971 972 return (val & 0xffff); 973 } 974 975 /****************************************************************************/ 976 /* PHY register write. */ 977 /* */ 978 /* Implements register writes on the MII bus. */ 979 /* */ 980 /* Returns: */ 981 /* The value of the register. */ 982 /****************************************************************************/ 983 void 984 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 985 { 986 struct bnx_softc *sc = device_private(dev); 987 u_int32_t val1; 988 int i; 989 990 /* Make sure we are accessing the correct PHY address. */ 991 if (phy != sc->bnx_phy_addr) { 992 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 993 phy); 994 return; 995 } 996 997 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 998 "val = 0x%04X\n", __func__, 999 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 1000 1001 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1002 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1003 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1004 1005 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1006 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1007 1008 DELAY(40); 1009 } 1010 1011 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1012 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1013 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1014 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1015 1016 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1017 DELAY(10); 1018 1019 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1020 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1021 DELAY(5); 1022 break; 1023 } 1024 } 1025 1026 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1027 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1028 __LINE__); 1029 } 1030 1031 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1032 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1033 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1034 1035 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1036 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1037 1038 DELAY(40); 1039 } 1040 } 1041 1042 /****************************************************************************/ 1043 /* MII bus status change. */ 1044 /* */ 1045 /* Called by the MII bus driver when the PHY establishes link to set the */ 1046 /* MAC interface registers. */ 1047 /* */ 1048 /* Returns: */ 1049 /* Nothing. */ 1050 /****************************************************************************/ 1051 void 1052 bnx_miibus_statchg(device_t dev) 1053 { 1054 struct bnx_softc *sc = device_private(dev); 1055 struct mii_data *mii = &sc->bnx_mii; 1056 int val; 1057 1058 val = REG_RD(sc, BNX_EMAC_MODE); 1059 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1060 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1061 BNX_EMAC_MODE_25G); 1062 1063 /* Set MII or GMII interface based on the speed 1064 * negotiated by the PHY. 1065 */ 1066 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1067 case IFM_10_T: 1068 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1069 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1070 val |= BNX_EMAC_MODE_PORT_MII_10; 1071 break; 1072 } 1073 /* FALLTHROUGH */ 1074 case IFM_100_TX: 1075 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1076 val |= BNX_EMAC_MODE_PORT_MII; 1077 break; 1078 case IFM_2500_SX: 1079 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1080 val |= BNX_EMAC_MODE_25G; 1081 /* FALLTHROUGH */ 1082 case IFM_1000_T: 1083 case IFM_1000_SX: 1084 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1085 val |= BNX_EMAC_MODE_PORT_GMII; 1086 break; 1087 default: 1088 val |= BNX_EMAC_MODE_PORT_GMII; 1089 break; 1090 } 1091 1092 /* Set half or full duplex based on the duplicity 1093 * negotiated by the PHY. 1094 */ 1095 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1096 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1097 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1098 } else { 1099 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1100 } 1101 1102 REG_WR(sc, BNX_EMAC_MODE, val); 1103 } 1104 1105 /****************************************************************************/ 1106 /* Acquire NVRAM lock. */ 1107 /* */ 1108 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1109 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1110 /* for use by the driver. */ 1111 /* */ 1112 /* Returns: */ 1113 /* 0 on success, positive value on failure. */ 1114 /****************************************************************************/ 1115 int 1116 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1117 { 1118 u_int32_t val; 1119 int j; 1120 1121 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1122 1123 /* Request access to the flash interface. */ 1124 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1125 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1126 val = REG_RD(sc, BNX_NVM_SW_ARB); 1127 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1128 break; 1129 1130 DELAY(5); 1131 } 1132 1133 if (j >= NVRAM_TIMEOUT_COUNT) { 1134 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1135 return (EBUSY); 1136 } 1137 1138 return (0); 1139 } 1140 1141 /****************************************************************************/ 1142 /* Release NVRAM lock. */ 1143 /* */ 1144 /* When the caller is finished accessing NVRAM the lock must be released. */ 1145 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1146 /* for use by the driver. */ 1147 /* */ 1148 /* Returns: */ 1149 /* 0 on success, positive value on failure. */ 1150 /****************************************************************************/ 1151 int 1152 bnx_release_nvram_lock(struct bnx_softc *sc) 1153 { 1154 int j; 1155 u_int32_t val; 1156 1157 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1158 1159 /* Relinquish nvram interface. */ 1160 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1161 1162 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1163 val = REG_RD(sc, BNX_NVM_SW_ARB); 1164 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1165 break; 1166 1167 DELAY(5); 1168 } 1169 1170 if (j >= NVRAM_TIMEOUT_COUNT) { 1171 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1172 return (EBUSY); 1173 } 1174 1175 return (0); 1176 } 1177 1178 #ifdef BNX_NVRAM_WRITE_SUPPORT 1179 /****************************************************************************/ 1180 /* Enable NVRAM write access. */ 1181 /* */ 1182 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1183 /* */ 1184 /* Returns: */ 1185 /* 0 on success, positive value on failure. */ 1186 /****************************************************************************/ 1187 int 1188 bnx_enable_nvram_write(struct bnx_softc *sc) 1189 { 1190 u_int32_t val; 1191 1192 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1193 1194 val = REG_RD(sc, BNX_MISC_CFG); 1195 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1196 1197 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1198 int j; 1199 1200 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1201 REG_WR(sc, BNX_NVM_COMMAND, 1202 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1203 1204 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1205 DELAY(5); 1206 1207 val = REG_RD(sc, BNX_NVM_COMMAND); 1208 if (val & BNX_NVM_COMMAND_DONE) 1209 break; 1210 } 1211 1212 if (j >= NVRAM_TIMEOUT_COUNT) { 1213 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1214 return (EBUSY); 1215 } 1216 } 1217 1218 return (0); 1219 } 1220 1221 /****************************************************************************/ 1222 /* Disable NVRAM write access. */ 1223 /* */ 1224 /* When the caller is finished writing to NVRAM write access must be */ 1225 /* disabled. */ 1226 /* */ 1227 /* Returns: */ 1228 /* Nothing. */ 1229 /****************************************************************************/ 1230 void 1231 bnx_disable_nvram_write(struct bnx_softc *sc) 1232 { 1233 u_int32_t val; 1234 1235 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1236 1237 val = REG_RD(sc, BNX_MISC_CFG); 1238 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1239 } 1240 #endif 1241 1242 /****************************************************************************/ 1243 /* Enable NVRAM access. */ 1244 /* */ 1245 /* Before accessing NVRAM for read or write operations the caller must */ 1246 /* enabled NVRAM access. */ 1247 /* */ 1248 /* Returns: */ 1249 /* Nothing. */ 1250 /****************************************************************************/ 1251 void 1252 bnx_enable_nvram_access(struct bnx_softc *sc) 1253 { 1254 u_int32_t val; 1255 1256 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1257 1258 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1259 /* Enable both bits, even on read. */ 1260 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1261 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1262 } 1263 1264 /****************************************************************************/ 1265 /* Disable NVRAM access. */ 1266 /* */ 1267 /* When the caller is finished accessing NVRAM access must be disabled. */ 1268 /* */ 1269 /* Returns: */ 1270 /* Nothing. */ 1271 /****************************************************************************/ 1272 void 1273 bnx_disable_nvram_access(struct bnx_softc *sc) 1274 { 1275 u_int32_t val; 1276 1277 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1278 1279 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1280 1281 /* Disable both bits, even after read. */ 1282 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1283 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1284 } 1285 1286 #ifdef BNX_NVRAM_WRITE_SUPPORT 1287 /****************************************************************************/ 1288 /* Erase NVRAM page before writing. */ 1289 /* */ 1290 /* Non-buffered flash parts require that a page be erased before it is */ 1291 /* written. */ 1292 /* */ 1293 /* Returns: */ 1294 /* 0 on success, positive value on failure. */ 1295 /****************************************************************************/ 1296 int 1297 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1298 { 1299 u_int32_t cmd; 1300 int j; 1301 1302 /* Buffered flash doesn't require an erase. */ 1303 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1304 return (0); 1305 1306 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1307 1308 /* Build an erase command. */ 1309 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1310 BNX_NVM_COMMAND_DOIT; 1311 1312 /* 1313 * Clear the DONE bit separately, set the NVRAM adress to erase, 1314 * and issue the erase command. 1315 */ 1316 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1317 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1318 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1319 1320 /* Wait for completion. */ 1321 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1322 u_int32_t val; 1323 1324 DELAY(5); 1325 1326 val = REG_RD(sc, BNX_NVM_COMMAND); 1327 if (val & BNX_NVM_COMMAND_DONE) 1328 break; 1329 } 1330 1331 if (j >= NVRAM_TIMEOUT_COUNT) { 1332 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1333 return (EBUSY); 1334 } 1335 1336 return (0); 1337 } 1338 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1339 1340 /****************************************************************************/ 1341 /* Read a dword (32 bits) from NVRAM. */ 1342 /* */ 1343 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1344 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1345 /* */ 1346 /* Returns: */ 1347 /* 0 on success and the 32 bit value read, positive value on failure. */ 1348 /****************************************************************************/ 1349 int 1350 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1351 u_int8_t *ret_val, u_int32_t cmd_flags) 1352 { 1353 u_int32_t cmd; 1354 int i, rc = 0; 1355 1356 /* Build the command word. */ 1357 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1358 1359 /* Calculate the offset for buffered flash if translation is used. */ 1360 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1361 offset = ((offset / sc->bnx_flash_info->page_size) << 1362 sc->bnx_flash_info->page_bits) + 1363 (offset % sc->bnx_flash_info->page_size); 1364 } 1365 1366 /* 1367 * Clear the DONE bit separately, set the address to read, 1368 * and issue the read. 1369 */ 1370 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1371 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1372 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1373 1374 /* Wait for completion. */ 1375 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1376 u_int32_t val; 1377 1378 DELAY(5); 1379 1380 val = REG_RD(sc, BNX_NVM_COMMAND); 1381 if (val & BNX_NVM_COMMAND_DONE) { 1382 val = REG_RD(sc, BNX_NVM_READ); 1383 1384 val = bnx_be32toh(val); 1385 memcpy(ret_val, &val, 4); 1386 break; 1387 } 1388 } 1389 1390 /* Check for errors. */ 1391 if (i >= NVRAM_TIMEOUT_COUNT) { 1392 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1393 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1394 rc = EBUSY; 1395 } 1396 1397 return(rc); 1398 } 1399 1400 #ifdef BNX_NVRAM_WRITE_SUPPORT 1401 /****************************************************************************/ 1402 /* Write a dword (32 bits) to NVRAM. */ 1403 /* */ 1404 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1405 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1406 /* enabled NVRAM write access. */ 1407 /* */ 1408 /* Returns: */ 1409 /* 0 on success, positive value on failure. */ 1410 /****************************************************************************/ 1411 int 1412 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1413 u_int32_t cmd_flags) 1414 { 1415 u_int32_t cmd, val32; 1416 int j; 1417 1418 /* Build the command word. */ 1419 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1420 1421 /* Calculate the offset for buffered flash if translation is used. */ 1422 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1423 offset = ((offset / sc->bnx_flash_info->page_size) << 1424 sc->bnx_flash_info->page_bits) + 1425 (offset % sc->bnx_flash_info->page_size); 1426 } 1427 1428 /* 1429 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1430 * set the NVRAM address to write, and issue the write command 1431 */ 1432 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1433 memcpy(&val32, val, 4); 1434 val32 = htobe32(val32); 1435 REG_WR(sc, BNX_NVM_WRITE, val32); 1436 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1437 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1438 1439 /* Wait for completion. */ 1440 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1441 DELAY(5); 1442 1443 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1444 break; 1445 } 1446 if (j >= NVRAM_TIMEOUT_COUNT) { 1447 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1448 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1449 return (EBUSY); 1450 } 1451 1452 return (0); 1453 } 1454 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1455 1456 /****************************************************************************/ 1457 /* Initialize NVRAM access. */ 1458 /* */ 1459 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1460 /* access that device. */ 1461 /* */ 1462 /* Returns: */ 1463 /* 0 on success, positive value on failure. */ 1464 /****************************************************************************/ 1465 int 1466 bnx_init_nvram(struct bnx_softc *sc) 1467 { 1468 u_int32_t val; 1469 int j, entry_count, rc = 0; 1470 struct flash_spec *flash; 1471 1472 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1473 1474 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1475 sc->bnx_flash_info = &flash_5709; 1476 goto bnx_init_nvram_get_flash_size; 1477 } 1478 1479 /* Determine the selected interface. */ 1480 val = REG_RD(sc, BNX_NVM_CFG1); 1481 1482 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1483 1484 /* 1485 * Flash reconfiguration is required to support additional 1486 * NVRAM devices not directly supported in hardware. 1487 * Check if the flash interface was reconfigured 1488 * by the bootcode. 1489 */ 1490 1491 if (val & 0x40000000) { 1492 /* Flash interface reconfigured by bootcode. */ 1493 1494 DBPRINT(sc,BNX_INFO_LOAD, 1495 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1496 1497 for (j = 0, flash = &flash_table[0]; j < entry_count; 1498 j++, flash++) { 1499 if ((val & FLASH_BACKUP_STRAP_MASK) == 1500 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1501 sc->bnx_flash_info = flash; 1502 break; 1503 } 1504 } 1505 } else { 1506 /* Flash interface not yet reconfigured. */ 1507 u_int32_t mask; 1508 1509 DBPRINT(sc,BNX_INFO_LOAD, 1510 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1511 1512 if (val & (1 << 23)) 1513 mask = FLASH_BACKUP_STRAP_MASK; 1514 else 1515 mask = FLASH_STRAP_MASK; 1516 1517 /* Look for the matching NVRAM device configuration data. */ 1518 for (j = 0, flash = &flash_table[0]; j < entry_count; 1519 j++, flash++) { 1520 /* Check if the dev matches any of the known devices. */ 1521 if ((val & mask) == (flash->strapping & mask)) { 1522 /* Found a device match. */ 1523 sc->bnx_flash_info = flash; 1524 1525 /* Request access to the flash interface. */ 1526 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1527 return (rc); 1528 1529 /* Reconfigure the flash interface. */ 1530 bnx_enable_nvram_access(sc); 1531 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1532 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1533 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1534 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1535 bnx_disable_nvram_access(sc); 1536 bnx_release_nvram_lock(sc); 1537 1538 break; 1539 } 1540 } 1541 } 1542 1543 /* Check if a matching device was found. */ 1544 if (j == entry_count) { 1545 sc->bnx_flash_info = NULL; 1546 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1547 __FILE__, __LINE__); 1548 rc = ENODEV; 1549 } 1550 1551 bnx_init_nvram_get_flash_size: 1552 /* Write the flash config data to the shared memory interface. */ 1553 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1554 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1555 if (val) 1556 sc->bnx_flash_size = val; 1557 else 1558 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1559 1560 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1561 "0x%08X\n", sc->bnx_flash_info->total_size); 1562 1563 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1564 1565 return (rc); 1566 } 1567 1568 /****************************************************************************/ 1569 /* Read an arbitrary range of data from NVRAM. */ 1570 /* */ 1571 /* Prepares the NVRAM interface for access and reads the requested data */ 1572 /* into the supplied buffer. */ 1573 /* */ 1574 /* Returns: */ 1575 /* 0 on success and the data read, positive value on failure. */ 1576 /****************************************************************************/ 1577 int 1578 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1579 int buf_size) 1580 { 1581 int rc = 0; 1582 u_int32_t cmd_flags, offset32, len32, extra; 1583 1584 if (buf_size == 0) 1585 return (0); 1586 1587 /* Request access to the flash interface. */ 1588 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1589 return (rc); 1590 1591 /* Enable access to flash interface */ 1592 bnx_enable_nvram_access(sc); 1593 1594 len32 = buf_size; 1595 offset32 = offset; 1596 extra = 0; 1597 1598 cmd_flags = 0; 1599 1600 if (offset32 & 3) { 1601 u_int8_t buf[4]; 1602 u_int32_t pre_len; 1603 1604 offset32 &= ~3; 1605 pre_len = 4 - (offset & 3); 1606 1607 if (pre_len >= len32) { 1608 pre_len = len32; 1609 cmd_flags = 1610 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1611 } else 1612 cmd_flags = BNX_NVM_COMMAND_FIRST; 1613 1614 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1615 1616 if (rc) 1617 return (rc); 1618 1619 memcpy(ret_buf, buf + (offset & 3), pre_len); 1620 1621 offset32 += 4; 1622 ret_buf += pre_len; 1623 len32 -= pre_len; 1624 } 1625 1626 if (len32 & 3) { 1627 extra = 4 - (len32 & 3); 1628 len32 = (len32 + 4) & ~3; 1629 } 1630 1631 if (len32 == 4) { 1632 u_int8_t buf[4]; 1633 1634 if (cmd_flags) 1635 cmd_flags = BNX_NVM_COMMAND_LAST; 1636 else 1637 cmd_flags = 1638 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1639 1640 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1641 1642 memcpy(ret_buf, buf, 4 - extra); 1643 } else if (len32 > 0) { 1644 u_int8_t buf[4]; 1645 1646 /* Read the first word. */ 1647 if (cmd_flags) 1648 cmd_flags = 0; 1649 else 1650 cmd_flags = BNX_NVM_COMMAND_FIRST; 1651 1652 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1653 1654 /* Advance to the next dword. */ 1655 offset32 += 4; 1656 ret_buf += 4; 1657 len32 -= 4; 1658 1659 while (len32 > 4 && rc == 0) { 1660 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1661 1662 /* Advance to the next dword. */ 1663 offset32 += 4; 1664 ret_buf += 4; 1665 len32 -= 4; 1666 } 1667 1668 if (rc) 1669 return (rc); 1670 1671 cmd_flags = BNX_NVM_COMMAND_LAST; 1672 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1673 1674 memcpy(ret_buf, buf, 4 - extra); 1675 } 1676 1677 /* Disable access to flash interface and release the lock. */ 1678 bnx_disable_nvram_access(sc); 1679 bnx_release_nvram_lock(sc); 1680 1681 return (rc); 1682 } 1683 1684 #ifdef BNX_NVRAM_WRITE_SUPPORT 1685 /****************************************************************************/ 1686 /* Write an arbitrary range of data from NVRAM. */ 1687 /* */ 1688 /* Prepares the NVRAM interface for write access and writes the requested */ 1689 /* data from the supplied buffer. The caller is responsible for */ 1690 /* calculating any appropriate CRCs. */ 1691 /* */ 1692 /* Returns: */ 1693 /* 0 on success, positive value on failure. */ 1694 /****************************************************************************/ 1695 int 1696 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1697 int buf_size) 1698 { 1699 u_int32_t written, offset32, len32; 1700 u_int8_t *buf, start[4], end[4]; 1701 int rc = 0; 1702 int align_start, align_end; 1703 1704 buf = data_buf; 1705 offset32 = offset; 1706 len32 = buf_size; 1707 align_start = align_end = 0; 1708 1709 if ((align_start = (offset32 & 3))) { 1710 offset32 &= ~3; 1711 len32 += align_start; 1712 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1713 return (rc); 1714 } 1715 1716 if (len32 & 3) { 1717 if ((len32 > 4) || !align_start) { 1718 align_end = 4 - (len32 & 3); 1719 len32 += align_end; 1720 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1721 end, 4))) { 1722 return (rc); 1723 } 1724 } 1725 } 1726 1727 if (align_start || align_end) { 1728 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1729 if (buf == 0) 1730 return (ENOMEM); 1731 1732 if (align_start) 1733 memcpy(buf, start, 4); 1734 1735 if (align_end) 1736 memcpy(buf + len32 - 4, end, 4); 1737 1738 memcpy(buf + align_start, data_buf, buf_size); 1739 } 1740 1741 written = 0; 1742 while ((written < len32) && (rc == 0)) { 1743 u_int32_t page_start, page_end, data_start, data_end; 1744 u_int32_t addr, cmd_flags; 1745 int i; 1746 u_int8_t flash_buffer[264]; 1747 1748 /* Find the page_start addr */ 1749 page_start = offset32 + written; 1750 page_start -= (page_start % sc->bnx_flash_info->page_size); 1751 /* Find the page_end addr */ 1752 page_end = page_start + sc->bnx_flash_info->page_size; 1753 /* Find the data_start addr */ 1754 data_start = (written == 0) ? offset32 : page_start; 1755 /* Find the data_end addr */ 1756 data_end = (page_end > offset32 + len32) ? 1757 (offset32 + len32) : page_end; 1758 1759 /* Request access to the flash interface. */ 1760 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1761 goto nvram_write_end; 1762 1763 /* Enable access to flash interface */ 1764 bnx_enable_nvram_access(sc); 1765 1766 cmd_flags = BNX_NVM_COMMAND_FIRST; 1767 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1768 int j; 1769 1770 /* Read the whole page into the buffer 1771 * (non-buffer flash only) */ 1772 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1773 if (j == (sc->bnx_flash_info->page_size - 4)) 1774 cmd_flags |= BNX_NVM_COMMAND_LAST; 1775 1776 rc = bnx_nvram_read_dword(sc, 1777 page_start + j, 1778 &flash_buffer[j], 1779 cmd_flags); 1780 1781 if (rc) 1782 goto nvram_write_end; 1783 1784 cmd_flags = 0; 1785 } 1786 } 1787 1788 /* Enable writes to flash interface (unlock write-protect) */ 1789 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1790 goto nvram_write_end; 1791 1792 /* Erase the page */ 1793 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1794 goto nvram_write_end; 1795 1796 /* Re-enable the write again for the actual write */ 1797 bnx_enable_nvram_write(sc); 1798 1799 /* Loop to write back the buffer data from page_start to 1800 * data_start */ 1801 i = 0; 1802 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1803 for (addr = page_start; addr < data_start; 1804 addr += 4, i += 4) { 1805 1806 rc = bnx_nvram_write_dword(sc, addr, 1807 &flash_buffer[i], cmd_flags); 1808 1809 if (rc != 0) 1810 goto nvram_write_end; 1811 1812 cmd_flags = 0; 1813 } 1814 } 1815 1816 /* Loop to write the new data from data_start to data_end */ 1817 for (addr = data_start; addr < data_end; addr += 4, i++) { 1818 if ((addr == page_end - 4) || 1819 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1820 && (addr == data_end - 4))) { 1821 1822 cmd_flags |= BNX_NVM_COMMAND_LAST; 1823 } 1824 1825 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1826 1827 if (rc != 0) 1828 goto nvram_write_end; 1829 1830 cmd_flags = 0; 1831 buf += 4; 1832 } 1833 1834 /* Loop to write back the buffer data from data_end 1835 * to page_end */ 1836 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1837 for (addr = data_end; addr < page_end; 1838 addr += 4, i += 4) { 1839 1840 if (addr == page_end-4) 1841 cmd_flags = BNX_NVM_COMMAND_LAST; 1842 1843 rc = bnx_nvram_write_dword(sc, addr, 1844 &flash_buffer[i], cmd_flags); 1845 1846 if (rc != 0) 1847 goto nvram_write_end; 1848 1849 cmd_flags = 0; 1850 } 1851 } 1852 1853 /* Disable writes to flash interface (lock write-protect) */ 1854 bnx_disable_nvram_write(sc); 1855 1856 /* Disable access to flash interface */ 1857 bnx_disable_nvram_access(sc); 1858 bnx_release_nvram_lock(sc); 1859 1860 /* Increment written */ 1861 written += data_end - data_start; 1862 } 1863 1864 nvram_write_end: 1865 if (align_start || align_end) 1866 free(buf, M_DEVBUF); 1867 1868 return (rc); 1869 } 1870 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1871 1872 /****************************************************************************/ 1873 /* Verifies that NVRAM is accessible and contains valid data. */ 1874 /* */ 1875 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1876 /* correct. */ 1877 /* */ 1878 /* Returns: */ 1879 /* 0 on success, positive value on failure. */ 1880 /****************************************************************************/ 1881 int 1882 bnx_nvram_test(struct bnx_softc *sc) 1883 { 1884 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1885 u_int8_t *data = (u_int8_t *) buf; 1886 int rc = 0; 1887 u_int32_t magic, csum; 1888 1889 /* 1890 * Check that the device NVRAM is valid by reading 1891 * the magic value at offset 0. 1892 */ 1893 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1894 goto bnx_nvram_test_done; 1895 1896 magic = bnx_be32toh(buf[0]); 1897 if (magic != BNX_NVRAM_MAGIC) { 1898 rc = ENODEV; 1899 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1900 "Expected: 0x%08X, Found: 0x%08X\n", 1901 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1902 goto bnx_nvram_test_done; 1903 } 1904 1905 /* 1906 * Verify that the device NVRAM includes valid 1907 * configuration data. 1908 */ 1909 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1910 goto bnx_nvram_test_done; 1911 1912 csum = ether_crc32_le(data, 0x100); 1913 if (csum != BNX_CRC32_RESIDUAL) { 1914 rc = ENODEV; 1915 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1916 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1917 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1918 goto bnx_nvram_test_done; 1919 } 1920 1921 csum = ether_crc32_le(data + 0x100, 0x100); 1922 if (csum != BNX_CRC32_RESIDUAL) { 1923 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1924 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1925 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1926 rc = ENODEV; 1927 } 1928 1929 bnx_nvram_test_done: 1930 return (rc); 1931 } 1932 1933 /****************************************************************************/ 1934 /* Identifies the current media type of the controller and sets the PHY */ 1935 /* address. */ 1936 /* */ 1937 /* Returns: */ 1938 /* Nothing. */ 1939 /****************************************************************************/ 1940 void 1941 bnx_get_media(struct bnx_softc *sc) 1942 { 1943 sc->bnx_phy_addr = 1; 1944 1945 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1946 u_int32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 1947 u_int32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 1948 u_int32_t strap; 1949 1950 /* 1951 * The BCM5709S is software configurable 1952 * for Copper or SerDes operation. 1953 */ 1954 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 1955 DBPRINT(sc, BNX_INFO_LOAD, 1956 "5709 bonded for copper.\n"); 1957 goto bnx_get_media_exit; 1958 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 1959 DBPRINT(sc, BNX_INFO_LOAD, 1960 "5709 bonded for dual media.\n"); 1961 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 1962 goto bnx_get_media_exit; 1963 } 1964 1965 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 1966 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 1967 else { 1968 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 1969 >> 8; 1970 } 1971 1972 if (sc->bnx_pa.pa_function == 0) { 1973 switch (strap) { 1974 case 0x4: 1975 case 0x5: 1976 case 0x6: 1977 DBPRINT(sc, BNX_INFO_LOAD, 1978 "BCM5709 s/w configured for SerDes.\n"); 1979 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 1980 break; 1981 default: 1982 DBPRINT(sc, BNX_INFO_LOAD, 1983 "BCM5709 s/w configured for Copper.\n"); 1984 } 1985 } else { 1986 switch (strap) { 1987 case 0x1: 1988 case 0x2: 1989 case 0x4: 1990 DBPRINT(sc, BNX_INFO_LOAD, 1991 "BCM5709 s/w configured for SerDes.\n"); 1992 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 1993 break; 1994 default: 1995 DBPRINT(sc, BNX_INFO_LOAD, 1996 "BCM5709 s/w configured for Copper.\n"); 1997 } 1998 } 1999 2000 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2001 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2002 2003 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2004 u_int32_t val; 2005 2006 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2007 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2008 sc->bnx_phy_addr = 2; 2009 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2010 BNX_SHARED_HW_CFG_CONFIG); 2011 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2012 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2013 DBPRINT(sc, BNX_INFO_LOAD, 2014 "Found 2.5Gb capable adapter\n"); 2015 } 2016 } 2017 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2018 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2019 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2020 2021 bnx_get_media_exit: 2022 DBPRINT(sc, (BNX_INFO_LOAD), 2023 "Using PHY address %d.\n", sc->bnx_phy_addr); 2024 } 2025 2026 /****************************************************************************/ 2027 /* Free any DMA memory owned by the driver. */ 2028 /* */ 2029 /* Scans through each data structre that requires DMA memory and frees */ 2030 /* the memory if allocated. */ 2031 /* */ 2032 /* Returns: */ 2033 /* Nothing. */ 2034 /****************************************************************************/ 2035 void 2036 bnx_dma_free(struct bnx_softc *sc) 2037 { 2038 int i; 2039 2040 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2041 2042 /* Destroy the status block. */ 2043 if (sc->status_block != NULL && sc->status_map != NULL) { 2044 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2045 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2046 BNX_STATUS_BLK_SZ); 2047 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2048 sc->status_rseg); 2049 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2050 sc->status_block = NULL; 2051 sc->status_map = NULL; 2052 } 2053 2054 /* Destroy the statistics block. */ 2055 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2056 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2057 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2058 BNX_STATS_BLK_SZ); 2059 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2060 sc->stats_rseg); 2061 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2062 sc->stats_block = NULL; 2063 sc->stats_map = NULL; 2064 } 2065 2066 /* Free, unmap and destroy all context memory pages. */ 2067 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2068 for (i = 0; i < sc->ctx_pages; i++) { 2069 if (sc->ctx_block[i] != NULL) { 2070 bus_dmamap_unload(sc->bnx_dmatag, 2071 sc->ctx_map[i]); 2072 bus_dmamem_unmap(sc->bnx_dmatag, 2073 (void *)sc->ctx_block[i], 2074 BCM_PAGE_SIZE); 2075 bus_dmamem_free(sc->bnx_dmatag, 2076 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2077 bus_dmamap_destroy(sc->bnx_dmatag, 2078 sc->ctx_map[i]); 2079 sc->ctx_block[i] = NULL; 2080 } 2081 } 2082 } 2083 2084 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2085 for (i = 0; i < TX_PAGES; i++ ) { 2086 if (sc->tx_bd_chain[i] != NULL && 2087 sc->tx_bd_chain_map[i] != NULL) { 2088 bus_dmamap_unload(sc->bnx_dmatag, 2089 sc->tx_bd_chain_map[i]); 2090 bus_dmamem_unmap(sc->bnx_dmatag, 2091 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2092 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2093 sc->tx_bd_chain_rseg[i]); 2094 bus_dmamap_destroy(sc->bnx_dmatag, 2095 sc->tx_bd_chain_map[i]); 2096 sc->tx_bd_chain[i] = NULL; 2097 sc->tx_bd_chain_map[i] = NULL; 2098 } 2099 } 2100 2101 /* Destroy the TX dmamaps. */ 2102 /* This isn't necessary since we dont allocate them up front */ 2103 2104 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2105 for (i = 0; i < RX_PAGES; i++ ) { 2106 if (sc->rx_bd_chain[i] != NULL && 2107 sc->rx_bd_chain_map[i] != NULL) { 2108 bus_dmamap_unload(sc->bnx_dmatag, 2109 sc->rx_bd_chain_map[i]); 2110 bus_dmamem_unmap(sc->bnx_dmatag, 2111 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2112 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2113 sc->rx_bd_chain_rseg[i]); 2114 2115 bus_dmamap_destroy(sc->bnx_dmatag, 2116 sc->rx_bd_chain_map[i]); 2117 sc->rx_bd_chain[i] = NULL; 2118 sc->rx_bd_chain_map[i] = NULL; 2119 } 2120 } 2121 2122 /* Unload and destroy the RX mbuf maps. */ 2123 for (i = 0; i < TOTAL_RX_BD; i++) { 2124 if (sc->rx_mbuf_map[i] != NULL) { 2125 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2126 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2127 } 2128 } 2129 2130 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2131 } 2132 2133 /****************************************************************************/ 2134 /* Allocate any DMA memory needed by the driver. */ 2135 /* */ 2136 /* Allocates DMA memory needed for the various global structures needed by */ 2137 /* hardware. */ 2138 /* */ 2139 /* Returns: */ 2140 /* 0 for success, positive value for failure. */ 2141 /****************************************************************************/ 2142 int 2143 bnx_dma_alloc(struct bnx_softc *sc) 2144 { 2145 int i, rc = 0; 2146 2147 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2148 2149 /* 2150 * Allocate DMA memory for the status block, map the memory into DMA 2151 * space, and fetch the physical address of the block. 2152 */ 2153 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2154 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2155 aprint_error_dev(sc->bnx_dev, 2156 "Could not create status block DMA map!\n"); 2157 rc = ENOMEM; 2158 goto bnx_dma_alloc_exit; 2159 } 2160 2161 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2162 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2163 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2164 aprint_error_dev(sc->bnx_dev, 2165 "Could not allocate status block DMA memory!\n"); 2166 rc = ENOMEM; 2167 goto bnx_dma_alloc_exit; 2168 } 2169 2170 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2171 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2172 aprint_error_dev(sc->bnx_dev, 2173 "Could not map status block DMA memory!\n"); 2174 rc = ENOMEM; 2175 goto bnx_dma_alloc_exit; 2176 } 2177 2178 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2179 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2180 aprint_error_dev(sc->bnx_dev, 2181 "Could not load status block DMA memory!\n"); 2182 rc = ENOMEM; 2183 goto bnx_dma_alloc_exit; 2184 } 2185 2186 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2187 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2188 2189 /* DRC - Fix for 64 bit addresses. */ 2190 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2191 (u_int32_t) sc->status_block_paddr); 2192 2193 /* BCM5709 uses host memory as cache for context memory. */ 2194 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2195 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2196 if (sc->ctx_pages == 0) 2197 sc->ctx_pages = 1; 2198 if (sc->ctx_pages > 4) /* XXX */ 2199 sc->ctx_pages = 4; 2200 2201 DBRUNIF((sc->ctx_pages > 512), 2202 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2203 __FILE__, __LINE__, sc->ctx_pages)); 2204 2205 2206 for (i = 0; i < sc->ctx_pages; i++) { 2207 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2208 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2209 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2210 &sc->ctx_map[i]) != 0) { 2211 rc = ENOMEM; 2212 goto bnx_dma_alloc_exit; 2213 } 2214 2215 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2216 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2217 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2218 rc = ENOMEM; 2219 goto bnx_dma_alloc_exit; 2220 } 2221 2222 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2223 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2224 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2225 rc = ENOMEM; 2226 goto bnx_dma_alloc_exit; 2227 } 2228 2229 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2230 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2231 BUS_DMA_NOWAIT) != 0) { 2232 rc = ENOMEM; 2233 goto bnx_dma_alloc_exit; 2234 } 2235 2236 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2237 } 2238 } 2239 2240 /* 2241 * Allocate DMA memory for the statistics block, map the memory into 2242 * DMA space, and fetch the physical address of the block. 2243 */ 2244 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2245 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2246 aprint_error_dev(sc->bnx_dev, 2247 "Could not create stats block DMA map!\n"); 2248 rc = ENOMEM; 2249 goto bnx_dma_alloc_exit; 2250 } 2251 2252 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2253 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2254 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2255 aprint_error_dev(sc->bnx_dev, 2256 "Could not allocate stats block DMA memory!\n"); 2257 rc = ENOMEM; 2258 goto bnx_dma_alloc_exit; 2259 } 2260 2261 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2262 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2263 aprint_error_dev(sc->bnx_dev, 2264 "Could not map stats block DMA memory!\n"); 2265 rc = ENOMEM; 2266 goto bnx_dma_alloc_exit; 2267 } 2268 2269 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2270 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2271 aprint_error_dev(sc->bnx_dev, 2272 "Could not load status block DMA memory!\n"); 2273 rc = ENOMEM; 2274 goto bnx_dma_alloc_exit; 2275 } 2276 2277 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2278 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2279 2280 /* DRC - Fix for 64 bit address. */ 2281 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2282 (u_int32_t) sc->stats_block_paddr); 2283 2284 /* 2285 * Allocate DMA memory for the TX buffer descriptor chain, 2286 * and fetch the physical address of the block. 2287 */ 2288 for (i = 0; i < TX_PAGES; i++) { 2289 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2290 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2291 &sc->tx_bd_chain_map[i])) { 2292 aprint_error_dev(sc->bnx_dev, 2293 "Could not create Tx desc %d DMA map!\n", i); 2294 rc = ENOMEM; 2295 goto bnx_dma_alloc_exit; 2296 } 2297 2298 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2299 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2300 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2301 aprint_error_dev(sc->bnx_dev, 2302 "Could not allocate TX desc %d DMA memory!\n", 2303 i); 2304 rc = ENOMEM; 2305 goto bnx_dma_alloc_exit; 2306 } 2307 2308 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2309 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2310 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2311 aprint_error_dev(sc->bnx_dev, 2312 "Could not map TX desc %d DMA memory!\n", i); 2313 rc = ENOMEM; 2314 goto bnx_dma_alloc_exit; 2315 } 2316 2317 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2318 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2319 BUS_DMA_NOWAIT)) { 2320 aprint_error_dev(sc->bnx_dev, 2321 "Could not load TX desc %d DMA memory!\n", i); 2322 rc = ENOMEM; 2323 goto bnx_dma_alloc_exit; 2324 } 2325 2326 sc->tx_bd_chain_paddr[i] = 2327 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2328 2329 /* DRC - Fix for 64 bit systems. */ 2330 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2331 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2332 } 2333 2334 /* 2335 * Create lists to hold TX mbufs. 2336 */ 2337 TAILQ_INIT(&sc->tx_free_pkts); 2338 TAILQ_INIT(&sc->tx_used_pkts); 2339 sc->tx_pkt_count = 0; 2340 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2341 2342 /* 2343 * Allocate DMA memory for the Rx buffer descriptor chain, 2344 * and fetch the physical address of the block. 2345 */ 2346 for (i = 0; i < RX_PAGES; i++) { 2347 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2348 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2349 &sc->rx_bd_chain_map[i])) { 2350 aprint_error_dev(sc->bnx_dev, 2351 "Could not create Rx desc %d DMA map!\n", i); 2352 rc = ENOMEM; 2353 goto bnx_dma_alloc_exit; 2354 } 2355 2356 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2357 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2358 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2359 aprint_error_dev(sc->bnx_dev, 2360 "Could not allocate Rx desc %d DMA memory!\n", i); 2361 rc = ENOMEM; 2362 goto bnx_dma_alloc_exit; 2363 } 2364 2365 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2366 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2367 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2368 aprint_error_dev(sc->bnx_dev, 2369 "Could not map Rx desc %d DMA memory!\n", i); 2370 rc = ENOMEM; 2371 goto bnx_dma_alloc_exit; 2372 } 2373 2374 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2375 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2376 BUS_DMA_NOWAIT)) { 2377 aprint_error_dev(sc->bnx_dev, 2378 "Could not load Rx desc %d DMA memory!\n", i); 2379 rc = ENOMEM; 2380 goto bnx_dma_alloc_exit; 2381 } 2382 2383 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2384 sc->rx_bd_chain_paddr[i] = 2385 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2386 2387 /* DRC - Fix for 64 bit systems. */ 2388 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2389 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2390 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2391 0, BNX_RX_CHAIN_PAGE_SZ, 2392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2393 } 2394 2395 /* 2396 * Create DMA maps for the Rx buffer mbufs. 2397 */ 2398 for (i = 0; i < TOTAL_RX_BD; i++) { 2399 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2400 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2401 &sc->rx_mbuf_map[i])) { 2402 aprint_error_dev(sc->bnx_dev, 2403 "Could not create Rx mbuf %d DMA map!\n", i); 2404 rc = ENOMEM; 2405 goto bnx_dma_alloc_exit; 2406 } 2407 } 2408 2409 bnx_dma_alloc_exit: 2410 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2411 2412 return(rc); 2413 } 2414 2415 /****************************************************************************/ 2416 /* Release all resources used by the driver. */ 2417 /* */ 2418 /* Releases all resources acquired by the driver including interrupts, */ 2419 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2420 /* */ 2421 /* Returns: */ 2422 /* Nothing. */ 2423 /****************************************************************************/ 2424 void 2425 bnx_release_resources(struct bnx_softc *sc) 2426 { 2427 struct pci_attach_args *pa = &(sc->bnx_pa); 2428 2429 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2430 2431 bnx_dma_free(sc); 2432 2433 if (sc->bnx_intrhand != NULL) 2434 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2435 2436 if (sc->bnx_size) 2437 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2438 2439 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2440 } 2441 2442 /****************************************************************************/ 2443 /* Firmware synchronization. */ 2444 /* */ 2445 /* Before performing certain events such as a chip reset, synchronize with */ 2446 /* the firmware first. */ 2447 /* */ 2448 /* Returns: */ 2449 /* 0 for success, positive value for failure. */ 2450 /****************************************************************************/ 2451 int 2452 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2453 { 2454 int i, rc = 0; 2455 u_int32_t val; 2456 2457 /* Don't waste any time if we've timed out before. */ 2458 if (sc->bnx_fw_timed_out) { 2459 rc = EBUSY; 2460 goto bnx_fw_sync_exit; 2461 } 2462 2463 /* Increment the message sequence number. */ 2464 sc->bnx_fw_wr_seq++; 2465 msg_data |= sc->bnx_fw_wr_seq; 2466 2467 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2468 msg_data); 2469 2470 /* Send the message to the bootcode driver mailbox. */ 2471 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2472 2473 /* Wait for the bootcode to acknowledge the message. */ 2474 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2475 /* Check for a response in the bootcode firmware mailbox. */ 2476 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2477 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2478 break; 2479 DELAY(1000); 2480 } 2481 2482 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2483 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2484 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2485 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2486 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2487 2488 msg_data &= ~BNX_DRV_MSG_CODE; 2489 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2490 2491 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2492 2493 sc->bnx_fw_timed_out = 1; 2494 rc = EBUSY; 2495 } 2496 2497 bnx_fw_sync_exit: 2498 return (rc); 2499 } 2500 2501 /****************************************************************************/ 2502 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2503 /* */ 2504 /* Returns: */ 2505 /* Nothing. */ 2506 /****************************************************************************/ 2507 void 2508 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2509 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2510 { 2511 int i; 2512 u_int32_t val; 2513 2514 /* Set the page size used by RV2P. */ 2515 if (rv2p_proc == RV2P_PROC2) { 2516 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2517 USABLE_RX_BD_PER_PAGE); 2518 } 2519 2520 for (i = 0; i < rv2p_code_len; i += 8) { 2521 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2522 rv2p_code++; 2523 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2524 rv2p_code++; 2525 2526 if (rv2p_proc == RV2P_PROC1) { 2527 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2528 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2529 } else { 2530 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2531 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2532 } 2533 } 2534 2535 /* Reset the processor, un-stall is done later. */ 2536 if (rv2p_proc == RV2P_PROC1) 2537 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2538 else 2539 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2540 } 2541 2542 /****************************************************************************/ 2543 /* Load RISC processor firmware. */ 2544 /* */ 2545 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2546 /* associated with a particular processor. */ 2547 /* */ 2548 /* Returns: */ 2549 /* Nothing. */ 2550 /****************************************************************************/ 2551 void 2552 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2553 struct fw_info *fw) 2554 { 2555 u_int32_t offset; 2556 u_int32_t val; 2557 2558 /* Halt the CPU. */ 2559 val = REG_RD_IND(sc, cpu_reg->mode); 2560 val |= cpu_reg->mode_value_halt; 2561 REG_WR_IND(sc, cpu_reg->mode, val); 2562 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2563 2564 /* Load the Text area. */ 2565 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2566 if (fw->text) { 2567 int j; 2568 2569 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2570 REG_WR_IND(sc, offset, fw->text[j]); 2571 } 2572 2573 /* Load the Data area. */ 2574 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2575 if (fw->data) { 2576 int j; 2577 2578 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2579 REG_WR_IND(sc, offset, fw->data[j]); 2580 } 2581 2582 /* Load the SBSS area. */ 2583 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2584 if (fw->sbss) { 2585 int j; 2586 2587 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2588 REG_WR_IND(sc, offset, fw->sbss[j]); 2589 } 2590 2591 /* Load the BSS area. */ 2592 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2593 if (fw->bss) { 2594 int j; 2595 2596 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2597 REG_WR_IND(sc, offset, fw->bss[j]); 2598 } 2599 2600 /* Load the Read-Only area. */ 2601 offset = cpu_reg->spad_base + 2602 (fw->rodata_addr - cpu_reg->mips_view_base); 2603 if (fw->rodata) { 2604 int j; 2605 2606 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2607 REG_WR_IND(sc, offset, fw->rodata[j]); 2608 } 2609 2610 /* Clear the pre-fetch instruction. */ 2611 REG_WR_IND(sc, cpu_reg->inst, 0); 2612 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2613 2614 /* Start the CPU. */ 2615 val = REG_RD_IND(sc, cpu_reg->mode); 2616 val &= ~cpu_reg->mode_value_halt; 2617 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2618 REG_WR_IND(sc, cpu_reg->mode, val); 2619 } 2620 2621 /****************************************************************************/ 2622 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2623 /* */ 2624 /* Loads the firmware for each CPU and starts the CPU. */ 2625 /* */ 2626 /* Returns: */ 2627 /* Nothing. */ 2628 /****************************************************************************/ 2629 void 2630 bnx_init_cpus(struct bnx_softc *sc) 2631 { 2632 struct cpu_reg cpu_reg; 2633 struct fw_info fw; 2634 2635 switch(BNX_CHIP_NUM(sc)) { 2636 case BNX_CHIP_NUM_5709: 2637 /* Initialize the RV2P processor. */ 2638 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2639 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2640 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2641 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2642 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2643 } else { 2644 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2645 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2646 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2647 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2648 } 2649 2650 /* Initialize the RX Processor. */ 2651 cpu_reg.mode = BNX_RXP_CPU_MODE; 2652 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2653 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2654 cpu_reg.state = BNX_RXP_CPU_STATE; 2655 cpu_reg.state_value_clear = 0xffffff; 2656 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2657 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2658 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2659 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2660 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2661 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2662 cpu_reg.mips_view_base = 0x8000000; 2663 2664 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2665 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2666 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2667 fw.start_addr = bnx_RXP_b09FwStartAddr; 2668 2669 fw.text_addr = bnx_RXP_b09FwTextAddr; 2670 fw.text_len = bnx_RXP_b09FwTextLen; 2671 fw.text_index = 0; 2672 fw.text = bnx_RXP_b09FwText; 2673 2674 fw.data_addr = bnx_RXP_b09FwDataAddr; 2675 fw.data_len = bnx_RXP_b09FwDataLen; 2676 fw.data_index = 0; 2677 fw.data = bnx_RXP_b09FwData; 2678 2679 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2680 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2681 fw.sbss_index = 0; 2682 fw.sbss = bnx_RXP_b09FwSbss; 2683 2684 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2685 fw.bss_len = bnx_RXP_b09FwBssLen; 2686 fw.bss_index = 0; 2687 fw.bss = bnx_RXP_b09FwBss; 2688 2689 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2690 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2691 fw.rodata_index = 0; 2692 fw.rodata = bnx_RXP_b09FwRodata; 2693 2694 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2695 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2696 2697 /* Initialize the TX Processor. */ 2698 cpu_reg.mode = BNX_TXP_CPU_MODE; 2699 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2700 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2701 cpu_reg.state = BNX_TXP_CPU_STATE; 2702 cpu_reg.state_value_clear = 0xffffff; 2703 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2704 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2705 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2706 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2707 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2708 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2709 cpu_reg.mips_view_base = 0x8000000; 2710 2711 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2712 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2713 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2714 fw.start_addr = bnx_TXP_b09FwStartAddr; 2715 2716 fw.text_addr = bnx_TXP_b09FwTextAddr; 2717 fw.text_len = bnx_TXP_b09FwTextLen; 2718 fw.text_index = 0; 2719 fw.text = bnx_TXP_b09FwText; 2720 2721 fw.data_addr = bnx_TXP_b09FwDataAddr; 2722 fw.data_len = bnx_TXP_b09FwDataLen; 2723 fw.data_index = 0; 2724 fw.data = bnx_TXP_b09FwData; 2725 2726 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2727 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2728 fw.sbss_index = 0; 2729 fw.sbss = bnx_TXP_b09FwSbss; 2730 2731 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2732 fw.bss_len = bnx_TXP_b09FwBssLen; 2733 fw.bss_index = 0; 2734 fw.bss = bnx_TXP_b09FwBss; 2735 2736 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2737 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2738 fw.rodata_index = 0; 2739 fw.rodata = bnx_TXP_b09FwRodata; 2740 2741 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2742 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2743 2744 /* Initialize the TX Patch-up Processor. */ 2745 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2746 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2747 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2748 cpu_reg.state = BNX_TPAT_CPU_STATE; 2749 cpu_reg.state_value_clear = 0xffffff; 2750 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2751 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2752 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2753 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2754 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2755 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2756 cpu_reg.mips_view_base = 0x8000000; 2757 2758 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2759 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2760 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2761 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2762 2763 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2764 fw.text_len = bnx_TPAT_b09FwTextLen; 2765 fw.text_index = 0; 2766 fw.text = bnx_TPAT_b09FwText; 2767 2768 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2769 fw.data_len = bnx_TPAT_b09FwDataLen; 2770 fw.data_index = 0; 2771 fw.data = bnx_TPAT_b09FwData; 2772 2773 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2774 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2775 fw.sbss_index = 0; 2776 fw.sbss = bnx_TPAT_b09FwSbss; 2777 2778 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2779 fw.bss_len = bnx_TPAT_b09FwBssLen; 2780 fw.bss_index = 0; 2781 fw.bss = bnx_TPAT_b09FwBss; 2782 2783 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2784 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2785 fw.rodata_index = 0; 2786 fw.rodata = bnx_TPAT_b09FwRodata; 2787 2788 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2789 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2790 2791 /* Initialize the Completion Processor. */ 2792 cpu_reg.mode = BNX_COM_CPU_MODE; 2793 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2794 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2795 cpu_reg.state = BNX_COM_CPU_STATE; 2796 cpu_reg.state_value_clear = 0xffffff; 2797 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2798 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2799 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2800 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2801 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2802 cpu_reg.spad_base = BNX_COM_SCRATCH; 2803 cpu_reg.mips_view_base = 0x8000000; 2804 2805 fw.ver_major = bnx_COM_b09FwReleaseMajor; 2806 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 2807 fw.ver_fix = bnx_COM_b09FwReleaseFix; 2808 fw.start_addr = bnx_COM_b09FwStartAddr; 2809 2810 fw.text_addr = bnx_COM_b09FwTextAddr; 2811 fw.text_len = bnx_COM_b09FwTextLen; 2812 fw.text_index = 0; 2813 fw.text = bnx_COM_b09FwText; 2814 2815 fw.data_addr = bnx_COM_b09FwDataAddr; 2816 fw.data_len = bnx_COM_b09FwDataLen; 2817 fw.data_index = 0; 2818 fw.data = bnx_COM_b09FwData; 2819 2820 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 2821 fw.sbss_len = bnx_COM_b09FwSbssLen; 2822 fw.sbss_index = 0; 2823 fw.sbss = bnx_COM_b09FwSbss; 2824 2825 fw.bss_addr = bnx_COM_b09FwBssAddr; 2826 fw.bss_len = bnx_COM_b09FwBssLen; 2827 fw.bss_index = 0; 2828 fw.bss = bnx_COM_b09FwBss; 2829 2830 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 2831 fw.rodata_len = bnx_COM_b09FwRodataLen; 2832 fw.rodata_index = 0; 2833 fw.rodata = bnx_COM_b09FwRodata; 2834 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2835 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2836 break; 2837 default: 2838 /* Initialize the RV2P processor. */ 2839 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2840 RV2P_PROC1); 2841 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2842 RV2P_PROC2); 2843 2844 /* Initialize the RX Processor. */ 2845 cpu_reg.mode = BNX_RXP_CPU_MODE; 2846 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2847 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2848 cpu_reg.state = BNX_RXP_CPU_STATE; 2849 cpu_reg.state_value_clear = 0xffffff; 2850 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2851 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2852 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2853 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2854 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2855 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2856 cpu_reg.mips_view_base = 0x8000000; 2857 2858 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2859 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2860 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2861 fw.start_addr = bnx_RXP_b06FwStartAddr; 2862 2863 fw.text_addr = bnx_RXP_b06FwTextAddr; 2864 fw.text_len = bnx_RXP_b06FwTextLen; 2865 fw.text_index = 0; 2866 fw.text = bnx_RXP_b06FwText; 2867 2868 fw.data_addr = bnx_RXP_b06FwDataAddr; 2869 fw.data_len = bnx_RXP_b06FwDataLen; 2870 fw.data_index = 0; 2871 fw.data = bnx_RXP_b06FwData; 2872 2873 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2874 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2875 fw.sbss_index = 0; 2876 fw.sbss = bnx_RXP_b06FwSbss; 2877 2878 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2879 fw.bss_len = bnx_RXP_b06FwBssLen; 2880 fw.bss_index = 0; 2881 fw.bss = bnx_RXP_b06FwBss; 2882 2883 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2884 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2885 fw.rodata_index = 0; 2886 fw.rodata = bnx_RXP_b06FwRodata; 2887 2888 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2889 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2890 2891 /* Initialize the TX Processor. */ 2892 cpu_reg.mode = BNX_TXP_CPU_MODE; 2893 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2894 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2895 cpu_reg.state = BNX_TXP_CPU_STATE; 2896 cpu_reg.state_value_clear = 0xffffff; 2897 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2898 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2899 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2900 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2901 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2902 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2903 cpu_reg.mips_view_base = 0x8000000; 2904 2905 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2906 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2907 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2908 fw.start_addr = bnx_TXP_b06FwStartAddr; 2909 2910 fw.text_addr = bnx_TXP_b06FwTextAddr; 2911 fw.text_len = bnx_TXP_b06FwTextLen; 2912 fw.text_index = 0; 2913 fw.text = bnx_TXP_b06FwText; 2914 2915 fw.data_addr = bnx_TXP_b06FwDataAddr; 2916 fw.data_len = bnx_TXP_b06FwDataLen; 2917 fw.data_index = 0; 2918 fw.data = bnx_TXP_b06FwData; 2919 2920 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2921 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2922 fw.sbss_index = 0; 2923 fw.sbss = bnx_TXP_b06FwSbss; 2924 2925 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2926 fw.bss_len = bnx_TXP_b06FwBssLen; 2927 fw.bss_index = 0; 2928 fw.bss = bnx_TXP_b06FwBss; 2929 2930 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 2931 fw.rodata_len = bnx_TXP_b06FwRodataLen; 2932 fw.rodata_index = 0; 2933 fw.rodata = bnx_TXP_b06FwRodata; 2934 2935 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2936 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2937 2938 /* Initialize the TX Patch-up Processor. */ 2939 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2940 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2941 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2942 cpu_reg.state = BNX_TPAT_CPU_STATE; 2943 cpu_reg.state_value_clear = 0xffffff; 2944 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2945 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2946 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2947 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2948 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2949 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2950 cpu_reg.mips_view_base = 0x8000000; 2951 2952 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 2953 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 2954 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 2955 fw.start_addr = bnx_TPAT_b06FwStartAddr; 2956 2957 fw.text_addr = bnx_TPAT_b06FwTextAddr; 2958 fw.text_len = bnx_TPAT_b06FwTextLen; 2959 fw.text_index = 0; 2960 fw.text = bnx_TPAT_b06FwText; 2961 2962 fw.data_addr = bnx_TPAT_b06FwDataAddr; 2963 fw.data_len = bnx_TPAT_b06FwDataLen; 2964 fw.data_index = 0; 2965 fw.data = bnx_TPAT_b06FwData; 2966 2967 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 2968 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 2969 fw.sbss_index = 0; 2970 fw.sbss = bnx_TPAT_b06FwSbss; 2971 2972 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 2973 fw.bss_len = bnx_TPAT_b06FwBssLen; 2974 fw.bss_index = 0; 2975 fw.bss = bnx_TPAT_b06FwBss; 2976 2977 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 2978 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 2979 fw.rodata_index = 0; 2980 fw.rodata = bnx_TPAT_b06FwRodata; 2981 2982 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2983 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2984 2985 /* Initialize the Completion Processor. */ 2986 cpu_reg.mode = BNX_COM_CPU_MODE; 2987 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2988 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2989 cpu_reg.state = BNX_COM_CPU_STATE; 2990 cpu_reg.state_value_clear = 0xffffff; 2991 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2992 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2993 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2994 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2995 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2996 cpu_reg.spad_base = BNX_COM_SCRATCH; 2997 cpu_reg.mips_view_base = 0x8000000; 2998 2999 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3000 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3001 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3002 fw.start_addr = bnx_COM_b06FwStartAddr; 3003 3004 fw.text_addr = bnx_COM_b06FwTextAddr; 3005 fw.text_len = bnx_COM_b06FwTextLen; 3006 fw.text_index = 0; 3007 fw.text = bnx_COM_b06FwText; 3008 3009 fw.data_addr = bnx_COM_b06FwDataAddr; 3010 fw.data_len = bnx_COM_b06FwDataLen; 3011 fw.data_index = 0; 3012 fw.data = bnx_COM_b06FwData; 3013 3014 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3015 fw.sbss_len = bnx_COM_b06FwSbssLen; 3016 fw.sbss_index = 0; 3017 fw.sbss = bnx_COM_b06FwSbss; 3018 3019 fw.bss_addr = bnx_COM_b06FwBssAddr; 3020 fw.bss_len = bnx_COM_b06FwBssLen; 3021 fw.bss_index = 0; 3022 fw.bss = bnx_COM_b06FwBss; 3023 3024 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3025 fw.rodata_len = bnx_COM_b06FwRodataLen; 3026 fw.rodata_index = 0; 3027 fw.rodata = bnx_COM_b06FwRodata; 3028 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3029 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3030 break; 3031 } 3032 } 3033 3034 /****************************************************************************/ 3035 /* Initialize context memory. */ 3036 /* */ 3037 /* Clears the memory associated with each Context ID (CID). */ 3038 /* */ 3039 /* Returns: */ 3040 /* Nothing. */ 3041 /****************************************************************************/ 3042 void 3043 bnx_init_context(struct bnx_softc *sc) 3044 { 3045 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3046 /* DRC: Replace this constant value with a #define. */ 3047 int i, retry_cnt = 10; 3048 u_int32_t val; 3049 3050 /* 3051 * BCM5709 context memory may be cached 3052 * in host memory so prepare the host memory 3053 * for access. 3054 */ 3055 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3056 | (1 << 12); 3057 val |= (BCM_PAGE_BITS - 8) << 16; 3058 REG_WR(sc, BNX_CTX_COMMAND, val); 3059 3060 /* Wait for mem init command to complete. */ 3061 for (i = 0; i < retry_cnt; i++) { 3062 val = REG_RD(sc, BNX_CTX_COMMAND); 3063 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3064 break; 3065 DELAY(2); 3066 } 3067 3068 3069 /* ToDo: Consider returning an error here. */ 3070 3071 for (i = 0; i < sc->ctx_pages; i++) { 3072 int j; 3073 3074 3075 /* Set the physaddr of the context memory cache. */ 3076 val = (u_int32_t)(sc->ctx_segs[i].ds_addr); 3077 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3078 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3079 val = (u_int32_t) 3080 ((u_int64_t)sc->ctx_segs[i].ds_addr >> 32); 3081 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3082 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3083 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3084 3085 3086 /* Verify that the context memory write was successful. */ 3087 for (j = 0; j < retry_cnt; j++) { 3088 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3089 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3090 break; 3091 DELAY(5); 3092 } 3093 3094 /* ToDo: Consider returning an error here. */ 3095 } 3096 } else { 3097 u_int32_t vcid_addr, offset; 3098 3099 /* 3100 * For the 5706/5708, context memory is local to 3101 * the controller, so initialize the controller 3102 * context memory. 3103 */ 3104 3105 vcid_addr = GET_CID_ADDR(96); 3106 while (vcid_addr) { 3107 3108 vcid_addr -= PHY_CTX_SIZE; 3109 3110 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3111 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3112 3113 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 3114 CTX_WR(sc, 0x00, offset, 0); 3115 } 3116 3117 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3118 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3119 } 3120 } 3121 } 3122 3123 /****************************************************************************/ 3124 /* Fetch the permanent MAC address of the controller. */ 3125 /* */ 3126 /* Returns: */ 3127 /* Nothing. */ 3128 /****************************************************************************/ 3129 void 3130 bnx_get_mac_addr(struct bnx_softc *sc) 3131 { 3132 u_int32_t mac_lo = 0, mac_hi = 0; 3133 3134 /* 3135 * The NetXtreme II bootcode populates various NIC 3136 * power-on and runtime configuration items in a 3137 * shared memory area. The factory configured MAC 3138 * address is available from both NVRAM and the 3139 * shared memory area so we'll read the value from 3140 * shared memory for speed. 3141 */ 3142 3143 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3144 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3145 3146 if ((mac_lo == 0) && (mac_hi == 0)) { 3147 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3148 __FILE__, __LINE__); 3149 } else { 3150 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3151 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3152 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3153 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3154 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3155 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3156 } 3157 3158 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3159 "%s\n", ether_sprintf(sc->eaddr)); 3160 } 3161 3162 /****************************************************************************/ 3163 /* Program the MAC address. */ 3164 /* */ 3165 /* Returns: */ 3166 /* Nothing. */ 3167 /****************************************************************************/ 3168 void 3169 bnx_set_mac_addr(struct bnx_softc *sc) 3170 { 3171 u_int32_t val; 3172 const u_int8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3173 3174 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3175 "%s\n", ether_sprintf(sc->eaddr)); 3176 3177 val = (mac_addr[0] << 8) | mac_addr[1]; 3178 3179 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3180 3181 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3182 (mac_addr[4] << 8) | mac_addr[5]; 3183 3184 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3185 } 3186 3187 /****************************************************************************/ 3188 /* Stop the controller. */ 3189 /* */ 3190 /* Returns: */ 3191 /* Nothing. */ 3192 /****************************************************************************/ 3193 void 3194 bnx_stop(struct ifnet *ifp, int disable) 3195 { 3196 struct bnx_softc *sc = ifp->if_softc; 3197 3198 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3199 3200 if ((ifp->if_flags & IFF_RUNNING) == 0) 3201 return; 3202 3203 callout_stop(&sc->bnx_timeout); 3204 3205 mii_down(&sc->bnx_mii); 3206 3207 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3208 3209 /* Disable the transmit/receive blocks. */ 3210 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3211 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3212 DELAY(20); 3213 3214 bnx_disable_intr(sc); 3215 3216 /* Tell firmware that the driver is going away. */ 3217 if (disable) 3218 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3219 else 3220 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3221 3222 /* Free RX buffers. */ 3223 bnx_free_rx_chain(sc); 3224 3225 /* Free TX buffers. */ 3226 bnx_free_tx_chain(sc); 3227 3228 ifp->if_timer = 0; 3229 3230 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3231 3232 } 3233 3234 int 3235 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 3236 { 3237 struct pci_attach_args *pa = &(sc->bnx_pa); 3238 u_int32_t val; 3239 int i, rc = 0; 3240 3241 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3242 3243 /* Wait for pending PCI transactions to complete. */ 3244 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3245 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3246 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3247 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3248 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3249 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3250 DELAY(5); 3251 3252 /* Disable DMA */ 3253 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3254 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3255 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3256 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3257 } 3258 3259 /* Assume bootcode is running. */ 3260 sc->bnx_fw_timed_out = 0; 3261 3262 /* Give the firmware a chance to prepare for the reset. */ 3263 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3264 if (rc) 3265 goto bnx_reset_exit; 3266 3267 /* Set a firmware reminder that this is a soft reset. */ 3268 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3269 BNX_DRV_RESET_SIGNATURE_MAGIC); 3270 3271 /* Dummy read to force the chip to complete all current transactions. */ 3272 val = REG_RD(sc, BNX_MISC_ID); 3273 3274 /* Chip reset. */ 3275 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3276 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3277 REG_RD(sc, BNX_MISC_COMMAND); 3278 DELAY(5); 3279 3280 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3281 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3282 3283 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3284 val); 3285 } else { 3286 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3287 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3288 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3289 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3290 3291 /* Allow up to 30us for reset to complete. */ 3292 for (i = 0; i < 10; i++) { 3293 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3294 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3295 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3296 break; 3297 } 3298 DELAY(10); 3299 } 3300 3301 /* Check that reset completed successfully. */ 3302 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3303 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3304 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3305 __FILE__, __LINE__); 3306 rc = EBUSY; 3307 goto bnx_reset_exit; 3308 } 3309 } 3310 3311 /* Make sure byte swapping is properly configured. */ 3312 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3313 if (val != 0x01020304) { 3314 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3315 __FILE__, __LINE__); 3316 rc = ENODEV; 3317 goto bnx_reset_exit; 3318 } 3319 3320 /* Just completed a reset, assume that firmware is running again. */ 3321 sc->bnx_fw_timed_out = 0; 3322 3323 /* Wait for the firmware to finish its initialization. */ 3324 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3325 if (rc) 3326 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3327 "initialization!\n", __FILE__, __LINE__); 3328 3329 bnx_reset_exit: 3330 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3331 3332 return (rc); 3333 } 3334 3335 int 3336 bnx_chipinit(struct bnx_softc *sc) 3337 { 3338 struct pci_attach_args *pa = &(sc->bnx_pa); 3339 u_int32_t val; 3340 int rc = 0; 3341 3342 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3343 3344 /* Make sure the interrupt is not active. */ 3345 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3346 3347 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3348 /* channels and PCI clock compensation delay. */ 3349 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3350 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3351 #if BYTE_ORDER == BIG_ENDIAN 3352 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3353 #endif 3354 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3355 DMA_READ_CHANS << 12 | 3356 DMA_WRITE_CHANS << 16; 3357 3358 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3359 3360 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3361 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3362 3363 /* 3364 * This setting resolves a problem observed on certain Intel PCI 3365 * chipsets that cannot handle multiple outstanding DMA operations. 3366 * See errata E9_5706A1_65. 3367 */ 3368 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3369 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3370 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3371 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3372 3373 REG_WR(sc, BNX_DMA_CONFIG, val); 3374 3375 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3376 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3377 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3378 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3379 val & ~0x20000); 3380 } 3381 3382 /* Enable the RX_V2P and Context state machines before access. */ 3383 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3384 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3385 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3386 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3387 3388 /* Initialize context mapping and zero out the quick contexts. */ 3389 bnx_init_context(sc); 3390 3391 /* Initialize the on-boards CPUs */ 3392 bnx_init_cpus(sc); 3393 3394 /* Prepare NVRAM for access. */ 3395 if (bnx_init_nvram(sc)) { 3396 rc = ENODEV; 3397 goto bnx_chipinit_exit; 3398 } 3399 3400 /* Set the kernel bypass block size */ 3401 val = REG_RD(sc, BNX_MQ_CONFIG); 3402 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3403 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3404 3405 /* Enable bins used on the 5709. */ 3406 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3407 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3408 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3409 val |= BNX_MQ_CONFIG_HALT_DIS; 3410 } 3411 3412 REG_WR(sc, BNX_MQ_CONFIG, val); 3413 3414 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3415 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3416 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3417 3418 val = (BCM_PAGE_BITS - 8) << 24; 3419 REG_WR(sc, BNX_RV2P_CONFIG, val); 3420 3421 /* Configure page size. */ 3422 val = REG_RD(sc, BNX_TBDR_CONFIG); 3423 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3424 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3425 REG_WR(sc, BNX_TBDR_CONFIG, val); 3426 3427 #if 0 3428 /* Set the perfect match control register to default. */ 3429 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3430 #endif 3431 3432 bnx_chipinit_exit: 3433 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3434 3435 return(rc); 3436 } 3437 3438 /****************************************************************************/ 3439 /* Initialize the controller in preparation to send/receive traffic. */ 3440 /* */ 3441 /* Returns: */ 3442 /* 0 for success, positive value for failure. */ 3443 /****************************************************************************/ 3444 int 3445 bnx_blockinit(struct bnx_softc *sc) 3446 { 3447 u_int32_t reg, val; 3448 int rc = 0; 3449 3450 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3451 3452 /* Load the hardware default MAC address. */ 3453 bnx_set_mac_addr(sc); 3454 3455 /* Set the Ethernet backoff seed value */ 3456 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3457 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3458 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3459 3460 sc->last_status_idx = 0; 3461 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3462 3463 /* Set up link change interrupt generation. */ 3464 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3465 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3466 3467 /* Program the physical address of the status block. */ 3468 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 3469 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3470 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 3471 3472 /* Program the physical address of the statistics block. */ 3473 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3474 (u_int32_t)(sc->stats_block_paddr)); 3475 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3476 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 3477 3478 /* Program various host coalescing parameters. */ 3479 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3480 << 16) | sc->bnx_tx_quick_cons_trip); 3481 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3482 << 16) | sc->bnx_rx_quick_cons_trip); 3483 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3484 sc->bnx_comp_prod_trip); 3485 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3486 sc->bnx_tx_ticks); 3487 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3488 sc->bnx_rx_ticks); 3489 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3490 sc->bnx_com_ticks); 3491 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3492 sc->bnx_cmd_ticks); 3493 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3494 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3495 REG_WR(sc, BNX_HC_CONFIG, 3496 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3497 BNX_HC_CONFIG_COLLECT_STATS)); 3498 3499 /* Clear the internal statistics counters. */ 3500 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3501 3502 /* Verify that bootcode is running. */ 3503 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3504 3505 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3506 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3507 __FILE__, __LINE__); reg = 0); 3508 3509 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3510 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3511 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3512 "Expected: 08%08X\n", __FILE__, __LINE__, 3513 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3514 BNX_DEV_INFO_SIGNATURE_MAGIC); 3515 rc = ENODEV; 3516 goto bnx_blockinit_exit; 3517 } 3518 3519 /* Check if any management firmware is running. */ 3520 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3521 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3522 BNX_PORT_FEATURE_IMD_ENABLED)) { 3523 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3524 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3525 } 3526 3527 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3528 BNX_DEV_INFO_BC_REV); 3529 3530 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3531 3532 /* Enable DMA */ 3533 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3534 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3535 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3536 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3537 } 3538 3539 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3540 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3541 3542 /* Enable link state change interrupt generation. */ 3543 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3544 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3545 BNX_MISC_ENABLE_DEFAULT_XI); 3546 } else 3547 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3548 3549 /* Enable all remaining blocks in the MAC. */ 3550 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3551 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3552 DELAY(20); 3553 3554 bnx_blockinit_exit: 3555 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3556 3557 return (rc); 3558 } 3559 3560 static int 3561 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, u_int16_t *prod, 3562 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3563 { 3564 bus_dmamap_t map; 3565 struct rx_bd *rxbd; 3566 u_int32_t addr; 3567 int i; 3568 #ifdef BNX_DEBUG 3569 u_int16_t debug_chain_prod = *chain_prod; 3570 #endif 3571 u_int16_t first_chain_prod; 3572 3573 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3574 3575 /* Map the mbuf cluster into device memory. */ 3576 map = sc->rx_mbuf_map[*chain_prod]; 3577 first_chain_prod = *chain_prod; 3578 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3579 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3580 __FILE__, __LINE__); 3581 3582 m_freem(m_new); 3583 3584 DBRUNIF(1, sc->rx_mbuf_alloc--); 3585 3586 return ENOBUFS; 3587 } 3588 /* Make sure there is room in the receive chain. */ 3589 if (map->dm_nsegs > sc->free_rx_bd) { 3590 bus_dmamap_unload(sc->bnx_dmatag, map); 3591 m_freem(m_new); 3592 return EFBIG; 3593 } 3594 #ifdef BNX_DEBUG 3595 /* Track the distribution of buffer segments. */ 3596 sc->rx_mbuf_segs[map->dm_nsegs]++; 3597 #endif 3598 3599 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3600 BUS_DMASYNC_PREREAD); 3601 3602 /* Update some debug statistics counters */ 3603 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3604 sc->rx_low_watermark = sc->free_rx_bd); 3605 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3606 3607 /* 3608 * Setup the rx_bd for the first segment 3609 */ 3610 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3611 3612 addr = (u_int32_t)(map->dm_segs[0].ds_addr); 3613 rxbd->rx_bd_haddr_lo = htole32(addr); 3614 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3615 rxbd->rx_bd_haddr_hi = htole32(addr); 3616 rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); 3617 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3618 *prod_bseq += map->dm_segs[0].ds_len; 3619 bus_dmamap_sync(sc->bnx_dmatag, 3620 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3621 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3622 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3623 3624 for (i = 1; i < map->dm_nsegs; i++) { 3625 *prod = NEXT_RX_BD(*prod); 3626 *chain_prod = RX_CHAIN_IDX(*prod); 3627 3628 rxbd = 3629 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3630 3631 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 3632 rxbd->rx_bd_haddr_lo = htole32(addr); 3633 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3634 rxbd->rx_bd_haddr_hi = htole32(addr); 3635 rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); 3636 rxbd->rx_bd_flags = 0; 3637 *prod_bseq += map->dm_segs[i].ds_len; 3638 bus_dmamap_sync(sc->bnx_dmatag, 3639 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3640 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3641 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3642 } 3643 3644 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3645 bus_dmamap_sync(sc->bnx_dmatag, 3646 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3647 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3648 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3649 3650 /* 3651 * Save the mbuf, ajust the map pointer (swap map for first and 3652 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3653 * and update counter. 3654 */ 3655 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3656 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3657 sc->rx_mbuf_map[*chain_prod] = map; 3658 sc->free_rx_bd -= map->dm_nsegs; 3659 3660 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3661 map->dm_nsegs)); 3662 *prod = NEXT_RX_BD(*prod); 3663 *chain_prod = RX_CHAIN_IDX(*prod); 3664 3665 return 0; 3666 } 3667 3668 /****************************************************************************/ 3669 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3670 /* */ 3671 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3672 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3673 /* necessary. */ 3674 /* */ 3675 /* Returns: */ 3676 /* 0 for success, positive value for failure. */ 3677 /****************************************************************************/ 3678 int 3679 bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, 3680 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3681 { 3682 struct mbuf *m_new = NULL; 3683 int rc = 0; 3684 u_int16_t min_free_bd; 3685 3686 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3687 __func__); 3688 3689 /* Make sure the inputs are valid. */ 3690 DBRUNIF((*chain_prod > MAX_RX_BD), 3691 aprint_error_dev(sc->bnx_dev, 3692 "RX producer out of range: 0x%04X > 0x%04X\n", 3693 *chain_prod, (u_int16_t)MAX_RX_BD)); 3694 3695 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3696 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3697 *prod_bseq); 3698 3699 /* try to get in as many mbufs as possible */ 3700 if (sc->mbuf_alloc_size == MCLBYTES) 3701 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3702 else 3703 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3704 while (sc->free_rx_bd >= min_free_bd) { 3705 /* Simulate an mbuf allocation failure. */ 3706 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3707 aprint_error_dev(sc->bnx_dev, 3708 "Simulating mbuf allocation failure.\n"); 3709 sc->mbuf_sim_alloc_failed++; 3710 rc = ENOBUFS; 3711 goto bnx_get_buf_exit); 3712 3713 /* This is a new mbuf allocation. */ 3714 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3715 if (m_new == NULL) { 3716 DBPRINT(sc, BNX_WARN, 3717 "%s(%d): RX mbuf header allocation failed!\n", 3718 __FILE__, __LINE__); 3719 3720 sc->mbuf_alloc_failed++; 3721 3722 rc = ENOBUFS; 3723 goto bnx_get_buf_exit; 3724 } 3725 3726 DBRUNIF(1, sc->rx_mbuf_alloc++); 3727 3728 /* Simulate an mbuf cluster allocation failure. */ 3729 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3730 m_freem(m_new); 3731 sc->rx_mbuf_alloc--; 3732 sc->mbuf_alloc_failed++; 3733 sc->mbuf_sim_alloc_failed++; 3734 rc = ENOBUFS; 3735 goto bnx_get_buf_exit); 3736 3737 if (sc->mbuf_alloc_size == MCLBYTES) 3738 MCLGET(m_new, M_DONTWAIT); 3739 else 3740 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3741 M_DONTWAIT); 3742 if (!(m_new->m_flags & M_EXT)) { 3743 DBPRINT(sc, BNX_WARN, 3744 "%s(%d): RX mbuf chain allocation failed!\n", 3745 __FILE__, __LINE__); 3746 3747 m_freem(m_new); 3748 3749 DBRUNIF(1, sc->rx_mbuf_alloc--); 3750 sc->mbuf_alloc_failed++; 3751 3752 rc = ENOBUFS; 3753 goto bnx_get_buf_exit; 3754 } 3755 3756 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3757 if (rc != 0) 3758 goto bnx_get_buf_exit; 3759 } 3760 3761 bnx_get_buf_exit: 3762 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3763 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3764 *chain_prod, *prod_bseq); 3765 3766 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3767 __func__); 3768 3769 return(rc); 3770 } 3771 3772 int 3773 bnx_alloc_pkts(struct bnx_softc *sc) 3774 { 3775 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3776 struct bnx_pkt *pkt; 3777 int i; 3778 3779 for (i = 0; i < 4; i++) { /* magic! */ 3780 pkt = pool_get(bnx_tx_pool, PR_NOWAIT); 3781 if (pkt == NULL) 3782 break; 3783 3784 if (bus_dmamap_create(sc->bnx_dmatag, 3785 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3786 MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 3787 &pkt->pkt_dmamap) != 0) 3788 goto put; 3789 3790 if (!ISSET(ifp->if_flags, IFF_UP)) 3791 goto stopping; 3792 3793 mutex_enter(&sc->tx_pkt_mtx); 3794 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3795 sc->tx_pkt_count++; 3796 mutex_exit(&sc->tx_pkt_mtx); 3797 } 3798 3799 return (i == 0) ? ENOMEM : 0; 3800 3801 stopping: 3802 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3803 put: 3804 pool_put(bnx_tx_pool, pkt); 3805 return (i == 0) ? ENOMEM : 0; 3806 } 3807 3808 /****************************************************************************/ 3809 /* Initialize the TX context memory. */ 3810 /* */ 3811 /* Returns: */ 3812 /* Nothing */ 3813 /****************************************************************************/ 3814 void 3815 bnx_init_tx_context(struct bnx_softc *sc) 3816 { 3817 u_int32_t val; 3818 3819 /* Initialize the context ID for an L2 TX chain. */ 3820 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3821 /* Set the CID type to support an L2 connection. */ 3822 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3823 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 3824 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3825 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 3826 3827 /* Point the hardware to the first page in the chain. */ 3828 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3829 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3830 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 3831 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3832 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3833 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 3834 } else { 3835 /* Set the CID type to support an L2 connection. */ 3836 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3837 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3838 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3839 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3840 3841 /* Point the hardware to the first page in the chain. */ 3842 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3843 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3844 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3845 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3846 } 3847 } 3848 3849 3850 /****************************************************************************/ 3851 /* Allocate memory and initialize the TX data structures. */ 3852 /* */ 3853 /* Returns: */ 3854 /* 0 for success, positive value for failure. */ 3855 /****************************************************************************/ 3856 int 3857 bnx_init_tx_chain(struct bnx_softc *sc) 3858 { 3859 struct tx_bd *txbd; 3860 u_int32_t addr; 3861 int i, rc = 0; 3862 3863 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3864 3865 /* Force an allocation of some dmamaps for tx up front */ 3866 bnx_alloc_pkts(sc); 3867 3868 /* Set the initial TX producer/consumer indices. */ 3869 sc->tx_prod = 0; 3870 sc->tx_cons = 0; 3871 sc->tx_prod_bseq = 0; 3872 sc->used_tx_bd = 0; 3873 sc->max_tx_bd = USABLE_TX_BD; 3874 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3875 DBRUNIF(1, sc->tx_full_count = 0); 3876 3877 /* 3878 * The NetXtreme II supports a linked-list structure called 3879 * a Buffer Descriptor Chain (or BD chain). A BD chain 3880 * consists of a series of 1 or more chain pages, each of which 3881 * consists of a fixed number of BD entries. 3882 * The last BD entry on each page is a pointer to the next page 3883 * in the chain, and the last pointer in the BD chain 3884 * points back to the beginning of the chain. 3885 */ 3886 3887 /* Set the TX next pointer chain entries. */ 3888 for (i = 0; i < TX_PAGES; i++) { 3889 int j; 3890 3891 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3892 3893 /* Check if we've reached the last page. */ 3894 if (i == (TX_PAGES - 1)) 3895 j = 0; 3896 else 3897 j = i + 1; 3898 3899 addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); 3900 txbd->tx_bd_haddr_lo = htole32(addr); 3901 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3902 txbd->tx_bd_haddr_hi = htole32(addr); 3903 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3904 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3905 } 3906 3907 /* 3908 * Initialize the context ID for an L2 TX chain. 3909 */ 3910 bnx_init_tx_context(sc); 3911 3912 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3913 3914 return(rc); 3915 } 3916 3917 /****************************************************************************/ 3918 /* Free memory and clear the TX data structures. */ 3919 /* */ 3920 /* Returns: */ 3921 /* Nothing. */ 3922 /****************************************************************************/ 3923 void 3924 bnx_free_tx_chain(struct bnx_softc *sc) 3925 { 3926 struct bnx_pkt *pkt; 3927 int i; 3928 3929 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3930 3931 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3932 mutex_enter(&sc->tx_pkt_mtx); 3933 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 3934 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 3935 mutex_exit(&sc->tx_pkt_mtx); 3936 3937 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 3938 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3939 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 3940 3941 m_freem(pkt->pkt_mbuf); 3942 DBRUNIF(1, sc->tx_mbuf_alloc--); 3943 3944 mutex_enter(&sc->tx_pkt_mtx); 3945 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3946 } 3947 3948 /* Destroy all the dmamaps we allocated for TX */ 3949 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 3950 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 3951 sc->tx_pkt_count--; 3952 mutex_exit(&sc->tx_pkt_mtx); 3953 3954 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3955 pool_put(bnx_tx_pool, pkt); 3956 3957 mutex_enter(&sc->tx_pkt_mtx); 3958 } 3959 mutex_exit(&sc->tx_pkt_mtx); 3960 3961 3962 3963 /* Clear each TX chain page. */ 3964 for (i = 0; i < TX_PAGES; i++) { 3965 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 3966 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3967 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3968 } 3969 3970 sc->used_tx_bd = 0; 3971 3972 /* Check if we lost any mbufs in the process. */ 3973 DBRUNIF((sc->tx_mbuf_alloc), 3974 aprint_error_dev(sc->bnx_dev, 3975 "Memory leak! Lost %d mbufs from tx chain!\n", 3976 sc->tx_mbuf_alloc)); 3977 3978 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3979 } 3980 3981 /****************************************************************************/ 3982 /* Initialize the RX context memory. */ 3983 /* */ 3984 /* Returns: */ 3985 /* Nothing */ 3986 /****************************************************************************/ 3987 void 3988 bnx_init_rx_context(struct bnx_softc *sc) 3989 { 3990 u_int32_t val; 3991 3992 /* Initialize the context ID for an L2 RX chain. */ 3993 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 3994 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 3995 3996 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3997 u_int32_t lo_water, hi_water; 3998 3999 lo_water = BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT; 4000 hi_water = USABLE_RX_BD / 4; 4001 4002 lo_water /= BNX_L2CTX_RX_LO_WATER_MARK_SCALE; 4003 hi_water /= BNX_L2CTX_RX_HI_WATER_MARK_SCALE; 4004 4005 if (hi_water > 0xf) 4006 hi_water = 0xf; 4007 else if (hi_water == 0) 4008 lo_water = 0; 4009 val |= lo_water | 4010 (hi_water << BNX_L2CTX_RX_HI_WATER_MARK_SHIFT); 4011 } 4012 4013 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4014 4015 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4016 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4017 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4018 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4019 } 4020 4021 /* Point the hardware to the first page in the chain. */ 4022 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 4023 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4024 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 4025 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4026 } 4027 4028 /****************************************************************************/ 4029 /* Allocate memory and initialize the RX data structures. */ 4030 /* */ 4031 /* Returns: */ 4032 /* 0 for success, positive value for failure. */ 4033 /****************************************************************************/ 4034 int 4035 bnx_init_rx_chain(struct bnx_softc *sc) 4036 { 4037 struct rx_bd *rxbd; 4038 int i, rc = 0; 4039 u_int16_t prod, chain_prod; 4040 u_int32_t prod_bseq, addr; 4041 4042 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4043 4044 /* Initialize the RX producer and consumer indices. */ 4045 sc->rx_prod = 0; 4046 sc->rx_cons = 0; 4047 sc->rx_prod_bseq = 0; 4048 sc->free_rx_bd = USABLE_RX_BD; 4049 sc->max_rx_bd = USABLE_RX_BD; 4050 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4051 DBRUNIF(1, sc->rx_empty_count = 0); 4052 4053 /* Initialize the RX next pointer chain entries. */ 4054 for (i = 0; i < RX_PAGES; i++) { 4055 int j; 4056 4057 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4058 4059 /* Check if we've reached the last page. */ 4060 if (i == (RX_PAGES - 1)) 4061 j = 0; 4062 else 4063 j = i + 1; 4064 4065 /* Setup the chain page pointers. */ 4066 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 4067 rxbd->rx_bd_haddr_hi = htole32(addr); 4068 addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); 4069 rxbd->rx_bd_haddr_lo = htole32(addr); 4070 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4071 0, BNX_RX_CHAIN_PAGE_SZ, 4072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4073 } 4074 4075 /* Allocate mbuf clusters for the rx_bd chain. */ 4076 prod = prod_bseq = 0; 4077 chain_prod = RX_CHAIN_IDX(prod); 4078 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4079 BNX_PRINTF(sc, 4080 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4081 } 4082 4083 /* Save the RX chain producer index. */ 4084 sc->rx_prod = prod; 4085 sc->rx_prod_bseq = prod_bseq; 4086 4087 for (i = 0; i < RX_PAGES; i++) 4088 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4089 sc->rx_bd_chain_map[i]->dm_mapsize, 4090 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4091 4092 /* Tell the chip about the waiting rx_bd's. */ 4093 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4094 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4095 4096 bnx_init_rx_context(sc); 4097 4098 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4099 4100 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4101 4102 return(rc); 4103 } 4104 4105 /****************************************************************************/ 4106 /* Free memory and clear the RX data structures. */ 4107 /* */ 4108 /* Returns: */ 4109 /* Nothing. */ 4110 /****************************************************************************/ 4111 void 4112 bnx_free_rx_chain(struct bnx_softc *sc) 4113 { 4114 int i; 4115 4116 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4117 4118 /* Free any mbufs still in the RX mbuf chain. */ 4119 for (i = 0; i < TOTAL_RX_BD; i++) { 4120 if (sc->rx_mbuf_ptr[i] != NULL) { 4121 if (sc->rx_mbuf_map[i] != NULL) { 4122 bus_dmamap_sync(sc->bnx_dmatag, 4123 sc->rx_mbuf_map[i], 0, 4124 sc->rx_mbuf_map[i]->dm_mapsize, 4125 BUS_DMASYNC_POSTREAD); 4126 bus_dmamap_unload(sc->bnx_dmatag, 4127 sc->rx_mbuf_map[i]); 4128 } 4129 m_freem(sc->rx_mbuf_ptr[i]); 4130 sc->rx_mbuf_ptr[i] = NULL; 4131 DBRUNIF(1, sc->rx_mbuf_alloc--); 4132 } 4133 } 4134 4135 /* Clear each RX chain page. */ 4136 for (i = 0; i < RX_PAGES; i++) 4137 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4138 4139 sc->free_rx_bd = sc->max_rx_bd; 4140 4141 /* Check if we lost any mbufs in the process. */ 4142 DBRUNIF((sc->rx_mbuf_alloc), 4143 aprint_error_dev(sc->bnx_dev, 4144 "Memory leak! Lost %d mbufs from rx chain!\n", 4145 sc->rx_mbuf_alloc)); 4146 4147 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4148 } 4149 4150 /****************************************************************************/ 4151 /* Handles PHY generated interrupt events. */ 4152 /* */ 4153 /* Returns: */ 4154 /* Nothing. */ 4155 /****************************************************************************/ 4156 void 4157 bnx_phy_intr(struct bnx_softc *sc) 4158 { 4159 u_int32_t new_link_state, old_link_state; 4160 4161 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4162 BUS_DMASYNC_POSTREAD); 4163 new_link_state = sc->status_block->status_attn_bits & 4164 STATUS_ATTN_BITS_LINK_STATE; 4165 old_link_state = sc->status_block->status_attn_bits_ack & 4166 STATUS_ATTN_BITS_LINK_STATE; 4167 4168 /* Handle any changes if the link state has changed. */ 4169 if (new_link_state != old_link_state) { 4170 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4171 4172 callout_stop(&sc->bnx_timeout); 4173 bnx_tick(sc); 4174 4175 /* Update the status_attn_bits_ack field in the status block. */ 4176 if (new_link_state) { 4177 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4178 STATUS_ATTN_BITS_LINK_STATE); 4179 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4180 } else { 4181 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4182 STATUS_ATTN_BITS_LINK_STATE); 4183 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4184 } 4185 } 4186 4187 /* Acknowledge the link change interrupt. */ 4188 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4189 } 4190 4191 /****************************************************************************/ 4192 /* Handles received frame interrupt events. */ 4193 /* */ 4194 /* Returns: */ 4195 /* Nothing. */ 4196 /****************************************************************************/ 4197 void 4198 bnx_rx_intr(struct bnx_softc *sc) 4199 { 4200 struct status_block *sblk = sc->status_block; 4201 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4202 u_int16_t hw_cons, sw_cons, sw_chain_cons; 4203 u_int16_t sw_prod, sw_chain_prod; 4204 u_int32_t sw_prod_bseq; 4205 struct l2_fhdr *l2fhdr; 4206 int i; 4207 4208 DBRUNIF(1, sc->rx_interrupts++); 4209 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4210 BUS_DMASYNC_POSTREAD); 4211 4212 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4213 for (i = 0; i < RX_PAGES; i++) 4214 bus_dmamap_sync(sc->bnx_dmatag, 4215 sc->rx_bd_chain_map[i], 0, 4216 sc->rx_bd_chain_map[i]->dm_mapsize, 4217 BUS_DMASYNC_POSTWRITE); 4218 4219 /* Get the hardware's view of the RX consumer index. */ 4220 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4221 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4222 hw_cons++; 4223 4224 /* Get working copies of the driver's view of the RX indices. */ 4225 sw_cons = sc->rx_cons; 4226 sw_prod = sc->rx_prod; 4227 sw_prod_bseq = sc->rx_prod_bseq; 4228 4229 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4230 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4231 __func__, sw_prod, sw_cons, sw_prod_bseq); 4232 4233 /* Prevent speculative reads from getting ahead of the status block. */ 4234 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4235 BUS_SPACE_BARRIER_READ); 4236 4237 /* Update some debug statistics counters */ 4238 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4239 sc->rx_low_watermark = sc->free_rx_bd); 4240 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4241 4242 /* 4243 * Scan through the receive chain as long 4244 * as there is work to do. 4245 */ 4246 while (sw_cons != hw_cons) { 4247 struct mbuf *m; 4248 struct rx_bd *rxbd; 4249 unsigned int len; 4250 u_int32_t status; 4251 4252 /* Convert the producer/consumer indices to an actual 4253 * rx_bd index. 4254 */ 4255 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4256 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4257 4258 /* Get the used rx_bd. */ 4259 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4260 sc->free_rx_bd++; 4261 4262 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4263 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4264 4265 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4266 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4267 #ifdef DIAGNOSTIC 4268 /* Validate that this is the last rx_bd. */ 4269 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4270 printf("%s: Unexpected mbuf found in " 4271 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4272 sw_chain_cons); 4273 } 4274 #endif 4275 4276 /* DRC - ToDo: If the received packet is small, say less 4277 * than 128 bytes, allocate a new mbuf here, 4278 * copy the data to that mbuf, and recycle 4279 * the mapped jumbo frame. 4280 */ 4281 4282 /* Unmap the mbuf from DMA space. */ 4283 #ifdef DIAGNOSTIC 4284 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4285 printf("invalid map sw_cons 0x%x " 4286 "sw_prod 0x%x " 4287 "sw_chain_cons 0x%x " 4288 "sw_chain_prod 0x%x " 4289 "hw_cons 0x%x " 4290 "TOTAL_RX_BD_PER_PAGE 0x%x " 4291 "TOTAL_RX_BD 0x%x\n", 4292 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4293 hw_cons, 4294 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4295 } 4296 #endif 4297 bus_dmamap_sync(sc->bnx_dmatag, 4298 sc->rx_mbuf_map[sw_chain_cons], 0, 4299 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4300 BUS_DMASYNC_POSTREAD); 4301 bus_dmamap_unload(sc->bnx_dmatag, 4302 sc->rx_mbuf_map[sw_chain_cons]); 4303 4304 /* Remove the mbuf from the driver's chain. */ 4305 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4306 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4307 4308 /* 4309 * Frames received on the NetXteme II are prepended 4310 * with the l2_fhdr structure which provides status 4311 * information about the received frame (including 4312 * VLAN tags and checksum info) and are also 4313 * automatically adjusted to align the IP header 4314 * (i.e. two null bytes are inserted before the 4315 * Ethernet header). 4316 */ 4317 l2fhdr = mtod(m, struct l2_fhdr *); 4318 4319 len = l2fhdr->l2_fhdr_pkt_len; 4320 status = l2fhdr->l2_fhdr_status; 4321 4322 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4323 aprint_error("Simulating l2_fhdr status error.\n"); 4324 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4325 4326 /* Watch for unusual sized frames. */ 4327 DBRUNIF(((len < BNX_MIN_MTU) || 4328 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4329 aprint_error_dev(sc->bnx_dev, 4330 "Unusual frame size found. " 4331 "Min(%d), Actual(%d), Max(%d)\n", 4332 (int)BNX_MIN_MTU, len, 4333 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4334 4335 bnx_dump_mbuf(sc, m); 4336 bnx_breakpoint(sc)); 4337 4338 len -= ETHER_CRC_LEN; 4339 4340 /* Check the received frame for errors. */ 4341 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4342 L2_FHDR_ERRORS_PHY_DECODE | 4343 L2_FHDR_ERRORS_ALIGNMENT | 4344 L2_FHDR_ERRORS_TOO_SHORT | 4345 L2_FHDR_ERRORS_GIANT_FRAME)) || 4346 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4347 len > 4348 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4349 ifp->if_ierrors++; 4350 DBRUNIF(1, sc->l2fhdr_status_errors++); 4351 4352 /* Reuse the mbuf for a new frame. */ 4353 if (bnx_add_buf(sc, m, &sw_prod, 4354 &sw_chain_prod, &sw_prod_bseq)) { 4355 DBRUNIF(1, bnx_breakpoint(sc)); 4356 panic("%s: Can't reuse RX mbuf!\n", 4357 device_xname(sc->bnx_dev)); 4358 } 4359 continue; 4360 } 4361 4362 /* 4363 * Get a new mbuf for the rx_bd. If no new 4364 * mbufs are available then reuse the current mbuf, 4365 * log an ierror on the interface, and generate 4366 * an error in the system log. 4367 */ 4368 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4369 &sw_prod_bseq)) { 4370 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4371 "Failed to allocate " 4372 "new mbuf, incoming frame dropped!\n")); 4373 4374 ifp->if_ierrors++; 4375 4376 /* Try and reuse the exisitng mbuf. */ 4377 if (bnx_add_buf(sc, m, &sw_prod, 4378 &sw_chain_prod, &sw_prod_bseq)) { 4379 DBRUNIF(1, bnx_breakpoint(sc)); 4380 panic("%s: Double mbuf allocation " 4381 "failure!", 4382 device_xname(sc->bnx_dev)); 4383 } 4384 continue; 4385 } 4386 4387 /* Skip over the l2_fhdr when passing the data up 4388 * the stack. 4389 */ 4390 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4391 4392 /* Adjust the pckt length to match the received data. */ 4393 m->m_pkthdr.len = m->m_len = len; 4394 4395 /* Send the packet to the appropriate interface. */ 4396 m->m_pkthdr.rcvif = ifp; 4397 4398 DBRUN(BNX_VERBOSE_RECV, 4399 struct ether_header *eh; 4400 eh = mtod(m, struct ether_header *); 4401 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4402 __func__, ether_sprintf(eh->ether_dhost), 4403 ether_sprintf(eh->ether_shost), 4404 htons(eh->ether_type))); 4405 4406 /* Validate the checksum. */ 4407 4408 /* Check for an IP datagram. */ 4409 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4410 /* Check if the IP checksum is valid. */ 4411 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 4412 == 0) 4413 m->m_pkthdr.csum_flags |= 4414 M_CSUM_IPv4; 4415 #ifdef BNX_DEBUG 4416 else 4417 DBPRINT(sc, BNX_WARN_SEND, 4418 "%s(): Invalid IP checksum " 4419 "= 0x%04X!\n", 4420 __func__, 4421 l2fhdr->l2_fhdr_ip_xsum 4422 ); 4423 #endif 4424 } 4425 4426 /* Check for a valid TCP/UDP frame. */ 4427 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4428 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4429 /* Check for a good TCP/UDP checksum. */ 4430 if ((status & 4431 (L2_FHDR_ERRORS_TCP_XSUM | 4432 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4433 m->m_pkthdr.csum_flags |= 4434 M_CSUM_TCPv4 | 4435 M_CSUM_UDPv4; 4436 } else { 4437 DBPRINT(sc, BNX_WARN_SEND, 4438 "%s(): Invalid TCP/UDP " 4439 "checksum = 0x%04X!\n", 4440 __func__, 4441 l2fhdr->l2_fhdr_tcp_udp_xsum); 4442 } 4443 } 4444 4445 /* 4446 * If we received a packet with a vlan tag, 4447 * attach that information to the packet. 4448 */ 4449 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4450 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4451 VLAN_INPUT_TAG(ifp, m, 4452 l2fhdr->l2_fhdr_vlan_tag, 4453 continue); 4454 } 4455 4456 /* 4457 * Handle BPF listeners. Let the BPF 4458 * user see the packet. 4459 */ 4460 bpf_mtap(ifp, m); 4461 4462 /* Pass the mbuf off to the upper layers. */ 4463 ifp->if_ipackets++; 4464 DBPRINT(sc, BNX_VERBOSE_RECV, 4465 "%s(): Passing received frame up.\n", __func__); 4466 (*ifp->if_input)(ifp, m); 4467 DBRUNIF(1, sc->rx_mbuf_alloc--); 4468 4469 } 4470 4471 sw_cons = NEXT_RX_BD(sw_cons); 4472 4473 /* Refresh hw_cons to see if there's new work */ 4474 if (sw_cons == hw_cons) { 4475 hw_cons = sc->hw_rx_cons = 4476 sblk->status_rx_quick_consumer_index0; 4477 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4478 USABLE_RX_BD_PER_PAGE) 4479 hw_cons++; 4480 } 4481 4482 /* Prevent speculative reads from getting ahead of 4483 * the status block. 4484 */ 4485 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4486 BUS_SPACE_BARRIER_READ); 4487 } 4488 4489 for (i = 0; i < RX_PAGES; i++) 4490 bus_dmamap_sync(sc->bnx_dmatag, 4491 sc->rx_bd_chain_map[i], 0, 4492 sc->rx_bd_chain_map[i]->dm_mapsize, 4493 BUS_DMASYNC_PREWRITE); 4494 4495 sc->rx_cons = sw_cons; 4496 sc->rx_prod = sw_prod; 4497 sc->rx_prod_bseq = sw_prod_bseq; 4498 4499 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4500 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4501 4502 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4503 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4504 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4505 } 4506 4507 /****************************************************************************/ 4508 /* Handles transmit completion interrupt events. */ 4509 /* */ 4510 /* Returns: */ 4511 /* Nothing. */ 4512 /****************************************************************************/ 4513 void 4514 bnx_tx_intr(struct bnx_softc *sc) 4515 { 4516 struct status_block *sblk = sc->status_block; 4517 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4518 struct bnx_pkt *pkt; 4519 bus_dmamap_t map; 4520 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4521 4522 DBRUNIF(1, sc->tx_interrupts++); 4523 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4524 BUS_DMASYNC_POSTREAD); 4525 4526 /* Get the hardware's view of the TX consumer index. */ 4527 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4528 4529 /* Skip to the next entry if this is a chain page pointer. */ 4530 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4531 hw_tx_cons++; 4532 4533 sw_tx_cons = sc->tx_cons; 4534 4535 /* Prevent speculative reads from getting ahead of the status block. */ 4536 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4537 BUS_SPACE_BARRIER_READ); 4538 4539 /* Cycle through any completed TX chain page entries. */ 4540 while (sw_tx_cons != hw_tx_cons) { 4541 #ifdef BNX_DEBUG 4542 struct tx_bd *txbd = NULL; 4543 #endif 4544 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4545 4546 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4547 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4548 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4549 4550 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4551 aprint_error_dev(sc->bnx_dev, 4552 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4553 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4554 4555 DBRUNIF(1, txbd = &sc->tx_bd_chain 4556 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4557 4558 DBRUNIF((txbd == NULL), 4559 aprint_error_dev(sc->bnx_dev, 4560 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4561 bnx_breakpoint(sc)); 4562 4563 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4564 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4565 4566 4567 mutex_enter(&sc->tx_pkt_mtx); 4568 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4569 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4570 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4571 mutex_exit(&sc->tx_pkt_mtx); 4572 /* 4573 * Free the associated mbuf. Remember 4574 * that only the last tx_bd of a packet 4575 * has an mbuf pointer and DMA map. 4576 */ 4577 map = pkt->pkt_dmamap; 4578 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4579 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4580 bus_dmamap_unload(sc->bnx_dmatag, map); 4581 4582 m_freem(pkt->pkt_mbuf); 4583 DBRUNIF(1, sc->tx_mbuf_alloc--); 4584 4585 ifp->if_opackets++; 4586 4587 mutex_enter(&sc->tx_pkt_mtx); 4588 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4589 } 4590 mutex_exit(&sc->tx_pkt_mtx); 4591 4592 sc->used_tx_bd--; 4593 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4594 __FILE__, __LINE__, sc->used_tx_bd); 4595 4596 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4597 4598 /* Refresh hw_cons to see if there's new work. */ 4599 hw_tx_cons = sc->hw_tx_cons = 4600 sblk->status_tx_quick_consumer_index0; 4601 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4602 USABLE_TX_BD_PER_PAGE) 4603 hw_tx_cons++; 4604 4605 /* Prevent speculative reads from getting ahead of 4606 * the status block. 4607 */ 4608 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4609 BUS_SPACE_BARRIER_READ); 4610 } 4611 4612 /* Clear the TX timeout timer. */ 4613 ifp->if_timer = 0; 4614 4615 /* Clear the tx hardware queue full flag. */ 4616 if (sc->used_tx_bd < sc->max_tx_bd) { 4617 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4618 aprint_debug_dev(sc->bnx_dev, 4619 "Open TX chain! %d/%d (used/total)\n", 4620 sc->used_tx_bd, sc->max_tx_bd)); 4621 ifp->if_flags &= ~IFF_OACTIVE; 4622 } 4623 4624 sc->tx_cons = sw_tx_cons; 4625 } 4626 4627 /****************************************************************************/ 4628 /* Disables interrupt generation. */ 4629 /* */ 4630 /* Returns: */ 4631 /* Nothing. */ 4632 /****************************************************************************/ 4633 void 4634 bnx_disable_intr(struct bnx_softc *sc) 4635 { 4636 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4637 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4638 } 4639 4640 /****************************************************************************/ 4641 /* Enables interrupt generation. */ 4642 /* */ 4643 /* Returns: */ 4644 /* Nothing. */ 4645 /****************************************************************************/ 4646 void 4647 bnx_enable_intr(struct bnx_softc *sc) 4648 { 4649 u_int32_t val; 4650 4651 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4652 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4653 4654 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4655 sc->last_status_idx); 4656 4657 val = REG_RD(sc, BNX_HC_COMMAND); 4658 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4659 } 4660 4661 /****************************************************************************/ 4662 /* Handles controller initialization. */ 4663 /* */ 4664 /****************************************************************************/ 4665 int 4666 bnx_init(struct ifnet *ifp) 4667 { 4668 struct bnx_softc *sc = ifp->if_softc; 4669 u_int32_t ether_mtu; 4670 int s, error = 0; 4671 4672 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4673 4674 s = splnet(); 4675 4676 bnx_stop(ifp, 0); 4677 4678 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4679 aprint_error_dev(sc->bnx_dev, 4680 "Controller reset failed!\n"); 4681 goto bnx_init_exit; 4682 } 4683 4684 if ((error = bnx_chipinit(sc)) != 0) { 4685 aprint_error_dev(sc->bnx_dev, 4686 "Controller initialization failed!\n"); 4687 goto bnx_init_exit; 4688 } 4689 4690 if ((error = bnx_blockinit(sc)) != 0) { 4691 aprint_error_dev(sc->bnx_dev, 4692 "Block initialization failed!\n"); 4693 goto bnx_init_exit; 4694 } 4695 4696 /* Calculate and program the Ethernet MRU size. */ 4697 if (ifp->if_mtu <= ETHERMTU) { 4698 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4699 sc->mbuf_alloc_size = MCLBYTES; 4700 } else { 4701 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4702 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4703 } 4704 4705 4706 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4707 __func__, ether_mtu); 4708 4709 /* 4710 * Program the MRU and enable Jumbo frame 4711 * support. 4712 */ 4713 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4714 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4715 4716 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4717 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4718 4719 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4720 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4721 sc->mbuf_alloc_size, sc->max_frame_size); 4722 4723 /* Program appropriate promiscuous/multicast filtering. */ 4724 bnx_iff(sc); 4725 4726 /* Init RX buffer descriptor chain. */ 4727 bnx_init_rx_chain(sc); 4728 4729 /* Init TX buffer descriptor chain. */ 4730 bnx_init_tx_chain(sc); 4731 4732 /* Enable host interrupts. */ 4733 bnx_enable_intr(sc); 4734 4735 if ((error = ether_mediachange(ifp)) != 0) 4736 goto bnx_init_exit; 4737 4738 ifp->if_flags |= IFF_RUNNING; 4739 ifp->if_flags &= ~IFF_OACTIVE; 4740 4741 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4742 4743 bnx_init_exit: 4744 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4745 4746 splx(s); 4747 4748 return(error); 4749 } 4750 4751 /****************************************************************************/ 4752 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4753 /* memory visible to the controller. */ 4754 /* */ 4755 /* Returns: */ 4756 /* 0 for success, positive value for failure. */ 4757 /****************************************************************************/ 4758 int 4759 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4760 { 4761 struct bnx_pkt *pkt; 4762 bus_dmamap_t map; 4763 struct tx_bd *txbd = NULL; 4764 u_int16_t vlan_tag = 0, flags = 0; 4765 u_int16_t chain_prod, prod; 4766 #ifdef BNX_DEBUG 4767 u_int16_t debug_prod; 4768 #endif 4769 u_int32_t addr, prod_bseq; 4770 int i, error; 4771 struct m_tag *mtag; 4772 4773 again: 4774 mutex_enter(&sc->tx_pkt_mtx); 4775 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 4776 if (pkt == NULL) { 4777 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 4778 mutex_exit(&sc->tx_pkt_mtx); 4779 return ENETDOWN; 4780 } 4781 if (sc->tx_pkt_count <= TOTAL_TX_BD) { 4782 mutex_exit(&sc->tx_pkt_mtx); 4783 if (bnx_alloc_pkts(sc) == 0) 4784 goto again; 4785 } else { 4786 mutex_exit(&sc->tx_pkt_mtx); 4787 } 4788 return (ENOMEM); 4789 } 4790 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4791 mutex_exit(&sc->tx_pkt_mtx); 4792 4793 /* Transfer any checksum offload flags to the bd. */ 4794 if (m->m_pkthdr.csum_flags) { 4795 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 4796 flags |= TX_BD_FLAGS_IP_CKSUM; 4797 if (m->m_pkthdr.csum_flags & 4798 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4799 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4800 } 4801 4802 /* Transfer any VLAN tags to the bd. */ 4803 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m); 4804 if (mtag != NULL) { 4805 flags |= TX_BD_FLAGS_VLAN_TAG; 4806 vlan_tag = VLAN_TAG_VALUE(mtag); 4807 } 4808 4809 /* Map the mbuf into DMAable memory. */ 4810 prod = sc->tx_prod; 4811 chain_prod = TX_CHAIN_IDX(prod); 4812 map = pkt->pkt_dmamap; 4813 4814 /* Map the mbuf into our DMA address space. */ 4815 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 4816 if (error != 0) { 4817 aprint_error_dev(sc->bnx_dev, 4818 "Error mapping mbuf into TX chain!\n"); 4819 sc->tx_dma_map_failures++; 4820 goto maperr; 4821 } 4822 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4823 BUS_DMASYNC_PREWRITE); 4824 /* Make sure there's room in the chain */ 4825 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 4826 goto nospace; 4827 4828 /* prod points to an empty tx_bd at this point. */ 4829 prod_bseq = sc->tx_prod_bseq; 4830 #ifdef BNX_DEBUG 4831 debug_prod = chain_prod; 4832 #endif 4833 DBPRINT(sc, BNX_INFO_SEND, 4834 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4835 "prod_bseq = 0x%08X\n", 4836 __func__, prod, chain_prod, prod_bseq); 4837 4838 /* 4839 * Cycle through each mbuf segment that makes up 4840 * the outgoing frame, gathering the mapping info 4841 * for that segment and creating a tx_bd for the 4842 * mbuf. 4843 */ 4844 for (i = 0; i < map->dm_nsegs ; i++) { 4845 chain_prod = TX_CHAIN_IDX(prod); 4846 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4847 4848 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 4849 txbd->tx_bd_haddr_lo = htole32(addr); 4850 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4851 txbd->tx_bd_haddr_hi = htole32(addr); 4852 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 4853 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4854 txbd->tx_bd_flags = htole16(flags); 4855 prod_bseq += map->dm_segs[i].ds_len; 4856 if (i == 0) 4857 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4858 prod = NEXT_TX_BD(prod); 4859 } 4860 /* Set the END flag on the last TX buffer descriptor. */ 4861 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4862 4863 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 4864 4865 DBPRINT(sc, BNX_INFO_SEND, 4866 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4867 "prod_bseq = 0x%08X\n", 4868 __func__, prod, chain_prod, prod_bseq); 4869 4870 pkt->pkt_mbuf = m; 4871 pkt->pkt_end_desc = chain_prod; 4872 4873 mutex_enter(&sc->tx_pkt_mtx); 4874 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 4875 mutex_exit(&sc->tx_pkt_mtx); 4876 4877 sc->used_tx_bd += map->dm_nsegs; 4878 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4879 __FILE__, __LINE__, sc->used_tx_bd); 4880 4881 /* Update some debug statistics counters */ 4882 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4883 sc->tx_hi_watermark = sc->used_tx_bd); 4884 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 4885 DBRUNIF(1, sc->tx_mbuf_alloc++); 4886 4887 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4888 map->dm_nsegs)); 4889 4890 /* prod points to the next free tx_bd at this point. */ 4891 sc->tx_prod = prod; 4892 sc->tx_prod_bseq = prod_bseq; 4893 4894 return (0); 4895 4896 4897 nospace: 4898 bus_dmamap_unload(sc->bnx_dmatag, map); 4899 maperr: 4900 mutex_enter(&sc->tx_pkt_mtx); 4901 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4902 mutex_exit(&sc->tx_pkt_mtx); 4903 4904 return (ENOMEM); 4905 } 4906 4907 /****************************************************************************/ 4908 /* Main transmit routine. */ 4909 /* */ 4910 /* Returns: */ 4911 /* Nothing. */ 4912 /****************************************************************************/ 4913 void 4914 bnx_start(struct ifnet *ifp) 4915 { 4916 struct bnx_softc *sc = ifp->if_softc; 4917 struct mbuf *m_head = NULL; 4918 int count = 0; 4919 u_int16_t tx_prod, tx_chain_prod; 4920 4921 /* If there's no link or the transmit queue is empty then just exit. */ 4922 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 4923 DBPRINT(sc, BNX_INFO_SEND, 4924 "%s(): output active or device not running.\n", __func__); 4925 goto bnx_start_exit; 4926 } 4927 4928 /* prod points to the next free tx_bd. */ 4929 tx_prod = sc->tx_prod; 4930 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4931 4932 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 4933 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 4934 "used_tx %d max_tx %d\n", 4935 __func__, tx_prod, tx_chain_prod, sc->tx_prod_bseq, 4936 sc->used_tx_bd, sc->max_tx_bd); 4937 4938 /* 4939 * Keep adding entries while there is space in the ring. 4940 */ 4941 while (sc->used_tx_bd < sc->max_tx_bd) { 4942 /* Check for any frames to send. */ 4943 IFQ_POLL(&ifp->if_snd, m_head); 4944 if (m_head == NULL) 4945 break; 4946 4947 /* 4948 * Pack the data into the transmit ring. If we 4949 * don't have room, set the OACTIVE flag to wait 4950 * for the NIC to drain the chain. 4951 */ 4952 if (bnx_tx_encap(sc, m_head)) { 4953 ifp->if_flags |= IFF_OACTIVE; 4954 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 4955 "business! Total tx_bd used = %d\n", 4956 sc->used_tx_bd); 4957 break; 4958 } 4959 4960 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4961 count++; 4962 4963 /* Send a copy of the frame to any BPF listeners. */ 4964 bpf_mtap(ifp, m_head); 4965 } 4966 4967 if (count == 0) { 4968 /* no packets were dequeued */ 4969 DBPRINT(sc, BNX_VERBOSE_SEND, 4970 "%s(): No packets were dequeued\n", __func__); 4971 goto bnx_start_exit; 4972 } 4973 4974 /* Update the driver's counters. */ 4975 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4976 4977 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 4978 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, tx_prod, 4979 tx_chain_prod, sc->tx_prod_bseq); 4980 4981 /* Start the transmit. */ 4982 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4983 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4984 4985 /* Set the tx timeout. */ 4986 ifp->if_timer = BNX_TX_TIMEOUT; 4987 4988 bnx_start_exit: 4989 return; 4990 } 4991 4992 /****************************************************************************/ 4993 /* Handles any IOCTL calls from the operating system. */ 4994 /* */ 4995 /* Returns: */ 4996 /* 0 for success, positive value for failure. */ 4997 /****************************************************************************/ 4998 int 4999 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5000 { 5001 struct bnx_softc *sc = ifp->if_softc; 5002 struct ifreq *ifr = (struct ifreq *) data; 5003 struct mii_data *mii = &sc->bnx_mii; 5004 int s, error = 0; 5005 5006 s = splnet(); 5007 5008 switch (command) { 5009 case SIOCSIFFLAGS: 5010 if ((error = ifioctl_common(ifp, command, data)) != 0) 5011 break; 5012 /* XXX set an ifflags callback and let ether_ioctl 5013 * handle all of this. 5014 */ 5015 if (ifp->if_flags & IFF_UP) { 5016 if (ifp->if_flags & IFF_RUNNING) 5017 error = ENETRESET; 5018 else 5019 bnx_init(ifp); 5020 } else if (ifp->if_flags & IFF_RUNNING) 5021 bnx_stop(ifp, 1); 5022 break; 5023 5024 case SIOCSIFMEDIA: 5025 case SIOCGIFMEDIA: 5026 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5027 sc->bnx_phy_flags); 5028 5029 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5030 break; 5031 5032 default: 5033 error = ether_ioctl(ifp, command, data); 5034 } 5035 5036 if (error == ENETRESET) { 5037 if (ifp->if_flags & IFF_RUNNING) 5038 bnx_iff(sc); 5039 error = 0; 5040 } 5041 5042 splx(s); 5043 return (error); 5044 } 5045 5046 /****************************************************************************/ 5047 /* Transmit timeout handler. */ 5048 /* */ 5049 /* Returns: */ 5050 /* Nothing. */ 5051 /****************************************************************************/ 5052 void 5053 bnx_watchdog(struct ifnet *ifp) 5054 { 5055 struct bnx_softc *sc = ifp->if_softc; 5056 5057 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5058 bnx_dump_status_block(sc)); 5059 /* 5060 * If we are in this routine because of pause frames, then 5061 * don't reset the hardware. 5062 */ 5063 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5064 return; 5065 5066 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5067 5068 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5069 5070 bnx_init(ifp); 5071 5072 ifp->if_oerrors++; 5073 } 5074 5075 /* 5076 * Interrupt handler. 5077 */ 5078 /****************************************************************************/ 5079 /* Main interrupt entry point. Verifies that the controller generated the */ 5080 /* interrupt and then calls a separate routine for handle the various */ 5081 /* interrupt causes (PHY, TX, RX). */ 5082 /* */ 5083 /* Returns: */ 5084 /* 0 for success, positive value for failure. */ 5085 /****************************************************************************/ 5086 int 5087 bnx_intr(void *xsc) 5088 { 5089 struct bnx_softc *sc; 5090 struct ifnet *ifp; 5091 u_int32_t status_attn_bits; 5092 const struct status_block *sblk; 5093 5094 sc = xsc; 5095 if (!device_is_active(sc->bnx_dev)) 5096 return 0; 5097 5098 ifp = &sc->bnx_ec.ec_if; 5099 5100 DBRUNIF(1, sc->interrupts_generated++); 5101 5102 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5103 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 5104 5105 /* 5106 * If the hardware status block index 5107 * matches the last value read by the 5108 * driver and we haven't asserted our 5109 * interrupt then there's nothing to do. 5110 */ 5111 if ((sc->status_block->status_idx == sc->last_status_idx) && 5112 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 5113 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 5114 return (0); 5115 5116 /* Ack the interrupt and stop others from occuring. */ 5117 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5118 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5119 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5120 5121 /* Keep processing data as long as there is work to do. */ 5122 for (;;) { 5123 sblk = sc->status_block; 5124 status_attn_bits = sblk->status_attn_bits; 5125 5126 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5127 aprint_debug("Simulating unexpected status attention bit set."); 5128 status_attn_bits = status_attn_bits | 5129 STATUS_ATTN_BITS_PARITY_ERROR); 5130 5131 /* Was it a link change interrupt? */ 5132 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5133 (sblk->status_attn_bits_ack & 5134 STATUS_ATTN_BITS_LINK_STATE)) 5135 bnx_phy_intr(sc); 5136 5137 /* If any other attention is asserted then the chip is toast. */ 5138 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5139 (sblk->status_attn_bits_ack & 5140 ~STATUS_ATTN_BITS_LINK_STATE))) { 5141 DBRUN(1, sc->unexpected_attentions++); 5142 5143 BNX_PRINTF(sc, 5144 "Fatal attention detected: 0x%08X\n", 5145 sblk->status_attn_bits); 5146 5147 DBRUN(BNX_FATAL, 5148 if (bnx_debug_unexpected_attention == 0) 5149 bnx_breakpoint(sc)); 5150 5151 bnx_init(ifp); 5152 return (1); 5153 } 5154 5155 /* Check for any completed RX frames. */ 5156 if (sblk->status_rx_quick_consumer_index0 != 5157 sc->hw_rx_cons) 5158 bnx_rx_intr(sc); 5159 5160 /* Check for any completed TX frames. */ 5161 if (sblk->status_tx_quick_consumer_index0 != 5162 sc->hw_tx_cons) 5163 bnx_tx_intr(sc); 5164 5165 /* Save the status block index value for use during the 5166 * next interrupt. 5167 */ 5168 sc->last_status_idx = sblk->status_idx; 5169 5170 /* Prevent speculative reads from getting ahead of the 5171 * status block. 5172 */ 5173 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 5174 BUS_SPACE_BARRIER_READ); 5175 5176 /* If there's no work left then exit the isr. */ 5177 if ((sblk->status_rx_quick_consumer_index0 == 5178 sc->hw_rx_cons) && 5179 (sblk->status_tx_quick_consumer_index0 == 5180 sc->hw_tx_cons)) 5181 break; 5182 } 5183 5184 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5185 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 5186 5187 /* Re-enable interrupts. */ 5188 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5189 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5190 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5191 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5192 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5193 5194 /* Handle any frames that arrived while handling the interrupt. */ 5195 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 5196 bnx_start(ifp); 5197 5198 return (1); 5199 } 5200 5201 /****************************************************************************/ 5202 /* Programs the various packet receive modes (broadcast and multicast). */ 5203 /* */ 5204 /* Returns: */ 5205 /* Nothing. */ 5206 /****************************************************************************/ 5207 void 5208 bnx_iff(struct bnx_softc *sc) 5209 { 5210 struct ethercom *ec = &sc->bnx_ec; 5211 struct ifnet *ifp = &ec->ec_if; 5212 struct ether_multi *enm; 5213 struct ether_multistep step; 5214 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5215 u_int32_t rx_mode, sort_mode; 5216 int h, i; 5217 5218 /* Initialize receive mode default settings. */ 5219 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5220 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5221 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5222 ifp->if_flags &= ~IFF_ALLMULTI; 5223 5224 /* 5225 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5226 * be enbled. 5227 */ 5228 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5229 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5230 5231 /* 5232 * Check for promiscuous, all multicast, or selected 5233 * multicast address filtering. 5234 */ 5235 if (ifp->if_flags & IFF_PROMISC) { 5236 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5237 5238 ifp->if_flags |= IFF_ALLMULTI; 5239 /* Enable promiscuous mode. */ 5240 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5241 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5242 } else if (ifp->if_flags & IFF_ALLMULTI) { 5243 allmulti: 5244 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5245 5246 ifp->if_flags |= IFF_ALLMULTI; 5247 /* Enable all multicast addresses. */ 5248 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5249 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5250 0xffffffff); 5251 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5252 } else { 5253 /* Accept one or more multicast(s). */ 5254 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5255 5256 ETHER_FIRST_MULTI(step, ec, enm); 5257 while (enm != NULL) { 5258 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5259 ETHER_ADDR_LEN)) { 5260 goto allmulti; 5261 } 5262 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5263 0xFF; 5264 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5265 ETHER_NEXT_MULTI(step, enm); 5266 } 5267 5268 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5269 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5270 hashes[i]); 5271 5272 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5273 } 5274 5275 /* Only make changes if the recive mode has actually changed. */ 5276 if (rx_mode != sc->rx_mode) { 5277 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5278 rx_mode); 5279 5280 sc->rx_mode = rx_mode; 5281 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5282 } 5283 5284 /* Disable and clear the exisitng sort before enabling a new sort. */ 5285 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5286 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5287 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5288 } 5289 5290 /****************************************************************************/ 5291 /* Called periodically to updates statistics from the controllers */ 5292 /* statistics block. */ 5293 /* */ 5294 /* Returns: */ 5295 /* Nothing. */ 5296 /****************************************************************************/ 5297 void 5298 bnx_stats_update(struct bnx_softc *sc) 5299 { 5300 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5301 struct statistics_block *stats; 5302 5303 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5304 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5305 BUS_DMASYNC_POSTREAD); 5306 5307 stats = (struct statistics_block *)sc->stats_block; 5308 5309 /* 5310 * Update the interface statistics from the 5311 * hardware statistics. 5312 */ 5313 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5314 5315 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5316 (u_long)stats->stat_EtherStatsOverrsizePkts + 5317 (u_long)stats->stat_IfInMBUFDiscards + 5318 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5319 (u_long)stats->stat_Dot3StatsFCSErrors; 5320 5321 ifp->if_oerrors = (u_long) 5322 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5323 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5324 (u_long)stats->stat_Dot3StatsLateCollisions; 5325 5326 /* 5327 * Certain controllers don't report 5328 * carrier sense errors correctly. 5329 * See errata E11_5708CA0_1165. 5330 */ 5331 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5332 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5333 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5334 5335 /* 5336 * Update the sysctl statistics from the 5337 * hardware statistics. 5338 */ 5339 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 5340 (u_int64_t) stats->stat_IfHCInOctets_lo; 5341 5342 sc->stat_IfHCInBadOctets = 5343 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5344 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 5345 5346 sc->stat_IfHCOutOctets = 5347 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 5348 (u_int64_t) stats->stat_IfHCOutOctets_lo; 5349 5350 sc->stat_IfHCOutBadOctets = 5351 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5352 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 5353 5354 sc->stat_IfHCInUcastPkts = 5355 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5356 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 5357 5358 sc->stat_IfHCInMulticastPkts = 5359 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5360 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 5361 5362 sc->stat_IfHCInBroadcastPkts = 5363 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5364 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 5365 5366 sc->stat_IfHCOutUcastPkts = 5367 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5368 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 5369 5370 sc->stat_IfHCOutMulticastPkts = 5371 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5372 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 5373 5374 sc->stat_IfHCOutBroadcastPkts = 5375 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5376 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5377 5378 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5379 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5380 5381 sc->stat_Dot3StatsCarrierSenseErrors = 5382 stats->stat_Dot3StatsCarrierSenseErrors; 5383 5384 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5385 5386 sc->stat_Dot3StatsAlignmentErrors = 5387 stats->stat_Dot3StatsAlignmentErrors; 5388 5389 sc->stat_Dot3StatsSingleCollisionFrames = 5390 stats->stat_Dot3StatsSingleCollisionFrames; 5391 5392 sc->stat_Dot3StatsMultipleCollisionFrames = 5393 stats->stat_Dot3StatsMultipleCollisionFrames; 5394 5395 sc->stat_Dot3StatsDeferredTransmissions = 5396 stats->stat_Dot3StatsDeferredTransmissions; 5397 5398 sc->stat_Dot3StatsExcessiveCollisions = 5399 stats->stat_Dot3StatsExcessiveCollisions; 5400 5401 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5402 5403 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5404 5405 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5406 5407 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5408 5409 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5410 5411 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5412 5413 sc->stat_EtherStatsPktsRx64Octets = 5414 stats->stat_EtherStatsPktsRx64Octets; 5415 5416 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5417 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5418 5419 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5420 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5421 5422 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5423 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5424 5425 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5426 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5427 5428 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5429 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5430 5431 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5432 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5433 5434 sc->stat_EtherStatsPktsTx64Octets = 5435 stats->stat_EtherStatsPktsTx64Octets; 5436 5437 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5438 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5439 5440 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5441 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5442 5443 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5444 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5445 5446 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5447 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5448 5449 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5450 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5451 5452 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5453 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5454 5455 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5456 5457 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5458 5459 sc->stat_OutXonSent = stats->stat_OutXonSent; 5460 5461 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5462 5463 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5464 5465 sc->stat_MacControlFramesReceived = 5466 stats->stat_MacControlFramesReceived; 5467 5468 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5469 5470 sc->stat_IfInFramesL2FilterDiscards = 5471 stats->stat_IfInFramesL2FilterDiscards; 5472 5473 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5474 5475 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5476 5477 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5478 5479 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5480 5481 sc->stat_CatchupInRuleCheckerDiscards = 5482 stats->stat_CatchupInRuleCheckerDiscards; 5483 5484 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5485 5486 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5487 5488 sc->stat_CatchupInRuleCheckerP4Hit = 5489 stats->stat_CatchupInRuleCheckerP4Hit; 5490 5491 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5492 } 5493 5494 void 5495 bnx_tick(void *xsc) 5496 { 5497 struct bnx_softc *sc = xsc; 5498 struct mii_data *mii; 5499 u_int32_t msg; 5500 u_int16_t prod, chain_prod; 5501 u_int32_t prod_bseq; 5502 int s = splnet(); 5503 5504 /* Tell the firmware that the driver is still running. */ 5505 #ifdef BNX_DEBUG 5506 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5507 #else 5508 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5509 #endif 5510 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5511 5512 /* Update the statistics from the hardware statistics block. */ 5513 bnx_stats_update(sc); 5514 5515 /* Schedule the next tick. */ 5516 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5517 5518 mii = &sc->bnx_mii; 5519 mii_tick(mii); 5520 5521 /* try to get more RX buffers, just in case */ 5522 prod = sc->rx_prod; 5523 prod_bseq = sc->rx_prod_bseq; 5524 chain_prod = RX_CHAIN_IDX(prod); 5525 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5526 sc->rx_prod = prod; 5527 sc->rx_prod_bseq = prod_bseq; 5528 splx(s); 5529 return; 5530 } 5531 5532 /****************************************************************************/ 5533 /* BNX Debug Routines */ 5534 /****************************************************************************/ 5535 #ifdef BNX_DEBUG 5536 5537 /****************************************************************************/ 5538 /* Prints out information about an mbuf. */ 5539 /* */ 5540 /* Returns: */ 5541 /* Nothing. */ 5542 /****************************************************************************/ 5543 void 5544 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5545 { 5546 struct mbuf *mp = m; 5547 5548 if (m == NULL) { 5549 /* Index out of range. */ 5550 aprint_error("mbuf ptr is null!\n"); 5551 return; 5552 } 5553 5554 while (mp) { 5555 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5556 mp, mp->m_len); 5557 5558 if (mp->m_flags & M_EXT) 5559 aprint_debug("M_EXT "); 5560 if (mp->m_flags & M_PKTHDR) 5561 aprint_debug("M_PKTHDR "); 5562 aprint_debug("\n"); 5563 5564 if (mp->m_flags & M_EXT) 5565 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 5566 mp, mp->m_ext.ext_size); 5567 5568 mp = mp->m_next; 5569 } 5570 } 5571 5572 /****************************************************************************/ 5573 /* Prints out the mbufs in the TX mbuf chain. */ 5574 /* */ 5575 /* Returns: */ 5576 /* Nothing. */ 5577 /****************************************************************************/ 5578 void 5579 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5580 { 5581 #if 0 5582 struct mbuf *m; 5583 int i; 5584 5585 aprint_debug_dev(sc->bnx_dev, 5586 "----------------------------" 5587 " tx mbuf data " 5588 "----------------------------\n"); 5589 5590 for (i = 0; i < count; i++) { 5591 m = sc->tx_mbuf_ptr[chain_prod]; 5592 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5593 bnx_dump_mbuf(sc, m); 5594 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5595 } 5596 5597 aprint_debug_dev(sc->bnx_dev, 5598 "--------------------------------------------" 5599 "----------------------------\n"); 5600 #endif 5601 } 5602 5603 /* 5604 * This routine prints the RX mbuf chain. 5605 */ 5606 void 5607 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5608 { 5609 struct mbuf *m; 5610 int i; 5611 5612 aprint_debug_dev(sc->bnx_dev, 5613 "----------------------------" 5614 " rx mbuf data " 5615 "----------------------------\n"); 5616 5617 for (i = 0; i < count; i++) { 5618 m = sc->rx_mbuf_ptr[chain_prod]; 5619 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5620 bnx_dump_mbuf(sc, m); 5621 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5622 } 5623 5624 5625 aprint_debug_dev(sc->bnx_dev, 5626 "--------------------------------------------" 5627 "----------------------------\n"); 5628 } 5629 5630 void 5631 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5632 { 5633 if (idx > MAX_TX_BD) 5634 /* Index out of range. */ 5635 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5636 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5637 /* TX Chain page pointer. */ 5638 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5639 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5640 txbd->tx_bd_haddr_lo); 5641 else 5642 /* Normal tx_bd entry. */ 5643 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5644 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5645 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5646 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5647 txbd->tx_bd_flags); 5648 } 5649 5650 void 5651 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5652 { 5653 if (idx > MAX_RX_BD) 5654 /* Index out of range. */ 5655 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5656 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5657 /* TX Chain page pointer. */ 5658 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5659 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5660 rxbd->rx_bd_haddr_lo); 5661 else 5662 /* Normal tx_bd entry. */ 5663 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5664 "0x%08X, flags = 0x%08X\n", idx, 5665 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5666 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5667 } 5668 5669 void 5670 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5671 { 5672 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5673 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5674 "tcp_udp_xsum = 0x%04X\n", idx, 5675 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5676 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5677 l2fhdr->l2_fhdr_tcp_udp_xsum); 5678 } 5679 5680 /* 5681 * This routine prints the TX chain. 5682 */ 5683 void 5684 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5685 { 5686 struct tx_bd *txbd; 5687 int i; 5688 5689 /* First some info about the tx_bd chain structure. */ 5690 aprint_debug_dev(sc->bnx_dev, 5691 "----------------------------" 5692 " tx_bd chain " 5693 "----------------------------\n"); 5694 5695 BNX_PRINTF(sc, 5696 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5697 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5698 5699 BNX_PRINTF(sc, 5700 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5701 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5702 5703 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5704 5705 aprint_error_dev(sc->bnx_dev, "" 5706 "-----------------------------" 5707 " tx_bd data " 5708 "-----------------------------\n"); 5709 5710 /* Now print out the tx_bd's themselves. */ 5711 for (i = 0; i < count; i++) { 5712 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5713 bnx_dump_txbd(sc, tx_prod, txbd); 5714 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5715 } 5716 5717 aprint_debug_dev(sc->bnx_dev, 5718 "-----------------------------" 5719 "--------------" 5720 "-----------------------------\n"); 5721 } 5722 5723 /* 5724 * This routine prints the RX chain. 5725 */ 5726 void 5727 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5728 { 5729 struct rx_bd *rxbd; 5730 int i; 5731 5732 /* First some info about the tx_bd chain structure. */ 5733 aprint_debug_dev(sc->bnx_dev, 5734 "----------------------------" 5735 " rx_bd chain " 5736 "----------------------------\n"); 5737 5738 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5739 5740 BNX_PRINTF(sc, 5741 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5742 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5743 5744 BNX_PRINTF(sc, 5745 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5746 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5747 5748 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5749 5750 aprint_error_dev(sc->bnx_dev, 5751 "----------------------------" 5752 " rx_bd data " 5753 "----------------------------\n"); 5754 5755 /* Now print out the rx_bd's themselves. */ 5756 for (i = 0; i < count; i++) { 5757 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5758 bnx_dump_rxbd(sc, rx_prod, rxbd); 5759 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5760 } 5761 5762 aprint_debug_dev(sc->bnx_dev, 5763 "----------------------------" 5764 "--------------" 5765 "----------------------------\n"); 5766 } 5767 5768 /* 5769 * This routine prints the status block. 5770 */ 5771 void 5772 bnx_dump_status_block(struct bnx_softc *sc) 5773 { 5774 struct status_block *sblk; 5775 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5776 BUS_DMASYNC_POSTREAD); 5777 5778 sblk = sc->status_block; 5779 5780 aprint_debug_dev(sc->bnx_dev, "----------------------------- Status Block " 5781 "-----------------------------\n"); 5782 5783 BNX_PRINTF(sc, 5784 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5785 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5786 sblk->status_idx); 5787 5788 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5789 sblk->status_rx_quick_consumer_index0, 5790 sblk->status_tx_quick_consumer_index0); 5791 5792 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5793 5794 /* Theses indices are not used for normal L2 drivers. */ 5795 if (sblk->status_rx_quick_consumer_index1 || 5796 sblk->status_tx_quick_consumer_index1) 5797 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5798 sblk->status_rx_quick_consumer_index1, 5799 sblk->status_tx_quick_consumer_index1); 5800 5801 if (sblk->status_rx_quick_consumer_index2 || 5802 sblk->status_tx_quick_consumer_index2) 5803 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5804 sblk->status_rx_quick_consumer_index2, 5805 sblk->status_tx_quick_consumer_index2); 5806 5807 if (sblk->status_rx_quick_consumer_index3 || 5808 sblk->status_tx_quick_consumer_index3) 5809 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5810 sblk->status_rx_quick_consumer_index3, 5811 sblk->status_tx_quick_consumer_index3); 5812 5813 if (sblk->status_rx_quick_consumer_index4 || 5814 sblk->status_rx_quick_consumer_index5) 5815 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5816 sblk->status_rx_quick_consumer_index4, 5817 sblk->status_rx_quick_consumer_index5); 5818 5819 if (sblk->status_rx_quick_consumer_index6 || 5820 sblk->status_rx_quick_consumer_index7) 5821 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5822 sblk->status_rx_quick_consumer_index6, 5823 sblk->status_rx_quick_consumer_index7); 5824 5825 if (sblk->status_rx_quick_consumer_index8 || 5826 sblk->status_rx_quick_consumer_index9) 5827 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5828 sblk->status_rx_quick_consumer_index8, 5829 sblk->status_rx_quick_consumer_index9); 5830 5831 if (sblk->status_rx_quick_consumer_index10 || 5832 sblk->status_rx_quick_consumer_index11) 5833 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5834 sblk->status_rx_quick_consumer_index10, 5835 sblk->status_rx_quick_consumer_index11); 5836 5837 if (sblk->status_rx_quick_consumer_index12 || 5838 sblk->status_rx_quick_consumer_index13) 5839 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5840 sblk->status_rx_quick_consumer_index12, 5841 sblk->status_rx_quick_consumer_index13); 5842 5843 if (sblk->status_rx_quick_consumer_index14 || 5844 sblk->status_rx_quick_consumer_index15) 5845 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5846 sblk->status_rx_quick_consumer_index14, 5847 sblk->status_rx_quick_consumer_index15); 5848 5849 if (sblk->status_completion_producer_index || 5850 sblk->status_cmd_consumer_index) 5851 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5852 sblk->status_completion_producer_index, 5853 sblk->status_cmd_consumer_index); 5854 5855 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 5856 "-----------------------------\n"); 5857 } 5858 5859 /* 5860 * This routine prints the statistics block. 5861 */ 5862 void 5863 bnx_dump_stats_block(struct bnx_softc *sc) 5864 { 5865 struct statistics_block *sblk; 5866 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5867 BUS_DMASYNC_POSTREAD); 5868 5869 sblk = sc->stats_block; 5870 5871 aprint_debug_dev(sc->bnx_dev, "" 5872 "-----------------------------" 5873 " Stats Block " 5874 "-----------------------------\n"); 5875 5876 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5877 "IfHcInBadOctets = 0x%08X:%08X\n", 5878 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5879 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5880 5881 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5882 "IfHcOutBadOctets = 0x%08X:%08X\n", 5883 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5884 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5885 5886 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5887 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5888 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5889 sblk->stat_IfHCInMulticastPkts_hi, 5890 sblk->stat_IfHCInMulticastPkts_lo); 5891 5892 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5893 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5894 sblk->stat_IfHCInBroadcastPkts_hi, 5895 sblk->stat_IfHCInBroadcastPkts_lo, 5896 sblk->stat_IfHCOutUcastPkts_hi, 5897 sblk->stat_IfHCOutUcastPkts_lo); 5898 5899 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5900 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5901 sblk->stat_IfHCOutMulticastPkts_hi, 5902 sblk->stat_IfHCOutMulticastPkts_lo, 5903 sblk->stat_IfHCOutBroadcastPkts_hi, 5904 sblk->stat_IfHCOutBroadcastPkts_lo); 5905 5906 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5907 BNX_PRINTF(sc, "0x%08X : " 5908 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5909 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5910 5911 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5912 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5913 sblk->stat_Dot3StatsCarrierSenseErrors); 5914 5915 if (sblk->stat_Dot3StatsFCSErrors) 5916 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5917 sblk->stat_Dot3StatsFCSErrors); 5918 5919 if (sblk->stat_Dot3StatsAlignmentErrors) 5920 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5921 sblk->stat_Dot3StatsAlignmentErrors); 5922 5923 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5924 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5925 sblk->stat_Dot3StatsSingleCollisionFrames); 5926 5927 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5928 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 5929 sblk->stat_Dot3StatsMultipleCollisionFrames); 5930 5931 if (sblk->stat_Dot3StatsDeferredTransmissions) 5932 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 5933 sblk->stat_Dot3StatsDeferredTransmissions); 5934 5935 if (sblk->stat_Dot3StatsExcessiveCollisions) 5936 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 5937 sblk->stat_Dot3StatsExcessiveCollisions); 5938 5939 if (sblk->stat_Dot3StatsLateCollisions) 5940 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 5941 sblk->stat_Dot3StatsLateCollisions); 5942 5943 if (sblk->stat_EtherStatsCollisions) 5944 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 5945 sblk->stat_EtherStatsCollisions); 5946 5947 if (sblk->stat_EtherStatsFragments) 5948 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 5949 sblk->stat_EtherStatsFragments); 5950 5951 if (sblk->stat_EtherStatsJabbers) 5952 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 5953 sblk->stat_EtherStatsJabbers); 5954 5955 if (sblk->stat_EtherStatsUndersizePkts) 5956 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 5957 sblk->stat_EtherStatsUndersizePkts); 5958 5959 if (sblk->stat_EtherStatsOverrsizePkts) 5960 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 5961 sblk->stat_EtherStatsOverrsizePkts); 5962 5963 if (sblk->stat_EtherStatsPktsRx64Octets) 5964 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 5965 sblk->stat_EtherStatsPktsRx64Octets); 5966 5967 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 5968 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 5969 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 5970 5971 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 5972 BNX_PRINTF(sc, "0x%08X : " 5973 "EtherStatsPktsRx128Octetsto255Octets\n", 5974 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 5975 5976 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 5977 BNX_PRINTF(sc, "0x%08X : " 5978 "EtherStatsPktsRx256Octetsto511Octets\n", 5979 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 5980 5981 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 5982 BNX_PRINTF(sc, "0x%08X : " 5983 "EtherStatsPktsRx512Octetsto1023Octets\n", 5984 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 5985 5986 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 5987 BNX_PRINTF(sc, "0x%08X : " 5988 "EtherStatsPktsRx1024Octetsto1522Octets\n", 5989 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 5990 5991 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 5992 BNX_PRINTF(sc, "0x%08X : " 5993 "EtherStatsPktsRx1523Octetsto9022Octets\n", 5994 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 5995 5996 if (sblk->stat_EtherStatsPktsTx64Octets) 5997 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 5998 sblk->stat_EtherStatsPktsTx64Octets); 5999 6000 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6001 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6002 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6003 6004 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6005 BNX_PRINTF(sc, "0x%08X : " 6006 "EtherStatsPktsTx128Octetsto255Octets\n", 6007 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6008 6009 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6010 BNX_PRINTF(sc, "0x%08X : " 6011 "EtherStatsPktsTx256Octetsto511Octets\n", 6012 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6013 6014 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6015 BNX_PRINTF(sc, "0x%08X : " 6016 "EtherStatsPktsTx512Octetsto1023Octets\n", 6017 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6018 6019 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6020 BNX_PRINTF(sc, "0x%08X : " 6021 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6022 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6023 6024 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6025 BNX_PRINTF(sc, "0x%08X : " 6026 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6027 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6028 6029 if (sblk->stat_XonPauseFramesReceived) 6030 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6031 sblk->stat_XonPauseFramesReceived); 6032 6033 if (sblk->stat_XoffPauseFramesReceived) 6034 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6035 sblk->stat_XoffPauseFramesReceived); 6036 6037 if (sblk->stat_OutXonSent) 6038 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6039 sblk->stat_OutXonSent); 6040 6041 if (sblk->stat_OutXoffSent) 6042 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6043 sblk->stat_OutXoffSent); 6044 6045 if (sblk->stat_FlowControlDone) 6046 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6047 sblk->stat_FlowControlDone); 6048 6049 if (sblk->stat_MacControlFramesReceived) 6050 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6051 sblk->stat_MacControlFramesReceived); 6052 6053 if (sblk->stat_XoffStateEntered) 6054 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6055 sblk->stat_XoffStateEntered); 6056 6057 if (sblk->stat_IfInFramesL2FilterDiscards) 6058 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6059 sblk->stat_IfInFramesL2FilterDiscards); 6060 6061 if (sblk->stat_IfInRuleCheckerDiscards) 6062 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6063 sblk->stat_IfInRuleCheckerDiscards); 6064 6065 if (sblk->stat_IfInFTQDiscards) 6066 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6067 sblk->stat_IfInFTQDiscards); 6068 6069 if (sblk->stat_IfInMBUFDiscards) 6070 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6071 sblk->stat_IfInMBUFDiscards); 6072 6073 if (sblk->stat_IfInRuleCheckerP4Hit) 6074 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6075 sblk->stat_IfInRuleCheckerP4Hit); 6076 6077 if (sblk->stat_CatchupInRuleCheckerDiscards) 6078 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6079 sblk->stat_CatchupInRuleCheckerDiscards); 6080 6081 if (sblk->stat_CatchupInFTQDiscards) 6082 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6083 sblk->stat_CatchupInFTQDiscards); 6084 6085 if (sblk->stat_CatchupInMBUFDiscards) 6086 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6087 sblk->stat_CatchupInMBUFDiscards); 6088 6089 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6090 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6091 sblk->stat_CatchupInRuleCheckerP4Hit); 6092 6093 aprint_debug_dev(sc->bnx_dev, 6094 "-----------------------------" 6095 "--------------" 6096 "-----------------------------\n"); 6097 } 6098 6099 void 6100 bnx_dump_driver_state(struct bnx_softc *sc) 6101 { 6102 aprint_debug_dev(sc->bnx_dev, 6103 "-----------------------------" 6104 " Driver State " 6105 "-----------------------------\n"); 6106 6107 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6108 "address\n", sc); 6109 6110 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6111 sc->status_block); 6112 6113 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6114 "address\n", sc->stats_block); 6115 6116 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6117 "adddress\n", sc->tx_bd_chain); 6118 6119 #if 0 6120 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6121 sc->rx_bd_chain); 6122 6123 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6124 sc->tx_mbuf_ptr); 6125 #endif 6126 6127 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6128 sc->rx_mbuf_ptr); 6129 6130 BNX_PRINTF(sc, 6131 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6132 sc->interrupts_generated); 6133 6134 BNX_PRINTF(sc, 6135 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6136 sc->rx_interrupts); 6137 6138 BNX_PRINTF(sc, 6139 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6140 sc->tx_interrupts); 6141 6142 BNX_PRINTF(sc, 6143 " 0x%08X - (sc->last_status_idx) status block index\n", 6144 sc->last_status_idx); 6145 6146 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6147 sc->tx_prod); 6148 6149 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6150 sc->tx_cons); 6151 6152 BNX_PRINTF(sc, 6153 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6154 sc->tx_prod_bseq); 6155 BNX_PRINTF(sc, 6156 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6157 sc->tx_mbuf_alloc); 6158 6159 BNX_PRINTF(sc, 6160 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6161 sc->used_tx_bd); 6162 6163 BNX_PRINTF(sc, 6164 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6165 sc->tx_hi_watermark, sc->max_tx_bd); 6166 6167 6168 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6169 sc->rx_prod); 6170 6171 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6172 sc->rx_cons); 6173 6174 BNX_PRINTF(sc, 6175 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6176 sc->rx_prod_bseq); 6177 6178 BNX_PRINTF(sc, 6179 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6180 sc->rx_mbuf_alloc); 6181 6182 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6183 sc->free_rx_bd); 6184 6185 BNX_PRINTF(sc, 6186 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6187 sc->rx_low_watermark, sc->max_rx_bd); 6188 6189 BNX_PRINTF(sc, 6190 " 0x%08X - (sc->mbuf_alloc_failed) " 6191 "mbuf alloc failures\n", 6192 sc->mbuf_alloc_failed); 6193 6194 BNX_PRINTF(sc, 6195 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6196 "simulated mbuf alloc failures\n", 6197 sc->mbuf_sim_alloc_failed); 6198 6199 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6200 "-----------------------------\n"); 6201 } 6202 6203 void 6204 bnx_dump_hw_state(struct bnx_softc *sc) 6205 { 6206 u_int32_t val1; 6207 int i; 6208 6209 aprint_debug_dev(sc->bnx_dev, 6210 "----------------------------" 6211 " Hardware State " 6212 "----------------------------\n"); 6213 6214 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6215 6216 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6217 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6218 val1, BNX_MISC_ENABLE_STATUS_BITS); 6219 6220 val1 = REG_RD(sc, BNX_DMA_STATUS); 6221 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6222 6223 val1 = REG_RD(sc, BNX_CTX_STATUS); 6224 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6225 6226 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6227 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6228 BNX_EMAC_STATUS); 6229 6230 val1 = REG_RD(sc, BNX_RPM_STATUS); 6231 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6232 6233 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6234 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6235 BNX_TBDR_STATUS); 6236 6237 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6238 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6239 BNX_TDMA_STATUS); 6240 6241 val1 = REG_RD(sc, BNX_HC_STATUS); 6242 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6243 6244 aprint_debug_dev(sc->bnx_dev, 6245 "----------------------------" 6246 "----------------" 6247 "----------------------------\n"); 6248 6249 aprint_debug_dev(sc->bnx_dev, 6250 "----------------------------" 6251 " Register Dump " 6252 "----------------------------\n"); 6253 6254 for (i = 0x400; i < 0x8000; i += 0x10) 6255 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6256 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6257 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6258 6259 aprint_debug_dev(sc->bnx_dev, 6260 "----------------------------" 6261 "----------------" 6262 "----------------------------\n"); 6263 } 6264 6265 void 6266 bnx_breakpoint(struct bnx_softc *sc) 6267 { 6268 /* Unreachable code to shut the compiler up about unused functions. */ 6269 if (0) { 6270 bnx_dump_txbd(sc, 0, NULL); 6271 bnx_dump_rxbd(sc, 0, NULL); 6272 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6273 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6274 bnx_dump_l2fhdr(sc, 0, NULL); 6275 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6276 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6277 bnx_dump_status_block(sc); 6278 bnx_dump_stats_block(sc); 6279 bnx_dump_driver_state(sc); 6280 bnx_dump_hw_state(sc); 6281 } 6282 6283 bnx_dump_driver_state(sc); 6284 /* Print the important status block fields. */ 6285 bnx_dump_status_block(sc); 6286 6287 #if 0 6288 /* Call the debugger. */ 6289 breakpoint(); 6290 #endif 6291 6292 return; 6293 } 6294 #endif 6295
Indexes created Mon Sep 22 13:09:51 GMT 2025