if_bnx.c revision 1.4
1 /* $NetBSD: if_bnx.c,v 1.4 2007/04/09 14:23:03 bouyer Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.43 2007/01/30 03:21:10 krw Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.4 2007/04/09 14:23:03 bouyer Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5708C B1 44 * 45 * The following controllers are not supported by this driver: 46 * (These are not "Production" versions of the controller.) 47 * 48 * BCM5706C A0, A1 49 * BCM5706S A0, A1, A2, A3 50 * BCM5708C A0, B0 51 * BCM5708S A0, B0, B1 52 */ 53 54 #include <sys/callout.h> 55 56 #include <dev/pci/if_bnxreg.h> 57 #include <dev/microcode/bnx/bnxfw.h> 58 59 /****************************************************************************/ 60 /* BNX Driver Version */ 61 /****************************************************************************/ 62 const char bnx_driver_version[] = "v0.9.6"; 63 64 /****************************************************************************/ 65 /* BNX Debug Options */ 66 /****************************************************************************/ 67 #ifdef BNX_DEBUG 68 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 69 70 /* 0 = Never */ 71 /* 1 = 1 in 2,147,483,648 */ 72 /* 256 = 1 in 8,388,608 */ 73 /* 2048 = 1 in 1,048,576 */ 74 /* 65536 = 1 in 32,768 */ 75 /* 1048576 = 1 in 2,048 */ 76 /* 268435456 = 1 in 8 */ 77 /* 536870912 = 1 in 4 */ 78 /* 1073741824 = 1 in 2 */ 79 80 /* Controls how often the l2_fhdr frame error check will fail. */ 81 int bnx_debug_l2fhdr_status_check = 0; 82 83 /* Controls how often the unexpected attention check will fail. */ 84 int bnx_debug_unexpected_attention = 0; 85 86 /* Controls how often to simulate an mbuf allocation failure. */ 87 int bnx_debug_mbuf_allocation_failure = 0; 88 89 /* Controls how often to simulate a DMA mapping failure. */ 90 int bnx_debug_dma_map_addr_failure = 0; 91 92 /* Controls how often to simulate a bootcode failure. */ 93 int bnx_debug_bootcode_running_failure = 0; 94 #endif 95 96 /****************************************************************************/ 97 /* PCI Device ID Table */ 98 /* */ 99 /* Used by bnx_probe() to identify the devices supported by this driver. */ 100 /****************************************************************************/ 101 static const struct bnx_product { 102 pci_vendor_id_t bp_vendor; 103 pci_product_id_t bp_product; 104 pci_vendor_id_t bp_subvendor; 105 pci_product_id_t bp_subproduct; 106 const char *bp_name; 107 } bnx_devices[] = { 108 #ifdef PCI_SUBPRODUCT_HP_NC370T 109 { 110 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 111 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 112 "HP NC370T Multifunction Gigabit Server Adapter" 113 }, 114 #endif 115 #ifdef PCI_SUBPRODUCT_HP_NC370i 116 { 117 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 118 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 119 "HP NC370i Multifunction Gigabit Server Adapter" 120 }, 121 #endif 122 { 123 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 124 0, 0, 125 "Broadcom NetXtreme II BCM5706 1000Base-T" 126 }, 127 #ifdef PCI_SUBPRODUCT_HP_NC370F 128 { 129 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 130 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 131 "HP NC370F Multifunction Gigabit Server Adapter" 132 }, 133 #endif 134 { 135 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 136 0, 0, 137 "Broadcom NetXtreme II BCM5706 1000Base-SX" 138 }, 139 { 140 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 141 0, 0, 142 "Broadcom NetXtreme II BCM5708 1000Base-T" 143 }, 144 { 145 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 146 0, 0, 147 "Broadcom NetXtreme II BCM5708 1000Base-SX" 148 }, 149 }; 150 151 /****************************************************************************/ 152 /* Supported Flash NVRAM device data. */ 153 /****************************************************************************/ 154 static struct flash_spec flash_table[] = 155 { 156 /* Slow EEPROM */ 157 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 158 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 159 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 160 "EEPROM - slow"}, 161 /* Expansion entry 0001 */ 162 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 164 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 165 "Entry 0001"}, 166 /* Saifun SA25F010 (non-buffered flash) */ 167 /* strap, cfg1, & write1 need updates */ 168 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 169 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 171 "Non-buffered flash (128kB)"}, 172 /* Saifun SA25F020 (non-buffered flash) */ 173 /* strap, cfg1, & write1 need updates */ 174 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 175 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 176 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 177 "Non-buffered flash (256kB)"}, 178 /* Expansion entry 0100 */ 179 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 0100"}, 183 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 184 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 185 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 186 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 187 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 188 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 189 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 190 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 191 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 192 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 193 /* Saifun SA25F005 (non-buffered flash) */ 194 /* strap, cfg1, & write1 need updates */ 195 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 196 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 197 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 198 "Non-buffered flash (64kB)"}, 199 /* Fast EEPROM */ 200 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 201 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 202 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 203 "EEPROM - fast"}, 204 /* Expansion entry 1001 */ 205 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 206 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 208 "Entry 1001"}, 209 /* Expansion entry 1010 */ 210 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 211 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 1010"}, 214 /* ATMEL AT45DB011B (buffered flash) */ 215 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 216 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 217 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 218 "Buffered flash (128kB)"}, 219 /* Expansion entry 1100 */ 220 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 221 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 223 "Entry 1100"}, 224 /* Expansion entry 1101 */ 225 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 226 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 228 "Entry 1101"}, 229 /* Ateml Expansion entry 1110 */ 230 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 231 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 232 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 233 "Entry 1110 (Atmel)"}, 234 /* ATMEL AT45DB021B (buffered flash) */ 235 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 236 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 237 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 238 "Buffered flash (256kB)"}, 239 }; 240 241 /****************************************************************************/ 242 /* OpenBSD device entry points. */ 243 /****************************************************************************/ 244 static int bnx_probe(device_t, cfdata_t, void *); 245 void bnx_attach(struct device *, struct device *, void *); 246 #if 0 247 void bnx_detach(void *); 248 #endif 249 void bnx_shutdown(void *); 250 251 /****************************************************************************/ 252 /* BNX Debug Data Structure Dump Routines */ 253 /****************************************************************************/ 254 #ifdef BNX_DEBUG 255 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 256 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 257 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 258 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 259 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 260 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 261 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 262 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 263 void bnx_dump_status_block(struct bnx_softc *); 264 void bnx_dump_stats_block(struct bnx_softc *); 265 void bnx_dump_driver_state(struct bnx_softc *); 266 void bnx_dump_hw_state(struct bnx_softc *); 267 void bnx_breakpoint(struct bnx_softc *); 268 #endif 269 270 /****************************************************************************/ 271 /* BNX Register/Memory Access Routines */ 272 /****************************************************************************/ 273 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 274 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 275 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 276 int bnx_miibus_read_reg(struct device *, int, int); 277 void bnx_miibus_write_reg(struct device *, int, int, int); 278 void bnx_miibus_statchg(struct device *); 279 280 /****************************************************************************/ 281 /* BNX NVRAM Access Routines */ 282 /****************************************************************************/ 283 int bnx_acquire_nvram_lock(struct bnx_softc *); 284 int bnx_release_nvram_lock(struct bnx_softc *); 285 void bnx_enable_nvram_access(struct bnx_softc *); 286 void bnx_disable_nvram_access(struct bnx_softc *); 287 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 288 u_int32_t); 289 int bnx_init_nvram(struct bnx_softc *); 290 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 291 int bnx_nvram_test(struct bnx_softc *); 292 #ifdef BNX_NVRAM_WRITE_SUPPORT 293 int bnx_enable_nvram_write(struct bnx_softc *); 294 void bnx_disable_nvram_write(struct bnx_softc *); 295 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 296 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 297 u_int32_t); 298 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 299 #endif 300 301 /****************************************************************************/ 302 /* */ 303 /****************************************************************************/ 304 int bnx_dma_alloc(struct bnx_softc *); 305 void bnx_dma_free(struct bnx_softc *); 306 void bnx_release_resources(struct bnx_softc *); 307 308 /****************************************************************************/ 309 /* BNX Firmware Synchronization and Load */ 310 /****************************************************************************/ 311 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 312 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 313 u_int32_t); 314 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 315 struct fw_info *); 316 void bnx_init_cpus(struct bnx_softc *); 317 318 void bnx_stop(struct bnx_softc *); 319 int bnx_reset(struct bnx_softc *, u_int32_t); 320 int bnx_chipinit(struct bnx_softc *); 321 int bnx_blockinit(struct bnx_softc *); 322 int bnx_get_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 323 u_int16_t *, u_int32_t *); 324 325 int bnx_init_tx_chain(struct bnx_softc *); 326 int bnx_init_rx_chain(struct bnx_softc *); 327 void bnx_free_rx_chain(struct bnx_softc *); 328 void bnx_free_tx_chain(struct bnx_softc *); 329 330 int bnx_tx_encap(struct bnx_softc *, struct mbuf **); 331 void bnx_start(struct ifnet *); 332 int bnx_ioctl(struct ifnet *, u_long, void *); 333 void bnx_watchdog(struct ifnet *); 334 int bnx_ifmedia_upd(struct ifnet *); 335 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 336 int bnx_init(struct ifnet *); 337 338 void bnx_init_context(struct bnx_softc *); 339 void bnx_get_mac_addr(struct bnx_softc *); 340 void bnx_set_mac_addr(struct bnx_softc *); 341 void bnx_phy_intr(struct bnx_softc *); 342 void bnx_rx_intr(struct bnx_softc *); 343 void bnx_tx_intr(struct bnx_softc *); 344 void bnx_disable_intr(struct bnx_softc *); 345 void bnx_enable_intr(struct bnx_softc *); 346 347 int bnx_intr(void *); 348 void bnx_set_rx_mode(struct bnx_softc *); 349 void bnx_stats_update(struct bnx_softc *); 350 void bnx_tick(void *); 351 352 /****************************************************************************/ 353 /* OpenBSD device dispatch table. */ 354 /****************************************************************************/ 355 CFATTACH_DECL(bnx, sizeof(struct bnx_softc), 356 bnx_probe, bnx_attach, NULL, NULL); 357 358 /****************************************************************************/ 359 /* Device probe function. */ 360 /* */ 361 /* Compares the device to the driver's list of supported devices and */ 362 /* reports back to the OS whether this is the right driver for the device. */ 363 /* */ 364 /* Returns: */ 365 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 366 /****************************************************************************/ 367 static const struct bnx_product * 368 bnx_lookup(const struct pci_attach_args *pa) 369 { 370 int i; 371 pcireg_t subid; 372 373 for (i = 0; i < sizeof(bnx_devices)/sizeof(struct bnx_product); i++) { 374 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 375 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 376 continue; 377 if (!bnx_devices[i].bp_subvendor) 378 return &bnx_devices[i]; 379 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 380 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 381 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 382 return &bnx_devices[i]; 383 } 384 385 return NULL; 386 } 387 static int 388 bnx_probe(device_t parent, cfdata_t match, void *aux) 389 { 390 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 391 392 if (bnx_lookup(pa) != NULL) 393 return (1); 394 395 return (0); 396 } 397 398 /****************************************************************************/ 399 /* Device attach function. */ 400 /* */ 401 /* Allocates device resources, performs secondary chip identification, */ 402 /* resets and initializes the hardware, and initializes driver instance */ 403 /* variables. */ 404 /* */ 405 /* Returns: */ 406 /* 0 on success, positive value on failure. */ 407 /****************************************************************************/ 408 void 409 bnx_attach(struct device *parent, struct device *self, void *aux) 410 { 411 const struct bnx_product *bp; 412 struct bnx_softc *sc = (struct bnx_softc *)self; 413 struct pci_attach_args *pa = aux; 414 pci_chipset_tag_t pc = pa->pa_pc; 415 pci_intr_handle_t ih; 416 const char *intrstr = NULL; 417 u_int32_t command; 418 struct ifnet *ifp; 419 u_int32_t val; 420 pcireg_t memtype; 421 422 bp = bnx_lookup(pa); 423 if (bp == NULL) 424 panic("unknown device"); 425 426 aprint_naive("\n"); 427 aprint_normal(": %s", bp->bp_name); 428 429 sc->bnx_pa = *pa; 430 431 /* 432 * Map control/status registers. 433 */ 434 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 435 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 436 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 437 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 438 439 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 440 aprint_error("%s: failed to enable memory mapping!\n", 441 sc->bnx_dev.dv_xname); 442 return; 443 } 444 445 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 446 switch (memtype) { 447 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 448 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 449 if (pci_mapreg_map(pa, BNX_PCI_BAR0, 450 memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, 451 NULL, &sc->bnx_size) == 0) 452 break; 453 default: 454 aprint_error("%s: can't find mem space\n", 455 sc->bnx_dev.dv_xname); 456 return; 457 } 458 459 if (pci_intr_map(pa, &ih)) { 460 aprint_error("%s: couldn't map interrupt\n", 461 sc->bnx_dev.dv_xname); 462 goto bnx_attach_fail; 463 } 464 465 intrstr = pci_intr_string(pc, ih); 466 467 /* 468 * Configure byte swap and enable indirect register access. 469 * Rely on CPU to do target byte swapping on big endian systems. 470 * Access to registers outside of PCI configurtion space are not 471 * valid until this is done. 472 */ 473 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 474 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 475 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 476 477 /* Save ASIC revsion info. */ 478 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 479 480 /* Weed out any non-production controller revisions. */ 481 switch(BNX_CHIP_ID(sc)) { 482 case BNX_CHIP_ID_5706_A0: 483 case BNX_CHIP_ID_5706_A1: 484 case BNX_CHIP_ID_5708_A0: 485 case BNX_CHIP_ID_5708_B0: 486 aprint_error("%s: unsupported controller revision (%c%d)!\n", 487 sc->bnx_dev.dv_xname, 488 ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A', 489 PCI_REVISION(pa->pa_class) & 0x0f); 490 goto bnx_attach_fail; 491 } 492 493 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 494 aprint_error("%s: SerDes controllers are not supported!\n", 495 sc->bnx_dev.dv_xname); 496 goto bnx_attach_fail; 497 } 498 499 /* 500 * Find the base address for shared memory access. 501 * Newer versions of bootcode use a signature and offset 502 * while older versions use a fixed address. 503 */ 504 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 505 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 506 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0); 507 else 508 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 509 510 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 511 512 /* Set initial device and PHY flags */ 513 sc->bnx_flags = 0; 514 sc->bnx_phy_flags = 0; 515 516 /* Get PCI bus information (speed and type). */ 517 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 518 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 519 u_int32_t clkreg; 520 521 sc->bnx_flags |= BNX_PCIX_FLAG; 522 523 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 524 525 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 526 switch (clkreg) { 527 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 528 sc->bus_speed_mhz = 133; 529 break; 530 531 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 532 sc->bus_speed_mhz = 100; 533 break; 534 535 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 536 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 537 sc->bus_speed_mhz = 66; 538 break; 539 540 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 541 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 542 sc->bus_speed_mhz = 50; 543 break; 544 545 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 546 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 547 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 548 sc->bus_speed_mhz = 33; 549 break; 550 } 551 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 552 sc->bus_speed_mhz = 66; 553 else 554 sc->bus_speed_mhz = 33; 555 556 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 557 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 558 559 /* Reset the controller. */ 560 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 561 goto bnx_attach_fail; 562 563 /* Initialize the controller. */ 564 if (bnx_chipinit(sc)) { 565 aprint_error("%s: Controller initialization failed!\n", 566 sc->bnx_dev.dv_xname); 567 goto bnx_attach_fail; 568 } 569 570 /* Perform NVRAM test. */ 571 if (bnx_nvram_test(sc)) { 572 aprint_error("%s: NVRAM test failed!\n", sc->bnx_dev.dv_xname); 573 goto bnx_attach_fail; 574 } 575 576 /* Fetch the permanent Ethernet MAC address. */ 577 bnx_get_mac_addr(sc); 578 aprint_normal("%s: Ethernet address %s\n", sc->bnx_dev.dv_xname, 579 ether_sprintf(sc->eaddr)); 580 581 /* 582 * Trip points control how many BDs 583 * should be ready before generating an 584 * interrupt while ticks control how long 585 * a BD can sit in the chain before 586 * generating an interrupt. Set the default 587 * values for the RX and TX rings. 588 */ 589 590 #ifdef BNX_DEBUG 591 /* Force more frequent interrupts. */ 592 sc->bnx_tx_quick_cons_trip_int = 1; 593 sc->bnx_tx_quick_cons_trip = 1; 594 sc->bnx_tx_ticks_int = 0; 595 sc->bnx_tx_ticks = 0; 596 597 sc->bnx_rx_quick_cons_trip_int = 1; 598 sc->bnx_rx_quick_cons_trip = 1; 599 sc->bnx_rx_ticks_int = 0; 600 sc->bnx_rx_ticks = 0; 601 #else 602 sc->bnx_tx_quick_cons_trip_int = 20; 603 sc->bnx_tx_quick_cons_trip = 20; 604 sc->bnx_tx_ticks_int = 80; 605 sc->bnx_tx_ticks = 80; 606 607 sc->bnx_rx_quick_cons_trip_int = 6; 608 sc->bnx_rx_quick_cons_trip = 6; 609 sc->bnx_rx_ticks_int = 18; 610 sc->bnx_rx_ticks = 18; 611 #endif 612 613 /* Update statistics once every second. */ 614 sc->bnx_stats_ticks = 1000000 & 0xffff00; 615 616 /* 617 * The copper based NetXtreme II controllers 618 * use an integrated PHY at address 1 while 619 * the SerDes controllers use a PHY at 620 * address 2. 621 */ 622 sc->bnx_phy_addr = 1; 623 624 if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { 625 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 626 sc->bnx_flags |= BNX_NO_WOL_FLAG; 627 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) { 628 sc->bnx_phy_addr = 2; 629 val = REG_RD_IND(sc, sc->bnx_shmem_base + 630 BNX_SHARED_HW_CFG_CONFIG); 631 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) 632 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 633 } 634 } 635 636 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 637 aprint_error("%s: SerDes is not supported by this driver!\n", 638 sc->bnx_dev.dv_xname); 639 goto bnx_attach_fail; 640 } 641 642 /* Allocate DMA memory resources. */ 643 sc->bnx_dmatag = pa->pa_dmat; 644 if (bnx_dma_alloc(sc)) { 645 aprint_error("%s: DMA resource allocation failed!\n", 646 sc->bnx_dev.dv_xname); 647 goto bnx_attach_fail; 648 } 649 650 /* Initialize the ifnet interface. */ 651 ifp = &sc->ethercom.ec_if; 652 ifp->if_softc = sc; 653 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 654 ifp->if_ioctl = bnx_ioctl; 655 ifp->if_start = bnx_start; 656 ifp->if_init = bnx_init; 657 ifp->if_timer = 0; 658 ifp->if_watchdog = bnx_watchdog; 659 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 660 ifp->if_baudrate = IF_Gbps(2.5); 661 else 662 ifp->if_baudrate = IF_Gbps(1); 663 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 664 IFQ_SET_READY(&ifp->if_snd); 665 bcopy(sc->bnx_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 666 667 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU | 668 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 669 670 ifp->if_capabilities |= 671 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 672 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 673 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 674 675 sc->mbuf_alloc_size = BNX_MAX_MRU; 676 677 /* Hookup IRQ last. */ 678 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 679 if (sc->bnx_intrhand == NULL) { 680 aprint_error("%s: couldn't establish interrupt", 681 sc->bnx_dev.dv_xname); 682 if (intrstr != NULL) 683 aprint_error(" at %s", intrstr); 684 aprint_error("\n"); 685 goto bnx_attach_fail; 686 } 687 688 sc->bnx_mii.mii_ifp = ifp; 689 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 690 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 691 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 692 693 /* Look for our PHY. */ 694 ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, 695 bnx_ifmedia_sts); 696 mii_attach(&sc->bnx_dev, &sc->bnx_mii, 0xffffffff, 697 MII_PHY_ANY, MII_OFFSET_ANY, 0); 698 699 if (LIST_FIRST(&sc->bnx_mii.mii_phys) == NULL) { 700 aprint_error("%s: no PHY found!\n", sc->bnx_dev.dv_xname); 701 ifmedia_add(&sc->bnx_mii.mii_media, 702 IFM_ETHER|IFM_MANUAL, 0, NULL); 703 ifmedia_set(&sc->bnx_mii.mii_media, 704 IFM_ETHER|IFM_MANUAL); 705 } else { 706 ifmedia_set(&sc->bnx_mii.mii_media, 707 IFM_ETHER|IFM_AUTO); 708 } 709 710 /* Attach to the Ethernet interface list. */ 711 if_attach(ifp); 712 ether_ifattach(ifp,sc->eaddr); 713 714 callout_init(&sc->bnx_timeout); 715 716 /* Print some important debugging info. */ 717 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 718 719 goto bnx_attach_exit; 720 721 bnx_attach_fail: 722 bnx_release_resources(sc); 723 724 bnx_attach_exit: 725 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 726 } 727 728 /****************************************************************************/ 729 /* Device detach function. */ 730 /* */ 731 /* Stops the controller, resets the controller, and releases resources. */ 732 /* */ 733 /* Returns: */ 734 /* 0 on success, positive value on failure. */ 735 /****************************************************************************/ 736 #if 0 737 void 738 bnx_detach(void *xsc) 739 { 740 struct bnx_softc *sc; 741 struct ifnet *ifp = &sc->arpcom.ac_if; 742 743 sc = device_get_softc(dev); 744 745 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 746 747 /* Stop and reset the controller. */ 748 bnx_stop(sc); 749 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 750 751 ether_ifdetach(ifp); 752 753 /* If we have a child device on the MII bus remove it too. */ 754 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 755 ifmedia_removeall(&sc->bnx_ifmedia); 756 } else { 757 bus_generic_detach(dev); 758 device_delete_child(dev, sc->bnx_mii); 759 } 760 761 /* Release all remaining resources. */ 762 bnx_release_resources(sc); 763 764 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 765 766 return(0); 767 } 768 #endif 769 770 /****************************************************************************/ 771 /* Device shutdown function. */ 772 /* */ 773 /* Stops and resets the controller. */ 774 /* */ 775 /* Returns: */ 776 /* Nothing */ 777 /****************************************************************************/ 778 void 779 bnx_shutdown(void *xsc) 780 { 781 struct bnx_softc *sc = (struct bnx_softc *)xsc; 782 783 bnx_stop(sc); 784 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 785 } 786 787 /****************************************************************************/ 788 /* Indirect register read. */ 789 /* */ 790 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 791 /* configuration space. Using this mechanism avoids issues with posted */ 792 /* reads but is much slower than memory-mapped I/O. */ 793 /* */ 794 /* Returns: */ 795 /* The value of the register. */ 796 /****************************************************************************/ 797 u_int32_t 798 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 799 { 800 struct pci_attach_args *pa = &(sc->bnx_pa); 801 802 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 803 offset); 804 #ifdef BNX_DEBUG 805 { 806 u_int32_t val; 807 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 808 BNX_PCICFG_REG_WINDOW); 809 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 810 "val = 0x%08X\n", __FUNCTION__, offset, val); 811 return (val); 812 } 813 #else 814 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 815 #endif 816 } 817 818 /****************************************************************************/ 819 /* Indirect register write. */ 820 /* */ 821 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 822 /* configuration space. Using this mechanism avoids issues with posted */ 823 /* writes but is muchh slower than memory-mapped I/O. */ 824 /* */ 825 /* Returns: */ 826 /* Nothing. */ 827 /****************************************************************************/ 828 void 829 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 830 { 831 struct pci_attach_args *pa = &(sc->bnx_pa); 832 833 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 834 __FUNCTION__, offset, val); 835 836 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 837 offset); 838 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 839 } 840 841 /****************************************************************************/ 842 /* Context memory write. */ 843 /* */ 844 /* The NetXtreme II controller uses context memory to track connection */ 845 /* information for L2 and higher network protocols. */ 846 /* */ 847 /* Returns: */ 848 /* Nothing. */ 849 /****************************************************************************/ 850 void 851 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, 852 u_int32_t val) 853 { 854 855 DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 856 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 857 858 offset += cid_addr; 859 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 860 REG_WR(sc, BNX_CTX_DATA, val); 861 } 862 863 /****************************************************************************/ 864 /* PHY register read. */ 865 /* */ 866 /* Implements register reads on the MII bus. */ 867 /* */ 868 /* Returns: */ 869 /* The value of the register. */ 870 /****************************************************************************/ 871 int 872 bnx_miibus_read_reg(struct device *dev, int phy, int reg) 873 { 874 struct bnx_softc *sc = (struct bnx_softc *)dev; 875 u_int32_t val; 876 int i; 877 878 /* Make sure we are accessing the correct PHY address. */ 879 if (phy != sc->bnx_phy_addr) { 880 DBPRINT(sc, BNX_VERBOSE, 881 "Invalid PHY address %d for PHY read!\n", phy); 882 return(0); 883 } 884 885 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 886 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 887 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 888 889 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 890 REG_RD(sc, BNX_EMAC_MDIO_MODE); 891 892 DELAY(40); 893 } 894 895 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 896 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 897 BNX_EMAC_MDIO_COMM_START_BUSY; 898 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 899 900 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 901 DELAY(10); 902 903 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 904 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 905 DELAY(5); 906 907 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 908 val &= BNX_EMAC_MDIO_COMM_DATA; 909 910 break; 911 } 912 } 913 914 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 915 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 916 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 917 val = 0x0; 918 } else 919 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 920 921 DBPRINT(sc, BNX_EXCESSIVE, 922 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __FUNCTION__, phy, 923 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 924 925 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 926 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 927 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 928 929 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 930 REG_RD(sc, BNX_EMAC_MDIO_MODE); 931 932 DELAY(40); 933 } 934 935 return (val & 0xffff); 936 } 937 938 /****************************************************************************/ 939 /* PHY register write. */ 940 /* */ 941 /* Implements register writes on the MII bus. */ 942 /* */ 943 /* Returns: */ 944 /* The value of the register. */ 945 /****************************************************************************/ 946 void 947 bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val) 948 { 949 struct bnx_softc *sc = (struct bnx_softc *)dev; 950 u_int32_t val1; 951 int i; 952 953 /* Make sure we are accessing the correct PHY address. */ 954 if (phy != sc->bnx_phy_addr) { 955 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 956 phy); 957 return; 958 } 959 960 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 961 "val = 0x%04X\n", __FUNCTION__, 962 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 963 964 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 965 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 966 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 967 968 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 969 REG_RD(sc, BNX_EMAC_MDIO_MODE); 970 971 DELAY(40); 972 } 973 974 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 975 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 976 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 977 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 978 979 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 980 DELAY(10); 981 982 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 983 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 984 DELAY(5); 985 break; 986 } 987 } 988 989 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 990 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 991 __LINE__); 992 } 993 994 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 995 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 996 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 997 998 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 999 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1000 1001 DELAY(40); 1002 } 1003 } 1004 1005 /****************************************************************************/ 1006 /* MII bus status change. */ 1007 /* */ 1008 /* Called by the MII bus driver when the PHY establishes link to set the */ 1009 /* MAC interface registers. */ 1010 /* */ 1011 /* Returns: */ 1012 /* Nothing. */ 1013 /****************************************************************************/ 1014 void 1015 bnx_miibus_statchg(struct device *dev) 1016 { 1017 struct bnx_softc *sc = (struct bnx_softc *)dev; 1018 struct mii_data *mii = &sc->bnx_mii; 1019 1020 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT); 1021 1022 /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ 1023 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 1024 DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n"); 1025 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII); 1026 } else { 1027 DBPRINT(sc, BNX_INFO, "Setting MII interface.\n"); 1028 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII); 1029 } 1030 1031 /* Set half or full duplex based on the duplicity 1032 * negotiated by the PHY. 1033 */ 1034 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1035 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1036 BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1037 } else { 1038 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1039 BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); 1040 } 1041 } 1042 1043 /****************************************************************************/ 1044 /* Acquire NVRAM lock. */ 1045 /* */ 1046 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1047 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1048 /* for use by the driver. */ 1049 /* */ 1050 /* Returns: */ 1051 /* 0 on success, positive value on failure. */ 1052 /****************************************************************************/ 1053 int 1054 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1055 { 1056 u_int32_t val; 1057 int j; 1058 1059 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1060 1061 /* Request access to the flash interface. */ 1062 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1063 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1064 val = REG_RD(sc, BNX_NVM_SW_ARB); 1065 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1066 break; 1067 1068 DELAY(5); 1069 } 1070 1071 if (j >= NVRAM_TIMEOUT_COUNT) { 1072 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1073 return (EBUSY); 1074 } 1075 1076 return (0); 1077 } 1078 1079 /****************************************************************************/ 1080 /* Release NVRAM lock. */ 1081 /* */ 1082 /* When the caller is finished accessing NVRAM the lock must be released. */ 1083 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1084 /* for use by the driver. */ 1085 /* */ 1086 /* Returns: */ 1087 /* 0 on success, positive value on failure. */ 1088 /****************************************************************************/ 1089 int 1090 bnx_release_nvram_lock(struct bnx_softc *sc) 1091 { 1092 int j; 1093 u_int32_t val; 1094 1095 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1096 1097 /* Relinquish nvram interface. */ 1098 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1099 1100 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1101 val = REG_RD(sc, BNX_NVM_SW_ARB); 1102 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1103 break; 1104 1105 DELAY(5); 1106 } 1107 1108 if (j >= NVRAM_TIMEOUT_COUNT) { 1109 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1110 return (EBUSY); 1111 } 1112 1113 return (0); 1114 } 1115 1116 #ifdef BNX_NVRAM_WRITE_SUPPORT 1117 /****************************************************************************/ 1118 /* Enable NVRAM write access. */ 1119 /* */ 1120 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1121 /* */ 1122 /* Returns: */ 1123 /* 0 on success, positive value on failure. */ 1124 /****************************************************************************/ 1125 int 1126 bnx_enable_nvram_write(struct bnx_softc *sc) 1127 { 1128 u_int32_t val; 1129 1130 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1131 1132 val = REG_RD(sc, BNX_MISC_CFG); 1133 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1134 1135 if (!sc->bnx_flash_info->buffered) { 1136 int j; 1137 1138 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1139 REG_WR(sc, BNX_NVM_COMMAND, 1140 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1141 1142 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1143 DELAY(5); 1144 1145 val = REG_RD(sc, BNX_NVM_COMMAND); 1146 if (val & BNX_NVM_COMMAND_DONE) 1147 break; 1148 } 1149 1150 if (j >= NVRAM_TIMEOUT_COUNT) { 1151 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1152 return (EBUSY); 1153 } 1154 } 1155 1156 return (0); 1157 } 1158 1159 /****************************************************************************/ 1160 /* Disable NVRAM write access. */ 1161 /* */ 1162 /* When the caller is finished writing to NVRAM write access must be */ 1163 /* disabled. */ 1164 /* */ 1165 /* Returns: */ 1166 /* Nothing. */ 1167 /****************************************************************************/ 1168 void 1169 bnx_disable_nvram_write(struct bnx_softc *sc) 1170 { 1171 u_int32_t val; 1172 1173 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1174 1175 val = REG_RD(sc, BNX_MISC_CFG); 1176 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1177 } 1178 #endif 1179 1180 /****************************************************************************/ 1181 /* Enable NVRAM access. */ 1182 /* */ 1183 /* Before accessing NVRAM for read or write operations the caller must */ 1184 /* enabled NVRAM access. */ 1185 /* */ 1186 /* Returns: */ 1187 /* Nothing. */ 1188 /****************************************************************************/ 1189 void 1190 bnx_enable_nvram_access(struct bnx_softc *sc) 1191 { 1192 u_int32_t val; 1193 1194 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1195 1196 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1197 /* Enable both bits, even on read. */ 1198 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1199 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1200 } 1201 1202 /****************************************************************************/ 1203 /* Disable NVRAM access. */ 1204 /* */ 1205 /* When the caller is finished accessing NVRAM access must be disabled. */ 1206 /* */ 1207 /* Returns: */ 1208 /* Nothing. */ 1209 /****************************************************************************/ 1210 void 1211 bnx_disable_nvram_access(struct bnx_softc *sc) 1212 { 1213 u_int32_t val; 1214 1215 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1216 1217 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1218 1219 /* Disable both bits, even after read. */ 1220 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1221 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1222 } 1223 1224 #ifdef BNX_NVRAM_WRITE_SUPPORT 1225 /****************************************************************************/ 1226 /* Erase NVRAM page before writing. */ 1227 /* */ 1228 /* Non-buffered flash parts require that a page be erased before it is */ 1229 /* written. */ 1230 /* */ 1231 /* Returns: */ 1232 /* 0 on success, positive value on failure. */ 1233 /****************************************************************************/ 1234 int 1235 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1236 { 1237 u_int32_t cmd; 1238 int j; 1239 1240 /* Buffered flash doesn't require an erase. */ 1241 if (sc->bnx_flash_info->buffered) 1242 return (0); 1243 1244 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1245 1246 /* Build an erase command. */ 1247 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1248 BNX_NVM_COMMAND_DOIT; 1249 1250 /* 1251 * Clear the DONE bit separately, set the NVRAM adress to erase, 1252 * and issue the erase command. 1253 */ 1254 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1255 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1256 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1257 1258 /* Wait for completion. */ 1259 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1260 u_int32_t val; 1261 1262 DELAY(5); 1263 1264 val = REG_RD(sc, BNX_NVM_COMMAND); 1265 if (val & BNX_NVM_COMMAND_DONE) 1266 break; 1267 } 1268 1269 if (j >= NVRAM_TIMEOUT_COUNT) { 1270 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1271 return (EBUSY); 1272 } 1273 1274 return (0); 1275 } 1276 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1277 1278 /****************************************************************************/ 1279 /* Read a dword (32 bits) from NVRAM. */ 1280 /* */ 1281 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1282 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1283 /* */ 1284 /* Returns: */ 1285 /* 0 on success and the 32 bit value read, positive value on failure. */ 1286 /****************************************************************************/ 1287 int 1288 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1289 u_int8_t *ret_val, u_int32_t cmd_flags) 1290 { 1291 u_int32_t cmd; 1292 int i, rc = 0; 1293 1294 /* Build the command word. */ 1295 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1296 1297 /* Calculate the offset for buffered flash. */ 1298 if (sc->bnx_flash_info->buffered) 1299 offset = ((offset / sc->bnx_flash_info->page_size) << 1300 sc->bnx_flash_info->page_bits) + 1301 (offset % sc->bnx_flash_info->page_size); 1302 1303 /* 1304 * Clear the DONE bit separately, set the address to read, 1305 * and issue the read. 1306 */ 1307 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1308 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1309 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1310 1311 /* Wait for completion. */ 1312 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1313 u_int32_t val; 1314 1315 DELAY(5); 1316 1317 val = REG_RD(sc, BNX_NVM_COMMAND); 1318 if (val & BNX_NVM_COMMAND_DONE) { 1319 val = REG_RD(sc, BNX_NVM_READ); 1320 1321 val = bnx_be32toh(val); 1322 memcpy(ret_val, &val, 4); 1323 break; 1324 } 1325 } 1326 1327 /* Check for errors. */ 1328 if (i >= NVRAM_TIMEOUT_COUNT) { 1329 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1330 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1331 rc = EBUSY; 1332 } 1333 1334 return(rc); 1335 } 1336 1337 #ifdef BNX_NVRAM_WRITE_SUPPORT 1338 /****************************************************************************/ 1339 /* Write a dword (32 bits) to NVRAM. */ 1340 /* */ 1341 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1342 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1343 /* enabled NVRAM write access. */ 1344 /* */ 1345 /* Returns: */ 1346 /* 0 on success, positive value on failure. */ 1347 /****************************************************************************/ 1348 int 1349 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1350 u_int32_t cmd_flags) 1351 { 1352 u_int32_t cmd, val32; 1353 int j; 1354 1355 /* Build the command word. */ 1356 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1357 1358 /* Calculate the offset for buffered flash. */ 1359 if (sc->bnx_flash_info->buffered) 1360 offset = ((offset / sc->bnx_flash_info->page_size) << 1361 sc->bnx_flash_info->page_bits) + 1362 (offset % sc->bnx_flash_info->page_size); 1363 1364 /* 1365 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1366 * set the NVRAM address to write, and issue the write command 1367 */ 1368 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1369 memcpy(&val32, val, 4); 1370 val32 = htobe32(val32); 1371 REG_WR(sc, BNX_NVM_WRITE, val32); 1372 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1373 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1374 1375 /* Wait for completion. */ 1376 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1377 DELAY(5); 1378 1379 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1380 break; 1381 } 1382 if (j >= NVRAM_TIMEOUT_COUNT) { 1383 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1384 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1385 return (EBUSY); 1386 } 1387 1388 return (0); 1389 } 1390 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1391 1392 /****************************************************************************/ 1393 /* Initialize NVRAM access. */ 1394 /* */ 1395 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1396 /* access that device. */ 1397 /* */ 1398 /* Returns: */ 1399 /* 0 on success, positive value on failure. */ 1400 /****************************************************************************/ 1401 int 1402 bnx_init_nvram(struct bnx_softc *sc) 1403 { 1404 u_int32_t val; 1405 int j, entry_count, rc; 1406 struct flash_spec *flash; 1407 1408 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1409 1410 /* Determine the selected interface. */ 1411 val = REG_RD(sc, BNX_NVM_CFG1); 1412 1413 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1414 1415 rc = 0; 1416 1417 /* 1418 * Flash reconfiguration is required to support additional 1419 * NVRAM devices not directly supported in hardware. 1420 * Check if the flash interface was reconfigured 1421 * by the bootcode. 1422 */ 1423 1424 if (val & 0x40000000) { 1425 /* Flash interface reconfigured by bootcode. */ 1426 1427 DBPRINT(sc,BNX_INFO_LOAD, 1428 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1429 1430 for (j = 0, flash = &flash_table[0]; j < entry_count; 1431 j++, flash++) { 1432 if ((val & FLASH_BACKUP_STRAP_MASK) == 1433 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1434 sc->bnx_flash_info = flash; 1435 break; 1436 } 1437 } 1438 } else { 1439 /* Flash interface not yet reconfigured. */ 1440 u_int32_t mask; 1441 1442 DBPRINT(sc,BNX_INFO_LOAD, 1443 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1444 1445 if (val & (1 << 23)) 1446 mask = FLASH_BACKUP_STRAP_MASK; 1447 else 1448 mask = FLASH_STRAP_MASK; 1449 1450 /* Look for the matching NVRAM device configuration data. */ 1451 for (j = 0, flash = &flash_table[0]; j < entry_count; 1452 j++, flash++) { 1453 /* Check if the dev matches any of the known devices. */ 1454 if ((val & mask) == (flash->strapping & mask)) { 1455 /* Found a device match. */ 1456 sc->bnx_flash_info = flash; 1457 1458 /* Request access to the flash interface. */ 1459 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1460 return (rc); 1461 1462 /* Reconfigure the flash interface. */ 1463 bnx_enable_nvram_access(sc); 1464 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1465 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1466 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1467 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1468 bnx_disable_nvram_access(sc); 1469 bnx_release_nvram_lock(sc); 1470 1471 break; 1472 } 1473 } 1474 } 1475 1476 /* Check if a matching device was found. */ 1477 if (j == entry_count) { 1478 sc->bnx_flash_info = NULL; 1479 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1480 __FILE__, __LINE__); 1481 rc = ENODEV; 1482 } 1483 1484 /* Write the flash config data to the shared memory interface. */ 1485 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1486 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1487 if (val) 1488 sc->bnx_flash_size = val; 1489 else 1490 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1491 1492 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1493 "0x%08X\n", sc->bnx_flash_info->total_size); 1494 1495 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1496 1497 return (rc); 1498 } 1499 1500 /****************************************************************************/ 1501 /* Read an arbitrary range of data from NVRAM. */ 1502 /* */ 1503 /* Prepares the NVRAM interface for access and reads the requested data */ 1504 /* into the supplied buffer. */ 1505 /* */ 1506 /* Returns: */ 1507 /* 0 on success and the data read, positive value on failure. */ 1508 /****************************************************************************/ 1509 int 1510 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1511 int buf_size) 1512 { 1513 int rc = 0; 1514 u_int32_t cmd_flags, offset32, len32, extra; 1515 1516 if (buf_size == 0) 1517 return (0); 1518 1519 /* Request access to the flash interface. */ 1520 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1521 return (rc); 1522 1523 /* Enable access to flash interface */ 1524 bnx_enable_nvram_access(sc); 1525 1526 len32 = buf_size; 1527 offset32 = offset; 1528 extra = 0; 1529 1530 cmd_flags = 0; 1531 1532 if (offset32 & 3) { 1533 u_int8_t buf[4]; 1534 u_int32_t pre_len; 1535 1536 offset32 &= ~3; 1537 pre_len = 4 - (offset & 3); 1538 1539 if (pre_len >= len32) { 1540 pre_len = len32; 1541 cmd_flags = 1542 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1543 } else 1544 cmd_flags = BNX_NVM_COMMAND_FIRST; 1545 1546 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1547 1548 if (rc) 1549 return (rc); 1550 1551 memcpy(ret_buf, buf + (offset & 3), pre_len); 1552 1553 offset32 += 4; 1554 ret_buf += pre_len; 1555 len32 -= pre_len; 1556 } 1557 1558 if (len32 & 3) { 1559 extra = 4 - (len32 & 3); 1560 len32 = (len32 + 4) & ~3; 1561 } 1562 1563 if (len32 == 4) { 1564 u_int8_t buf[4]; 1565 1566 if (cmd_flags) 1567 cmd_flags = BNX_NVM_COMMAND_LAST; 1568 else 1569 cmd_flags = 1570 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1571 1572 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1573 1574 memcpy(ret_buf, buf, 4 - extra); 1575 } else if (len32 > 0) { 1576 u_int8_t buf[4]; 1577 1578 /* Read the first word. */ 1579 if (cmd_flags) 1580 cmd_flags = 0; 1581 else 1582 cmd_flags = BNX_NVM_COMMAND_FIRST; 1583 1584 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1585 1586 /* Advance to the next dword. */ 1587 offset32 += 4; 1588 ret_buf += 4; 1589 len32 -= 4; 1590 1591 while (len32 > 4 && rc == 0) { 1592 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1593 1594 /* Advance to the next dword. */ 1595 offset32 += 4; 1596 ret_buf += 4; 1597 len32 -= 4; 1598 } 1599 1600 if (rc) 1601 return (rc); 1602 1603 cmd_flags = BNX_NVM_COMMAND_LAST; 1604 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1605 1606 memcpy(ret_buf, buf, 4 - extra); 1607 } 1608 1609 /* Disable access to flash interface and release the lock. */ 1610 bnx_disable_nvram_access(sc); 1611 bnx_release_nvram_lock(sc); 1612 1613 return (rc); 1614 } 1615 1616 #ifdef BNX_NVRAM_WRITE_SUPPORT 1617 /****************************************************************************/ 1618 /* Write an arbitrary range of data from NVRAM. */ 1619 /* */ 1620 /* Prepares the NVRAM interface for write access and writes the requested */ 1621 /* data from the supplied buffer. The caller is responsible for */ 1622 /* calculating any appropriate CRCs. */ 1623 /* */ 1624 /* Returns: */ 1625 /* 0 on success, positive value on failure. */ 1626 /****************************************************************************/ 1627 int 1628 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1629 int buf_size) 1630 { 1631 u_int32_t written, offset32, len32; 1632 u_int8_t *buf, start[4], end[4]; 1633 int rc = 0; 1634 int align_start, align_end; 1635 1636 buf = data_buf; 1637 offset32 = offset; 1638 len32 = buf_size; 1639 align_start = align_end = 0; 1640 1641 if ((align_start = (offset32 & 3))) { 1642 offset32 &= ~3; 1643 len32 += align_start; 1644 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1645 return (rc); 1646 } 1647 1648 if (len32 & 3) { 1649 if ((len32 > 4) || !align_start) { 1650 align_end = 4 - (len32 & 3); 1651 len32 += align_end; 1652 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1653 end, 4))) { 1654 return (rc); 1655 } 1656 } 1657 } 1658 1659 if (align_start || align_end) { 1660 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1661 if (buf == 0) 1662 return (ENOMEM); 1663 1664 if (align_start) 1665 memcpy(buf, start, 4); 1666 1667 if (align_end) 1668 memcpy(buf + len32 - 4, end, 4); 1669 1670 memcpy(buf + align_start, data_buf, buf_size); 1671 } 1672 1673 written = 0; 1674 while ((written < len32) && (rc == 0)) { 1675 u_int32_t page_start, page_end, data_start, data_end; 1676 u_int32_t addr, cmd_flags; 1677 int i; 1678 u_int8_t flash_buffer[264]; 1679 1680 /* Find the page_start addr */ 1681 page_start = offset32 + written; 1682 page_start -= (page_start % sc->bnx_flash_info->page_size); 1683 /* Find the page_end addr */ 1684 page_end = page_start + sc->bnx_flash_info->page_size; 1685 /* Find the data_start addr */ 1686 data_start = (written == 0) ? offset32 : page_start; 1687 /* Find the data_end addr */ 1688 data_end = (page_end > offset32 + len32) ? 1689 (offset32 + len32) : page_end; 1690 1691 /* Request access to the flash interface. */ 1692 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1693 goto nvram_write_end; 1694 1695 /* Enable access to flash interface */ 1696 bnx_enable_nvram_access(sc); 1697 1698 cmd_flags = BNX_NVM_COMMAND_FIRST; 1699 if (sc->bnx_flash_info->buffered == 0) { 1700 int j; 1701 1702 /* Read the whole page into the buffer 1703 * (non-buffer flash only) */ 1704 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1705 if (j == (sc->bnx_flash_info->page_size - 4)) 1706 cmd_flags |= BNX_NVM_COMMAND_LAST; 1707 1708 rc = bnx_nvram_read_dword(sc, 1709 page_start + j, 1710 &flash_buffer[j], 1711 cmd_flags); 1712 1713 if (rc) 1714 goto nvram_write_end; 1715 1716 cmd_flags = 0; 1717 } 1718 } 1719 1720 /* Enable writes to flash interface (unlock write-protect) */ 1721 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1722 goto nvram_write_end; 1723 1724 /* Erase the page */ 1725 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1726 goto nvram_write_end; 1727 1728 /* Re-enable the write again for the actual write */ 1729 bnx_enable_nvram_write(sc); 1730 1731 /* Loop to write back the buffer data from page_start to 1732 * data_start */ 1733 i = 0; 1734 if (sc->bnx_flash_info->buffered == 0) { 1735 for (addr = page_start; addr < data_start; 1736 addr += 4, i += 4) { 1737 1738 rc = bnx_nvram_write_dword(sc, addr, 1739 &flash_buffer[i], cmd_flags); 1740 1741 if (rc != 0) 1742 goto nvram_write_end; 1743 1744 cmd_flags = 0; 1745 } 1746 } 1747 1748 /* Loop to write the new data from data_start to data_end */ 1749 for (addr = data_start; addr < data_end; addr += 4, i++) { 1750 if ((addr == page_end - 4) || 1751 ((sc->bnx_flash_info->buffered) && 1752 (addr == data_end - 4))) { 1753 1754 cmd_flags |= BNX_NVM_COMMAND_LAST; 1755 } 1756 1757 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1758 1759 if (rc != 0) 1760 goto nvram_write_end; 1761 1762 cmd_flags = 0; 1763 buf += 4; 1764 } 1765 1766 /* Loop to write back the buffer data from data_end 1767 * to page_end */ 1768 if (sc->bnx_flash_info->buffered == 0) { 1769 for (addr = data_end; addr < page_end; 1770 addr += 4, i += 4) { 1771 1772 if (addr == page_end-4) 1773 cmd_flags = BNX_NVM_COMMAND_LAST; 1774 1775 rc = bnx_nvram_write_dword(sc, addr, 1776 &flash_buffer[i], cmd_flags); 1777 1778 if (rc != 0) 1779 goto nvram_write_end; 1780 1781 cmd_flags = 0; 1782 } 1783 } 1784 1785 /* Disable writes to flash interface (lock write-protect) */ 1786 bnx_disable_nvram_write(sc); 1787 1788 /* Disable access to flash interface */ 1789 bnx_disable_nvram_access(sc); 1790 bnx_release_nvram_lock(sc); 1791 1792 /* Increment written */ 1793 written += data_end - data_start; 1794 } 1795 1796 nvram_write_end: 1797 if (align_start || align_end) 1798 free(buf, M_DEVBUF); 1799 1800 return (rc); 1801 } 1802 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1803 1804 /****************************************************************************/ 1805 /* Verifies that NVRAM is accessible and contains valid data. */ 1806 /* */ 1807 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1808 /* correct. */ 1809 /* */ 1810 /* Returns: */ 1811 /* 0 on success, positive value on failure. */ 1812 /****************************************************************************/ 1813 int 1814 bnx_nvram_test(struct bnx_softc *sc) 1815 { 1816 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1817 u_int8_t *data = (u_int8_t *) buf; 1818 int rc = 0; 1819 u_int32_t magic, csum; 1820 1821 /* 1822 * Check that the device NVRAM is valid by reading 1823 * the magic value at offset 0. 1824 */ 1825 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1826 goto bnx_nvram_test_done; 1827 1828 magic = bnx_be32toh(buf[0]); 1829 if (magic != BNX_NVRAM_MAGIC) { 1830 rc = ENODEV; 1831 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1832 "Expected: 0x%08X, Found: 0x%08X\n", 1833 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1834 goto bnx_nvram_test_done; 1835 } 1836 1837 /* 1838 * Verify that the device NVRAM includes valid 1839 * configuration data. 1840 */ 1841 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1842 goto bnx_nvram_test_done; 1843 1844 csum = ether_crc32_le(data, 0x100); 1845 if (csum != BNX_CRC32_RESIDUAL) { 1846 rc = ENODEV; 1847 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1848 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1849 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1850 goto bnx_nvram_test_done; 1851 } 1852 1853 csum = ether_crc32_le(data + 0x100, 0x100); 1854 if (csum != BNX_CRC32_RESIDUAL) { 1855 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1856 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1857 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1858 rc = ENODEV; 1859 } 1860 1861 bnx_nvram_test_done: 1862 return (rc); 1863 } 1864 1865 /****************************************************************************/ 1866 /* Free any DMA memory owned by the driver. */ 1867 /* */ 1868 /* Scans through each data structre that requires DMA memory and frees */ 1869 /* the memory if allocated. */ 1870 /* */ 1871 /* Returns: */ 1872 /* Nothing. */ 1873 /****************************************************************************/ 1874 void 1875 bnx_dma_free(struct bnx_softc *sc) 1876 { 1877 int i; 1878 1879 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1880 1881 /* Destroy the status block. */ 1882 if (sc->status_block != NULL && sc->status_map != NULL) { 1883 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 1884 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 1885 BNX_STATUS_BLK_SZ); 1886 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 1887 sc->status_rseg); 1888 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 1889 sc->status_block = NULL; 1890 sc->status_map = NULL; 1891 } 1892 1893 /* Destroy the statistics block. */ 1894 if (sc->stats_block != NULL && sc->stats_map != NULL) { 1895 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 1896 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 1897 BNX_STATS_BLK_SZ); 1898 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 1899 sc->stats_rseg); 1900 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 1901 sc->stats_block = NULL; 1902 sc->stats_map = NULL; 1903 } 1904 1905 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 1906 for (i = 0; i < TX_PAGES; i++ ) { 1907 if (sc->tx_bd_chain[i] != NULL && 1908 sc->tx_bd_chain_map[i] != NULL) { 1909 bus_dmamap_unload(sc->bnx_dmatag, 1910 sc->tx_bd_chain_map[i]); 1911 bus_dmamem_unmap(sc->bnx_dmatag, 1912 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 1913 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 1914 sc->tx_bd_chain_rseg[i]); 1915 bus_dmamap_destroy(sc->bnx_dmatag, 1916 sc->tx_bd_chain_map[i]); 1917 sc->tx_bd_chain[i] = NULL; 1918 sc->tx_bd_chain_map[i] = NULL; 1919 } 1920 } 1921 1922 /* Unload and destroy the TX mbuf maps. */ 1923 for (i = 0; i < TOTAL_TX_BD; i++) { 1924 if (sc->tx_mbuf_map[i] != NULL) { 1925 bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1926 bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]); 1927 } 1928 } 1929 1930 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 1931 for (i = 0; i < RX_PAGES; i++ ) { 1932 if (sc->rx_bd_chain[i] != NULL && 1933 sc->rx_bd_chain_map[i] != NULL) { 1934 bus_dmamap_unload(sc->bnx_dmatag, 1935 sc->rx_bd_chain_map[i]); 1936 bus_dmamem_unmap(sc->bnx_dmatag, 1937 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 1938 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 1939 sc->rx_bd_chain_rseg[i]); 1940 1941 bus_dmamap_destroy(sc->bnx_dmatag, 1942 sc->rx_bd_chain_map[i]); 1943 sc->rx_bd_chain[i] = NULL; 1944 sc->rx_bd_chain_map[i] = NULL; 1945 } 1946 } 1947 1948 /* Unload and destroy the RX mbuf maps. */ 1949 for (i = 0; i < TOTAL_RX_BD; i++) { 1950 if (sc->rx_mbuf_map[i] != NULL) { 1951 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1952 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 1953 } 1954 } 1955 1956 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1957 } 1958 1959 /****************************************************************************/ 1960 /* Allocate any DMA memory needed by the driver. */ 1961 /* */ 1962 /* Allocates DMA memory needed for the various global structures needed by */ 1963 /* hardware. */ 1964 /* */ 1965 /* Returns: */ 1966 /* 0 for success, positive value for failure. */ 1967 /****************************************************************************/ 1968 int 1969 bnx_dma_alloc(struct bnx_softc *sc) 1970 { 1971 int i, rc = 0; 1972 1973 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1974 1975 /* 1976 * Allocate DMA memory for the status block, map the memory into DMA 1977 * space, and fetch the physical address of the block. 1978 */ 1979 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 1980 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 1981 aprint_error("%s: Could not create status block DMA map!\n", 1982 sc->bnx_dev.dv_xname); 1983 rc = ENOMEM; 1984 goto bnx_dma_alloc_exit; 1985 } 1986 1987 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1988 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 1989 &sc->status_rseg, BUS_DMA_NOWAIT)) { 1990 aprint_error( 1991 "%s: Could not allocate status block DMA memory!\n", 1992 sc->bnx_dev.dv_xname); 1993 rc = ENOMEM; 1994 goto bnx_dma_alloc_exit; 1995 } 1996 1997 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 1998 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 1999 aprint_error("%s: Could not map status block DMA memory!\n", 2000 sc->bnx_dev.dv_xname); 2001 rc = ENOMEM; 2002 goto bnx_dma_alloc_exit; 2003 } 2004 2005 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2006 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2007 aprint_error("%s: Could not load status block DMA memory!\n", 2008 sc->bnx_dev.dv_xname); 2009 rc = ENOMEM; 2010 goto bnx_dma_alloc_exit; 2011 } 2012 2013 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2014 bzero(sc->status_block, BNX_STATUS_BLK_SZ); 2015 2016 /* DRC - Fix for 64 bit addresses. */ 2017 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2018 (u_int32_t) sc->status_block_paddr); 2019 2020 /* 2021 * Allocate DMA memory for the statistics block, map the memory into 2022 * DMA space, and fetch the physical address of the block. 2023 */ 2024 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2025 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2026 aprint_error("%s: Could not create stats block DMA map!\n", 2027 sc->bnx_dev.dv_xname); 2028 rc = ENOMEM; 2029 goto bnx_dma_alloc_exit; 2030 } 2031 2032 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2033 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2034 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2035 aprint_error("%s: Could not allocate stats block DMA memory!\n", 2036 sc->bnx_dev.dv_xname); 2037 rc = ENOMEM; 2038 goto bnx_dma_alloc_exit; 2039 } 2040 2041 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2042 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2043 aprint_error("%s: Could not map stats block DMA memory!\n", 2044 sc->bnx_dev.dv_xname); 2045 rc = ENOMEM; 2046 goto bnx_dma_alloc_exit; 2047 } 2048 2049 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2050 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2051 aprint_error("%s: Could not load status block DMA memory!\n", 2052 sc->bnx_dev.dv_xname); 2053 rc = ENOMEM; 2054 goto bnx_dma_alloc_exit; 2055 } 2056 2057 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2058 bzero(sc->stats_block, BNX_STATS_BLK_SZ); 2059 2060 /* DRC - Fix for 64 bit address. */ 2061 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2062 (u_int32_t) sc->stats_block_paddr); 2063 2064 /* 2065 * Allocate DMA memory for the TX buffer descriptor chain, 2066 * and fetch the physical address of the block. 2067 */ 2068 for (i = 0; i < TX_PAGES; i++) { 2069 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2070 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2071 &sc->tx_bd_chain_map[i])) { 2072 aprint_error( 2073 "%s: Could not create Tx desc %d DMA map!\n", 2074 sc->bnx_dev.dv_xname, i); 2075 rc = ENOMEM; 2076 goto bnx_dma_alloc_exit; 2077 } 2078 2079 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2080 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2081 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2082 aprint_error( 2083 "%s: Could not allocate TX desc %d DMA memory!\n", 2084 sc->bnx_dev.dv_xname, i); 2085 rc = ENOMEM; 2086 goto bnx_dma_alloc_exit; 2087 } 2088 2089 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2090 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2091 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2092 aprint_error( 2093 "%s: Could not map TX desc %d DMA memory!\n", 2094 sc->bnx_dev.dv_xname, i); 2095 rc = ENOMEM; 2096 goto bnx_dma_alloc_exit; 2097 } 2098 2099 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2100 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2101 BUS_DMA_NOWAIT)) { 2102 aprint_error( 2103 "%s: Could not load TX desc %d DMA memory!\n", 2104 sc->bnx_dev.dv_xname, i); 2105 rc = ENOMEM; 2106 goto bnx_dma_alloc_exit; 2107 } 2108 2109 sc->tx_bd_chain_paddr[i] = 2110 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2111 2112 /* DRC - Fix for 64 bit systems. */ 2113 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2114 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2115 } 2116 2117 /* 2118 * Create DMA maps for the TX buffer mbufs. 2119 */ 2120 for (i = 0; i < TOTAL_TX_BD; i++) { 2121 if (bus_dmamap_create(sc->bnx_dmatag, 2122 MCLBYTES * BNX_MAX_SEGMENTS, 2123 USABLE_TX_BD - BNX_TX_SLACK_SPACE, 2124 MCLBYTES, 0, BUS_DMA_NOWAIT, 2125 &sc->tx_mbuf_map[i])) { 2126 aprint_error( 2127 "%s: Could not create Tx mbuf %d DMA map!\n", 2128 sc->bnx_dev.dv_xname, i); 2129 rc = ENOMEM; 2130 goto bnx_dma_alloc_exit; 2131 } 2132 } 2133 2134 /* 2135 * Allocate DMA memory for the Rx buffer descriptor chain, 2136 * and fetch the physical address of the block. 2137 */ 2138 for (i = 0; i < RX_PAGES; i++) { 2139 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2140 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2141 &sc->rx_bd_chain_map[i])) { 2142 aprint_error( 2143 "%s: Could not create Rx desc %d DMA map!\n", 2144 sc->bnx_dev.dv_xname, i); 2145 rc = ENOMEM; 2146 goto bnx_dma_alloc_exit; 2147 } 2148 2149 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2150 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2151 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2152 aprint_error( 2153 "%s: Could not allocate Rx desc %d DMA memory!\n", 2154 sc->bnx_dev.dv_xname, i); 2155 rc = ENOMEM; 2156 goto bnx_dma_alloc_exit; 2157 } 2158 2159 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2160 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2161 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2162 aprint_error( 2163 "%s: Could not map Rx desc %d DMA memory!\n", 2164 sc->bnx_dev.dv_xname, i); 2165 rc = ENOMEM; 2166 goto bnx_dma_alloc_exit; 2167 } 2168 2169 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2170 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2171 BUS_DMA_NOWAIT)) { 2172 aprint_error( 2173 "%s: Could not load Rx desc %d DMA memory!\n", 2174 sc->bnx_dev.dv_xname, i); 2175 rc = ENOMEM; 2176 goto bnx_dma_alloc_exit; 2177 } 2178 2179 bzero(sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2180 sc->rx_bd_chain_paddr[i] = 2181 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2182 2183 /* DRC - Fix for 64 bit systems. */ 2184 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2185 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2186 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2187 0, BNX_RX_CHAIN_PAGE_SZ, 2188 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2189 } 2190 2191 /* 2192 * Create DMA maps for the Rx buffer mbufs. 2193 */ 2194 for (i = 0; i < TOTAL_RX_BD; i++) { 2195 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU, 2196 BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT, 2197 &sc->rx_mbuf_map[i])) { 2198 aprint_error( 2199 "%s: Could not create Rx mbuf %d DMA map!\n", 2200 sc->bnx_dev.dv_xname, i); 2201 rc = ENOMEM; 2202 goto bnx_dma_alloc_exit; 2203 } 2204 } 2205 2206 bnx_dma_alloc_exit: 2207 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2208 2209 return(rc); 2210 } 2211 2212 /****************************************************************************/ 2213 /* Release all resources used by the driver. */ 2214 /* */ 2215 /* Releases all resources acquired by the driver including interrupts, */ 2216 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2217 /* */ 2218 /* Returns: */ 2219 /* Nothing. */ 2220 /****************************************************************************/ 2221 void 2222 bnx_release_resources(struct bnx_softc *sc) 2223 { 2224 struct pci_attach_args *pa = &(sc->bnx_pa); 2225 2226 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2227 2228 bnx_dma_free(sc); 2229 2230 if (sc->bnx_intrhand != NULL) 2231 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2232 2233 if (sc->bnx_size) 2234 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2235 2236 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2237 } 2238 2239 /****************************************************************************/ 2240 /* Firmware synchronization. */ 2241 /* */ 2242 /* Before performing certain events such as a chip reset, synchronize with */ 2243 /* the firmware first. */ 2244 /* */ 2245 /* Returns: */ 2246 /* 0 for success, positive value for failure. */ 2247 /****************************************************************************/ 2248 int 2249 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2250 { 2251 int i, rc = 0; 2252 u_int32_t val; 2253 2254 /* Don't waste any time if we've timed out before. */ 2255 if (sc->bnx_fw_timed_out) { 2256 rc = EBUSY; 2257 goto bnx_fw_sync_exit; 2258 } 2259 2260 /* Increment the message sequence number. */ 2261 sc->bnx_fw_wr_seq++; 2262 msg_data |= sc->bnx_fw_wr_seq; 2263 2264 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2265 msg_data); 2266 2267 /* Send the message to the bootcode driver mailbox. */ 2268 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2269 2270 /* Wait for the bootcode to acknowledge the message. */ 2271 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2272 /* Check for a response in the bootcode firmware mailbox. */ 2273 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2274 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2275 break; 2276 DELAY(1000); 2277 } 2278 2279 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2280 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2281 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2282 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2283 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2284 2285 msg_data &= ~BNX_DRV_MSG_CODE; 2286 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2287 2288 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2289 2290 sc->bnx_fw_timed_out = 1; 2291 rc = EBUSY; 2292 } 2293 2294 bnx_fw_sync_exit: 2295 return (rc); 2296 } 2297 2298 /****************************************************************************/ 2299 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2300 /* */ 2301 /* Returns: */ 2302 /* Nothing. */ 2303 /****************************************************************************/ 2304 void 2305 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2306 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2307 { 2308 int i; 2309 u_int32_t val; 2310 2311 for (i = 0; i < rv2p_code_len; i += 8) { 2312 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2313 rv2p_code++; 2314 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2315 rv2p_code++; 2316 2317 if (rv2p_proc == RV2P_PROC1) { 2318 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2319 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2320 } 2321 else { 2322 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2323 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2324 } 2325 } 2326 2327 /* Reset the processor, un-stall is done later. */ 2328 if (rv2p_proc == RV2P_PROC1) 2329 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2330 else 2331 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2332 } 2333 2334 /****************************************************************************/ 2335 /* Load RISC processor firmware. */ 2336 /* */ 2337 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2338 /* associated with a particular processor. */ 2339 /* */ 2340 /* Returns: */ 2341 /* Nothing. */ 2342 /****************************************************************************/ 2343 void 2344 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2345 struct fw_info *fw) 2346 { 2347 u_int32_t offset; 2348 u_int32_t val; 2349 2350 /* Halt the CPU. */ 2351 val = REG_RD_IND(sc, cpu_reg->mode); 2352 val |= cpu_reg->mode_value_halt; 2353 REG_WR_IND(sc, cpu_reg->mode, val); 2354 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2355 2356 /* Load the Text area. */ 2357 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2358 if (fw->text) { 2359 int j; 2360 2361 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2362 REG_WR_IND(sc, offset, fw->text[j]); 2363 } 2364 2365 /* Load the Data area. */ 2366 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2367 if (fw->data) { 2368 int j; 2369 2370 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2371 REG_WR_IND(sc, offset, fw->data[j]); 2372 } 2373 2374 /* Load the SBSS area. */ 2375 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2376 if (fw->sbss) { 2377 int j; 2378 2379 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2380 REG_WR_IND(sc, offset, fw->sbss[j]); 2381 } 2382 2383 /* Load the BSS area. */ 2384 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2385 if (fw->bss) { 2386 int j; 2387 2388 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2389 REG_WR_IND(sc, offset, fw->bss[j]); 2390 } 2391 2392 /* Load the Read-Only area. */ 2393 offset = cpu_reg->spad_base + 2394 (fw->rodata_addr - cpu_reg->mips_view_base); 2395 if (fw->rodata) { 2396 int j; 2397 2398 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2399 REG_WR_IND(sc, offset, fw->rodata[j]); 2400 } 2401 2402 /* Clear the pre-fetch instruction. */ 2403 REG_WR_IND(sc, cpu_reg->inst, 0); 2404 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2405 2406 /* Start the CPU. */ 2407 val = REG_RD_IND(sc, cpu_reg->mode); 2408 val &= ~cpu_reg->mode_value_halt; 2409 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2410 REG_WR_IND(sc, cpu_reg->mode, val); 2411 } 2412 2413 /****************************************************************************/ 2414 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2415 /* */ 2416 /* Loads the firmware for each CPU and starts the CPU. */ 2417 /* */ 2418 /* Returns: */ 2419 /* Nothing. */ 2420 /****************************************************************************/ 2421 void 2422 bnx_init_cpus(struct bnx_softc *sc) 2423 { 2424 struct cpu_reg cpu_reg; 2425 struct fw_info fw; 2426 2427 /* Initialize the RV2P processor. */ 2428 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2429 RV2P_PROC1); 2430 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2431 RV2P_PROC2); 2432 2433 /* Initialize the RX Processor. */ 2434 cpu_reg.mode = BNX_RXP_CPU_MODE; 2435 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2436 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2437 cpu_reg.state = BNX_RXP_CPU_STATE; 2438 cpu_reg.state_value_clear = 0xffffff; 2439 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2440 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2441 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2442 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2443 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2444 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2445 cpu_reg.mips_view_base = 0x8000000; 2446 2447 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2448 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2449 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2450 fw.start_addr = bnx_RXP_b06FwStartAddr; 2451 2452 fw.text_addr = bnx_RXP_b06FwTextAddr; 2453 fw.text_len = bnx_RXP_b06FwTextLen; 2454 fw.text_index = 0; 2455 fw.text = bnx_RXP_b06FwText; 2456 2457 fw.data_addr = bnx_RXP_b06FwDataAddr; 2458 fw.data_len = bnx_RXP_b06FwDataLen; 2459 fw.data_index = 0; 2460 fw.data = bnx_RXP_b06FwData; 2461 2462 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2463 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2464 fw.sbss_index = 0; 2465 fw.sbss = bnx_RXP_b06FwSbss; 2466 2467 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2468 fw.bss_len = bnx_RXP_b06FwBssLen; 2469 fw.bss_index = 0; 2470 fw.bss = bnx_RXP_b06FwBss; 2471 2472 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2473 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2474 fw.rodata_index = 0; 2475 fw.rodata = bnx_RXP_b06FwRodata; 2476 2477 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2478 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2479 2480 /* Initialize the TX Processor. */ 2481 cpu_reg.mode = BNX_TXP_CPU_MODE; 2482 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2483 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2484 cpu_reg.state = BNX_TXP_CPU_STATE; 2485 cpu_reg.state_value_clear = 0xffffff; 2486 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2487 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2488 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2489 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2490 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2491 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2492 cpu_reg.mips_view_base = 0x8000000; 2493 2494 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2495 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2496 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2497 fw.start_addr = bnx_TXP_b06FwStartAddr; 2498 2499 fw.text_addr = bnx_TXP_b06FwTextAddr; 2500 fw.text_len = bnx_TXP_b06FwTextLen; 2501 fw.text_index = 0; 2502 fw.text = bnx_TXP_b06FwText; 2503 2504 fw.data_addr = bnx_TXP_b06FwDataAddr; 2505 fw.data_len = bnx_TXP_b06FwDataLen; 2506 fw.data_index = 0; 2507 fw.data = bnx_TXP_b06FwData; 2508 2509 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2510 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2511 fw.sbss_index = 0; 2512 fw.sbss = bnx_TXP_b06FwSbss; 2513 2514 fw.bss_addr = bnx_TXP_b06FwBssAddr; 2515 fw.bss_len = bnx_TXP_b06FwBssLen; 2516 fw.bss_index = 0; 2517 fw.bss = bnx_TXP_b06FwBss; 2518 2519 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 2520 fw.rodata_len = bnx_TXP_b06FwRodataLen; 2521 fw.rodata_index = 0; 2522 fw.rodata = bnx_TXP_b06FwRodata; 2523 2524 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2525 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2526 2527 /* Initialize the TX Patch-up Processor. */ 2528 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2529 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2530 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2531 cpu_reg.state = BNX_TPAT_CPU_STATE; 2532 cpu_reg.state_value_clear = 0xffffff; 2533 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2534 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2535 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2536 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2537 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2538 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2539 cpu_reg.mips_view_base = 0x8000000; 2540 2541 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 2542 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 2543 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 2544 fw.start_addr = bnx_TPAT_b06FwStartAddr; 2545 2546 fw.text_addr = bnx_TPAT_b06FwTextAddr; 2547 fw.text_len = bnx_TPAT_b06FwTextLen; 2548 fw.text_index = 0; 2549 fw.text = bnx_TPAT_b06FwText; 2550 2551 fw.data_addr = bnx_TPAT_b06FwDataAddr; 2552 fw.data_len = bnx_TPAT_b06FwDataLen; 2553 fw.data_index = 0; 2554 fw.data = bnx_TPAT_b06FwData; 2555 2556 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 2557 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 2558 fw.sbss_index = 0; 2559 fw.sbss = bnx_TPAT_b06FwSbss; 2560 2561 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 2562 fw.bss_len = bnx_TPAT_b06FwBssLen; 2563 fw.bss_index = 0; 2564 fw.bss = bnx_TPAT_b06FwBss; 2565 2566 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 2567 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 2568 fw.rodata_index = 0; 2569 fw.rodata = bnx_TPAT_b06FwRodata; 2570 2571 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2572 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2573 2574 /* Initialize the Completion Processor. */ 2575 cpu_reg.mode = BNX_COM_CPU_MODE; 2576 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2577 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2578 cpu_reg.state = BNX_COM_CPU_STATE; 2579 cpu_reg.state_value_clear = 0xffffff; 2580 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2581 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2582 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2583 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2584 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2585 cpu_reg.spad_base = BNX_COM_SCRATCH; 2586 cpu_reg.mips_view_base = 0x8000000; 2587 2588 fw.ver_major = bnx_COM_b06FwReleaseMajor; 2589 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 2590 fw.ver_fix = bnx_COM_b06FwReleaseFix; 2591 fw.start_addr = bnx_COM_b06FwStartAddr; 2592 2593 fw.text_addr = bnx_COM_b06FwTextAddr; 2594 fw.text_len = bnx_COM_b06FwTextLen; 2595 fw.text_index = 0; 2596 fw.text = bnx_COM_b06FwText; 2597 2598 fw.data_addr = bnx_COM_b06FwDataAddr; 2599 fw.data_len = bnx_COM_b06FwDataLen; 2600 fw.data_index = 0; 2601 fw.data = bnx_COM_b06FwData; 2602 2603 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 2604 fw.sbss_len = bnx_COM_b06FwSbssLen; 2605 fw.sbss_index = 0; 2606 fw.sbss = bnx_COM_b06FwSbss; 2607 2608 fw.bss_addr = bnx_COM_b06FwBssAddr; 2609 fw.bss_len = bnx_COM_b06FwBssLen; 2610 fw.bss_index = 0; 2611 fw.bss = bnx_COM_b06FwBss; 2612 2613 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 2614 fw.rodata_len = bnx_COM_b06FwRodataLen; 2615 fw.rodata_index = 0; 2616 fw.rodata = bnx_COM_b06FwRodata; 2617 2618 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2619 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2620 } 2621 2622 /****************************************************************************/ 2623 /* Initialize context memory. */ 2624 /* */ 2625 /* Clears the memory associated with each Context ID (CID). */ 2626 /* */ 2627 /* Returns: */ 2628 /* Nothing. */ 2629 /****************************************************************************/ 2630 void 2631 bnx_init_context(struct bnx_softc *sc) 2632 { 2633 u_int32_t vcid; 2634 2635 vcid = 96; 2636 while (vcid) { 2637 u_int32_t vcid_addr, pcid_addr, offset; 2638 2639 vcid--; 2640 2641 vcid_addr = GET_CID_ADDR(vcid); 2642 pcid_addr = vcid_addr; 2643 2644 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); 2645 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2646 2647 /* Zero out the context. */ 2648 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2649 CTX_WR(sc, 0x00, offset, 0); 2650 2651 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 2652 REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); 2653 } 2654 } 2655 2656 /****************************************************************************/ 2657 /* Fetch the permanent MAC address of the controller. */ 2658 /* */ 2659 /* Returns: */ 2660 /* Nothing. */ 2661 /****************************************************************************/ 2662 void 2663 bnx_get_mac_addr(struct bnx_softc *sc) 2664 { 2665 u_int32_t mac_lo = 0, mac_hi = 0; 2666 2667 /* 2668 * The NetXtreme II bootcode populates various NIC 2669 * power-on and runtime configuration items in a 2670 * shared memory area. The factory configured MAC 2671 * address is available from both NVRAM and the 2672 * shared memory area so we'll read the value from 2673 * shared memory for speed. 2674 */ 2675 2676 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 2677 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 2678 2679 if ((mac_lo == 0) && (mac_hi == 0)) { 2680 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 2681 __FILE__, __LINE__); 2682 } else { 2683 sc->eaddr[0] = (u_char)(mac_hi >> 8); 2684 sc->eaddr[1] = (u_char)(mac_hi >> 0); 2685 sc->eaddr[2] = (u_char)(mac_lo >> 24); 2686 sc->eaddr[3] = (u_char)(mac_lo >> 16); 2687 sc->eaddr[4] = (u_char)(mac_lo >> 8); 2688 sc->eaddr[5] = (u_char)(mac_lo >> 0); 2689 } 2690 2691 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 2692 "%s\n", ether_sprintf(sc->eaddr)); 2693 } 2694 2695 /****************************************************************************/ 2696 /* Program the MAC address. */ 2697 /* */ 2698 /* Returns: */ 2699 /* Nothing. */ 2700 /****************************************************************************/ 2701 void 2702 bnx_set_mac_addr(struct bnx_softc *sc) 2703 { 2704 u_int32_t val; 2705 u_int8_t *mac_addr = LLADDR(sc->ethercom.ec_if.if_sadl); 2706 2707 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 2708 "%s\n", ether_sprintf(sc->eaddr)); 2709 2710 val = (mac_addr[0] << 8) | mac_addr[1]; 2711 2712 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 2713 2714 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2715 (mac_addr[4] << 8) | mac_addr[5]; 2716 2717 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 2718 } 2719 2720 /****************************************************************************/ 2721 /* Stop the controller. */ 2722 /* */ 2723 /* Returns: */ 2724 /* Nothing. */ 2725 /****************************************************************************/ 2726 void 2727 bnx_stop(struct bnx_softc *sc) 2728 { 2729 struct ifnet *ifp = &sc->ethercom.ec_if; 2730 struct mii_data *mii = NULL; 2731 2732 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2733 2734 mii = &sc->bnx_mii; 2735 2736 callout_stop(&sc->bnx_timeout); 2737 2738 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2739 2740 /* Disable the transmit/receive blocks. */ 2741 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 2742 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2743 DELAY(20); 2744 2745 bnx_disable_intr(sc); 2746 2747 /* Tell firmware that the driver is going away. */ 2748 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 2749 2750 /* Free the RX lists. */ 2751 bnx_free_rx_chain(sc); 2752 2753 /* Free TX buffers. */ 2754 bnx_free_tx_chain(sc); 2755 2756 ifp->if_timer = 0; 2757 2758 sc->bnx_link = 0; 2759 2760 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2761 2762 } 2763 2764 int 2765 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 2766 { 2767 u_int32_t val; 2768 int i, rc = 0; 2769 2770 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2771 2772 /* Wait for pending PCI transactions to complete. */ 2773 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 2774 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 2775 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 2776 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 2777 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 2778 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 2779 DELAY(5); 2780 2781 /* Assume bootcode is running. */ 2782 sc->bnx_fw_timed_out = 0; 2783 2784 /* Give the firmware a chance to prepare for the reset. */ 2785 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 2786 if (rc) 2787 goto bnx_reset_exit; 2788 2789 /* Set a firmware reminder that this is a soft reset. */ 2790 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 2791 BNX_DRV_RESET_SIGNATURE_MAGIC); 2792 2793 /* Dummy read to force the chip to complete all current transactions. */ 2794 val = REG_RD(sc, BNX_MISC_ID); 2795 2796 /* Chip reset. */ 2797 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2798 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 2799 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 2800 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 2801 2802 /* Allow up to 30us for reset to complete. */ 2803 for (i = 0; i < 10; i++) { 2804 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 2805 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2806 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 2807 break; 2808 2809 DELAY(10); 2810 } 2811 2812 /* Check that reset completed successfully. */ 2813 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 2814 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 2815 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__); 2816 rc = EBUSY; 2817 goto bnx_reset_exit; 2818 } 2819 2820 /* Make sure byte swapping is properly configured. */ 2821 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 2822 if (val != 0x01020304) { 2823 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 2824 __FILE__, __LINE__); 2825 rc = ENODEV; 2826 goto bnx_reset_exit; 2827 } 2828 2829 /* Just completed a reset, assume that firmware is running again. */ 2830 sc->bnx_fw_timed_out = 0; 2831 2832 /* Wait for the firmware to finish its initialization. */ 2833 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 2834 if (rc) 2835 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 2836 "initialization!\n", __FILE__, __LINE__); 2837 2838 bnx_reset_exit: 2839 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2840 2841 return (rc); 2842 } 2843 2844 int 2845 bnx_chipinit(struct bnx_softc *sc) 2846 { 2847 struct pci_attach_args *pa = &(sc->bnx_pa); 2848 u_int32_t val; 2849 int rc = 0; 2850 2851 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2852 2853 /* Make sure the interrupt is not active. */ 2854 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 2855 2856 /* Initialize DMA byte/word swapping, configure the number of DMA */ 2857 /* channels and PCI clock compensation delay. */ 2858 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 2859 BNX_DMA_CONFIG_DATA_WORD_SWAP | 2860 #if BYTE_ORDER == BIG_ENDIAN 2861 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 2862 #endif 2863 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 2864 DMA_READ_CHANS << 12 | 2865 DMA_WRITE_CHANS << 16; 2866 2867 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 2868 2869 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 2870 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 2871 2872 /* 2873 * This setting resolves a problem observed on certain Intel PCI 2874 * chipsets that cannot handle multiple outstanding DMA operations. 2875 * See errata E9_5706A1_65. 2876 */ 2877 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 2878 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 2879 !(sc->bnx_flags & BNX_PCIX_FLAG)) 2880 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 2881 2882 REG_WR(sc, BNX_DMA_CONFIG, val); 2883 2884 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 2885 if (sc->bnx_flags & BNX_PCIX_FLAG) { 2886 u_int16_t nval; 2887 2888 nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 2889 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 2890 nval & ~0x2); 2891 } 2892 2893 /* Enable the RX_V2P and Context state machines before access. */ 2894 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 2895 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 2896 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 2897 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 2898 2899 /* Initialize context mapping and zero out the quick contexts. */ 2900 bnx_init_context(sc); 2901 2902 /* Initialize the on-boards CPUs */ 2903 bnx_init_cpus(sc); 2904 2905 /* Prepare NVRAM for access. */ 2906 if (bnx_init_nvram(sc)) { 2907 rc = ENODEV; 2908 goto bnx_chipinit_exit; 2909 } 2910 2911 /* Set the kernel bypass block size */ 2912 val = REG_RD(sc, BNX_MQ_CONFIG); 2913 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 2914 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 2915 REG_WR(sc, BNX_MQ_CONFIG, val); 2916 2917 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 2918 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 2919 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 2920 2921 val = (BCM_PAGE_BITS - 8) << 24; 2922 REG_WR(sc, BNX_RV2P_CONFIG, val); 2923 2924 /* Configure page size. */ 2925 val = REG_RD(sc, BNX_TBDR_CONFIG); 2926 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 2927 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 2928 REG_WR(sc, BNX_TBDR_CONFIG, val); 2929 2930 bnx_chipinit_exit: 2931 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2932 2933 return(rc); 2934 } 2935 2936 /****************************************************************************/ 2937 /* Initialize the controller in preparation to send/receive traffic. */ 2938 /* */ 2939 /* Returns: */ 2940 /* 0 for success, positive value for failure. */ 2941 /****************************************************************************/ 2942 int 2943 bnx_blockinit(struct bnx_softc *sc) 2944 { 2945 u_int32_t reg, val; 2946 int rc = 0; 2947 2948 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2949 2950 /* Load the hardware default MAC address. */ 2951 bnx_set_mac_addr(sc); 2952 2953 /* Set the Ethernet backoff seed value */ 2954 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 2955 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 2956 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 2957 2958 sc->last_status_idx = 0; 2959 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 2960 2961 /* Set up link change interrupt generation. */ 2962 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 2963 2964 /* Program the physical address of the status block. */ 2965 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 2966 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 2967 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 2968 2969 /* Program the physical address of the statistics block. */ 2970 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 2971 (u_int32_t)(sc->stats_block_paddr)); 2972 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 2973 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 2974 2975 /* Program various host coalescing parameters. */ 2976 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 2977 << 16) | sc->bnx_tx_quick_cons_trip); 2978 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 2979 << 16) | sc->bnx_rx_quick_cons_trip); 2980 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 2981 sc->bnx_comp_prod_trip); 2982 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 2983 sc->bnx_tx_ticks); 2984 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 2985 sc->bnx_rx_ticks); 2986 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 2987 sc->bnx_com_ticks); 2988 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 2989 sc->bnx_cmd_ticks); 2990 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 2991 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 2992 REG_WR(sc, BNX_HC_CONFIG, 2993 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 2994 BNX_HC_CONFIG_COLLECT_STATS)); 2995 2996 /* Clear the internal statistics counters. */ 2997 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 2998 2999 /* Verify that bootcode is running. */ 3000 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3001 3002 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3003 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3004 __FILE__, __LINE__); reg = 0); 3005 3006 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3007 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3008 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3009 "Expected: 08%08X\n", __FILE__, __LINE__, 3010 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3011 BNX_DEV_INFO_SIGNATURE_MAGIC); 3012 rc = ENODEV; 3013 goto bnx_blockinit_exit; 3014 } 3015 3016 /* Check if any management firmware is running. */ 3017 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3018 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3019 BNX_PORT_FEATURE_IMD_ENABLED)) { 3020 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3021 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3022 } 3023 3024 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3025 BNX_DEV_INFO_BC_REV); 3026 3027 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3028 3029 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3030 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3031 3032 /* Enable link state change interrupt generation. */ 3033 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3034 3035 /* Enable all remaining blocks in the MAC. */ 3036 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3037 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3038 DELAY(20); 3039 3040 bnx_blockinit_exit: 3041 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3042 3043 return (rc); 3044 } 3045 3046 /****************************************************************************/ 3047 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3048 /* */ 3049 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3050 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3051 /* necessary. */ 3052 /* */ 3053 /* Returns: */ 3054 /* 0 for success, positive value for failure. */ 3055 /****************************************************************************/ 3056 int 3057 bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod, 3058 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3059 { 3060 bus_dmamap_t map; 3061 struct mbuf *m_new = NULL; 3062 struct rx_bd *rxbd; 3063 int i, rc = 0; 3064 u_int32_t addr; 3065 #ifdef BNX_DEBUG 3066 u_int16_t debug_chain_prod = *chain_prod; 3067 #endif 3068 u_int16_t first_chain_prod; 3069 3070 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3071 __FUNCTION__); 3072 3073 /* Make sure the inputs are valid. */ 3074 DBRUNIF((*chain_prod > MAX_RX_BD), 3075 aprint_error("%s: RX producer out of range: 0x%04X > 0x%04X\n", 3076 sc->bnx_dev.dv_xname, *chain_prod, (u_int16_t) MAX_RX_BD)); 3077 3078 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3079 "0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, 3080 *prod_bseq); 3081 3082 if (m == NULL) { 3083 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3084 BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n"); 3085 3086 sc->mbuf_alloc_failed++; 3087 rc = ENOBUFS; 3088 goto bnx_get_buf_exit); 3089 3090 /* This is a new mbuf allocation. */ 3091 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3092 if (m_new == NULL) { 3093 DBPRINT(sc, BNX_WARN, 3094 "%s(%d): RX mbuf header allocation failed!\n", 3095 __FILE__, __LINE__); 3096 3097 DBRUNIF(1, sc->mbuf_alloc_failed++); 3098 3099 rc = ENOBUFS; 3100 goto bnx_get_buf_exit; 3101 } 3102 3103 DBRUNIF(1, sc->rx_mbuf_alloc++); 3104 MEXTMALLOC(m_new, sc->mbuf_alloc_size, M_DONTWAIT); 3105 if (!(m_new->m_flags & M_EXT)) { 3106 DBPRINT(sc, BNX_WARN, 3107 "%s(%d): RX mbuf chain allocation failed!\n", 3108 __FILE__, __LINE__); 3109 3110 m_freem(m_new); 3111 3112 DBRUNIF(1, sc->rx_mbuf_alloc--); 3113 DBRUNIF(1, sc->mbuf_alloc_failed++); 3114 3115 rc = ENOBUFS; 3116 goto bnx_get_buf_exit; 3117 } 3118 3119 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3120 } else { 3121 m_new = m; 3122 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3123 m_new->m_data = m_new->m_ext.ext_buf; 3124 } 3125 3126 /* Map the mbuf cluster into device memory. */ 3127 map = sc->rx_mbuf_map[*chain_prod]; 3128 first_chain_prod = *chain_prod; 3129 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3130 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3131 __FILE__, __LINE__); 3132 3133 m_freem(m_new); 3134 3135 DBRUNIF(1, sc->rx_mbuf_alloc--); 3136 3137 rc = ENOBUFS; 3138 goto bnx_get_buf_exit; 3139 } 3140 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3141 BUS_DMASYNC_PREREAD); 3142 3143 /* Watch for overflow. */ 3144 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3145 aprint_error("%s: Too many free rx_bd (0x%04X > 0x%04X)!\n", 3146 sc->bnx_dev.dv_xname, 3147 sc->free_rx_bd, (u_int16_t) USABLE_RX_BD)); 3148 3149 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3150 sc->rx_low_watermark = sc->free_rx_bd); 3151 3152 /* Setup the rx_bd for the first segment. */ 3153 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3154 3155 addr = (u_int32_t)(map->dm_segs[0].ds_addr); 3156 rxbd->rx_bd_haddr_lo = htole32(addr); 3157 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3158 rxbd->rx_bd_haddr_hi = htole32(addr); 3159 rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); 3160 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3161 *prod_bseq += map->dm_segs[0].ds_len; 3162 bus_dmamap_sync(sc->bnx_dmatag, 3163 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3164 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3165 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3166 3167 for (i = 1; i < map->dm_nsegs; i++) { 3168 *prod = NEXT_RX_BD(*prod); 3169 *chain_prod = RX_CHAIN_IDX(*prod); 3170 3171 rxbd = 3172 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3173 3174 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 3175 rxbd->rx_bd_haddr_lo = htole32(addr); 3176 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3177 rxbd->rx_bd_haddr_hi = htole32(addr); 3178 rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); 3179 rxbd->rx_bd_flags = 0; 3180 *prod_bseq += map->dm_segs[i].ds_len; 3181 bus_dmamap_sync(sc->bnx_dmatag, 3182 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3183 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3184 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3185 } 3186 3187 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3188 bus_dmamap_sync(sc->bnx_dmatag, 3189 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3190 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3191 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3192 3193 /* 3194 * Save the mbuf, ajust the map pointer (swap map for first and 3195 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3196 * and update counter. 3197 */ 3198 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3199 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3200 sc->rx_mbuf_map[*chain_prod] = map; 3201 sc->free_rx_bd -= map->dm_nsegs; 3202 3203 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3204 map->dm_nsegs)); 3205 3206 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3207 "= 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, 3208 *chain_prod, *prod_bseq); 3209 3210 bnx_get_buf_exit: 3211 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3212 __FUNCTION__); 3213 3214 return(rc); 3215 } 3216 3217 /****************************************************************************/ 3218 /* Allocate memory and initialize the TX data structures. */ 3219 /* */ 3220 /* Returns: */ 3221 /* 0 for success, positive value for failure. */ 3222 /****************************************************************************/ 3223 int 3224 bnx_init_tx_chain(struct bnx_softc *sc) 3225 { 3226 struct tx_bd *txbd; 3227 u_int32_t val, addr; 3228 int i, rc = 0; 3229 3230 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3231 3232 /* Set the initial TX producer/consumer indices. */ 3233 sc->tx_prod = 0; 3234 sc->tx_cons = 0; 3235 sc->tx_prod_bseq = 0; 3236 sc->used_tx_bd = 0; 3237 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3238 3239 /* 3240 * The NetXtreme II supports a linked-list structure called 3241 * a Buffer Descriptor Chain (or BD chain). A BD chain 3242 * consists of a series of 1 or more chain pages, each of which 3243 * consists of a fixed number of BD entries. 3244 * The last BD entry on each page is a pointer to the next page 3245 * in the chain, and the last pointer in the BD chain 3246 * points back to the beginning of the chain. 3247 */ 3248 3249 /* Set the TX next pointer chain entries. */ 3250 for (i = 0; i < TX_PAGES; i++) { 3251 int j; 3252 3253 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3254 3255 /* Check if we've reached the last page. */ 3256 if (i == (TX_PAGES - 1)) 3257 j = 0; 3258 else 3259 j = i + 1; 3260 3261 addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); 3262 txbd->tx_bd_haddr_lo = htole32(addr); 3263 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3264 txbd->tx_bd_haddr_hi = htole32(addr); 3265 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3266 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3267 } 3268 3269 /* 3270 * Initialize the context ID for an L2 TX chain. 3271 */ 3272 val = BNX_L2CTX_TYPE_TYPE_L2; 3273 val |= BNX_L2CTX_TYPE_SIZE_L2; 3274 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3275 3276 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3277 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3278 3279 /* Point the hardware to the first page in the chain. */ 3280 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3281 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3282 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3283 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3284 3285 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3286 3287 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3288 3289 return(rc); 3290 } 3291 3292 /****************************************************************************/ 3293 /* Free memory and clear the TX data structures. */ 3294 /* */ 3295 /* Returns: */ 3296 /* Nothing. */ 3297 /****************************************************************************/ 3298 void 3299 bnx_free_tx_chain(struct bnx_softc *sc) 3300 { 3301 int i; 3302 3303 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3304 3305 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3306 for (i = 0; i < TOTAL_TX_BD; i++) { 3307 if (sc->tx_mbuf_ptr[i] != NULL) { 3308 if (sc->tx_mbuf_map != NULL) 3309 bus_dmamap_sync(sc->bnx_dmatag, 3310 sc->tx_mbuf_map[i], 0, 3311 sc->tx_mbuf_map[i]->dm_mapsize, 3312 BUS_DMASYNC_POSTWRITE); 3313 m_freem(sc->tx_mbuf_ptr[i]); 3314 sc->tx_mbuf_ptr[i] = NULL; 3315 DBRUNIF(1, sc->tx_mbuf_alloc--); 3316 } 3317 } 3318 3319 /* Clear each TX chain page. */ 3320 for (i = 0; i < TX_PAGES; i++) { 3321 bzero((char *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 3322 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3323 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3324 } 3325 3326 /* Check if we lost any mbufs in the process. */ 3327 DBRUNIF((sc->tx_mbuf_alloc), 3328 aprint_error("%s: Memory leak! Lost %d mbufs from tx chain!\n", 3329 sc->bnx_dev.dv_xname, sc->tx_mbuf_alloc)); 3330 3331 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3332 } 3333 3334 /****************************************************************************/ 3335 /* Allocate memory and initialize the RX data structures. */ 3336 /* */ 3337 /* Returns: */ 3338 /* 0 for success, positive value for failure. */ 3339 /****************************************************************************/ 3340 int 3341 bnx_init_rx_chain(struct bnx_softc *sc) 3342 { 3343 struct rx_bd *rxbd; 3344 int i, rc = 0; 3345 u_int16_t prod, chain_prod; 3346 u_int32_t prod_bseq, val, addr; 3347 3348 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3349 3350 /* Initialize the RX producer and consumer indices. */ 3351 sc->rx_prod = 0; 3352 sc->rx_cons = 0; 3353 sc->rx_prod_bseq = 0; 3354 sc->free_rx_bd = BNX_RX_SLACK_SPACE; 3355 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3356 3357 /* Initialize the RX next pointer chain entries. */ 3358 for (i = 0; i < RX_PAGES; i++) { 3359 int j; 3360 3361 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3362 3363 /* Check if we've reached the last page. */ 3364 if (i == (RX_PAGES - 1)) 3365 j = 0; 3366 else 3367 j = i + 1; 3368 3369 /* Setup the chain page pointers. */ 3370 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 3371 rxbd->rx_bd_haddr_hi = htole32(addr); 3372 addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); 3373 rxbd->rx_bd_haddr_lo = htole32(addr); 3374 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 3375 0, BNX_RX_CHAIN_PAGE_SZ, 3376 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3377 } 3378 3379 /* Initialize the context ID for an L2 RX chain. */ 3380 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3381 val |= BNX_L2CTX_CTX_TYPE_SIZE_L2; 3382 val |= 0x02 << 8; 3383 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 3384 3385 /* Point the hardware to the first page in the chain. */ 3386 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 3387 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 3388 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 3389 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 3390 3391 /* Allocate mbuf clusters for the rx_bd chain. */ 3392 prod = prod_bseq = 0; 3393 while (prod < BNX_RX_SLACK_SPACE) { 3394 chain_prod = RX_CHAIN_IDX(prod); 3395 if (bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3396 BNX_PRINTF(sc, 3397 "Error filling RX chain: rx_bd[0x%04X]!\n", 3398 chain_prod); 3399 rc = ENOBUFS; 3400 break; 3401 } 3402 prod = NEXT_RX_BD(prod); 3403 } 3404 3405 /* Save the RX chain producer index. */ 3406 sc->rx_prod = prod; 3407 sc->rx_prod_bseq = prod_bseq; 3408 3409 for (i = 0; i < RX_PAGES; i++) 3410 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 3411 sc->rx_bd_chain_map[i]->dm_mapsize, 3412 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3413 3414 /* Tell the chip about the waiting rx_bd's. */ 3415 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3416 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3417 3418 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3419 3420 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3421 3422 return(rc); 3423 } 3424 3425 /****************************************************************************/ 3426 /* Free memory and clear the RX data structures. */ 3427 /* */ 3428 /* Returns: */ 3429 /* Nothing. */ 3430 /****************************************************************************/ 3431 void 3432 bnx_free_rx_chain(struct bnx_softc *sc) 3433 { 3434 int i; 3435 3436 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3437 3438 /* Free any mbufs still in the RX mbuf chain. */ 3439 for (i = 0; i < TOTAL_RX_BD; i++) { 3440 if (sc->rx_mbuf_ptr[i] != NULL) { 3441 if (sc->rx_mbuf_map[i] != NULL) 3442 bus_dmamap_sync(sc->bnx_dmatag, 3443 sc->rx_mbuf_map[i], 0, 3444 sc->rx_mbuf_map[i]->dm_mapsize, 3445 BUS_DMASYNC_POSTREAD); 3446 m_freem(sc->rx_mbuf_ptr[i]); 3447 sc->rx_mbuf_ptr[i] = NULL; 3448 DBRUNIF(1, sc->rx_mbuf_alloc--); 3449 } 3450 } 3451 3452 /* Clear each RX chain page. */ 3453 for (i = 0; i < RX_PAGES; i++) 3454 bzero((char *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 3455 3456 /* Check if we lost any mbufs in the process. */ 3457 DBRUNIF((sc->rx_mbuf_alloc), 3458 aprint_error("%s: Memory leak! Lost %d mbufs from rx chain!\n", 3459 sc->bnx_dev.dv_xname, sc->rx_mbuf_alloc)); 3460 3461 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3462 } 3463 3464 /****************************************************************************/ 3465 /* Set media options. */ 3466 /* */ 3467 /* Returns: */ 3468 /* 0 for success, positive value for failure. */ 3469 /****************************************************************************/ 3470 int 3471 bnx_ifmedia_upd(struct ifnet *ifp) 3472 { 3473 struct bnx_softc *sc; 3474 struct mii_data *mii; 3475 struct ifmedia *ifm; 3476 int rc = 0; 3477 3478 sc = ifp->if_softc; 3479 ifm = &sc->bnx_ifmedia; 3480 3481 /* DRC - ToDo: Add SerDes support. */ 3482 3483 mii = &sc->bnx_mii; 3484 sc->bnx_link = 0; 3485 if (mii->mii_instance) { 3486 struct mii_softc *miisc; 3487 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3488 mii_phy_reset(miisc); 3489 } 3490 mii_mediachg(mii); 3491 3492 return(rc); 3493 } 3494 3495 /****************************************************************************/ 3496 /* Reports current media status. */ 3497 /* */ 3498 /* Returns: */ 3499 /* Nothing. */ 3500 /****************************************************************************/ 3501 void 3502 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3503 { 3504 struct bnx_softc *sc; 3505 struct mii_data *mii; 3506 int s; 3507 3508 sc = ifp->if_softc; 3509 3510 s = splnet(); 3511 3512 mii = &sc->bnx_mii; 3513 3514 /* DRC - ToDo: Add SerDes support. */ 3515 3516 mii_pollstat(mii); 3517 ifmr->ifm_active = mii->mii_media_active; 3518 ifmr->ifm_status = mii->mii_media_status; 3519 3520 splx(s); 3521 } 3522 3523 /****************************************************************************/ 3524 /* Handles PHY generated interrupt events. */ 3525 /* */ 3526 /* Returns: */ 3527 /* Nothing. */ 3528 /****************************************************************************/ 3529 void 3530 bnx_phy_intr(struct bnx_softc *sc) 3531 { 3532 u_int32_t new_link_state, old_link_state; 3533 3534 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3535 BUS_DMASYNC_POSTREAD); 3536 new_link_state = sc->status_block->status_attn_bits & 3537 STATUS_ATTN_BITS_LINK_STATE; 3538 old_link_state = sc->status_block->status_attn_bits_ack & 3539 STATUS_ATTN_BITS_LINK_STATE; 3540 3541 /* Handle any changes if the link state has changed. */ 3542 if (new_link_state != old_link_state) { 3543 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 3544 3545 sc->bnx_link = 0; 3546 callout_stop(&sc->bnx_timeout); 3547 bnx_tick(sc); 3548 3549 /* Update the status_attn_bits_ack field in the status block. */ 3550 if (new_link_state) { 3551 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 3552 STATUS_ATTN_BITS_LINK_STATE); 3553 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 3554 } else { 3555 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 3556 STATUS_ATTN_BITS_LINK_STATE); 3557 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 3558 } 3559 } 3560 3561 /* Acknowledge the link change interrupt. */ 3562 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 3563 } 3564 3565 /****************************************************************************/ 3566 /* Handles received frame interrupt events. */ 3567 /* */ 3568 /* Returns: */ 3569 /* Nothing. */ 3570 /****************************************************************************/ 3571 void 3572 bnx_rx_intr(struct bnx_softc *sc) 3573 { 3574 struct status_block *sblk = sc->status_block; 3575 struct ifnet *ifp = &sc->ethercom.ec_if; 3576 u_int16_t hw_cons, sw_cons, sw_chain_cons; 3577 u_int16_t sw_prod, sw_chain_prod; 3578 u_int32_t sw_prod_bseq; 3579 struct l2_fhdr *l2fhdr; 3580 int i; 3581 3582 DBRUNIF(1, sc->rx_interrupts++); 3583 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3584 BUS_DMASYNC_POSTREAD); 3585 3586 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3587 for (i = 0; i < RX_PAGES; i++) 3588 bus_dmamap_sync(sc->bnx_dmatag, 3589 sc->rx_bd_chain_map[i], 0, 3590 sc->rx_bd_chain_map[i]->dm_mapsize, 3591 BUS_DMASYNC_POSTWRITE); 3592 3593 /* Get the hardware's view of the RX consumer index. */ 3594 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3595 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3596 hw_cons++; 3597 3598 /* Get working copies of the driver's view of the RX indices. */ 3599 sw_cons = sc->rx_cons; 3600 sw_prod = sc->rx_prod; 3601 sw_prod_bseq = sc->rx_prod_bseq; 3602 3603 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3604 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3605 __FUNCTION__, sw_prod, sw_cons, sw_prod_bseq); 3606 3607 /* Prevent speculative reads from getting ahead of the status block. */ 3608 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3609 BUS_SPACE_BARRIER_READ); 3610 3611 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3612 sc->rx_low_watermark = sc->free_rx_bd); 3613 3614 /* 3615 * Scan through the receive chain as long 3616 * as there is work to do. 3617 */ 3618 while (sw_cons != hw_cons) { 3619 struct mbuf *m; 3620 struct rx_bd *rxbd; 3621 unsigned int len; 3622 u_int32_t status; 3623 3624 /* Convert the producer/consumer indices to an actual 3625 * rx_bd index. 3626 */ 3627 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3628 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3629 3630 /* Get the used rx_bd. */ 3631 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3632 sc->free_rx_bd++; 3633 3634 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __FUNCTION__); 3635 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 3636 3637 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3638 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3639 /* Validate that this is the last rx_bd. */ 3640 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), 3641 aprint_error("%s: Unexpected mbuf found in " 3642 "rx_bd[0x%04X]!\n", sc->bnx_dev.dv_xname, 3643 sw_chain_cons); 3644 bnx_breakpoint(sc)); 3645 3646 /* DRC - ToDo: If the received packet is small, say less 3647 * than 128 bytes, allocate a new mbuf here, 3648 * copy the data to that mbuf, and recycle 3649 * the mapped jumbo frame. 3650 */ 3651 3652 /* Unmap the mbuf from DMA space. */ 3653 bus_dmamap_sync(sc->bnx_dmatag, 3654 sc->rx_mbuf_map[sw_chain_cons], 0, 3655 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 3656 BUS_DMASYNC_POSTREAD); 3657 bus_dmamap_unload(sc->bnx_dmatag, 3658 sc->rx_mbuf_map[sw_chain_cons]); 3659 3660 /* Remove the mbuf from the driver's chain. */ 3661 m = sc->rx_mbuf_ptr[sw_chain_cons]; 3662 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 3663 3664 /* 3665 * Frames received on the NetXteme II are prepended 3666 * with the l2_fhdr structure which provides status 3667 * information about the received frame (including 3668 * VLAN tags and checksum info) and are also 3669 * automatically adjusted to align the IP header 3670 * (i.e. two null bytes are inserted before the 3671 * Ethernet header). 3672 */ 3673 l2fhdr = mtod(m, struct l2_fhdr *); 3674 3675 len = l2fhdr->l2_fhdr_pkt_len; 3676 status = l2fhdr->l2_fhdr_status; 3677 3678 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 3679 aprint_error("Simulating l2_fhdr status error.\n"); 3680 status = status | L2_FHDR_ERRORS_PHY_DECODE); 3681 3682 /* Watch for unusual sized frames. */ 3683 DBRUNIF(((len < BNX_MIN_MTU) || 3684 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 3685 aprint_error("%s: Unusual frame size found. " 3686 "Min(%d), Actual(%d), Max(%d)\n", 3687 sc->bnx_dev.dv_xname, (int)BNX_MIN_MTU, len, 3688 (int) BNX_MAX_JUMBO_ETHER_MTU_VLAN); 3689 3690 bnx_dump_mbuf(sc, m); 3691 bnx_breakpoint(sc)); 3692 3693 len -= ETHER_CRC_LEN; 3694 3695 /* Check the received frame for errors. */ 3696 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 3697 L2_FHDR_ERRORS_PHY_DECODE | 3698 L2_FHDR_ERRORS_ALIGNMENT | 3699 L2_FHDR_ERRORS_TOO_SHORT | 3700 L2_FHDR_ERRORS_GIANT_FRAME)) || 3701 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 3702 len > 3703 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 3704 ifp->if_ierrors++; 3705 DBRUNIF(1, sc->l2fhdr_status_errors++); 3706 3707 /* Reuse the mbuf for a new frame. */ 3708 if (bnx_get_buf(sc, m, &sw_prod, 3709 &sw_chain_prod, &sw_prod_bseq)) { 3710 DBRUNIF(1, bnx_breakpoint(sc)); 3711 panic("%s: Can't reuse RX mbuf!\n", 3712 sc->bnx_dev.dv_xname); 3713 } 3714 goto bnx_rx_int_next_rx; 3715 } 3716 3717 /* 3718 * Get a new mbuf for the rx_bd. If no new 3719 * mbufs are available then reuse the current mbuf, 3720 * log an ierror on the interface, and generate 3721 * an error in the system log. 3722 */ 3723 if (bnx_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, 3724 &sw_prod_bseq)) { 3725 DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate " 3726 "new mbuf, incoming frame dropped!\n")); 3727 3728 ifp->if_ierrors++; 3729 3730 /* Try and reuse the exisitng mbuf. */ 3731 if (bnx_get_buf(sc, m, &sw_prod, 3732 &sw_chain_prod, &sw_prod_bseq)) { 3733 DBRUNIF(1, bnx_breakpoint(sc)); 3734 panic("%s: Double mbuf allocation " 3735 "failure!", sc->bnx_dev.dv_xname); 3736 } 3737 goto bnx_rx_int_next_rx; 3738 } 3739 3740 /* Skip over the l2_fhdr when passing the data up 3741 * the stack. 3742 */ 3743 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 3744 3745 /* Adjust the pckt length to match the received data. */ 3746 m->m_pkthdr.len = m->m_len = len; 3747 3748 /* Send the packet to the appropriate interface. */ 3749 m->m_pkthdr.rcvif = ifp; 3750 3751 DBRUN(BNX_VERBOSE_RECV, 3752 struct ether_header *eh; 3753 eh = mtod(m, struct ether_header *); 3754 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 3755 __FUNCTION__, ether_sprintf(eh->ether_dhost), 3756 ether_sprintf(eh->ether_shost), 3757 htons(eh->ether_type))); 3758 3759 /* Validate the checksum. */ 3760 3761 /* Check for an IP datagram. */ 3762 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 3763 /* Check if the IP checksum is valid. */ 3764 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 3765 == 0) 3766 m->m_pkthdr.csum_flags |= 3767 M_CSUM_IPv4; 3768 #ifdef BNX_DEBUG 3769 else 3770 DBPRINT(sc, BNX_WARN_SEND, 3771 "%s(): Invalid IP checksum " 3772 "= 0x%04X!\n", 3773 __FUNCTION__, 3774 l2fhdr->l2_fhdr_ip_xsum 3775 ); 3776 #endif 3777 } 3778 3779 /* Check for a valid TCP/UDP frame. */ 3780 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3781 L2_FHDR_STATUS_UDP_DATAGRAM)) { 3782 /* Check for a good TCP/UDP checksum. */ 3783 if ((status & 3784 (L2_FHDR_ERRORS_TCP_XSUM | 3785 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 3786 m->m_pkthdr.csum_flags |= 3787 M_CSUM_TCPv4 | 3788 M_CSUM_UDPv4; 3789 } else { 3790 DBPRINT(sc, BNX_WARN_SEND, 3791 "%s(): Invalid TCP/UDP " 3792 "checksum = 0x%04X!\n", 3793 __FUNCTION__, 3794 l2fhdr->l2_fhdr_tcp_udp_xsum); 3795 } 3796 } 3797 3798 /* 3799 * If we received a packet with a vlan tag, 3800 * attach that information to the packet. 3801 */ 3802 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 3803 #if 0 3804 struct ether_vlan_header vh; 3805 3806 DBPRINT(sc, BNX_VERBOSE_SEND, 3807 "%s(): VLAN tag = 0x%04X\n", 3808 __FUNCTION__, 3809 l2fhdr->l2_fhdr_vlan_tag); 3810 3811 if (m->m_pkthdr.len < ETHER_HDR_LEN) { 3812 m_freem(m); 3813 goto bnx_rx_int_next_rx; 3814 } 3815 m_copydata(m, 0, ETHER_HDR_LEN, (void *)&vh); 3816 vh.evl_proto = vh.evl_encap_proto; 3817 vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag; 3818 vh.evl_encap_proto = htons(ETHERTYPE_VLAN); 3819 m_adj(m, ETHER_HDR_LEN); 3820 if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL) 3821 goto bnx_rx_int_next_rx; 3822 m->m_pkthdr.len += sizeof(vh); 3823 if (m->m_len < sizeof(vh) && 3824 (m = m_pullup(m, sizeof(vh))) == NULL) 3825 goto bnx_rx_int_next_rx; 3826 m_copyback(m, 0, sizeof(vh), &vh); 3827 #else 3828 VLAN_INPUT_TAG(ifp, m, 3829 l2fhdr->l2_fhdr_vlan_tag >> 16, 3830 goto bnx_rx_int_next_rx); 3831 #endif 3832 } 3833 3834 #if NBPFILTER > 0 3835 /* 3836 * Handle BPF listeners. Let the BPF 3837 * user see the packet. 3838 */ 3839 if (ifp->if_bpf) 3840 bpf_mtap(ifp->if_bpf, m); 3841 #endif 3842 3843 /* Pass the mbuf off to the upper layers. */ 3844 ifp->if_ipackets++; 3845 DBPRINT(sc, BNX_VERBOSE_RECV, 3846 "%s(): Passing received frame up.\n", __FUNCTION__); 3847 //ether_input_mbuf(ifp, m); 3848 (*ifp->if_input)(ifp, m); 3849 DBRUNIF(1, sc->rx_mbuf_alloc--); 3850 3851 bnx_rx_int_next_rx: 3852 sw_prod = NEXT_RX_BD(sw_prod); 3853 } 3854 3855 sw_cons = NEXT_RX_BD(sw_cons); 3856 3857 /* Refresh hw_cons to see if there's new work */ 3858 if (sw_cons == hw_cons) { 3859 hw_cons = sc->hw_rx_cons = 3860 sblk->status_rx_quick_consumer_index0; 3861 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 3862 USABLE_RX_BD_PER_PAGE) 3863 hw_cons++; 3864 } 3865 3866 /* Prevent speculative reads from getting ahead of 3867 * the status block. 3868 */ 3869 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3870 BUS_SPACE_BARRIER_READ); 3871 } 3872 3873 for (i = 0; i < RX_PAGES; i++) 3874 bus_dmamap_sync(sc->bnx_dmatag, 3875 sc->rx_bd_chain_map[i], 0, 3876 sc->rx_bd_chain_map[i]->dm_mapsize, 3877 BUS_DMASYNC_PREWRITE); 3878 3879 sc->rx_cons = sw_cons; 3880 sc->rx_prod = sw_prod; 3881 sc->rx_prod_bseq = sw_prod_bseq; 3882 3883 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 3884 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3885 3886 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 3887 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 3888 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 3889 } 3890 3891 /****************************************************************************/ 3892 /* Handles transmit completion interrupt events. */ 3893 /* */ 3894 /* Returns: */ 3895 /* Nothing. */ 3896 /****************************************************************************/ 3897 void 3898 bnx_tx_intr(struct bnx_softc *sc) 3899 { 3900 struct status_block *sblk = sc->status_block; 3901 struct ifnet *ifp = &sc->ethercom.ec_if; 3902 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 3903 3904 DBRUNIF(1, sc->tx_interrupts++); 3905 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 3906 BUS_DMASYNC_POSTREAD); 3907 3908 /* Get the hardware's view of the TX consumer index. */ 3909 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 3910 3911 /* Skip to the next entry if this is a chain page pointer. */ 3912 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 3913 hw_tx_cons++; 3914 3915 sw_tx_cons = sc->tx_cons; 3916 3917 /* Prevent speculative reads from getting ahead of the status block. */ 3918 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3919 BUS_SPACE_BARRIER_READ); 3920 3921 /* Cycle through any completed TX chain page entries. */ 3922 while (sw_tx_cons != hw_tx_cons) { 3923 #ifdef BNX_DEBUG 3924 struct tx_bd *txbd = NULL; 3925 #endif 3926 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 3927 3928 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 3929 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 3930 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 3931 3932 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 3933 aprint_error("%s: TX chain consumer out of range! " 3934 " 0x%04X > 0x%04X\n", sc->bnx_dev.dv_xname, 3935 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 3936 3937 DBRUNIF(1, txbd = &sc->tx_bd_chain 3938 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 3939 3940 DBRUNIF((txbd == NULL), 3941 aprint_error("%s: Unexpected NULL tx_bd[0x%04X]!\n", 3942 sc->bnx_dev.dv_xname, sw_tx_chain_cons); 3943 bnx_breakpoint(sc)); 3944 3945 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __FUNCTION__); 3946 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 3947 3948 /* 3949 * Free the associated mbuf. Remember 3950 * that only the last tx_bd of a packet 3951 * has an mbuf pointer and DMA map. 3952 */ 3953 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 3954 /* Validate that this is the last tx_bd. */ 3955 DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & 3956 TX_BD_FLAGS_END)), 3957 aprint_error("%s: tx_bd END flag not set but " 3958 "txmbuf == NULL!\n", sc->bnx_dev.dv_xname); 3959 bnx_breakpoint(sc)); 3960 3961 DBRUN(BNX_INFO_SEND, 3962 aprint_debug("%s: Unloading map/freeing mbuf " 3963 "from tx_bd[0x%04X]\n", 3964 __FUNCTION__, sw_tx_chain_cons)); 3965 3966 /* Unmap the mbuf. */ 3967 bus_dmamap_unload(sc->bnx_dmatag, 3968 sc->tx_mbuf_map[sw_tx_chain_cons]); 3969 3970 /* Free the mbuf. */ 3971 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 3972 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 3973 DBRUNIF(1, sc->tx_mbuf_alloc--); 3974 3975 ifp->if_opackets++; 3976 } 3977 3978 sc->used_tx_bd--; 3979 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 3980 3981 /* Refresh hw_cons to see if there's new work. */ 3982 hw_tx_cons = sc->hw_tx_cons = 3983 sblk->status_tx_quick_consumer_index0; 3984 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 3985 USABLE_TX_BD_PER_PAGE) 3986 hw_tx_cons++; 3987 3988 /* Prevent speculative reads from getting ahead of 3989 * the status block. 3990 */ 3991 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 3992 BUS_SPACE_BARRIER_READ); 3993 } 3994 3995 /* Clear the TX timeout timer. */ 3996 ifp->if_timer = 0; 3997 3998 /* Clear the tx hardware queue full flag. */ 3999 if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) { 4000 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4001 aprint_debug("%s: TX chain is open for business! Used " 4002 "tx_bd = %d\n", sc->bnx_dev.dv_xname, 4003 sc->used_tx_bd)); 4004 ifp->if_flags &= ~IFF_OACTIVE; 4005 } 4006 4007 sc->tx_cons = sw_tx_cons; 4008 } 4009 4010 /****************************************************************************/ 4011 /* Disables interrupt generation. */ 4012 /* */ 4013 /* Returns: */ 4014 /* Nothing. */ 4015 /****************************************************************************/ 4016 void 4017 bnx_disable_intr(struct bnx_softc *sc) 4018 { 4019 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4020 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4021 } 4022 4023 /****************************************************************************/ 4024 /* Enables interrupt generation. */ 4025 /* */ 4026 /* Returns: */ 4027 /* Nothing. */ 4028 /****************************************************************************/ 4029 void 4030 bnx_enable_intr(struct bnx_softc *sc) 4031 { 4032 u_int32_t val; 4033 4034 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4035 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4036 4037 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4038 sc->last_status_idx); 4039 4040 val = REG_RD(sc, BNX_HC_COMMAND); 4041 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4042 } 4043 4044 /****************************************************************************/ 4045 /* Handles controller initialization. */ 4046 /* */ 4047 /****************************************************************************/ 4048 int 4049 bnx_init(struct ifnet *ifp) 4050 { 4051 struct bnx_softc *sc = ifp->if_softc; 4052 u_int32_t ether_mtu; 4053 int s, error = 0; 4054 4055 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4056 4057 s = splnet(); 4058 4059 bnx_stop(sc); 4060 4061 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4062 aprint_error("bnx: Controller reset failed!\n"); 4063 goto bnx_init_exit; 4064 } 4065 4066 if ((error = bnx_chipinit(sc)) != 0) { 4067 aprint_error("bnx: Controller initialization failed!\n"); 4068 goto bnx_init_exit; 4069 } 4070 4071 if ((error = bnx_blockinit(sc)) != 0) { 4072 aprint_error("bnx: Block initialization failed!\n"); 4073 goto bnx_init_exit; 4074 } 4075 4076 /* Calculate and program the Ethernet MRU size. */ 4077 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4078 4079 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4080 __FUNCTION__, ether_mtu); 4081 4082 /* 4083 * Program the MRU and enable Jumbo frame 4084 * support. 4085 */ 4086 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4087 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4088 4089 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4090 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4091 4092 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4093 "max_frame_size = %d\n", __FUNCTION__, (int)MCLBYTES, 4094 sc->mbuf_alloc_size, sc->max_frame_size); 4095 4096 /* Program appropriate promiscuous/multicast filtering. */ 4097 bnx_set_rx_mode(sc); 4098 4099 /* Init RX buffer descriptor chain. */ 4100 bnx_init_rx_chain(sc); 4101 4102 /* Init TX buffer descriptor chain. */ 4103 bnx_init_tx_chain(sc); 4104 4105 /* Enable host interrupts. */ 4106 bnx_enable_intr(sc); 4107 4108 bnx_ifmedia_upd(ifp); 4109 4110 ifp->if_flags |= IFF_RUNNING; 4111 ifp->if_flags &= ~IFF_OACTIVE; 4112 4113 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4114 4115 bnx_init_exit: 4116 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4117 4118 splx(s); 4119 4120 return(error); 4121 } 4122 4123 /****************************************************************************/ 4124 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4125 /* memory visible to the controller. */ 4126 /* */ 4127 /* Returns: */ 4128 /* 0 for success, positive value for failure. */ 4129 /****************************************************************************/ 4130 int 4131 bnx_tx_encap(struct bnx_softc *sc, struct mbuf **m_head) 4132 { 4133 bus_dmamap_t map; 4134 struct tx_bd *txbd = NULL; 4135 struct mbuf *m0; 4136 u_int16_t vlan_tag = 0, flags = 0; 4137 u_int16_t chain_prod, prod; 4138 #ifdef BNX_DEBUG 4139 u_int16_t debug_prod; 4140 #endif 4141 u_int32_t addr, prod_bseq; 4142 int i, error, rc = 0; 4143 struct m_tag *mtag; 4144 4145 m0 = *m_head; 4146 4147 /* Transfer any checksum offload flags to the bd. */ 4148 if (m0->m_pkthdr.csum_flags) { 4149 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 4150 flags |= TX_BD_FLAGS_IP_CKSUM; 4151 if (m0->m_pkthdr.csum_flags & 4152 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4153 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4154 } 4155 4156 /* Transfer any VLAN tags to the bd. */ 4157 mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m0); 4158 if (mtag != NULL) { 4159 flags |= TX_BD_FLAGS_VLAN_TAG; 4160 vlan_tag = VLAN_TAG_VALUE(mtag); 4161 } 4162 4163 /* Map the mbuf into DMAable memory. */ 4164 prod = sc->tx_prod; 4165 chain_prod = TX_CHAIN_IDX(prod); 4166 map = sc->tx_mbuf_map[chain_prod]; 4167 4168 /* Map the mbuf into our DMA address space. */ 4169 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m0, BUS_DMA_NOWAIT); 4170 if (error != 0) { 4171 aprint_error("%s: Error mapping mbuf into TX chain!\n", 4172 sc->bnx_dev.dv_xname); 4173 m_freem(m0); 4174 *m_head = NULL; 4175 return (error); 4176 } 4177 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4178 BUS_DMASYNC_PREWRITE); 4179 /* 4180 * The chip seems to require that at least 16 descriptors be kept 4181 * empty at all times. Make sure we honor that. 4182 * XXX Would it be faster to assume worst case scenario for 4183 * map->dm_nsegs and do this calculation higher up? 4184 */ 4185 if (map->dm_nsegs > (USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE)) { 4186 bus_dmamap_unload(sc->bnx_dmatag, map); 4187 return (ENOBUFS); 4188 } 4189 4190 /* prod points to an empty tx_bd at this point. */ 4191 prod_bseq = sc->tx_prod_bseq; 4192 #ifdef BNX_DEBUG 4193 debug_prod = chain_prod; 4194 #endif 4195 DBPRINT(sc, BNX_INFO_SEND, 4196 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4197 "prod_bseq = 0x%08X\n", 4198 __FUNCTION__, *prod, chain_prod, prod_bseq); 4199 4200 /* 4201 * Cycle through each mbuf segment that makes up 4202 * the outgoing frame, gathering the mapping info 4203 * for that segment and creating a tx_bd for the 4204 * mbuf. 4205 */ 4206 for (i = 0; i < map->dm_nsegs ; i++) { 4207 chain_prod = TX_CHAIN_IDX(prod); 4208 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4209 4210 addr = (u_int32_t)(map->dm_segs[i].ds_addr); 4211 txbd->tx_bd_haddr_lo = htole32(addr); 4212 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4213 txbd->tx_bd_haddr_hi = htole32(addr); 4214 txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); 4215 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4216 txbd->tx_bd_flags = htole16(flags); 4217 prod_bseq += map->dm_segs[i].ds_len; 4218 if (i == 0) 4219 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4220 prod = NEXT_TX_BD(prod); 4221 } 4222 /* Set the END flag on the last TX buffer descriptor. */ 4223 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4224 4225 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg)); 4226 4227 DBPRINT(sc, BNX_INFO_SEND, 4228 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4229 "prod_bseq = 0x%08X\n", 4230 __FUNCTION__, prod, chain_prod, prod_bseq); 4231 4232 /* 4233 * Ensure that the mbuf pointer for this 4234 * transmission is placed at the array 4235 * index of the last descriptor in this 4236 * chain. This is done because a single 4237 * map is used for all segments of the mbuf 4238 * and we don't want to unload the map before 4239 * all of the segments have been freed. 4240 */ 4241 sc->tx_mbuf_ptr[chain_prod] = m0; 4242 sc->used_tx_bd += map->dm_nsegs; 4243 4244 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4245 sc->tx_hi_watermark = sc->used_tx_bd); 4246 4247 DBRUNIF(1, sc->tx_mbuf_alloc++); 4248 4249 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4250 map_arg.maxsegs)); 4251 4252 /* prod points to the next free tx_bd at this point. */ 4253 sc->tx_prod = prod; 4254 sc->tx_prod_bseq = prod_bseq; 4255 4256 return (rc); 4257 } 4258 4259 /****************************************************************************/ 4260 /* Main transmit routine. */ 4261 /* */ 4262 /* Returns: */ 4263 /* Nothing. */ 4264 /****************************************************************************/ 4265 void 4266 bnx_start(struct ifnet *ifp) 4267 { 4268 struct bnx_softc *sc = ifp->if_softc; 4269 struct mbuf *m_head = NULL; 4270 int count = 0; 4271 u_int16_t tx_prod, tx_chain_prod; 4272 4273 /* If there's no link or the transmit queue is empty then just exit. */ 4274 if (!sc->bnx_link || IFQ_IS_EMPTY(&ifp->if_snd)) { 4275 DBPRINT(sc, BNX_INFO_SEND, 4276 "%s(): No link or transmit queue empty.\n", __FUNCTION__); 4277 goto bnx_start_exit; 4278 } 4279 4280 /* prod points to the next free tx_bd. */ 4281 tx_prod = sc->tx_prod; 4282 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4283 4284 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 4285 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n", 4286 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4287 4288 /* 4289 * Keep adding entries while there is space in the ring. We keep 4290 * BNX_TX_SLACK_SPACE entries unused at all times. 4291 */ 4292 while (sc->used_tx_bd < USABLE_TX_BD - BNX_TX_SLACK_SPACE) { 4293 /* Check for any frames to send. */ 4294 IFQ_POLL(&ifp->if_snd, m_head); 4295 if (m_head == NULL) 4296 break; 4297 4298 /* 4299 * Pack the data into the transmit ring. If we 4300 * don't have room, set the OACTIVE flag to wait 4301 * for the NIC to drain the chain. 4302 */ 4303 if (bnx_tx_encap(sc, &m_head)) { 4304 ifp->if_flags |= IFF_OACTIVE; 4305 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 4306 "business! Total tx_bd used = %d\n", 4307 sc->used_tx_bd); 4308 break; 4309 } 4310 4311 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4312 count++; 4313 4314 #if NBPFILTER > 0 4315 /* Send a copy of the frame to any BPF listeners. */ 4316 if (ifp->if_bpf) 4317 bpf_mtap(ifp->if_bpf, m_head); 4318 #endif 4319 } 4320 4321 if (count == 0) { 4322 /* no packets were dequeued */ 4323 DBPRINT(sc, BNX_VERBOSE_SEND, 4324 "%s(): No packets were dequeued\n", __FUNCTION__); 4325 goto bnx_start_exit; 4326 } 4327 4328 /* Update the driver's counters. */ 4329 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4330 4331 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 4332 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __FUNCTION__, tx_prod, 4333 tx_chain_prod, sc->tx_prod_bseq); 4334 4335 /* Start the transmit. */ 4336 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4337 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4338 4339 /* Set the tx timeout. */ 4340 ifp->if_timer = BNX_TX_TIMEOUT; 4341 4342 bnx_start_exit: 4343 return; 4344 } 4345 4346 /****************************************************************************/ 4347 /* Handles any IOCTL calls from the operating system. */ 4348 /* */ 4349 /* Returns: */ 4350 /* 0 for success, positive value for failure. */ 4351 /****************************************************************************/ 4352 int 4353 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 4354 { 4355 struct bnx_softc *sc = ifp->if_softc; 4356 struct ifreq *ifr = (struct ifreq *) data; 4357 struct mii_data *mii; 4358 int s, error = 0; 4359 4360 s = splnet(); 4361 4362 switch (command) { 4363 case SIOCSIFFLAGS: 4364 if (ifp->if_flags & IFF_UP) { 4365 if ((ifp->if_flags & IFF_RUNNING) && 4366 ((ifp->if_flags ^ sc->bnx_if_flags) & 4367 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 4368 bnx_set_rx_mode(sc); 4369 } else if (!(ifp->if_flags & IFF_RUNNING)) 4370 bnx_init(ifp); 4371 4372 } else if (ifp->if_flags & IFF_RUNNING) 4373 bnx_stop(sc); 4374 4375 sc->bnx_if_flags = ifp->if_flags; 4376 break; 4377 4378 case SIOCSIFMEDIA: 4379 case SIOCGIFMEDIA: 4380 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 4381 sc->bnx_phy_flags); 4382 4383 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 4384 error = ifmedia_ioctl(ifp, ifr, 4385 &sc->bnx_ifmedia, command); 4386 else { 4387 mii = &sc->bnx_mii; 4388 error = ifmedia_ioctl(ifp, ifr, 4389 &mii->mii_media, command); 4390 } 4391 break; 4392 4393 default: 4394 error = ether_ioctl(ifp, command, data); 4395 if (error == ENETRESET) { 4396 #if 0 4397 if (ifp->if_flags & IFF_RUNNING) 4398 /*bnx_setmulti(sc)*/; 4399 #endif 4400 error = 0; 4401 } 4402 break; 4403 } 4404 4405 splx(s); 4406 4407 return (error); 4408 } 4409 4410 /****************************************************************************/ 4411 /* Transmit timeout handler. */ 4412 /* */ 4413 /* Returns: */ 4414 /* Nothing. */ 4415 /****************************************************************************/ 4416 void 4417 bnx_watchdog(struct ifnet *ifp) 4418 { 4419 struct bnx_softc *sc = ifp->if_softc; 4420 4421 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 4422 bnx_dump_status_block(sc)); 4423 4424 aprint_error("%s: Watchdog timeout -- resetting!\n", 4425 sc->bnx_dev.dv_xname); 4426 4427 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 4428 4429 bnx_init(ifp); 4430 4431 ifp->if_oerrors++; 4432 } 4433 4434 /* 4435 * Interrupt handler. 4436 */ 4437 /****************************************************************************/ 4438 /* Main interrupt entry point. Verifies that the controller generated the */ 4439 /* interrupt and then calls a separate routine for handle the various */ 4440 /* interrupt causes (PHY, TX, RX). */ 4441 /* */ 4442 /* Returns: */ 4443 /* 0 for success, positive value for failure. */ 4444 /****************************************************************************/ 4445 int 4446 bnx_intr(void *xsc) 4447 { 4448 struct bnx_softc *sc; 4449 struct ifnet *ifp; 4450 u_int32_t status_attn_bits; 4451 4452 sc = xsc; 4453 ifp = &sc->ethercom.ec_if; 4454 4455 DBRUNIF(1, sc->interrupts_generated++); 4456 4457 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4458 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4459 4460 /* 4461 * If the hardware status block index 4462 * matches the last value read by the 4463 * driver and we haven't asserted our 4464 * interrupt then there's nothing to do. 4465 */ 4466 if ((sc->status_block->status_idx == sc->last_status_idx) && 4467 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 4468 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 4469 return (0); 4470 4471 /* Ack the interrupt and stop others from occuring. */ 4472 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4473 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 4474 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4475 4476 /* Keep processing data as long as there is work to do. */ 4477 for (;;) { 4478 status_attn_bits = sc->status_block->status_attn_bits; 4479 4480 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 4481 aprint_debug("Simulating unexpected status attention bit set."); 4482 status_attn_bits = status_attn_bits | 4483 STATUS_ATTN_BITS_PARITY_ERROR); 4484 4485 /* Was it a link change interrupt? */ 4486 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 4487 (sc->status_block->status_attn_bits_ack & 4488 STATUS_ATTN_BITS_LINK_STATE)) 4489 bnx_phy_intr(sc); 4490 4491 /* If any other attention is asserted then the chip is toast. */ 4492 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 4493 (sc->status_block->status_attn_bits_ack & 4494 ~STATUS_ATTN_BITS_LINK_STATE))) { 4495 DBRUN(1, sc->unexpected_attentions++); 4496 4497 aprint_error("%s: Fatal attention detected: 0x%08X\n", 4498 sc->bnx_dev.dv_xname, 4499 sc->status_block->status_attn_bits); 4500 4501 DBRUN(BNX_FATAL, 4502 if (bnx_debug_unexpected_attention == 0) 4503 bnx_breakpoint(sc)); 4504 4505 bnx_init(ifp); 4506 return (1); 4507 } 4508 4509 /* Check for any completed RX frames. */ 4510 if (sc->status_block->status_rx_quick_consumer_index0 != 4511 sc->hw_rx_cons) 4512 bnx_rx_intr(sc); 4513 4514 /* Check for any completed TX frames. */ 4515 if (sc->status_block->status_tx_quick_consumer_index0 != 4516 sc->hw_tx_cons) 4517 bnx_tx_intr(sc); 4518 4519 /* Save the status block index value for use during the 4520 * next interrupt. 4521 */ 4522 sc->last_status_idx = sc->status_block->status_idx; 4523 4524 /* Prevent speculative reads from getting ahead of the 4525 * status block. 4526 */ 4527 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4528 BUS_SPACE_BARRIER_READ); 4529 4530 /* If there's no work left then exit the isr. */ 4531 if ((sc->status_block->status_rx_quick_consumer_index0 == 4532 sc->hw_rx_cons) && 4533 (sc->status_block->status_tx_quick_consumer_index0 == 4534 sc->hw_tx_cons)) 4535 break; 4536 } 4537 4538 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 4539 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 4540 4541 /* Re-enable interrupts. */ 4542 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4543 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 4544 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4545 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 4546 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4547 4548 /* Handle any frames that arrived while handling the interrupt. */ 4549 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4550 bnx_start(ifp); 4551 4552 return (1); 4553 } 4554 4555 /****************************************************************************/ 4556 /* Programs the various packet receive modes (broadcast and multicast). */ 4557 /* */ 4558 /* Returns: */ 4559 /* Nothing. */ 4560 /****************************************************************************/ 4561 void 4562 bnx_set_rx_mode(struct bnx_softc *sc) 4563 { 4564 struct ethercom *ec = &sc->ethercom; 4565 struct ifnet *ifp = &ec->ec_if; 4566 struct ether_multi *enm; 4567 struct ether_multistep step; 4568 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 4569 u_int32_t rx_mode, sort_mode; 4570 int h, i; 4571 4572 /* Initialize receive mode default settings. */ 4573 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 4574 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 4575 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 4576 4577 /* 4578 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 4579 * be enbled. 4580 */ 4581 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 4582 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 4583 4584 /* 4585 * Check for promiscuous, all multicast, or selected 4586 * multicast address filtering. 4587 */ 4588 if (ifp->if_flags & IFF_PROMISC) { 4589 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 4590 4591 /* Enable promiscuous mode. */ 4592 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 4593 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 4594 } else if (ifp->if_flags & IFF_ALLMULTI) { 4595 allmulti: 4596 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 4597 4598 /* Enable all multicast addresses. */ 4599 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4600 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4601 0xffffffff); 4602 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 4603 } else { 4604 /* Accept one or more multicast(s). */ 4605 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 4606 4607 ETHER_FIRST_MULTI(step, ec, enm); 4608 while (enm != NULL) { 4609 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 4610 ETHER_ADDR_LEN)) { 4611 ifp->if_flags |= IFF_ALLMULTI; 4612 goto allmulti; 4613 } 4614 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 4615 0xFF; 4616 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 4617 ETHER_NEXT_MULTI(step, enm); 4618 } 4619 4620 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 4621 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 4622 hashes[i]); 4623 4624 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 4625 } 4626 4627 /* Only make changes if the recive mode has actually changed. */ 4628 if (rx_mode != sc->rx_mode) { 4629 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 4630 rx_mode); 4631 4632 sc->rx_mode = rx_mode; 4633 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 4634 } 4635 4636 /* Disable and clear the exisitng sort before enabling a new sort. */ 4637 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 4638 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 4639 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 4640 } 4641 4642 /****************************************************************************/ 4643 /* Called periodically to updates statistics from the controllers */ 4644 /* statistics block. */ 4645 /* */ 4646 /* Returns: */ 4647 /* Nothing. */ 4648 /****************************************************************************/ 4649 void 4650 bnx_stats_update(struct bnx_softc *sc) 4651 { 4652 struct ifnet *ifp = &sc->ethercom.ec_if; 4653 struct statistics_block *stats; 4654 4655 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 4656 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4657 BUS_DMASYNC_POSTREAD); 4658 4659 stats = (struct statistics_block *)sc->stats_block; 4660 4661 /* 4662 * Update the interface statistics from the 4663 * hardware statistics. 4664 */ 4665 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 4666 4667 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 4668 (u_long)stats->stat_EtherStatsOverrsizePkts + 4669 (u_long)stats->stat_IfInMBUFDiscards + 4670 (u_long)stats->stat_Dot3StatsAlignmentErrors + 4671 (u_long)stats->stat_Dot3StatsFCSErrors; 4672 4673 ifp->if_oerrors = (u_long) 4674 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 4675 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 4676 (u_long)stats->stat_Dot3StatsLateCollisions; 4677 4678 /* 4679 * Certain controllers don't report 4680 * carrier sense errors correctly. 4681 * See errata E11_5708CA0_1165. 4682 */ 4683 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 4684 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 4685 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 4686 4687 /* 4688 * Update the sysctl statistics from the 4689 * hardware statistics. 4690 */ 4691 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 4692 (u_int64_t) stats->stat_IfHCInOctets_lo; 4693 4694 sc->stat_IfHCInBadOctets = 4695 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 4696 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 4697 4698 sc->stat_IfHCOutOctets = 4699 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 4700 (u_int64_t) stats->stat_IfHCOutOctets_lo; 4701 4702 sc->stat_IfHCOutBadOctets = 4703 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 4704 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 4705 4706 sc->stat_IfHCInUcastPkts = 4707 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 4708 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 4709 4710 sc->stat_IfHCInMulticastPkts = 4711 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 4712 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 4713 4714 sc->stat_IfHCInBroadcastPkts = 4715 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 4716 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 4717 4718 sc->stat_IfHCOutUcastPkts = 4719 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 4720 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 4721 4722 sc->stat_IfHCOutMulticastPkts = 4723 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 4724 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 4725 4726 sc->stat_IfHCOutBroadcastPkts = 4727 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 4728 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 4729 4730 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 4731 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4732 4733 sc->stat_Dot3StatsCarrierSenseErrors = 4734 stats->stat_Dot3StatsCarrierSenseErrors; 4735 4736 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 4737 4738 sc->stat_Dot3StatsAlignmentErrors = 4739 stats->stat_Dot3StatsAlignmentErrors; 4740 4741 sc->stat_Dot3StatsSingleCollisionFrames = 4742 stats->stat_Dot3StatsSingleCollisionFrames; 4743 4744 sc->stat_Dot3StatsMultipleCollisionFrames = 4745 stats->stat_Dot3StatsMultipleCollisionFrames; 4746 4747 sc->stat_Dot3StatsDeferredTransmissions = 4748 stats->stat_Dot3StatsDeferredTransmissions; 4749 4750 sc->stat_Dot3StatsExcessiveCollisions = 4751 stats->stat_Dot3StatsExcessiveCollisions; 4752 4753 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 4754 4755 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 4756 4757 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 4758 4759 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 4760 4761 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 4762 4763 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 4764 4765 sc->stat_EtherStatsPktsRx64Octets = 4766 stats->stat_EtherStatsPktsRx64Octets; 4767 4768 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 4769 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 4770 4771 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 4772 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 4773 4774 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 4775 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 4776 4777 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 4778 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 4779 4780 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 4781 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 4782 4783 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 4784 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 4785 4786 sc->stat_EtherStatsPktsTx64Octets = 4787 stats->stat_EtherStatsPktsTx64Octets; 4788 4789 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 4790 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 4791 4792 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 4793 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 4794 4795 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 4796 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 4797 4798 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 4799 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 4800 4801 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 4802 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 4803 4804 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 4805 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 4806 4807 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 4808 4809 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 4810 4811 sc->stat_OutXonSent = stats->stat_OutXonSent; 4812 4813 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 4814 4815 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 4816 4817 sc->stat_MacControlFramesReceived = 4818 stats->stat_MacControlFramesReceived; 4819 4820 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 4821 4822 sc->stat_IfInFramesL2FilterDiscards = 4823 stats->stat_IfInFramesL2FilterDiscards; 4824 4825 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 4826 4827 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 4828 4829 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 4830 4831 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 4832 4833 sc->stat_CatchupInRuleCheckerDiscards = 4834 stats->stat_CatchupInRuleCheckerDiscards; 4835 4836 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 4837 4838 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 4839 4840 sc->stat_CatchupInRuleCheckerP4Hit = 4841 stats->stat_CatchupInRuleCheckerP4Hit; 4842 4843 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 4844 } 4845 4846 void 4847 bnx_tick(void *xsc) 4848 { 4849 struct bnx_softc *sc = xsc; 4850 struct ifnet *ifp = &sc->ethercom.ec_if; 4851 struct mii_data *mii = NULL; 4852 u_int32_t msg; 4853 int s = splnet(); 4854 4855 /* Tell the firmware that the driver is still running. */ 4856 #ifdef BNX_DEBUG 4857 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 4858 #else 4859 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 4860 #endif 4861 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 4862 4863 /* Update the statistics from the hardware statistics block. */ 4864 bnx_stats_update(sc); 4865 4866 /* Schedule the next tick. */ 4867 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4868 4869 /* If link is up already up then we're done. */ 4870 if (sc->bnx_link) 4871 goto bnx_tick_exit; 4872 4873 /* DRC - ToDo: Add SerDes support and check SerDes link here. */ 4874 4875 mii = &sc->bnx_mii; 4876 mii_tick(mii); 4877 4878 /* Check if the link has come up. */ 4879 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 4880 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4881 sc->bnx_link++; 4882 /* Now that link is up, handle any outstanding TX traffic. */ 4883 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4884 bnx_start(ifp); 4885 } 4886 4887 bnx_tick_exit: 4888 splx(s); 4889 return; 4890 } 4891 4892 /****************************************************************************/ 4893 /* BNX Debug Routines */ 4894 /****************************************************************************/ 4895 #ifdef BNX_DEBUG 4896 4897 /****************************************************************************/ 4898 /* Prints out information about an mbuf. */ 4899 /* */ 4900 /* Returns: */ 4901 /* Nothing. */ 4902 /****************************************************************************/ 4903 void 4904 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 4905 { 4906 struct mbuf *mp = m; 4907 4908 if (m == NULL) { 4909 /* Index out of range. */ 4910 aprint_error("mbuf ptr is null!\n"); 4911 return; 4912 } 4913 4914 while (mp) { 4915 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 4916 mp, mp->m_len); 4917 4918 if (mp->m_flags & M_EXT) 4919 aprint_debug("M_EXT "); 4920 if (mp->m_flags & M_PKTHDR) 4921 aprint_debug("M_PKTHDR "); 4922 aprint_debug("\n"); 4923 4924 if (mp->m_flags & M_EXT) 4925 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 4926 mp, mp->m_ext.ext_size); 4927 4928 mp = mp->m_next; 4929 } 4930 } 4931 4932 /****************************************************************************/ 4933 /* Prints out the mbufs in the TX mbuf chain. */ 4934 /* */ 4935 /* Returns: */ 4936 /* Nothing. */ 4937 /****************************************************************************/ 4938 void 4939 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4940 { 4941 struct mbuf *m; 4942 int i; 4943 4944 BNX_PRINTF(sc, 4945 "----------------------------" 4946 " tx mbuf data " 4947 "----------------------------\n"); 4948 4949 for (i = 0; i < count; i++) { 4950 m = sc->tx_mbuf_ptr[chain_prod]; 4951 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 4952 bnx_dump_mbuf(sc, m); 4953 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 4954 } 4955 4956 BNX_PRINTF(sc, 4957 "--------------------------------------------" 4958 "----------------------------\n"); 4959 } 4960 4961 /* 4962 * This routine prints the RX mbuf chain. 4963 */ 4964 void 4965 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 4966 { 4967 struct mbuf *m; 4968 int i; 4969 4970 BNX_PRINTF(sc, 4971 "----------------------------" 4972 " rx mbuf data " 4973 "----------------------------\n"); 4974 4975 for (i = 0; i < count; i++) { 4976 m = sc->rx_mbuf_ptr[chain_prod]; 4977 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 4978 bnx_dump_mbuf(sc, m); 4979 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 4980 } 4981 4982 4983 BNX_PRINTF(sc, 4984 "--------------------------------------------" 4985 "----------------------------\n"); 4986 } 4987 4988 void 4989 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 4990 { 4991 if (idx > MAX_TX_BD) 4992 /* Index out of range. */ 4993 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 4994 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4995 /* TX Chain page pointer. */ 4996 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 4997 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 4998 txbd->tx_bd_haddr_lo); 4999 else 5000 /* Normal tx_bd entry. */ 5001 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5002 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5003 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5004 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5005 txbd->tx_bd_flags); 5006 } 5007 5008 void 5009 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5010 { 5011 if (idx > MAX_RX_BD) 5012 /* Index out of range. */ 5013 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5014 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5015 /* TX Chain page pointer. */ 5016 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5017 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5018 rxbd->rx_bd_haddr_lo); 5019 else 5020 /* Normal tx_bd entry. */ 5021 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5022 "0x%08X, flags = 0x%08X\n", idx, 5023 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5024 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5025 } 5026 5027 void 5028 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5029 { 5030 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5031 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5032 "tcp_udp_xsum = 0x%04X\n", idx, 5033 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5034 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5035 l2fhdr->l2_fhdr_tcp_udp_xsum); 5036 } 5037 5038 /* 5039 * This routine prints the TX chain. 5040 */ 5041 void 5042 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5043 { 5044 struct tx_bd *txbd; 5045 int i; 5046 5047 /* First some info about the tx_bd chain structure. */ 5048 BNX_PRINTF(sc, 5049 "----------------------------" 5050 " tx_bd chain " 5051 "----------------------------\n"); 5052 5053 BNX_PRINTF(sc, 5054 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5055 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5056 5057 BNX_PRINTF(sc, 5058 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5059 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5060 5061 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD); 5062 5063 BNX_PRINTF(sc, "" 5064 "-----------------------------" 5065 " tx_bd data " 5066 "-----------------------------\n"); 5067 5068 /* Now print out the tx_bd's themselves. */ 5069 for (i = 0; i < count; i++) { 5070 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5071 bnx_dump_txbd(sc, tx_prod, txbd); 5072 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5073 } 5074 5075 BNX_PRINTF(sc, 5076 "-----------------------------" 5077 "--------------" 5078 "-----------------------------\n"); 5079 } 5080 5081 /* 5082 * This routine prints the RX chain. 5083 */ 5084 void 5085 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5086 { 5087 struct rx_bd *rxbd; 5088 int i; 5089 5090 /* First some info about the tx_bd chain structure. */ 5091 BNX_PRINTF(sc, 5092 "----------------------------" 5093 " rx_bd chain " 5094 "----------------------------\n"); 5095 5096 BNX_PRINTF(sc, "----- RX_BD Chain -----\n"); 5097 5098 BNX_PRINTF(sc, 5099 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5100 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5101 5102 BNX_PRINTF(sc, 5103 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5104 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5105 5106 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD); 5107 5108 BNX_PRINTF(sc, 5109 "----------------------------" 5110 " rx_bd data " 5111 "----------------------------\n"); 5112 5113 /* Now print out the rx_bd's themselves. */ 5114 for (i = 0; i < count; i++) { 5115 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5116 bnx_dump_rxbd(sc, rx_prod, rxbd); 5117 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5118 } 5119 5120 BNX_PRINTF(sc, 5121 "----------------------------" 5122 "--------------" 5123 "----------------------------\n"); 5124 } 5125 5126 /* 5127 * This routine prints the status block. 5128 */ 5129 void 5130 bnx_dump_status_block(struct bnx_softc *sc) 5131 { 5132 struct status_block *sblk; 5133 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5134 BUS_DMASYNC_POSTREAD); 5135 5136 sblk = sc->status_block; 5137 5138 BNX_PRINTF(sc, "----------------------------- Status Block " 5139 "-----------------------------\n"); 5140 5141 BNX_PRINTF(sc, 5142 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5143 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5144 sblk->status_idx); 5145 5146 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5147 sblk->status_rx_quick_consumer_index0, 5148 sblk->status_tx_quick_consumer_index0); 5149 5150 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5151 5152 /* Theses indices are not used for normal L2 drivers. */ 5153 if (sblk->status_rx_quick_consumer_index1 || 5154 sblk->status_tx_quick_consumer_index1) 5155 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5156 sblk->status_rx_quick_consumer_index1, 5157 sblk->status_tx_quick_consumer_index1); 5158 5159 if (sblk->status_rx_quick_consumer_index2 || 5160 sblk->status_tx_quick_consumer_index2) 5161 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5162 sblk->status_rx_quick_consumer_index2, 5163 sblk->status_tx_quick_consumer_index2); 5164 5165 if (sblk->status_rx_quick_consumer_index3 || 5166 sblk->status_tx_quick_consumer_index3) 5167 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5168 sblk->status_rx_quick_consumer_index3, 5169 sblk->status_tx_quick_consumer_index3); 5170 5171 if (sblk->status_rx_quick_consumer_index4 || 5172 sblk->status_rx_quick_consumer_index5) 5173 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5174 sblk->status_rx_quick_consumer_index4, 5175 sblk->status_rx_quick_consumer_index5); 5176 5177 if (sblk->status_rx_quick_consumer_index6 || 5178 sblk->status_rx_quick_consumer_index7) 5179 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5180 sblk->status_rx_quick_consumer_index6, 5181 sblk->status_rx_quick_consumer_index7); 5182 5183 if (sblk->status_rx_quick_consumer_index8 || 5184 sblk->status_rx_quick_consumer_index9) 5185 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5186 sblk->status_rx_quick_consumer_index8, 5187 sblk->status_rx_quick_consumer_index9); 5188 5189 if (sblk->status_rx_quick_consumer_index10 || 5190 sblk->status_rx_quick_consumer_index11) 5191 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5192 sblk->status_rx_quick_consumer_index10, 5193 sblk->status_rx_quick_consumer_index11); 5194 5195 if (sblk->status_rx_quick_consumer_index12 || 5196 sblk->status_rx_quick_consumer_index13) 5197 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5198 sblk->status_rx_quick_consumer_index12, 5199 sblk->status_rx_quick_consumer_index13); 5200 5201 if (sblk->status_rx_quick_consumer_index14 || 5202 sblk->status_rx_quick_consumer_index15) 5203 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5204 sblk->status_rx_quick_consumer_index14, 5205 sblk->status_rx_quick_consumer_index15); 5206 5207 if (sblk->status_completion_producer_index || 5208 sblk->status_cmd_consumer_index) 5209 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5210 sblk->status_completion_producer_index, 5211 sblk->status_cmd_consumer_index); 5212 5213 BNX_PRINTF(sc, "-------------------------------------------" 5214 "-----------------------------\n"); 5215 } 5216 5217 /* 5218 * This routine prints the statistics block. 5219 */ 5220 void 5221 bnx_dump_stats_block(struct bnx_softc *sc) 5222 { 5223 struct statistics_block *sblk; 5224 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5225 BUS_DMASYNC_POSTREAD); 5226 5227 sblk = sc->stats_block; 5228 5229 BNX_PRINTF(sc, "" 5230 "-----------------------------" 5231 " Stats Block " 5232 "-----------------------------\n"); 5233 5234 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5235 "IfHcInBadOctets = 0x%08X:%08X\n", 5236 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5237 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5238 5239 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5240 "IfHcOutBadOctets = 0x%08X:%08X\n", 5241 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5242 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5243 5244 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5245 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5246 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5247 sblk->stat_IfHCInMulticastPkts_hi, 5248 sblk->stat_IfHCInMulticastPkts_lo); 5249 5250 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5251 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5252 sblk->stat_IfHCInBroadcastPkts_hi, 5253 sblk->stat_IfHCInBroadcastPkts_lo, 5254 sblk->stat_IfHCOutUcastPkts_hi, 5255 sblk->stat_IfHCOutUcastPkts_lo); 5256 5257 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5258 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5259 sblk->stat_IfHCOutMulticastPkts_hi, 5260 sblk->stat_IfHCOutMulticastPkts_lo, 5261 sblk->stat_IfHCOutBroadcastPkts_hi, 5262 sblk->stat_IfHCOutBroadcastPkts_lo); 5263 5264 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5265 BNX_PRINTF(sc, "0x%08X : " 5266 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 5267 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 5268 5269 if (sblk->stat_Dot3StatsCarrierSenseErrors) 5270 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 5271 sblk->stat_Dot3StatsCarrierSenseErrors); 5272 5273 if (sblk->stat_Dot3StatsFCSErrors) 5274 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 5275 sblk->stat_Dot3StatsFCSErrors); 5276 5277 if (sblk->stat_Dot3StatsAlignmentErrors) 5278 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 5279 sblk->stat_Dot3StatsAlignmentErrors); 5280 5281 if (sblk->stat_Dot3StatsSingleCollisionFrames) 5282 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 5283 sblk->stat_Dot3StatsSingleCollisionFrames); 5284 5285 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 5286 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 5287 sblk->stat_Dot3StatsMultipleCollisionFrames); 5288 5289 if (sblk->stat_Dot3StatsDeferredTransmissions) 5290 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 5291 sblk->stat_Dot3StatsDeferredTransmissions); 5292 5293 if (sblk->stat_Dot3StatsExcessiveCollisions) 5294 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 5295 sblk->stat_Dot3StatsExcessiveCollisions); 5296 5297 if (sblk->stat_Dot3StatsLateCollisions) 5298 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 5299 sblk->stat_Dot3StatsLateCollisions); 5300 5301 if (sblk->stat_EtherStatsCollisions) 5302 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 5303 sblk->stat_EtherStatsCollisions); 5304 5305 if (sblk->stat_EtherStatsFragments) 5306 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 5307 sblk->stat_EtherStatsFragments); 5308 5309 if (sblk->stat_EtherStatsJabbers) 5310 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 5311 sblk->stat_EtherStatsJabbers); 5312 5313 if (sblk->stat_EtherStatsUndersizePkts) 5314 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 5315 sblk->stat_EtherStatsUndersizePkts); 5316 5317 if (sblk->stat_EtherStatsOverrsizePkts) 5318 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 5319 sblk->stat_EtherStatsOverrsizePkts); 5320 5321 if (sblk->stat_EtherStatsPktsRx64Octets) 5322 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 5323 sblk->stat_EtherStatsPktsRx64Octets); 5324 5325 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 5326 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 5327 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 5328 5329 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 5330 BNX_PRINTF(sc, "0x%08X : " 5331 "EtherStatsPktsRx128Octetsto255Octets\n", 5332 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 5333 5334 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 5335 BNX_PRINTF(sc, "0x%08X : " 5336 "EtherStatsPktsRx256Octetsto511Octets\n", 5337 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 5338 5339 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 5340 BNX_PRINTF(sc, "0x%08X : " 5341 "EtherStatsPktsRx512Octetsto1023Octets\n", 5342 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 5343 5344 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 5345 BNX_PRINTF(sc, "0x%08X : " 5346 "EtherStatsPktsRx1024Octetsto1522Octets\n", 5347 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 5348 5349 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 5350 BNX_PRINTF(sc, "0x%08X : " 5351 "EtherStatsPktsRx1523Octetsto9022Octets\n", 5352 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 5353 5354 if (sblk->stat_EtherStatsPktsTx64Octets) 5355 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 5356 sblk->stat_EtherStatsPktsTx64Octets); 5357 5358 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 5359 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 5360 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 5361 5362 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 5363 BNX_PRINTF(sc, "0x%08X : " 5364 "EtherStatsPktsTx128Octetsto255Octets\n", 5365 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 5366 5367 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 5368 BNX_PRINTF(sc, "0x%08X : " 5369 "EtherStatsPktsTx256Octetsto511Octets\n", 5370 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 5371 5372 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 5373 BNX_PRINTF(sc, "0x%08X : " 5374 "EtherStatsPktsTx512Octetsto1023Octets\n", 5375 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 5376 5377 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 5378 BNX_PRINTF(sc, "0x%08X : " 5379 "EtherStatsPktsTx1024Octetsto1522Octets\n", 5380 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 5381 5382 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 5383 BNX_PRINTF(sc, "0x%08X : " 5384 "EtherStatsPktsTx1523Octetsto9022Octets\n", 5385 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 5386 5387 if (sblk->stat_XonPauseFramesReceived) 5388 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 5389 sblk->stat_XonPauseFramesReceived); 5390 5391 if (sblk->stat_XoffPauseFramesReceived) 5392 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 5393 sblk->stat_XoffPauseFramesReceived); 5394 5395 if (sblk->stat_OutXonSent) 5396 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 5397 sblk->stat_OutXonSent); 5398 5399 if (sblk->stat_OutXoffSent) 5400 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 5401 sblk->stat_OutXoffSent); 5402 5403 if (sblk->stat_FlowControlDone) 5404 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 5405 sblk->stat_FlowControlDone); 5406 5407 if (sblk->stat_MacControlFramesReceived) 5408 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 5409 sblk->stat_MacControlFramesReceived); 5410 5411 if (sblk->stat_XoffStateEntered) 5412 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 5413 sblk->stat_XoffStateEntered); 5414 5415 if (sblk->stat_IfInFramesL2FilterDiscards) 5416 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 5417 sblk->stat_IfInFramesL2FilterDiscards); 5418 5419 if (sblk->stat_IfInRuleCheckerDiscards) 5420 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 5421 sblk->stat_IfInRuleCheckerDiscards); 5422 5423 if (sblk->stat_IfInFTQDiscards) 5424 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 5425 sblk->stat_IfInFTQDiscards); 5426 5427 if (sblk->stat_IfInMBUFDiscards) 5428 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 5429 sblk->stat_IfInMBUFDiscards); 5430 5431 if (sblk->stat_IfInRuleCheckerP4Hit) 5432 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 5433 sblk->stat_IfInRuleCheckerP4Hit); 5434 5435 if (sblk->stat_CatchupInRuleCheckerDiscards) 5436 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 5437 sblk->stat_CatchupInRuleCheckerDiscards); 5438 5439 if (sblk->stat_CatchupInFTQDiscards) 5440 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 5441 sblk->stat_CatchupInFTQDiscards); 5442 5443 if (sblk->stat_CatchupInMBUFDiscards) 5444 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 5445 sblk->stat_CatchupInMBUFDiscards); 5446 5447 if (sblk->stat_CatchupInRuleCheckerP4Hit) 5448 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 5449 sblk->stat_CatchupInRuleCheckerP4Hit); 5450 5451 BNX_PRINTF(sc, 5452 "-----------------------------" 5453 "--------------" 5454 "-----------------------------\n"); 5455 } 5456 5457 void 5458 bnx_dump_driver_state(struct bnx_softc *sc) 5459 { 5460 BNX_PRINTF(sc, 5461 "-----------------------------" 5462 " Driver State " 5463 "-----------------------------\n"); 5464 5465 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 5466 "address\n", sc); 5467 5468 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 5469 sc->status_block); 5470 5471 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 5472 "address\n", sc->stats_block); 5473 5474 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 5475 "adddress\n", sc->tx_bd_chain); 5476 5477 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 5478 sc->rx_bd_chain); 5479 5480 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 5481 sc->tx_mbuf_ptr); 5482 5483 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 5484 sc->rx_mbuf_ptr); 5485 5486 BNX_PRINTF(sc, 5487 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 5488 sc->interrupts_generated); 5489 5490 BNX_PRINTF(sc, 5491 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 5492 sc->rx_interrupts); 5493 5494 BNX_PRINTF(sc, 5495 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 5496 sc->tx_interrupts); 5497 5498 BNX_PRINTF(sc, 5499 " 0x%08X - (sc->last_status_idx) status block index\n", 5500 sc->last_status_idx); 5501 5502 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 5503 sc->tx_prod); 5504 5505 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 5506 sc->tx_cons); 5507 5508 BNX_PRINTF(sc, 5509 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 5510 sc->tx_prod_bseq); 5511 5512 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 5513 sc->rx_prod); 5514 5515 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 5516 sc->rx_cons); 5517 5518 BNX_PRINTF(sc, 5519 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 5520 sc->rx_prod_bseq); 5521 5522 BNX_PRINTF(sc, 5523 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5524 sc->rx_mbuf_alloc); 5525 5526 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 5527 sc->free_rx_bd); 5528 5529 BNX_PRINTF(sc, 5530 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 5531 sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD); 5532 5533 BNX_PRINTF(sc, 5534 " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 5535 sc->tx_mbuf_alloc); 5536 5537 BNX_PRINTF(sc, 5538 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 5539 sc->rx_mbuf_alloc); 5540 5541 BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 5542 sc->used_tx_bd); 5543 5544 BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 5545 sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD); 5546 5547 BNX_PRINTF(sc, 5548 " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 5549 sc->mbuf_alloc_failed); 5550 5551 BNX_PRINTF(sc, "-------------------------------------------" 5552 "-----------------------------\n"); 5553 } 5554 5555 void 5556 bnx_dump_hw_state(struct bnx_softc *sc) 5557 { 5558 u_int32_t val1; 5559 int i; 5560 5561 BNX_PRINTF(sc, 5562 "----------------------------" 5563 " Hardware State " 5564 "----------------------------\n"); 5565 5566 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 5567 5568 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 5569 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 5570 val1, BNX_MISC_ENABLE_STATUS_BITS); 5571 5572 val1 = REG_RD(sc, BNX_DMA_STATUS); 5573 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 5574 5575 val1 = REG_RD(sc, BNX_CTX_STATUS); 5576 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 5577 5578 val1 = REG_RD(sc, BNX_EMAC_STATUS); 5579 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 5580 BNX_EMAC_STATUS); 5581 5582 val1 = REG_RD(sc, BNX_RPM_STATUS); 5583 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 5584 5585 val1 = REG_RD(sc, BNX_TBDR_STATUS); 5586 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 5587 BNX_TBDR_STATUS); 5588 5589 val1 = REG_RD(sc, BNX_TDMA_STATUS); 5590 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 5591 BNX_TDMA_STATUS); 5592 5593 val1 = REG_RD(sc, BNX_HC_STATUS); 5594 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 5595 5596 BNX_PRINTF(sc, 5597 "----------------------------" 5598 "----------------" 5599 "----------------------------\n"); 5600 5601 BNX_PRINTF(sc, 5602 "----------------------------" 5603 " Register Dump " 5604 "----------------------------\n"); 5605 5606 for (i = 0x400; i < 0x8000; i += 0x10) 5607 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 5608 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 5609 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 5610 5611 BNX_PRINTF(sc, 5612 "----------------------------" 5613 "----------------" 5614 "----------------------------\n"); 5615 } 5616 5617 void 5618 bnx_breakpoint(struct bnx_softc *sc) 5619 { 5620 /* Unreachable code to shut the compiler up about unused functions. */ 5621 if (0) { 5622 bnx_dump_txbd(sc, 0, NULL); 5623 bnx_dump_rxbd(sc, 0, NULL); 5624 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 5625 bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 5626 bnx_dump_l2fhdr(sc, 0, NULL); 5627 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 5628 bnx_dump_rx_chain(sc, 0, USABLE_RX_BD); 5629 bnx_dump_status_block(sc); 5630 bnx_dump_stats_block(sc); 5631 bnx_dump_driver_state(sc); 5632 bnx_dump_hw_state(sc); 5633 } 5634 5635 bnx_dump_driver_state(sc); 5636 /* Print the important status block fields. */ 5637 bnx_dump_status_block(sc); 5638 5639 #if 0 5640 /* Call the debugger. */ 5641 breakpoint(); 5642 #endif 5643 5644 return; 5645 } 5646 #endif 5647
Indexes created Mon Sep 22 13:09:51 GMT 2025