if_bnx.c revision 1.49
1 /* $NetBSD: if_bnx.c,v 1.49 2013/09/13 20:54:14 martin Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.49 2013/09/13 20:54:14 martin Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * 52 * BCM5706C A0, A1 53 * BCM5706S A0, A1 54 * BCM5708C A0, B0 55 * BCM5708S A0, B0 56 * BCM5709C A0 B0, B1, B2 (pre-production) 57 * BCM5709S A0, B0, B1, B2 (pre-production) 58 */ 59 60 #include <sys/callout.h> 61 #include <sys/mutex.h> 62 63 #include <dev/pci/if_bnxreg.h> 64 #include <dev/pci/if_bnxvar.h> 65 66 #include <dev/microcode/bnx/bnxfw.h> 67 68 /****************************************************************************/ 69 /* BNX Driver Version */ 70 /****************************************************************************/ 71 #define BNX_DRIVER_VERSION "v0.9.6" 72 73 /****************************************************************************/ 74 /* BNX Debug Options */ 75 /****************************************************************************/ 76 #ifdef BNX_DEBUG 77 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 78 79 /* 0 = Never */ 80 /* 1 = 1 in 2,147,483,648 */ 81 /* 256 = 1 in 8,388,608 */ 82 /* 2048 = 1 in 1,048,576 */ 83 /* 65536 = 1 in 32,768 */ 84 /* 1048576 = 1 in 2,048 */ 85 /* 268435456 = 1 in 8 */ 86 /* 536870912 = 1 in 4 */ 87 /* 1073741824 = 1 in 2 */ 88 89 /* Controls how often the l2_fhdr frame error check will fail. */ 90 int bnx_debug_l2fhdr_status_check = 0; 91 92 /* Controls how often the unexpected attention check will fail. */ 93 int bnx_debug_unexpected_attention = 0; 94 95 /* Controls how often to simulate an mbuf allocation failure. */ 96 int bnx_debug_mbuf_allocation_failure = 0; 97 98 /* Controls how often to simulate a DMA mapping failure. */ 99 int bnx_debug_dma_map_addr_failure = 0; 100 101 /* Controls how often to simulate a bootcode failure. */ 102 int bnx_debug_bootcode_running_failure = 0; 103 #endif 104 105 /****************************************************************************/ 106 /* PCI Device ID Table */ 107 /* */ 108 /* Used by bnx_probe() to identify the devices supported by this driver. */ 109 /****************************************************************************/ 110 static const struct bnx_product { 111 pci_vendor_id_t bp_vendor; 112 pci_product_id_t bp_product; 113 pci_vendor_id_t bp_subvendor; 114 pci_product_id_t bp_subproduct; 115 const char *bp_name; 116 } bnx_devices[] = { 117 #ifdef PCI_SUBPRODUCT_HP_NC370T 118 { 119 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 120 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 121 "HP NC370T Multifunction Gigabit Server Adapter" 122 }, 123 #endif 124 #ifdef PCI_SUBPRODUCT_HP_NC370i 125 { 126 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 127 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 128 "HP NC370i Multifunction Gigabit Server Adapter" 129 }, 130 #endif 131 { 132 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 133 0, 0, 134 "Broadcom NetXtreme II BCM5706 1000Base-T" 135 }, 136 #ifdef PCI_SUBPRODUCT_HP_NC370F 137 { 138 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 139 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 140 "HP NC370F Multifunction Gigabit Server Adapter" 141 }, 142 #endif 143 { 144 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 145 0, 0, 146 "Broadcom NetXtreme II BCM5706 1000Base-SX" 147 }, 148 { 149 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 150 0, 0, 151 "Broadcom NetXtreme II BCM5708 1000Base-T" 152 }, 153 { 154 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 155 0, 0, 156 "Broadcom NetXtreme II BCM5708 1000Base-SX" 157 }, 158 { 159 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 160 0, 0, 161 "Broadcom NetXtreme II BCM5709 1000Base-T" 162 }, 163 { 164 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 165 0, 0, 166 "Broadcom NetXtreme II BCM5709 1000Base-SX" 167 }, 168 { 169 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 170 0, 0, 171 "Broadcom NetXtreme II BCM5716 1000Base-T" 172 }, 173 { 174 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 175 0, 0, 176 "Broadcom NetXtreme II BCM5716 1000Base-SX" 177 }, 178 }; 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 /* Slow EEPROM */ 188 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 189 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 190 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 191 "EEPROM - slow"}, 192 /* Expansion entry 0001 */ 193 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 195 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 196 "Entry 0001"}, 197 /* Saifun SA25F010 (non-buffered flash) */ 198 /* strap, cfg1, & write1 need updates */ 199 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 200 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 201 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 202 "Non-buffered flash (128kB)"}, 203 /* Saifun SA25F020 (non-buffered flash) */ 204 /* strap, cfg1, & write1 need updates */ 205 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 206 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 208 "Non-buffered flash (256kB)"}, 209 /* Expansion entry 0100 */ 210 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 211 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 0100"}, 214 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 215 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 216 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 217 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 218 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 219 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 220 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 221 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 222 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 223 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 224 /* Saifun SA25F005 (non-buffered flash) */ 225 /* strap, cfg1, & write1 need updates */ 226 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 227 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 228 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 229 "Non-buffered flash (64kB)"}, 230 /* Fast EEPROM */ 231 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 232 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 233 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 234 "EEPROM - fast"}, 235 /* Expansion entry 1001 */ 236 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 239 "Entry 1001"}, 240 /* Expansion entry 1010 */ 241 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 242 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 243 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 244 "Entry 1010"}, 245 /* ATMEL AT45DB011B (buffered flash) */ 246 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 247 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 248 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 249 "Buffered flash (128kB)"}, 250 /* Expansion entry 1100 */ 251 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 252 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 253 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 254 "Entry 1100"}, 255 /* Expansion entry 1101 */ 256 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 257 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 258 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 259 "Entry 1101"}, 260 /* Ateml Expansion entry 1110 */ 261 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 262 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 263 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 264 "Entry 1110 (Atmel)"}, 265 /* ATMEL AT45DB021B (buffered flash) */ 266 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 267 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 268 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 269 "Buffered flash (256kB)"}, 270 }; 271 272 /* 273 * The BCM5709 controllers transparently handle the 274 * differences between Atmel 264 byte pages and all 275 * flash devices which use 256 byte pages, so no 276 * logical-to-physical mapping is required in the 277 * driver. 278 */ 279 static struct flash_spec flash_5709 = { 280 .flags = BNX_NV_BUFFERED, 281 .page_bits = BCM5709_FLASH_PAGE_BITS, 282 .page_size = BCM5709_FLASH_PAGE_SIZE, 283 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 284 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 285 .name = "5709 buffered flash (256kB)", 286 }; 287 288 /****************************************************************************/ 289 /* OpenBSD device entry points. */ 290 /****************************************************************************/ 291 static int bnx_probe(device_t, cfdata_t, void *); 292 void bnx_attach(device_t, device_t, void *); 293 int bnx_detach(device_t, int); 294 295 /****************************************************************************/ 296 /* BNX Debug Data Structure Dump Routines */ 297 /****************************************************************************/ 298 #ifdef BNX_DEBUG 299 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 300 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 303 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 304 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 305 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_status_block(struct bnx_softc *); 308 void bnx_dump_stats_block(struct bnx_softc *); 309 void bnx_dump_driver_state(struct bnx_softc *); 310 void bnx_dump_hw_state(struct bnx_softc *); 311 void bnx_breakpoint(struct bnx_softc *); 312 #endif 313 314 /****************************************************************************/ 315 /* BNX Register/Memory Access Routines */ 316 /****************************************************************************/ 317 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 318 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 319 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 320 int bnx_miibus_read_reg(device_t, int, int); 321 void bnx_miibus_write_reg(device_t, int, int, int); 322 void bnx_miibus_statchg(struct ifnet *); 323 324 /****************************************************************************/ 325 /* BNX NVRAM Access Routines */ 326 /****************************************************************************/ 327 int bnx_acquire_nvram_lock(struct bnx_softc *); 328 int bnx_release_nvram_lock(struct bnx_softc *); 329 void bnx_enable_nvram_access(struct bnx_softc *); 330 void bnx_disable_nvram_access(struct bnx_softc *); 331 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 332 u_int32_t); 333 int bnx_init_nvram(struct bnx_softc *); 334 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 335 int bnx_nvram_test(struct bnx_softc *); 336 #ifdef BNX_NVRAM_WRITE_SUPPORT 337 int bnx_enable_nvram_write(struct bnx_softc *); 338 void bnx_disable_nvram_write(struct bnx_softc *); 339 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 340 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 341 u_int32_t); 342 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 343 #endif 344 345 /****************************************************************************/ 346 /* */ 347 /****************************************************************************/ 348 void bnx_get_media(struct bnx_softc *); 349 void bnx_init_media(struct bnx_softc *); 350 int bnx_dma_alloc(struct bnx_softc *); 351 void bnx_dma_free(struct bnx_softc *); 352 void bnx_release_resources(struct bnx_softc *); 353 354 /****************************************************************************/ 355 /* BNX Firmware Synchronization and Load */ 356 /****************************************************************************/ 357 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 358 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 359 u_int32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 void bnx_stop(struct ifnet *, int); 365 int bnx_reset(struct bnx_softc *, u_int32_t); 366 int bnx_chipinit(struct bnx_softc *); 367 int bnx_blockinit(struct bnx_softc *); 368 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 369 u_int16_t *, u_int32_t *); 370 int bnx_get_buf(struct bnx_softc *, u_int16_t *, u_int16_t *, u_int32_t *); 371 372 int bnx_init_tx_chain(struct bnx_softc *); 373 void bnx_init_tx_context(struct bnx_softc *); 374 int bnx_init_rx_chain(struct bnx_softc *); 375 void bnx_init_rx_context(struct bnx_softc *); 376 void bnx_free_rx_chain(struct bnx_softc *); 377 void bnx_free_tx_chain(struct bnx_softc *); 378 379 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 380 void bnx_start(struct ifnet *); 381 int bnx_ioctl(struct ifnet *, u_long, void *); 382 void bnx_watchdog(struct ifnet *); 383 int bnx_init(struct ifnet *); 384 385 void bnx_init_context(struct bnx_softc *); 386 void bnx_get_mac_addr(struct bnx_softc *); 387 void bnx_set_mac_addr(struct bnx_softc *); 388 void bnx_phy_intr(struct bnx_softc *); 389 void bnx_rx_intr(struct bnx_softc *); 390 void bnx_tx_intr(struct bnx_softc *); 391 void bnx_disable_intr(struct bnx_softc *); 392 void bnx_enable_intr(struct bnx_softc *); 393 394 int bnx_intr(void *); 395 void bnx_iff(struct bnx_softc *); 396 void bnx_stats_update(struct bnx_softc *); 397 void bnx_tick(void *); 398 399 struct pool *bnx_tx_pool = NULL; 400 void bnx_alloc_pkts(struct work *, void *); 401 402 /****************************************************************************/ 403 /* OpenBSD device dispatch table. */ 404 /****************************************************************************/ 405 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 406 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 407 408 /****************************************************************************/ 409 /* Device probe function. */ 410 /* */ 411 /* Compares the device to the driver's list of supported devices and */ 412 /* reports back to the OS whether this is the right driver for the device. */ 413 /* */ 414 /* Returns: */ 415 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 416 /****************************************************************************/ 417 static const struct bnx_product * 418 bnx_lookup(const struct pci_attach_args *pa) 419 { 420 int i; 421 pcireg_t subid; 422 423 for (i = 0; i < __arraycount(bnx_devices); i++) { 424 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 425 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 426 continue; 427 if (!bnx_devices[i].bp_subvendor) 428 return &bnx_devices[i]; 429 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 430 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 431 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 432 return &bnx_devices[i]; 433 } 434 435 return NULL; 436 } 437 static int 438 bnx_probe(device_t parent, cfdata_t match, void *aux) 439 { 440 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 441 442 if (bnx_lookup(pa) != NULL) 443 return (1); 444 445 return (0); 446 } 447 448 /****************************************************************************/ 449 /* Device attach function. */ 450 /* */ 451 /* Allocates device resources, performs secondary chip identification, */ 452 /* resets and initializes the hardware, and initializes driver instance */ 453 /* variables. */ 454 /* */ 455 /* Returns: */ 456 /* 0 on success, positive value on failure. */ 457 /****************************************************************************/ 458 void 459 bnx_attach(device_t parent, device_t self, void *aux) 460 { 461 const struct bnx_product *bp; 462 struct bnx_softc *sc = device_private(self); 463 prop_dictionary_t dict; 464 struct pci_attach_args *pa = aux; 465 pci_chipset_tag_t pc = pa->pa_pc; 466 pci_intr_handle_t ih; 467 const char *intrstr = NULL; 468 u_int32_t command; 469 struct ifnet *ifp; 470 u_int32_t val; 471 int mii_flags = MIIF_FORCEANEG; 472 pcireg_t memtype; 473 474 if (bnx_tx_pool == NULL) { 475 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 476 if (bnx_tx_pool != NULL) { 477 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 478 0, 0, 0, "bnxpkts", NULL, IPL_NET); 479 } else { 480 aprint_error(": can't alloc bnx_tx_pool\n"); 481 return; 482 } 483 } 484 485 bp = bnx_lookup(pa); 486 if (bp == NULL) 487 panic("unknown device"); 488 489 sc->bnx_dev = self; 490 491 aprint_naive("\n"); 492 aprint_normal(": %s\n", bp->bp_name); 493 494 sc->bnx_pa = *pa; 495 496 /* 497 * Map control/status registers. 498 */ 499 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 501 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 502 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 503 504 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 505 aprint_error_dev(sc->bnx_dev, 506 "failed to enable memory mapping!\n"); 507 return; 508 } 509 510 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 511 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 512 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 513 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 514 return; 515 } 516 517 if (pci_intr_map(pa, &ih)) { 518 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 519 goto bnx_attach_fail; 520 } 521 522 intrstr = pci_intr_string(pc, ih); 523 524 /* 525 * Configure byte swap and enable indirect register access. 526 * Rely on CPU to do target byte swapping on big endian systems. 527 * Access to registers outside of PCI configurtion space are not 528 * valid until this is done. 529 */ 530 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 531 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 532 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 533 534 /* Save ASIC revsion info. */ 535 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 536 537 /* 538 * Find the base address for shared memory access. 539 * Newer versions of bootcode use a signature and offset 540 * while older versions use a fixed address. 541 */ 542 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 543 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 544 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 545 (sc->bnx_pa.pa_function << 2)); 546 else 547 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 548 549 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 550 551 /* Set initial device and PHY flags */ 552 sc->bnx_flags = 0; 553 sc->bnx_phy_flags = 0; 554 555 /* Get PCI bus information (speed and type). */ 556 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 557 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 558 u_int32_t clkreg; 559 560 sc->bnx_flags |= BNX_PCIX_FLAG; 561 562 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 563 564 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 565 switch (clkreg) { 566 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 567 sc->bus_speed_mhz = 133; 568 break; 569 570 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 571 sc->bus_speed_mhz = 100; 572 break; 573 574 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 575 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 576 sc->bus_speed_mhz = 66; 577 break; 578 579 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 580 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 581 sc->bus_speed_mhz = 50; 582 break; 583 584 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 585 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 586 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 587 sc->bus_speed_mhz = 33; 588 break; 589 } 590 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 591 sc->bus_speed_mhz = 66; 592 else 593 sc->bus_speed_mhz = 33; 594 595 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 596 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 597 598 /* Reset the controller. */ 599 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 600 goto bnx_attach_fail; 601 602 /* Initialize the controller. */ 603 if (bnx_chipinit(sc)) { 604 aprint_error_dev(sc->bnx_dev, 605 "Controller initialization failed!\n"); 606 goto bnx_attach_fail; 607 } 608 609 /* Perform NVRAM test. */ 610 if (bnx_nvram_test(sc)) { 611 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 612 goto bnx_attach_fail; 613 } 614 615 /* Fetch the permanent Ethernet MAC address. */ 616 bnx_get_mac_addr(sc); 617 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 618 ether_sprintf(sc->eaddr)); 619 620 /* 621 * Trip points control how many BDs 622 * should be ready before generating an 623 * interrupt while ticks control how long 624 * a BD can sit in the chain before 625 * generating an interrupt. Set the default 626 * values for the RX and TX rings. 627 */ 628 629 #ifdef BNX_DEBUG 630 /* Force more frequent interrupts. */ 631 sc->bnx_tx_quick_cons_trip_int = 1; 632 sc->bnx_tx_quick_cons_trip = 1; 633 sc->bnx_tx_ticks_int = 0; 634 sc->bnx_tx_ticks = 0; 635 636 sc->bnx_rx_quick_cons_trip_int = 1; 637 sc->bnx_rx_quick_cons_trip = 1; 638 sc->bnx_rx_ticks_int = 0; 639 sc->bnx_rx_ticks = 0; 640 #else 641 sc->bnx_tx_quick_cons_trip_int = 20; 642 sc->bnx_tx_quick_cons_trip = 20; 643 sc->bnx_tx_ticks_int = 80; 644 sc->bnx_tx_ticks = 80; 645 646 sc->bnx_rx_quick_cons_trip_int = 6; 647 sc->bnx_rx_quick_cons_trip = 6; 648 sc->bnx_rx_ticks_int = 18; 649 sc->bnx_rx_ticks = 18; 650 #endif 651 652 /* Update statistics once every second. */ 653 sc->bnx_stats_ticks = 1000000 & 0xffff00; 654 655 /* Find the media type for the adapter. */ 656 bnx_get_media(sc); 657 658 /* 659 * Store config data needed by the PHY driver for 660 * backplane applications 661 */ 662 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 663 BNX_SHARED_HW_CFG_CONFIG); 664 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 665 BNX_PORT_HW_CFG_CONFIG); 666 667 /* Allocate DMA memory resources. */ 668 sc->bnx_dmatag = pa->pa_dmat; 669 if (bnx_dma_alloc(sc)) { 670 aprint_error_dev(sc->bnx_dev, 671 "DMA resource allocation failed!\n"); 672 goto bnx_attach_fail; 673 } 674 675 /* Initialize the ifnet interface. */ 676 ifp = &sc->bnx_ec.ec_if; 677 ifp->if_softc = sc; 678 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 679 ifp->if_ioctl = bnx_ioctl; 680 ifp->if_stop = bnx_stop; 681 ifp->if_start = bnx_start; 682 ifp->if_init = bnx_init; 683 ifp->if_timer = 0; 684 ifp->if_watchdog = bnx_watchdog; 685 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 686 IFQ_SET_READY(&ifp->if_snd); 687 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 688 689 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 690 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 691 692 ifp->if_capabilities |= 693 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 694 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 695 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 696 697 /* Hookup IRQ last. */ 698 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 699 if (sc->bnx_intrhand == NULL) { 700 aprint_error_dev(self, "couldn't establish interrupt"); 701 if (intrstr != NULL) 702 aprint_error(" at %s", intrstr); 703 aprint_error("\n"); 704 goto bnx_attach_fail; 705 } 706 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 707 708 /* create workqueue to handle packet allocations */ 709 if (workqueue_create(&sc->bnx_wq, device_xname(self), 710 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 711 aprint_error_dev(self, "failed to create workqueue\n"); 712 goto bnx_attach_fail; 713 } 714 715 sc->bnx_mii.mii_ifp = ifp; 716 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 717 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 718 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 719 720 /* Handle any special PHY initialization for SerDes PHYs. */ 721 bnx_init_media(sc); 722 723 sc->bnx_ec.ec_mii = &sc->bnx_mii; 724 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 725 ether_mediastatus); 726 727 /* set phyflags and chipid before mii_attach() */ 728 dict = device_properties(self); 729 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 730 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 731 732 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 733 mii_flags |= MIIF_HAVEFIBER; 734 mii_attach(self, &sc->bnx_mii, 0xffffffff, 735 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 736 737 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 738 aprint_error_dev(self, "no PHY found!\n"); 739 ifmedia_add(&sc->bnx_mii.mii_media, 740 IFM_ETHER|IFM_MANUAL, 0, NULL); 741 ifmedia_set(&sc->bnx_mii.mii_media, 742 IFM_ETHER|IFM_MANUAL); 743 } else { 744 ifmedia_set(&sc->bnx_mii.mii_media, 745 IFM_ETHER|IFM_AUTO); 746 } 747 748 /* Attach to the Ethernet interface list. */ 749 if_attach(ifp); 750 ether_ifattach(ifp,sc->eaddr); 751 752 callout_init(&sc->bnx_timeout, 0); 753 754 if (pmf_device_register(self, NULL, NULL)) 755 pmf_class_network_register(self, ifp); 756 else 757 aprint_error_dev(self, "couldn't establish power handler\n"); 758 759 /* Print some important debugging info. */ 760 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 761 762 goto bnx_attach_exit; 763 764 bnx_attach_fail: 765 bnx_release_resources(sc); 766 767 bnx_attach_exit: 768 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 769 } 770 771 /****************************************************************************/ 772 /* Device detach function. */ 773 /* */ 774 /* Stops the controller, resets the controller, and releases resources. */ 775 /* */ 776 /* Returns: */ 777 /* 0 on success, positive value on failure. */ 778 /****************************************************************************/ 779 int 780 bnx_detach(device_t dev, int flags) 781 { 782 int s; 783 struct bnx_softc *sc; 784 struct ifnet *ifp; 785 786 sc = device_private(dev); 787 ifp = &sc->bnx_ec.ec_if; 788 789 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 790 791 /* Stop and reset the controller. */ 792 s = splnet(); 793 if (ifp->if_flags & IFF_RUNNING) 794 bnx_stop(ifp, 1); 795 else { 796 /* Disable the transmit/receive blocks. */ 797 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 798 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 799 DELAY(20); 800 bnx_disable_intr(sc); 801 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 802 } 803 804 splx(s); 805 806 pmf_device_deregister(dev); 807 callout_destroy(&sc->bnx_timeout); 808 ether_ifdetach(ifp); 809 workqueue_destroy(sc->bnx_wq); 810 811 /* Delete all remaining media. */ 812 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 813 814 if_detach(ifp); 815 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 816 817 /* Release all remaining resources. */ 818 bnx_release_resources(sc); 819 820 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 821 822 return(0); 823 } 824 825 /****************************************************************************/ 826 /* Indirect register read. */ 827 /* */ 828 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 829 /* configuration space. Using this mechanism avoids issues with posted */ 830 /* reads but is much slower than memory-mapped I/O. */ 831 /* */ 832 /* Returns: */ 833 /* The value of the register. */ 834 /****************************************************************************/ 835 u_int32_t 836 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 837 { 838 struct pci_attach_args *pa = &(sc->bnx_pa); 839 840 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 841 offset); 842 #ifdef BNX_DEBUG 843 { 844 u_int32_t val; 845 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 846 BNX_PCICFG_REG_WINDOW); 847 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 848 "val = 0x%08X\n", __func__, offset, val); 849 return (val); 850 } 851 #else 852 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 853 #endif 854 } 855 856 /****************************************************************************/ 857 /* Indirect register write. */ 858 /* */ 859 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 860 /* configuration space. Using this mechanism avoids issues with posted */ 861 /* writes but is muchh slower than memory-mapped I/O. */ 862 /* */ 863 /* Returns: */ 864 /* Nothing. */ 865 /****************************************************************************/ 866 void 867 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 868 { 869 struct pci_attach_args *pa = &(sc->bnx_pa); 870 871 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 872 __func__, offset, val); 873 874 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 875 offset); 876 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 877 } 878 879 /****************************************************************************/ 880 /* Context memory write. */ 881 /* */ 882 /* The NetXtreme II controller uses context memory to track connection */ 883 /* information for L2 and higher network protocols. */ 884 /* */ 885 /* Returns: */ 886 /* Nothing. */ 887 /****************************************************************************/ 888 void 889 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t ctx_offset, 890 u_int32_t ctx_val) 891 { 892 u_int32_t idx, offset = ctx_offset + cid_addr; 893 u_int32_t val, retry_cnt = 5; 894 895 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 896 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 897 REG_WR(sc, BNX_CTX_CTX_CTRL, 898 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 899 900 for (idx = 0; idx < retry_cnt; idx++) { 901 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 902 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 903 break; 904 DELAY(5); 905 } 906 907 #if 0 908 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 909 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 910 "cid_addr = 0x%08X, offset = 0x%08X!\n", 911 __FILE__, __LINE__, cid_addr, ctx_offset); 912 #endif 913 914 } else { 915 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 916 REG_WR(sc, BNX_CTX_DATA, ctx_val); 917 } 918 } 919 920 /****************************************************************************/ 921 /* PHY register read. */ 922 /* */ 923 /* Implements register reads on the MII bus. */ 924 /* */ 925 /* Returns: */ 926 /* The value of the register. */ 927 /****************************************************************************/ 928 int 929 bnx_miibus_read_reg(device_t dev, int phy, int reg) 930 { 931 struct bnx_softc *sc = device_private(dev); 932 u_int32_t val; 933 int i; 934 935 /* Make sure we are accessing the correct PHY address. */ 936 if (phy != sc->bnx_phy_addr) { 937 DBPRINT(sc, BNX_VERBOSE, 938 "Invalid PHY address %d for PHY read!\n", phy); 939 return(0); 940 } 941 942 /* 943 * The BCM5709S PHY is an IEEE Clause 45 PHY 944 * with special mappings to work with IEEE 945 * Clause 22 register accesses. 946 */ 947 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 948 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 949 reg += 0x10; 950 } 951 952 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 953 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 954 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 955 956 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 957 REG_RD(sc, BNX_EMAC_MDIO_MODE); 958 959 DELAY(40); 960 } 961 962 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 963 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 964 BNX_EMAC_MDIO_COMM_START_BUSY; 965 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 966 967 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 968 DELAY(10); 969 970 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 971 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 972 DELAY(5); 973 974 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 975 val &= BNX_EMAC_MDIO_COMM_DATA; 976 977 break; 978 } 979 } 980 981 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 982 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 983 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 984 val = 0x0; 985 } else 986 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 987 988 DBPRINT(sc, BNX_EXCESSIVE, 989 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 990 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 991 992 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 993 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 994 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 995 996 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 997 REG_RD(sc, BNX_EMAC_MDIO_MODE); 998 999 DELAY(40); 1000 } 1001 1002 return (val & 0xffff); 1003 } 1004 1005 /****************************************************************************/ 1006 /* PHY register write. */ 1007 /* */ 1008 /* Implements register writes on the MII bus. */ 1009 /* */ 1010 /* Returns: */ 1011 /* The value of the register. */ 1012 /****************************************************************************/ 1013 void 1014 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 1015 { 1016 struct bnx_softc *sc = device_private(dev); 1017 u_int32_t val1; 1018 int i; 1019 1020 /* Make sure we are accessing the correct PHY address. */ 1021 if (phy != sc->bnx_phy_addr) { 1022 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 1023 phy); 1024 return; 1025 } 1026 1027 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1028 "val = 0x%04X\n", __func__, 1029 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 1030 1031 /* 1032 * The BCM5709S PHY is an IEEE Clause 45 PHY 1033 * with special mappings to work with IEEE 1034 * Clause 22 register accesses. 1035 */ 1036 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1037 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1038 reg += 0x10; 1039 } 1040 1041 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1042 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1043 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1044 1045 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1046 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1047 1048 DELAY(40); 1049 } 1050 1051 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1052 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1053 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1054 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1055 1056 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1057 DELAY(10); 1058 1059 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1060 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1061 DELAY(5); 1062 break; 1063 } 1064 } 1065 1066 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1067 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1068 __LINE__); 1069 } 1070 1071 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1072 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1073 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1074 1075 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1076 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1077 1078 DELAY(40); 1079 } 1080 } 1081 1082 /****************************************************************************/ 1083 /* MII bus status change. */ 1084 /* */ 1085 /* Called by the MII bus driver when the PHY establishes link to set the */ 1086 /* MAC interface registers. */ 1087 /* */ 1088 /* Returns: */ 1089 /* Nothing. */ 1090 /****************************************************************************/ 1091 void 1092 bnx_miibus_statchg(struct ifnet *ifp) 1093 { 1094 struct bnx_softc *sc = ifp->if_softc; 1095 struct mii_data *mii = &sc->bnx_mii; 1096 int val; 1097 1098 val = REG_RD(sc, BNX_EMAC_MODE); 1099 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1100 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1101 BNX_EMAC_MODE_25G); 1102 1103 /* Set MII or GMII interface based on the speed 1104 * negotiated by the PHY. 1105 */ 1106 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1107 case IFM_10_T: 1108 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1109 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1110 val |= BNX_EMAC_MODE_PORT_MII_10; 1111 break; 1112 } 1113 /* FALLTHROUGH */ 1114 case IFM_100_TX: 1115 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1116 val |= BNX_EMAC_MODE_PORT_MII; 1117 break; 1118 case IFM_2500_SX: 1119 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1120 val |= BNX_EMAC_MODE_25G; 1121 /* FALLTHROUGH */ 1122 case IFM_1000_T: 1123 case IFM_1000_SX: 1124 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1125 val |= BNX_EMAC_MODE_PORT_GMII; 1126 break; 1127 default: 1128 val |= BNX_EMAC_MODE_PORT_GMII; 1129 break; 1130 } 1131 1132 /* Set half or full duplex based on the duplicity 1133 * negotiated by the PHY. 1134 */ 1135 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1136 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1137 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1138 } else { 1139 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1140 } 1141 1142 REG_WR(sc, BNX_EMAC_MODE, val); 1143 } 1144 1145 /****************************************************************************/ 1146 /* Acquire NVRAM lock. */ 1147 /* */ 1148 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1149 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1150 /* for use by the driver. */ 1151 /* */ 1152 /* Returns: */ 1153 /* 0 on success, positive value on failure. */ 1154 /****************************************************************************/ 1155 int 1156 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1157 { 1158 u_int32_t val; 1159 int j; 1160 1161 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1162 1163 /* Request access to the flash interface. */ 1164 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1165 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1166 val = REG_RD(sc, BNX_NVM_SW_ARB); 1167 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1168 break; 1169 1170 DELAY(5); 1171 } 1172 1173 if (j >= NVRAM_TIMEOUT_COUNT) { 1174 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1175 return (EBUSY); 1176 } 1177 1178 return (0); 1179 } 1180 1181 /****************************************************************************/ 1182 /* Release NVRAM lock. */ 1183 /* */ 1184 /* When the caller is finished accessing NVRAM the lock must be released. */ 1185 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1186 /* for use by the driver. */ 1187 /* */ 1188 /* Returns: */ 1189 /* 0 on success, positive value on failure. */ 1190 /****************************************************************************/ 1191 int 1192 bnx_release_nvram_lock(struct bnx_softc *sc) 1193 { 1194 int j; 1195 u_int32_t val; 1196 1197 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1198 1199 /* Relinquish nvram interface. */ 1200 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1201 1202 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1203 val = REG_RD(sc, BNX_NVM_SW_ARB); 1204 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1205 break; 1206 1207 DELAY(5); 1208 } 1209 1210 if (j >= NVRAM_TIMEOUT_COUNT) { 1211 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1212 return (EBUSY); 1213 } 1214 1215 return (0); 1216 } 1217 1218 #ifdef BNX_NVRAM_WRITE_SUPPORT 1219 /****************************************************************************/ 1220 /* Enable NVRAM write access. */ 1221 /* */ 1222 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1223 /* */ 1224 /* Returns: */ 1225 /* 0 on success, positive value on failure. */ 1226 /****************************************************************************/ 1227 int 1228 bnx_enable_nvram_write(struct bnx_softc *sc) 1229 { 1230 u_int32_t val; 1231 1232 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1233 1234 val = REG_RD(sc, BNX_MISC_CFG); 1235 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1236 1237 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1238 int j; 1239 1240 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1241 REG_WR(sc, BNX_NVM_COMMAND, 1242 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1243 1244 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1245 DELAY(5); 1246 1247 val = REG_RD(sc, BNX_NVM_COMMAND); 1248 if (val & BNX_NVM_COMMAND_DONE) 1249 break; 1250 } 1251 1252 if (j >= NVRAM_TIMEOUT_COUNT) { 1253 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1254 return (EBUSY); 1255 } 1256 } 1257 1258 return (0); 1259 } 1260 1261 /****************************************************************************/ 1262 /* Disable NVRAM write access. */ 1263 /* */ 1264 /* When the caller is finished writing to NVRAM write access must be */ 1265 /* disabled. */ 1266 /* */ 1267 /* Returns: */ 1268 /* Nothing. */ 1269 /****************************************************************************/ 1270 void 1271 bnx_disable_nvram_write(struct bnx_softc *sc) 1272 { 1273 u_int32_t val; 1274 1275 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1276 1277 val = REG_RD(sc, BNX_MISC_CFG); 1278 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1279 } 1280 #endif 1281 1282 /****************************************************************************/ 1283 /* Enable NVRAM access. */ 1284 /* */ 1285 /* Before accessing NVRAM for read or write operations the caller must */ 1286 /* enabled NVRAM access. */ 1287 /* */ 1288 /* Returns: */ 1289 /* Nothing. */ 1290 /****************************************************************************/ 1291 void 1292 bnx_enable_nvram_access(struct bnx_softc *sc) 1293 { 1294 u_int32_t val; 1295 1296 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1297 1298 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1299 /* Enable both bits, even on read. */ 1300 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1301 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1302 } 1303 1304 /****************************************************************************/ 1305 /* Disable NVRAM access. */ 1306 /* */ 1307 /* When the caller is finished accessing NVRAM access must be disabled. */ 1308 /* */ 1309 /* Returns: */ 1310 /* Nothing. */ 1311 /****************************************************************************/ 1312 void 1313 bnx_disable_nvram_access(struct bnx_softc *sc) 1314 { 1315 u_int32_t val; 1316 1317 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1318 1319 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1320 1321 /* Disable both bits, even after read. */ 1322 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1323 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1324 } 1325 1326 #ifdef BNX_NVRAM_WRITE_SUPPORT 1327 /****************************************************************************/ 1328 /* Erase NVRAM page before writing. */ 1329 /* */ 1330 /* Non-buffered flash parts require that a page be erased before it is */ 1331 /* written. */ 1332 /* */ 1333 /* Returns: */ 1334 /* 0 on success, positive value on failure. */ 1335 /****************************************************************************/ 1336 int 1337 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1338 { 1339 u_int32_t cmd; 1340 int j; 1341 1342 /* Buffered flash doesn't require an erase. */ 1343 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1344 return (0); 1345 1346 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1347 1348 /* Build an erase command. */ 1349 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1350 BNX_NVM_COMMAND_DOIT; 1351 1352 /* 1353 * Clear the DONE bit separately, set the NVRAM adress to erase, 1354 * and issue the erase command. 1355 */ 1356 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1357 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1358 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1359 1360 /* Wait for completion. */ 1361 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1362 u_int32_t val; 1363 1364 DELAY(5); 1365 1366 val = REG_RD(sc, BNX_NVM_COMMAND); 1367 if (val & BNX_NVM_COMMAND_DONE) 1368 break; 1369 } 1370 1371 if (j >= NVRAM_TIMEOUT_COUNT) { 1372 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1373 return (EBUSY); 1374 } 1375 1376 return (0); 1377 } 1378 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1379 1380 /****************************************************************************/ 1381 /* Read a dword (32 bits) from NVRAM. */ 1382 /* */ 1383 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1384 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1385 /* */ 1386 /* Returns: */ 1387 /* 0 on success and the 32 bit value read, positive value on failure. */ 1388 /****************************************************************************/ 1389 int 1390 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1391 u_int8_t *ret_val, u_int32_t cmd_flags) 1392 { 1393 u_int32_t cmd; 1394 int i, rc = 0; 1395 1396 /* Build the command word. */ 1397 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1398 1399 /* Calculate the offset for buffered flash if translation is used. */ 1400 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1401 offset = ((offset / sc->bnx_flash_info->page_size) << 1402 sc->bnx_flash_info->page_bits) + 1403 (offset % sc->bnx_flash_info->page_size); 1404 } 1405 1406 /* 1407 * Clear the DONE bit separately, set the address to read, 1408 * and issue the read. 1409 */ 1410 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1411 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1412 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1413 1414 /* Wait for completion. */ 1415 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1416 u_int32_t val; 1417 1418 DELAY(5); 1419 1420 val = REG_RD(sc, BNX_NVM_COMMAND); 1421 if (val & BNX_NVM_COMMAND_DONE) { 1422 val = REG_RD(sc, BNX_NVM_READ); 1423 1424 val = bnx_be32toh(val); 1425 memcpy(ret_val, &val, 4); 1426 break; 1427 } 1428 } 1429 1430 /* Check for errors. */ 1431 if (i >= NVRAM_TIMEOUT_COUNT) { 1432 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1433 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1434 rc = EBUSY; 1435 } 1436 1437 return(rc); 1438 } 1439 1440 #ifdef BNX_NVRAM_WRITE_SUPPORT 1441 /****************************************************************************/ 1442 /* Write a dword (32 bits) to NVRAM. */ 1443 /* */ 1444 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1445 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1446 /* enabled NVRAM write access. */ 1447 /* */ 1448 /* Returns: */ 1449 /* 0 on success, positive value on failure. */ 1450 /****************************************************************************/ 1451 int 1452 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1453 u_int32_t cmd_flags) 1454 { 1455 u_int32_t cmd, val32; 1456 int j; 1457 1458 /* Build the command word. */ 1459 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1460 1461 /* Calculate the offset for buffered flash if translation is used. */ 1462 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1463 offset = ((offset / sc->bnx_flash_info->page_size) << 1464 sc->bnx_flash_info->page_bits) + 1465 (offset % sc->bnx_flash_info->page_size); 1466 } 1467 1468 /* 1469 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1470 * set the NVRAM address to write, and issue the write command 1471 */ 1472 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1473 memcpy(&val32, val, 4); 1474 val32 = htobe32(val32); 1475 REG_WR(sc, BNX_NVM_WRITE, val32); 1476 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1477 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1478 1479 /* Wait for completion. */ 1480 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1481 DELAY(5); 1482 1483 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1484 break; 1485 } 1486 if (j >= NVRAM_TIMEOUT_COUNT) { 1487 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1488 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1489 return (EBUSY); 1490 } 1491 1492 return (0); 1493 } 1494 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1495 1496 /****************************************************************************/ 1497 /* Initialize NVRAM access. */ 1498 /* */ 1499 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1500 /* access that device. */ 1501 /* */ 1502 /* Returns: */ 1503 /* 0 on success, positive value on failure. */ 1504 /****************************************************************************/ 1505 int 1506 bnx_init_nvram(struct bnx_softc *sc) 1507 { 1508 u_int32_t val; 1509 int j, entry_count, rc = 0; 1510 struct flash_spec *flash; 1511 1512 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1513 1514 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1515 sc->bnx_flash_info = &flash_5709; 1516 goto bnx_init_nvram_get_flash_size; 1517 } 1518 1519 /* Determine the selected interface. */ 1520 val = REG_RD(sc, BNX_NVM_CFG1); 1521 1522 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1523 1524 /* 1525 * Flash reconfiguration is required to support additional 1526 * NVRAM devices not directly supported in hardware. 1527 * Check if the flash interface was reconfigured 1528 * by the bootcode. 1529 */ 1530 1531 if (val & 0x40000000) { 1532 /* Flash interface reconfigured by bootcode. */ 1533 1534 DBPRINT(sc,BNX_INFO_LOAD, 1535 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1536 1537 for (j = 0, flash = &flash_table[0]; j < entry_count; 1538 j++, flash++) { 1539 if ((val & FLASH_BACKUP_STRAP_MASK) == 1540 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1541 sc->bnx_flash_info = flash; 1542 break; 1543 } 1544 } 1545 } else { 1546 /* Flash interface not yet reconfigured. */ 1547 u_int32_t mask; 1548 1549 DBPRINT(sc,BNX_INFO_LOAD, 1550 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1551 1552 if (val & (1 << 23)) 1553 mask = FLASH_BACKUP_STRAP_MASK; 1554 else 1555 mask = FLASH_STRAP_MASK; 1556 1557 /* Look for the matching NVRAM device configuration data. */ 1558 for (j = 0, flash = &flash_table[0]; j < entry_count; 1559 j++, flash++) { 1560 /* Check if the dev matches any of the known devices. */ 1561 if ((val & mask) == (flash->strapping & mask)) { 1562 /* Found a device match. */ 1563 sc->bnx_flash_info = flash; 1564 1565 /* Request access to the flash interface. */ 1566 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1567 return (rc); 1568 1569 /* Reconfigure the flash interface. */ 1570 bnx_enable_nvram_access(sc); 1571 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1572 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1573 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1574 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1575 bnx_disable_nvram_access(sc); 1576 bnx_release_nvram_lock(sc); 1577 1578 break; 1579 } 1580 } 1581 } 1582 1583 /* Check if a matching device was found. */ 1584 if (j == entry_count) { 1585 sc->bnx_flash_info = NULL; 1586 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1587 __FILE__, __LINE__); 1588 rc = ENODEV; 1589 } 1590 1591 bnx_init_nvram_get_flash_size: 1592 /* Write the flash config data to the shared memory interface. */ 1593 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1594 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1595 if (val) 1596 sc->bnx_flash_size = val; 1597 else 1598 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1599 1600 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1601 "0x%08X\n", sc->bnx_flash_info->total_size); 1602 1603 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1604 1605 return (rc); 1606 } 1607 1608 /****************************************************************************/ 1609 /* Read an arbitrary range of data from NVRAM. */ 1610 /* */ 1611 /* Prepares the NVRAM interface for access and reads the requested data */ 1612 /* into the supplied buffer. */ 1613 /* */ 1614 /* Returns: */ 1615 /* 0 on success and the data read, positive value on failure. */ 1616 /****************************************************************************/ 1617 int 1618 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1619 int buf_size) 1620 { 1621 int rc = 0; 1622 u_int32_t cmd_flags, offset32, len32, extra; 1623 1624 if (buf_size == 0) 1625 return (0); 1626 1627 /* Request access to the flash interface. */ 1628 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1629 return (rc); 1630 1631 /* Enable access to flash interface */ 1632 bnx_enable_nvram_access(sc); 1633 1634 len32 = buf_size; 1635 offset32 = offset; 1636 extra = 0; 1637 1638 cmd_flags = 0; 1639 1640 if (offset32 & 3) { 1641 u_int8_t buf[4]; 1642 u_int32_t pre_len; 1643 1644 offset32 &= ~3; 1645 pre_len = 4 - (offset & 3); 1646 1647 if (pre_len >= len32) { 1648 pre_len = len32; 1649 cmd_flags = 1650 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1651 } else 1652 cmd_flags = BNX_NVM_COMMAND_FIRST; 1653 1654 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1655 1656 if (rc) 1657 return (rc); 1658 1659 memcpy(ret_buf, buf + (offset & 3), pre_len); 1660 1661 offset32 += 4; 1662 ret_buf += pre_len; 1663 len32 -= pre_len; 1664 } 1665 1666 if (len32 & 3) { 1667 extra = 4 - (len32 & 3); 1668 len32 = (len32 + 4) & ~3; 1669 } 1670 1671 if (len32 == 4) { 1672 u_int8_t buf[4]; 1673 1674 if (cmd_flags) 1675 cmd_flags = BNX_NVM_COMMAND_LAST; 1676 else 1677 cmd_flags = 1678 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1679 1680 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1681 1682 memcpy(ret_buf, buf, 4 - extra); 1683 } else if (len32 > 0) { 1684 u_int8_t buf[4]; 1685 1686 /* Read the first word. */ 1687 if (cmd_flags) 1688 cmd_flags = 0; 1689 else 1690 cmd_flags = BNX_NVM_COMMAND_FIRST; 1691 1692 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1693 1694 /* Advance to the next dword. */ 1695 offset32 += 4; 1696 ret_buf += 4; 1697 len32 -= 4; 1698 1699 while (len32 > 4 && rc == 0) { 1700 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1701 1702 /* Advance to the next dword. */ 1703 offset32 += 4; 1704 ret_buf += 4; 1705 len32 -= 4; 1706 } 1707 1708 if (rc) 1709 return (rc); 1710 1711 cmd_flags = BNX_NVM_COMMAND_LAST; 1712 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1713 1714 memcpy(ret_buf, buf, 4 - extra); 1715 } 1716 1717 /* Disable access to flash interface and release the lock. */ 1718 bnx_disable_nvram_access(sc); 1719 bnx_release_nvram_lock(sc); 1720 1721 return (rc); 1722 } 1723 1724 #ifdef BNX_NVRAM_WRITE_SUPPORT 1725 /****************************************************************************/ 1726 /* Write an arbitrary range of data from NVRAM. */ 1727 /* */ 1728 /* Prepares the NVRAM interface for write access and writes the requested */ 1729 /* data from the supplied buffer. The caller is responsible for */ 1730 /* calculating any appropriate CRCs. */ 1731 /* */ 1732 /* Returns: */ 1733 /* 0 on success, positive value on failure. */ 1734 /****************************************************************************/ 1735 int 1736 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1737 int buf_size) 1738 { 1739 u_int32_t written, offset32, len32; 1740 u_int8_t *buf, start[4], end[4]; 1741 int rc = 0; 1742 int align_start, align_end; 1743 1744 buf = data_buf; 1745 offset32 = offset; 1746 len32 = buf_size; 1747 align_start = align_end = 0; 1748 1749 if ((align_start = (offset32 & 3))) { 1750 offset32 &= ~3; 1751 len32 += align_start; 1752 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1753 return (rc); 1754 } 1755 1756 if (len32 & 3) { 1757 if ((len32 > 4) || !align_start) { 1758 align_end = 4 - (len32 & 3); 1759 len32 += align_end; 1760 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1761 end, 4))) { 1762 return (rc); 1763 } 1764 } 1765 } 1766 1767 if (align_start || align_end) { 1768 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1769 if (buf == 0) 1770 return (ENOMEM); 1771 1772 if (align_start) 1773 memcpy(buf, start, 4); 1774 1775 if (align_end) 1776 memcpy(buf + len32 - 4, end, 4); 1777 1778 memcpy(buf + align_start, data_buf, buf_size); 1779 } 1780 1781 written = 0; 1782 while ((written < len32) && (rc == 0)) { 1783 u_int32_t page_start, page_end, data_start, data_end; 1784 u_int32_t addr, cmd_flags; 1785 int i; 1786 u_int8_t flash_buffer[264]; 1787 1788 /* Find the page_start addr */ 1789 page_start = offset32 + written; 1790 page_start -= (page_start % sc->bnx_flash_info->page_size); 1791 /* Find the page_end addr */ 1792 page_end = page_start + sc->bnx_flash_info->page_size; 1793 /* Find the data_start addr */ 1794 data_start = (written == 0) ? offset32 : page_start; 1795 /* Find the data_end addr */ 1796 data_end = (page_end > offset32 + len32) ? 1797 (offset32 + len32) : page_end; 1798 1799 /* Request access to the flash interface. */ 1800 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1801 goto nvram_write_end; 1802 1803 /* Enable access to flash interface */ 1804 bnx_enable_nvram_access(sc); 1805 1806 cmd_flags = BNX_NVM_COMMAND_FIRST; 1807 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1808 int j; 1809 1810 /* Read the whole page into the buffer 1811 * (non-buffer flash only) */ 1812 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1813 if (j == (sc->bnx_flash_info->page_size - 4)) 1814 cmd_flags |= BNX_NVM_COMMAND_LAST; 1815 1816 rc = bnx_nvram_read_dword(sc, 1817 page_start + j, 1818 &flash_buffer[j], 1819 cmd_flags); 1820 1821 if (rc) 1822 goto nvram_write_end; 1823 1824 cmd_flags = 0; 1825 } 1826 } 1827 1828 /* Enable writes to flash interface (unlock write-protect) */ 1829 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1830 goto nvram_write_end; 1831 1832 /* Erase the page */ 1833 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1834 goto nvram_write_end; 1835 1836 /* Re-enable the write again for the actual write */ 1837 bnx_enable_nvram_write(sc); 1838 1839 /* Loop to write back the buffer data from page_start to 1840 * data_start */ 1841 i = 0; 1842 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1843 for (addr = page_start; addr < data_start; 1844 addr += 4, i += 4) { 1845 1846 rc = bnx_nvram_write_dword(sc, addr, 1847 &flash_buffer[i], cmd_flags); 1848 1849 if (rc != 0) 1850 goto nvram_write_end; 1851 1852 cmd_flags = 0; 1853 } 1854 } 1855 1856 /* Loop to write the new data from data_start to data_end */ 1857 for (addr = data_start; addr < data_end; addr += 4, i++) { 1858 if ((addr == page_end - 4) || 1859 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1860 && (addr == data_end - 4))) { 1861 1862 cmd_flags |= BNX_NVM_COMMAND_LAST; 1863 } 1864 1865 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1866 1867 if (rc != 0) 1868 goto nvram_write_end; 1869 1870 cmd_flags = 0; 1871 buf += 4; 1872 } 1873 1874 /* Loop to write back the buffer data from data_end 1875 * to page_end */ 1876 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1877 for (addr = data_end; addr < page_end; 1878 addr += 4, i += 4) { 1879 1880 if (addr == page_end-4) 1881 cmd_flags = BNX_NVM_COMMAND_LAST; 1882 1883 rc = bnx_nvram_write_dword(sc, addr, 1884 &flash_buffer[i], cmd_flags); 1885 1886 if (rc != 0) 1887 goto nvram_write_end; 1888 1889 cmd_flags = 0; 1890 } 1891 } 1892 1893 /* Disable writes to flash interface (lock write-protect) */ 1894 bnx_disable_nvram_write(sc); 1895 1896 /* Disable access to flash interface */ 1897 bnx_disable_nvram_access(sc); 1898 bnx_release_nvram_lock(sc); 1899 1900 /* Increment written */ 1901 written += data_end - data_start; 1902 } 1903 1904 nvram_write_end: 1905 if (align_start || align_end) 1906 free(buf, M_DEVBUF); 1907 1908 return (rc); 1909 } 1910 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1911 1912 /****************************************************************************/ 1913 /* Verifies that NVRAM is accessible and contains valid data. */ 1914 /* */ 1915 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1916 /* correct. */ 1917 /* */ 1918 /* Returns: */ 1919 /* 0 on success, positive value on failure. */ 1920 /****************************************************************************/ 1921 int 1922 bnx_nvram_test(struct bnx_softc *sc) 1923 { 1924 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1925 u_int8_t *data = (u_int8_t *) buf; 1926 int rc = 0; 1927 u_int32_t magic, csum; 1928 1929 /* 1930 * Check that the device NVRAM is valid by reading 1931 * the magic value at offset 0. 1932 */ 1933 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1934 goto bnx_nvram_test_done; 1935 1936 magic = bnx_be32toh(buf[0]); 1937 if (magic != BNX_NVRAM_MAGIC) { 1938 rc = ENODEV; 1939 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1940 "Expected: 0x%08X, Found: 0x%08X\n", 1941 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1942 goto bnx_nvram_test_done; 1943 } 1944 1945 /* 1946 * Verify that the device NVRAM includes valid 1947 * configuration data. 1948 */ 1949 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1950 goto bnx_nvram_test_done; 1951 1952 csum = ether_crc32_le(data, 0x100); 1953 if (csum != BNX_CRC32_RESIDUAL) { 1954 rc = ENODEV; 1955 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1956 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1957 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1958 goto bnx_nvram_test_done; 1959 } 1960 1961 csum = ether_crc32_le(data + 0x100, 0x100); 1962 if (csum != BNX_CRC32_RESIDUAL) { 1963 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1964 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1965 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1966 rc = ENODEV; 1967 } 1968 1969 bnx_nvram_test_done: 1970 return (rc); 1971 } 1972 1973 /****************************************************************************/ 1974 /* Identifies the current media type of the controller and sets the PHY */ 1975 /* address. */ 1976 /* */ 1977 /* Returns: */ 1978 /* Nothing. */ 1979 /****************************************************************************/ 1980 void 1981 bnx_get_media(struct bnx_softc *sc) 1982 { 1983 sc->bnx_phy_addr = 1; 1984 1985 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1986 u_int32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 1987 u_int32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 1988 u_int32_t strap; 1989 1990 /* 1991 * The BCM5709S is software configurable 1992 * for Copper or SerDes operation. 1993 */ 1994 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 1995 DBPRINT(sc, BNX_INFO_LOAD, 1996 "5709 bonded for copper.\n"); 1997 goto bnx_get_media_exit; 1998 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 1999 DBPRINT(sc, BNX_INFO_LOAD, 2000 "5709 bonded for dual media.\n"); 2001 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2002 goto bnx_get_media_exit; 2003 } 2004 2005 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2006 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2007 else { 2008 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2009 >> 8; 2010 } 2011 2012 if (sc->bnx_pa.pa_function == 0) { 2013 switch (strap) { 2014 case 0x4: 2015 case 0x5: 2016 case 0x6: 2017 DBPRINT(sc, BNX_INFO_LOAD, 2018 "BCM5709 s/w configured for SerDes.\n"); 2019 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2020 break; 2021 default: 2022 DBPRINT(sc, BNX_INFO_LOAD, 2023 "BCM5709 s/w configured for Copper.\n"); 2024 } 2025 } else { 2026 switch (strap) { 2027 case 0x1: 2028 case 0x2: 2029 case 0x4: 2030 DBPRINT(sc, BNX_INFO_LOAD, 2031 "BCM5709 s/w configured for SerDes.\n"); 2032 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2033 break; 2034 default: 2035 DBPRINT(sc, BNX_INFO_LOAD, 2036 "BCM5709 s/w configured for Copper.\n"); 2037 } 2038 } 2039 2040 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2041 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2042 2043 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2044 u_int32_t val; 2045 2046 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2047 2048 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2049 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2050 2051 /* 2052 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2053 * separate PHY for SerDes. 2054 */ 2055 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2056 sc->bnx_phy_addr = 2; 2057 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2058 BNX_SHARED_HW_CFG_CONFIG); 2059 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2060 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2061 DBPRINT(sc, BNX_INFO_LOAD, 2062 "Found 2.5Gb capable adapter\n"); 2063 } 2064 } 2065 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2066 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2067 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2068 2069 bnx_get_media_exit: 2070 DBPRINT(sc, (BNX_INFO_LOAD), 2071 "Using PHY address %d.\n", sc->bnx_phy_addr); 2072 } 2073 2074 /****************************************************************************/ 2075 /* Performs PHY initialization required before MII drivers access the */ 2076 /* device. */ 2077 /* */ 2078 /* Returns: */ 2079 /* Nothing. */ 2080 /****************************************************************************/ 2081 void 2082 bnx_init_media(struct bnx_softc *sc) 2083 { 2084 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2085 /* 2086 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2087 * IEEE Clause 22 method. Otherwise we have no way to attach 2088 * the PHY to the mii(4) layer. PHY specific configuration 2089 * is done by the mii(4) layer. 2090 */ 2091 2092 /* Select auto-negotiation MMD of the PHY. */ 2093 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2094 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2095 2096 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2097 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2098 2099 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2100 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2101 } 2102 } 2103 2104 /****************************************************************************/ 2105 /* Free any DMA memory owned by the driver. */ 2106 /* */ 2107 /* Scans through each data structre that requires DMA memory and frees */ 2108 /* the memory if allocated. */ 2109 /* */ 2110 /* Returns: */ 2111 /* Nothing. */ 2112 /****************************************************************************/ 2113 void 2114 bnx_dma_free(struct bnx_softc *sc) 2115 { 2116 int i; 2117 2118 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2119 2120 /* Destroy the status block. */ 2121 if (sc->status_block != NULL && sc->status_map != NULL) { 2122 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2123 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2124 BNX_STATUS_BLK_SZ); 2125 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2126 sc->status_rseg); 2127 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2128 sc->status_block = NULL; 2129 sc->status_map = NULL; 2130 } 2131 2132 /* Destroy the statistics block. */ 2133 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2134 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2135 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2136 BNX_STATS_BLK_SZ); 2137 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2138 sc->stats_rseg); 2139 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2140 sc->stats_block = NULL; 2141 sc->stats_map = NULL; 2142 } 2143 2144 /* Free, unmap and destroy all context memory pages. */ 2145 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2146 for (i = 0; i < sc->ctx_pages; i++) { 2147 if (sc->ctx_block[i] != NULL) { 2148 bus_dmamap_unload(sc->bnx_dmatag, 2149 sc->ctx_map[i]); 2150 bus_dmamem_unmap(sc->bnx_dmatag, 2151 (void *)sc->ctx_block[i], 2152 BCM_PAGE_SIZE); 2153 bus_dmamem_free(sc->bnx_dmatag, 2154 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2155 bus_dmamap_destroy(sc->bnx_dmatag, 2156 sc->ctx_map[i]); 2157 sc->ctx_block[i] = NULL; 2158 } 2159 } 2160 } 2161 2162 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2163 for (i = 0; i < TX_PAGES; i++ ) { 2164 if (sc->tx_bd_chain[i] != NULL && 2165 sc->tx_bd_chain_map[i] != NULL) { 2166 bus_dmamap_unload(sc->bnx_dmatag, 2167 sc->tx_bd_chain_map[i]); 2168 bus_dmamem_unmap(sc->bnx_dmatag, 2169 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2170 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2171 sc->tx_bd_chain_rseg[i]); 2172 bus_dmamap_destroy(sc->bnx_dmatag, 2173 sc->tx_bd_chain_map[i]); 2174 sc->tx_bd_chain[i] = NULL; 2175 sc->tx_bd_chain_map[i] = NULL; 2176 } 2177 } 2178 2179 /* Destroy the TX dmamaps. */ 2180 /* This isn't necessary since we dont allocate them up front */ 2181 2182 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2183 for (i = 0; i < RX_PAGES; i++ ) { 2184 if (sc->rx_bd_chain[i] != NULL && 2185 sc->rx_bd_chain_map[i] != NULL) { 2186 bus_dmamap_unload(sc->bnx_dmatag, 2187 sc->rx_bd_chain_map[i]); 2188 bus_dmamem_unmap(sc->bnx_dmatag, 2189 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2190 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2191 sc->rx_bd_chain_rseg[i]); 2192 2193 bus_dmamap_destroy(sc->bnx_dmatag, 2194 sc->rx_bd_chain_map[i]); 2195 sc->rx_bd_chain[i] = NULL; 2196 sc->rx_bd_chain_map[i] = NULL; 2197 } 2198 } 2199 2200 /* Unload and destroy the RX mbuf maps. */ 2201 for (i = 0; i < TOTAL_RX_BD; i++) { 2202 if (sc->rx_mbuf_map[i] != NULL) { 2203 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2204 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2205 } 2206 } 2207 2208 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2209 } 2210 2211 /****************************************************************************/ 2212 /* Allocate any DMA memory needed by the driver. */ 2213 /* */ 2214 /* Allocates DMA memory needed for the various global structures needed by */ 2215 /* hardware. */ 2216 /* */ 2217 /* Returns: */ 2218 /* 0 for success, positive value for failure. */ 2219 /****************************************************************************/ 2220 int 2221 bnx_dma_alloc(struct bnx_softc *sc) 2222 { 2223 int i, rc = 0; 2224 2225 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2226 2227 /* 2228 * Allocate DMA memory for the status block, map the memory into DMA 2229 * space, and fetch the physical address of the block. 2230 */ 2231 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2232 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2233 aprint_error_dev(sc->bnx_dev, 2234 "Could not create status block DMA map!\n"); 2235 rc = ENOMEM; 2236 goto bnx_dma_alloc_exit; 2237 } 2238 2239 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2240 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2241 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2242 aprint_error_dev(sc->bnx_dev, 2243 "Could not allocate status block DMA memory!\n"); 2244 rc = ENOMEM; 2245 goto bnx_dma_alloc_exit; 2246 } 2247 2248 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2249 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2250 aprint_error_dev(sc->bnx_dev, 2251 "Could not map status block DMA memory!\n"); 2252 rc = ENOMEM; 2253 goto bnx_dma_alloc_exit; 2254 } 2255 2256 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2257 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2258 aprint_error_dev(sc->bnx_dev, 2259 "Could not load status block DMA memory!\n"); 2260 rc = ENOMEM; 2261 goto bnx_dma_alloc_exit; 2262 } 2263 2264 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2265 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2266 2267 /* DRC - Fix for 64 bit addresses. */ 2268 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2269 (u_int32_t) sc->status_block_paddr); 2270 2271 /* BCM5709 uses host memory as cache for context memory. */ 2272 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2273 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2274 if (sc->ctx_pages == 0) 2275 sc->ctx_pages = 1; 2276 if (sc->ctx_pages > 4) /* XXX */ 2277 sc->ctx_pages = 4; 2278 2279 DBRUNIF((sc->ctx_pages > 512), 2280 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2281 __FILE__, __LINE__, sc->ctx_pages)); 2282 2283 2284 for (i = 0; i < sc->ctx_pages; i++) { 2285 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2286 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2287 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2288 &sc->ctx_map[i]) != 0) { 2289 rc = ENOMEM; 2290 goto bnx_dma_alloc_exit; 2291 } 2292 2293 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2294 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2295 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2296 rc = ENOMEM; 2297 goto bnx_dma_alloc_exit; 2298 } 2299 2300 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2301 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2302 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2303 rc = ENOMEM; 2304 goto bnx_dma_alloc_exit; 2305 } 2306 2307 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2308 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2309 BUS_DMA_NOWAIT) != 0) { 2310 rc = ENOMEM; 2311 goto bnx_dma_alloc_exit; 2312 } 2313 2314 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2315 } 2316 } 2317 2318 /* 2319 * Allocate DMA memory for the statistics block, map the memory into 2320 * DMA space, and fetch the physical address of the block. 2321 */ 2322 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2323 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2324 aprint_error_dev(sc->bnx_dev, 2325 "Could not create stats block DMA map!\n"); 2326 rc = ENOMEM; 2327 goto bnx_dma_alloc_exit; 2328 } 2329 2330 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2331 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2332 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2333 aprint_error_dev(sc->bnx_dev, 2334 "Could not allocate stats block DMA memory!\n"); 2335 rc = ENOMEM; 2336 goto bnx_dma_alloc_exit; 2337 } 2338 2339 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2340 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2341 aprint_error_dev(sc->bnx_dev, 2342 "Could not map stats block DMA memory!\n"); 2343 rc = ENOMEM; 2344 goto bnx_dma_alloc_exit; 2345 } 2346 2347 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2348 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2349 aprint_error_dev(sc->bnx_dev, 2350 "Could not load status block DMA memory!\n"); 2351 rc = ENOMEM; 2352 goto bnx_dma_alloc_exit; 2353 } 2354 2355 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2356 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2357 2358 /* DRC - Fix for 64 bit address. */ 2359 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2360 (u_int32_t) sc->stats_block_paddr); 2361 2362 /* 2363 * Allocate DMA memory for the TX buffer descriptor chain, 2364 * and fetch the physical address of the block. 2365 */ 2366 for (i = 0; i < TX_PAGES; i++) { 2367 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2368 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2369 &sc->tx_bd_chain_map[i])) { 2370 aprint_error_dev(sc->bnx_dev, 2371 "Could not create Tx desc %d DMA map!\n", i); 2372 rc = ENOMEM; 2373 goto bnx_dma_alloc_exit; 2374 } 2375 2376 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2377 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2378 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2379 aprint_error_dev(sc->bnx_dev, 2380 "Could not allocate TX desc %d DMA memory!\n", 2381 i); 2382 rc = ENOMEM; 2383 goto bnx_dma_alloc_exit; 2384 } 2385 2386 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2387 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2388 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2389 aprint_error_dev(sc->bnx_dev, 2390 "Could not map TX desc %d DMA memory!\n", i); 2391 rc = ENOMEM; 2392 goto bnx_dma_alloc_exit; 2393 } 2394 2395 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2396 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2397 BUS_DMA_NOWAIT)) { 2398 aprint_error_dev(sc->bnx_dev, 2399 "Could not load TX desc %d DMA memory!\n", i); 2400 rc = ENOMEM; 2401 goto bnx_dma_alloc_exit; 2402 } 2403 2404 sc->tx_bd_chain_paddr[i] = 2405 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2406 2407 /* DRC - Fix for 64 bit systems. */ 2408 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2409 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2410 } 2411 2412 /* 2413 * Create lists to hold TX mbufs. 2414 */ 2415 TAILQ_INIT(&sc->tx_free_pkts); 2416 TAILQ_INIT(&sc->tx_used_pkts); 2417 sc->tx_pkt_count = 0; 2418 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2419 2420 /* 2421 * Allocate DMA memory for the Rx buffer descriptor chain, 2422 * and fetch the physical address of the block. 2423 */ 2424 for (i = 0; i < RX_PAGES; i++) { 2425 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2426 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2427 &sc->rx_bd_chain_map[i])) { 2428 aprint_error_dev(sc->bnx_dev, 2429 "Could not create Rx desc %d DMA map!\n", i); 2430 rc = ENOMEM; 2431 goto bnx_dma_alloc_exit; 2432 } 2433 2434 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2435 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2436 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2437 aprint_error_dev(sc->bnx_dev, 2438 "Could not allocate Rx desc %d DMA memory!\n", i); 2439 rc = ENOMEM; 2440 goto bnx_dma_alloc_exit; 2441 } 2442 2443 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2444 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2445 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2446 aprint_error_dev(sc->bnx_dev, 2447 "Could not map Rx desc %d DMA memory!\n", i); 2448 rc = ENOMEM; 2449 goto bnx_dma_alloc_exit; 2450 } 2451 2452 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2453 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2454 BUS_DMA_NOWAIT)) { 2455 aprint_error_dev(sc->bnx_dev, 2456 "Could not load Rx desc %d DMA memory!\n", i); 2457 rc = ENOMEM; 2458 goto bnx_dma_alloc_exit; 2459 } 2460 2461 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2462 sc->rx_bd_chain_paddr[i] = 2463 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2464 2465 /* DRC - Fix for 64 bit systems. */ 2466 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2467 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2468 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2469 0, BNX_RX_CHAIN_PAGE_SZ, 2470 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2471 } 2472 2473 /* 2474 * Create DMA maps for the Rx buffer mbufs. 2475 */ 2476 for (i = 0; i < TOTAL_RX_BD; i++) { 2477 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2478 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2479 &sc->rx_mbuf_map[i])) { 2480 aprint_error_dev(sc->bnx_dev, 2481 "Could not create Rx mbuf %d DMA map!\n", i); 2482 rc = ENOMEM; 2483 goto bnx_dma_alloc_exit; 2484 } 2485 } 2486 2487 bnx_dma_alloc_exit: 2488 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2489 2490 return(rc); 2491 } 2492 2493 /****************************************************************************/ 2494 /* Release all resources used by the driver. */ 2495 /* */ 2496 /* Releases all resources acquired by the driver including interrupts, */ 2497 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2498 /* */ 2499 /* Returns: */ 2500 /* Nothing. */ 2501 /****************************************************************************/ 2502 void 2503 bnx_release_resources(struct bnx_softc *sc) 2504 { 2505 struct pci_attach_args *pa = &(sc->bnx_pa); 2506 2507 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2508 2509 bnx_dma_free(sc); 2510 2511 if (sc->bnx_intrhand != NULL) 2512 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2513 2514 if (sc->bnx_size) 2515 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2516 2517 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2518 } 2519 2520 /****************************************************************************/ 2521 /* Firmware synchronization. */ 2522 /* */ 2523 /* Before performing certain events such as a chip reset, synchronize with */ 2524 /* the firmware first. */ 2525 /* */ 2526 /* Returns: */ 2527 /* 0 for success, positive value for failure. */ 2528 /****************************************************************************/ 2529 int 2530 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2531 { 2532 int i, rc = 0; 2533 u_int32_t val; 2534 2535 /* Don't waste any time if we've timed out before. */ 2536 if (sc->bnx_fw_timed_out) { 2537 rc = EBUSY; 2538 goto bnx_fw_sync_exit; 2539 } 2540 2541 /* Increment the message sequence number. */ 2542 sc->bnx_fw_wr_seq++; 2543 msg_data |= sc->bnx_fw_wr_seq; 2544 2545 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2546 msg_data); 2547 2548 /* Send the message to the bootcode driver mailbox. */ 2549 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2550 2551 /* Wait for the bootcode to acknowledge the message. */ 2552 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2553 /* Check for a response in the bootcode firmware mailbox. */ 2554 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2555 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2556 break; 2557 DELAY(1000); 2558 } 2559 2560 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2561 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2562 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2563 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2564 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2565 2566 msg_data &= ~BNX_DRV_MSG_CODE; 2567 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2568 2569 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2570 2571 sc->bnx_fw_timed_out = 1; 2572 rc = EBUSY; 2573 } 2574 2575 bnx_fw_sync_exit: 2576 return (rc); 2577 } 2578 2579 /****************************************************************************/ 2580 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2581 /* */ 2582 /* Returns: */ 2583 /* Nothing. */ 2584 /****************************************************************************/ 2585 void 2586 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2587 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2588 { 2589 int i; 2590 u_int32_t val; 2591 2592 /* Set the page size used by RV2P. */ 2593 if (rv2p_proc == RV2P_PROC2) { 2594 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2595 USABLE_RX_BD_PER_PAGE); 2596 } 2597 2598 for (i = 0; i < rv2p_code_len; i += 8) { 2599 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2600 rv2p_code++; 2601 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2602 rv2p_code++; 2603 2604 if (rv2p_proc == RV2P_PROC1) { 2605 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2606 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2607 } else { 2608 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2609 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2610 } 2611 } 2612 2613 /* Reset the processor, un-stall is done later. */ 2614 if (rv2p_proc == RV2P_PROC1) 2615 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2616 else 2617 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2618 } 2619 2620 /****************************************************************************/ 2621 /* Load RISC processor firmware. */ 2622 /* */ 2623 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2624 /* associated with a particular processor. */ 2625 /* */ 2626 /* Returns: */ 2627 /* Nothing. */ 2628 /****************************************************************************/ 2629 void 2630 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2631 struct fw_info *fw) 2632 { 2633 u_int32_t offset; 2634 u_int32_t val; 2635 2636 /* Halt the CPU. */ 2637 val = REG_RD_IND(sc, cpu_reg->mode); 2638 val |= cpu_reg->mode_value_halt; 2639 REG_WR_IND(sc, cpu_reg->mode, val); 2640 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2641 2642 /* Load the Text area. */ 2643 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2644 if (fw->text) { 2645 int j; 2646 2647 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2648 REG_WR_IND(sc, offset, fw->text[j]); 2649 } 2650 2651 /* Load the Data area. */ 2652 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2653 if (fw->data) { 2654 int j; 2655 2656 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2657 REG_WR_IND(sc, offset, fw->data[j]); 2658 } 2659 2660 /* Load the SBSS area. */ 2661 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2662 if (fw->sbss) { 2663 int j; 2664 2665 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2666 REG_WR_IND(sc, offset, fw->sbss[j]); 2667 } 2668 2669 /* Load the BSS area. */ 2670 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2671 if (fw->bss) { 2672 int j; 2673 2674 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2675 REG_WR_IND(sc, offset, fw->bss[j]); 2676 } 2677 2678 /* Load the Read-Only area. */ 2679 offset = cpu_reg->spad_base + 2680 (fw->rodata_addr - cpu_reg->mips_view_base); 2681 if (fw->rodata) { 2682 int j; 2683 2684 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2685 REG_WR_IND(sc, offset, fw->rodata[j]); 2686 } 2687 2688 /* Clear the pre-fetch instruction. */ 2689 REG_WR_IND(sc, cpu_reg->inst, 0); 2690 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2691 2692 /* Start the CPU. */ 2693 val = REG_RD_IND(sc, cpu_reg->mode); 2694 val &= ~cpu_reg->mode_value_halt; 2695 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2696 REG_WR_IND(sc, cpu_reg->mode, val); 2697 } 2698 2699 /****************************************************************************/ 2700 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2701 /* */ 2702 /* Loads the firmware for each CPU and starts the CPU. */ 2703 /* */ 2704 /* Returns: */ 2705 /* Nothing. */ 2706 /****************************************************************************/ 2707 void 2708 bnx_init_cpus(struct bnx_softc *sc) 2709 { 2710 struct cpu_reg cpu_reg; 2711 struct fw_info fw; 2712 2713 switch(BNX_CHIP_NUM(sc)) { 2714 case BNX_CHIP_NUM_5709: 2715 /* Initialize the RV2P processor. */ 2716 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2717 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2718 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2719 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2720 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2721 } else { 2722 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2723 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2724 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2725 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2726 } 2727 2728 /* Initialize the RX Processor. */ 2729 cpu_reg.mode = BNX_RXP_CPU_MODE; 2730 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2731 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2732 cpu_reg.state = BNX_RXP_CPU_STATE; 2733 cpu_reg.state_value_clear = 0xffffff; 2734 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2735 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2736 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2737 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2738 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2739 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2740 cpu_reg.mips_view_base = 0x8000000; 2741 2742 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2743 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2744 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2745 fw.start_addr = bnx_RXP_b09FwStartAddr; 2746 2747 fw.text_addr = bnx_RXP_b09FwTextAddr; 2748 fw.text_len = bnx_RXP_b09FwTextLen; 2749 fw.text_index = 0; 2750 fw.text = bnx_RXP_b09FwText; 2751 2752 fw.data_addr = bnx_RXP_b09FwDataAddr; 2753 fw.data_len = bnx_RXP_b09FwDataLen; 2754 fw.data_index = 0; 2755 fw.data = bnx_RXP_b09FwData; 2756 2757 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2758 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2759 fw.sbss_index = 0; 2760 fw.sbss = bnx_RXP_b09FwSbss; 2761 2762 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2763 fw.bss_len = bnx_RXP_b09FwBssLen; 2764 fw.bss_index = 0; 2765 fw.bss = bnx_RXP_b09FwBss; 2766 2767 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2768 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2769 fw.rodata_index = 0; 2770 fw.rodata = bnx_RXP_b09FwRodata; 2771 2772 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2773 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2774 2775 /* Initialize the TX Processor. */ 2776 cpu_reg.mode = BNX_TXP_CPU_MODE; 2777 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2778 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2779 cpu_reg.state = BNX_TXP_CPU_STATE; 2780 cpu_reg.state_value_clear = 0xffffff; 2781 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2782 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2783 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2784 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2785 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2786 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2787 cpu_reg.mips_view_base = 0x8000000; 2788 2789 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2790 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2791 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2792 fw.start_addr = bnx_TXP_b09FwStartAddr; 2793 2794 fw.text_addr = bnx_TXP_b09FwTextAddr; 2795 fw.text_len = bnx_TXP_b09FwTextLen; 2796 fw.text_index = 0; 2797 fw.text = bnx_TXP_b09FwText; 2798 2799 fw.data_addr = bnx_TXP_b09FwDataAddr; 2800 fw.data_len = bnx_TXP_b09FwDataLen; 2801 fw.data_index = 0; 2802 fw.data = bnx_TXP_b09FwData; 2803 2804 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2805 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2806 fw.sbss_index = 0; 2807 fw.sbss = bnx_TXP_b09FwSbss; 2808 2809 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2810 fw.bss_len = bnx_TXP_b09FwBssLen; 2811 fw.bss_index = 0; 2812 fw.bss = bnx_TXP_b09FwBss; 2813 2814 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2815 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2816 fw.rodata_index = 0; 2817 fw.rodata = bnx_TXP_b09FwRodata; 2818 2819 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2820 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2821 2822 /* Initialize the TX Patch-up Processor. */ 2823 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2824 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2825 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2826 cpu_reg.state = BNX_TPAT_CPU_STATE; 2827 cpu_reg.state_value_clear = 0xffffff; 2828 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2829 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2830 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2831 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2832 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2833 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2834 cpu_reg.mips_view_base = 0x8000000; 2835 2836 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2837 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2838 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2839 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2840 2841 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2842 fw.text_len = bnx_TPAT_b09FwTextLen; 2843 fw.text_index = 0; 2844 fw.text = bnx_TPAT_b09FwText; 2845 2846 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2847 fw.data_len = bnx_TPAT_b09FwDataLen; 2848 fw.data_index = 0; 2849 fw.data = bnx_TPAT_b09FwData; 2850 2851 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2852 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2853 fw.sbss_index = 0; 2854 fw.sbss = bnx_TPAT_b09FwSbss; 2855 2856 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2857 fw.bss_len = bnx_TPAT_b09FwBssLen; 2858 fw.bss_index = 0; 2859 fw.bss = bnx_TPAT_b09FwBss; 2860 2861 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2862 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2863 fw.rodata_index = 0; 2864 fw.rodata = bnx_TPAT_b09FwRodata; 2865 2866 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2867 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2868 2869 /* Initialize the Completion Processor. */ 2870 cpu_reg.mode = BNX_COM_CPU_MODE; 2871 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2872 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2873 cpu_reg.state = BNX_COM_CPU_STATE; 2874 cpu_reg.state_value_clear = 0xffffff; 2875 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2876 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2877 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2878 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2879 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2880 cpu_reg.spad_base = BNX_COM_SCRATCH; 2881 cpu_reg.mips_view_base = 0x8000000; 2882 2883 fw.ver_major = bnx_COM_b09FwReleaseMajor; 2884 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 2885 fw.ver_fix = bnx_COM_b09FwReleaseFix; 2886 fw.start_addr = bnx_COM_b09FwStartAddr; 2887 2888 fw.text_addr = bnx_COM_b09FwTextAddr; 2889 fw.text_len = bnx_COM_b09FwTextLen; 2890 fw.text_index = 0; 2891 fw.text = bnx_COM_b09FwText; 2892 2893 fw.data_addr = bnx_COM_b09FwDataAddr; 2894 fw.data_len = bnx_COM_b09FwDataLen; 2895 fw.data_index = 0; 2896 fw.data = bnx_COM_b09FwData; 2897 2898 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 2899 fw.sbss_len = bnx_COM_b09FwSbssLen; 2900 fw.sbss_index = 0; 2901 fw.sbss = bnx_COM_b09FwSbss; 2902 2903 fw.bss_addr = bnx_COM_b09FwBssAddr; 2904 fw.bss_len = bnx_COM_b09FwBssLen; 2905 fw.bss_index = 0; 2906 fw.bss = bnx_COM_b09FwBss; 2907 2908 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 2909 fw.rodata_len = bnx_COM_b09FwRodataLen; 2910 fw.rodata_index = 0; 2911 fw.rodata = bnx_COM_b09FwRodata; 2912 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2913 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2914 break; 2915 default: 2916 /* Initialize the RV2P processor. */ 2917 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2918 RV2P_PROC1); 2919 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2920 RV2P_PROC2); 2921 2922 /* Initialize the RX Processor. */ 2923 cpu_reg.mode = BNX_RXP_CPU_MODE; 2924 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2925 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2926 cpu_reg.state = BNX_RXP_CPU_STATE; 2927 cpu_reg.state_value_clear = 0xffffff; 2928 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2929 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2930 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2931 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2932 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2933 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2934 cpu_reg.mips_view_base = 0x8000000; 2935 2936 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2937 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2938 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2939 fw.start_addr = bnx_RXP_b06FwStartAddr; 2940 2941 fw.text_addr = bnx_RXP_b06FwTextAddr; 2942 fw.text_len = bnx_RXP_b06FwTextLen; 2943 fw.text_index = 0; 2944 fw.text = bnx_RXP_b06FwText; 2945 2946 fw.data_addr = bnx_RXP_b06FwDataAddr; 2947 fw.data_len = bnx_RXP_b06FwDataLen; 2948 fw.data_index = 0; 2949 fw.data = bnx_RXP_b06FwData; 2950 2951 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2952 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2953 fw.sbss_index = 0; 2954 fw.sbss = bnx_RXP_b06FwSbss; 2955 2956 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2957 fw.bss_len = bnx_RXP_b06FwBssLen; 2958 fw.bss_index = 0; 2959 fw.bss = bnx_RXP_b06FwBss; 2960 2961 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2962 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2963 fw.rodata_index = 0; 2964 fw.rodata = bnx_RXP_b06FwRodata; 2965 2966 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2967 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2968 2969 /* Initialize the TX Processor. */ 2970 cpu_reg.mode = BNX_TXP_CPU_MODE; 2971 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2972 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2973 cpu_reg.state = BNX_TXP_CPU_STATE; 2974 cpu_reg.state_value_clear = 0xffffff; 2975 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2976 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2977 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2978 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2979 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2980 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2981 cpu_reg.mips_view_base = 0x8000000; 2982 2983 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2984 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2985 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2986 fw.start_addr = bnx_TXP_b06FwStartAddr; 2987 2988 fw.text_addr = bnx_TXP_b06FwTextAddr; 2989 fw.text_len = bnx_TXP_b06FwTextLen; 2990 fw.text_index = 0; 2991 fw.text = bnx_TXP_b06FwText; 2992 2993 fw.data_addr = bnx_TXP_b06FwDataAddr; 2994 fw.data_len = bnx_TXP_b06FwDataLen; 2995 fw.data_index = 0; 2996 fw.data = bnx_TXP_b06FwData; 2997 2998 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2999 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3000 fw.sbss_index = 0; 3001 fw.sbss = bnx_TXP_b06FwSbss; 3002 3003 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3004 fw.bss_len = bnx_TXP_b06FwBssLen; 3005 fw.bss_index = 0; 3006 fw.bss = bnx_TXP_b06FwBss; 3007 3008 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3009 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3010 fw.rodata_index = 0; 3011 fw.rodata = bnx_TXP_b06FwRodata; 3012 3013 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3014 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3015 3016 /* Initialize the TX Patch-up Processor. */ 3017 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3018 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3019 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3020 cpu_reg.state = BNX_TPAT_CPU_STATE; 3021 cpu_reg.state_value_clear = 0xffffff; 3022 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3023 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3024 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3025 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3026 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3027 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3028 cpu_reg.mips_view_base = 0x8000000; 3029 3030 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3031 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3032 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3033 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3034 3035 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3036 fw.text_len = bnx_TPAT_b06FwTextLen; 3037 fw.text_index = 0; 3038 fw.text = bnx_TPAT_b06FwText; 3039 3040 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3041 fw.data_len = bnx_TPAT_b06FwDataLen; 3042 fw.data_index = 0; 3043 fw.data = bnx_TPAT_b06FwData; 3044 3045 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3046 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3047 fw.sbss_index = 0; 3048 fw.sbss = bnx_TPAT_b06FwSbss; 3049 3050 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3051 fw.bss_len = bnx_TPAT_b06FwBssLen; 3052 fw.bss_index = 0; 3053 fw.bss = bnx_TPAT_b06FwBss; 3054 3055 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3056 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3057 fw.rodata_index = 0; 3058 fw.rodata = bnx_TPAT_b06FwRodata; 3059 3060 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3061 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3062 3063 /* Initialize the Completion Processor. */ 3064 cpu_reg.mode = BNX_COM_CPU_MODE; 3065 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3066 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3067 cpu_reg.state = BNX_COM_CPU_STATE; 3068 cpu_reg.state_value_clear = 0xffffff; 3069 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3070 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3071 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3072 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3073 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3074 cpu_reg.spad_base = BNX_COM_SCRATCH; 3075 cpu_reg.mips_view_base = 0x8000000; 3076 3077 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3078 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3079 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3080 fw.start_addr = bnx_COM_b06FwStartAddr; 3081 3082 fw.text_addr = bnx_COM_b06FwTextAddr; 3083 fw.text_len = bnx_COM_b06FwTextLen; 3084 fw.text_index = 0; 3085 fw.text = bnx_COM_b06FwText; 3086 3087 fw.data_addr = bnx_COM_b06FwDataAddr; 3088 fw.data_len = bnx_COM_b06FwDataLen; 3089 fw.data_index = 0; 3090 fw.data = bnx_COM_b06FwData; 3091 3092 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3093 fw.sbss_len = bnx_COM_b06FwSbssLen; 3094 fw.sbss_index = 0; 3095 fw.sbss = bnx_COM_b06FwSbss; 3096 3097 fw.bss_addr = bnx_COM_b06FwBssAddr; 3098 fw.bss_len = bnx_COM_b06FwBssLen; 3099 fw.bss_index = 0; 3100 fw.bss = bnx_COM_b06FwBss; 3101 3102 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3103 fw.rodata_len = bnx_COM_b06FwRodataLen; 3104 fw.rodata_index = 0; 3105 fw.rodata = bnx_COM_b06FwRodata; 3106 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3107 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3108 break; 3109 } 3110 } 3111 3112 /****************************************************************************/ 3113 /* Initialize context memory. */ 3114 /* */ 3115 /* Clears the memory associated with each Context ID (CID). */ 3116 /* */ 3117 /* Returns: */ 3118 /* Nothing. */ 3119 /****************************************************************************/ 3120 void 3121 bnx_init_context(struct bnx_softc *sc) 3122 { 3123 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3124 /* DRC: Replace this constant value with a #define. */ 3125 int i, retry_cnt = 10; 3126 u_int32_t val; 3127 3128 /* 3129 * BCM5709 context memory may be cached 3130 * in host memory so prepare the host memory 3131 * for access. 3132 */ 3133 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3134 | (1 << 12); 3135 val |= (BCM_PAGE_BITS - 8) << 16; 3136 REG_WR(sc, BNX_CTX_COMMAND, val); 3137 3138 /* Wait for mem init command to complete. */ 3139 for (i = 0; i < retry_cnt; i++) { 3140 val = REG_RD(sc, BNX_CTX_COMMAND); 3141 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3142 break; 3143 DELAY(2); 3144 } 3145 3146 3147 /* ToDo: Consider returning an error here. */ 3148 3149 for (i = 0; i < sc->ctx_pages; i++) { 3150 int j; 3151 3152 3153 /* Set the physaddr of the context memory cache. */ 3154 val = (u_int32_t)(sc->ctx_segs[i].ds_addr); 3155 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3156 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3157 val = (u_int32_t) 3158 ((u_int64_t)sc->ctx_segs[i].ds_addr >> 32); 3159 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3160 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3161 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3162 3163 3164 /* Verify that the context memory write was successful. */ 3165 for (j = 0; j < retry_cnt; j++) { 3166 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3167 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3168 break; 3169 DELAY(5); 3170 } 3171 3172 /* ToDo: Consider returning an error here. */ 3173 } 3174 } else { 3175 u_int32_t vcid_addr, offset; 3176 3177 /* 3178 * For the 5706/5708, context memory is local to 3179 * the controller, so initialize the controller 3180 * context memory. 3181 */ 3182 3183 vcid_addr = GET_CID_ADDR(96); 3184 while (vcid_addr) { 3185 3186 vcid_addr -= BNX_PHY_CTX_SIZE; 3187 3188 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3189 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3190 3191 for(offset = 0; offset < BNX_PHY_CTX_SIZE; offset += 4) { 3192 CTX_WR(sc, 0x00, offset, 0); 3193 } 3194 3195 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3196 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3197 } 3198 } 3199 } 3200 3201 /****************************************************************************/ 3202 /* Fetch the permanent MAC address of the controller. */ 3203 /* */ 3204 /* Returns: */ 3205 /* Nothing. */ 3206 /****************************************************************************/ 3207 void 3208 bnx_get_mac_addr(struct bnx_softc *sc) 3209 { 3210 u_int32_t mac_lo = 0, mac_hi = 0; 3211 3212 /* 3213 * The NetXtreme II bootcode populates various NIC 3214 * power-on and runtime configuration items in a 3215 * shared memory area. The factory configured MAC 3216 * address is available from both NVRAM and the 3217 * shared memory area so we'll read the value from 3218 * shared memory for speed. 3219 */ 3220 3221 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3222 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3223 3224 if ((mac_lo == 0) && (mac_hi == 0)) { 3225 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3226 __FILE__, __LINE__); 3227 } else { 3228 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3229 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3230 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3231 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3232 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3233 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3234 } 3235 3236 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3237 "%s\n", ether_sprintf(sc->eaddr)); 3238 } 3239 3240 /****************************************************************************/ 3241 /* Program the MAC address. */ 3242 /* */ 3243 /* Returns: */ 3244 /* Nothing. */ 3245 /****************************************************************************/ 3246 void 3247 bnx_set_mac_addr(struct bnx_softc *sc) 3248 { 3249 u_int32_t val; 3250 const u_int8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3251 3252 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3253 "%s\n", ether_sprintf(sc->eaddr)); 3254 3255 val = (mac_addr[0] << 8) | mac_addr[1]; 3256 3257 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3258 3259 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3260 (mac_addr[4] << 8) | mac_addr[5]; 3261 3262 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3263 } 3264 3265 /****************************************************************************/ 3266 /* Stop the controller. */ 3267 /* */ 3268 /* Returns: */ 3269 /* Nothing. */ 3270 /****************************************************************************/ 3271 void 3272 bnx_stop(struct ifnet *ifp, int disable) 3273 { 3274 struct bnx_softc *sc = ifp->if_softc; 3275 3276 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3277 3278 if ((ifp->if_flags & IFF_RUNNING) == 0) 3279 return; 3280 3281 callout_stop(&sc->bnx_timeout); 3282 3283 mii_down(&sc->bnx_mii); 3284 3285 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3286 3287 /* Disable the transmit/receive blocks. */ 3288 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3289 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3290 DELAY(20); 3291 3292 bnx_disable_intr(sc); 3293 3294 /* Tell firmware that the driver is going away. */ 3295 if (disable) 3296 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3297 else 3298 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3299 3300 /* Free RX buffers. */ 3301 bnx_free_rx_chain(sc); 3302 3303 /* Free TX buffers. */ 3304 bnx_free_tx_chain(sc); 3305 3306 ifp->if_timer = 0; 3307 3308 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3309 3310 } 3311 3312 int 3313 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 3314 { 3315 struct pci_attach_args *pa = &(sc->bnx_pa); 3316 u_int32_t val; 3317 int i, rc = 0; 3318 3319 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3320 3321 /* Wait for pending PCI transactions to complete. */ 3322 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3323 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3324 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3325 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3326 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3327 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3328 DELAY(5); 3329 3330 /* Disable DMA */ 3331 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3332 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3333 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3334 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3335 } 3336 3337 /* Assume bootcode is running. */ 3338 sc->bnx_fw_timed_out = 0; 3339 3340 /* Give the firmware a chance to prepare for the reset. */ 3341 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3342 if (rc) 3343 goto bnx_reset_exit; 3344 3345 /* Set a firmware reminder that this is a soft reset. */ 3346 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3347 BNX_DRV_RESET_SIGNATURE_MAGIC); 3348 3349 /* Dummy read to force the chip to complete all current transactions. */ 3350 val = REG_RD(sc, BNX_MISC_ID); 3351 3352 /* Chip reset. */ 3353 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3354 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3355 REG_RD(sc, BNX_MISC_COMMAND); 3356 DELAY(5); 3357 3358 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3359 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3360 3361 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3362 val); 3363 } else { 3364 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3365 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3366 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3367 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3368 3369 /* Allow up to 30us for reset to complete. */ 3370 for (i = 0; i < 10; i++) { 3371 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3372 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3373 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3374 break; 3375 } 3376 DELAY(10); 3377 } 3378 3379 /* Check that reset completed successfully. */ 3380 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3381 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3382 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3383 __FILE__, __LINE__); 3384 rc = EBUSY; 3385 goto bnx_reset_exit; 3386 } 3387 } 3388 3389 /* Make sure byte swapping is properly configured. */ 3390 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3391 if (val != 0x01020304) { 3392 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3393 __FILE__, __LINE__); 3394 rc = ENODEV; 3395 goto bnx_reset_exit; 3396 } 3397 3398 /* Just completed a reset, assume that firmware is running again. */ 3399 sc->bnx_fw_timed_out = 0; 3400 3401 /* Wait for the firmware to finish its initialization. */ 3402 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3403 if (rc) 3404 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3405 "initialization!\n", __FILE__, __LINE__); 3406 3407 bnx_reset_exit: 3408 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3409 3410 return (rc); 3411 } 3412 3413 int 3414 bnx_chipinit(struct bnx_softc *sc) 3415 { 3416 struct pci_attach_args *pa = &(sc->bnx_pa); 3417 u_int32_t val; 3418 int rc = 0; 3419 3420 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3421 3422 /* Make sure the interrupt is not active. */ 3423 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3424 3425 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3426 /* channels and PCI clock compensation delay. */ 3427 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3428 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3429 #if BYTE_ORDER == BIG_ENDIAN 3430 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3431 #endif 3432 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3433 DMA_READ_CHANS << 12 | 3434 DMA_WRITE_CHANS << 16; 3435 3436 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3437 3438 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3439 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3440 3441 /* 3442 * This setting resolves a problem observed on certain Intel PCI 3443 * chipsets that cannot handle multiple outstanding DMA operations. 3444 * See errata E9_5706A1_65. 3445 */ 3446 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3447 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3448 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3449 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3450 3451 REG_WR(sc, BNX_DMA_CONFIG, val); 3452 3453 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3454 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3455 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3456 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3457 val & ~0x20000); 3458 } 3459 3460 /* Enable the RX_V2P and Context state machines before access. */ 3461 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3462 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3463 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3464 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3465 3466 /* Initialize context mapping and zero out the quick contexts. */ 3467 bnx_init_context(sc); 3468 3469 /* Initialize the on-boards CPUs */ 3470 bnx_init_cpus(sc); 3471 3472 /* Prepare NVRAM for access. */ 3473 if (bnx_init_nvram(sc)) { 3474 rc = ENODEV; 3475 goto bnx_chipinit_exit; 3476 } 3477 3478 /* Set the kernel bypass block size */ 3479 val = REG_RD(sc, BNX_MQ_CONFIG); 3480 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3481 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3482 3483 /* Enable bins used on the 5709. */ 3484 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3485 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3486 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3487 val |= BNX_MQ_CONFIG_HALT_DIS; 3488 } 3489 3490 REG_WR(sc, BNX_MQ_CONFIG, val); 3491 3492 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3493 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3494 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3495 3496 val = (BCM_PAGE_BITS - 8) << 24; 3497 REG_WR(sc, BNX_RV2P_CONFIG, val); 3498 3499 /* Configure page size. */ 3500 val = REG_RD(sc, BNX_TBDR_CONFIG); 3501 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3502 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3503 REG_WR(sc, BNX_TBDR_CONFIG, val); 3504 3505 #if 0 3506 /* Set the perfect match control register to default. */ 3507 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3508 #endif 3509 3510 bnx_chipinit_exit: 3511 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3512 3513 return(rc); 3514 } 3515 3516 /****************************************************************************/ 3517 /* Initialize the controller in preparation to send/receive traffic. */ 3518 /* */ 3519 /* Returns: */ 3520 /* 0 for success, positive value for failure. */ 3521 /****************************************************************************/ 3522 int 3523 bnx_blockinit(struct bnx_softc *sc) 3524 { 3525 u_int32_t reg, val; 3526 int rc = 0; 3527 3528 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3529 3530 /* Load the hardware default MAC address. */ 3531 bnx_set_mac_addr(sc); 3532 3533 /* Set the Ethernet backoff seed value */ 3534 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3535 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3536 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3537 3538 sc->last_status_idx = 0; 3539 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3540 3541 /* Set up link change interrupt generation. */ 3542 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3543 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3544 3545 /* Program the physical address of the status block. */ 3546 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 3547 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3548 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 3549 3550 /* Program the physical address of the statistics block. */ 3551 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3552 (u_int32_t)(sc->stats_block_paddr)); 3553 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3554 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 3555 3556 /* Program various host coalescing parameters. */ 3557 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3558 << 16) | sc->bnx_tx_quick_cons_trip); 3559 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3560 << 16) | sc->bnx_rx_quick_cons_trip); 3561 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3562 sc->bnx_comp_prod_trip); 3563 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3564 sc->bnx_tx_ticks); 3565 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3566 sc->bnx_rx_ticks); 3567 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3568 sc->bnx_com_ticks); 3569 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3570 sc->bnx_cmd_ticks); 3571 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3572 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3573 REG_WR(sc, BNX_HC_CONFIG, 3574 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3575 BNX_HC_CONFIG_COLLECT_STATS)); 3576 3577 /* Clear the internal statistics counters. */ 3578 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3579 3580 /* Verify that bootcode is running. */ 3581 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3582 3583 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3584 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3585 __FILE__, __LINE__); reg = 0); 3586 3587 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3588 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3589 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3590 "Expected: 08%08X\n", __FILE__, __LINE__, 3591 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3592 BNX_DEV_INFO_SIGNATURE_MAGIC); 3593 rc = ENODEV; 3594 goto bnx_blockinit_exit; 3595 } 3596 3597 /* Check if any management firmware is running. */ 3598 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3599 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3600 BNX_PORT_FEATURE_IMD_ENABLED)) { 3601 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3602 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3603 } 3604 3605 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3606 BNX_DEV_INFO_BC_REV); 3607 3608 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3609 3610 /* Enable DMA */ 3611 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3612 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3613 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3614 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3615 } 3616 3617 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3618 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3619 3620 /* Enable link state change interrupt generation. */ 3621 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3622 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3623 BNX_MISC_ENABLE_DEFAULT_XI); 3624 } else 3625 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3626 3627 /* Enable all remaining blocks in the MAC. */ 3628 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3629 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3630 DELAY(20); 3631 3632 bnx_blockinit_exit: 3633 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3634 3635 return (rc); 3636 } 3637 3638 static int 3639 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, u_int16_t *prod, 3640 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3641 { 3642 bus_dmamap_t map; 3643 struct rx_bd *rxbd; 3644 u_int32_t addr; 3645 int i; 3646 #ifdef BNX_DEBUG 3647 u_int16_t debug_chain_prod = *chain_prod; 3648 #endif 3649 u_int16_t first_chain_prod; 3650 3651 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3652 3653 /* Map the mbuf cluster into device memory. */ 3654 map = sc->rx_mbuf_map[*chain_prod]; 3655 first_chain_prod = *chain_prod; 3656 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3657 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3658 __FILE__, __LINE__); 3659 3660 m_freem(m_new); 3661 3662 DBRUNIF(1, sc->rx_mbuf_alloc--); 3663 3664 return ENOBUFS; 3665 } 3666 /* Make sure there is room in the receive chain. */ 3667 if (map->dm_nsegs > sc->free_rx_bd) { 3668 bus_dmamap_unload(sc->bnx_dmatag, map); 3669 m_freem(m_new); 3670 return EFBIG; 3671 } 3672 #ifdef BNX_DEBUG 3673 /* Track the distribution of buffer segments. */ 3674 sc->rx_mbuf_segs[map->dm_nsegs]++; 3675 #endif 3676 3677 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3678 BUS_DMASYNC_PREREAD); 3679 3680 /* Update some debug statistics counters */ 3681 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3682 sc->rx_low_watermark = sc->free_rx_bd); 3683 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3684 3685 /* 3686 * Setup the rx_bd for the first segment 3687 */ 3688 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3689 3690 addr = (u_int32_t)map->dm_segs[0].ds_addr; 3691 rxbd->rx_bd_haddr_lo = addr; 3692 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3693 rxbd->rx_bd_haddr_hi = addr; 3694 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3695 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3696 *prod_bseq += map->dm_segs[0].ds_len; 3697 bus_dmamap_sync(sc->bnx_dmatag, 3698 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3699 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3700 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3701 3702 for (i = 1; i < map->dm_nsegs; i++) { 3703 *prod = NEXT_RX_BD(*prod); 3704 *chain_prod = RX_CHAIN_IDX(*prod); 3705 3706 rxbd = 3707 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3708 3709 addr = (u_int32_t)map->dm_segs[i].ds_addr; 3710 rxbd->rx_bd_haddr_lo = addr; 3711 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3712 rxbd->rx_bd_haddr_hi = addr; 3713 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3714 rxbd->rx_bd_flags = 0; 3715 *prod_bseq += map->dm_segs[i].ds_len; 3716 bus_dmamap_sync(sc->bnx_dmatag, 3717 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3718 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3719 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3720 } 3721 3722 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3723 bus_dmamap_sync(sc->bnx_dmatag, 3724 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3725 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3726 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3727 3728 /* 3729 * Save the mbuf, ajust the map pointer (swap map for first and 3730 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3731 * and update counter. 3732 */ 3733 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3734 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3735 sc->rx_mbuf_map[*chain_prod] = map; 3736 sc->free_rx_bd -= map->dm_nsegs; 3737 3738 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3739 map->dm_nsegs)); 3740 *prod = NEXT_RX_BD(*prod); 3741 *chain_prod = RX_CHAIN_IDX(*prod); 3742 3743 return 0; 3744 } 3745 3746 /****************************************************************************/ 3747 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3748 /* */ 3749 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3750 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3751 /* necessary. */ 3752 /* */ 3753 /* Returns: */ 3754 /* 0 for success, positive value for failure. */ 3755 /****************************************************************************/ 3756 int 3757 bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, 3758 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3759 { 3760 struct mbuf *m_new = NULL; 3761 int rc = 0; 3762 u_int16_t min_free_bd; 3763 3764 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3765 __func__); 3766 3767 /* Make sure the inputs are valid. */ 3768 DBRUNIF((*chain_prod > MAX_RX_BD), 3769 aprint_error_dev(sc->bnx_dev, 3770 "RX producer out of range: 0x%04X > 0x%04X\n", 3771 *chain_prod, (u_int16_t)MAX_RX_BD)); 3772 3773 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3774 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3775 *prod_bseq); 3776 3777 /* try to get in as many mbufs as possible */ 3778 if (sc->mbuf_alloc_size == MCLBYTES) 3779 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3780 else 3781 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3782 while (sc->free_rx_bd >= min_free_bd) { 3783 /* Simulate an mbuf allocation failure. */ 3784 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3785 aprint_error_dev(sc->bnx_dev, 3786 "Simulating mbuf allocation failure.\n"); 3787 sc->mbuf_sim_alloc_failed++; 3788 rc = ENOBUFS; 3789 goto bnx_get_buf_exit); 3790 3791 /* This is a new mbuf allocation. */ 3792 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3793 if (m_new == NULL) { 3794 DBPRINT(sc, BNX_WARN, 3795 "%s(%d): RX mbuf header allocation failed!\n", 3796 __FILE__, __LINE__); 3797 3798 sc->mbuf_alloc_failed++; 3799 3800 rc = ENOBUFS; 3801 goto bnx_get_buf_exit; 3802 } 3803 3804 DBRUNIF(1, sc->rx_mbuf_alloc++); 3805 3806 /* Simulate an mbuf cluster allocation failure. */ 3807 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3808 m_freem(m_new); 3809 sc->rx_mbuf_alloc--; 3810 sc->mbuf_alloc_failed++; 3811 sc->mbuf_sim_alloc_failed++; 3812 rc = ENOBUFS; 3813 goto bnx_get_buf_exit); 3814 3815 if (sc->mbuf_alloc_size == MCLBYTES) 3816 MCLGET(m_new, M_DONTWAIT); 3817 else 3818 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3819 M_DONTWAIT); 3820 if (!(m_new->m_flags & M_EXT)) { 3821 DBPRINT(sc, BNX_WARN, 3822 "%s(%d): RX mbuf chain allocation failed!\n", 3823 __FILE__, __LINE__); 3824 3825 m_freem(m_new); 3826 3827 DBRUNIF(1, sc->rx_mbuf_alloc--); 3828 sc->mbuf_alloc_failed++; 3829 3830 rc = ENOBUFS; 3831 goto bnx_get_buf_exit; 3832 } 3833 3834 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3835 if (rc != 0) 3836 goto bnx_get_buf_exit; 3837 } 3838 3839 bnx_get_buf_exit: 3840 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3841 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3842 *chain_prod, *prod_bseq); 3843 3844 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3845 __func__); 3846 3847 return(rc); 3848 } 3849 3850 void 3851 bnx_alloc_pkts(struct work * unused, void * arg) 3852 { 3853 struct bnx_softc *sc = arg; 3854 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3855 struct bnx_pkt *pkt; 3856 int i, s; 3857 3858 for (i = 0; i < 4; i++) { /* magic! */ 3859 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 3860 if (pkt == NULL) 3861 break; 3862 3863 if (bus_dmamap_create(sc->bnx_dmatag, 3864 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3865 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3866 &pkt->pkt_dmamap) != 0) 3867 goto put; 3868 3869 if (!ISSET(ifp->if_flags, IFF_UP)) 3870 goto stopping; 3871 3872 mutex_enter(&sc->tx_pkt_mtx); 3873 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3874 sc->tx_pkt_count++; 3875 mutex_exit(&sc->tx_pkt_mtx); 3876 } 3877 3878 mutex_enter(&sc->tx_pkt_mtx); 3879 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 3880 mutex_exit(&sc->tx_pkt_mtx); 3881 3882 /* fire-up TX now that allocations have been done */ 3883 s = splnet(); 3884 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3885 bnx_start(ifp); 3886 splx(s); 3887 3888 return; 3889 3890 stopping: 3891 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3892 put: 3893 pool_put(bnx_tx_pool, pkt); 3894 return; 3895 } 3896 3897 /****************************************************************************/ 3898 /* Initialize the TX context memory. */ 3899 /* */ 3900 /* Returns: */ 3901 /* Nothing */ 3902 /****************************************************************************/ 3903 void 3904 bnx_init_tx_context(struct bnx_softc *sc) 3905 { 3906 u_int32_t val; 3907 3908 /* Initialize the context ID for an L2 TX chain. */ 3909 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3910 /* Set the CID type to support an L2 connection. */ 3911 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3912 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 3913 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3914 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 3915 3916 /* Point the hardware to the first page in the chain. */ 3917 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3918 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3919 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 3920 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3921 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3922 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 3923 } else { 3924 /* Set the CID type to support an L2 connection. */ 3925 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3926 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3927 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3928 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3929 3930 /* Point the hardware to the first page in the chain. */ 3931 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3932 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3933 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3934 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3935 } 3936 } 3937 3938 3939 /****************************************************************************/ 3940 /* Allocate memory and initialize the TX data structures. */ 3941 /* */ 3942 /* Returns: */ 3943 /* 0 for success, positive value for failure. */ 3944 /****************************************************************************/ 3945 int 3946 bnx_init_tx_chain(struct bnx_softc *sc) 3947 { 3948 struct tx_bd *txbd; 3949 u_int32_t addr; 3950 int i, rc = 0; 3951 3952 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3953 3954 /* Force an allocation of some dmamaps for tx up front */ 3955 bnx_alloc_pkts(NULL, sc); 3956 3957 /* Set the initial TX producer/consumer indices. */ 3958 sc->tx_prod = 0; 3959 sc->tx_cons = 0; 3960 sc->tx_prod_bseq = 0; 3961 sc->used_tx_bd = 0; 3962 sc->max_tx_bd = USABLE_TX_BD; 3963 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3964 DBRUNIF(1, sc->tx_full_count = 0); 3965 3966 /* 3967 * The NetXtreme II supports a linked-list structure called 3968 * a Buffer Descriptor Chain (or BD chain). A BD chain 3969 * consists of a series of 1 or more chain pages, each of which 3970 * consists of a fixed number of BD entries. 3971 * The last BD entry on each page is a pointer to the next page 3972 * in the chain, and the last pointer in the BD chain 3973 * points back to the beginning of the chain. 3974 */ 3975 3976 /* Set the TX next pointer chain entries. */ 3977 for (i = 0; i < TX_PAGES; i++) { 3978 int j; 3979 3980 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3981 3982 /* Check if we've reached the last page. */ 3983 if (i == (TX_PAGES - 1)) 3984 j = 0; 3985 else 3986 j = i + 1; 3987 3988 addr = (u_int32_t)sc->tx_bd_chain_paddr[j]; 3989 txbd->tx_bd_haddr_lo = addr; 3990 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3991 txbd->tx_bd_haddr_hi = addr; 3992 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3993 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3994 } 3995 3996 /* 3997 * Initialize the context ID for an L2 TX chain. 3998 */ 3999 bnx_init_tx_context(sc); 4000 4001 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4002 4003 return(rc); 4004 } 4005 4006 /****************************************************************************/ 4007 /* Free memory and clear the TX data structures. */ 4008 /* */ 4009 /* Returns: */ 4010 /* Nothing. */ 4011 /****************************************************************************/ 4012 void 4013 bnx_free_tx_chain(struct bnx_softc *sc) 4014 { 4015 struct bnx_pkt *pkt; 4016 int i; 4017 4018 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4019 4020 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4021 mutex_enter(&sc->tx_pkt_mtx); 4022 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4023 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4024 mutex_exit(&sc->tx_pkt_mtx); 4025 4026 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4027 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4028 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4029 4030 m_freem(pkt->pkt_mbuf); 4031 DBRUNIF(1, sc->tx_mbuf_alloc--); 4032 4033 mutex_enter(&sc->tx_pkt_mtx); 4034 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4035 } 4036 4037 /* Destroy all the dmamaps we allocated for TX */ 4038 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4039 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4040 sc->tx_pkt_count--; 4041 mutex_exit(&sc->tx_pkt_mtx); 4042 4043 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4044 pool_put(bnx_tx_pool, pkt); 4045 4046 mutex_enter(&sc->tx_pkt_mtx); 4047 } 4048 mutex_exit(&sc->tx_pkt_mtx); 4049 4050 4051 4052 /* Clear each TX chain page. */ 4053 for (i = 0; i < TX_PAGES; i++) { 4054 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4055 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4056 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4057 } 4058 4059 sc->used_tx_bd = 0; 4060 4061 /* Check if we lost any mbufs in the process. */ 4062 DBRUNIF((sc->tx_mbuf_alloc), 4063 aprint_error_dev(sc->bnx_dev, 4064 "Memory leak! Lost %d mbufs from tx chain!\n", 4065 sc->tx_mbuf_alloc)); 4066 4067 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4068 } 4069 4070 /****************************************************************************/ 4071 /* Initialize the RX context memory. */ 4072 /* */ 4073 /* Returns: */ 4074 /* Nothing */ 4075 /****************************************************************************/ 4076 void 4077 bnx_init_rx_context(struct bnx_softc *sc) 4078 { 4079 u_int32_t val; 4080 4081 /* Initialize the context ID for an L2 RX chain. */ 4082 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4083 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4084 4085 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4086 u_int32_t lo_water, hi_water; 4087 4088 lo_water = BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT; 4089 hi_water = USABLE_RX_BD / 4; 4090 4091 lo_water /= BNX_L2CTX_RX_LO_WATER_MARK_SCALE; 4092 hi_water /= BNX_L2CTX_RX_HI_WATER_MARK_SCALE; 4093 4094 if (hi_water > 0xf) 4095 hi_water = 0xf; 4096 else if (hi_water == 0) 4097 lo_water = 0; 4098 val |= lo_water | 4099 (hi_water << BNX_L2CTX_RX_HI_WATER_MARK_SHIFT); 4100 } 4101 4102 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4103 4104 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4105 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4106 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4107 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4108 } 4109 4110 /* Point the hardware to the first page in the chain. */ 4111 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 4112 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4113 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 4114 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4115 } 4116 4117 /****************************************************************************/ 4118 /* Allocate memory and initialize the RX data structures. */ 4119 /* */ 4120 /* Returns: */ 4121 /* 0 for success, positive value for failure. */ 4122 /****************************************************************************/ 4123 int 4124 bnx_init_rx_chain(struct bnx_softc *sc) 4125 { 4126 struct rx_bd *rxbd; 4127 int i, rc = 0; 4128 u_int16_t prod, chain_prod; 4129 u_int32_t prod_bseq, addr; 4130 4131 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4132 4133 /* Initialize the RX producer and consumer indices. */ 4134 sc->rx_prod = 0; 4135 sc->rx_cons = 0; 4136 sc->rx_prod_bseq = 0; 4137 sc->free_rx_bd = USABLE_RX_BD; 4138 sc->max_rx_bd = USABLE_RX_BD; 4139 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4140 DBRUNIF(1, sc->rx_empty_count = 0); 4141 4142 /* Initialize the RX next pointer chain entries. */ 4143 for (i = 0; i < RX_PAGES; i++) { 4144 int j; 4145 4146 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4147 4148 /* Check if we've reached the last page. */ 4149 if (i == (RX_PAGES - 1)) 4150 j = 0; 4151 else 4152 j = i + 1; 4153 4154 /* Setup the chain page pointers. */ 4155 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 4156 rxbd->rx_bd_haddr_hi = addr; 4157 addr = (u_int32_t)sc->rx_bd_chain_paddr[j]; 4158 rxbd->rx_bd_haddr_lo = addr; 4159 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4160 0, BNX_RX_CHAIN_PAGE_SZ, 4161 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4162 } 4163 4164 /* Allocate mbuf clusters for the rx_bd chain. */ 4165 prod = prod_bseq = 0; 4166 chain_prod = RX_CHAIN_IDX(prod); 4167 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4168 BNX_PRINTF(sc, 4169 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4170 } 4171 4172 /* Save the RX chain producer index. */ 4173 sc->rx_prod = prod; 4174 sc->rx_prod_bseq = prod_bseq; 4175 4176 for (i = 0; i < RX_PAGES; i++) 4177 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4178 sc->rx_bd_chain_map[i]->dm_mapsize, 4179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4180 4181 /* Tell the chip about the waiting rx_bd's. */ 4182 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4183 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4184 4185 bnx_init_rx_context(sc); 4186 4187 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4188 4189 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4190 4191 return(rc); 4192 } 4193 4194 /****************************************************************************/ 4195 /* Free memory and clear the RX data structures. */ 4196 /* */ 4197 /* Returns: */ 4198 /* Nothing. */ 4199 /****************************************************************************/ 4200 void 4201 bnx_free_rx_chain(struct bnx_softc *sc) 4202 { 4203 int i; 4204 4205 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4206 4207 /* Free any mbufs still in the RX mbuf chain. */ 4208 for (i = 0; i < TOTAL_RX_BD; i++) { 4209 if (sc->rx_mbuf_ptr[i] != NULL) { 4210 if (sc->rx_mbuf_map[i] != NULL) { 4211 bus_dmamap_sync(sc->bnx_dmatag, 4212 sc->rx_mbuf_map[i], 0, 4213 sc->rx_mbuf_map[i]->dm_mapsize, 4214 BUS_DMASYNC_POSTREAD); 4215 bus_dmamap_unload(sc->bnx_dmatag, 4216 sc->rx_mbuf_map[i]); 4217 } 4218 m_freem(sc->rx_mbuf_ptr[i]); 4219 sc->rx_mbuf_ptr[i] = NULL; 4220 DBRUNIF(1, sc->rx_mbuf_alloc--); 4221 } 4222 } 4223 4224 /* Clear each RX chain page. */ 4225 for (i = 0; i < RX_PAGES; i++) 4226 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4227 4228 sc->free_rx_bd = sc->max_rx_bd; 4229 4230 /* Check if we lost any mbufs in the process. */ 4231 DBRUNIF((sc->rx_mbuf_alloc), 4232 aprint_error_dev(sc->bnx_dev, 4233 "Memory leak! Lost %d mbufs from rx chain!\n", 4234 sc->rx_mbuf_alloc)); 4235 4236 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4237 } 4238 4239 /****************************************************************************/ 4240 /* Handles PHY generated interrupt events. */ 4241 /* */ 4242 /* Returns: */ 4243 /* Nothing. */ 4244 /****************************************************************************/ 4245 void 4246 bnx_phy_intr(struct bnx_softc *sc) 4247 { 4248 u_int32_t new_link_state, old_link_state; 4249 4250 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4251 BUS_DMASYNC_POSTREAD); 4252 new_link_state = sc->status_block->status_attn_bits & 4253 STATUS_ATTN_BITS_LINK_STATE; 4254 old_link_state = sc->status_block->status_attn_bits_ack & 4255 STATUS_ATTN_BITS_LINK_STATE; 4256 4257 /* Handle any changes if the link state has changed. */ 4258 if (new_link_state != old_link_state) { 4259 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4260 4261 callout_stop(&sc->bnx_timeout); 4262 bnx_tick(sc); 4263 4264 /* Update the status_attn_bits_ack field in the status block. */ 4265 if (new_link_state) { 4266 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4267 STATUS_ATTN_BITS_LINK_STATE); 4268 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4269 } else { 4270 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4271 STATUS_ATTN_BITS_LINK_STATE); 4272 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4273 } 4274 } 4275 4276 /* Acknowledge the link change interrupt. */ 4277 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4278 } 4279 4280 /****************************************************************************/ 4281 /* Handles received frame interrupt events. */ 4282 /* */ 4283 /* Returns: */ 4284 /* Nothing. */ 4285 /****************************************************************************/ 4286 void 4287 bnx_rx_intr(struct bnx_softc *sc) 4288 { 4289 struct status_block *sblk = sc->status_block; 4290 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4291 u_int16_t hw_cons, sw_cons, sw_chain_cons; 4292 u_int16_t sw_prod, sw_chain_prod; 4293 u_int32_t sw_prod_bseq; 4294 struct l2_fhdr *l2fhdr; 4295 int i; 4296 4297 DBRUNIF(1, sc->rx_interrupts++); 4298 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4299 BUS_DMASYNC_POSTREAD); 4300 4301 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4302 for (i = 0; i < RX_PAGES; i++) 4303 bus_dmamap_sync(sc->bnx_dmatag, 4304 sc->rx_bd_chain_map[i], 0, 4305 sc->rx_bd_chain_map[i]->dm_mapsize, 4306 BUS_DMASYNC_POSTWRITE); 4307 4308 /* Get the hardware's view of the RX consumer index. */ 4309 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4310 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4311 hw_cons++; 4312 4313 /* Get working copies of the driver's view of the RX indices. */ 4314 sw_cons = sc->rx_cons; 4315 sw_prod = sc->rx_prod; 4316 sw_prod_bseq = sc->rx_prod_bseq; 4317 4318 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4319 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4320 __func__, sw_prod, sw_cons, sw_prod_bseq); 4321 4322 /* Prevent speculative reads from getting ahead of the status block. */ 4323 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4324 BUS_SPACE_BARRIER_READ); 4325 4326 /* Update some debug statistics counters */ 4327 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4328 sc->rx_low_watermark = sc->free_rx_bd); 4329 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4330 4331 /* 4332 * Scan through the receive chain as long 4333 * as there is work to do. 4334 */ 4335 while (sw_cons != hw_cons) { 4336 struct mbuf *m; 4337 struct rx_bd *rxbd; 4338 unsigned int len; 4339 u_int32_t status; 4340 4341 /* Convert the producer/consumer indices to an actual 4342 * rx_bd index. 4343 */ 4344 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4345 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4346 4347 /* Get the used rx_bd. */ 4348 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4349 sc->free_rx_bd++; 4350 4351 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4352 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4353 4354 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4355 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4356 #ifdef DIAGNOSTIC 4357 /* Validate that this is the last rx_bd. */ 4358 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4359 printf("%s: Unexpected mbuf found in " 4360 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4361 sw_chain_cons); 4362 } 4363 #endif 4364 4365 /* DRC - ToDo: If the received packet is small, say less 4366 * than 128 bytes, allocate a new mbuf here, 4367 * copy the data to that mbuf, and recycle 4368 * the mapped jumbo frame. 4369 */ 4370 4371 /* Unmap the mbuf from DMA space. */ 4372 #ifdef DIAGNOSTIC 4373 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4374 printf("invalid map sw_cons 0x%x " 4375 "sw_prod 0x%x " 4376 "sw_chain_cons 0x%x " 4377 "sw_chain_prod 0x%x " 4378 "hw_cons 0x%x " 4379 "TOTAL_RX_BD_PER_PAGE 0x%x " 4380 "TOTAL_RX_BD 0x%x\n", 4381 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4382 hw_cons, 4383 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4384 } 4385 #endif 4386 bus_dmamap_sync(sc->bnx_dmatag, 4387 sc->rx_mbuf_map[sw_chain_cons], 0, 4388 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4389 BUS_DMASYNC_POSTREAD); 4390 bus_dmamap_unload(sc->bnx_dmatag, 4391 sc->rx_mbuf_map[sw_chain_cons]); 4392 4393 /* Remove the mbuf from the driver's chain. */ 4394 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4395 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4396 4397 /* 4398 * Frames received on the NetXteme II are prepended 4399 * with the l2_fhdr structure which provides status 4400 * information about the received frame (including 4401 * VLAN tags and checksum info) and are also 4402 * automatically adjusted to align the IP header 4403 * (i.e. two null bytes are inserted before the 4404 * Ethernet header). 4405 */ 4406 l2fhdr = mtod(m, struct l2_fhdr *); 4407 4408 len = l2fhdr->l2_fhdr_pkt_len; 4409 status = l2fhdr->l2_fhdr_status; 4410 4411 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4412 aprint_error("Simulating l2_fhdr status error.\n"); 4413 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4414 4415 /* Watch for unusual sized frames. */ 4416 DBRUNIF(((len < BNX_MIN_MTU) || 4417 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4418 aprint_error_dev(sc->bnx_dev, 4419 "Unusual frame size found. " 4420 "Min(%d), Actual(%d), Max(%d)\n", 4421 (int)BNX_MIN_MTU, len, 4422 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4423 4424 bnx_dump_mbuf(sc, m); 4425 bnx_breakpoint(sc)); 4426 4427 len -= ETHER_CRC_LEN; 4428 4429 /* Check the received frame for errors. */ 4430 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4431 L2_FHDR_ERRORS_PHY_DECODE | 4432 L2_FHDR_ERRORS_ALIGNMENT | 4433 L2_FHDR_ERRORS_TOO_SHORT | 4434 L2_FHDR_ERRORS_GIANT_FRAME)) || 4435 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4436 len > 4437 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4438 ifp->if_ierrors++; 4439 DBRUNIF(1, sc->l2fhdr_status_errors++); 4440 4441 /* Reuse the mbuf for a new frame. */ 4442 if (bnx_add_buf(sc, m, &sw_prod, 4443 &sw_chain_prod, &sw_prod_bseq)) { 4444 DBRUNIF(1, bnx_breakpoint(sc)); 4445 panic("%s: Can't reuse RX mbuf!\n", 4446 device_xname(sc->bnx_dev)); 4447 } 4448 continue; 4449 } 4450 4451 /* 4452 * Get a new mbuf for the rx_bd. If no new 4453 * mbufs are available then reuse the current mbuf, 4454 * log an ierror on the interface, and generate 4455 * an error in the system log. 4456 */ 4457 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4458 &sw_prod_bseq)) { 4459 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4460 "Failed to allocate " 4461 "new mbuf, incoming frame dropped!\n")); 4462 4463 ifp->if_ierrors++; 4464 4465 /* Try and reuse the exisitng mbuf. */ 4466 if (bnx_add_buf(sc, m, &sw_prod, 4467 &sw_chain_prod, &sw_prod_bseq)) { 4468 DBRUNIF(1, bnx_breakpoint(sc)); 4469 panic("%s: Double mbuf allocation " 4470 "failure!", 4471 device_xname(sc->bnx_dev)); 4472 } 4473 continue; 4474 } 4475 4476 /* Skip over the l2_fhdr when passing the data up 4477 * the stack. 4478 */ 4479 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4480 4481 /* Adjust the pckt length to match the received data. */ 4482 m->m_pkthdr.len = m->m_len = len; 4483 4484 /* Send the packet to the appropriate interface. */ 4485 m->m_pkthdr.rcvif = ifp; 4486 4487 DBRUN(BNX_VERBOSE_RECV, 4488 struct ether_header *eh; 4489 eh = mtod(m, struct ether_header *); 4490 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4491 __func__, ether_sprintf(eh->ether_dhost), 4492 ether_sprintf(eh->ether_shost), 4493 htons(eh->ether_type))); 4494 4495 /* Validate the checksum. */ 4496 4497 /* Check for an IP datagram. */ 4498 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4499 /* Check if the IP checksum is valid. */ 4500 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 4501 == 0) 4502 m->m_pkthdr.csum_flags |= 4503 M_CSUM_IPv4; 4504 #ifdef BNX_DEBUG 4505 else 4506 DBPRINT(sc, BNX_WARN_SEND, 4507 "%s(): Invalid IP checksum " 4508 "= 0x%04X!\n", 4509 __func__, 4510 l2fhdr->l2_fhdr_ip_xsum 4511 ); 4512 #endif 4513 } 4514 4515 /* Check for a valid TCP/UDP frame. */ 4516 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4517 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4518 /* Check for a good TCP/UDP checksum. */ 4519 if ((status & 4520 (L2_FHDR_ERRORS_TCP_XSUM | 4521 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4522 m->m_pkthdr.csum_flags |= 4523 M_CSUM_TCPv4 | 4524 M_CSUM_UDPv4; 4525 } else { 4526 DBPRINT(sc, BNX_WARN_SEND, 4527 "%s(): Invalid TCP/UDP " 4528 "checksum = 0x%04X!\n", 4529 __func__, 4530 l2fhdr->l2_fhdr_tcp_udp_xsum); 4531 } 4532 } 4533 4534 /* 4535 * If we received a packet with a vlan tag, 4536 * attach that information to the packet. 4537 */ 4538 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4539 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4540 VLAN_INPUT_TAG(ifp, m, 4541 l2fhdr->l2_fhdr_vlan_tag, 4542 continue); 4543 } 4544 4545 /* 4546 * Handle BPF listeners. Let the BPF 4547 * user see the packet. 4548 */ 4549 bpf_mtap(ifp, m); 4550 4551 /* Pass the mbuf off to the upper layers. */ 4552 ifp->if_ipackets++; 4553 DBPRINT(sc, BNX_VERBOSE_RECV, 4554 "%s(): Passing received frame up.\n", __func__); 4555 (*ifp->if_input)(ifp, m); 4556 DBRUNIF(1, sc->rx_mbuf_alloc--); 4557 4558 } 4559 4560 sw_cons = NEXT_RX_BD(sw_cons); 4561 4562 /* Refresh hw_cons to see if there's new work */ 4563 if (sw_cons == hw_cons) { 4564 hw_cons = sc->hw_rx_cons = 4565 sblk->status_rx_quick_consumer_index0; 4566 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4567 USABLE_RX_BD_PER_PAGE) 4568 hw_cons++; 4569 } 4570 4571 /* Prevent speculative reads from getting ahead of 4572 * the status block. 4573 */ 4574 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4575 BUS_SPACE_BARRIER_READ); 4576 } 4577 4578 for (i = 0; i < RX_PAGES; i++) 4579 bus_dmamap_sync(sc->bnx_dmatag, 4580 sc->rx_bd_chain_map[i], 0, 4581 sc->rx_bd_chain_map[i]->dm_mapsize, 4582 BUS_DMASYNC_PREWRITE); 4583 4584 sc->rx_cons = sw_cons; 4585 sc->rx_prod = sw_prod; 4586 sc->rx_prod_bseq = sw_prod_bseq; 4587 4588 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4589 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4590 4591 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4592 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4593 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4594 } 4595 4596 /****************************************************************************/ 4597 /* Handles transmit completion interrupt events. */ 4598 /* */ 4599 /* Returns: */ 4600 /* Nothing. */ 4601 /****************************************************************************/ 4602 void 4603 bnx_tx_intr(struct bnx_softc *sc) 4604 { 4605 struct status_block *sblk = sc->status_block; 4606 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4607 struct bnx_pkt *pkt; 4608 bus_dmamap_t map; 4609 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4610 4611 DBRUNIF(1, sc->tx_interrupts++); 4612 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4613 BUS_DMASYNC_POSTREAD); 4614 4615 /* Get the hardware's view of the TX consumer index. */ 4616 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4617 4618 /* Skip to the next entry if this is a chain page pointer. */ 4619 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4620 hw_tx_cons++; 4621 4622 sw_tx_cons = sc->tx_cons; 4623 4624 /* Prevent speculative reads from getting ahead of the status block. */ 4625 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4626 BUS_SPACE_BARRIER_READ); 4627 4628 /* Cycle through any completed TX chain page entries. */ 4629 while (sw_tx_cons != hw_tx_cons) { 4630 #ifdef BNX_DEBUG 4631 struct tx_bd *txbd = NULL; 4632 #endif 4633 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4634 4635 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4636 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4637 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4638 4639 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4640 aprint_error_dev(sc->bnx_dev, 4641 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4642 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4643 4644 DBRUNIF(1, txbd = &sc->tx_bd_chain 4645 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4646 4647 DBRUNIF((txbd == NULL), 4648 aprint_error_dev(sc->bnx_dev, 4649 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4650 bnx_breakpoint(sc)); 4651 4652 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4653 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4654 4655 4656 mutex_enter(&sc->tx_pkt_mtx); 4657 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4658 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4659 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4660 mutex_exit(&sc->tx_pkt_mtx); 4661 /* 4662 * Free the associated mbuf. Remember 4663 * that only the last tx_bd of a packet 4664 * has an mbuf pointer and DMA map. 4665 */ 4666 map = pkt->pkt_dmamap; 4667 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4668 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4669 bus_dmamap_unload(sc->bnx_dmatag, map); 4670 4671 m_freem(pkt->pkt_mbuf); 4672 DBRUNIF(1, sc->tx_mbuf_alloc--); 4673 4674 ifp->if_opackets++; 4675 4676 mutex_enter(&sc->tx_pkt_mtx); 4677 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4678 } 4679 mutex_exit(&sc->tx_pkt_mtx); 4680 4681 sc->used_tx_bd--; 4682 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4683 __FILE__, __LINE__, sc->used_tx_bd); 4684 4685 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4686 4687 /* Refresh hw_cons to see if there's new work. */ 4688 hw_tx_cons = sc->hw_tx_cons = 4689 sblk->status_tx_quick_consumer_index0; 4690 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4691 USABLE_TX_BD_PER_PAGE) 4692 hw_tx_cons++; 4693 4694 /* Prevent speculative reads from getting ahead of 4695 * the status block. 4696 */ 4697 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4698 BUS_SPACE_BARRIER_READ); 4699 } 4700 4701 /* Clear the TX timeout timer. */ 4702 ifp->if_timer = 0; 4703 4704 /* Clear the tx hardware queue full flag. */ 4705 if (sc->used_tx_bd < sc->max_tx_bd) { 4706 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4707 aprint_debug_dev(sc->bnx_dev, 4708 "Open TX chain! %d/%d (used/total)\n", 4709 sc->used_tx_bd, sc->max_tx_bd)); 4710 ifp->if_flags &= ~IFF_OACTIVE; 4711 } 4712 4713 sc->tx_cons = sw_tx_cons; 4714 } 4715 4716 /****************************************************************************/ 4717 /* Disables interrupt generation. */ 4718 /* */ 4719 /* Returns: */ 4720 /* Nothing. */ 4721 /****************************************************************************/ 4722 void 4723 bnx_disable_intr(struct bnx_softc *sc) 4724 { 4725 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4726 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4727 } 4728 4729 /****************************************************************************/ 4730 /* Enables interrupt generation. */ 4731 /* */ 4732 /* Returns: */ 4733 /* Nothing. */ 4734 /****************************************************************************/ 4735 void 4736 bnx_enable_intr(struct bnx_softc *sc) 4737 { 4738 u_int32_t val; 4739 4740 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4741 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4742 4743 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4744 sc->last_status_idx); 4745 4746 val = REG_RD(sc, BNX_HC_COMMAND); 4747 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4748 } 4749 4750 /****************************************************************************/ 4751 /* Handles controller initialization. */ 4752 /* */ 4753 /****************************************************************************/ 4754 int 4755 bnx_init(struct ifnet *ifp) 4756 { 4757 struct bnx_softc *sc = ifp->if_softc; 4758 u_int32_t ether_mtu; 4759 int s, error = 0; 4760 4761 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4762 4763 s = splnet(); 4764 4765 bnx_stop(ifp, 0); 4766 4767 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4768 aprint_error_dev(sc->bnx_dev, 4769 "Controller reset failed!\n"); 4770 goto bnx_init_exit; 4771 } 4772 4773 if ((error = bnx_chipinit(sc)) != 0) { 4774 aprint_error_dev(sc->bnx_dev, 4775 "Controller initialization failed!\n"); 4776 goto bnx_init_exit; 4777 } 4778 4779 if ((error = bnx_blockinit(sc)) != 0) { 4780 aprint_error_dev(sc->bnx_dev, 4781 "Block initialization failed!\n"); 4782 goto bnx_init_exit; 4783 } 4784 4785 /* Calculate and program the Ethernet MRU size. */ 4786 if (ifp->if_mtu <= ETHERMTU) { 4787 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4788 sc->mbuf_alloc_size = MCLBYTES; 4789 } else { 4790 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4791 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4792 } 4793 4794 4795 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4796 __func__, ether_mtu); 4797 4798 /* 4799 * Program the MRU and enable Jumbo frame 4800 * support. 4801 */ 4802 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4803 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4804 4805 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4806 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4807 4808 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4809 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4810 sc->mbuf_alloc_size, sc->max_frame_size); 4811 4812 /* Program appropriate promiscuous/multicast filtering. */ 4813 bnx_iff(sc); 4814 4815 /* Init RX buffer descriptor chain. */ 4816 bnx_init_rx_chain(sc); 4817 4818 /* Init TX buffer descriptor chain. */ 4819 bnx_init_tx_chain(sc); 4820 4821 /* Enable host interrupts. */ 4822 bnx_enable_intr(sc); 4823 4824 if ((error = ether_mediachange(ifp)) != 0) 4825 goto bnx_init_exit; 4826 4827 SET(ifp->if_flags, IFF_RUNNING); 4828 CLR(ifp->if_flags, IFF_OACTIVE); 4829 4830 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4831 4832 bnx_init_exit: 4833 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4834 4835 splx(s); 4836 4837 return(error); 4838 } 4839 4840 /****************************************************************************/ 4841 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4842 /* memory visible to the controller. */ 4843 /* */ 4844 /* Returns: */ 4845 /* 0 for success, positive value for failure. */ 4846 /****************************************************************************/ 4847 int 4848 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4849 { 4850 struct bnx_pkt *pkt; 4851 bus_dmamap_t map; 4852 struct tx_bd *txbd = NULL; 4853 u_int16_t vlan_tag = 0, flags = 0; 4854 u_int16_t chain_prod, prod; 4855 #ifdef BNX_DEBUG 4856 u_int16_t debug_prod; 4857 #endif 4858 u_int32_t addr, prod_bseq; 4859 int i, error; 4860 struct m_tag *mtag; 4861 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 4862 4863 mutex_enter(&sc->tx_pkt_mtx); 4864 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 4865 if (pkt == NULL) { 4866 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 4867 mutex_exit(&sc->tx_pkt_mtx); 4868 return ENETDOWN; 4869 } 4870 4871 if (sc->tx_pkt_count <= TOTAL_TX_BD && 4872 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 4873 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 4874 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4875 } 4876 4877 mutex_exit(&sc->tx_pkt_mtx); 4878 return ENOMEM; 4879 } 4880 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4881 mutex_exit(&sc->tx_pkt_mtx); 4882 4883 /* Transfer any checksum offload flags to the bd. */ 4884 if (m->m_pkthdr.csum_flags) { 4885 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 4886 flags |= TX_BD_FLAGS_IP_CKSUM; 4887 if (m->m_pkthdr.csum_flags & 4888 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4889 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4890 } 4891 4892 /* Transfer any VLAN tags to the bd. */ 4893 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m); 4894 if (mtag != NULL) { 4895 flags |= TX_BD_FLAGS_VLAN_TAG; 4896 vlan_tag = VLAN_TAG_VALUE(mtag); 4897 } 4898 4899 /* Map the mbuf into DMAable memory. */ 4900 prod = sc->tx_prod; 4901 chain_prod = TX_CHAIN_IDX(prod); 4902 map = pkt->pkt_dmamap; 4903 4904 /* Map the mbuf into our DMA address space. */ 4905 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 4906 if (error != 0) { 4907 aprint_error_dev(sc->bnx_dev, 4908 "Error mapping mbuf into TX chain!\n"); 4909 sc->tx_dma_map_failures++; 4910 goto maperr; 4911 } 4912 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4913 BUS_DMASYNC_PREWRITE); 4914 /* Make sure there's room in the chain */ 4915 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 4916 goto nospace; 4917 4918 /* prod points to an empty tx_bd at this point. */ 4919 prod_bseq = sc->tx_prod_bseq; 4920 #ifdef BNX_DEBUG 4921 debug_prod = chain_prod; 4922 #endif 4923 DBPRINT(sc, BNX_INFO_SEND, 4924 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4925 "prod_bseq = 0x%08X\n", 4926 __func__, prod, chain_prod, prod_bseq); 4927 4928 /* 4929 * Cycle through each mbuf segment that makes up 4930 * the outgoing frame, gathering the mapping info 4931 * for that segment and creating a tx_bd for the 4932 * mbuf. 4933 */ 4934 for (i = 0; i < map->dm_nsegs ; i++) { 4935 chain_prod = TX_CHAIN_IDX(prod); 4936 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4937 4938 addr = (u_int32_t)map->dm_segs[i].ds_addr; 4939 txbd->tx_bd_haddr_lo = addr; 4940 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4941 txbd->tx_bd_haddr_hi = addr; 4942 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 4943 txbd->tx_bd_vlan_tag = vlan_tag; 4944 txbd->tx_bd_flags = flags; 4945 prod_bseq += map->dm_segs[i].ds_len; 4946 if (i == 0) 4947 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 4948 prod = NEXT_TX_BD(prod); 4949 } 4950 /* Set the END flag on the last TX buffer descriptor. */ 4951 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 4952 4953 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 4954 4955 DBPRINT(sc, BNX_INFO_SEND, 4956 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4957 "prod_bseq = 0x%08X\n", 4958 __func__, prod, chain_prod, prod_bseq); 4959 4960 pkt->pkt_mbuf = m; 4961 pkt->pkt_end_desc = chain_prod; 4962 4963 mutex_enter(&sc->tx_pkt_mtx); 4964 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 4965 mutex_exit(&sc->tx_pkt_mtx); 4966 4967 sc->used_tx_bd += map->dm_nsegs; 4968 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4969 __FILE__, __LINE__, sc->used_tx_bd); 4970 4971 /* Update some debug statistics counters */ 4972 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4973 sc->tx_hi_watermark = sc->used_tx_bd); 4974 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 4975 DBRUNIF(1, sc->tx_mbuf_alloc++); 4976 4977 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4978 map->dm_nsegs)); 4979 4980 /* prod points to the next free tx_bd at this point. */ 4981 sc->tx_prod = prod; 4982 sc->tx_prod_bseq = prod_bseq; 4983 4984 return (0); 4985 4986 4987 nospace: 4988 bus_dmamap_unload(sc->bnx_dmatag, map); 4989 maperr: 4990 mutex_enter(&sc->tx_pkt_mtx); 4991 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4992 mutex_exit(&sc->tx_pkt_mtx); 4993 4994 return (ENOMEM); 4995 } 4996 4997 /****************************************************************************/ 4998 /* Main transmit routine. */ 4999 /* */ 5000 /* Returns: */ 5001 /* Nothing. */ 5002 /****************************************************************************/ 5003 void 5004 bnx_start(struct ifnet *ifp) 5005 { 5006 struct bnx_softc *sc = ifp->if_softc; 5007 struct mbuf *m_head = NULL; 5008 int count = 0; 5009 #ifdef BNX_DEBUG 5010 u_int16_t tx_chain_prod; 5011 #endif 5012 5013 /* If there's no link or the transmit queue is empty then just exit. */ 5014 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5015 DBPRINT(sc, BNX_INFO_SEND, 5016 "%s(): output active or device not running.\n", __func__); 5017 goto bnx_start_exit; 5018 } 5019 5020 /* prod points to the next free tx_bd. */ 5021 #ifdef BNX_DEBUG 5022 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5023 #endif 5024 5025 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5026 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5027 "used_tx %d max_tx %d\n", 5028 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5029 sc->used_tx_bd, sc->max_tx_bd); 5030 5031 /* 5032 * Keep adding entries while there is space in the ring. 5033 */ 5034 while (sc->used_tx_bd < sc->max_tx_bd) { 5035 /* Check for any frames to send. */ 5036 IFQ_POLL(&ifp->if_snd, m_head); 5037 if (m_head == NULL) 5038 break; 5039 5040 /* 5041 * Pack the data into the transmit ring. If we 5042 * don't have room, set the OACTIVE flag to wait 5043 * for the NIC to drain the chain. 5044 */ 5045 if (bnx_tx_encap(sc, m_head)) { 5046 ifp->if_flags |= IFF_OACTIVE; 5047 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5048 "business! Total tx_bd used = %d\n", 5049 sc->used_tx_bd); 5050 break; 5051 } 5052 5053 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5054 count++; 5055 5056 /* Send a copy of the frame to any BPF listeners. */ 5057 bpf_mtap(ifp, m_head); 5058 } 5059 5060 if (count == 0) { 5061 /* no packets were dequeued */ 5062 DBPRINT(sc, BNX_VERBOSE_SEND, 5063 "%s(): No packets were dequeued\n", __func__); 5064 goto bnx_start_exit; 5065 } 5066 5067 /* Update the driver's counters. */ 5068 #ifdef BNX_DEBUG 5069 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5070 #endif 5071 5072 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 5073 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, sc->tx_prod, 5074 tx_chain_prod, sc->tx_prod_bseq); 5075 5076 /* Start the transmit. */ 5077 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5078 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5079 5080 /* Set the tx timeout. */ 5081 ifp->if_timer = BNX_TX_TIMEOUT; 5082 5083 bnx_start_exit: 5084 return; 5085 } 5086 5087 /****************************************************************************/ 5088 /* Handles any IOCTL calls from the operating system. */ 5089 /* */ 5090 /* Returns: */ 5091 /* 0 for success, positive value for failure. */ 5092 /****************************************************************************/ 5093 int 5094 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5095 { 5096 struct bnx_softc *sc = ifp->if_softc; 5097 struct ifreq *ifr = (struct ifreq *) data; 5098 struct mii_data *mii = &sc->bnx_mii; 5099 int s, error = 0; 5100 5101 s = splnet(); 5102 5103 switch (command) { 5104 case SIOCSIFFLAGS: 5105 if ((error = ifioctl_common(ifp, command, data)) != 0) 5106 break; 5107 /* XXX set an ifflags callback and let ether_ioctl 5108 * handle all of this. 5109 */ 5110 if (ISSET(ifp->if_flags, IFF_UP)) { 5111 if (ifp->if_flags & IFF_RUNNING) 5112 error = ENETRESET; 5113 else 5114 bnx_init(ifp); 5115 } else if (ifp->if_flags & IFF_RUNNING) 5116 bnx_stop(ifp, 1); 5117 break; 5118 5119 case SIOCSIFMEDIA: 5120 case SIOCGIFMEDIA: 5121 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5122 sc->bnx_phy_flags); 5123 5124 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5125 break; 5126 5127 default: 5128 error = ether_ioctl(ifp, command, data); 5129 } 5130 5131 if (error == ENETRESET) { 5132 if (ifp->if_flags & IFF_RUNNING) 5133 bnx_iff(sc); 5134 error = 0; 5135 } 5136 5137 splx(s); 5138 return (error); 5139 } 5140 5141 /****************************************************************************/ 5142 /* Transmit timeout handler. */ 5143 /* */ 5144 /* Returns: */ 5145 /* Nothing. */ 5146 /****************************************************************************/ 5147 void 5148 bnx_watchdog(struct ifnet *ifp) 5149 { 5150 struct bnx_softc *sc = ifp->if_softc; 5151 5152 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5153 bnx_dump_status_block(sc)); 5154 /* 5155 * If we are in this routine because of pause frames, then 5156 * don't reset the hardware. 5157 */ 5158 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5159 return; 5160 5161 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5162 5163 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5164 5165 bnx_init(ifp); 5166 5167 ifp->if_oerrors++; 5168 } 5169 5170 /* 5171 * Interrupt handler. 5172 */ 5173 /****************************************************************************/ 5174 /* Main interrupt entry point. Verifies that the controller generated the */ 5175 /* interrupt and then calls a separate routine for handle the various */ 5176 /* interrupt causes (PHY, TX, RX). */ 5177 /* */ 5178 /* Returns: */ 5179 /* 0 for success, positive value for failure. */ 5180 /****************************************************************************/ 5181 int 5182 bnx_intr(void *xsc) 5183 { 5184 struct bnx_softc *sc; 5185 struct ifnet *ifp; 5186 u_int32_t status_attn_bits; 5187 const struct status_block *sblk; 5188 5189 sc = xsc; 5190 5191 ifp = &sc->bnx_ec.ec_if; 5192 5193 if (!device_is_active(sc->bnx_dev) || 5194 (ifp->if_flags & IFF_RUNNING) == 0) 5195 return 0; 5196 5197 DBRUNIF(1, sc->interrupts_generated++); 5198 5199 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5200 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 5201 5202 /* 5203 * If the hardware status block index 5204 * matches the last value read by the 5205 * driver and we haven't asserted our 5206 * interrupt then there's nothing to do. 5207 */ 5208 if ((sc->status_block->status_idx == sc->last_status_idx) && 5209 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 5210 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 5211 return (0); 5212 5213 /* Ack the interrupt and stop others from occuring. */ 5214 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5215 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5216 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5217 5218 /* Keep processing data as long as there is work to do. */ 5219 for (;;) { 5220 sblk = sc->status_block; 5221 status_attn_bits = sblk->status_attn_bits; 5222 5223 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5224 aprint_debug("Simulating unexpected status attention bit set."); 5225 status_attn_bits = status_attn_bits | 5226 STATUS_ATTN_BITS_PARITY_ERROR); 5227 5228 /* Was it a link change interrupt? */ 5229 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5230 (sblk->status_attn_bits_ack & 5231 STATUS_ATTN_BITS_LINK_STATE)) 5232 bnx_phy_intr(sc); 5233 5234 /* If any other attention is asserted then the chip is toast. */ 5235 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5236 (sblk->status_attn_bits_ack & 5237 ~STATUS_ATTN_BITS_LINK_STATE))) { 5238 DBRUN(1, sc->unexpected_attentions++); 5239 5240 BNX_PRINTF(sc, 5241 "Fatal attention detected: 0x%08X\n", 5242 sblk->status_attn_bits); 5243 5244 DBRUN(BNX_FATAL, 5245 if (bnx_debug_unexpected_attention == 0) 5246 bnx_breakpoint(sc)); 5247 5248 bnx_init(ifp); 5249 return (1); 5250 } 5251 5252 /* Check for any completed RX frames. */ 5253 if (sblk->status_rx_quick_consumer_index0 != 5254 sc->hw_rx_cons) 5255 bnx_rx_intr(sc); 5256 5257 /* Check for any completed TX frames. */ 5258 if (sblk->status_tx_quick_consumer_index0 != 5259 sc->hw_tx_cons) 5260 bnx_tx_intr(sc); 5261 5262 /* Save the status block index value for use during the 5263 * next interrupt. 5264 */ 5265 sc->last_status_idx = sblk->status_idx; 5266 5267 /* Prevent speculative reads from getting ahead of the 5268 * status block. 5269 */ 5270 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 5271 BUS_SPACE_BARRIER_READ); 5272 5273 /* If there's no work left then exit the isr. */ 5274 if ((sblk->status_rx_quick_consumer_index0 == 5275 sc->hw_rx_cons) && 5276 (sblk->status_tx_quick_consumer_index0 == 5277 sc->hw_tx_cons)) 5278 break; 5279 } 5280 5281 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5282 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 5283 5284 /* Re-enable interrupts. */ 5285 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5286 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5287 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5288 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5289 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5290 5291 /* Handle any frames that arrived while handling the interrupt. */ 5292 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 5293 bnx_start(ifp); 5294 5295 return (1); 5296 } 5297 5298 /****************************************************************************/ 5299 /* Programs the various packet receive modes (broadcast and multicast). */ 5300 /* */ 5301 /* Returns: */ 5302 /* Nothing. */ 5303 /****************************************************************************/ 5304 void 5305 bnx_iff(struct bnx_softc *sc) 5306 { 5307 struct ethercom *ec = &sc->bnx_ec; 5308 struct ifnet *ifp = &ec->ec_if; 5309 struct ether_multi *enm; 5310 struct ether_multistep step; 5311 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5312 u_int32_t rx_mode, sort_mode; 5313 int h, i; 5314 5315 /* Initialize receive mode default settings. */ 5316 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5317 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5318 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5319 ifp->if_flags &= ~IFF_ALLMULTI; 5320 5321 /* 5322 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5323 * be enbled. 5324 */ 5325 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5326 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5327 5328 /* 5329 * Check for promiscuous, all multicast, or selected 5330 * multicast address filtering. 5331 */ 5332 if (ifp->if_flags & IFF_PROMISC) { 5333 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5334 5335 ifp->if_flags |= IFF_ALLMULTI; 5336 /* Enable promiscuous mode. */ 5337 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5338 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5339 } else if (ifp->if_flags & IFF_ALLMULTI) { 5340 allmulti: 5341 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5342 5343 ifp->if_flags |= IFF_ALLMULTI; 5344 /* Enable all multicast addresses. */ 5345 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5346 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5347 0xffffffff); 5348 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5349 } else { 5350 /* Accept one or more multicast(s). */ 5351 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5352 5353 ETHER_FIRST_MULTI(step, ec, enm); 5354 while (enm != NULL) { 5355 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5356 ETHER_ADDR_LEN)) { 5357 goto allmulti; 5358 } 5359 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5360 0xFF; 5361 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5362 ETHER_NEXT_MULTI(step, enm); 5363 } 5364 5365 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5366 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5367 hashes[i]); 5368 5369 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5370 } 5371 5372 /* Only make changes if the recive mode has actually changed. */ 5373 if (rx_mode != sc->rx_mode) { 5374 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5375 rx_mode); 5376 5377 sc->rx_mode = rx_mode; 5378 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5379 } 5380 5381 /* Disable and clear the exisitng sort before enabling a new sort. */ 5382 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5383 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5384 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5385 } 5386 5387 /****************************************************************************/ 5388 /* Called periodically to updates statistics from the controllers */ 5389 /* statistics block. */ 5390 /* */ 5391 /* Returns: */ 5392 /* Nothing. */ 5393 /****************************************************************************/ 5394 void 5395 bnx_stats_update(struct bnx_softc *sc) 5396 { 5397 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5398 struct statistics_block *stats; 5399 5400 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5401 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5402 BUS_DMASYNC_POSTREAD); 5403 5404 stats = (struct statistics_block *)sc->stats_block; 5405 5406 /* 5407 * Update the interface statistics from the 5408 * hardware statistics. 5409 */ 5410 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5411 5412 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5413 (u_long)stats->stat_EtherStatsOverrsizePkts + 5414 (u_long)stats->stat_IfInMBUFDiscards + 5415 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5416 (u_long)stats->stat_Dot3StatsFCSErrors; 5417 5418 ifp->if_oerrors = (u_long) 5419 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5420 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5421 (u_long)stats->stat_Dot3StatsLateCollisions; 5422 5423 /* 5424 * Certain controllers don't report 5425 * carrier sense errors correctly. 5426 * See errata E11_5708CA0_1165. 5427 */ 5428 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5429 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5430 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5431 5432 /* 5433 * Update the sysctl statistics from the 5434 * hardware statistics. 5435 */ 5436 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 5437 (u_int64_t) stats->stat_IfHCInOctets_lo; 5438 5439 sc->stat_IfHCInBadOctets = 5440 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5441 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 5442 5443 sc->stat_IfHCOutOctets = 5444 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 5445 (u_int64_t) stats->stat_IfHCOutOctets_lo; 5446 5447 sc->stat_IfHCOutBadOctets = 5448 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5449 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 5450 5451 sc->stat_IfHCInUcastPkts = 5452 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5453 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 5454 5455 sc->stat_IfHCInMulticastPkts = 5456 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5457 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 5458 5459 sc->stat_IfHCInBroadcastPkts = 5460 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5461 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 5462 5463 sc->stat_IfHCOutUcastPkts = 5464 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5465 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 5466 5467 sc->stat_IfHCOutMulticastPkts = 5468 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5469 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 5470 5471 sc->stat_IfHCOutBroadcastPkts = 5472 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5473 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5474 5475 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5476 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5477 5478 sc->stat_Dot3StatsCarrierSenseErrors = 5479 stats->stat_Dot3StatsCarrierSenseErrors; 5480 5481 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5482 5483 sc->stat_Dot3StatsAlignmentErrors = 5484 stats->stat_Dot3StatsAlignmentErrors; 5485 5486 sc->stat_Dot3StatsSingleCollisionFrames = 5487 stats->stat_Dot3StatsSingleCollisionFrames; 5488 5489 sc->stat_Dot3StatsMultipleCollisionFrames = 5490 stats->stat_Dot3StatsMultipleCollisionFrames; 5491 5492 sc->stat_Dot3StatsDeferredTransmissions = 5493 stats->stat_Dot3StatsDeferredTransmissions; 5494 5495 sc->stat_Dot3StatsExcessiveCollisions = 5496 stats->stat_Dot3StatsExcessiveCollisions; 5497 5498 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5499 5500 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5501 5502 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5503 5504 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5505 5506 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5507 5508 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5509 5510 sc->stat_EtherStatsPktsRx64Octets = 5511 stats->stat_EtherStatsPktsRx64Octets; 5512 5513 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5514 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5515 5516 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5517 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5518 5519 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5520 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5521 5522 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5523 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5524 5525 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5526 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5527 5528 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5529 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5530 5531 sc->stat_EtherStatsPktsTx64Octets = 5532 stats->stat_EtherStatsPktsTx64Octets; 5533 5534 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5535 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5536 5537 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5538 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5539 5540 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5541 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5542 5543 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5544 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5545 5546 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5547 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5548 5549 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5550 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5551 5552 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5553 5554 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5555 5556 sc->stat_OutXonSent = stats->stat_OutXonSent; 5557 5558 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5559 5560 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5561 5562 sc->stat_MacControlFramesReceived = 5563 stats->stat_MacControlFramesReceived; 5564 5565 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5566 5567 sc->stat_IfInFramesL2FilterDiscards = 5568 stats->stat_IfInFramesL2FilterDiscards; 5569 5570 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5571 5572 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5573 5574 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5575 5576 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5577 5578 sc->stat_CatchupInRuleCheckerDiscards = 5579 stats->stat_CatchupInRuleCheckerDiscards; 5580 5581 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5582 5583 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5584 5585 sc->stat_CatchupInRuleCheckerP4Hit = 5586 stats->stat_CatchupInRuleCheckerP4Hit; 5587 5588 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5589 } 5590 5591 void 5592 bnx_tick(void *xsc) 5593 { 5594 struct bnx_softc *sc = xsc; 5595 struct mii_data *mii; 5596 u_int32_t msg; 5597 u_int16_t prod, chain_prod; 5598 u_int32_t prod_bseq; 5599 int s = splnet(); 5600 5601 /* Tell the firmware that the driver is still running. */ 5602 #ifdef BNX_DEBUG 5603 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5604 #else 5605 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5606 #endif 5607 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5608 5609 /* Update the statistics from the hardware statistics block. */ 5610 bnx_stats_update(sc); 5611 5612 /* Schedule the next tick. */ 5613 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5614 5615 mii = &sc->bnx_mii; 5616 mii_tick(mii); 5617 5618 /* try to get more RX buffers, just in case */ 5619 prod = sc->rx_prod; 5620 prod_bseq = sc->rx_prod_bseq; 5621 chain_prod = RX_CHAIN_IDX(prod); 5622 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5623 sc->rx_prod = prod; 5624 sc->rx_prod_bseq = prod_bseq; 5625 splx(s); 5626 return; 5627 } 5628 5629 /****************************************************************************/ 5630 /* BNX Debug Routines */ 5631 /****************************************************************************/ 5632 #ifdef BNX_DEBUG 5633 5634 /****************************************************************************/ 5635 /* Prints out information about an mbuf. */ 5636 /* */ 5637 /* Returns: */ 5638 /* Nothing. */ 5639 /****************************************************************************/ 5640 void 5641 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5642 { 5643 struct mbuf *mp = m; 5644 5645 if (m == NULL) { 5646 /* Index out of range. */ 5647 aprint_error("mbuf ptr is null!\n"); 5648 return; 5649 } 5650 5651 while (mp) { 5652 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5653 mp, mp->m_len); 5654 5655 if (mp->m_flags & M_EXT) 5656 aprint_debug("M_EXT "); 5657 if (mp->m_flags & M_PKTHDR) 5658 aprint_debug("M_PKTHDR "); 5659 aprint_debug("\n"); 5660 5661 if (mp->m_flags & M_EXT) 5662 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 5663 mp, mp->m_ext.ext_size); 5664 5665 mp = mp->m_next; 5666 } 5667 } 5668 5669 /****************************************************************************/ 5670 /* Prints out the mbufs in the TX mbuf chain. */ 5671 /* */ 5672 /* Returns: */ 5673 /* Nothing. */ 5674 /****************************************************************************/ 5675 void 5676 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5677 { 5678 #if 0 5679 struct mbuf *m; 5680 int i; 5681 5682 aprint_debug_dev(sc->bnx_dev, 5683 "----------------------------" 5684 " tx mbuf data " 5685 "----------------------------\n"); 5686 5687 for (i = 0; i < count; i++) { 5688 m = sc->tx_mbuf_ptr[chain_prod]; 5689 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5690 bnx_dump_mbuf(sc, m); 5691 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5692 } 5693 5694 aprint_debug_dev(sc->bnx_dev, 5695 "--------------------------------------------" 5696 "----------------------------\n"); 5697 #endif 5698 } 5699 5700 /* 5701 * This routine prints the RX mbuf chain. 5702 */ 5703 void 5704 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5705 { 5706 struct mbuf *m; 5707 int i; 5708 5709 aprint_debug_dev(sc->bnx_dev, 5710 "----------------------------" 5711 " rx mbuf data " 5712 "----------------------------\n"); 5713 5714 for (i = 0; i < count; i++) { 5715 m = sc->rx_mbuf_ptr[chain_prod]; 5716 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5717 bnx_dump_mbuf(sc, m); 5718 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5719 } 5720 5721 5722 aprint_debug_dev(sc->bnx_dev, 5723 "--------------------------------------------" 5724 "----------------------------\n"); 5725 } 5726 5727 void 5728 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5729 { 5730 if (idx > MAX_TX_BD) 5731 /* Index out of range. */ 5732 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5733 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5734 /* TX Chain page pointer. */ 5735 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5736 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5737 txbd->tx_bd_haddr_lo); 5738 else 5739 /* Normal tx_bd entry. */ 5740 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5741 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5742 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5743 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5744 txbd->tx_bd_flags); 5745 } 5746 5747 void 5748 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5749 { 5750 if (idx > MAX_RX_BD) 5751 /* Index out of range. */ 5752 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5753 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5754 /* TX Chain page pointer. */ 5755 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5756 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5757 rxbd->rx_bd_haddr_lo); 5758 else 5759 /* Normal tx_bd entry. */ 5760 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5761 "0x%08X, flags = 0x%08X\n", idx, 5762 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5763 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5764 } 5765 5766 void 5767 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5768 { 5769 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5770 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5771 "tcp_udp_xsum = 0x%04X\n", idx, 5772 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5773 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5774 l2fhdr->l2_fhdr_tcp_udp_xsum); 5775 } 5776 5777 /* 5778 * This routine prints the TX chain. 5779 */ 5780 void 5781 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5782 { 5783 struct tx_bd *txbd; 5784 int i; 5785 5786 /* First some info about the tx_bd chain structure. */ 5787 aprint_debug_dev(sc->bnx_dev, 5788 "----------------------------" 5789 " tx_bd chain " 5790 "----------------------------\n"); 5791 5792 BNX_PRINTF(sc, 5793 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5794 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5795 5796 BNX_PRINTF(sc, 5797 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5798 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5799 5800 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5801 5802 aprint_error_dev(sc->bnx_dev, "" 5803 "-----------------------------" 5804 " tx_bd data " 5805 "-----------------------------\n"); 5806 5807 /* Now print out the tx_bd's themselves. */ 5808 for (i = 0; i < count; i++) { 5809 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5810 bnx_dump_txbd(sc, tx_prod, txbd); 5811 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5812 } 5813 5814 aprint_debug_dev(sc->bnx_dev, 5815 "-----------------------------" 5816 "--------------" 5817 "-----------------------------\n"); 5818 } 5819 5820 /* 5821 * This routine prints the RX chain. 5822 */ 5823 void 5824 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5825 { 5826 struct rx_bd *rxbd; 5827 int i; 5828 5829 /* First some info about the tx_bd chain structure. */ 5830 aprint_debug_dev(sc->bnx_dev, 5831 "----------------------------" 5832 " rx_bd chain " 5833 "----------------------------\n"); 5834 5835 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5836 5837 BNX_PRINTF(sc, 5838 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5839 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5840 5841 BNX_PRINTF(sc, 5842 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5843 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5844 5845 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5846 5847 aprint_error_dev(sc->bnx_dev, 5848 "----------------------------" 5849 " rx_bd data " 5850 "----------------------------\n"); 5851 5852 /* Now print out the rx_bd's themselves. */ 5853 for (i = 0; i < count; i++) { 5854 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5855 bnx_dump_rxbd(sc, rx_prod, rxbd); 5856 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5857 } 5858 5859 aprint_debug_dev(sc->bnx_dev, 5860 "----------------------------" 5861 "--------------" 5862 "----------------------------\n"); 5863 } 5864 5865 /* 5866 * This routine prints the status block. 5867 */ 5868 void 5869 bnx_dump_status_block(struct bnx_softc *sc) 5870 { 5871 struct status_block *sblk; 5872 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5873 BUS_DMASYNC_POSTREAD); 5874 5875 sblk = sc->status_block; 5876 5877 aprint_debug_dev(sc->bnx_dev, "----------------------------- Status Block " 5878 "-----------------------------\n"); 5879 5880 BNX_PRINTF(sc, 5881 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5882 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5883 sblk->status_idx); 5884 5885 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5886 sblk->status_rx_quick_consumer_index0, 5887 sblk->status_tx_quick_consumer_index0); 5888 5889 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5890 5891 /* Theses indices are not used for normal L2 drivers. */ 5892 if (sblk->status_rx_quick_consumer_index1 || 5893 sblk->status_tx_quick_consumer_index1) 5894 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5895 sblk->status_rx_quick_consumer_index1, 5896 sblk->status_tx_quick_consumer_index1); 5897 5898 if (sblk->status_rx_quick_consumer_index2 || 5899 sblk->status_tx_quick_consumer_index2) 5900 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5901 sblk->status_rx_quick_consumer_index2, 5902 sblk->status_tx_quick_consumer_index2); 5903 5904 if (sblk->status_rx_quick_consumer_index3 || 5905 sblk->status_tx_quick_consumer_index3) 5906 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5907 sblk->status_rx_quick_consumer_index3, 5908 sblk->status_tx_quick_consumer_index3); 5909 5910 if (sblk->status_rx_quick_consumer_index4 || 5911 sblk->status_rx_quick_consumer_index5) 5912 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5913 sblk->status_rx_quick_consumer_index4, 5914 sblk->status_rx_quick_consumer_index5); 5915 5916 if (sblk->status_rx_quick_consumer_index6 || 5917 sblk->status_rx_quick_consumer_index7) 5918 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5919 sblk->status_rx_quick_consumer_index6, 5920 sblk->status_rx_quick_consumer_index7); 5921 5922 if (sblk->status_rx_quick_consumer_index8 || 5923 sblk->status_rx_quick_consumer_index9) 5924 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5925 sblk->status_rx_quick_consumer_index8, 5926 sblk->status_rx_quick_consumer_index9); 5927 5928 if (sblk->status_rx_quick_consumer_index10 || 5929 sblk->status_rx_quick_consumer_index11) 5930 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5931 sblk->status_rx_quick_consumer_index10, 5932 sblk->status_rx_quick_consumer_index11); 5933 5934 if (sblk->status_rx_quick_consumer_index12 || 5935 sblk->status_rx_quick_consumer_index13) 5936 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5937 sblk->status_rx_quick_consumer_index12, 5938 sblk->status_rx_quick_consumer_index13); 5939 5940 if (sblk->status_rx_quick_consumer_index14 || 5941 sblk->status_rx_quick_consumer_index15) 5942 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5943 sblk->status_rx_quick_consumer_index14, 5944 sblk->status_rx_quick_consumer_index15); 5945 5946 if (sblk->status_completion_producer_index || 5947 sblk->status_cmd_consumer_index) 5948 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5949 sblk->status_completion_producer_index, 5950 sblk->status_cmd_consumer_index); 5951 5952 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 5953 "-----------------------------\n"); 5954 } 5955 5956 /* 5957 * This routine prints the statistics block. 5958 */ 5959 void 5960 bnx_dump_stats_block(struct bnx_softc *sc) 5961 { 5962 struct statistics_block *sblk; 5963 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5964 BUS_DMASYNC_POSTREAD); 5965 5966 sblk = sc->stats_block; 5967 5968 aprint_debug_dev(sc->bnx_dev, "" 5969 "-----------------------------" 5970 " Stats Block " 5971 "-----------------------------\n"); 5972 5973 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5974 "IfHcInBadOctets = 0x%08X:%08X\n", 5975 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5976 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5977 5978 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5979 "IfHcOutBadOctets = 0x%08X:%08X\n", 5980 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5981 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5982 5983 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5984 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5985 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5986 sblk->stat_IfHCInMulticastPkts_hi, 5987 sblk->stat_IfHCInMulticastPkts_lo); 5988 5989 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5990 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5991 sblk->stat_IfHCInBroadcastPkts_hi, 5992 sblk->stat_IfHCInBroadcastPkts_lo, 5993 sblk->stat_IfHCOutUcastPkts_hi, 5994 sblk->stat_IfHCOutUcastPkts_lo); 5995 5996 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5997 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5998 sblk->stat_IfHCOutMulticastPkts_hi, 5999 sblk->stat_IfHCOutMulticastPkts_lo, 6000 sblk->stat_IfHCOutBroadcastPkts_hi, 6001 sblk->stat_IfHCOutBroadcastPkts_lo); 6002 6003 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6004 BNX_PRINTF(sc, "0x%08X : " 6005 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6006 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6007 6008 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6009 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6010 sblk->stat_Dot3StatsCarrierSenseErrors); 6011 6012 if (sblk->stat_Dot3StatsFCSErrors) 6013 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6014 sblk->stat_Dot3StatsFCSErrors); 6015 6016 if (sblk->stat_Dot3StatsAlignmentErrors) 6017 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6018 sblk->stat_Dot3StatsAlignmentErrors); 6019 6020 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6021 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6022 sblk->stat_Dot3StatsSingleCollisionFrames); 6023 6024 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6025 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6026 sblk->stat_Dot3StatsMultipleCollisionFrames); 6027 6028 if (sblk->stat_Dot3StatsDeferredTransmissions) 6029 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6030 sblk->stat_Dot3StatsDeferredTransmissions); 6031 6032 if (sblk->stat_Dot3StatsExcessiveCollisions) 6033 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6034 sblk->stat_Dot3StatsExcessiveCollisions); 6035 6036 if (sblk->stat_Dot3StatsLateCollisions) 6037 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6038 sblk->stat_Dot3StatsLateCollisions); 6039 6040 if (sblk->stat_EtherStatsCollisions) 6041 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6042 sblk->stat_EtherStatsCollisions); 6043 6044 if (sblk->stat_EtherStatsFragments) 6045 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6046 sblk->stat_EtherStatsFragments); 6047 6048 if (sblk->stat_EtherStatsJabbers) 6049 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6050 sblk->stat_EtherStatsJabbers); 6051 6052 if (sblk->stat_EtherStatsUndersizePkts) 6053 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6054 sblk->stat_EtherStatsUndersizePkts); 6055 6056 if (sblk->stat_EtherStatsOverrsizePkts) 6057 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6058 sblk->stat_EtherStatsOverrsizePkts); 6059 6060 if (sblk->stat_EtherStatsPktsRx64Octets) 6061 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6062 sblk->stat_EtherStatsPktsRx64Octets); 6063 6064 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6065 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6066 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6067 6068 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6069 BNX_PRINTF(sc, "0x%08X : " 6070 "EtherStatsPktsRx128Octetsto255Octets\n", 6071 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6072 6073 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6074 BNX_PRINTF(sc, "0x%08X : " 6075 "EtherStatsPktsRx256Octetsto511Octets\n", 6076 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6077 6078 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6079 BNX_PRINTF(sc, "0x%08X : " 6080 "EtherStatsPktsRx512Octetsto1023Octets\n", 6081 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6082 6083 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6084 BNX_PRINTF(sc, "0x%08X : " 6085 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6086 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6087 6088 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6089 BNX_PRINTF(sc, "0x%08X : " 6090 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6091 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6092 6093 if (sblk->stat_EtherStatsPktsTx64Octets) 6094 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6095 sblk->stat_EtherStatsPktsTx64Octets); 6096 6097 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6098 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6099 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6100 6101 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6102 BNX_PRINTF(sc, "0x%08X : " 6103 "EtherStatsPktsTx128Octetsto255Octets\n", 6104 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6105 6106 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6107 BNX_PRINTF(sc, "0x%08X : " 6108 "EtherStatsPktsTx256Octetsto511Octets\n", 6109 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6110 6111 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6112 BNX_PRINTF(sc, "0x%08X : " 6113 "EtherStatsPktsTx512Octetsto1023Octets\n", 6114 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6115 6116 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6117 BNX_PRINTF(sc, "0x%08X : " 6118 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6119 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6120 6121 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6122 BNX_PRINTF(sc, "0x%08X : " 6123 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6124 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6125 6126 if (sblk->stat_XonPauseFramesReceived) 6127 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6128 sblk->stat_XonPauseFramesReceived); 6129 6130 if (sblk->stat_XoffPauseFramesReceived) 6131 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6132 sblk->stat_XoffPauseFramesReceived); 6133 6134 if (sblk->stat_OutXonSent) 6135 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6136 sblk->stat_OutXonSent); 6137 6138 if (sblk->stat_OutXoffSent) 6139 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6140 sblk->stat_OutXoffSent); 6141 6142 if (sblk->stat_FlowControlDone) 6143 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6144 sblk->stat_FlowControlDone); 6145 6146 if (sblk->stat_MacControlFramesReceived) 6147 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6148 sblk->stat_MacControlFramesReceived); 6149 6150 if (sblk->stat_XoffStateEntered) 6151 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6152 sblk->stat_XoffStateEntered); 6153 6154 if (sblk->stat_IfInFramesL2FilterDiscards) 6155 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6156 sblk->stat_IfInFramesL2FilterDiscards); 6157 6158 if (sblk->stat_IfInRuleCheckerDiscards) 6159 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6160 sblk->stat_IfInRuleCheckerDiscards); 6161 6162 if (sblk->stat_IfInFTQDiscards) 6163 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6164 sblk->stat_IfInFTQDiscards); 6165 6166 if (sblk->stat_IfInMBUFDiscards) 6167 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6168 sblk->stat_IfInMBUFDiscards); 6169 6170 if (sblk->stat_IfInRuleCheckerP4Hit) 6171 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6172 sblk->stat_IfInRuleCheckerP4Hit); 6173 6174 if (sblk->stat_CatchupInRuleCheckerDiscards) 6175 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6176 sblk->stat_CatchupInRuleCheckerDiscards); 6177 6178 if (sblk->stat_CatchupInFTQDiscards) 6179 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6180 sblk->stat_CatchupInFTQDiscards); 6181 6182 if (sblk->stat_CatchupInMBUFDiscards) 6183 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6184 sblk->stat_CatchupInMBUFDiscards); 6185 6186 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6187 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6188 sblk->stat_CatchupInRuleCheckerP4Hit); 6189 6190 aprint_debug_dev(sc->bnx_dev, 6191 "-----------------------------" 6192 "--------------" 6193 "-----------------------------\n"); 6194 } 6195 6196 void 6197 bnx_dump_driver_state(struct bnx_softc *sc) 6198 { 6199 aprint_debug_dev(sc->bnx_dev, 6200 "-----------------------------" 6201 " Driver State " 6202 "-----------------------------\n"); 6203 6204 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6205 "address\n", sc); 6206 6207 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6208 sc->status_block); 6209 6210 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6211 "address\n", sc->stats_block); 6212 6213 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6214 "adddress\n", sc->tx_bd_chain); 6215 6216 #if 0 6217 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6218 sc->rx_bd_chain); 6219 6220 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6221 sc->tx_mbuf_ptr); 6222 #endif 6223 6224 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6225 sc->rx_mbuf_ptr); 6226 6227 BNX_PRINTF(sc, 6228 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6229 sc->interrupts_generated); 6230 6231 BNX_PRINTF(sc, 6232 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6233 sc->rx_interrupts); 6234 6235 BNX_PRINTF(sc, 6236 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6237 sc->tx_interrupts); 6238 6239 BNX_PRINTF(sc, 6240 " 0x%08X - (sc->last_status_idx) status block index\n", 6241 sc->last_status_idx); 6242 6243 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6244 sc->tx_prod); 6245 6246 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6247 sc->tx_cons); 6248 6249 BNX_PRINTF(sc, 6250 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6251 sc->tx_prod_bseq); 6252 BNX_PRINTF(sc, 6253 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6254 sc->tx_mbuf_alloc); 6255 6256 BNX_PRINTF(sc, 6257 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6258 sc->used_tx_bd); 6259 6260 BNX_PRINTF(sc, 6261 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6262 sc->tx_hi_watermark, sc->max_tx_bd); 6263 6264 6265 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6266 sc->rx_prod); 6267 6268 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6269 sc->rx_cons); 6270 6271 BNX_PRINTF(sc, 6272 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6273 sc->rx_prod_bseq); 6274 6275 BNX_PRINTF(sc, 6276 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6277 sc->rx_mbuf_alloc); 6278 6279 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6280 sc->free_rx_bd); 6281 6282 BNX_PRINTF(sc, 6283 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6284 sc->rx_low_watermark, sc->max_rx_bd); 6285 6286 BNX_PRINTF(sc, 6287 " 0x%08X - (sc->mbuf_alloc_failed) " 6288 "mbuf alloc failures\n", 6289 sc->mbuf_alloc_failed); 6290 6291 BNX_PRINTF(sc, 6292 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6293 "simulated mbuf alloc failures\n", 6294 sc->mbuf_sim_alloc_failed); 6295 6296 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6297 "-----------------------------\n"); 6298 } 6299 6300 void 6301 bnx_dump_hw_state(struct bnx_softc *sc) 6302 { 6303 u_int32_t val1; 6304 int i; 6305 6306 aprint_debug_dev(sc->bnx_dev, 6307 "----------------------------" 6308 " Hardware State " 6309 "----------------------------\n"); 6310 6311 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6312 6313 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6314 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6315 val1, BNX_MISC_ENABLE_STATUS_BITS); 6316 6317 val1 = REG_RD(sc, BNX_DMA_STATUS); 6318 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6319 6320 val1 = REG_RD(sc, BNX_CTX_STATUS); 6321 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6322 6323 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6324 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6325 BNX_EMAC_STATUS); 6326 6327 val1 = REG_RD(sc, BNX_RPM_STATUS); 6328 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6329 6330 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6331 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6332 BNX_TBDR_STATUS); 6333 6334 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6335 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6336 BNX_TDMA_STATUS); 6337 6338 val1 = REG_RD(sc, BNX_HC_STATUS); 6339 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6340 6341 aprint_debug_dev(sc->bnx_dev, 6342 "----------------------------" 6343 "----------------" 6344 "----------------------------\n"); 6345 6346 aprint_debug_dev(sc->bnx_dev, 6347 "----------------------------" 6348 " Register Dump " 6349 "----------------------------\n"); 6350 6351 for (i = 0x400; i < 0x8000; i += 0x10) 6352 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6353 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6354 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6355 6356 aprint_debug_dev(sc->bnx_dev, 6357 "----------------------------" 6358 "----------------" 6359 "----------------------------\n"); 6360 } 6361 6362 void 6363 bnx_breakpoint(struct bnx_softc *sc) 6364 { 6365 /* Unreachable code to shut the compiler up about unused functions. */ 6366 if (0) { 6367 bnx_dump_txbd(sc, 0, NULL); 6368 bnx_dump_rxbd(sc, 0, NULL); 6369 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6370 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6371 bnx_dump_l2fhdr(sc, 0, NULL); 6372 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6373 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6374 bnx_dump_status_block(sc); 6375 bnx_dump_stats_block(sc); 6376 bnx_dump_driver_state(sc); 6377 bnx_dump_hw_state(sc); 6378 } 6379 6380 bnx_dump_driver_state(sc); 6381 /* Print the important status block fields. */ 6382 bnx_dump_status_block(sc); 6383 6384 #if 0 6385 /* Call the debugger. */ 6386 breakpoint(); 6387 #endif 6388 6389 return; 6390 } 6391 #endif 6392
Indexes created Tue Sep 23 07:09:52 GMT 2025