if_bnx.c revision 1.53
1 /* $NetBSD: if_bnx.c,v 1.53 2014/06/17 21:37:20 msaitoh Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.53 2014/06/17 21:37:20 msaitoh Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * 52 * BCM5706C A0, A1 53 * BCM5706S A0, A1 54 * BCM5708C A0, B0 55 * BCM5708S A0, B0 56 * BCM5709C A0 B0, B1, B2 (pre-production) 57 * BCM5709S A0, B0, B1, B2 (pre-production) 58 */ 59 60 #include <sys/callout.h> 61 #include <sys/mutex.h> 62 63 #include <dev/pci/if_bnxreg.h> 64 #include <dev/pci/if_bnxvar.h> 65 66 #include <dev/microcode/bnx/bnxfw.h> 67 68 /****************************************************************************/ 69 /* BNX Driver Version */ 70 /****************************************************************************/ 71 #define BNX_DRIVER_VERSION "v0.9.6" 72 73 /****************************************************************************/ 74 /* BNX Debug Options */ 75 /****************************************************************************/ 76 #ifdef BNX_DEBUG 77 u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 78 79 /* 0 = Never */ 80 /* 1 = 1 in 2,147,483,648 */ 81 /* 256 = 1 in 8,388,608 */ 82 /* 2048 = 1 in 1,048,576 */ 83 /* 65536 = 1 in 32,768 */ 84 /* 1048576 = 1 in 2,048 */ 85 /* 268435456 = 1 in 8 */ 86 /* 536870912 = 1 in 4 */ 87 /* 1073741824 = 1 in 2 */ 88 89 /* Controls how often the l2_fhdr frame error check will fail. */ 90 int bnx_debug_l2fhdr_status_check = 0; 91 92 /* Controls how often the unexpected attention check will fail. */ 93 int bnx_debug_unexpected_attention = 0; 94 95 /* Controls how often to simulate an mbuf allocation failure. */ 96 int bnx_debug_mbuf_allocation_failure = 0; 97 98 /* Controls how often to simulate a DMA mapping failure. */ 99 int bnx_debug_dma_map_addr_failure = 0; 100 101 /* Controls how often to simulate a bootcode failure. */ 102 int bnx_debug_bootcode_running_failure = 0; 103 #endif 104 105 /****************************************************************************/ 106 /* PCI Device ID Table */ 107 /* */ 108 /* Used by bnx_probe() to identify the devices supported by this driver. */ 109 /****************************************************************************/ 110 static const struct bnx_product { 111 pci_vendor_id_t bp_vendor; 112 pci_product_id_t bp_product; 113 pci_vendor_id_t bp_subvendor; 114 pci_product_id_t bp_subproduct; 115 const char *bp_name; 116 } bnx_devices[] = { 117 #ifdef PCI_SUBPRODUCT_HP_NC370T 118 { 119 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 120 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 121 "HP NC370T Multifunction Gigabit Server Adapter" 122 }, 123 #endif 124 #ifdef PCI_SUBPRODUCT_HP_NC370i 125 { 126 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 127 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 128 "HP NC370i Multifunction Gigabit Server Adapter" 129 }, 130 #endif 131 { 132 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 133 0, 0, 134 "Broadcom NetXtreme II BCM5706 1000Base-T" 135 }, 136 #ifdef PCI_SUBPRODUCT_HP_NC370F 137 { 138 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 139 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 140 "HP NC370F Multifunction Gigabit Server Adapter" 141 }, 142 #endif 143 { 144 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 145 0, 0, 146 "Broadcom NetXtreme II BCM5706 1000Base-SX" 147 }, 148 { 149 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 150 0, 0, 151 "Broadcom NetXtreme II BCM5708 1000Base-T" 152 }, 153 { 154 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 155 0, 0, 156 "Broadcom NetXtreme II BCM5708 1000Base-SX" 157 }, 158 { 159 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 160 0, 0, 161 "Broadcom NetXtreme II BCM5709 1000Base-T" 162 }, 163 { 164 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 165 0, 0, 166 "Broadcom NetXtreme II BCM5709 1000Base-SX" 167 }, 168 { 169 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 170 0, 0, 171 "Broadcom NetXtreme II BCM5716 1000Base-T" 172 }, 173 { 174 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 175 0, 0, 176 "Broadcom NetXtreme II BCM5716 1000Base-SX" 177 }, 178 }; 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 /* Slow EEPROM */ 188 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 189 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 190 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 191 "EEPROM - slow"}, 192 /* Expansion entry 0001 */ 193 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 195 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 196 "Entry 0001"}, 197 /* Saifun SA25F010 (non-buffered flash) */ 198 /* strap, cfg1, & write1 need updates */ 199 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 200 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 201 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 202 "Non-buffered flash (128kB)"}, 203 /* Saifun SA25F020 (non-buffered flash) */ 204 /* strap, cfg1, & write1 need updates */ 205 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 206 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 207 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 208 "Non-buffered flash (256kB)"}, 209 /* Expansion entry 0100 */ 210 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 211 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 212 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 213 "Entry 0100"}, 214 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 215 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 216 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 217 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 218 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 219 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 220 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 221 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 222 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 223 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 224 /* Saifun SA25F005 (non-buffered flash) */ 225 /* strap, cfg1, & write1 need updates */ 226 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 227 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 228 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 229 "Non-buffered flash (64kB)"}, 230 /* Fast EEPROM */ 231 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 232 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 233 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 234 "EEPROM - fast"}, 235 /* Expansion entry 1001 */ 236 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 239 "Entry 1001"}, 240 /* Expansion entry 1010 */ 241 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 242 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 243 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 244 "Entry 1010"}, 245 /* ATMEL AT45DB011B (buffered flash) */ 246 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 247 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 248 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 249 "Buffered flash (128kB)"}, 250 /* Expansion entry 1100 */ 251 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 252 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 253 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 254 "Entry 1100"}, 255 /* Expansion entry 1101 */ 256 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 257 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 258 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 259 "Entry 1101"}, 260 /* Ateml Expansion entry 1110 */ 261 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 262 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 263 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 264 "Entry 1110 (Atmel)"}, 265 /* ATMEL AT45DB021B (buffered flash) */ 266 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 267 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 268 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 269 "Buffered flash (256kB)"}, 270 }; 271 272 /* 273 * The BCM5709 controllers transparently handle the 274 * differences between Atmel 264 byte pages and all 275 * flash devices which use 256 byte pages, so no 276 * logical-to-physical mapping is required in the 277 * driver. 278 */ 279 static struct flash_spec flash_5709 = { 280 .flags = BNX_NV_BUFFERED, 281 .page_bits = BCM5709_FLASH_PAGE_BITS, 282 .page_size = BCM5709_FLASH_PAGE_SIZE, 283 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 284 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 285 .name = "5709 buffered flash (256kB)", 286 }; 287 288 /****************************************************************************/ 289 /* OpenBSD device entry points. */ 290 /****************************************************************************/ 291 static int bnx_probe(device_t, cfdata_t, void *); 292 void bnx_attach(device_t, device_t, void *); 293 int bnx_detach(device_t, int); 294 295 /****************************************************************************/ 296 /* BNX Debug Data Structure Dump Routines */ 297 /****************************************************************************/ 298 #ifdef BNX_DEBUG 299 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 300 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 303 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 304 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 305 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_status_block(struct bnx_softc *); 308 void bnx_dump_stats_block(struct bnx_softc *); 309 void bnx_dump_driver_state(struct bnx_softc *); 310 void bnx_dump_hw_state(struct bnx_softc *); 311 void bnx_breakpoint(struct bnx_softc *); 312 #endif 313 314 /****************************************************************************/ 315 /* BNX Register/Memory Access Routines */ 316 /****************************************************************************/ 317 u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); 318 void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); 319 void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); 320 int bnx_miibus_read_reg(device_t, int, int); 321 void bnx_miibus_write_reg(device_t, int, int, int); 322 void bnx_miibus_statchg(struct ifnet *); 323 324 /****************************************************************************/ 325 /* BNX NVRAM Access Routines */ 326 /****************************************************************************/ 327 int bnx_acquire_nvram_lock(struct bnx_softc *); 328 int bnx_release_nvram_lock(struct bnx_softc *); 329 void bnx_enable_nvram_access(struct bnx_softc *); 330 void bnx_disable_nvram_access(struct bnx_softc *); 331 int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 332 u_int32_t); 333 int bnx_init_nvram(struct bnx_softc *); 334 int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); 335 int bnx_nvram_test(struct bnx_softc *); 336 #ifdef BNX_NVRAM_WRITE_SUPPORT 337 int bnx_enable_nvram_write(struct bnx_softc *); 338 void bnx_disable_nvram_write(struct bnx_softc *); 339 int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); 340 int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, 341 u_int32_t); 342 int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); 343 #endif 344 345 /****************************************************************************/ 346 /* */ 347 /****************************************************************************/ 348 void bnx_get_media(struct bnx_softc *); 349 void bnx_init_media(struct bnx_softc *); 350 int bnx_dma_alloc(struct bnx_softc *); 351 void bnx_dma_free(struct bnx_softc *); 352 void bnx_release_resources(struct bnx_softc *); 353 354 /****************************************************************************/ 355 /* BNX Firmware Synchronization and Load */ 356 /****************************************************************************/ 357 int bnx_fw_sync(struct bnx_softc *, u_int32_t); 358 void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, 359 u_int32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 void bnx_stop(struct ifnet *, int); 365 int bnx_reset(struct bnx_softc *, u_int32_t); 366 int bnx_chipinit(struct bnx_softc *); 367 int bnx_blockinit(struct bnx_softc *); 368 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, 369 u_int16_t *, u_int32_t *); 370 int bnx_get_buf(struct bnx_softc *, u_int16_t *, u_int16_t *, u_int32_t *); 371 372 int bnx_init_tx_chain(struct bnx_softc *); 373 void bnx_init_tx_context(struct bnx_softc *); 374 int bnx_init_rx_chain(struct bnx_softc *); 375 void bnx_init_rx_context(struct bnx_softc *); 376 void bnx_free_rx_chain(struct bnx_softc *); 377 void bnx_free_tx_chain(struct bnx_softc *); 378 379 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 380 void bnx_start(struct ifnet *); 381 int bnx_ioctl(struct ifnet *, u_long, void *); 382 void bnx_watchdog(struct ifnet *); 383 int bnx_init(struct ifnet *); 384 385 void bnx_init_context(struct bnx_softc *); 386 void bnx_get_mac_addr(struct bnx_softc *); 387 void bnx_set_mac_addr(struct bnx_softc *); 388 void bnx_phy_intr(struct bnx_softc *); 389 void bnx_rx_intr(struct bnx_softc *); 390 void bnx_tx_intr(struct bnx_softc *); 391 void bnx_disable_intr(struct bnx_softc *); 392 void bnx_enable_intr(struct bnx_softc *); 393 394 int bnx_intr(void *); 395 void bnx_iff(struct bnx_softc *); 396 void bnx_stats_update(struct bnx_softc *); 397 void bnx_tick(void *); 398 399 struct pool *bnx_tx_pool = NULL; 400 void bnx_alloc_pkts(struct work *, void *); 401 402 /****************************************************************************/ 403 /* OpenBSD device dispatch table. */ 404 /****************************************************************************/ 405 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 406 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 407 408 /****************************************************************************/ 409 /* Device probe function. */ 410 /* */ 411 /* Compares the device to the driver's list of supported devices and */ 412 /* reports back to the OS whether this is the right driver for the device. */ 413 /* */ 414 /* Returns: */ 415 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 416 /****************************************************************************/ 417 static const struct bnx_product * 418 bnx_lookup(const struct pci_attach_args *pa) 419 { 420 int i; 421 pcireg_t subid; 422 423 for (i = 0; i < __arraycount(bnx_devices); i++) { 424 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 425 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 426 continue; 427 if (!bnx_devices[i].bp_subvendor) 428 return &bnx_devices[i]; 429 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 430 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 431 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 432 return &bnx_devices[i]; 433 } 434 435 return NULL; 436 } 437 static int 438 bnx_probe(device_t parent, cfdata_t match, void *aux) 439 { 440 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 441 442 if (bnx_lookup(pa) != NULL) 443 return 1; 444 445 return 0; 446 } 447 448 /****************************************************************************/ 449 /* Device attach function. */ 450 /* */ 451 /* Allocates device resources, performs secondary chip identification, */ 452 /* resets and initializes the hardware, and initializes driver instance */ 453 /* variables. */ 454 /* */ 455 /* Returns: */ 456 /* 0 on success, positive value on failure. */ 457 /****************************************************************************/ 458 void 459 bnx_attach(device_t parent, device_t self, void *aux) 460 { 461 const struct bnx_product *bp; 462 struct bnx_softc *sc = device_private(self); 463 prop_dictionary_t dict; 464 struct pci_attach_args *pa = aux; 465 pci_chipset_tag_t pc = pa->pa_pc; 466 pci_intr_handle_t ih; 467 const char *intrstr = NULL; 468 u_int32_t command; 469 struct ifnet *ifp; 470 u_int32_t val; 471 int mii_flags = MIIF_FORCEANEG; 472 pcireg_t memtype; 473 char intrbuf[PCI_INTRSTR_LEN]; 474 475 if (bnx_tx_pool == NULL) { 476 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 477 if (bnx_tx_pool != NULL) { 478 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 479 0, 0, 0, "bnxpkts", NULL, IPL_NET); 480 } else { 481 aprint_error(": can't alloc bnx_tx_pool\n"); 482 return; 483 } 484 } 485 486 bp = bnx_lookup(pa); 487 if (bp == NULL) 488 panic("unknown device"); 489 490 sc->bnx_dev = self; 491 492 aprint_naive("\n"); 493 aprint_normal(": %s\n", bp->bp_name); 494 495 sc->bnx_pa = *pa; 496 497 /* 498 * Map control/status registers. 499 */ 500 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 501 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 502 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 503 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 504 505 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 506 aprint_error_dev(sc->bnx_dev, 507 "failed to enable memory mapping!\n"); 508 return; 509 } 510 511 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 512 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 513 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 514 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 515 return; 516 } 517 518 if (pci_intr_map(pa, &ih)) { 519 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 520 goto bnx_attach_fail; 521 } 522 523 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 524 525 /* 526 * Configure byte swap and enable indirect register access. 527 * Rely on CPU to do target byte swapping on big endian systems. 528 * Access to registers outside of PCI configurtion space are not 529 * valid until this is done. 530 */ 531 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 532 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 533 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 534 535 /* Save ASIC revsion info. */ 536 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 537 538 /* 539 * Find the base address for shared memory access. 540 * Newer versions of bootcode use a signature and offset 541 * while older versions use a fixed address. 542 */ 543 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 544 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 545 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 546 (sc->bnx_pa.pa_function << 2)); 547 else 548 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 549 550 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 551 552 /* Set initial device and PHY flags */ 553 sc->bnx_flags = 0; 554 sc->bnx_phy_flags = 0; 555 556 /* Get PCI bus information (speed and type). */ 557 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 558 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 559 u_int32_t clkreg; 560 561 sc->bnx_flags |= BNX_PCIX_FLAG; 562 563 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 564 565 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 566 switch (clkreg) { 567 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 568 sc->bus_speed_mhz = 133; 569 break; 570 571 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 572 sc->bus_speed_mhz = 100; 573 break; 574 575 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 576 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 577 sc->bus_speed_mhz = 66; 578 break; 579 580 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 581 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 582 sc->bus_speed_mhz = 50; 583 break; 584 585 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 586 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 587 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 588 sc->bus_speed_mhz = 33; 589 break; 590 } 591 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 592 sc->bus_speed_mhz = 66; 593 else 594 sc->bus_speed_mhz = 33; 595 596 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 597 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 598 599 /* Reset the controller. */ 600 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 601 goto bnx_attach_fail; 602 603 /* Initialize the controller. */ 604 if (bnx_chipinit(sc)) { 605 aprint_error_dev(sc->bnx_dev, 606 "Controller initialization failed!\n"); 607 goto bnx_attach_fail; 608 } 609 610 /* Perform NVRAM test. */ 611 if (bnx_nvram_test(sc)) { 612 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 613 goto bnx_attach_fail; 614 } 615 616 /* Fetch the permanent Ethernet MAC address. */ 617 bnx_get_mac_addr(sc); 618 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 619 ether_sprintf(sc->eaddr)); 620 621 /* 622 * Trip points control how many BDs 623 * should be ready before generating an 624 * interrupt while ticks control how long 625 * a BD can sit in the chain before 626 * generating an interrupt. Set the default 627 * values for the RX and TX rings. 628 */ 629 630 #ifdef BNX_DEBUG 631 /* Force more frequent interrupts. */ 632 sc->bnx_tx_quick_cons_trip_int = 1; 633 sc->bnx_tx_quick_cons_trip = 1; 634 sc->bnx_tx_ticks_int = 0; 635 sc->bnx_tx_ticks = 0; 636 637 sc->bnx_rx_quick_cons_trip_int = 1; 638 sc->bnx_rx_quick_cons_trip = 1; 639 sc->bnx_rx_ticks_int = 0; 640 sc->bnx_rx_ticks = 0; 641 #else 642 sc->bnx_tx_quick_cons_trip_int = 20; 643 sc->bnx_tx_quick_cons_trip = 20; 644 sc->bnx_tx_ticks_int = 80; 645 sc->bnx_tx_ticks = 80; 646 647 sc->bnx_rx_quick_cons_trip_int = 6; 648 sc->bnx_rx_quick_cons_trip = 6; 649 sc->bnx_rx_ticks_int = 18; 650 sc->bnx_rx_ticks = 18; 651 #endif 652 653 /* Update statistics once every second. */ 654 sc->bnx_stats_ticks = 1000000 & 0xffff00; 655 656 /* Find the media type for the adapter. */ 657 bnx_get_media(sc); 658 659 /* 660 * Store config data needed by the PHY driver for 661 * backplane applications 662 */ 663 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 664 BNX_SHARED_HW_CFG_CONFIG); 665 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 666 BNX_PORT_HW_CFG_CONFIG); 667 668 /* Allocate DMA memory resources. */ 669 sc->bnx_dmatag = pa->pa_dmat; 670 if (bnx_dma_alloc(sc)) { 671 aprint_error_dev(sc->bnx_dev, 672 "DMA resource allocation failed!\n"); 673 goto bnx_attach_fail; 674 } 675 676 /* Initialize the ifnet interface. */ 677 ifp = &sc->bnx_ec.ec_if; 678 ifp->if_softc = sc; 679 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 680 ifp->if_ioctl = bnx_ioctl; 681 ifp->if_stop = bnx_stop; 682 ifp->if_start = bnx_start; 683 ifp->if_init = bnx_init; 684 ifp->if_timer = 0; 685 ifp->if_watchdog = bnx_watchdog; 686 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 687 IFQ_SET_READY(&ifp->if_snd); 688 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 689 690 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 691 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 692 693 ifp->if_capabilities |= 694 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 695 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 696 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 697 698 /* Hookup IRQ last. */ 699 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 700 if (sc->bnx_intrhand == NULL) { 701 aprint_error_dev(self, "couldn't establish interrupt"); 702 if (intrstr != NULL) 703 aprint_error(" at %s", intrstr); 704 aprint_error("\n"); 705 goto bnx_attach_fail; 706 } 707 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 708 709 /* create workqueue to handle packet allocations */ 710 if (workqueue_create(&sc->bnx_wq, device_xname(self), 711 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 712 aprint_error_dev(self, "failed to create workqueue\n"); 713 goto bnx_attach_fail; 714 } 715 716 sc->bnx_mii.mii_ifp = ifp; 717 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 718 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 719 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 720 721 /* Handle any special PHY initialization for SerDes PHYs. */ 722 bnx_init_media(sc); 723 724 sc->bnx_ec.ec_mii = &sc->bnx_mii; 725 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 726 ether_mediastatus); 727 728 /* set phyflags and chipid before mii_attach() */ 729 dict = device_properties(self); 730 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 731 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 732 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 733 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 734 735 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 736 mii_flags |= MIIF_HAVEFIBER; 737 mii_attach(self, &sc->bnx_mii, 0xffffffff, 738 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 739 740 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 741 aprint_error_dev(self, "no PHY found!\n"); 742 ifmedia_add(&sc->bnx_mii.mii_media, 743 IFM_ETHER|IFM_MANUAL, 0, NULL); 744 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_MANUAL); 745 } else 746 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_AUTO); 747 748 /* Attach to the Ethernet interface list. */ 749 if_attach(ifp); 750 ether_ifattach(ifp,sc->eaddr); 751 752 callout_init(&sc->bnx_timeout, 0); 753 754 if (pmf_device_register(self, NULL, NULL)) 755 pmf_class_network_register(self, ifp); 756 else 757 aprint_error_dev(self, "couldn't establish power handler\n"); 758 759 /* Print some important debugging info. */ 760 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 761 762 goto bnx_attach_exit; 763 764 bnx_attach_fail: 765 bnx_release_resources(sc); 766 767 bnx_attach_exit: 768 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 769 } 770 771 /****************************************************************************/ 772 /* Device detach function. */ 773 /* */ 774 /* Stops the controller, resets the controller, and releases resources. */ 775 /* */ 776 /* Returns: */ 777 /* 0 on success, positive value on failure. */ 778 /****************************************************************************/ 779 int 780 bnx_detach(device_t dev, int flags) 781 { 782 int s; 783 struct bnx_softc *sc; 784 struct ifnet *ifp; 785 786 sc = device_private(dev); 787 ifp = &sc->bnx_ec.ec_if; 788 789 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 790 791 /* Stop and reset the controller. */ 792 s = splnet(); 793 if (ifp->if_flags & IFF_RUNNING) 794 bnx_stop(ifp, 1); 795 else { 796 /* Disable the transmit/receive blocks. */ 797 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 798 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 799 DELAY(20); 800 bnx_disable_intr(sc); 801 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 802 } 803 804 splx(s); 805 806 pmf_device_deregister(dev); 807 callout_destroy(&sc->bnx_timeout); 808 ether_ifdetach(ifp); 809 workqueue_destroy(sc->bnx_wq); 810 811 /* Delete all remaining media. */ 812 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 813 814 if_detach(ifp); 815 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 816 817 /* Release all remaining resources. */ 818 bnx_release_resources(sc); 819 820 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 821 822 return 0; 823 } 824 825 /****************************************************************************/ 826 /* Indirect register read. */ 827 /* */ 828 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 829 /* configuration space. Using this mechanism avoids issues with posted */ 830 /* reads but is much slower than memory-mapped I/O. */ 831 /* */ 832 /* Returns: */ 833 /* The value of the register. */ 834 /****************************************************************************/ 835 u_int32_t 836 bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) 837 { 838 struct pci_attach_args *pa = &(sc->bnx_pa); 839 840 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 841 offset); 842 #ifdef BNX_DEBUG 843 { 844 u_int32_t val; 845 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 846 BNX_PCICFG_REG_WINDOW); 847 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 848 "val = 0x%08X\n", __func__, offset, val); 849 return val; 850 } 851 #else 852 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 853 #endif 854 } 855 856 /****************************************************************************/ 857 /* Indirect register write. */ 858 /* */ 859 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 860 /* configuration space. Using this mechanism avoids issues with posted */ 861 /* writes but is muchh slower than memory-mapped I/O. */ 862 /* */ 863 /* Returns: */ 864 /* Nothing. */ 865 /****************************************************************************/ 866 void 867 bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) 868 { 869 struct pci_attach_args *pa = &(sc->bnx_pa); 870 871 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 872 __func__, offset, val); 873 874 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 875 offset); 876 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 877 } 878 879 /****************************************************************************/ 880 /* Context memory write. */ 881 /* */ 882 /* The NetXtreme II controller uses context memory to track connection */ 883 /* information for L2 and higher network protocols. */ 884 /* */ 885 /* Returns: */ 886 /* Nothing. */ 887 /****************************************************************************/ 888 void 889 bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t ctx_offset, 890 u_int32_t ctx_val) 891 { 892 u_int32_t idx, offset = ctx_offset + cid_addr; 893 u_int32_t val, retry_cnt = 5; 894 895 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 896 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 897 REG_WR(sc, BNX_CTX_CTX_CTRL, 898 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 899 900 for (idx = 0; idx < retry_cnt; idx++) { 901 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 902 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 903 break; 904 DELAY(5); 905 } 906 907 #if 0 908 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 909 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 910 "cid_addr = 0x%08X, offset = 0x%08X!\n", 911 __FILE__, __LINE__, cid_addr, ctx_offset); 912 #endif 913 914 } else { 915 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 916 REG_WR(sc, BNX_CTX_DATA, ctx_val); 917 } 918 } 919 920 /****************************************************************************/ 921 /* PHY register read. */ 922 /* */ 923 /* Implements register reads on the MII bus. */ 924 /* */ 925 /* Returns: */ 926 /* The value of the register. */ 927 /****************************************************************************/ 928 int 929 bnx_miibus_read_reg(device_t dev, int phy, int reg) 930 { 931 struct bnx_softc *sc = device_private(dev); 932 u_int32_t val; 933 int i; 934 935 /* Make sure we are accessing the correct PHY address. */ 936 if (phy != sc->bnx_phy_addr) { 937 DBPRINT(sc, BNX_VERBOSE, 938 "Invalid PHY address %d for PHY read!\n", phy); 939 return 0; 940 } 941 942 /* 943 * The BCM5709S PHY is an IEEE Clause 45 PHY 944 * with special mappings to work with IEEE 945 * Clause 22 register accesses. 946 */ 947 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 948 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 949 reg += 0x10; 950 } 951 952 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 953 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 954 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 955 956 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 957 REG_RD(sc, BNX_EMAC_MDIO_MODE); 958 959 DELAY(40); 960 } 961 962 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 963 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 964 BNX_EMAC_MDIO_COMM_START_BUSY; 965 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 966 967 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 968 DELAY(10); 969 970 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 971 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 972 DELAY(5); 973 974 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 975 val &= BNX_EMAC_MDIO_COMM_DATA; 976 977 break; 978 } 979 } 980 981 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 982 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 983 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 984 val = 0x0; 985 } else 986 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 987 988 DBPRINT(sc, BNX_EXCESSIVE, 989 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 990 (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 991 992 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 993 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 994 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 995 996 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 997 REG_RD(sc, BNX_EMAC_MDIO_MODE); 998 999 DELAY(40); 1000 } 1001 1002 return (val & 0xffff); 1003 } 1004 1005 /****************************************************************************/ 1006 /* PHY register write. */ 1007 /* */ 1008 /* Implements register writes on the MII bus. */ 1009 /* */ 1010 /* Returns: */ 1011 /* The value of the register. */ 1012 /****************************************************************************/ 1013 void 1014 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 1015 { 1016 struct bnx_softc *sc = device_private(dev); 1017 u_int32_t val1; 1018 int i; 1019 1020 /* Make sure we are accessing the correct PHY address. */ 1021 if (phy != sc->bnx_phy_addr) { 1022 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 1023 phy); 1024 return; 1025 } 1026 1027 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1028 "val = 0x%04X\n", __func__, 1029 phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); 1030 1031 /* 1032 * The BCM5709S PHY is an IEEE Clause 45 PHY 1033 * with special mappings to work with IEEE 1034 * Clause 22 register accesses. 1035 */ 1036 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1037 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1038 reg += 0x10; 1039 } 1040 1041 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1042 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1043 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1044 1045 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1046 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1047 1048 DELAY(40); 1049 } 1050 1051 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1052 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1053 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1054 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1055 1056 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1057 DELAY(10); 1058 1059 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1060 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1061 DELAY(5); 1062 break; 1063 } 1064 } 1065 1066 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1067 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1068 __LINE__); 1069 } 1070 1071 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1072 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1073 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1074 1075 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1076 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1077 1078 DELAY(40); 1079 } 1080 } 1081 1082 /****************************************************************************/ 1083 /* MII bus status change. */ 1084 /* */ 1085 /* Called by the MII bus driver when the PHY establishes link to set the */ 1086 /* MAC interface registers. */ 1087 /* */ 1088 /* Returns: */ 1089 /* Nothing. */ 1090 /****************************************************************************/ 1091 void 1092 bnx_miibus_statchg(struct ifnet *ifp) 1093 { 1094 struct bnx_softc *sc = ifp->if_softc; 1095 struct mii_data *mii = &sc->bnx_mii; 1096 int val; 1097 1098 val = REG_RD(sc, BNX_EMAC_MODE); 1099 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1100 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1101 BNX_EMAC_MODE_25G); 1102 1103 /* Set MII or GMII interface based on the speed 1104 * negotiated by the PHY. 1105 */ 1106 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1107 case IFM_10_T: 1108 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1109 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1110 val |= BNX_EMAC_MODE_PORT_MII_10; 1111 break; 1112 } 1113 /* FALLTHROUGH */ 1114 case IFM_100_TX: 1115 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1116 val |= BNX_EMAC_MODE_PORT_MII; 1117 break; 1118 case IFM_2500_SX: 1119 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1120 val |= BNX_EMAC_MODE_25G; 1121 /* FALLTHROUGH */ 1122 case IFM_1000_T: 1123 case IFM_1000_SX: 1124 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1125 val |= BNX_EMAC_MODE_PORT_GMII; 1126 break; 1127 default: 1128 val |= BNX_EMAC_MODE_PORT_GMII; 1129 break; 1130 } 1131 1132 /* Set half or full duplex based on the duplicity 1133 * negotiated by the PHY. 1134 */ 1135 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1136 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1137 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1138 } else { 1139 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1140 } 1141 1142 REG_WR(sc, BNX_EMAC_MODE, val); 1143 } 1144 1145 /****************************************************************************/ 1146 /* Acquire NVRAM lock. */ 1147 /* */ 1148 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1149 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1150 /* for use by the driver. */ 1151 /* */ 1152 /* Returns: */ 1153 /* 0 on success, positive value on failure. */ 1154 /****************************************************************************/ 1155 int 1156 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1157 { 1158 u_int32_t val; 1159 int j; 1160 1161 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1162 1163 /* Request access to the flash interface. */ 1164 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1165 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1166 val = REG_RD(sc, BNX_NVM_SW_ARB); 1167 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1168 break; 1169 1170 DELAY(5); 1171 } 1172 1173 if (j >= NVRAM_TIMEOUT_COUNT) { 1174 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1175 return EBUSY; 1176 } 1177 1178 return 0; 1179 } 1180 1181 /****************************************************************************/ 1182 /* Release NVRAM lock. */ 1183 /* */ 1184 /* When the caller is finished accessing NVRAM the lock must be released. */ 1185 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1186 /* for use by the driver. */ 1187 /* */ 1188 /* Returns: */ 1189 /* 0 on success, positive value on failure. */ 1190 /****************************************************************************/ 1191 int 1192 bnx_release_nvram_lock(struct bnx_softc *sc) 1193 { 1194 int j; 1195 u_int32_t val; 1196 1197 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1198 1199 /* Relinquish nvram interface. */ 1200 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1201 1202 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1203 val = REG_RD(sc, BNX_NVM_SW_ARB); 1204 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1205 break; 1206 1207 DELAY(5); 1208 } 1209 1210 if (j >= NVRAM_TIMEOUT_COUNT) { 1211 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1212 return EBUSY; 1213 } 1214 1215 return 0; 1216 } 1217 1218 #ifdef BNX_NVRAM_WRITE_SUPPORT 1219 /****************************************************************************/ 1220 /* Enable NVRAM write access. */ 1221 /* */ 1222 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1223 /* */ 1224 /* Returns: */ 1225 /* 0 on success, positive value on failure. */ 1226 /****************************************************************************/ 1227 int 1228 bnx_enable_nvram_write(struct bnx_softc *sc) 1229 { 1230 u_int32_t val; 1231 1232 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1233 1234 val = REG_RD(sc, BNX_MISC_CFG); 1235 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1236 1237 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1238 int j; 1239 1240 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1241 REG_WR(sc, BNX_NVM_COMMAND, 1242 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1243 1244 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1245 DELAY(5); 1246 1247 val = REG_RD(sc, BNX_NVM_COMMAND); 1248 if (val & BNX_NVM_COMMAND_DONE) 1249 break; 1250 } 1251 1252 if (j >= NVRAM_TIMEOUT_COUNT) { 1253 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1254 return EBUSY; 1255 } 1256 } 1257 1258 return 0; 1259 } 1260 1261 /****************************************************************************/ 1262 /* Disable NVRAM write access. */ 1263 /* */ 1264 /* When the caller is finished writing to NVRAM write access must be */ 1265 /* disabled. */ 1266 /* */ 1267 /* Returns: */ 1268 /* Nothing. */ 1269 /****************************************************************************/ 1270 void 1271 bnx_disable_nvram_write(struct bnx_softc *sc) 1272 { 1273 u_int32_t val; 1274 1275 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1276 1277 val = REG_RD(sc, BNX_MISC_CFG); 1278 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1279 } 1280 #endif 1281 1282 /****************************************************************************/ 1283 /* Enable NVRAM access. */ 1284 /* */ 1285 /* Before accessing NVRAM for read or write operations the caller must */ 1286 /* enabled NVRAM access. */ 1287 /* */ 1288 /* Returns: */ 1289 /* Nothing. */ 1290 /****************************************************************************/ 1291 void 1292 bnx_enable_nvram_access(struct bnx_softc *sc) 1293 { 1294 u_int32_t val; 1295 1296 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1297 1298 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1299 /* Enable both bits, even on read. */ 1300 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1301 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1302 } 1303 1304 /****************************************************************************/ 1305 /* Disable NVRAM access. */ 1306 /* */ 1307 /* When the caller is finished accessing NVRAM access must be disabled. */ 1308 /* */ 1309 /* Returns: */ 1310 /* Nothing. */ 1311 /****************************************************************************/ 1312 void 1313 bnx_disable_nvram_access(struct bnx_softc *sc) 1314 { 1315 u_int32_t val; 1316 1317 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1318 1319 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1320 1321 /* Disable both bits, even after read. */ 1322 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1323 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1324 } 1325 1326 #ifdef BNX_NVRAM_WRITE_SUPPORT 1327 /****************************************************************************/ 1328 /* Erase NVRAM page before writing. */ 1329 /* */ 1330 /* Non-buffered flash parts require that a page be erased before it is */ 1331 /* written. */ 1332 /* */ 1333 /* Returns: */ 1334 /* 0 on success, positive value on failure. */ 1335 /****************************************************************************/ 1336 int 1337 bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) 1338 { 1339 u_int32_t cmd; 1340 int j; 1341 1342 /* Buffered flash doesn't require an erase. */ 1343 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1344 return 0; 1345 1346 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1347 1348 /* Build an erase command. */ 1349 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1350 BNX_NVM_COMMAND_DOIT; 1351 1352 /* 1353 * Clear the DONE bit separately, set the NVRAM address to erase, 1354 * and issue the erase command. 1355 */ 1356 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1357 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1358 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1359 1360 /* Wait for completion. */ 1361 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1362 u_int32_t val; 1363 1364 DELAY(5); 1365 1366 val = REG_RD(sc, BNX_NVM_COMMAND); 1367 if (val & BNX_NVM_COMMAND_DONE) 1368 break; 1369 } 1370 1371 if (j >= NVRAM_TIMEOUT_COUNT) { 1372 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1373 return EBUSY; 1374 } 1375 1376 return 0; 1377 } 1378 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1379 1380 /****************************************************************************/ 1381 /* Read a dword (32 bits) from NVRAM. */ 1382 /* */ 1383 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1384 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1385 /* */ 1386 /* Returns: */ 1387 /* 0 on success and the 32 bit value read, positive value on failure. */ 1388 /****************************************************************************/ 1389 int 1390 bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, 1391 u_int8_t *ret_val, u_int32_t cmd_flags) 1392 { 1393 u_int32_t cmd; 1394 int i, rc = 0; 1395 1396 /* Build the command word. */ 1397 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1398 1399 /* Calculate the offset for buffered flash if translation is used. */ 1400 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1401 offset = ((offset / sc->bnx_flash_info->page_size) << 1402 sc->bnx_flash_info->page_bits) + 1403 (offset % sc->bnx_flash_info->page_size); 1404 } 1405 1406 /* 1407 * Clear the DONE bit separately, set the address to read, 1408 * and issue the read. 1409 */ 1410 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1411 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1412 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1413 1414 /* Wait for completion. */ 1415 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1416 u_int32_t val; 1417 1418 DELAY(5); 1419 1420 val = REG_RD(sc, BNX_NVM_COMMAND); 1421 if (val & BNX_NVM_COMMAND_DONE) { 1422 val = REG_RD(sc, BNX_NVM_READ); 1423 1424 val = bnx_be32toh(val); 1425 memcpy(ret_val, &val, 4); 1426 break; 1427 } 1428 } 1429 1430 /* Check for errors. */ 1431 if (i >= NVRAM_TIMEOUT_COUNT) { 1432 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1433 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1434 rc = EBUSY; 1435 } 1436 1437 return rc; 1438 } 1439 1440 #ifdef BNX_NVRAM_WRITE_SUPPORT 1441 /****************************************************************************/ 1442 /* Write a dword (32 bits) to NVRAM. */ 1443 /* */ 1444 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1445 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1446 /* enabled NVRAM write access. */ 1447 /* */ 1448 /* Returns: */ 1449 /* 0 on success, positive value on failure. */ 1450 /****************************************************************************/ 1451 int 1452 bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, 1453 u_int32_t cmd_flags) 1454 { 1455 u_int32_t cmd, val32; 1456 int j; 1457 1458 /* Build the command word. */ 1459 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1460 1461 /* Calculate the offset for buffered flash if translation is used. */ 1462 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1463 offset = ((offset / sc->bnx_flash_info->page_size) << 1464 sc->bnx_flash_info->page_bits) + 1465 (offset % sc->bnx_flash_info->page_size); 1466 } 1467 1468 /* 1469 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1470 * set the NVRAM address to write, and issue the write command 1471 */ 1472 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1473 memcpy(&val32, val, 4); 1474 val32 = htobe32(val32); 1475 REG_WR(sc, BNX_NVM_WRITE, val32); 1476 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1477 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1478 1479 /* Wait for completion. */ 1480 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1481 DELAY(5); 1482 1483 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1484 break; 1485 } 1486 if (j >= NVRAM_TIMEOUT_COUNT) { 1487 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1488 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1489 return EBUSY; 1490 } 1491 1492 return 0; 1493 } 1494 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1495 1496 /****************************************************************************/ 1497 /* Initialize NVRAM access. */ 1498 /* */ 1499 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1500 /* access that device. */ 1501 /* */ 1502 /* Returns: */ 1503 /* 0 on success, positive value on failure. */ 1504 /****************************************************************************/ 1505 int 1506 bnx_init_nvram(struct bnx_softc *sc) 1507 { 1508 u_int32_t val; 1509 int j, entry_count, rc = 0; 1510 struct flash_spec *flash; 1511 1512 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1513 1514 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1515 sc->bnx_flash_info = &flash_5709; 1516 goto bnx_init_nvram_get_flash_size; 1517 } 1518 1519 /* Determine the selected interface. */ 1520 val = REG_RD(sc, BNX_NVM_CFG1); 1521 1522 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1523 1524 /* 1525 * Flash reconfiguration is required to support additional 1526 * NVRAM devices not directly supported in hardware. 1527 * Check if the flash interface was reconfigured 1528 * by the bootcode. 1529 */ 1530 1531 if (val & 0x40000000) { 1532 /* Flash interface reconfigured by bootcode. */ 1533 1534 DBPRINT(sc,BNX_INFO_LOAD, 1535 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1536 1537 for (j = 0, flash = &flash_table[0]; j < entry_count; 1538 j++, flash++) { 1539 if ((val & FLASH_BACKUP_STRAP_MASK) == 1540 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1541 sc->bnx_flash_info = flash; 1542 break; 1543 } 1544 } 1545 } else { 1546 /* Flash interface not yet reconfigured. */ 1547 u_int32_t mask; 1548 1549 DBPRINT(sc,BNX_INFO_LOAD, 1550 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1551 1552 if (val & (1 << 23)) 1553 mask = FLASH_BACKUP_STRAP_MASK; 1554 else 1555 mask = FLASH_STRAP_MASK; 1556 1557 /* Look for the matching NVRAM device configuration data. */ 1558 for (j = 0, flash = &flash_table[0]; j < entry_count; 1559 j++, flash++) { 1560 /* Check if the dev matches any of the known devices. */ 1561 if ((val & mask) == (flash->strapping & mask)) { 1562 /* Found a device match. */ 1563 sc->bnx_flash_info = flash; 1564 1565 /* Request access to the flash interface. */ 1566 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1567 return rc; 1568 1569 /* Reconfigure the flash interface. */ 1570 bnx_enable_nvram_access(sc); 1571 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1572 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1573 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1574 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1575 bnx_disable_nvram_access(sc); 1576 bnx_release_nvram_lock(sc); 1577 1578 break; 1579 } 1580 } 1581 } 1582 1583 /* Check if a matching device was found. */ 1584 if (j == entry_count) { 1585 sc->bnx_flash_info = NULL; 1586 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1587 __FILE__, __LINE__); 1588 rc = ENODEV; 1589 } 1590 1591 bnx_init_nvram_get_flash_size: 1592 /* Write the flash config data to the shared memory interface. */ 1593 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1594 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1595 if (val) 1596 sc->bnx_flash_size = val; 1597 else 1598 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1599 1600 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1601 "0x%08X\n", sc->bnx_flash_info->total_size); 1602 1603 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1604 1605 return rc; 1606 } 1607 1608 /****************************************************************************/ 1609 /* Read an arbitrary range of data from NVRAM. */ 1610 /* */ 1611 /* Prepares the NVRAM interface for access and reads the requested data */ 1612 /* into the supplied buffer. */ 1613 /* */ 1614 /* Returns: */ 1615 /* 0 on success and the data read, positive value on failure. */ 1616 /****************************************************************************/ 1617 int 1618 bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, 1619 int buf_size) 1620 { 1621 int rc = 0; 1622 u_int32_t cmd_flags, offset32, len32, extra; 1623 1624 if (buf_size == 0) 1625 return 0; 1626 1627 /* Request access to the flash interface. */ 1628 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1629 return rc; 1630 1631 /* Enable access to flash interface */ 1632 bnx_enable_nvram_access(sc); 1633 1634 len32 = buf_size; 1635 offset32 = offset; 1636 extra = 0; 1637 1638 cmd_flags = 0; 1639 1640 if (offset32 & 3) { 1641 u_int8_t buf[4]; 1642 u_int32_t pre_len; 1643 1644 offset32 &= ~3; 1645 pre_len = 4 - (offset & 3); 1646 1647 if (pre_len >= len32) { 1648 pre_len = len32; 1649 cmd_flags = 1650 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1651 } else 1652 cmd_flags = BNX_NVM_COMMAND_FIRST; 1653 1654 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1655 1656 if (rc) 1657 return rc; 1658 1659 memcpy(ret_buf, buf + (offset & 3), pre_len); 1660 1661 offset32 += 4; 1662 ret_buf += pre_len; 1663 len32 -= pre_len; 1664 } 1665 1666 if (len32 & 3) { 1667 extra = 4 - (len32 & 3); 1668 len32 = (len32 + 4) & ~3; 1669 } 1670 1671 if (len32 == 4) { 1672 u_int8_t buf[4]; 1673 1674 if (cmd_flags) 1675 cmd_flags = BNX_NVM_COMMAND_LAST; 1676 else 1677 cmd_flags = 1678 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1679 1680 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1681 1682 memcpy(ret_buf, buf, 4 - extra); 1683 } else if (len32 > 0) { 1684 u_int8_t buf[4]; 1685 1686 /* Read the first word. */ 1687 if (cmd_flags) 1688 cmd_flags = 0; 1689 else 1690 cmd_flags = BNX_NVM_COMMAND_FIRST; 1691 1692 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1693 1694 /* Advance to the next dword. */ 1695 offset32 += 4; 1696 ret_buf += 4; 1697 len32 -= 4; 1698 1699 while (len32 > 4 && rc == 0) { 1700 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1701 1702 /* Advance to the next dword. */ 1703 offset32 += 4; 1704 ret_buf += 4; 1705 len32 -= 4; 1706 } 1707 1708 if (rc) 1709 return rc; 1710 1711 cmd_flags = BNX_NVM_COMMAND_LAST; 1712 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1713 1714 memcpy(ret_buf, buf, 4 - extra); 1715 } 1716 1717 /* Disable access to flash interface and release the lock. */ 1718 bnx_disable_nvram_access(sc); 1719 bnx_release_nvram_lock(sc); 1720 1721 return rc; 1722 } 1723 1724 #ifdef BNX_NVRAM_WRITE_SUPPORT 1725 /****************************************************************************/ 1726 /* Write an arbitrary range of data from NVRAM. */ 1727 /* */ 1728 /* Prepares the NVRAM interface for write access and writes the requested */ 1729 /* data from the supplied buffer. The caller is responsible for */ 1730 /* calculating any appropriate CRCs. */ 1731 /* */ 1732 /* Returns: */ 1733 /* 0 on success, positive value on failure. */ 1734 /****************************************************************************/ 1735 int 1736 bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, 1737 int buf_size) 1738 { 1739 u_int32_t written, offset32, len32; 1740 u_int8_t *buf, start[4], end[4]; 1741 int rc = 0; 1742 int align_start, align_end; 1743 1744 buf = data_buf; 1745 offset32 = offset; 1746 len32 = buf_size; 1747 align_start = align_end = 0; 1748 1749 if ((align_start = (offset32 & 3))) { 1750 offset32 &= ~3; 1751 len32 += align_start; 1752 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1753 return rc; 1754 } 1755 1756 if (len32 & 3) { 1757 if ((len32 > 4) || !align_start) { 1758 align_end = 4 - (len32 & 3); 1759 len32 += align_end; 1760 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1761 end, 4))) 1762 return rc; 1763 } 1764 } 1765 1766 if (align_start || align_end) { 1767 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1768 if (buf == 0) 1769 return ENOMEM; 1770 1771 if (align_start) 1772 memcpy(buf, start, 4); 1773 1774 if (align_end) 1775 memcpy(buf + len32 - 4, end, 4); 1776 1777 memcpy(buf + align_start, data_buf, buf_size); 1778 } 1779 1780 written = 0; 1781 while ((written < len32) && (rc == 0)) { 1782 u_int32_t page_start, page_end, data_start, data_end; 1783 u_int32_t addr, cmd_flags; 1784 int i; 1785 u_int8_t flash_buffer[264]; 1786 1787 /* Find the page_start addr */ 1788 page_start = offset32 + written; 1789 page_start -= (page_start % sc->bnx_flash_info->page_size); 1790 /* Find the page_end addr */ 1791 page_end = page_start + sc->bnx_flash_info->page_size; 1792 /* Find the data_start addr */ 1793 data_start = (written == 0) ? offset32 : page_start; 1794 /* Find the data_end addr */ 1795 data_end = (page_end > offset32 + len32) ? 1796 (offset32 + len32) : page_end; 1797 1798 /* Request access to the flash interface. */ 1799 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1800 goto nvram_write_end; 1801 1802 /* Enable access to flash interface */ 1803 bnx_enable_nvram_access(sc); 1804 1805 cmd_flags = BNX_NVM_COMMAND_FIRST; 1806 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1807 int j; 1808 1809 /* Read the whole page into the buffer 1810 * (non-buffer flash only) */ 1811 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1812 if (j == (sc->bnx_flash_info->page_size - 4)) 1813 cmd_flags |= BNX_NVM_COMMAND_LAST; 1814 1815 rc = bnx_nvram_read_dword(sc, 1816 page_start + j, 1817 &flash_buffer[j], 1818 cmd_flags); 1819 1820 if (rc) 1821 goto nvram_write_end; 1822 1823 cmd_flags = 0; 1824 } 1825 } 1826 1827 /* Enable writes to flash interface (unlock write-protect) */ 1828 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1829 goto nvram_write_end; 1830 1831 /* Erase the page */ 1832 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1833 goto nvram_write_end; 1834 1835 /* Re-enable the write again for the actual write */ 1836 bnx_enable_nvram_write(sc); 1837 1838 /* Loop to write back the buffer data from page_start to 1839 * data_start */ 1840 i = 0; 1841 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1842 for (addr = page_start; addr < data_start; 1843 addr += 4, i += 4) { 1844 1845 rc = bnx_nvram_write_dword(sc, addr, 1846 &flash_buffer[i], cmd_flags); 1847 1848 if (rc != 0) 1849 goto nvram_write_end; 1850 1851 cmd_flags = 0; 1852 } 1853 } 1854 1855 /* Loop to write the new data from data_start to data_end */ 1856 for (addr = data_start; addr < data_end; addr += 4, i++) { 1857 if ((addr == page_end - 4) || 1858 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1859 && (addr == data_end - 4))) { 1860 1861 cmd_flags |= BNX_NVM_COMMAND_LAST; 1862 } 1863 1864 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1865 1866 if (rc != 0) 1867 goto nvram_write_end; 1868 1869 cmd_flags = 0; 1870 buf += 4; 1871 } 1872 1873 /* Loop to write back the buffer data from data_end 1874 * to page_end */ 1875 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1876 for (addr = data_end; addr < page_end; 1877 addr += 4, i += 4) { 1878 1879 if (addr == page_end-4) 1880 cmd_flags = BNX_NVM_COMMAND_LAST; 1881 1882 rc = bnx_nvram_write_dword(sc, addr, 1883 &flash_buffer[i], cmd_flags); 1884 1885 if (rc != 0) 1886 goto nvram_write_end; 1887 1888 cmd_flags = 0; 1889 } 1890 } 1891 1892 /* Disable writes to flash interface (lock write-protect) */ 1893 bnx_disable_nvram_write(sc); 1894 1895 /* Disable access to flash interface */ 1896 bnx_disable_nvram_access(sc); 1897 bnx_release_nvram_lock(sc); 1898 1899 /* Increment written */ 1900 written += data_end - data_start; 1901 } 1902 1903 nvram_write_end: 1904 if (align_start || align_end) 1905 free(buf, M_DEVBUF); 1906 1907 return rc; 1908 } 1909 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1910 1911 /****************************************************************************/ 1912 /* Verifies that NVRAM is accessible and contains valid data. */ 1913 /* */ 1914 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1915 /* correct. */ 1916 /* */ 1917 /* Returns: */ 1918 /* 0 on success, positive value on failure. */ 1919 /****************************************************************************/ 1920 int 1921 bnx_nvram_test(struct bnx_softc *sc) 1922 { 1923 u_int32_t buf[BNX_NVRAM_SIZE / 4]; 1924 u_int8_t *data = (u_int8_t *) buf; 1925 int rc = 0; 1926 u_int32_t magic, csum; 1927 1928 /* 1929 * Check that the device NVRAM is valid by reading 1930 * the magic value at offset 0. 1931 */ 1932 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1933 goto bnx_nvram_test_done; 1934 1935 magic = bnx_be32toh(buf[0]); 1936 if (magic != BNX_NVRAM_MAGIC) { 1937 rc = ENODEV; 1938 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1939 "Expected: 0x%08X, Found: 0x%08X\n", 1940 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1941 goto bnx_nvram_test_done; 1942 } 1943 1944 /* 1945 * Verify that the device NVRAM includes valid 1946 * configuration data. 1947 */ 1948 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1949 goto bnx_nvram_test_done; 1950 1951 csum = ether_crc32_le(data, 0x100); 1952 if (csum != BNX_CRC32_RESIDUAL) { 1953 rc = ENODEV; 1954 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1955 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1956 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1957 goto bnx_nvram_test_done; 1958 } 1959 1960 csum = ether_crc32_le(data + 0x100, 0x100); 1961 if (csum != BNX_CRC32_RESIDUAL) { 1962 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1963 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1964 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1965 rc = ENODEV; 1966 } 1967 1968 bnx_nvram_test_done: 1969 return rc; 1970 } 1971 1972 /****************************************************************************/ 1973 /* Identifies the current media type of the controller and sets the PHY */ 1974 /* address. */ 1975 /* */ 1976 /* Returns: */ 1977 /* Nothing. */ 1978 /****************************************************************************/ 1979 void 1980 bnx_get_media(struct bnx_softc *sc) 1981 { 1982 sc->bnx_phy_addr = 1; 1983 1984 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1985 u_int32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 1986 u_int32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 1987 u_int32_t strap; 1988 1989 /* 1990 * The BCM5709S is software configurable 1991 * for Copper or SerDes operation. 1992 */ 1993 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 1994 DBPRINT(sc, BNX_INFO_LOAD, 1995 "5709 bonded for copper.\n"); 1996 goto bnx_get_media_exit; 1997 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 1998 DBPRINT(sc, BNX_INFO_LOAD, 1999 "5709 bonded for dual media.\n"); 2000 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2001 goto bnx_get_media_exit; 2002 } 2003 2004 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2005 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2006 else { 2007 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2008 >> 8; 2009 } 2010 2011 if (sc->bnx_pa.pa_function == 0) { 2012 switch (strap) { 2013 case 0x4: 2014 case 0x5: 2015 case 0x6: 2016 DBPRINT(sc, BNX_INFO_LOAD, 2017 "BCM5709 s/w configured for SerDes.\n"); 2018 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2019 break; 2020 default: 2021 DBPRINT(sc, BNX_INFO_LOAD, 2022 "BCM5709 s/w configured for Copper.\n"); 2023 } 2024 } else { 2025 switch (strap) { 2026 case 0x1: 2027 case 0x2: 2028 case 0x4: 2029 DBPRINT(sc, BNX_INFO_LOAD, 2030 "BCM5709 s/w configured for SerDes.\n"); 2031 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2032 break; 2033 default: 2034 DBPRINT(sc, BNX_INFO_LOAD, 2035 "BCM5709 s/w configured for Copper.\n"); 2036 } 2037 } 2038 2039 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2040 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2041 2042 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2043 u_int32_t val; 2044 2045 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2046 2047 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2048 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2049 2050 /* 2051 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2052 * separate PHY for SerDes. 2053 */ 2054 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2055 sc->bnx_phy_addr = 2; 2056 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2057 BNX_SHARED_HW_CFG_CONFIG); 2058 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2059 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2060 DBPRINT(sc, BNX_INFO_LOAD, 2061 "Found 2.5Gb capable adapter\n"); 2062 } 2063 } 2064 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2065 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2066 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2067 2068 bnx_get_media_exit: 2069 DBPRINT(sc, (BNX_INFO_LOAD), 2070 "Using PHY address %d.\n", sc->bnx_phy_addr); 2071 } 2072 2073 /****************************************************************************/ 2074 /* Performs PHY initialization required before MII drivers access the */ 2075 /* device. */ 2076 /* */ 2077 /* Returns: */ 2078 /* Nothing. */ 2079 /****************************************************************************/ 2080 void 2081 bnx_init_media(struct bnx_softc *sc) 2082 { 2083 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2084 /* 2085 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2086 * IEEE Clause 22 method. Otherwise we have no way to attach 2087 * the PHY to the mii(4) layer. PHY specific configuration 2088 * is done by the mii(4) layer. 2089 */ 2090 2091 /* Select auto-negotiation MMD of the PHY. */ 2092 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2093 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2094 2095 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2096 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2097 2098 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2099 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2100 } 2101 } 2102 2103 /****************************************************************************/ 2104 /* Free any DMA memory owned by the driver. */ 2105 /* */ 2106 /* Scans through each data structre that requires DMA memory and frees */ 2107 /* the memory if allocated. */ 2108 /* */ 2109 /* Returns: */ 2110 /* Nothing. */ 2111 /****************************************************************************/ 2112 void 2113 bnx_dma_free(struct bnx_softc *sc) 2114 { 2115 int i; 2116 2117 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2118 2119 /* Destroy the status block. */ 2120 if (sc->status_block != NULL && sc->status_map != NULL) { 2121 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2122 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2123 BNX_STATUS_BLK_SZ); 2124 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2125 sc->status_rseg); 2126 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2127 sc->status_block = NULL; 2128 sc->status_map = NULL; 2129 } 2130 2131 /* Destroy the statistics block. */ 2132 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2133 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2134 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2135 BNX_STATS_BLK_SZ); 2136 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2137 sc->stats_rseg); 2138 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2139 sc->stats_block = NULL; 2140 sc->stats_map = NULL; 2141 } 2142 2143 /* Free, unmap and destroy all context memory pages. */ 2144 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2145 for (i = 0; i < sc->ctx_pages; i++) { 2146 if (sc->ctx_block[i] != NULL) { 2147 bus_dmamap_unload(sc->bnx_dmatag, 2148 sc->ctx_map[i]); 2149 bus_dmamem_unmap(sc->bnx_dmatag, 2150 (void *)sc->ctx_block[i], 2151 BCM_PAGE_SIZE); 2152 bus_dmamem_free(sc->bnx_dmatag, 2153 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2154 bus_dmamap_destroy(sc->bnx_dmatag, 2155 sc->ctx_map[i]); 2156 sc->ctx_block[i] = NULL; 2157 } 2158 } 2159 } 2160 2161 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2162 for (i = 0; i < TX_PAGES; i++ ) { 2163 if (sc->tx_bd_chain[i] != NULL && 2164 sc->tx_bd_chain_map[i] != NULL) { 2165 bus_dmamap_unload(sc->bnx_dmatag, 2166 sc->tx_bd_chain_map[i]); 2167 bus_dmamem_unmap(sc->bnx_dmatag, 2168 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2169 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2170 sc->tx_bd_chain_rseg[i]); 2171 bus_dmamap_destroy(sc->bnx_dmatag, 2172 sc->tx_bd_chain_map[i]); 2173 sc->tx_bd_chain[i] = NULL; 2174 sc->tx_bd_chain_map[i] = NULL; 2175 } 2176 } 2177 2178 /* Destroy the TX dmamaps. */ 2179 /* This isn't necessary since we dont allocate them up front */ 2180 2181 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2182 for (i = 0; i < RX_PAGES; i++ ) { 2183 if (sc->rx_bd_chain[i] != NULL && 2184 sc->rx_bd_chain_map[i] != NULL) { 2185 bus_dmamap_unload(sc->bnx_dmatag, 2186 sc->rx_bd_chain_map[i]); 2187 bus_dmamem_unmap(sc->bnx_dmatag, 2188 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2189 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2190 sc->rx_bd_chain_rseg[i]); 2191 2192 bus_dmamap_destroy(sc->bnx_dmatag, 2193 sc->rx_bd_chain_map[i]); 2194 sc->rx_bd_chain[i] = NULL; 2195 sc->rx_bd_chain_map[i] = NULL; 2196 } 2197 } 2198 2199 /* Unload and destroy the RX mbuf maps. */ 2200 for (i = 0; i < TOTAL_RX_BD; i++) { 2201 if (sc->rx_mbuf_map[i] != NULL) { 2202 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2203 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2204 } 2205 } 2206 2207 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2208 } 2209 2210 /****************************************************************************/ 2211 /* Allocate any DMA memory needed by the driver. */ 2212 /* */ 2213 /* Allocates DMA memory needed for the various global structures needed by */ 2214 /* hardware. */ 2215 /* */ 2216 /* Returns: */ 2217 /* 0 for success, positive value for failure. */ 2218 /****************************************************************************/ 2219 int 2220 bnx_dma_alloc(struct bnx_softc *sc) 2221 { 2222 int i, rc = 0; 2223 2224 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2225 2226 /* 2227 * Allocate DMA memory for the status block, map the memory into DMA 2228 * space, and fetch the physical address of the block. 2229 */ 2230 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2231 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2232 aprint_error_dev(sc->bnx_dev, 2233 "Could not create status block DMA map!\n"); 2234 rc = ENOMEM; 2235 goto bnx_dma_alloc_exit; 2236 } 2237 2238 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2239 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2240 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2241 aprint_error_dev(sc->bnx_dev, 2242 "Could not allocate status block DMA memory!\n"); 2243 rc = ENOMEM; 2244 goto bnx_dma_alloc_exit; 2245 } 2246 2247 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2248 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2249 aprint_error_dev(sc->bnx_dev, 2250 "Could not map status block DMA memory!\n"); 2251 rc = ENOMEM; 2252 goto bnx_dma_alloc_exit; 2253 } 2254 2255 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2256 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2257 aprint_error_dev(sc->bnx_dev, 2258 "Could not load status block DMA memory!\n"); 2259 rc = ENOMEM; 2260 goto bnx_dma_alloc_exit; 2261 } 2262 2263 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2264 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2265 2266 /* DRC - Fix for 64 bit addresses. */ 2267 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2268 (u_int32_t) sc->status_block_paddr); 2269 2270 /* BCM5709 uses host memory as cache for context memory. */ 2271 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2272 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2273 if (sc->ctx_pages == 0) 2274 sc->ctx_pages = 1; 2275 if (sc->ctx_pages > 4) /* XXX */ 2276 sc->ctx_pages = 4; 2277 2278 DBRUNIF((sc->ctx_pages > 512), 2279 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2280 __FILE__, __LINE__, sc->ctx_pages)); 2281 2282 2283 for (i = 0; i < sc->ctx_pages; i++) { 2284 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2285 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2286 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2287 &sc->ctx_map[i]) != 0) { 2288 rc = ENOMEM; 2289 goto bnx_dma_alloc_exit; 2290 } 2291 2292 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2293 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2294 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2295 rc = ENOMEM; 2296 goto bnx_dma_alloc_exit; 2297 } 2298 2299 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2300 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2301 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2302 rc = ENOMEM; 2303 goto bnx_dma_alloc_exit; 2304 } 2305 2306 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2307 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2308 BUS_DMA_NOWAIT) != 0) { 2309 rc = ENOMEM; 2310 goto bnx_dma_alloc_exit; 2311 } 2312 2313 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2314 } 2315 } 2316 2317 /* 2318 * Allocate DMA memory for the statistics block, map the memory into 2319 * DMA space, and fetch the physical address of the block. 2320 */ 2321 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2322 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2323 aprint_error_dev(sc->bnx_dev, 2324 "Could not create stats block DMA map!\n"); 2325 rc = ENOMEM; 2326 goto bnx_dma_alloc_exit; 2327 } 2328 2329 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2330 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2331 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2332 aprint_error_dev(sc->bnx_dev, 2333 "Could not allocate stats block DMA memory!\n"); 2334 rc = ENOMEM; 2335 goto bnx_dma_alloc_exit; 2336 } 2337 2338 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2339 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2340 aprint_error_dev(sc->bnx_dev, 2341 "Could not map stats block DMA memory!\n"); 2342 rc = ENOMEM; 2343 goto bnx_dma_alloc_exit; 2344 } 2345 2346 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2347 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2348 aprint_error_dev(sc->bnx_dev, 2349 "Could not load status block DMA memory!\n"); 2350 rc = ENOMEM; 2351 goto bnx_dma_alloc_exit; 2352 } 2353 2354 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2355 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2356 2357 /* DRC - Fix for 64 bit address. */ 2358 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2359 (u_int32_t) sc->stats_block_paddr); 2360 2361 /* 2362 * Allocate DMA memory for the TX buffer descriptor chain, 2363 * and fetch the physical address of the block. 2364 */ 2365 for (i = 0; i < TX_PAGES; i++) { 2366 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2367 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2368 &sc->tx_bd_chain_map[i])) { 2369 aprint_error_dev(sc->bnx_dev, 2370 "Could not create Tx desc %d DMA map!\n", i); 2371 rc = ENOMEM; 2372 goto bnx_dma_alloc_exit; 2373 } 2374 2375 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2376 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2377 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2378 aprint_error_dev(sc->bnx_dev, 2379 "Could not allocate TX desc %d DMA memory!\n", 2380 i); 2381 rc = ENOMEM; 2382 goto bnx_dma_alloc_exit; 2383 } 2384 2385 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2386 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2387 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2388 aprint_error_dev(sc->bnx_dev, 2389 "Could not map TX desc %d DMA memory!\n", i); 2390 rc = ENOMEM; 2391 goto bnx_dma_alloc_exit; 2392 } 2393 2394 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2395 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2396 BUS_DMA_NOWAIT)) { 2397 aprint_error_dev(sc->bnx_dev, 2398 "Could not load TX desc %d DMA memory!\n", i); 2399 rc = ENOMEM; 2400 goto bnx_dma_alloc_exit; 2401 } 2402 2403 sc->tx_bd_chain_paddr[i] = 2404 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2405 2406 /* DRC - Fix for 64 bit systems. */ 2407 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2408 i, (u_int32_t) sc->tx_bd_chain_paddr[i]); 2409 } 2410 2411 /* 2412 * Create lists to hold TX mbufs. 2413 */ 2414 TAILQ_INIT(&sc->tx_free_pkts); 2415 TAILQ_INIT(&sc->tx_used_pkts); 2416 sc->tx_pkt_count = 0; 2417 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2418 2419 /* 2420 * Allocate DMA memory for the Rx buffer descriptor chain, 2421 * and fetch the physical address of the block. 2422 */ 2423 for (i = 0; i < RX_PAGES; i++) { 2424 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2425 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2426 &sc->rx_bd_chain_map[i])) { 2427 aprint_error_dev(sc->bnx_dev, 2428 "Could not create Rx desc %d DMA map!\n", i); 2429 rc = ENOMEM; 2430 goto bnx_dma_alloc_exit; 2431 } 2432 2433 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2434 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2435 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2436 aprint_error_dev(sc->bnx_dev, 2437 "Could not allocate Rx desc %d DMA memory!\n", i); 2438 rc = ENOMEM; 2439 goto bnx_dma_alloc_exit; 2440 } 2441 2442 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2443 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2444 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2445 aprint_error_dev(sc->bnx_dev, 2446 "Could not map Rx desc %d DMA memory!\n", i); 2447 rc = ENOMEM; 2448 goto bnx_dma_alloc_exit; 2449 } 2450 2451 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2452 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2453 BUS_DMA_NOWAIT)) { 2454 aprint_error_dev(sc->bnx_dev, 2455 "Could not load Rx desc %d DMA memory!\n", i); 2456 rc = ENOMEM; 2457 goto bnx_dma_alloc_exit; 2458 } 2459 2460 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2461 sc->rx_bd_chain_paddr[i] = 2462 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2463 2464 /* DRC - Fix for 64 bit systems. */ 2465 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2466 i, (u_int32_t) sc->rx_bd_chain_paddr[i]); 2467 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2468 0, BNX_RX_CHAIN_PAGE_SZ, 2469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2470 } 2471 2472 /* 2473 * Create DMA maps for the Rx buffer mbufs. 2474 */ 2475 for (i = 0; i < TOTAL_RX_BD; i++) { 2476 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2477 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2478 &sc->rx_mbuf_map[i])) { 2479 aprint_error_dev(sc->bnx_dev, 2480 "Could not create Rx mbuf %d DMA map!\n", i); 2481 rc = ENOMEM; 2482 goto bnx_dma_alloc_exit; 2483 } 2484 } 2485 2486 bnx_dma_alloc_exit: 2487 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2488 2489 return rc; 2490 } 2491 2492 /****************************************************************************/ 2493 /* Release all resources used by the driver. */ 2494 /* */ 2495 /* Releases all resources acquired by the driver including interrupts, */ 2496 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2497 /* */ 2498 /* Returns: */ 2499 /* Nothing. */ 2500 /****************************************************************************/ 2501 void 2502 bnx_release_resources(struct bnx_softc *sc) 2503 { 2504 struct pci_attach_args *pa = &(sc->bnx_pa); 2505 2506 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2507 2508 bnx_dma_free(sc); 2509 2510 if (sc->bnx_intrhand != NULL) 2511 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2512 2513 if (sc->bnx_size) 2514 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2515 2516 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2517 } 2518 2519 /****************************************************************************/ 2520 /* Firmware synchronization. */ 2521 /* */ 2522 /* Before performing certain events such as a chip reset, synchronize with */ 2523 /* the firmware first. */ 2524 /* */ 2525 /* Returns: */ 2526 /* 0 for success, positive value for failure. */ 2527 /****************************************************************************/ 2528 int 2529 bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) 2530 { 2531 int i, rc = 0; 2532 u_int32_t val; 2533 2534 /* Don't waste any time if we've timed out before. */ 2535 if (sc->bnx_fw_timed_out) { 2536 rc = EBUSY; 2537 goto bnx_fw_sync_exit; 2538 } 2539 2540 /* Increment the message sequence number. */ 2541 sc->bnx_fw_wr_seq++; 2542 msg_data |= sc->bnx_fw_wr_seq; 2543 2544 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2545 msg_data); 2546 2547 /* Send the message to the bootcode driver mailbox. */ 2548 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2549 2550 /* Wait for the bootcode to acknowledge the message. */ 2551 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2552 /* Check for a response in the bootcode firmware mailbox. */ 2553 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2554 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2555 break; 2556 DELAY(1000); 2557 } 2558 2559 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2560 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2561 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2562 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2563 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2564 2565 msg_data &= ~BNX_DRV_MSG_CODE; 2566 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2567 2568 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2569 2570 sc->bnx_fw_timed_out = 1; 2571 rc = EBUSY; 2572 } 2573 2574 bnx_fw_sync_exit: 2575 return rc; 2576 } 2577 2578 /****************************************************************************/ 2579 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2580 /* */ 2581 /* Returns: */ 2582 /* Nothing. */ 2583 /****************************************************************************/ 2584 void 2585 bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, 2586 u_int32_t rv2p_code_len, u_int32_t rv2p_proc) 2587 { 2588 int i; 2589 u_int32_t val; 2590 2591 /* Set the page size used by RV2P. */ 2592 if (rv2p_proc == RV2P_PROC2) { 2593 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2594 USABLE_RX_BD_PER_PAGE); 2595 } 2596 2597 for (i = 0; i < rv2p_code_len; i += 8) { 2598 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2599 rv2p_code++; 2600 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2601 rv2p_code++; 2602 2603 if (rv2p_proc == RV2P_PROC1) { 2604 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2605 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2606 } else { 2607 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2608 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2609 } 2610 } 2611 2612 /* Reset the processor, un-stall is done later. */ 2613 if (rv2p_proc == RV2P_PROC1) 2614 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2615 else 2616 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2617 } 2618 2619 /****************************************************************************/ 2620 /* Load RISC processor firmware. */ 2621 /* */ 2622 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2623 /* associated with a particular processor. */ 2624 /* */ 2625 /* Returns: */ 2626 /* Nothing. */ 2627 /****************************************************************************/ 2628 void 2629 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2630 struct fw_info *fw) 2631 { 2632 u_int32_t offset; 2633 u_int32_t val; 2634 2635 /* Halt the CPU. */ 2636 val = REG_RD_IND(sc, cpu_reg->mode); 2637 val |= cpu_reg->mode_value_halt; 2638 REG_WR_IND(sc, cpu_reg->mode, val); 2639 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2640 2641 /* Load the Text area. */ 2642 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2643 if (fw->text) { 2644 int j; 2645 2646 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2647 REG_WR_IND(sc, offset, fw->text[j]); 2648 } 2649 2650 /* Load the Data area. */ 2651 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2652 if (fw->data) { 2653 int j; 2654 2655 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2656 REG_WR_IND(sc, offset, fw->data[j]); 2657 } 2658 2659 /* Load the SBSS area. */ 2660 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2661 if (fw->sbss) { 2662 int j; 2663 2664 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2665 REG_WR_IND(sc, offset, fw->sbss[j]); 2666 } 2667 2668 /* Load the BSS area. */ 2669 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2670 if (fw->bss) { 2671 int j; 2672 2673 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2674 REG_WR_IND(sc, offset, fw->bss[j]); 2675 } 2676 2677 /* Load the Read-Only area. */ 2678 offset = cpu_reg->spad_base + 2679 (fw->rodata_addr - cpu_reg->mips_view_base); 2680 if (fw->rodata) { 2681 int j; 2682 2683 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2684 REG_WR_IND(sc, offset, fw->rodata[j]); 2685 } 2686 2687 /* Clear the pre-fetch instruction. */ 2688 REG_WR_IND(sc, cpu_reg->inst, 0); 2689 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2690 2691 /* Start the CPU. */ 2692 val = REG_RD_IND(sc, cpu_reg->mode); 2693 val &= ~cpu_reg->mode_value_halt; 2694 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2695 REG_WR_IND(sc, cpu_reg->mode, val); 2696 } 2697 2698 /****************************************************************************/ 2699 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2700 /* */ 2701 /* Loads the firmware for each CPU and starts the CPU. */ 2702 /* */ 2703 /* Returns: */ 2704 /* Nothing. */ 2705 /****************************************************************************/ 2706 void 2707 bnx_init_cpus(struct bnx_softc *sc) 2708 { 2709 struct cpu_reg cpu_reg; 2710 struct fw_info fw; 2711 2712 switch(BNX_CHIP_NUM(sc)) { 2713 case BNX_CHIP_NUM_5709: 2714 /* Initialize the RV2P processor. */ 2715 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2716 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2717 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2718 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2719 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2720 } else { 2721 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2722 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2723 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2724 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2725 } 2726 2727 /* Initialize the RX Processor. */ 2728 cpu_reg.mode = BNX_RXP_CPU_MODE; 2729 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2730 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2731 cpu_reg.state = BNX_RXP_CPU_STATE; 2732 cpu_reg.state_value_clear = 0xffffff; 2733 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2734 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2735 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2736 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2737 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2738 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2739 cpu_reg.mips_view_base = 0x8000000; 2740 2741 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2742 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2743 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2744 fw.start_addr = bnx_RXP_b09FwStartAddr; 2745 2746 fw.text_addr = bnx_RXP_b09FwTextAddr; 2747 fw.text_len = bnx_RXP_b09FwTextLen; 2748 fw.text_index = 0; 2749 fw.text = bnx_RXP_b09FwText; 2750 2751 fw.data_addr = bnx_RXP_b09FwDataAddr; 2752 fw.data_len = bnx_RXP_b09FwDataLen; 2753 fw.data_index = 0; 2754 fw.data = bnx_RXP_b09FwData; 2755 2756 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2757 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2758 fw.sbss_index = 0; 2759 fw.sbss = bnx_RXP_b09FwSbss; 2760 2761 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2762 fw.bss_len = bnx_RXP_b09FwBssLen; 2763 fw.bss_index = 0; 2764 fw.bss = bnx_RXP_b09FwBss; 2765 2766 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2767 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2768 fw.rodata_index = 0; 2769 fw.rodata = bnx_RXP_b09FwRodata; 2770 2771 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2772 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2773 2774 /* Initialize the TX Processor. */ 2775 cpu_reg.mode = BNX_TXP_CPU_MODE; 2776 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2777 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2778 cpu_reg.state = BNX_TXP_CPU_STATE; 2779 cpu_reg.state_value_clear = 0xffffff; 2780 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2781 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2782 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2783 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2784 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2785 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2786 cpu_reg.mips_view_base = 0x8000000; 2787 2788 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2789 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2790 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2791 fw.start_addr = bnx_TXP_b09FwStartAddr; 2792 2793 fw.text_addr = bnx_TXP_b09FwTextAddr; 2794 fw.text_len = bnx_TXP_b09FwTextLen; 2795 fw.text_index = 0; 2796 fw.text = bnx_TXP_b09FwText; 2797 2798 fw.data_addr = bnx_TXP_b09FwDataAddr; 2799 fw.data_len = bnx_TXP_b09FwDataLen; 2800 fw.data_index = 0; 2801 fw.data = bnx_TXP_b09FwData; 2802 2803 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2804 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2805 fw.sbss_index = 0; 2806 fw.sbss = bnx_TXP_b09FwSbss; 2807 2808 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2809 fw.bss_len = bnx_TXP_b09FwBssLen; 2810 fw.bss_index = 0; 2811 fw.bss = bnx_TXP_b09FwBss; 2812 2813 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2814 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2815 fw.rodata_index = 0; 2816 fw.rodata = bnx_TXP_b09FwRodata; 2817 2818 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2819 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2820 2821 /* Initialize the TX Patch-up Processor. */ 2822 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2823 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2824 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2825 cpu_reg.state = BNX_TPAT_CPU_STATE; 2826 cpu_reg.state_value_clear = 0xffffff; 2827 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2828 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2829 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2830 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2831 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2832 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2833 cpu_reg.mips_view_base = 0x8000000; 2834 2835 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2836 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2837 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2838 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2839 2840 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2841 fw.text_len = bnx_TPAT_b09FwTextLen; 2842 fw.text_index = 0; 2843 fw.text = bnx_TPAT_b09FwText; 2844 2845 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2846 fw.data_len = bnx_TPAT_b09FwDataLen; 2847 fw.data_index = 0; 2848 fw.data = bnx_TPAT_b09FwData; 2849 2850 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2851 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2852 fw.sbss_index = 0; 2853 fw.sbss = bnx_TPAT_b09FwSbss; 2854 2855 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2856 fw.bss_len = bnx_TPAT_b09FwBssLen; 2857 fw.bss_index = 0; 2858 fw.bss = bnx_TPAT_b09FwBss; 2859 2860 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2861 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2862 fw.rodata_index = 0; 2863 fw.rodata = bnx_TPAT_b09FwRodata; 2864 2865 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2866 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2867 2868 /* Initialize the Completion Processor. */ 2869 cpu_reg.mode = BNX_COM_CPU_MODE; 2870 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2871 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2872 cpu_reg.state = BNX_COM_CPU_STATE; 2873 cpu_reg.state_value_clear = 0xffffff; 2874 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2875 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2876 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2877 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2878 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2879 cpu_reg.spad_base = BNX_COM_SCRATCH; 2880 cpu_reg.mips_view_base = 0x8000000; 2881 2882 fw.ver_major = bnx_COM_b09FwReleaseMajor; 2883 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 2884 fw.ver_fix = bnx_COM_b09FwReleaseFix; 2885 fw.start_addr = bnx_COM_b09FwStartAddr; 2886 2887 fw.text_addr = bnx_COM_b09FwTextAddr; 2888 fw.text_len = bnx_COM_b09FwTextLen; 2889 fw.text_index = 0; 2890 fw.text = bnx_COM_b09FwText; 2891 2892 fw.data_addr = bnx_COM_b09FwDataAddr; 2893 fw.data_len = bnx_COM_b09FwDataLen; 2894 fw.data_index = 0; 2895 fw.data = bnx_COM_b09FwData; 2896 2897 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 2898 fw.sbss_len = bnx_COM_b09FwSbssLen; 2899 fw.sbss_index = 0; 2900 fw.sbss = bnx_COM_b09FwSbss; 2901 2902 fw.bss_addr = bnx_COM_b09FwBssAddr; 2903 fw.bss_len = bnx_COM_b09FwBssLen; 2904 fw.bss_index = 0; 2905 fw.bss = bnx_COM_b09FwBss; 2906 2907 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 2908 fw.rodata_len = bnx_COM_b09FwRodataLen; 2909 fw.rodata_index = 0; 2910 fw.rodata = bnx_COM_b09FwRodata; 2911 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2912 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2913 break; 2914 default: 2915 /* Initialize the RV2P processor. */ 2916 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2917 RV2P_PROC1); 2918 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2919 RV2P_PROC2); 2920 2921 /* Initialize the RX Processor. */ 2922 cpu_reg.mode = BNX_RXP_CPU_MODE; 2923 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2924 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2925 cpu_reg.state = BNX_RXP_CPU_STATE; 2926 cpu_reg.state_value_clear = 0xffffff; 2927 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2928 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2929 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2930 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2931 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2932 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2933 cpu_reg.mips_view_base = 0x8000000; 2934 2935 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2936 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2937 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2938 fw.start_addr = bnx_RXP_b06FwStartAddr; 2939 2940 fw.text_addr = bnx_RXP_b06FwTextAddr; 2941 fw.text_len = bnx_RXP_b06FwTextLen; 2942 fw.text_index = 0; 2943 fw.text = bnx_RXP_b06FwText; 2944 2945 fw.data_addr = bnx_RXP_b06FwDataAddr; 2946 fw.data_len = bnx_RXP_b06FwDataLen; 2947 fw.data_index = 0; 2948 fw.data = bnx_RXP_b06FwData; 2949 2950 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2951 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2952 fw.sbss_index = 0; 2953 fw.sbss = bnx_RXP_b06FwSbss; 2954 2955 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2956 fw.bss_len = bnx_RXP_b06FwBssLen; 2957 fw.bss_index = 0; 2958 fw.bss = bnx_RXP_b06FwBss; 2959 2960 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2961 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2962 fw.rodata_index = 0; 2963 fw.rodata = bnx_RXP_b06FwRodata; 2964 2965 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2966 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2967 2968 /* Initialize the TX Processor. */ 2969 cpu_reg.mode = BNX_TXP_CPU_MODE; 2970 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2971 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2972 cpu_reg.state = BNX_TXP_CPU_STATE; 2973 cpu_reg.state_value_clear = 0xffffff; 2974 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2975 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2976 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2977 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2978 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2979 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2980 cpu_reg.mips_view_base = 0x8000000; 2981 2982 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2983 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2984 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2985 fw.start_addr = bnx_TXP_b06FwStartAddr; 2986 2987 fw.text_addr = bnx_TXP_b06FwTextAddr; 2988 fw.text_len = bnx_TXP_b06FwTextLen; 2989 fw.text_index = 0; 2990 fw.text = bnx_TXP_b06FwText; 2991 2992 fw.data_addr = bnx_TXP_b06FwDataAddr; 2993 fw.data_len = bnx_TXP_b06FwDataLen; 2994 fw.data_index = 0; 2995 fw.data = bnx_TXP_b06FwData; 2996 2997 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2998 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2999 fw.sbss_index = 0; 3000 fw.sbss = bnx_TXP_b06FwSbss; 3001 3002 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3003 fw.bss_len = bnx_TXP_b06FwBssLen; 3004 fw.bss_index = 0; 3005 fw.bss = bnx_TXP_b06FwBss; 3006 3007 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3008 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3009 fw.rodata_index = 0; 3010 fw.rodata = bnx_TXP_b06FwRodata; 3011 3012 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3013 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3014 3015 /* Initialize the TX Patch-up Processor. */ 3016 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3017 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3018 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3019 cpu_reg.state = BNX_TPAT_CPU_STATE; 3020 cpu_reg.state_value_clear = 0xffffff; 3021 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3022 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3023 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3024 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3025 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3026 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3027 cpu_reg.mips_view_base = 0x8000000; 3028 3029 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3030 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3031 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3032 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3033 3034 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3035 fw.text_len = bnx_TPAT_b06FwTextLen; 3036 fw.text_index = 0; 3037 fw.text = bnx_TPAT_b06FwText; 3038 3039 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3040 fw.data_len = bnx_TPAT_b06FwDataLen; 3041 fw.data_index = 0; 3042 fw.data = bnx_TPAT_b06FwData; 3043 3044 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3045 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3046 fw.sbss_index = 0; 3047 fw.sbss = bnx_TPAT_b06FwSbss; 3048 3049 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3050 fw.bss_len = bnx_TPAT_b06FwBssLen; 3051 fw.bss_index = 0; 3052 fw.bss = bnx_TPAT_b06FwBss; 3053 3054 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3055 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3056 fw.rodata_index = 0; 3057 fw.rodata = bnx_TPAT_b06FwRodata; 3058 3059 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3060 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3061 3062 /* Initialize the Completion Processor. */ 3063 cpu_reg.mode = BNX_COM_CPU_MODE; 3064 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3065 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3066 cpu_reg.state = BNX_COM_CPU_STATE; 3067 cpu_reg.state_value_clear = 0xffffff; 3068 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3069 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3070 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3071 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3072 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3073 cpu_reg.spad_base = BNX_COM_SCRATCH; 3074 cpu_reg.mips_view_base = 0x8000000; 3075 3076 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3077 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3078 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3079 fw.start_addr = bnx_COM_b06FwStartAddr; 3080 3081 fw.text_addr = bnx_COM_b06FwTextAddr; 3082 fw.text_len = bnx_COM_b06FwTextLen; 3083 fw.text_index = 0; 3084 fw.text = bnx_COM_b06FwText; 3085 3086 fw.data_addr = bnx_COM_b06FwDataAddr; 3087 fw.data_len = bnx_COM_b06FwDataLen; 3088 fw.data_index = 0; 3089 fw.data = bnx_COM_b06FwData; 3090 3091 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3092 fw.sbss_len = bnx_COM_b06FwSbssLen; 3093 fw.sbss_index = 0; 3094 fw.sbss = bnx_COM_b06FwSbss; 3095 3096 fw.bss_addr = bnx_COM_b06FwBssAddr; 3097 fw.bss_len = bnx_COM_b06FwBssLen; 3098 fw.bss_index = 0; 3099 fw.bss = bnx_COM_b06FwBss; 3100 3101 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3102 fw.rodata_len = bnx_COM_b06FwRodataLen; 3103 fw.rodata_index = 0; 3104 fw.rodata = bnx_COM_b06FwRodata; 3105 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3106 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3107 break; 3108 } 3109 } 3110 3111 /****************************************************************************/ 3112 /* Initialize context memory. */ 3113 /* */ 3114 /* Clears the memory associated with each Context ID (CID). */ 3115 /* */ 3116 /* Returns: */ 3117 /* Nothing. */ 3118 /****************************************************************************/ 3119 void 3120 bnx_init_context(struct bnx_softc *sc) 3121 { 3122 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3123 /* DRC: Replace this constant value with a #define. */ 3124 int i, retry_cnt = 10; 3125 u_int32_t val; 3126 3127 /* 3128 * BCM5709 context memory may be cached 3129 * in host memory so prepare the host memory 3130 * for access. 3131 */ 3132 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3133 | (1 << 12); 3134 val |= (BCM_PAGE_BITS - 8) << 16; 3135 REG_WR(sc, BNX_CTX_COMMAND, val); 3136 3137 /* Wait for mem init command to complete. */ 3138 for (i = 0; i < retry_cnt; i++) { 3139 val = REG_RD(sc, BNX_CTX_COMMAND); 3140 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3141 break; 3142 DELAY(2); 3143 } 3144 3145 3146 /* ToDo: Consider returning an error here. */ 3147 3148 for (i = 0; i < sc->ctx_pages; i++) { 3149 int j; 3150 3151 3152 /* Set the physaddr of the context memory cache. */ 3153 val = (u_int32_t)(sc->ctx_segs[i].ds_addr); 3154 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3155 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3156 val = (u_int32_t) 3157 ((u_int64_t)sc->ctx_segs[i].ds_addr >> 32); 3158 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3159 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3160 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3161 3162 3163 /* Verify that the context memory write was successful. */ 3164 for (j = 0; j < retry_cnt; j++) { 3165 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3166 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3167 break; 3168 DELAY(5); 3169 } 3170 3171 /* ToDo: Consider returning an error here. */ 3172 } 3173 } else { 3174 u_int32_t vcid_addr, offset; 3175 3176 /* 3177 * For the 5706/5708, context memory is local to 3178 * the controller, so initialize the controller 3179 * context memory. 3180 */ 3181 3182 vcid_addr = GET_CID_ADDR(96); 3183 while (vcid_addr) { 3184 3185 vcid_addr -= BNX_PHY_CTX_SIZE; 3186 3187 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3188 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3189 3190 for(offset = 0; offset < BNX_PHY_CTX_SIZE; offset += 4) { 3191 CTX_WR(sc, 0x00, offset, 0); 3192 } 3193 3194 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3195 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3196 } 3197 } 3198 } 3199 3200 /****************************************************************************/ 3201 /* Fetch the permanent MAC address of the controller. */ 3202 /* */ 3203 /* Returns: */ 3204 /* Nothing. */ 3205 /****************************************************************************/ 3206 void 3207 bnx_get_mac_addr(struct bnx_softc *sc) 3208 { 3209 u_int32_t mac_lo = 0, mac_hi = 0; 3210 3211 /* 3212 * The NetXtreme II bootcode populates various NIC 3213 * power-on and runtime configuration items in a 3214 * shared memory area. The factory configured MAC 3215 * address is available from both NVRAM and the 3216 * shared memory area so we'll read the value from 3217 * shared memory for speed. 3218 */ 3219 3220 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3221 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3222 3223 if ((mac_lo == 0) && (mac_hi == 0)) { 3224 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3225 __FILE__, __LINE__); 3226 } else { 3227 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3228 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3229 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3230 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3231 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3232 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3233 } 3234 3235 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3236 "%s\n", ether_sprintf(sc->eaddr)); 3237 } 3238 3239 /****************************************************************************/ 3240 /* Program the MAC address. */ 3241 /* */ 3242 /* Returns: */ 3243 /* Nothing. */ 3244 /****************************************************************************/ 3245 void 3246 bnx_set_mac_addr(struct bnx_softc *sc) 3247 { 3248 u_int32_t val; 3249 const u_int8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3250 3251 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3252 "%s\n", ether_sprintf(sc->eaddr)); 3253 3254 val = (mac_addr[0] << 8) | mac_addr[1]; 3255 3256 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3257 3258 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3259 (mac_addr[4] << 8) | mac_addr[5]; 3260 3261 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3262 } 3263 3264 /****************************************************************************/ 3265 /* Stop the controller. */ 3266 /* */ 3267 /* Returns: */ 3268 /* Nothing. */ 3269 /****************************************************************************/ 3270 void 3271 bnx_stop(struct ifnet *ifp, int disable) 3272 { 3273 struct bnx_softc *sc = ifp->if_softc; 3274 3275 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3276 3277 if ((ifp->if_flags & IFF_RUNNING) == 0) 3278 return; 3279 3280 callout_stop(&sc->bnx_timeout); 3281 3282 mii_down(&sc->bnx_mii); 3283 3284 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3285 3286 /* Disable the transmit/receive blocks. */ 3287 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3288 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3289 DELAY(20); 3290 3291 bnx_disable_intr(sc); 3292 3293 /* Tell firmware that the driver is going away. */ 3294 if (disable) 3295 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3296 else 3297 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3298 3299 /* Free RX buffers. */ 3300 bnx_free_rx_chain(sc); 3301 3302 /* Free TX buffers. */ 3303 bnx_free_tx_chain(sc); 3304 3305 ifp->if_timer = 0; 3306 3307 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3308 3309 } 3310 3311 int 3312 bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) 3313 { 3314 struct pci_attach_args *pa = &(sc->bnx_pa); 3315 u_int32_t val; 3316 int i, rc = 0; 3317 3318 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3319 3320 /* Wait for pending PCI transactions to complete. */ 3321 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3322 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3323 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3324 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3325 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3326 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3327 DELAY(5); 3328 3329 /* Disable DMA */ 3330 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3331 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3332 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3333 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3334 } 3335 3336 /* Assume bootcode is running. */ 3337 sc->bnx_fw_timed_out = 0; 3338 3339 /* Give the firmware a chance to prepare for the reset. */ 3340 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3341 if (rc) 3342 goto bnx_reset_exit; 3343 3344 /* Set a firmware reminder that this is a soft reset. */ 3345 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3346 BNX_DRV_RESET_SIGNATURE_MAGIC); 3347 3348 /* Dummy read to force the chip to complete all current transactions. */ 3349 val = REG_RD(sc, BNX_MISC_ID); 3350 3351 /* Chip reset. */ 3352 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3353 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3354 REG_RD(sc, BNX_MISC_COMMAND); 3355 DELAY(5); 3356 3357 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3358 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3359 3360 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3361 val); 3362 } else { 3363 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3364 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3365 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3366 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3367 3368 /* Allow up to 30us for reset to complete. */ 3369 for (i = 0; i < 10; i++) { 3370 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3371 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3372 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3373 break; 3374 } 3375 DELAY(10); 3376 } 3377 3378 /* Check that reset completed successfully. */ 3379 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3380 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3381 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3382 __FILE__, __LINE__); 3383 rc = EBUSY; 3384 goto bnx_reset_exit; 3385 } 3386 } 3387 3388 /* Make sure byte swapping is properly configured. */ 3389 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3390 if (val != 0x01020304) { 3391 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3392 __FILE__, __LINE__); 3393 rc = ENODEV; 3394 goto bnx_reset_exit; 3395 } 3396 3397 /* Just completed a reset, assume that firmware is running again. */ 3398 sc->bnx_fw_timed_out = 0; 3399 3400 /* Wait for the firmware to finish its initialization. */ 3401 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3402 if (rc) 3403 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3404 "initialization!\n", __FILE__, __LINE__); 3405 3406 bnx_reset_exit: 3407 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3408 3409 return rc; 3410 } 3411 3412 int 3413 bnx_chipinit(struct bnx_softc *sc) 3414 { 3415 struct pci_attach_args *pa = &(sc->bnx_pa); 3416 u_int32_t val; 3417 int rc = 0; 3418 3419 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3420 3421 /* Make sure the interrupt is not active. */ 3422 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3423 3424 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3425 /* channels and PCI clock compensation delay. */ 3426 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3427 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3428 #if BYTE_ORDER == BIG_ENDIAN 3429 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3430 #endif 3431 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3432 DMA_READ_CHANS << 12 | 3433 DMA_WRITE_CHANS << 16; 3434 3435 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3436 3437 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3438 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3439 3440 /* 3441 * This setting resolves a problem observed on certain Intel PCI 3442 * chipsets that cannot handle multiple outstanding DMA operations. 3443 * See errata E9_5706A1_65. 3444 */ 3445 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3446 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3447 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3448 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3449 3450 REG_WR(sc, BNX_DMA_CONFIG, val); 3451 3452 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3453 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3454 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3455 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3456 val & ~0x20000); 3457 } 3458 3459 /* Enable the RX_V2P and Context state machines before access. */ 3460 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3461 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3462 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3463 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3464 3465 /* Initialize context mapping and zero out the quick contexts. */ 3466 bnx_init_context(sc); 3467 3468 /* Initialize the on-boards CPUs */ 3469 bnx_init_cpus(sc); 3470 3471 /* Prepare NVRAM for access. */ 3472 if (bnx_init_nvram(sc)) { 3473 rc = ENODEV; 3474 goto bnx_chipinit_exit; 3475 } 3476 3477 /* Set the kernel bypass block size */ 3478 val = REG_RD(sc, BNX_MQ_CONFIG); 3479 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3480 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3481 3482 /* Enable bins used on the 5709. */ 3483 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3484 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3485 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3486 val |= BNX_MQ_CONFIG_HALT_DIS; 3487 } 3488 3489 REG_WR(sc, BNX_MQ_CONFIG, val); 3490 3491 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3492 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3493 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3494 3495 val = (BCM_PAGE_BITS - 8) << 24; 3496 REG_WR(sc, BNX_RV2P_CONFIG, val); 3497 3498 /* Configure page size. */ 3499 val = REG_RD(sc, BNX_TBDR_CONFIG); 3500 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3501 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3502 REG_WR(sc, BNX_TBDR_CONFIG, val); 3503 3504 #if 0 3505 /* Set the perfect match control register to default. */ 3506 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3507 #endif 3508 3509 bnx_chipinit_exit: 3510 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3511 3512 return rc; 3513 } 3514 3515 /****************************************************************************/ 3516 /* Initialize the controller in preparation to send/receive traffic. */ 3517 /* */ 3518 /* Returns: */ 3519 /* 0 for success, positive value for failure. */ 3520 /****************************************************************************/ 3521 int 3522 bnx_blockinit(struct bnx_softc *sc) 3523 { 3524 u_int32_t reg, val; 3525 int rc = 0; 3526 3527 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3528 3529 /* Load the hardware default MAC address. */ 3530 bnx_set_mac_addr(sc); 3531 3532 /* Set the Ethernet backoff seed value */ 3533 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3534 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3535 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3536 3537 sc->last_status_idx = 0; 3538 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3539 3540 /* Set up link change interrupt generation. */ 3541 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3542 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3543 3544 /* Program the physical address of the status block. */ 3545 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); 3546 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3547 (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); 3548 3549 /* Program the physical address of the statistics block. */ 3550 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3551 (u_int32_t)(sc->stats_block_paddr)); 3552 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3553 (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); 3554 3555 /* Program various host coalescing parameters. */ 3556 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3557 << 16) | sc->bnx_tx_quick_cons_trip); 3558 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3559 << 16) | sc->bnx_rx_quick_cons_trip); 3560 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3561 sc->bnx_comp_prod_trip); 3562 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3563 sc->bnx_tx_ticks); 3564 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3565 sc->bnx_rx_ticks); 3566 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3567 sc->bnx_com_ticks); 3568 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3569 sc->bnx_cmd_ticks); 3570 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3571 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3572 REG_WR(sc, BNX_HC_CONFIG, 3573 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3574 BNX_HC_CONFIG_COLLECT_STATS)); 3575 3576 /* Clear the internal statistics counters. */ 3577 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3578 3579 /* Verify that bootcode is running. */ 3580 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3581 3582 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3583 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3584 __FILE__, __LINE__); reg = 0); 3585 3586 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3587 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3588 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3589 "Expected: 08%08X\n", __FILE__, __LINE__, 3590 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3591 BNX_DEV_INFO_SIGNATURE_MAGIC); 3592 rc = ENODEV; 3593 goto bnx_blockinit_exit; 3594 } 3595 3596 /* Check if any management firmware is running. */ 3597 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3598 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3599 BNX_PORT_FEATURE_IMD_ENABLED)) { 3600 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3601 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3602 } 3603 3604 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3605 BNX_DEV_INFO_BC_REV); 3606 3607 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3608 3609 /* Enable DMA */ 3610 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3611 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3612 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3613 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3614 } 3615 3616 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3617 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3618 3619 /* Enable link state change interrupt generation. */ 3620 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3621 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3622 BNX_MISC_ENABLE_DEFAULT_XI); 3623 } else 3624 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3625 3626 /* Enable all remaining blocks in the MAC. */ 3627 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3628 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3629 DELAY(20); 3630 3631 bnx_blockinit_exit: 3632 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3633 3634 return rc; 3635 } 3636 3637 static int 3638 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, u_int16_t *prod, 3639 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3640 { 3641 bus_dmamap_t map; 3642 struct rx_bd *rxbd; 3643 u_int32_t addr; 3644 int i; 3645 #ifdef BNX_DEBUG 3646 u_int16_t debug_chain_prod = *chain_prod; 3647 #endif 3648 u_int16_t first_chain_prod; 3649 3650 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3651 3652 /* Map the mbuf cluster into device memory. */ 3653 map = sc->rx_mbuf_map[*chain_prod]; 3654 first_chain_prod = *chain_prod; 3655 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3656 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3657 __FILE__, __LINE__); 3658 3659 m_freem(m_new); 3660 3661 DBRUNIF(1, sc->rx_mbuf_alloc--); 3662 3663 return ENOBUFS; 3664 } 3665 /* Make sure there is room in the receive chain. */ 3666 if (map->dm_nsegs > sc->free_rx_bd) { 3667 bus_dmamap_unload(sc->bnx_dmatag, map); 3668 m_freem(m_new); 3669 return EFBIG; 3670 } 3671 #ifdef BNX_DEBUG 3672 /* Track the distribution of buffer segments. */ 3673 sc->rx_mbuf_segs[map->dm_nsegs]++; 3674 #endif 3675 3676 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3677 BUS_DMASYNC_PREREAD); 3678 3679 /* Update some debug statistics counters */ 3680 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3681 sc->rx_low_watermark = sc->free_rx_bd); 3682 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3683 3684 /* 3685 * Setup the rx_bd for the first segment 3686 */ 3687 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3688 3689 addr = (u_int32_t)map->dm_segs[0].ds_addr; 3690 rxbd->rx_bd_haddr_lo = addr; 3691 addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); 3692 rxbd->rx_bd_haddr_hi = addr; 3693 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3694 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3695 *prod_bseq += map->dm_segs[0].ds_len; 3696 bus_dmamap_sync(sc->bnx_dmatag, 3697 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3698 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3700 3701 for (i = 1; i < map->dm_nsegs; i++) { 3702 *prod = NEXT_RX_BD(*prod); 3703 *chain_prod = RX_CHAIN_IDX(*prod); 3704 3705 rxbd = 3706 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3707 3708 addr = (u_int32_t)map->dm_segs[i].ds_addr; 3709 rxbd->rx_bd_haddr_lo = addr; 3710 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 3711 rxbd->rx_bd_haddr_hi = addr; 3712 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3713 rxbd->rx_bd_flags = 0; 3714 *prod_bseq += map->dm_segs[i].ds_len; 3715 bus_dmamap_sync(sc->bnx_dmatag, 3716 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3717 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3718 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3719 } 3720 3721 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3722 bus_dmamap_sync(sc->bnx_dmatag, 3723 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3724 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3725 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3726 3727 /* 3728 * Save the mbuf, ajust the map pointer (swap map for first and 3729 * last rx_bd entry to that rx_mbuf_ptr and rx_mbuf_map matches) 3730 * and update counter. 3731 */ 3732 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3733 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3734 sc->rx_mbuf_map[*chain_prod] = map; 3735 sc->free_rx_bd -= map->dm_nsegs; 3736 3737 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3738 map->dm_nsegs)); 3739 *prod = NEXT_RX_BD(*prod); 3740 *chain_prod = RX_CHAIN_IDX(*prod); 3741 3742 return 0; 3743 } 3744 3745 /****************************************************************************/ 3746 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3747 /* */ 3748 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3749 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3750 /* necessary. */ 3751 /* */ 3752 /* Returns: */ 3753 /* 0 for success, positive value for failure. */ 3754 /****************************************************************************/ 3755 int 3756 bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, 3757 u_int16_t *chain_prod, u_int32_t *prod_bseq) 3758 { 3759 struct mbuf *m_new = NULL; 3760 int rc = 0; 3761 u_int16_t min_free_bd; 3762 3763 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3764 __func__); 3765 3766 /* Make sure the inputs are valid. */ 3767 DBRUNIF((*chain_prod > MAX_RX_BD), 3768 aprint_error_dev(sc->bnx_dev, 3769 "RX producer out of range: 0x%04X > 0x%04X\n", 3770 *chain_prod, (u_int16_t)MAX_RX_BD)); 3771 3772 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3773 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3774 *prod_bseq); 3775 3776 /* try to get in as many mbufs as possible */ 3777 if (sc->mbuf_alloc_size == MCLBYTES) 3778 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3779 else 3780 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3781 while (sc->free_rx_bd >= min_free_bd) { 3782 /* Simulate an mbuf allocation failure. */ 3783 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3784 aprint_error_dev(sc->bnx_dev, 3785 "Simulating mbuf allocation failure.\n"); 3786 sc->mbuf_sim_alloc_failed++; 3787 rc = ENOBUFS; 3788 goto bnx_get_buf_exit); 3789 3790 /* This is a new mbuf allocation. */ 3791 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3792 if (m_new == NULL) { 3793 DBPRINT(sc, BNX_WARN, 3794 "%s(%d): RX mbuf header allocation failed!\n", 3795 __FILE__, __LINE__); 3796 3797 sc->mbuf_alloc_failed++; 3798 3799 rc = ENOBUFS; 3800 goto bnx_get_buf_exit; 3801 } 3802 3803 DBRUNIF(1, sc->rx_mbuf_alloc++); 3804 3805 /* Simulate an mbuf cluster allocation failure. */ 3806 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3807 m_freem(m_new); 3808 sc->rx_mbuf_alloc--; 3809 sc->mbuf_alloc_failed++; 3810 sc->mbuf_sim_alloc_failed++; 3811 rc = ENOBUFS; 3812 goto bnx_get_buf_exit); 3813 3814 if (sc->mbuf_alloc_size == MCLBYTES) 3815 MCLGET(m_new, M_DONTWAIT); 3816 else 3817 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3818 M_DONTWAIT); 3819 if (!(m_new->m_flags & M_EXT)) { 3820 DBPRINT(sc, BNX_WARN, 3821 "%s(%d): RX mbuf chain allocation failed!\n", 3822 __FILE__, __LINE__); 3823 3824 m_freem(m_new); 3825 3826 DBRUNIF(1, sc->rx_mbuf_alloc--); 3827 sc->mbuf_alloc_failed++; 3828 3829 rc = ENOBUFS; 3830 goto bnx_get_buf_exit; 3831 } 3832 3833 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3834 if (rc != 0) 3835 goto bnx_get_buf_exit; 3836 } 3837 3838 bnx_get_buf_exit: 3839 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3840 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3841 *chain_prod, *prod_bseq); 3842 3843 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3844 __func__); 3845 3846 return rc; 3847 } 3848 3849 void 3850 bnx_alloc_pkts(struct work * unused, void * arg) 3851 { 3852 struct bnx_softc *sc = arg; 3853 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3854 struct bnx_pkt *pkt; 3855 int i, s; 3856 3857 for (i = 0; i < 4; i++) { /* magic! */ 3858 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 3859 if (pkt == NULL) 3860 break; 3861 3862 if (bus_dmamap_create(sc->bnx_dmatag, 3863 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3864 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3865 &pkt->pkt_dmamap) != 0) 3866 goto put; 3867 3868 if (!ISSET(ifp->if_flags, IFF_UP)) 3869 goto stopping; 3870 3871 mutex_enter(&sc->tx_pkt_mtx); 3872 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3873 sc->tx_pkt_count++; 3874 mutex_exit(&sc->tx_pkt_mtx); 3875 } 3876 3877 mutex_enter(&sc->tx_pkt_mtx); 3878 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 3879 mutex_exit(&sc->tx_pkt_mtx); 3880 3881 /* fire-up TX now that allocations have been done */ 3882 s = splnet(); 3883 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3884 bnx_start(ifp); 3885 splx(s); 3886 3887 return; 3888 3889 stopping: 3890 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3891 put: 3892 pool_put(bnx_tx_pool, pkt); 3893 return; 3894 } 3895 3896 /****************************************************************************/ 3897 /* Initialize the TX context memory. */ 3898 /* */ 3899 /* Returns: */ 3900 /* Nothing */ 3901 /****************************************************************************/ 3902 void 3903 bnx_init_tx_context(struct bnx_softc *sc) 3904 { 3905 u_int32_t val; 3906 3907 /* Initialize the context ID for an L2 TX chain. */ 3908 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3909 /* Set the CID type to support an L2 connection. */ 3910 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3911 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 3912 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3913 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 3914 3915 /* Point the hardware to the first page in the chain. */ 3916 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3917 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3918 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 3919 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3920 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3921 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 3922 } else { 3923 /* Set the CID type to support an L2 connection. */ 3924 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3925 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3926 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3927 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3928 3929 /* Point the hardware to the first page in the chain. */ 3930 val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); 3931 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3932 val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); 3933 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3934 } 3935 } 3936 3937 3938 /****************************************************************************/ 3939 /* Allocate memory and initialize the TX data structures. */ 3940 /* */ 3941 /* Returns: */ 3942 /* 0 for success, positive value for failure. */ 3943 /****************************************************************************/ 3944 int 3945 bnx_init_tx_chain(struct bnx_softc *sc) 3946 { 3947 struct tx_bd *txbd; 3948 u_int32_t addr; 3949 int i, rc = 0; 3950 3951 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3952 3953 /* Force an allocation of some dmamaps for tx up front */ 3954 bnx_alloc_pkts(NULL, sc); 3955 3956 /* Set the initial TX producer/consumer indices. */ 3957 sc->tx_prod = 0; 3958 sc->tx_cons = 0; 3959 sc->tx_prod_bseq = 0; 3960 sc->used_tx_bd = 0; 3961 sc->max_tx_bd = USABLE_TX_BD; 3962 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3963 DBRUNIF(1, sc->tx_full_count = 0); 3964 3965 /* 3966 * The NetXtreme II supports a linked-list structure called 3967 * a Buffer Descriptor Chain (or BD chain). A BD chain 3968 * consists of a series of 1 or more chain pages, each of which 3969 * consists of a fixed number of BD entries. 3970 * The last BD entry on each page is a pointer to the next page 3971 * in the chain, and the last pointer in the BD chain 3972 * points back to the beginning of the chain. 3973 */ 3974 3975 /* Set the TX next pointer chain entries. */ 3976 for (i = 0; i < TX_PAGES; i++) { 3977 int j; 3978 3979 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3980 3981 /* Check if we've reached the last page. */ 3982 if (i == (TX_PAGES - 1)) 3983 j = 0; 3984 else 3985 j = i + 1; 3986 3987 addr = (u_int32_t)sc->tx_bd_chain_paddr[j]; 3988 txbd->tx_bd_haddr_lo = addr; 3989 addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); 3990 txbd->tx_bd_haddr_hi = addr; 3991 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3992 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3993 } 3994 3995 /* 3996 * Initialize the context ID for an L2 TX chain. 3997 */ 3998 bnx_init_tx_context(sc); 3999 4000 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4001 4002 return rc; 4003 } 4004 4005 /****************************************************************************/ 4006 /* Free memory and clear the TX data structures. */ 4007 /* */ 4008 /* Returns: */ 4009 /* Nothing. */ 4010 /****************************************************************************/ 4011 void 4012 bnx_free_tx_chain(struct bnx_softc *sc) 4013 { 4014 struct bnx_pkt *pkt; 4015 int i; 4016 4017 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4018 4019 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4020 mutex_enter(&sc->tx_pkt_mtx); 4021 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4022 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4023 mutex_exit(&sc->tx_pkt_mtx); 4024 4025 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4026 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4027 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4028 4029 m_freem(pkt->pkt_mbuf); 4030 DBRUNIF(1, sc->tx_mbuf_alloc--); 4031 4032 mutex_enter(&sc->tx_pkt_mtx); 4033 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4034 } 4035 4036 /* Destroy all the dmamaps we allocated for TX */ 4037 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4038 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4039 sc->tx_pkt_count--; 4040 mutex_exit(&sc->tx_pkt_mtx); 4041 4042 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4043 pool_put(bnx_tx_pool, pkt); 4044 4045 mutex_enter(&sc->tx_pkt_mtx); 4046 } 4047 mutex_exit(&sc->tx_pkt_mtx); 4048 4049 4050 4051 /* Clear each TX chain page. */ 4052 for (i = 0; i < TX_PAGES; i++) { 4053 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4054 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4055 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4056 } 4057 4058 sc->used_tx_bd = 0; 4059 4060 /* Check if we lost any mbufs in the process. */ 4061 DBRUNIF((sc->tx_mbuf_alloc), 4062 aprint_error_dev(sc->bnx_dev, 4063 "Memory leak! Lost %d mbufs from tx chain!\n", 4064 sc->tx_mbuf_alloc)); 4065 4066 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4067 } 4068 4069 /****************************************************************************/ 4070 /* Initialize the RX context memory. */ 4071 /* */ 4072 /* Returns: */ 4073 /* Nothing */ 4074 /****************************************************************************/ 4075 void 4076 bnx_init_rx_context(struct bnx_softc *sc) 4077 { 4078 u_int32_t val; 4079 4080 /* Initialize the context ID for an L2 RX chain. */ 4081 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4082 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4083 4084 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4085 u_int32_t lo_water, hi_water; 4086 4087 lo_water = BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT; 4088 hi_water = USABLE_RX_BD / 4; 4089 4090 lo_water /= BNX_L2CTX_RX_LO_WATER_MARK_SCALE; 4091 hi_water /= BNX_L2CTX_RX_HI_WATER_MARK_SCALE; 4092 4093 if (hi_water > 0xf) 4094 hi_water = 0xf; 4095 else if (hi_water == 0) 4096 lo_water = 0; 4097 val |= lo_water | 4098 (hi_water << BNX_L2CTX_RX_HI_WATER_MARK_SHIFT); 4099 } 4100 4101 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4102 4103 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4104 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4105 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4106 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4107 } 4108 4109 /* Point the hardware to the first page in the chain. */ 4110 val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); 4111 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4112 val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); 4113 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4114 } 4115 4116 /****************************************************************************/ 4117 /* Allocate memory and initialize the RX data structures. */ 4118 /* */ 4119 /* Returns: */ 4120 /* 0 for success, positive value for failure. */ 4121 /****************************************************************************/ 4122 int 4123 bnx_init_rx_chain(struct bnx_softc *sc) 4124 { 4125 struct rx_bd *rxbd; 4126 int i, rc = 0; 4127 u_int16_t prod, chain_prod; 4128 u_int32_t prod_bseq, addr; 4129 4130 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4131 4132 /* Initialize the RX producer and consumer indices. */ 4133 sc->rx_prod = 0; 4134 sc->rx_cons = 0; 4135 sc->rx_prod_bseq = 0; 4136 sc->free_rx_bd = USABLE_RX_BD; 4137 sc->max_rx_bd = USABLE_RX_BD; 4138 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4139 DBRUNIF(1, sc->rx_empty_count = 0); 4140 4141 /* Initialize the RX next pointer chain entries. */ 4142 for (i = 0; i < RX_PAGES; i++) { 4143 int j; 4144 4145 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4146 4147 /* Check if we've reached the last page. */ 4148 if (i == (RX_PAGES - 1)) 4149 j = 0; 4150 else 4151 j = i + 1; 4152 4153 /* Setup the chain page pointers. */ 4154 addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); 4155 rxbd->rx_bd_haddr_hi = addr; 4156 addr = (u_int32_t)sc->rx_bd_chain_paddr[j]; 4157 rxbd->rx_bd_haddr_lo = addr; 4158 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4159 0, BNX_RX_CHAIN_PAGE_SZ, 4160 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4161 } 4162 4163 /* Allocate mbuf clusters for the rx_bd chain. */ 4164 prod = prod_bseq = 0; 4165 chain_prod = RX_CHAIN_IDX(prod); 4166 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4167 BNX_PRINTF(sc, 4168 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4169 } 4170 4171 /* Save the RX chain producer index. */ 4172 sc->rx_prod = prod; 4173 sc->rx_prod_bseq = prod_bseq; 4174 4175 for (i = 0; i < RX_PAGES; i++) 4176 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4177 sc->rx_bd_chain_map[i]->dm_mapsize, 4178 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4179 4180 /* Tell the chip about the waiting rx_bd's. */ 4181 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4182 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4183 4184 bnx_init_rx_context(sc); 4185 4186 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4187 4188 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4189 4190 return rc; 4191 } 4192 4193 /****************************************************************************/ 4194 /* Free memory and clear the RX data structures. */ 4195 /* */ 4196 /* Returns: */ 4197 /* Nothing. */ 4198 /****************************************************************************/ 4199 void 4200 bnx_free_rx_chain(struct bnx_softc *sc) 4201 { 4202 int i; 4203 4204 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4205 4206 /* Free any mbufs still in the RX mbuf chain. */ 4207 for (i = 0; i < TOTAL_RX_BD; i++) { 4208 if (sc->rx_mbuf_ptr[i] != NULL) { 4209 if (sc->rx_mbuf_map[i] != NULL) { 4210 bus_dmamap_sync(sc->bnx_dmatag, 4211 sc->rx_mbuf_map[i], 0, 4212 sc->rx_mbuf_map[i]->dm_mapsize, 4213 BUS_DMASYNC_POSTREAD); 4214 bus_dmamap_unload(sc->bnx_dmatag, 4215 sc->rx_mbuf_map[i]); 4216 } 4217 m_freem(sc->rx_mbuf_ptr[i]); 4218 sc->rx_mbuf_ptr[i] = NULL; 4219 DBRUNIF(1, sc->rx_mbuf_alloc--); 4220 } 4221 } 4222 4223 /* Clear each RX chain page. */ 4224 for (i = 0; i < RX_PAGES; i++) 4225 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4226 4227 sc->free_rx_bd = sc->max_rx_bd; 4228 4229 /* Check if we lost any mbufs in the process. */ 4230 DBRUNIF((sc->rx_mbuf_alloc), 4231 aprint_error_dev(sc->bnx_dev, 4232 "Memory leak! Lost %d mbufs from rx chain!\n", 4233 sc->rx_mbuf_alloc)); 4234 4235 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4236 } 4237 4238 /****************************************************************************/ 4239 /* Handles PHY generated interrupt events. */ 4240 /* */ 4241 /* Returns: */ 4242 /* Nothing. */ 4243 /****************************************************************************/ 4244 void 4245 bnx_phy_intr(struct bnx_softc *sc) 4246 { 4247 u_int32_t new_link_state, old_link_state; 4248 4249 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4250 BUS_DMASYNC_POSTREAD); 4251 new_link_state = sc->status_block->status_attn_bits & 4252 STATUS_ATTN_BITS_LINK_STATE; 4253 old_link_state = sc->status_block->status_attn_bits_ack & 4254 STATUS_ATTN_BITS_LINK_STATE; 4255 4256 /* Handle any changes if the link state has changed. */ 4257 if (new_link_state != old_link_state) { 4258 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4259 4260 callout_stop(&sc->bnx_timeout); 4261 bnx_tick(sc); 4262 4263 /* Update the status_attn_bits_ack field in the status block. */ 4264 if (new_link_state) { 4265 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4266 STATUS_ATTN_BITS_LINK_STATE); 4267 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4268 } else { 4269 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4270 STATUS_ATTN_BITS_LINK_STATE); 4271 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4272 } 4273 } 4274 4275 /* Acknowledge the link change interrupt. */ 4276 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4277 } 4278 4279 /****************************************************************************/ 4280 /* Handles received frame interrupt events. */ 4281 /* */ 4282 /* Returns: */ 4283 /* Nothing. */ 4284 /****************************************************************************/ 4285 void 4286 bnx_rx_intr(struct bnx_softc *sc) 4287 { 4288 struct status_block *sblk = sc->status_block; 4289 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4290 u_int16_t hw_cons, sw_cons, sw_chain_cons; 4291 u_int16_t sw_prod, sw_chain_prod; 4292 u_int32_t sw_prod_bseq; 4293 struct l2_fhdr *l2fhdr; 4294 int i; 4295 4296 DBRUNIF(1, sc->rx_interrupts++); 4297 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4298 BUS_DMASYNC_POSTREAD); 4299 4300 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4301 for (i = 0; i < RX_PAGES; i++) 4302 bus_dmamap_sync(sc->bnx_dmatag, 4303 sc->rx_bd_chain_map[i], 0, 4304 sc->rx_bd_chain_map[i]->dm_mapsize, 4305 BUS_DMASYNC_POSTWRITE); 4306 4307 /* Get the hardware's view of the RX consumer index. */ 4308 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4309 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4310 hw_cons++; 4311 4312 /* Get working copies of the driver's view of the RX indices. */ 4313 sw_cons = sc->rx_cons; 4314 sw_prod = sc->rx_prod; 4315 sw_prod_bseq = sc->rx_prod_bseq; 4316 4317 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4318 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4319 __func__, sw_prod, sw_cons, sw_prod_bseq); 4320 4321 /* Prevent speculative reads from getting ahead of the status block. */ 4322 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4323 BUS_SPACE_BARRIER_READ); 4324 4325 /* Update some debug statistics counters */ 4326 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4327 sc->rx_low_watermark = sc->free_rx_bd); 4328 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4329 4330 /* 4331 * Scan through the receive chain as long 4332 * as there is work to do. 4333 */ 4334 while (sw_cons != hw_cons) { 4335 struct mbuf *m; 4336 struct rx_bd *rxbd __diagused; 4337 unsigned int len; 4338 u_int32_t status; 4339 4340 /* Convert the producer/consumer indices to an actual 4341 * rx_bd index. 4342 */ 4343 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4344 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4345 4346 /* Get the used rx_bd. */ 4347 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4348 sc->free_rx_bd++; 4349 4350 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4351 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4352 4353 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4354 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4355 #ifdef DIAGNOSTIC 4356 /* Validate that this is the last rx_bd. */ 4357 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4358 printf("%s: Unexpected mbuf found in " 4359 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4360 sw_chain_cons); 4361 } 4362 #endif 4363 4364 /* DRC - ToDo: If the received packet is small, say less 4365 * than 128 bytes, allocate a new mbuf here, 4366 * copy the data to that mbuf, and recycle 4367 * the mapped jumbo frame. 4368 */ 4369 4370 /* Unmap the mbuf from DMA space. */ 4371 #ifdef DIAGNOSTIC 4372 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4373 printf("invalid map sw_cons 0x%x " 4374 "sw_prod 0x%x " 4375 "sw_chain_cons 0x%x " 4376 "sw_chain_prod 0x%x " 4377 "hw_cons 0x%x " 4378 "TOTAL_RX_BD_PER_PAGE 0x%x " 4379 "TOTAL_RX_BD 0x%x\n", 4380 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4381 hw_cons, 4382 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4383 } 4384 #endif 4385 bus_dmamap_sync(sc->bnx_dmatag, 4386 sc->rx_mbuf_map[sw_chain_cons], 0, 4387 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4388 BUS_DMASYNC_POSTREAD); 4389 bus_dmamap_unload(sc->bnx_dmatag, 4390 sc->rx_mbuf_map[sw_chain_cons]); 4391 4392 /* Remove the mbuf from the driver's chain. */ 4393 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4394 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4395 4396 /* 4397 * Frames received on the NetXteme II are prepended 4398 * with the l2_fhdr structure which provides status 4399 * information about the received frame (including 4400 * VLAN tags and checksum info) and are also 4401 * automatically adjusted to align the IP header 4402 * (i.e. two null bytes are inserted before the 4403 * Ethernet header). 4404 */ 4405 l2fhdr = mtod(m, struct l2_fhdr *); 4406 4407 len = l2fhdr->l2_fhdr_pkt_len; 4408 status = l2fhdr->l2_fhdr_status; 4409 4410 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4411 aprint_error("Simulating l2_fhdr status error.\n"); 4412 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4413 4414 /* Watch for unusual sized frames. */ 4415 DBRUNIF(((len < BNX_MIN_MTU) || 4416 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4417 aprint_error_dev(sc->bnx_dev, 4418 "Unusual frame size found. " 4419 "Min(%d), Actual(%d), Max(%d)\n", 4420 (int)BNX_MIN_MTU, len, 4421 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4422 4423 bnx_dump_mbuf(sc, m); 4424 bnx_breakpoint(sc)); 4425 4426 len -= ETHER_CRC_LEN; 4427 4428 /* Check the received frame for errors. */ 4429 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4430 L2_FHDR_ERRORS_PHY_DECODE | 4431 L2_FHDR_ERRORS_ALIGNMENT | 4432 L2_FHDR_ERRORS_TOO_SHORT | 4433 L2_FHDR_ERRORS_GIANT_FRAME)) || 4434 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4435 len > 4436 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4437 ifp->if_ierrors++; 4438 DBRUNIF(1, sc->l2fhdr_status_errors++); 4439 4440 /* Reuse the mbuf for a new frame. */ 4441 if (bnx_add_buf(sc, m, &sw_prod, 4442 &sw_chain_prod, &sw_prod_bseq)) { 4443 DBRUNIF(1, bnx_breakpoint(sc)); 4444 panic("%s: Can't reuse RX mbuf!\n", 4445 device_xname(sc->bnx_dev)); 4446 } 4447 continue; 4448 } 4449 4450 /* 4451 * Get a new mbuf for the rx_bd. If no new 4452 * mbufs are available then reuse the current mbuf, 4453 * log an ierror on the interface, and generate 4454 * an error in the system log. 4455 */ 4456 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4457 &sw_prod_bseq)) { 4458 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4459 "Failed to allocate " 4460 "new mbuf, incoming frame dropped!\n")); 4461 4462 ifp->if_ierrors++; 4463 4464 /* Try and reuse the exisitng mbuf. */ 4465 if (bnx_add_buf(sc, m, &sw_prod, 4466 &sw_chain_prod, &sw_prod_bseq)) { 4467 DBRUNIF(1, bnx_breakpoint(sc)); 4468 panic("%s: Double mbuf allocation " 4469 "failure!", 4470 device_xname(sc->bnx_dev)); 4471 } 4472 continue; 4473 } 4474 4475 /* Skip over the l2_fhdr when passing the data up 4476 * the stack. 4477 */ 4478 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4479 4480 /* Adjust the pckt length to match the received data. */ 4481 m->m_pkthdr.len = m->m_len = len; 4482 4483 /* Send the packet to the appropriate interface. */ 4484 m->m_pkthdr.rcvif = ifp; 4485 4486 DBRUN(BNX_VERBOSE_RECV, 4487 struct ether_header *eh; 4488 eh = mtod(m, struct ether_header *); 4489 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4490 __func__, ether_sprintf(eh->ether_dhost), 4491 ether_sprintf(eh->ether_shost), 4492 htons(eh->ether_type))); 4493 4494 /* Validate the checksum. */ 4495 4496 /* Check for an IP datagram. */ 4497 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4498 /* Check if the IP checksum is valid. */ 4499 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 4500 == 0) 4501 m->m_pkthdr.csum_flags |= 4502 M_CSUM_IPv4; 4503 #ifdef BNX_DEBUG 4504 else 4505 DBPRINT(sc, BNX_WARN_SEND, 4506 "%s(): Invalid IP checksum " 4507 "= 0x%04X!\n", 4508 __func__, 4509 l2fhdr->l2_fhdr_ip_xsum 4510 ); 4511 #endif 4512 } 4513 4514 /* Check for a valid TCP/UDP frame. */ 4515 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4516 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4517 /* Check for a good TCP/UDP checksum. */ 4518 if ((status & 4519 (L2_FHDR_ERRORS_TCP_XSUM | 4520 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4521 m->m_pkthdr.csum_flags |= 4522 M_CSUM_TCPv4 | 4523 M_CSUM_UDPv4; 4524 } else { 4525 DBPRINT(sc, BNX_WARN_SEND, 4526 "%s(): Invalid TCP/UDP " 4527 "checksum = 0x%04X!\n", 4528 __func__, 4529 l2fhdr->l2_fhdr_tcp_udp_xsum); 4530 } 4531 } 4532 4533 /* 4534 * If we received a packet with a vlan tag, 4535 * attach that information to the packet. 4536 */ 4537 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4538 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4539 VLAN_INPUT_TAG(ifp, m, 4540 l2fhdr->l2_fhdr_vlan_tag, 4541 continue); 4542 } 4543 4544 /* 4545 * Handle BPF listeners. Let the BPF 4546 * user see the packet. 4547 */ 4548 bpf_mtap(ifp, m); 4549 4550 /* Pass the mbuf off to the upper layers. */ 4551 ifp->if_ipackets++; 4552 DBPRINT(sc, BNX_VERBOSE_RECV, 4553 "%s(): Passing received frame up.\n", __func__); 4554 (*ifp->if_input)(ifp, m); 4555 DBRUNIF(1, sc->rx_mbuf_alloc--); 4556 4557 } 4558 4559 sw_cons = NEXT_RX_BD(sw_cons); 4560 4561 /* Refresh hw_cons to see if there's new work */ 4562 if (sw_cons == hw_cons) { 4563 hw_cons = sc->hw_rx_cons = 4564 sblk->status_rx_quick_consumer_index0; 4565 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4566 USABLE_RX_BD_PER_PAGE) 4567 hw_cons++; 4568 } 4569 4570 /* Prevent speculative reads from getting ahead of 4571 * the status block. 4572 */ 4573 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4574 BUS_SPACE_BARRIER_READ); 4575 } 4576 4577 for (i = 0; i < RX_PAGES; i++) 4578 bus_dmamap_sync(sc->bnx_dmatag, 4579 sc->rx_bd_chain_map[i], 0, 4580 sc->rx_bd_chain_map[i]->dm_mapsize, 4581 BUS_DMASYNC_PREWRITE); 4582 4583 sc->rx_cons = sw_cons; 4584 sc->rx_prod = sw_prod; 4585 sc->rx_prod_bseq = sw_prod_bseq; 4586 4587 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4588 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4589 4590 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4591 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4592 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4593 } 4594 4595 /****************************************************************************/ 4596 /* Handles transmit completion interrupt events. */ 4597 /* */ 4598 /* Returns: */ 4599 /* Nothing. */ 4600 /****************************************************************************/ 4601 void 4602 bnx_tx_intr(struct bnx_softc *sc) 4603 { 4604 struct status_block *sblk = sc->status_block; 4605 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4606 struct bnx_pkt *pkt; 4607 bus_dmamap_t map; 4608 u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4609 4610 DBRUNIF(1, sc->tx_interrupts++); 4611 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4612 BUS_DMASYNC_POSTREAD); 4613 4614 /* Get the hardware's view of the TX consumer index. */ 4615 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4616 4617 /* Skip to the next entry if this is a chain page pointer. */ 4618 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4619 hw_tx_cons++; 4620 4621 sw_tx_cons = sc->tx_cons; 4622 4623 /* Prevent speculative reads from getting ahead of the status block. */ 4624 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4625 BUS_SPACE_BARRIER_READ); 4626 4627 /* Cycle through any completed TX chain page entries. */ 4628 while (sw_tx_cons != hw_tx_cons) { 4629 #ifdef BNX_DEBUG 4630 struct tx_bd *txbd = NULL; 4631 #endif 4632 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4633 4634 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4635 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4636 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4637 4638 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4639 aprint_error_dev(sc->bnx_dev, 4640 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4641 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4642 4643 DBRUNIF(1, txbd = &sc->tx_bd_chain 4644 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4645 4646 DBRUNIF((txbd == NULL), 4647 aprint_error_dev(sc->bnx_dev, 4648 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4649 bnx_breakpoint(sc)); 4650 4651 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4652 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4653 4654 4655 mutex_enter(&sc->tx_pkt_mtx); 4656 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4657 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4658 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4659 mutex_exit(&sc->tx_pkt_mtx); 4660 /* 4661 * Free the associated mbuf. Remember 4662 * that only the last tx_bd of a packet 4663 * has an mbuf pointer and DMA map. 4664 */ 4665 map = pkt->pkt_dmamap; 4666 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4667 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4668 bus_dmamap_unload(sc->bnx_dmatag, map); 4669 4670 m_freem(pkt->pkt_mbuf); 4671 DBRUNIF(1, sc->tx_mbuf_alloc--); 4672 4673 ifp->if_opackets++; 4674 4675 mutex_enter(&sc->tx_pkt_mtx); 4676 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4677 } 4678 mutex_exit(&sc->tx_pkt_mtx); 4679 4680 sc->used_tx_bd--; 4681 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4682 __FILE__, __LINE__, sc->used_tx_bd); 4683 4684 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4685 4686 /* Refresh hw_cons to see if there's new work. */ 4687 hw_tx_cons = sc->hw_tx_cons = 4688 sblk->status_tx_quick_consumer_index0; 4689 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4690 USABLE_TX_BD_PER_PAGE) 4691 hw_tx_cons++; 4692 4693 /* Prevent speculative reads from getting ahead of 4694 * the status block. 4695 */ 4696 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4697 BUS_SPACE_BARRIER_READ); 4698 } 4699 4700 /* Clear the TX timeout timer. */ 4701 ifp->if_timer = 0; 4702 4703 /* Clear the tx hardware queue full flag. */ 4704 if (sc->used_tx_bd < sc->max_tx_bd) { 4705 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4706 aprint_debug_dev(sc->bnx_dev, 4707 "Open TX chain! %d/%d (used/total)\n", 4708 sc->used_tx_bd, sc->max_tx_bd)); 4709 ifp->if_flags &= ~IFF_OACTIVE; 4710 } 4711 4712 sc->tx_cons = sw_tx_cons; 4713 } 4714 4715 /****************************************************************************/ 4716 /* Disables interrupt generation. */ 4717 /* */ 4718 /* Returns: */ 4719 /* Nothing. */ 4720 /****************************************************************************/ 4721 void 4722 bnx_disable_intr(struct bnx_softc *sc) 4723 { 4724 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4725 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4726 } 4727 4728 /****************************************************************************/ 4729 /* Enables interrupt generation. */ 4730 /* */ 4731 /* Returns: */ 4732 /* Nothing. */ 4733 /****************************************************************************/ 4734 void 4735 bnx_enable_intr(struct bnx_softc *sc) 4736 { 4737 u_int32_t val; 4738 4739 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4740 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4741 4742 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4743 sc->last_status_idx); 4744 4745 val = REG_RD(sc, BNX_HC_COMMAND); 4746 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4747 } 4748 4749 /****************************************************************************/ 4750 /* Handles controller initialization. */ 4751 /* */ 4752 /****************************************************************************/ 4753 int 4754 bnx_init(struct ifnet *ifp) 4755 { 4756 struct bnx_softc *sc = ifp->if_softc; 4757 u_int32_t ether_mtu; 4758 int s, error = 0; 4759 4760 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4761 4762 s = splnet(); 4763 4764 bnx_stop(ifp, 0); 4765 4766 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4767 aprint_error_dev(sc->bnx_dev, 4768 "Controller reset failed!\n"); 4769 goto bnx_init_exit; 4770 } 4771 4772 if ((error = bnx_chipinit(sc)) != 0) { 4773 aprint_error_dev(sc->bnx_dev, 4774 "Controller initialization failed!\n"); 4775 goto bnx_init_exit; 4776 } 4777 4778 if ((error = bnx_blockinit(sc)) != 0) { 4779 aprint_error_dev(sc->bnx_dev, 4780 "Block initialization failed!\n"); 4781 goto bnx_init_exit; 4782 } 4783 4784 /* Calculate and program the Ethernet MRU size. */ 4785 if (ifp->if_mtu <= ETHERMTU) { 4786 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4787 sc->mbuf_alloc_size = MCLBYTES; 4788 } else { 4789 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4790 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4791 } 4792 4793 4794 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4795 __func__, ether_mtu); 4796 4797 /* 4798 * Program the MRU and enable Jumbo frame 4799 * support. 4800 */ 4801 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4802 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4803 4804 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4805 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4806 4807 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4808 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4809 sc->mbuf_alloc_size, sc->max_frame_size); 4810 4811 /* Program appropriate promiscuous/multicast filtering. */ 4812 bnx_iff(sc); 4813 4814 /* Init RX buffer descriptor chain. */ 4815 bnx_init_rx_chain(sc); 4816 4817 /* Init TX buffer descriptor chain. */ 4818 bnx_init_tx_chain(sc); 4819 4820 /* Enable host interrupts. */ 4821 bnx_enable_intr(sc); 4822 4823 if ((error = ether_mediachange(ifp)) != 0) 4824 goto bnx_init_exit; 4825 4826 SET(ifp->if_flags, IFF_RUNNING); 4827 CLR(ifp->if_flags, IFF_OACTIVE); 4828 4829 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4830 4831 bnx_init_exit: 4832 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4833 4834 splx(s); 4835 4836 return error; 4837 } 4838 4839 /****************************************************************************/ 4840 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4841 /* memory visible to the controller. */ 4842 /* */ 4843 /* Returns: */ 4844 /* 0 for success, positive value for failure. */ 4845 /****************************************************************************/ 4846 int 4847 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4848 { 4849 struct bnx_pkt *pkt; 4850 bus_dmamap_t map; 4851 struct tx_bd *txbd = NULL; 4852 u_int16_t vlan_tag = 0, flags = 0; 4853 u_int16_t chain_prod, prod; 4854 #ifdef BNX_DEBUG 4855 u_int16_t debug_prod; 4856 #endif 4857 u_int32_t addr, prod_bseq; 4858 int i, error; 4859 struct m_tag *mtag; 4860 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 4861 4862 mutex_enter(&sc->tx_pkt_mtx); 4863 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 4864 if (pkt == NULL) { 4865 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 4866 mutex_exit(&sc->tx_pkt_mtx); 4867 return ENETDOWN; 4868 } 4869 4870 if (sc->tx_pkt_count <= TOTAL_TX_BD && 4871 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 4872 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 4873 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4874 } 4875 4876 mutex_exit(&sc->tx_pkt_mtx); 4877 return ENOMEM; 4878 } 4879 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4880 mutex_exit(&sc->tx_pkt_mtx); 4881 4882 /* Transfer any checksum offload flags to the bd. */ 4883 if (m->m_pkthdr.csum_flags) { 4884 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 4885 flags |= TX_BD_FLAGS_IP_CKSUM; 4886 if (m->m_pkthdr.csum_flags & 4887 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4888 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4889 } 4890 4891 /* Transfer any VLAN tags to the bd. */ 4892 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m); 4893 if (mtag != NULL) { 4894 flags |= TX_BD_FLAGS_VLAN_TAG; 4895 vlan_tag = VLAN_TAG_VALUE(mtag); 4896 } 4897 4898 /* Map the mbuf into DMAable memory. */ 4899 prod = sc->tx_prod; 4900 chain_prod = TX_CHAIN_IDX(prod); 4901 map = pkt->pkt_dmamap; 4902 4903 /* Map the mbuf into our DMA address space. */ 4904 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 4905 if (error != 0) { 4906 aprint_error_dev(sc->bnx_dev, 4907 "Error mapping mbuf into TX chain!\n"); 4908 sc->tx_dma_map_failures++; 4909 goto maperr; 4910 } 4911 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4912 BUS_DMASYNC_PREWRITE); 4913 /* Make sure there's room in the chain */ 4914 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 4915 goto nospace; 4916 4917 /* prod points to an empty tx_bd at this point. */ 4918 prod_bseq = sc->tx_prod_bseq; 4919 #ifdef BNX_DEBUG 4920 debug_prod = chain_prod; 4921 #endif 4922 DBPRINT(sc, BNX_INFO_SEND, 4923 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4924 "prod_bseq = 0x%08X\n", 4925 __func__, prod, chain_prod, prod_bseq); 4926 4927 /* 4928 * Cycle through each mbuf segment that makes up 4929 * the outgoing frame, gathering the mapping info 4930 * for that segment and creating a tx_bd for the 4931 * mbuf. 4932 */ 4933 for (i = 0; i < map->dm_nsegs ; i++) { 4934 chain_prod = TX_CHAIN_IDX(prod); 4935 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4936 4937 addr = (u_int32_t)map->dm_segs[i].ds_addr; 4938 txbd->tx_bd_haddr_lo = addr; 4939 addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); 4940 txbd->tx_bd_haddr_hi = addr; 4941 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 4942 txbd->tx_bd_vlan_tag = vlan_tag; 4943 txbd->tx_bd_flags = flags; 4944 prod_bseq += map->dm_segs[i].ds_len; 4945 if (i == 0) 4946 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 4947 prod = NEXT_TX_BD(prod); 4948 } 4949 /* Set the END flag on the last TX buffer descriptor. */ 4950 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 4951 4952 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 4953 4954 DBPRINT(sc, BNX_INFO_SEND, 4955 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4956 "prod_bseq = 0x%08X\n", 4957 __func__, prod, chain_prod, prod_bseq); 4958 4959 pkt->pkt_mbuf = m; 4960 pkt->pkt_end_desc = chain_prod; 4961 4962 mutex_enter(&sc->tx_pkt_mtx); 4963 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 4964 mutex_exit(&sc->tx_pkt_mtx); 4965 4966 sc->used_tx_bd += map->dm_nsegs; 4967 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4968 __FILE__, __LINE__, sc->used_tx_bd); 4969 4970 /* Update some debug statistics counters */ 4971 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4972 sc->tx_hi_watermark = sc->used_tx_bd); 4973 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 4974 DBRUNIF(1, sc->tx_mbuf_alloc++); 4975 4976 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4977 map->dm_nsegs)); 4978 4979 /* prod points to the next free tx_bd at this point. */ 4980 sc->tx_prod = prod; 4981 sc->tx_prod_bseq = prod_bseq; 4982 4983 return 0; 4984 4985 4986 nospace: 4987 bus_dmamap_unload(sc->bnx_dmatag, map); 4988 maperr: 4989 mutex_enter(&sc->tx_pkt_mtx); 4990 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4991 mutex_exit(&sc->tx_pkt_mtx); 4992 4993 return ENOMEM; 4994 } 4995 4996 /****************************************************************************/ 4997 /* Main transmit routine. */ 4998 /* */ 4999 /* Returns: */ 5000 /* Nothing. */ 5001 /****************************************************************************/ 5002 void 5003 bnx_start(struct ifnet *ifp) 5004 { 5005 struct bnx_softc *sc = ifp->if_softc; 5006 struct mbuf *m_head = NULL; 5007 int count = 0; 5008 #ifdef BNX_DEBUG 5009 u_int16_t tx_chain_prod; 5010 #endif 5011 5012 /* If there's no link or the transmit queue is empty then just exit. */ 5013 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5014 DBPRINT(sc, BNX_INFO_SEND, 5015 "%s(): output active or device not running.\n", __func__); 5016 goto bnx_start_exit; 5017 } 5018 5019 /* prod points to the next free tx_bd. */ 5020 #ifdef BNX_DEBUG 5021 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5022 #endif 5023 5024 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5025 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5026 "used_tx %d max_tx %d\n", 5027 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5028 sc->used_tx_bd, sc->max_tx_bd); 5029 5030 /* 5031 * Keep adding entries while there is space in the ring. 5032 */ 5033 while (sc->used_tx_bd < sc->max_tx_bd) { 5034 /* Check for any frames to send. */ 5035 IFQ_POLL(&ifp->if_snd, m_head); 5036 if (m_head == NULL) 5037 break; 5038 5039 /* 5040 * Pack the data into the transmit ring. If we 5041 * don't have room, set the OACTIVE flag to wait 5042 * for the NIC to drain the chain. 5043 */ 5044 if (bnx_tx_encap(sc, m_head)) { 5045 ifp->if_flags |= IFF_OACTIVE; 5046 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5047 "business! Total tx_bd used = %d\n", 5048 sc->used_tx_bd); 5049 break; 5050 } 5051 5052 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5053 count++; 5054 5055 /* Send a copy of the frame to any BPF listeners. */ 5056 bpf_mtap(ifp, m_head); 5057 } 5058 5059 if (count == 0) { 5060 /* no packets were dequeued */ 5061 DBPRINT(sc, BNX_VERBOSE_SEND, 5062 "%s(): No packets were dequeued\n", __func__); 5063 goto bnx_start_exit; 5064 } 5065 5066 /* Update the driver's counters. */ 5067 #ifdef BNX_DEBUG 5068 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5069 #endif 5070 5071 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 5072 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, sc->tx_prod, 5073 tx_chain_prod, sc->tx_prod_bseq); 5074 5075 /* Start the transmit. */ 5076 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5077 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5078 5079 /* Set the tx timeout. */ 5080 ifp->if_timer = BNX_TX_TIMEOUT; 5081 5082 bnx_start_exit: 5083 return; 5084 } 5085 5086 /****************************************************************************/ 5087 /* Handles any IOCTL calls from the operating system. */ 5088 /* */ 5089 /* Returns: */ 5090 /* 0 for success, positive value for failure. */ 5091 /****************************************************************************/ 5092 int 5093 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5094 { 5095 struct bnx_softc *sc = ifp->if_softc; 5096 struct ifreq *ifr = (struct ifreq *) data; 5097 struct mii_data *mii = &sc->bnx_mii; 5098 int s, error = 0; 5099 5100 s = splnet(); 5101 5102 switch (command) { 5103 case SIOCSIFFLAGS: 5104 if ((error = ifioctl_common(ifp, command, data)) != 0) 5105 break; 5106 /* XXX set an ifflags callback and let ether_ioctl 5107 * handle all of this. 5108 */ 5109 if (ISSET(ifp->if_flags, IFF_UP)) { 5110 if (ifp->if_flags & IFF_RUNNING) 5111 error = ENETRESET; 5112 else 5113 bnx_init(ifp); 5114 } else if (ifp->if_flags & IFF_RUNNING) 5115 bnx_stop(ifp, 1); 5116 break; 5117 5118 case SIOCSIFMEDIA: 5119 case SIOCGIFMEDIA: 5120 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5121 sc->bnx_phy_flags); 5122 5123 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5124 break; 5125 5126 default: 5127 error = ether_ioctl(ifp, command, data); 5128 } 5129 5130 if (error == ENETRESET) { 5131 if (ifp->if_flags & IFF_RUNNING) 5132 bnx_iff(sc); 5133 error = 0; 5134 } 5135 5136 splx(s); 5137 return error; 5138 } 5139 5140 /****************************************************************************/ 5141 /* Transmit timeout handler. */ 5142 /* */ 5143 /* Returns: */ 5144 /* Nothing. */ 5145 /****************************************************************************/ 5146 void 5147 bnx_watchdog(struct ifnet *ifp) 5148 { 5149 struct bnx_softc *sc = ifp->if_softc; 5150 5151 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5152 bnx_dump_status_block(sc)); 5153 /* 5154 * If we are in this routine because of pause frames, then 5155 * don't reset the hardware. 5156 */ 5157 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5158 return; 5159 5160 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5161 5162 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5163 5164 bnx_init(ifp); 5165 5166 ifp->if_oerrors++; 5167 } 5168 5169 /* 5170 * Interrupt handler. 5171 */ 5172 /****************************************************************************/ 5173 /* Main interrupt entry point. Verifies that the controller generated the */ 5174 /* interrupt and then calls a separate routine for handle the various */ 5175 /* interrupt causes (PHY, TX, RX). */ 5176 /* */ 5177 /* Returns: */ 5178 /* 0 for success, positive value for failure. */ 5179 /****************************************************************************/ 5180 int 5181 bnx_intr(void *xsc) 5182 { 5183 struct bnx_softc *sc; 5184 struct ifnet *ifp; 5185 u_int32_t status_attn_bits; 5186 const struct status_block *sblk; 5187 5188 sc = xsc; 5189 5190 ifp = &sc->bnx_ec.ec_if; 5191 5192 if (!device_is_active(sc->bnx_dev) || 5193 (ifp->if_flags & IFF_RUNNING) == 0) 5194 return 0; 5195 5196 DBRUNIF(1, sc->interrupts_generated++); 5197 5198 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5199 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 5200 5201 /* 5202 * If the hardware status block index 5203 * matches the last value read by the 5204 * driver and we haven't asserted our 5205 * interrupt then there's nothing to do. 5206 */ 5207 if ((sc->status_block->status_idx == sc->last_status_idx) && 5208 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 5209 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 5210 return 0; 5211 5212 /* Ack the interrupt and stop others from occuring. */ 5213 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5214 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5215 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5216 5217 /* Keep processing data as long as there is work to do. */ 5218 for (;;) { 5219 sblk = sc->status_block; 5220 status_attn_bits = sblk->status_attn_bits; 5221 5222 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5223 aprint_debug("Simulating unexpected status attention bit set."); 5224 status_attn_bits = status_attn_bits | 5225 STATUS_ATTN_BITS_PARITY_ERROR); 5226 5227 /* Was it a link change interrupt? */ 5228 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5229 (sblk->status_attn_bits_ack & 5230 STATUS_ATTN_BITS_LINK_STATE)) 5231 bnx_phy_intr(sc); 5232 5233 /* If any other attention is asserted then the chip is toast. */ 5234 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5235 (sblk->status_attn_bits_ack & 5236 ~STATUS_ATTN_BITS_LINK_STATE))) { 5237 DBRUN(1, sc->unexpected_attentions++); 5238 5239 BNX_PRINTF(sc, 5240 "Fatal attention detected: 0x%08X\n", 5241 sblk->status_attn_bits); 5242 5243 DBRUN(BNX_FATAL, 5244 if (bnx_debug_unexpected_attention == 0) 5245 bnx_breakpoint(sc)); 5246 5247 bnx_init(ifp); 5248 return 1; 5249 } 5250 5251 /* Check for any completed RX frames. */ 5252 if (sblk->status_rx_quick_consumer_index0 != 5253 sc->hw_rx_cons) 5254 bnx_rx_intr(sc); 5255 5256 /* Check for any completed TX frames. */ 5257 if (sblk->status_tx_quick_consumer_index0 != 5258 sc->hw_tx_cons) 5259 bnx_tx_intr(sc); 5260 5261 /* Save the status block index value for use during the 5262 * next interrupt. 5263 */ 5264 sc->last_status_idx = sblk->status_idx; 5265 5266 /* Prevent speculative reads from getting ahead of the 5267 * status block. 5268 */ 5269 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 5270 BUS_SPACE_BARRIER_READ); 5271 5272 /* If there's no work left then exit the isr. */ 5273 if ((sblk->status_rx_quick_consumer_index0 == 5274 sc->hw_rx_cons) && 5275 (sblk->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5276 break; 5277 } 5278 5279 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5280 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 5281 5282 /* Re-enable interrupts. */ 5283 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5284 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5285 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5286 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5287 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5288 5289 /* Handle any frames that arrived while handling the interrupt. */ 5290 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 5291 bnx_start(ifp); 5292 5293 return 1; 5294 } 5295 5296 /****************************************************************************/ 5297 /* Programs the various packet receive modes (broadcast and multicast). */ 5298 /* */ 5299 /* Returns: */ 5300 /* Nothing. */ 5301 /****************************************************************************/ 5302 void 5303 bnx_iff(struct bnx_softc *sc) 5304 { 5305 struct ethercom *ec = &sc->bnx_ec; 5306 struct ifnet *ifp = &ec->ec_if; 5307 struct ether_multi *enm; 5308 struct ether_multistep step; 5309 u_int32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5310 u_int32_t rx_mode, sort_mode; 5311 int h, i; 5312 5313 /* Initialize receive mode default settings. */ 5314 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5315 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5316 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5317 ifp->if_flags &= ~IFF_ALLMULTI; 5318 5319 /* 5320 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5321 * be enbled. 5322 */ 5323 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5324 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5325 5326 /* 5327 * Check for promiscuous, all multicast, or selected 5328 * multicast address filtering. 5329 */ 5330 if (ifp->if_flags & IFF_PROMISC) { 5331 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5332 5333 ifp->if_flags |= IFF_ALLMULTI; 5334 /* Enable promiscuous mode. */ 5335 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5336 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5337 } else if (ifp->if_flags & IFF_ALLMULTI) { 5338 allmulti: 5339 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5340 5341 ifp->if_flags |= IFF_ALLMULTI; 5342 /* Enable all multicast addresses. */ 5343 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5344 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5345 0xffffffff); 5346 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5347 } else { 5348 /* Accept one or more multicast(s). */ 5349 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5350 5351 ETHER_FIRST_MULTI(step, ec, enm); 5352 while (enm != NULL) { 5353 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5354 ETHER_ADDR_LEN)) { 5355 goto allmulti; 5356 } 5357 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5358 0xFF; 5359 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5360 ETHER_NEXT_MULTI(step, enm); 5361 } 5362 5363 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5364 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5365 hashes[i]); 5366 5367 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5368 } 5369 5370 /* Only make changes if the recive mode has actually changed. */ 5371 if (rx_mode != sc->rx_mode) { 5372 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5373 rx_mode); 5374 5375 sc->rx_mode = rx_mode; 5376 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5377 } 5378 5379 /* Disable and clear the exisitng sort before enabling a new sort. */ 5380 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5381 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5382 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5383 } 5384 5385 /****************************************************************************/ 5386 /* Called periodically to updates statistics from the controllers */ 5387 /* statistics block. */ 5388 /* */ 5389 /* Returns: */ 5390 /* Nothing. */ 5391 /****************************************************************************/ 5392 void 5393 bnx_stats_update(struct bnx_softc *sc) 5394 { 5395 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5396 struct statistics_block *stats; 5397 5398 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5399 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5400 BUS_DMASYNC_POSTREAD); 5401 5402 stats = (struct statistics_block *)sc->stats_block; 5403 5404 /* 5405 * Update the interface statistics from the 5406 * hardware statistics. 5407 */ 5408 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5409 5410 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5411 (u_long)stats->stat_EtherStatsOverrsizePkts + 5412 (u_long)stats->stat_IfInMBUFDiscards + 5413 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5414 (u_long)stats->stat_Dot3StatsFCSErrors; 5415 5416 ifp->if_oerrors = (u_long) 5417 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5418 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5419 (u_long)stats->stat_Dot3StatsLateCollisions; 5420 5421 /* 5422 * Certain controllers don't report 5423 * carrier sense errors correctly. 5424 * See errata E11_5708CA0_1165. 5425 */ 5426 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5427 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5428 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5429 5430 /* 5431 * Update the sysctl statistics from the 5432 * hardware statistics. 5433 */ 5434 sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + 5435 (u_int64_t) stats->stat_IfHCInOctets_lo; 5436 5437 sc->stat_IfHCInBadOctets = 5438 ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5439 (u_int64_t) stats->stat_IfHCInBadOctets_lo; 5440 5441 sc->stat_IfHCOutOctets = 5442 ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + 5443 (u_int64_t) stats->stat_IfHCOutOctets_lo; 5444 5445 sc->stat_IfHCOutBadOctets = 5446 ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5447 (u_int64_t) stats->stat_IfHCOutBadOctets_lo; 5448 5449 sc->stat_IfHCInUcastPkts = 5450 ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5451 (u_int64_t) stats->stat_IfHCInUcastPkts_lo; 5452 5453 sc->stat_IfHCInMulticastPkts = 5454 ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5455 (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; 5456 5457 sc->stat_IfHCInBroadcastPkts = 5458 ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5459 (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; 5460 5461 sc->stat_IfHCOutUcastPkts = 5462 ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5463 (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; 5464 5465 sc->stat_IfHCOutMulticastPkts = 5466 ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5467 (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; 5468 5469 sc->stat_IfHCOutBroadcastPkts = 5470 ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5471 (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5472 5473 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5474 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5475 5476 sc->stat_Dot3StatsCarrierSenseErrors = 5477 stats->stat_Dot3StatsCarrierSenseErrors; 5478 5479 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5480 5481 sc->stat_Dot3StatsAlignmentErrors = 5482 stats->stat_Dot3StatsAlignmentErrors; 5483 5484 sc->stat_Dot3StatsSingleCollisionFrames = 5485 stats->stat_Dot3StatsSingleCollisionFrames; 5486 5487 sc->stat_Dot3StatsMultipleCollisionFrames = 5488 stats->stat_Dot3StatsMultipleCollisionFrames; 5489 5490 sc->stat_Dot3StatsDeferredTransmissions = 5491 stats->stat_Dot3StatsDeferredTransmissions; 5492 5493 sc->stat_Dot3StatsExcessiveCollisions = 5494 stats->stat_Dot3StatsExcessiveCollisions; 5495 5496 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5497 5498 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5499 5500 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5501 5502 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5503 5504 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5505 5506 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5507 5508 sc->stat_EtherStatsPktsRx64Octets = 5509 stats->stat_EtherStatsPktsRx64Octets; 5510 5511 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5512 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5513 5514 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5515 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5516 5517 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5518 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5519 5520 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5521 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5522 5523 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5524 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5525 5526 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5527 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5528 5529 sc->stat_EtherStatsPktsTx64Octets = 5530 stats->stat_EtherStatsPktsTx64Octets; 5531 5532 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5533 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5534 5535 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5536 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5537 5538 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5539 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5540 5541 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5542 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5543 5544 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5545 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5546 5547 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5548 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5549 5550 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5551 5552 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5553 5554 sc->stat_OutXonSent = stats->stat_OutXonSent; 5555 5556 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5557 5558 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5559 5560 sc->stat_MacControlFramesReceived = 5561 stats->stat_MacControlFramesReceived; 5562 5563 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5564 5565 sc->stat_IfInFramesL2FilterDiscards = 5566 stats->stat_IfInFramesL2FilterDiscards; 5567 5568 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5569 5570 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5571 5572 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5573 5574 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5575 5576 sc->stat_CatchupInRuleCheckerDiscards = 5577 stats->stat_CatchupInRuleCheckerDiscards; 5578 5579 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5580 5581 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5582 5583 sc->stat_CatchupInRuleCheckerP4Hit = 5584 stats->stat_CatchupInRuleCheckerP4Hit; 5585 5586 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5587 } 5588 5589 void 5590 bnx_tick(void *xsc) 5591 { 5592 struct bnx_softc *sc = xsc; 5593 struct mii_data *mii; 5594 u_int32_t msg; 5595 u_int16_t prod, chain_prod; 5596 u_int32_t prod_bseq; 5597 int s = splnet(); 5598 5599 /* Tell the firmware that the driver is still running. */ 5600 #ifdef BNX_DEBUG 5601 msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5602 #else 5603 msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5604 #endif 5605 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5606 5607 /* Update the statistics from the hardware statistics block. */ 5608 bnx_stats_update(sc); 5609 5610 /* Schedule the next tick. */ 5611 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5612 5613 mii = &sc->bnx_mii; 5614 mii_tick(mii); 5615 5616 /* try to get more RX buffers, just in case */ 5617 prod = sc->rx_prod; 5618 prod_bseq = sc->rx_prod_bseq; 5619 chain_prod = RX_CHAIN_IDX(prod); 5620 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5621 sc->rx_prod = prod; 5622 sc->rx_prod_bseq = prod_bseq; 5623 splx(s); 5624 return; 5625 } 5626 5627 /****************************************************************************/ 5628 /* BNX Debug Routines */ 5629 /****************************************************************************/ 5630 #ifdef BNX_DEBUG 5631 5632 /****************************************************************************/ 5633 /* Prints out information about an mbuf. */ 5634 /* */ 5635 /* Returns: */ 5636 /* Nothing. */ 5637 /****************************************************************************/ 5638 void 5639 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5640 { 5641 struct mbuf *mp = m; 5642 5643 if (m == NULL) { 5644 /* Index out of range. */ 5645 aprint_error("mbuf ptr is null!\n"); 5646 return; 5647 } 5648 5649 while (mp) { 5650 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5651 mp, mp->m_len); 5652 5653 if (mp->m_flags & M_EXT) 5654 aprint_debug("M_EXT "); 5655 if (mp->m_flags & M_PKTHDR) 5656 aprint_debug("M_PKTHDR "); 5657 aprint_debug("\n"); 5658 5659 if (mp->m_flags & M_EXT) 5660 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 5661 mp, mp->m_ext.ext_size); 5662 5663 mp = mp->m_next; 5664 } 5665 } 5666 5667 /****************************************************************************/ 5668 /* Prints out the mbufs in the TX mbuf chain. */ 5669 /* */ 5670 /* Returns: */ 5671 /* Nothing. */ 5672 /****************************************************************************/ 5673 void 5674 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5675 { 5676 #if 0 5677 struct mbuf *m; 5678 int i; 5679 5680 aprint_debug_dev(sc->bnx_dev, 5681 "----------------------------" 5682 " tx mbuf data " 5683 "----------------------------\n"); 5684 5685 for (i = 0; i < count; i++) { 5686 m = sc->tx_mbuf_ptr[chain_prod]; 5687 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5688 bnx_dump_mbuf(sc, m); 5689 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5690 } 5691 5692 aprint_debug_dev(sc->bnx_dev, 5693 "--------------------------------------------" 5694 "----------------------------\n"); 5695 #endif 5696 } 5697 5698 /* 5699 * This routine prints the RX mbuf chain. 5700 */ 5701 void 5702 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5703 { 5704 struct mbuf *m; 5705 int i; 5706 5707 aprint_debug_dev(sc->bnx_dev, 5708 "----------------------------" 5709 " rx mbuf data " 5710 "----------------------------\n"); 5711 5712 for (i = 0; i < count; i++) { 5713 m = sc->rx_mbuf_ptr[chain_prod]; 5714 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5715 bnx_dump_mbuf(sc, m); 5716 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5717 } 5718 5719 5720 aprint_debug_dev(sc->bnx_dev, 5721 "--------------------------------------------" 5722 "----------------------------\n"); 5723 } 5724 5725 void 5726 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5727 { 5728 if (idx > MAX_TX_BD) 5729 /* Index out of range. */ 5730 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5731 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5732 /* TX Chain page pointer. */ 5733 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5734 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5735 txbd->tx_bd_haddr_lo); 5736 else 5737 /* Normal tx_bd entry. */ 5738 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5739 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5740 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5741 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5742 txbd->tx_bd_flags); 5743 } 5744 5745 void 5746 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5747 { 5748 if (idx > MAX_RX_BD) 5749 /* Index out of range. */ 5750 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5751 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5752 /* TX Chain page pointer. */ 5753 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5754 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5755 rxbd->rx_bd_haddr_lo); 5756 else 5757 /* Normal tx_bd entry. */ 5758 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5759 "0x%08X, flags = 0x%08X\n", idx, 5760 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5761 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5762 } 5763 5764 void 5765 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5766 { 5767 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5768 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5769 "tcp_udp_xsum = 0x%04X\n", idx, 5770 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5771 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5772 l2fhdr->l2_fhdr_tcp_udp_xsum); 5773 } 5774 5775 /* 5776 * This routine prints the TX chain. 5777 */ 5778 void 5779 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5780 { 5781 struct tx_bd *txbd; 5782 int i; 5783 5784 /* First some info about the tx_bd chain structure. */ 5785 aprint_debug_dev(sc->bnx_dev, 5786 "----------------------------" 5787 " tx_bd chain " 5788 "----------------------------\n"); 5789 5790 BNX_PRINTF(sc, 5791 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5792 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); 5793 5794 BNX_PRINTF(sc, 5795 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5796 (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); 5797 5798 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5799 5800 aprint_error_dev(sc->bnx_dev, "" 5801 "-----------------------------" 5802 " tx_bd data " 5803 "-----------------------------\n"); 5804 5805 /* Now print out the tx_bd's themselves. */ 5806 for (i = 0; i < count; i++) { 5807 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5808 bnx_dump_txbd(sc, tx_prod, txbd); 5809 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5810 } 5811 5812 aprint_debug_dev(sc->bnx_dev, 5813 "-----------------------------" 5814 "--------------" 5815 "-----------------------------\n"); 5816 } 5817 5818 /* 5819 * This routine prints the RX chain. 5820 */ 5821 void 5822 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5823 { 5824 struct rx_bd *rxbd; 5825 int i; 5826 5827 /* First some info about the tx_bd chain structure. */ 5828 aprint_debug_dev(sc->bnx_dev, 5829 "----------------------------" 5830 " rx_bd chain " 5831 "----------------------------\n"); 5832 5833 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5834 5835 BNX_PRINTF(sc, 5836 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5837 (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); 5838 5839 BNX_PRINTF(sc, 5840 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5841 (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); 5842 5843 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5844 5845 aprint_error_dev(sc->bnx_dev, 5846 "----------------------------" 5847 " rx_bd data " 5848 "----------------------------\n"); 5849 5850 /* Now print out the rx_bd's themselves. */ 5851 for (i = 0; i < count; i++) { 5852 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5853 bnx_dump_rxbd(sc, rx_prod, rxbd); 5854 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5855 } 5856 5857 aprint_debug_dev(sc->bnx_dev, 5858 "----------------------------" 5859 "--------------" 5860 "----------------------------\n"); 5861 } 5862 5863 /* 5864 * This routine prints the status block. 5865 */ 5866 void 5867 bnx_dump_status_block(struct bnx_softc *sc) 5868 { 5869 struct status_block *sblk; 5870 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5871 BUS_DMASYNC_POSTREAD); 5872 5873 sblk = sc->status_block; 5874 5875 aprint_debug_dev(sc->bnx_dev, "----------------------------- Status Block " 5876 "-----------------------------\n"); 5877 5878 BNX_PRINTF(sc, 5879 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5880 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5881 sblk->status_idx); 5882 5883 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5884 sblk->status_rx_quick_consumer_index0, 5885 sblk->status_tx_quick_consumer_index0); 5886 5887 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5888 5889 /* Theses indices are not used for normal L2 drivers. */ 5890 if (sblk->status_rx_quick_consumer_index1 || 5891 sblk->status_tx_quick_consumer_index1) 5892 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5893 sblk->status_rx_quick_consumer_index1, 5894 sblk->status_tx_quick_consumer_index1); 5895 5896 if (sblk->status_rx_quick_consumer_index2 || 5897 sblk->status_tx_quick_consumer_index2) 5898 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5899 sblk->status_rx_quick_consumer_index2, 5900 sblk->status_tx_quick_consumer_index2); 5901 5902 if (sblk->status_rx_quick_consumer_index3 || 5903 sblk->status_tx_quick_consumer_index3) 5904 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5905 sblk->status_rx_quick_consumer_index3, 5906 sblk->status_tx_quick_consumer_index3); 5907 5908 if (sblk->status_rx_quick_consumer_index4 || 5909 sblk->status_rx_quick_consumer_index5) 5910 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5911 sblk->status_rx_quick_consumer_index4, 5912 sblk->status_rx_quick_consumer_index5); 5913 5914 if (sblk->status_rx_quick_consumer_index6 || 5915 sblk->status_rx_quick_consumer_index7) 5916 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5917 sblk->status_rx_quick_consumer_index6, 5918 sblk->status_rx_quick_consumer_index7); 5919 5920 if (sblk->status_rx_quick_consumer_index8 || 5921 sblk->status_rx_quick_consumer_index9) 5922 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5923 sblk->status_rx_quick_consumer_index8, 5924 sblk->status_rx_quick_consumer_index9); 5925 5926 if (sblk->status_rx_quick_consumer_index10 || 5927 sblk->status_rx_quick_consumer_index11) 5928 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5929 sblk->status_rx_quick_consumer_index10, 5930 sblk->status_rx_quick_consumer_index11); 5931 5932 if (sblk->status_rx_quick_consumer_index12 || 5933 sblk->status_rx_quick_consumer_index13) 5934 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5935 sblk->status_rx_quick_consumer_index12, 5936 sblk->status_rx_quick_consumer_index13); 5937 5938 if (sblk->status_rx_quick_consumer_index14 || 5939 sblk->status_rx_quick_consumer_index15) 5940 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5941 sblk->status_rx_quick_consumer_index14, 5942 sblk->status_rx_quick_consumer_index15); 5943 5944 if (sblk->status_completion_producer_index || 5945 sblk->status_cmd_consumer_index) 5946 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5947 sblk->status_completion_producer_index, 5948 sblk->status_cmd_consumer_index); 5949 5950 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 5951 "-----------------------------\n"); 5952 } 5953 5954 /* 5955 * This routine prints the statistics block. 5956 */ 5957 void 5958 bnx_dump_stats_block(struct bnx_softc *sc) 5959 { 5960 struct statistics_block *sblk; 5961 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5962 BUS_DMASYNC_POSTREAD); 5963 5964 sblk = sc->stats_block; 5965 5966 aprint_debug_dev(sc->bnx_dev, "" 5967 "-----------------------------" 5968 " Stats Block " 5969 "-----------------------------\n"); 5970 5971 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5972 "IfHcInBadOctets = 0x%08X:%08X\n", 5973 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5974 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5975 5976 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5977 "IfHcOutBadOctets = 0x%08X:%08X\n", 5978 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5979 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5980 5981 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5982 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5983 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5984 sblk->stat_IfHCInMulticastPkts_hi, 5985 sblk->stat_IfHCInMulticastPkts_lo); 5986 5987 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5988 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5989 sblk->stat_IfHCInBroadcastPkts_hi, 5990 sblk->stat_IfHCInBroadcastPkts_lo, 5991 sblk->stat_IfHCOutUcastPkts_hi, 5992 sblk->stat_IfHCOutUcastPkts_lo); 5993 5994 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5995 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5996 sblk->stat_IfHCOutMulticastPkts_hi, 5997 sblk->stat_IfHCOutMulticastPkts_lo, 5998 sblk->stat_IfHCOutBroadcastPkts_hi, 5999 sblk->stat_IfHCOutBroadcastPkts_lo); 6000 6001 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6002 BNX_PRINTF(sc, "0x%08X : " 6003 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6004 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6005 6006 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6007 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6008 sblk->stat_Dot3StatsCarrierSenseErrors); 6009 6010 if (sblk->stat_Dot3StatsFCSErrors) 6011 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6012 sblk->stat_Dot3StatsFCSErrors); 6013 6014 if (sblk->stat_Dot3StatsAlignmentErrors) 6015 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6016 sblk->stat_Dot3StatsAlignmentErrors); 6017 6018 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6019 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6020 sblk->stat_Dot3StatsSingleCollisionFrames); 6021 6022 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6023 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6024 sblk->stat_Dot3StatsMultipleCollisionFrames); 6025 6026 if (sblk->stat_Dot3StatsDeferredTransmissions) 6027 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6028 sblk->stat_Dot3StatsDeferredTransmissions); 6029 6030 if (sblk->stat_Dot3StatsExcessiveCollisions) 6031 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6032 sblk->stat_Dot3StatsExcessiveCollisions); 6033 6034 if (sblk->stat_Dot3StatsLateCollisions) 6035 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6036 sblk->stat_Dot3StatsLateCollisions); 6037 6038 if (sblk->stat_EtherStatsCollisions) 6039 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6040 sblk->stat_EtherStatsCollisions); 6041 6042 if (sblk->stat_EtherStatsFragments) 6043 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6044 sblk->stat_EtherStatsFragments); 6045 6046 if (sblk->stat_EtherStatsJabbers) 6047 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6048 sblk->stat_EtherStatsJabbers); 6049 6050 if (sblk->stat_EtherStatsUndersizePkts) 6051 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6052 sblk->stat_EtherStatsUndersizePkts); 6053 6054 if (sblk->stat_EtherStatsOverrsizePkts) 6055 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6056 sblk->stat_EtherStatsOverrsizePkts); 6057 6058 if (sblk->stat_EtherStatsPktsRx64Octets) 6059 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6060 sblk->stat_EtherStatsPktsRx64Octets); 6061 6062 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6063 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6064 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6065 6066 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6067 BNX_PRINTF(sc, "0x%08X : " 6068 "EtherStatsPktsRx128Octetsto255Octets\n", 6069 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6070 6071 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6072 BNX_PRINTF(sc, "0x%08X : " 6073 "EtherStatsPktsRx256Octetsto511Octets\n", 6074 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6075 6076 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6077 BNX_PRINTF(sc, "0x%08X : " 6078 "EtherStatsPktsRx512Octetsto1023Octets\n", 6079 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6080 6081 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6082 BNX_PRINTF(sc, "0x%08X : " 6083 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6084 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6085 6086 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6087 BNX_PRINTF(sc, "0x%08X : " 6088 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6089 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6090 6091 if (sblk->stat_EtherStatsPktsTx64Octets) 6092 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6093 sblk->stat_EtherStatsPktsTx64Octets); 6094 6095 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6096 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6097 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6098 6099 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6100 BNX_PRINTF(sc, "0x%08X : " 6101 "EtherStatsPktsTx128Octetsto255Octets\n", 6102 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6103 6104 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6105 BNX_PRINTF(sc, "0x%08X : " 6106 "EtherStatsPktsTx256Octetsto511Octets\n", 6107 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6108 6109 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6110 BNX_PRINTF(sc, "0x%08X : " 6111 "EtherStatsPktsTx512Octetsto1023Octets\n", 6112 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6113 6114 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6115 BNX_PRINTF(sc, "0x%08X : " 6116 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6117 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6118 6119 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6120 BNX_PRINTF(sc, "0x%08X : " 6121 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6122 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6123 6124 if (sblk->stat_XonPauseFramesReceived) 6125 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6126 sblk->stat_XonPauseFramesReceived); 6127 6128 if (sblk->stat_XoffPauseFramesReceived) 6129 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6130 sblk->stat_XoffPauseFramesReceived); 6131 6132 if (sblk->stat_OutXonSent) 6133 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6134 sblk->stat_OutXonSent); 6135 6136 if (sblk->stat_OutXoffSent) 6137 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6138 sblk->stat_OutXoffSent); 6139 6140 if (sblk->stat_FlowControlDone) 6141 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6142 sblk->stat_FlowControlDone); 6143 6144 if (sblk->stat_MacControlFramesReceived) 6145 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6146 sblk->stat_MacControlFramesReceived); 6147 6148 if (sblk->stat_XoffStateEntered) 6149 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6150 sblk->stat_XoffStateEntered); 6151 6152 if (sblk->stat_IfInFramesL2FilterDiscards) 6153 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6154 sblk->stat_IfInFramesL2FilterDiscards); 6155 6156 if (sblk->stat_IfInRuleCheckerDiscards) 6157 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6158 sblk->stat_IfInRuleCheckerDiscards); 6159 6160 if (sblk->stat_IfInFTQDiscards) 6161 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6162 sblk->stat_IfInFTQDiscards); 6163 6164 if (sblk->stat_IfInMBUFDiscards) 6165 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6166 sblk->stat_IfInMBUFDiscards); 6167 6168 if (sblk->stat_IfInRuleCheckerP4Hit) 6169 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6170 sblk->stat_IfInRuleCheckerP4Hit); 6171 6172 if (sblk->stat_CatchupInRuleCheckerDiscards) 6173 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6174 sblk->stat_CatchupInRuleCheckerDiscards); 6175 6176 if (sblk->stat_CatchupInFTQDiscards) 6177 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6178 sblk->stat_CatchupInFTQDiscards); 6179 6180 if (sblk->stat_CatchupInMBUFDiscards) 6181 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6182 sblk->stat_CatchupInMBUFDiscards); 6183 6184 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6185 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6186 sblk->stat_CatchupInRuleCheckerP4Hit); 6187 6188 aprint_debug_dev(sc->bnx_dev, 6189 "-----------------------------" 6190 "--------------" 6191 "-----------------------------\n"); 6192 } 6193 6194 void 6195 bnx_dump_driver_state(struct bnx_softc *sc) 6196 { 6197 aprint_debug_dev(sc->bnx_dev, 6198 "-----------------------------" 6199 " Driver State " 6200 "-----------------------------\n"); 6201 6202 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6203 "address\n", sc); 6204 6205 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6206 sc->status_block); 6207 6208 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6209 "address\n", sc->stats_block); 6210 6211 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6212 "adddress\n", sc->tx_bd_chain); 6213 6214 #if 0 6215 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6216 sc->rx_bd_chain); 6217 6218 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6219 sc->tx_mbuf_ptr); 6220 #endif 6221 6222 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6223 sc->rx_mbuf_ptr); 6224 6225 BNX_PRINTF(sc, 6226 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6227 sc->interrupts_generated); 6228 6229 BNX_PRINTF(sc, 6230 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6231 sc->rx_interrupts); 6232 6233 BNX_PRINTF(sc, 6234 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6235 sc->tx_interrupts); 6236 6237 BNX_PRINTF(sc, 6238 " 0x%08X - (sc->last_status_idx) status block index\n", 6239 sc->last_status_idx); 6240 6241 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6242 sc->tx_prod); 6243 6244 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6245 sc->tx_cons); 6246 6247 BNX_PRINTF(sc, 6248 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6249 sc->tx_prod_bseq); 6250 BNX_PRINTF(sc, 6251 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6252 sc->tx_mbuf_alloc); 6253 6254 BNX_PRINTF(sc, 6255 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6256 sc->used_tx_bd); 6257 6258 BNX_PRINTF(sc, 6259 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6260 sc->tx_hi_watermark, sc->max_tx_bd); 6261 6262 6263 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6264 sc->rx_prod); 6265 6266 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6267 sc->rx_cons); 6268 6269 BNX_PRINTF(sc, 6270 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6271 sc->rx_prod_bseq); 6272 6273 BNX_PRINTF(sc, 6274 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6275 sc->rx_mbuf_alloc); 6276 6277 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6278 sc->free_rx_bd); 6279 6280 BNX_PRINTF(sc, 6281 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6282 sc->rx_low_watermark, sc->max_rx_bd); 6283 6284 BNX_PRINTF(sc, 6285 " 0x%08X - (sc->mbuf_alloc_failed) " 6286 "mbuf alloc failures\n", 6287 sc->mbuf_alloc_failed); 6288 6289 BNX_PRINTF(sc, 6290 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6291 "simulated mbuf alloc failures\n", 6292 sc->mbuf_sim_alloc_failed); 6293 6294 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6295 "-----------------------------\n"); 6296 } 6297 6298 void 6299 bnx_dump_hw_state(struct bnx_softc *sc) 6300 { 6301 u_int32_t val1; 6302 int i; 6303 6304 aprint_debug_dev(sc->bnx_dev, 6305 "----------------------------" 6306 " Hardware State " 6307 "----------------------------\n"); 6308 6309 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6310 6311 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6312 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6313 val1, BNX_MISC_ENABLE_STATUS_BITS); 6314 6315 val1 = REG_RD(sc, BNX_DMA_STATUS); 6316 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6317 6318 val1 = REG_RD(sc, BNX_CTX_STATUS); 6319 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6320 6321 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6322 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6323 BNX_EMAC_STATUS); 6324 6325 val1 = REG_RD(sc, BNX_RPM_STATUS); 6326 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6327 6328 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6329 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6330 BNX_TBDR_STATUS); 6331 6332 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6333 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6334 BNX_TDMA_STATUS); 6335 6336 val1 = REG_RD(sc, BNX_HC_STATUS); 6337 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6338 6339 aprint_debug_dev(sc->bnx_dev, 6340 "----------------------------" 6341 "----------------" 6342 "----------------------------\n"); 6343 6344 aprint_debug_dev(sc->bnx_dev, 6345 "----------------------------" 6346 " Register Dump " 6347 "----------------------------\n"); 6348 6349 for (i = 0x400; i < 0x8000; i += 0x10) 6350 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6351 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6352 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6353 6354 aprint_debug_dev(sc->bnx_dev, 6355 "----------------------------" 6356 "----------------" 6357 "----------------------------\n"); 6358 } 6359 6360 void 6361 bnx_breakpoint(struct bnx_softc *sc) 6362 { 6363 /* Unreachable code to shut the compiler up about unused functions. */ 6364 if (0) { 6365 bnx_dump_txbd(sc, 0, NULL); 6366 bnx_dump_rxbd(sc, 0, NULL); 6367 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6368 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6369 bnx_dump_l2fhdr(sc, 0, NULL); 6370 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6371 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6372 bnx_dump_status_block(sc); 6373 bnx_dump_stats_block(sc); 6374 bnx_dump_driver_state(sc); 6375 bnx_dump_hw_state(sc); 6376 } 6377 6378 bnx_dump_driver_state(sc); 6379 /* Print the important status block fields. */ 6380 bnx_dump_status_block(sc); 6381 6382 #if 0 6383 /* Call the debugger. */ 6384 breakpoint(); 6385 #endif 6386 6387 return; 6388 } 6389 #endif 6390
Indexes created Sat Sep 27 14:09:57 GMT 2025