if_bnx.c revision 1.55
1 /* $NetBSD: if_bnx.c,v 1.55 2014/07/01 15:23:35 msaitoh Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.55 2014/07/01 15:23:35 msaitoh Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 /****************************************************************************/ 180 /* Supported Flash NVRAM device data. */ 181 /****************************************************************************/ 182 static struct flash_spec flash_table[] = 183 { 184 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 185 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 186 /* Slow EEPROM */ 187 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 188 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 189 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 190 "EEPROM - slow"}, 191 /* Expansion entry 0001 */ 192 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0001"}, 196 /* Saifun SA25F010 (non-buffered flash) */ 197 /* strap, cfg1, & write1 need updates */ 198 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 201 "Non-buffered flash (128kB)"}, 202 /* Saifun SA25F020 (non-buffered flash) */ 203 /* strap, cfg1, & write1 need updates */ 204 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 205 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 206 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 207 "Non-buffered flash (256kB)"}, 208 /* Expansion entry 0100 */ 209 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 210 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 211 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 212 "Entry 0100"}, 213 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 214 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 216 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 217 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 218 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 219 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 221 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 222 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 223 /* Saifun SA25F005 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 228 "Non-buffered flash (64kB)"}, 229 /* Fast EEPROM */ 230 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 231 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 232 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 233 "EEPROM - fast"}, 234 /* Expansion entry 1001 */ 235 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 236 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 237 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 238 "Entry 1001"}, 239 /* Expansion entry 1010 */ 240 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 241 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 242 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 243 "Entry 1010"}, 244 /* ATMEL AT45DB011B (buffered flash) */ 245 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 246 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 247 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 248 "Buffered flash (128kB)"}, 249 /* Expansion entry 1100 */ 250 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 251 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 252 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 253 "Entry 1100"}, 254 /* Expansion entry 1101 */ 255 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 256 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 257 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 258 "Entry 1101"}, 259 /* Ateml Expansion entry 1110 */ 260 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 261 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 262 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 263 "Entry 1110 (Atmel)"}, 264 /* ATMEL AT45DB021B (buffered flash) */ 265 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 266 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 267 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 268 "Buffered flash (256kB)"}, 269 }; 270 271 /* 272 * The BCM5709 controllers transparently handle the 273 * differences between Atmel 264 byte pages and all 274 * flash devices which use 256 byte pages, so no 275 * logical-to-physical mapping is required in the 276 * driver. 277 */ 278 static struct flash_spec flash_5709 = { 279 .flags = BNX_NV_BUFFERED, 280 .page_bits = BCM5709_FLASH_PAGE_BITS, 281 .page_size = BCM5709_FLASH_PAGE_SIZE, 282 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 283 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 284 .name = "5709 buffered flash (256kB)", 285 }; 286 287 /****************************************************************************/ 288 /* OpenBSD device entry points. */ 289 /****************************************************************************/ 290 static int bnx_probe(device_t, cfdata_t, void *); 291 void bnx_attach(device_t, device_t, void *); 292 int bnx_detach(device_t, int); 293 294 /****************************************************************************/ 295 /* BNX Debug Data Structure Dump Routines */ 296 /****************************************************************************/ 297 #ifdef BNX_DEBUG 298 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 299 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 300 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 302 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 303 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 304 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 305 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_status_block(struct bnx_softc *); 307 void bnx_dump_stats_block(struct bnx_softc *); 308 void bnx_dump_driver_state(struct bnx_softc *); 309 void bnx_dump_hw_state(struct bnx_softc *); 310 void bnx_breakpoint(struct bnx_softc *); 311 #endif 312 313 /****************************************************************************/ 314 /* BNX Register/Memory Access Routines */ 315 /****************************************************************************/ 316 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 317 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 318 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 319 int bnx_miibus_read_reg(device_t, int, int); 320 void bnx_miibus_write_reg(device_t, int, int, int); 321 void bnx_miibus_statchg(struct ifnet *); 322 323 /****************************************************************************/ 324 /* BNX NVRAM Access Routines */ 325 /****************************************************************************/ 326 int bnx_acquire_nvram_lock(struct bnx_softc *); 327 int bnx_release_nvram_lock(struct bnx_softc *); 328 void bnx_enable_nvram_access(struct bnx_softc *); 329 void bnx_disable_nvram_access(struct bnx_softc *); 330 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 331 uint32_t); 332 int bnx_init_nvram(struct bnx_softc *); 333 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 334 int bnx_nvram_test(struct bnx_softc *); 335 #ifdef BNX_NVRAM_WRITE_SUPPORT 336 int bnx_enable_nvram_write(struct bnx_softc *); 337 void bnx_disable_nvram_write(struct bnx_softc *); 338 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 339 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 340 uint32_t); 341 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 342 #endif 343 344 /****************************************************************************/ 345 /* */ 346 /****************************************************************************/ 347 void bnx_get_media(struct bnx_softc *); 348 void bnx_init_media(struct bnx_softc *); 349 int bnx_dma_alloc(struct bnx_softc *); 350 void bnx_dma_free(struct bnx_softc *); 351 void bnx_release_resources(struct bnx_softc *); 352 353 /****************************************************************************/ 354 /* BNX Firmware Synchronization and Load */ 355 /****************************************************************************/ 356 int bnx_fw_sync(struct bnx_softc *, uint32_t); 357 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, 358 uint32_t); 359 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 360 struct fw_info *); 361 void bnx_init_cpus(struct bnx_softc *); 362 363 void bnx_stop(struct ifnet *, int); 364 int bnx_reset(struct bnx_softc *, uint32_t); 365 int bnx_chipinit(struct bnx_softc *); 366 int bnx_blockinit(struct bnx_softc *); 367 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 368 uint16_t *, uint32_t *); 369 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 370 371 int bnx_init_tx_chain(struct bnx_softc *); 372 void bnx_init_tx_context(struct bnx_softc *); 373 int bnx_init_rx_chain(struct bnx_softc *); 374 void bnx_init_rx_context(struct bnx_softc *); 375 void bnx_free_rx_chain(struct bnx_softc *); 376 void bnx_free_tx_chain(struct bnx_softc *); 377 378 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 379 void bnx_start(struct ifnet *); 380 int bnx_ioctl(struct ifnet *, u_long, void *); 381 void bnx_watchdog(struct ifnet *); 382 int bnx_init(struct ifnet *); 383 384 void bnx_init_context(struct bnx_softc *); 385 void bnx_get_mac_addr(struct bnx_softc *); 386 void bnx_set_mac_addr(struct bnx_softc *); 387 void bnx_phy_intr(struct bnx_softc *); 388 void bnx_rx_intr(struct bnx_softc *); 389 void bnx_tx_intr(struct bnx_softc *); 390 void bnx_disable_intr(struct bnx_softc *); 391 void bnx_enable_intr(struct bnx_softc *); 392 393 int bnx_intr(void *); 394 void bnx_iff(struct bnx_softc *); 395 void bnx_stats_update(struct bnx_softc *); 396 void bnx_tick(void *); 397 398 struct pool *bnx_tx_pool = NULL; 399 void bnx_alloc_pkts(struct work *, void *); 400 401 /****************************************************************************/ 402 /* OpenBSD device dispatch table. */ 403 /****************************************************************************/ 404 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 405 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 406 407 /****************************************************************************/ 408 /* Device probe function. */ 409 /* */ 410 /* Compares the device to the driver's list of supported devices and */ 411 /* reports back to the OS whether this is the right driver for the device. */ 412 /* */ 413 /* Returns: */ 414 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 415 /****************************************************************************/ 416 static const struct bnx_product * 417 bnx_lookup(const struct pci_attach_args *pa) 418 { 419 int i; 420 pcireg_t subid; 421 422 for (i = 0; i < __arraycount(bnx_devices); i++) { 423 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 424 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 425 continue; 426 if (!bnx_devices[i].bp_subvendor) 427 return &bnx_devices[i]; 428 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 429 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 430 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 431 return &bnx_devices[i]; 432 } 433 434 return NULL; 435 } 436 static int 437 bnx_probe(device_t parent, cfdata_t match, void *aux) 438 { 439 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 440 441 if (bnx_lookup(pa) != NULL) 442 return 1; 443 444 return 0; 445 } 446 447 /****************************************************************************/ 448 /* Device attach function. */ 449 /* */ 450 /* Allocates device resources, performs secondary chip identification, */ 451 /* resets and initializes the hardware, and initializes driver instance */ 452 /* variables. */ 453 /* */ 454 /* Returns: */ 455 /* 0 on success, positive value on failure. */ 456 /****************************************************************************/ 457 void 458 bnx_attach(device_t parent, device_t self, void *aux) 459 { 460 const struct bnx_product *bp; 461 struct bnx_softc *sc = device_private(self); 462 prop_dictionary_t dict; 463 struct pci_attach_args *pa = aux; 464 pci_chipset_tag_t pc = pa->pa_pc; 465 pci_intr_handle_t ih; 466 const char *intrstr = NULL; 467 uint32_t command; 468 struct ifnet *ifp; 469 uint32_t val; 470 int mii_flags = MIIF_FORCEANEG; 471 pcireg_t memtype; 472 char intrbuf[PCI_INTRSTR_LEN]; 473 474 if (bnx_tx_pool == NULL) { 475 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 476 if (bnx_tx_pool != NULL) { 477 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 478 0, 0, 0, "bnxpkts", NULL, IPL_NET); 479 } else { 480 aprint_error(": can't alloc bnx_tx_pool\n"); 481 return; 482 } 483 } 484 485 bp = bnx_lookup(pa); 486 if (bp == NULL) 487 panic("unknown device"); 488 489 sc->bnx_dev = self; 490 491 aprint_naive("\n"); 492 aprint_normal(": %s\n", bp->bp_name); 493 494 sc->bnx_pa = *pa; 495 496 /* 497 * Map control/status registers. 498 */ 499 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 501 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 502 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 503 504 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 505 aprint_error_dev(sc->bnx_dev, 506 "failed to enable memory mapping!\n"); 507 return; 508 } 509 510 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 511 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 512 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 513 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 514 return; 515 } 516 517 if (pci_intr_map(pa, &ih)) { 518 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 519 goto bnx_attach_fail; 520 } 521 522 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 523 524 /* 525 * Configure byte swap and enable indirect register access. 526 * Rely on CPU to do target byte swapping on big endian systems. 527 * Access to registers outside of PCI configurtion space are not 528 * valid until this is done. 529 */ 530 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 531 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 532 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 533 534 /* Save ASIC revsion info. */ 535 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 536 537 /* 538 * Find the base address for shared memory access. 539 * Newer versions of bootcode use a signature and offset 540 * while older versions use a fixed address. 541 */ 542 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 543 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 544 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 545 (sc->bnx_pa.pa_function << 2)); 546 else 547 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 548 549 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 550 551 /* Set initial device and PHY flags */ 552 sc->bnx_flags = 0; 553 sc->bnx_phy_flags = 0; 554 555 /* Get PCI bus information (speed and type). */ 556 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 557 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 558 uint32_t clkreg; 559 560 sc->bnx_flags |= BNX_PCIX_FLAG; 561 562 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 563 564 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 565 switch (clkreg) { 566 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 567 sc->bus_speed_mhz = 133; 568 break; 569 570 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 571 sc->bus_speed_mhz = 100; 572 break; 573 574 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 575 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 576 sc->bus_speed_mhz = 66; 577 break; 578 579 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 580 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 581 sc->bus_speed_mhz = 50; 582 break; 583 584 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 585 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 586 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 587 sc->bus_speed_mhz = 33; 588 break; 589 } 590 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 591 sc->bus_speed_mhz = 66; 592 else 593 sc->bus_speed_mhz = 33; 594 595 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 596 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 597 598 /* Reset the controller. */ 599 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 600 goto bnx_attach_fail; 601 602 /* Initialize the controller. */ 603 if (bnx_chipinit(sc)) { 604 aprint_error_dev(sc->bnx_dev, 605 "Controller initialization failed!\n"); 606 goto bnx_attach_fail; 607 } 608 609 /* Perform NVRAM test. */ 610 if (bnx_nvram_test(sc)) { 611 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 612 goto bnx_attach_fail; 613 } 614 615 /* Fetch the permanent Ethernet MAC address. */ 616 bnx_get_mac_addr(sc); 617 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 618 ether_sprintf(sc->eaddr)); 619 620 /* 621 * Trip points control how many BDs 622 * should be ready before generating an 623 * interrupt while ticks control how long 624 * a BD can sit in the chain before 625 * generating an interrupt. Set the default 626 * values for the RX and TX rings. 627 */ 628 629 #ifdef BNX_DEBUG 630 /* Force more frequent interrupts. */ 631 sc->bnx_tx_quick_cons_trip_int = 1; 632 sc->bnx_tx_quick_cons_trip = 1; 633 sc->bnx_tx_ticks_int = 0; 634 sc->bnx_tx_ticks = 0; 635 636 sc->bnx_rx_quick_cons_trip_int = 1; 637 sc->bnx_rx_quick_cons_trip = 1; 638 sc->bnx_rx_ticks_int = 0; 639 sc->bnx_rx_ticks = 0; 640 #else 641 sc->bnx_tx_quick_cons_trip_int = 20; 642 sc->bnx_tx_quick_cons_trip = 20; 643 sc->bnx_tx_ticks_int = 80; 644 sc->bnx_tx_ticks = 80; 645 646 sc->bnx_rx_quick_cons_trip_int = 6; 647 sc->bnx_rx_quick_cons_trip = 6; 648 sc->bnx_rx_ticks_int = 18; 649 sc->bnx_rx_ticks = 18; 650 #endif 651 652 /* Update statistics once every second. */ 653 sc->bnx_stats_ticks = 1000000 & 0xffff00; 654 655 /* Find the media type for the adapter. */ 656 bnx_get_media(sc); 657 658 /* 659 * Store config data needed by the PHY driver for 660 * backplane applications 661 */ 662 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 663 BNX_SHARED_HW_CFG_CONFIG); 664 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 665 BNX_PORT_HW_CFG_CONFIG); 666 667 /* Allocate DMA memory resources. */ 668 sc->bnx_dmatag = pa->pa_dmat; 669 if (bnx_dma_alloc(sc)) { 670 aprint_error_dev(sc->bnx_dev, 671 "DMA resource allocation failed!\n"); 672 goto bnx_attach_fail; 673 } 674 675 /* Initialize the ifnet interface. */ 676 ifp = &sc->bnx_ec.ec_if; 677 ifp->if_softc = sc; 678 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 679 ifp->if_ioctl = bnx_ioctl; 680 ifp->if_stop = bnx_stop; 681 ifp->if_start = bnx_start; 682 ifp->if_init = bnx_init; 683 ifp->if_timer = 0; 684 ifp->if_watchdog = bnx_watchdog; 685 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 686 IFQ_SET_READY(&ifp->if_snd); 687 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 688 689 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 690 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 691 692 ifp->if_capabilities |= 693 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 694 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 695 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 696 697 /* Hookup IRQ last. */ 698 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 699 if (sc->bnx_intrhand == NULL) { 700 aprint_error_dev(self, "couldn't establish interrupt"); 701 if (intrstr != NULL) 702 aprint_error(" at %s", intrstr); 703 aprint_error("\n"); 704 goto bnx_attach_fail; 705 } 706 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 707 708 /* create workqueue to handle packet allocations */ 709 if (workqueue_create(&sc->bnx_wq, device_xname(self), 710 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 711 aprint_error_dev(self, "failed to create workqueue\n"); 712 goto bnx_attach_fail; 713 } 714 715 sc->bnx_mii.mii_ifp = ifp; 716 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 717 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 718 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 719 720 /* Handle any special PHY initialization for SerDes PHYs. */ 721 bnx_init_media(sc); 722 723 sc->bnx_ec.ec_mii = &sc->bnx_mii; 724 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 725 ether_mediastatus); 726 727 /* set phyflags and chipid before mii_attach() */ 728 dict = device_properties(self); 729 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 730 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 731 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 732 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 733 734 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 735 mii_flags |= MIIF_HAVEFIBER; 736 mii_attach(self, &sc->bnx_mii, 0xffffffff, 737 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 738 739 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 740 aprint_error_dev(self, "no PHY found!\n"); 741 ifmedia_add(&sc->bnx_mii.mii_media, 742 IFM_ETHER|IFM_MANUAL, 0, NULL); 743 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_MANUAL); 744 } else 745 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_AUTO); 746 747 /* Attach to the Ethernet interface list. */ 748 if_attach(ifp); 749 ether_ifattach(ifp,sc->eaddr); 750 751 callout_init(&sc->bnx_timeout, 0); 752 753 if (pmf_device_register(self, NULL, NULL)) 754 pmf_class_network_register(self, ifp); 755 else 756 aprint_error_dev(self, "couldn't establish power handler\n"); 757 758 /* Print some important debugging info. */ 759 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 760 761 goto bnx_attach_exit; 762 763 bnx_attach_fail: 764 bnx_release_resources(sc); 765 766 bnx_attach_exit: 767 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 768 } 769 770 /****************************************************************************/ 771 /* Device detach function. */ 772 /* */ 773 /* Stops the controller, resets the controller, and releases resources. */ 774 /* */ 775 /* Returns: */ 776 /* 0 on success, positive value on failure. */ 777 /****************************************************************************/ 778 int 779 bnx_detach(device_t dev, int flags) 780 { 781 int s; 782 struct bnx_softc *sc; 783 struct ifnet *ifp; 784 785 sc = device_private(dev); 786 ifp = &sc->bnx_ec.ec_if; 787 788 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 789 790 /* Stop and reset the controller. */ 791 s = splnet(); 792 if (ifp->if_flags & IFF_RUNNING) 793 bnx_stop(ifp, 1); 794 else { 795 /* Disable the transmit/receive blocks. */ 796 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 797 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 798 DELAY(20); 799 bnx_disable_intr(sc); 800 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 801 } 802 803 splx(s); 804 805 pmf_device_deregister(dev); 806 callout_destroy(&sc->bnx_timeout); 807 ether_ifdetach(ifp); 808 workqueue_destroy(sc->bnx_wq); 809 810 /* Delete all remaining media. */ 811 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 812 813 if_detach(ifp); 814 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 815 816 /* Release all remaining resources. */ 817 bnx_release_resources(sc); 818 819 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 820 821 return 0; 822 } 823 824 /****************************************************************************/ 825 /* Indirect register read. */ 826 /* */ 827 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 828 /* configuration space. Using this mechanism avoids issues with posted */ 829 /* reads but is much slower than memory-mapped I/O. */ 830 /* */ 831 /* Returns: */ 832 /* The value of the register. */ 833 /****************************************************************************/ 834 uint32_t 835 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 836 { 837 struct pci_attach_args *pa = &(sc->bnx_pa); 838 839 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 840 offset); 841 #ifdef BNX_DEBUG 842 { 843 uint32_t val; 844 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 845 BNX_PCICFG_REG_WINDOW); 846 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 847 "val = 0x%08X\n", __func__, offset, val); 848 return val; 849 } 850 #else 851 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 852 #endif 853 } 854 855 /****************************************************************************/ 856 /* Indirect register write. */ 857 /* */ 858 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 859 /* configuration space. Using this mechanism avoids issues with posted */ 860 /* writes but is muchh slower than memory-mapped I/O. */ 861 /* */ 862 /* Returns: */ 863 /* Nothing. */ 864 /****************************************************************************/ 865 void 866 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 867 { 868 struct pci_attach_args *pa = &(sc->bnx_pa); 869 870 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 871 __func__, offset, val); 872 873 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 874 offset); 875 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 876 } 877 878 /****************************************************************************/ 879 /* Context memory write. */ 880 /* */ 881 /* The NetXtreme II controller uses context memory to track connection */ 882 /* information for L2 and higher network protocols. */ 883 /* */ 884 /* Returns: */ 885 /* Nothing. */ 886 /****************************************************************************/ 887 void 888 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 889 uint32_t ctx_val) 890 { 891 uint32_t idx, offset = ctx_offset + cid_addr; 892 uint32_t val, retry_cnt = 5; 893 894 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 895 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 896 REG_WR(sc, BNX_CTX_CTX_CTRL, 897 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 898 899 for (idx = 0; idx < retry_cnt; idx++) { 900 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 901 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 902 break; 903 DELAY(5); 904 } 905 906 #if 0 907 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 908 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 909 "cid_addr = 0x%08X, offset = 0x%08X!\n", 910 __FILE__, __LINE__, cid_addr, ctx_offset); 911 #endif 912 913 } else { 914 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 915 REG_WR(sc, BNX_CTX_DATA, ctx_val); 916 } 917 } 918 919 /****************************************************************************/ 920 /* PHY register read. */ 921 /* */ 922 /* Implements register reads on the MII bus. */ 923 /* */ 924 /* Returns: */ 925 /* The value of the register. */ 926 /****************************************************************************/ 927 int 928 bnx_miibus_read_reg(device_t dev, int phy, int reg) 929 { 930 struct bnx_softc *sc = device_private(dev); 931 uint32_t val; 932 int i; 933 934 /* Make sure we are accessing the correct PHY address. */ 935 if (phy != sc->bnx_phy_addr) { 936 DBPRINT(sc, BNX_VERBOSE, 937 "Invalid PHY address %d for PHY read!\n", phy); 938 return 0; 939 } 940 941 /* 942 * The BCM5709S PHY is an IEEE Clause 45 PHY 943 * with special mappings to work with IEEE 944 * Clause 22 register accesses. 945 */ 946 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 947 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 948 reg += 0x10; 949 } 950 951 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 952 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 953 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 954 955 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 956 REG_RD(sc, BNX_EMAC_MDIO_MODE); 957 958 DELAY(40); 959 } 960 961 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 962 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 963 BNX_EMAC_MDIO_COMM_START_BUSY; 964 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 965 966 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 967 DELAY(10); 968 969 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 970 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 971 DELAY(5); 972 973 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 974 val &= BNX_EMAC_MDIO_COMM_DATA; 975 976 break; 977 } 978 } 979 980 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 981 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 982 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 983 val = 0x0; 984 } else 985 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 986 987 DBPRINT(sc, BNX_EXCESSIVE, 988 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 989 (uint16_t) reg & 0xffff, (uint16_t) val & 0xffff); 990 991 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 992 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 993 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 994 995 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 996 REG_RD(sc, BNX_EMAC_MDIO_MODE); 997 998 DELAY(40); 999 } 1000 1001 return (val & 0xffff); 1002 } 1003 1004 /****************************************************************************/ 1005 /* PHY register write. */ 1006 /* */ 1007 /* Implements register writes on the MII bus. */ 1008 /* */ 1009 /* Returns: */ 1010 /* The value of the register. */ 1011 /****************************************************************************/ 1012 void 1013 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 1014 { 1015 struct bnx_softc *sc = device_private(dev); 1016 uint32_t val1; 1017 int i; 1018 1019 /* Make sure we are accessing the correct PHY address. */ 1020 if (phy != sc->bnx_phy_addr) { 1021 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 1022 phy); 1023 return; 1024 } 1025 1026 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1027 "val = 0x%04X\n", __func__, 1028 phy, (uint16_t) reg & 0xffff, (uint16_t) val & 0xffff); 1029 1030 /* 1031 * The BCM5709S PHY is an IEEE Clause 45 PHY 1032 * with special mappings to work with IEEE 1033 * Clause 22 register accesses. 1034 */ 1035 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1036 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1037 reg += 0x10; 1038 } 1039 1040 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1041 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1042 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1043 1044 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1045 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1046 1047 DELAY(40); 1048 } 1049 1050 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1051 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1052 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1053 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1054 1055 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1056 DELAY(10); 1057 1058 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1059 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1060 DELAY(5); 1061 break; 1062 } 1063 } 1064 1065 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1066 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1067 __LINE__); 1068 } 1069 1070 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1071 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1072 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1073 1074 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1075 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1076 1077 DELAY(40); 1078 } 1079 } 1080 1081 /****************************************************************************/ 1082 /* MII bus status change. */ 1083 /* */ 1084 /* Called by the MII bus driver when the PHY establishes link to set the */ 1085 /* MAC interface registers. */ 1086 /* */ 1087 /* Returns: */ 1088 /* Nothing. */ 1089 /****************************************************************************/ 1090 void 1091 bnx_miibus_statchg(struct ifnet *ifp) 1092 { 1093 struct bnx_softc *sc = ifp->if_softc; 1094 struct mii_data *mii = &sc->bnx_mii; 1095 int val; 1096 1097 val = REG_RD(sc, BNX_EMAC_MODE); 1098 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1099 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1100 BNX_EMAC_MODE_25G); 1101 1102 /* Set MII or GMII interface based on the speed 1103 * negotiated by the PHY. 1104 */ 1105 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1106 case IFM_10_T: 1107 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1108 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1109 val |= BNX_EMAC_MODE_PORT_MII_10; 1110 break; 1111 } 1112 /* FALLTHROUGH */ 1113 case IFM_100_TX: 1114 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1115 val |= BNX_EMAC_MODE_PORT_MII; 1116 break; 1117 case IFM_2500_SX: 1118 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1119 val |= BNX_EMAC_MODE_25G; 1120 /* FALLTHROUGH */ 1121 case IFM_1000_T: 1122 case IFM_1000_SX: 1123 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1124 val |= BNX_EMAC_MODE_PORT_GMII; 1125 break; 1126 default: 1127 val |= BNX_EMAC_MODE_PORT_GMII; 1128 break; 1129 } 1130 1131 /* Set half or full duplex based on the duplicity 1132 * negotiated by the PHY. 1133 */ 1134 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1135 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1136 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1137 } else { 1138 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1139 } 1140 1141 REG_WR(sc, BNX_EMAC_MODE, val); 1142 } 1143 1144 /****************************************************************************/ 1145 /* Acquire NVRAM lock. */ 1146 /* */ 1147 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1148 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1149 /* for use by the driver. */ 1150 /* */ 1151 /* Returns: */ 1152 /* 0 on success, positive value on failure. */ 1153 /****************************************************************************/ 1154 int 1155 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1156 { 1157 uint32_t val; 1158 int j; 1159 1160 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1161 1162 /* Request access to the flash interface. */ 1163 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1164 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1165 val = REG_RD(sc, BNX_NVM_SW_ARB); 1166 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1167 break; 1168 1169 DELAY(5); 1170 } 1171 1172 if (j >= NVRAM_TIMEOUT_COUNT) { 1173 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1174 return EBUSY; 1175 } 1176 1177 return 0; 1178 } 1179 1180 /****************************************************************************/ 1181 /* Release NVRAM lock. */ 1182 /* */ 1183 /* When the caller is finished accessing NVRAM the lock must be released. */ 1184 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1185 /* for use by the driver. */ 1186 /* */ 1187 /* Returns: */ 1188 /* 0 on success, positive value on failure. */ 1189 /****************************************************************************/ 1190 int 1191 bnx_release_nvram_lock(struct bnx_softc *sc) 1192 { 1193 int j; 1194 uint32_t val; 1195 1196 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1197 1198 /* Relinquish nvram interface. */ 1199 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1200 1201 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1202 val = REG_RD(sc, BNX_NVM_SW_ARB); 1203 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1204 break; 1205 1206 DELAY(5); 1207 } 1208 1209 if (j >= NVRAM_TIMEOUT_COUNT) { 1210 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1211 return EBUSY; 1212 } 1213 1214 return 0; 1215 } 1216 1217 #ifdef BNX_NVRAM_WRITE_SUPPORT 1218 /****************************************************************************/ 1219 /* Enable NVRAM write access. */ 1220 /* */ 1221 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1222 /* */ 1223 /* Returns: */ 1224 /* 0 on success, positive value on failure. */ 1225 /****************************************************************************/ 1226 int 1227 bnx_enable_nvram_write(struct bnx_softc *sc) 1228 { 1229 uint32_t val; 1230 1231 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1232 1233 val = REG_RD(sc, BNX_MISC_CFG); 1234 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1235 1236 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1237 int j; 1238 1239 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1240 REG_WR(sc, BNX_NVM_COMMAND, 1241 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1242 1243 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1244 DELAY(5); 1245 1246 val = REG_RD(sc, BNX_NVM_COMMAND); 1247 if (val & BNX_NVM_COMMAND_DONE) 1248 break; 1249 } 1250 1251 if (j >= NVRAM_TIMEOUT_COUNT) { 1252 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1253 return EBUSY; 1254 } 1255 } 1256 1257 return 0; 1258 } 1259 1260 /****************************************************************************/ 1261 /* Disable NVRAM write access. */ 1262 /* */ 1263 /* When the caller is finished writing to NVRAM write access must be */ 1264 /* disabled. */ 1265 /* */ 1266 /* Returns: */ 1267 /* Nothing. */ 1268 /****************************************************************************/ 1269 void 1270 bnx_disable_nvram_write(struct bnx_softc *sc) 1271 { 1272 uint32_t val; 1273 1274 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1275 1276 val = REG_RD(sc, BNX_MISC_CFG); 1277 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1278 } 1279 #endif 1280 1281 /****************************************************************************/ 1282 /* Enable NVRAM access. */ 1283 /* */ 1284 /* Before accessing NVRAM for read or write operations the caller must */ 1285 /* enabled NVRAM access. */ 1286 /* */ 1287 /* Returns: */ 1288 /* Nothing. */ 1289 /****************************************************************************/ 1290 void 1291 bnx_enable_nvram_access(struct bnx_softc *sc) 1292 { 1293 uint32_t val; 1294 1295 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1296 1297 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1298 /* Enable both bits, even on read. */ 1299 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1300 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1301 } 1302 1303 /****************************************************************************/ 1304 /* Disable NVRAM access. */ 1305 /* */ 1306 /* When the caller is finished accessing NVRAM access must be disabled. */ 1307 /* */ 1308 /* Returns: */ 1309 /* Nothing. */ 1310 /****************************************************************************/ 1311 void 1312 bnx_disable_nvram_access(struct bnx_softc *sc) 1313 { 1314 uint32_t val; 1315 1316 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1317 1318 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1319 1320 /* Disable both bits, even after read. */ 1321 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1322 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1323 } 1324 1325 #ifdef BNX_NVRAM_WRITE_SUPPORT 1326 /****************************************************************************/ 1327 /* Erase NVRAM page before writing. */ 1328 /* */ 1329 /* Non-buffered flash parts require that a page be erased before it is */ 1330 /* written. */ 1331 /* */ 1332 /* Returns: */ 1333 /* 0 on success, positive value on failure. */ 1334 /****************************************************************************/ 1335 int 1336 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1337 { 1338 uint32_t cmd; 1339 int j; 1340 1341 /* Buffered flash doesn't require an erase. */ 1342 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1343 return 0; 1344 1345 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1346 1347 /* Build an erase command. */ 1348 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1349 BNX_NVM_COMMAND_DOIT; 1350 1351 /* 1352 * Clear the DONE bit separately, set the NVRAM address to erase, 1353 * and issue the erase command. 1354 */ 1355 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1356 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1357 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1358 1359 /* Wait for completion. */ 1360 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1361 uint32_t val; 1362 1363 DELAY(5); 1364 1365 val = REG_RD(sc, BNX_NVM_COMMAND); 1366 if (val & BNX_NVM_COMMAND_DONE) 1367 break; 1368 } 1369 1370 if (j >= NVRAM_TIMEOUT_COUNT) { 1371 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1372 return EBUSY; 1373 } 1374 1375 return 0; 1376 } 1377 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1378 1379 /****************************************************************************/ 1380 /* Read a dword (32 bits) from NVRAM. */ 1381 /* */ 1382 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1383 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1384 /* */ 1385 /* Returns: */ 1386 /* 0 on success and the 32 bit value read, positive value on failure. */ 1387 /****************************************************************************/ 1388 int 1389 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1390 uint8_t *ret_val, uint32_t cmd_flags) 1391 { 1392 uint32_t cmd; 1393 int i, rc = 0; 1394 1395 /* Build the command word. */ 1396 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1397 1398 /* Calculate the offset for buffered flash if translation is used. */ 1399 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1400 offset = ((offset / sc->bnx_flash_info->page_size) << 1401 sc->bnx_flash_info->page_bits) + 1402 (offset % sc->bnx_flash_info->page_size); 1403 } 1404 1405 /* 1406 * Clear the DONE bit separately, set the address to read, 1407 * and issue the read. 1408 */ 1409 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1410 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1411 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1412 1413 /* Wait for completion. */ 1414 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1415 uint32_t val; 1416 1417 DELAY(5); 1418 1419 val = REG_RD(sc, BNX_NVM_COMMAND); 1420 if (val & BNX_NVM_COMMAND_DONE) { 1421 val = REG_RD(sc, BNX_NVM_READ); 1422 1423 val = bnx_be32toh(val); 1424 memcpy(ret_val, &val, 4); 1425 break; 1426 } 1427 } 1428 1429 /* Check for errors. */ 1430 if (i >= NVRAM_TIMEOUT_COUNT) { 1431 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1432 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1433 rc = EBUSY; 1434 } 1435 1436 return rc; 1437 } 1438 1439 #ifdef BNX_NVRAM_WRITE_SUPPORT 1440 /****************************************************************************/ 1441 /* Write a dword (32 bits) to NVRAM. */ 1442 /* */ 1443 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1444 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1445 /* enabled NVRAM write access. */ 1446 /* */ 1447 /* Returns: */ 1448 /* 0 on success, positive value on failure. */ 1449 /****************************************************************************/ 1450 int 1451 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1452 uint32_t cmd_flags) 1453 { 1454 uint32_t cmd, val32; 1455 int j; 1456 1457 /* Build the command word. */ 1458 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1459 1460 /* Calculate the offset for buffered flash if translation is used. */ 1461 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1462 offset = ((offset / sc->bnx_flash_info->page_size) << 1463 sc->bnx_flash_info->page_bits) + 1464 (offset % sc->bnx_flash_info->page_size); 1465 } 1466 1467 /* 1468 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1469 * set the NVRAM address to write, and issue the write command 1470 */ 1471 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1472 memcpy(&val32, val, 4); 1473 val32 = htobe32(val32); 1474 REG_WR(sc, BNX_NVM_WRITE, val32); 1475 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1476 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1477 1478 /* Wait for completion. */ 1479 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1480 DELAY(5); 1481 1482 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1483 break; 1484 } 1485 if (j >= NVRAM_TIMEOUT_COUNT) { 1486 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1487 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1488 return EBUSY; 1489 } 1490 1491 return 0; 1492 } 1493 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1494 1495 /****************************************************************************/ 1496 /* Initialize NVRAM access. */ 1497 /* */ 1498 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1499 /* access that device. */ 1500 /* */ 1501 /* Returns: */ 1502 /* 0 on success, positive value on failure. */ 1503 /****************************************************************************/ 1504 int 1505 bnx_init_nvram(struct bnx_softc *sc) 1506 { 1507 uint32_t val; 1508 int j, entry_count, rc = 0; 1509 struct flash_spec *flash; 1510 1511 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1512 1513 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1514 sc->bnx_flash_info = &flash_5709; 1515 goto bnx_init_nvram_get_flash_size; 1516 } 1517 1518 /* Determine the selected interface. */ 1519 val = REG_RD(sc, BNX_NVM_CFG1); 1520 1521 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1522 1523 /* 1524 * Flash reconfiguration is required to support additional 1525 * NVRAM devices not directly supported in hardware. 1526 * Check if the flash interface was reconfigured 1527 * by the bootcode. 1528 */ 1529 1530 if (val & 0x40000000) { 1531 /* Flash interface reconfigured by bootcode. */ 1532 1533 DBPRINT(sc,BNX_INFO_LOAD, 1534 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1535 1536 for (j = 0, flash = &flash_table[0]; j < entry_count; 1537 j++, flash++) { 1538 if ((val & FLASH_BACKUP_STRAP_MASK) == 1539 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1540 sc->bnx_flash_info = flash; 1541 break; 1542 } 1543 } 1544 } else { 1545 /* Flash interface not yet reconfigured. */ 1546 uint32_t mask; 1547 1548 DBPRINT(sc,BNX_INFO_LOAD, 1549 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1550 1551 if (val & (1 << 23)) 1552 mask = FLASH_BACKUP_STRAP_MASK; 1553 else 1554 mask = FLASH_STRAP_MASK; 1555 1556 /* Look for the matching NVRAM device configuration data. */ 1557 for (j = 0, flash = &flash_table[0]; j < entry_count; 1558 j++, flash++) { 1559 /* Check if the dev matches any of the known devices. */ 1560 if ((val & mask) == (flash->strapping & mask)) { 1561 /* Found a device match. */ 1562 sc->bnx_flash_info = flash; 1563 1564 /* Request access to the flash interface. */ 1565 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1566 return rc; 1567 1568 /* Reconfigure the flash interface. */ 1569 bnx_enable_nvram_access(sc); 1570 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1571 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1572 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1573 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1574 bnx_disable_nvram_access(sc); 1575 bnx_release_nvram_lock(sc); 1576 1577 break; 1578 } 1579 } 1580 } 1581 1582 /* Check if a matching device was found. */ 1583 if (j == entry_count) { 1584 sc->bnx_flash_info = NULL; 1585 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1586 __FILE__, __LINE__); 1587 rc = ENODEV; 1588 } 1589 1590 bnx_init_nvram_get_flash_size: 1591 /* Write the flash config data to the shared memory interface. */ 1592 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1593 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1594 if (val) 1595 sc->bnx_flash_size = val; 1596 else 1597 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1598 1599 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1600 "0x%08X\n", sc->bnx_flash_info->total_size); 1601 1602 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1603 1604 return rc; 1605 } 1606 1607 /****************************************************************************/ 1608 /* Read an arbitrary range of data from NVRAM. */ 1609 /* */ 1610 /* Prepares the NVRAM interface for access and reads the requested data */ 1611 /* into the supplied buffer. */ 1612 /* */ 1613 /* Returns: */ 1614 /* 0 on success and the data read, positive value on failure. */ 1615 /****************************************************************************/ 1616 int 1617 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1618 int buf_size) 1619 { 1620 int rc = 0; 1621 uint32_t cmd_flags, offset32, len32, extra; 1622 1623 if (buf_size == 0) 1624 return 0; 1625 1626 /* Request access to the flash interface. */ 1627 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1628 return rc; 1629 1630 /* Enable access to flash interface */ 1631 bnx_enable_nvram_access(sc); 1632 1633 len32 = buf_size; 1634 offset32 = offset; 1635 extra = 0; 1636 1637 cmd_flags = 0; 1638 1639 if (offset32 & 3) { 1640 uint8_t buf[4]; 1641 uint32_t pre_len; 1642 1643 offset32 &= ~3; 1644 pre_len = 4 - (offset & 3); 1645 1646 if (pre_len >= len32) { 1647 pre_len = len32; 1648 cmd_flags = 1649 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1650 } else 1651 cmd_flags = BNX_NVM_COMMAND_FIRST; 1652 1653 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1654 1655 if (rc) 1656 return rc; 1657 1658 memcpy(ret_buf, buf + (offset & 3), pre_len); 1659 1660 offset32 += 4; 1661 ret_buf += pre_len; 1662 len32 -= pre_len; 1663 } 1664 1665 if (len32 & 3) { 1666 extra = 4 - (len32 & 3); 1667 len32 = (len32 + 4) & ~3; 1668 } 1669 1670 if (len32 == 4) { 1671 uint8_t buf[4]; 1672 1673 if (cmd_flags) 1674 cmd_flags = BNX_NVM_COMMAND_LAST; 1675 else 1676 cmd_flags = 1677 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1678 1679 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1680 1681 memcpy(ret_buf, buf, 4 - extra); 1682 } else if (len32 > 0) { 1683 uint8_t buf[4]; 1684 1685 /* Read the first word. */ 1686 if (cmd_flags) 1687 cmd_flags = 0; 1688 else 1689 cmd_flags = BNX_NVM_COMMAND_FIRST; 1690 1691 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1692 1693 /* Advance to the next dword. */ 1694 offset32 += 4; 1695 ret_buf += 4; 1696 len32 -= 4; 1697 1698 while (len32 > 4 && rc == 0) { 1699 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1700 1701 /* Advance to the next dword. */ 1702 offset32 += 4; 1703 ret_buf += 4; 1704 len32 -= 4; 1705 } 1706 1707 if (rc) 1708 return rc; 1709 1710 cmd_flags = BNX_NVM_COMMAND_LAST; 1711 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1712 1713 memcpy(ret_buf, buf, 4 - extra); 1714 } 1715 1716 /* Disable access to flash interface and release the lock. */ 1717 bnx_disable_nvram_access(sc); 1718 bnx_release_nvram_lock(sc); 1719 1720 return rc; 1721 } 1722 1723 #ifdef BNX_NVRAM_WRITE_SUPPORT 1724 /****************************************************************************/ 1725 /* Write an arbitrary range of data from NVRAM. */ 1726 /* */ 1727 /* Prepares the NVRAM interface for write access and writes the requested */ 1728 /* data from the supplied buffer. The caller is responsible for */ 1729 /* calculating any appropriate CRCs. */ 1730 /* */ 1731 /* Returns: */ 1732 /* 0 on success, positive value on failure. */ 1733 /****************************************************************************/ 1734 int 1735 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1736 int buf_size) 1737 { 1738 uint32_t written, offset32, len32; 1739 uint8_t *buf, start[4], end[4]; 1740 int rc = 0; 1741 int align_start, align_end; 1742 1743 buf = data_buf; 1744 offset32 = offset; 1745 len32 = buf_size; 1746 align_start = align_end = 0; 1747 1748 if ((align_start = (offset32 & 3))) { 1749 offset32 &= ~3; 1750 len32 += align_start; 1751 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1752 return rc; 1753 } 1754 1755 if (len32 & 3) { 1756 if ((len32 > 4) || !align_start) { 1757 align_end = 4 - (len32 & 3); 1758 len32 += align_end; 1759 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1760 end, 4))) 1761 return rc; 1762 } 1763 } 1764 1765 if (align_start || align_end) { 1766 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1767 if (buf == 0) 1768 return ENOMEM; 1769 1770 if (align_start) 1771 memcpy(buf, start, 4); 1772 1773 if (align_end) 1774 memcpy(buf + len32 - 4, end, 4); 1775 1776 memcpy(buf + align_start, data_buf, buf_size); 1777 } 1778 1779 written = 0; 1780 while ((written < len32) && (rc == 0)) { 1781 uint32_t page_start, page_end, data_start, data_end; 1782 uint32_t addr, cmd_flags; 1783 int i; 1784 uint8_t flash_buffer[264]; 1785 1786 /* Find the page_start addr */ 1787 page_start = offset32 + written; 1788 page_start -= (page_start % sc->bnx_flash_info->page_size); 1789 /* Find the page_end addr */ 1790 page_end = page_start + sc->bnx_flash_info->page_size; 1791 /* Find the data_start addr */ 1792 data_start = (written == 0) ? offset32 : page_start; 1793 /* Find the data_end addr */ 1794 data_end = (page_end > offset32 + len32) ? 1795 (offset32 + len32) : page_end; 1796 1797 /* Request access to the flash interface. */ 1798 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1799 goto nvram_write_end; 1800 1801 /* Enable access to flash interface */ 1802 bnx_enable_nvram_access(sc); 1803 1804 cmd_flags = BNX_NVM_COMMAND_FIRST; 1805 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1806 int j; 1807 1808 /* Read the whole page into the buffer 1809 * (non-buffer flash only) */ 1810 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1811 if (j == (sc->bnx_flash_info->page_size - 4)) 1812 cmd_flags |= BNX_NVM_COMMAND_LAST; 1813 1814 rc = bnx_nvram_read_dword(sc, 1815 page_start + j, 1816 &flash_buffer[j], 1817 cmd_flags); 1818 1819 if (rc) 1820 goto nvram_write_end; 1821 1822 cmd_flags = 0; 1823 } 1824 } 1825 1826 /* Enable writes to flash interface (unlock write-protect) */ 1827 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1828 goto nvram_write_end; 1829 1830 /* Erase the page */ 1831 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1832 goto nvram_write_end; 1833 1834 /* Re-enable the write again for the actual write */ 1835 bnx_enable_nvram_write(sc); 1836 1837 /* Loop to write back the buffer data from page_start to 1838 * data_start */ 1839 i = 0; 1840 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1841 for (addr = page_start; addr < data_start; 1842 addr += 4, i += 4) { 1843 1844 rc = bnx_nvram_write_dword(sc, addr, 1845 &flash_buffer[i], cmd_flags); 1846 1847 if (rc != 0) 1848 goto nvram_write_end; 1849 1850 cmd_flags = 0; 1851 } 1852 } 1853 1854 /* Loop to write the new data from data_start to data_end */ 1855 for (addr = data_start; addr < data_end; addr += 4, i++) { 1856 if ((addr == page_end - 4) || 1857 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1858 && (addr == data_end - 4))) { 1859 1860 cmd_flags |= BNX_NVM_COMMAND_LAST; 1861 } 1862 1863 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1864 1865 if (rc != 0) 1866 goto nvram_write_end; 1867 1868 cmd_flags = 0; 1869 buf += 4; 1870 } 1871 1872 /* Loop to write back the buffer data from data_end 1873 * to page_end */ 1874 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1875 for (addr = data_end; addr < page_end; 1876 addr += 4, i += 4) { 1877 1878 if (addr == page_end-4) 1879 cmd_flags = BNX_NVM_COMMAND_LAST; 1880 1881 rc = bnx_nvram_write_dword(sc, addr, 1882 &flash_buffer[i], cmd_flags); 1883 1884 if (rc != 0) 1885 goto nvram_write_end; 1886 1887 cmd_flags = 0; 1888 } 1889 } 1890 1891 /* Disable writes to flash interface (lock write-protect) */ 1892 bnx_disable_nvram_write(sc); 1893 1894 /* Disable access to flash interface */ 1895 bnx_disable_nvram_access(sc); 1896 bnx_release_nvram_lock(sc); 1897 1898 /* Increment written */ 1899 written += data_end - data_start; 1900 } 1901 1902 nvram_write_end: 1903 if (align_start || align_end) 1904 free(buf, M_DEVBUF); 1905 1906 return rc; 1907 } 1908 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1909 1910 /****************************************************************************/ 1911 /* Verifies that NVRAM is accessible and contains valid data. */ 1912 /* */ 1913 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1914 /* correct. */ 1915 /* */ 1916 /* Returns: */ 1917 /* 0 on success, positive value on failure. */ 1918 /****************************************************************************/ 1919 int 1920 bnx_nvram_test(struct bnx_softc *sc) 1921 { 1922 uint32_t buf[BNX_NVRAM_SIZE / 4]; 1923 uint8_t *data = (uint8_t *) buf; 1924 int rc = 0; 1925 uint32_t magic, csum; 1926 1927 /* 1928 * Check that the device NVRAM is valid by reading 1929 * the magic value at offset 0. 1930 */ 1931 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 1932 goto bnx_nvram_test_done; 1933 1934 magic = bnx_be32toh(buf[0]); 1935 if (magic != BNX_NVRAM_MAGIC) { 1936 rc = ENODEV; 1937 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 1938 "Expected: 0x%08X, Found: 0x%08X\n", 1939 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 1940 goto bnx_nvram_test_done; 1941 } 1942 1943 /* 1944 * Verify that the device NVRAM includes valid 1945 * configuration data. 1946 */ 1947 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 1948 goto bnx_nvram_test_done; 1949 1950 csum = ether_crc32_le(data, 0x100); 1951 if (csum != BNX_CRC32_RESIDUAL) { 1952 rc = ENODEV; 1953 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 1954 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 1955 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1956 goto bnx_nvram_test_done; 1957 } 1958 1959 csum = ether_crc32_le(data + 0x100, 0x100); 1960 if (csum != BNX_CRC32_RESIDUAL) { 1961 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 1962 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1963 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 1964 rc = ENODEV; 1965 } 1966 1967 bnx_nvram_test_done: 1968 return rc; 1969 } 1970 1971 /****************************************************************************/ 1972 /* Identifies the current media type of the controller and sets the PHY */ 1973 /* address. */ 1974 /* */ 1975 /* Returns: */ 1976 /* Nothing. */ 1977 /****************************************************************************/ 1978 void 1979 bnx_get_media(struct bnx_softc *sc) 1980 { 1981 sc->bnx_phy_addr = 1; 1982 1983 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1984 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 1985 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 1986 uint32_t strap; 1987 1988 /* 1989 * The BCM5709S is software configurable 1990 * for Copper or SerDes operation. 1991 */ 1992 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 1993 DBPRINT(sc, BNX_INFO_LOAD, 1994 "5709 bonded for copper.\n"); 1995 goto bnx_get_media_exit; 1996 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 1997 DBPRINT(sc, BNX_INFO_LOAD, 1998 "5709 bonded for dual media.\n"); 1999 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2000 goto bnx_get_media_exit; 2001 } 2002 2003 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2004 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2005 else { 2006 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2007 >> 8; 2008 } 2009 2010 if (sc->bnx_pa.pa_function == 0) { 2011 switch (strap) { 2012 case 0x4: 2013 case 0x5: 2014 case 0x6: 2015 DBPRINT(sc, BNX_INFO_LOAD, 2016 "BCM5709 s/w configured for SerDes.\n"); 2017 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2018 break; 2019 default: 2020 DBPRINT(sc, BNX_INFO_LOAD, 2021 "BCM5709 s/w configured for Copper.\n"); 2022 } 2023 } else { 2024 switch (strap) { 2025 case 0x1: 2026 case 0x2: 2027 case 0x4: 2028 DBPRINT(sc, BNX_INFO_LOAD, 2029 "BCM5709 s/w configured for SerDes.\n"); 2030 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2031 break; 2032 default: 2033 DBPRINT(sc, BNX_INFO_LOAD, 2034 "BCM5709 s/w configured for Copper.\n"); 2035 } 2036 } 2037 2038 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2039 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2040 2041 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2042 uint32_t val; 2043 2044 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2045 2046 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2047 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2048 2049 /* 2050 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2051 * separate PHY for SerDes. 2052 */ 2053 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2054 sc->bnx_phy_addr = 2; 2055 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2056 BNX_SHARED_HW_CFG_CONFIG); 2057 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2058 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2059 DBPRINT(sc, BNX_INFO_LOAD, 2060 "Found 2.5Gb capable adapter\n"); 2061 } 2062 } 2063 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2064 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2065 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2066 2067 bnx_get_media_exit: 2068 DBPRINT(sc, (BNX_INFO_LOAD), 2069 "Using PHY address %d.\n", sc->bnx_phy_addr); 2070 } 2071 2072 /****************************************************************************/ 2073 /* Performs PHY initialization required before MII drivers access the */ 2074 /* device. */ 2075 /* */ 2076 /* Returns: */ 2077 /* Nothing. */ 2078 /****************************************************************************/ 2079 void 2080 bnx_init_media(struct bnx_softc *sc) 2081 { 2082 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2083 /* 2084 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2085 * IEEE Clause 22 method. Otherwise we have no way to attach 2086 * the PHY to the mii(4) layer. PHY specific configuration 2087 * is done by the mii(4) layer. 2088 */ 2089 2090 /* Select auto-negotiation MMD of the PHY. */ 2091 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2092 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2093 2094 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2095 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2096 2097 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2098 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2099 } 2100 } 2101 2102 /****************************************************************************/ 2103 /* Free any DMA memory owned by the driver. */ 2104 /* */ 2105 /* Scans through each data structre that requires DMA memory and frees */ 2106 /* the memory if allocated. */ 2107 /* */ 2108 /* Returns: */ 2109 /* Nothing. */ 2110 /****************************************************************************/ 2111 void 2112 bnx_dma_free(struct bnx_softc *sc) 2113 { 2114 int i; 2115 2116 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2117 2118 /* Destroy the status block. */ 2119 if (sc->status_block != NULL && sc->status_map != NULL) { 2120 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2121 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2122 BNX_STATUS_BLK_SZ); 2123 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2124 sc->status_rseg); 2125 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2126 sc->status_block = NULL; 2127 sc->status_map = NULL; 2128 } 2129 2130 /* Destroy the statistics block. */ 2131 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2132 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2133 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2134 BNX_STATS_BLK_SZ); 2135 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2136 sc->stats_rseg); 2137 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2138 sc->stats_block = NULL; 2139 sc->stats_map = NULL; 2140 } 2141 2142 /* Free, unmap and destroy all context memory pages. */ 2143 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2144 for (i = 0; i < sc->ctx_pages; i++) { 2145 if (sc->ctx_block[i] != NULL) { 2146 bus_dmamap_unload(sc->bnx_dmatag, 2147 sc->ctx_map[i]); 2148 bus_dmamem_unmap(sc->bnx_dmatag, 2149 (void *)sc->ctx_block[i], 2150 BCM_PAGE_SIZE); 2151 bus_dmamem_free(sc->bnx_dmatag, 2152 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2153 bus_dmamap_destroy(sc->bnx_dmatag, 2154 sc->ctx_map[i]); 2155 sc->ctx_block[i] = NULL; 2156 } 2157 } 2158 } 2159 2160 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2161 for (i = 0; i < TX_PAGES; i++ ) { 2162 if (sc->tx_bd_chain[i] != NULL && 2163 sc->tx_bd_chain_map[i] != NULL) { 2164 bus_dmamap_unload(sc->bnx_dmatag, 2165 sc->tx_bd_chain_map[i]); 2166 bus_dmamem_unmap(sc->bnx_dmatag, 2167 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2168 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2169 sc->tx_bd_chain_rseg[i]); 2170 bus_dmamap_destroy(sc->bnx_dmatag, 2171 sc->tx_bd_chain_map[i]); 2172 sc->tx_bd_chain[i] = NULL; 2173 sc->tx_bd_chain_map[i] = NULL; 2174 } 2175 } 2176 2177 /* Destroy the TX dmamaps. */ 2178 /* This isn't necessary since we dont allocate them up front */ 2179 2180 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2181 for (i = 0; i < RX_PAGES; i++ ) { 2182 if (sc->rx_bd_chain[i] != NULL && 2183 sc->rx_bd_chain_map[i] != NULL) { 2184 bus_dmamap_unload(sc->bnx_dmatag, 2185 sc->rx_bd_chain_map[i]); 2186 bus_dmamem_unmap(sc->bnx_dmatag, 2187 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2188 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2189 sc->rx_bd_chain_rseg[i]); 2190 2191 bus_dmamap_destroy(sc->bnx_dmatag, 2192 sc->rx_bd_chain_map[i]); 2193 sc->rx_bd_chain[i] = NULL; 2194 sc->rx_bd_chain_map[i] = NULL; 2195 } 2196 } 2197 2198 /* Unload and destroy the RX mbuf maps. */ 2199 for (i = 0; i < TOTAL_RX_BD; i++) { 2200 if (sc->rx_mbuf_map[i] != NULL) { 2201 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2202 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2203 } 2204 } 2205 2206 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2207 } 2208 2209 /****************************************************************************/ 2210 /* Allocate any DMA memory needed by the driver. */ 2211 /* */ 2212 /* Allocates DMA memory needed for the various global structures needed by */ 2213 /* hardware. */ 2214 /* */ 2215 /* Returns: */ 2216 /* 0 for success, positive value for failure. */ 2217 /****************************************************************************/ 2218 int 2219 bnx_dma_alloc(struct bnx_softc *sc) 2220 { 2221 int i, rc = 0; 2222 2223 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2224 2225 /* 2226 * Allocate DMA memory for the status block, map the memory into DMA 2227 * space, and fetch the physical address of the block. 2228 */ 2229 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2230 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2231 aprint_error_dev(sc->bnx_dev, 2232 "Could not create status block DMA map!\n"); 2233 rc = ENOMEM; 2234 goto bnx_dma_alloc_exit; 2235 } 2236 2237 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2238 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2239 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2240 aprint_error_dev(sc->bnx_dev, 2241 "Could not allocate status block DMA memory!\n"); 2242 rc = ENOMEM; 2243 goto bnx_dma_alloc_exit; 2244 } 2245 2246 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2247 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2248 aprint_error_dev(sc->bnx_dev, 2249 "Could not map status block DMA memory!\n"); 2250 rc = ENOMEM; 2251 goto bnx_dma_alloc_exit; 2252 } 2253 2254 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2255 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2256 aprint_error_dev(sc->bnx_dev, 2257 "Could not load status block DMA memory!\n"); 2258 rc = ENOMEM; 2259 goto bnx_dma_alloc_exit; 2260 } 2261 2262 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2263 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2264 2265 /* DRC - Fix for 64 bit addresses. */ 2266 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2267 (uint32_t) sc->status_block_paddr); 2268 2269 /* BCM5709 uses host memory as cache for context memory. */ 2270 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2271 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2272 if (sc->ctx_pages == 0) 2273 sc->ctx_pages = 1; 2274 if (sc->ctx_pages > 4) /* XXX */ 2275 sc->ctx_pages = 4; 2276 2277 DBRUNIF((sc->ctx_pages > 512), 2278 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2279 __FILE__, __LINE__, sc->ctx_pages)); 2280 2281 2282 for (i = 0; i < sc->ctx_pages; i++) { 2283 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2284 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2285 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2286 &sc->ctx_map[i]) != 0) { 2287 rc = ENOMEM; 2288 goto bnx_dma_alloc_exit; 2289 } 2290 2291 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2292 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2293 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2294 rc = ENOMEM; 2295 goto bnx_dma_alloc_exit; 2296 } 2297 2298 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2299 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2300 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2301 rc = ENOMEM; 2302 goto bnx_dma_alloc_exit; 2303 } 2304 2305 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2306 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2307 BUS_DMA_NOWAIT) != 0) { 2308 rc = ENOMEM; 2309 goto bnx_dma_alloc_exit; 2310 } 2311 2312 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2313 } 2314 } 2315 2316 /* 2317 * Allocate DMA memory for the statistics block, map the memory into 2318 * DMA space, and fetch the physical address of the block. 2319 */ 2320 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2321 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2322 aprint_error_dev(sc->bnx_dev, 2323 "Could not create stats block DMA map!\n"); 2324 rc = ENOMEM; 2325 goto bnx_dma_alloc_exit; 2326 } 2327 2328 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2329 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2330 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2331 aprint_error_dev(sc->bnx_dev, 2332 "Could not allocate stats block DMA memory!\n"); 2333 rc = ENOMEM; 2334 goto bnx_dma_alloc_exit; 2335 } 2336 2337 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2338 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2339 aprint_error_dev(sc->bnx_dev, 2340 "Could not map stats block DMA memory!\n"); 2341 rc = ENOMEM; 2342 goto bnx_dma_alloc_exit; 2343 } 2344 2345 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2346 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2347 aprint_error_dev(sc->bnx_dev, 2348 "Could not load status block DMA memory!\n"); 2349 rc = ENOMEM; 2350 goto bnx_dma_alloc_exit; 2351 } 2352 2353 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2354 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2355 2356 /* DRC - Fix for 64 bit address. */ 2357 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2358 (uint32_t) sc->stats_block_paddr); 2359 2360 /* 2361 * Allocate DMA memory for the TX buffer descriptor chain, 2362 * and fetch the physical address of the block. 2363 */ 2364 for (i = 0; i < TX_PAGES; i++) { 2365 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2366 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2367 &sc->tx_bd_chain_map[i])) { 2368 aprint_error_dev(sc->bnx_dev, 2369 "Could not create Tx desc %d DMA map!\n", i); 2370 rc = ENOMEM; 2371 goto bnx_dma_alloc_exit; 2372 } 2373 2374 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2375 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2376 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2377 aprint_error_dev(sc->bnx_dev, 2378 "Could not allocate TX desc %d DMA memory!\n", 2379 i); 2380 rc = ENOMEM; 2381 goto bnx_dma_alloc_exit; 2382 } 2383 2384 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2385 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2386 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2387 aprint_error_dev(sc->bnx_dev, 2388 "Could not map TX desc %d DMA memory!\n", i); 2389 rc = ENOMEM; 2390 goto bnx_dma_alloc_exit; 2391 } 2392 2393 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2394 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2395 BUS_DMA_NOWAIT)) { 2396 aprint_error_dev(sc->bnx_dev, 2397 "Could not load TX desc %d DMA memory!\n", i); 2398 rc = ENOMEM; 2399 goto bnx_dma_alloc_exit; 2400 } 2401 2402 sc->tx_bd_chain_paddr[i] = 2403 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2404 2405 /* DRC - Fix for 64 bit systems. */ 2406 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2407 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2408 } 2409 2410 /* 2411 * Create lists to hold TX mbufs. 2412 */ 2413 TAILQ_INIT(&sc->tx_free_pkts); 2414 TAILQ_INIT(&sc->tx_used_pkts); 2415 sc->tx_pkt_count = 0; 2416 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2417 2418 /* 2419 * Allocate DMA memory for the Rx buffer descriptor chain, 2420 * and fetch the physical address of the block. 2421 */ 2422 for (i = 0; i < RX_PAGES; i++) { 2423 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2424 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2425 &sc->rx_bd_chain_map[i])) { 2426 aprint_error_dev(sc->bnx_dev, 2427 "Could not create Rx desc %d DMA map!\n", i); 2428 rc = ENOMEM; 2429 goto bnx_dma_alloc_exit; 2430 } 2431 2432 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2433 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2434 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2435 aprint_error_dev(sc->bnx_dev, 2436 "Could not allocate Rx desc %d DMA memory!\n", i); 2437 rc = ENOMEM; 2438 goto bnx_dma_alloc_exit; 2439 } 2440 2441 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2442 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2443 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2444 aprint_error_dev(sc->bnx_dev, 2445 "Could not map Rx desc %d DMA memory!\n", i); 2446 rc = ENOMEM; 2447 goto bnx_dma_alloc_exit; 2448 } 2449 2450 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2451 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2452 BUS_DMA_NOWAIT)) { 2453 aprint_error_dev(sc->bnx_dev, 2454 "Could not load Rx desc %d DMA memory!\n", i); 2455 rc = ENOMEM; 2456 goto bnx_dma_alloc_exit; 2457 } 2458 2459 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2460 sc->rx_bd_chain_paddr[i] = 2461 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2462 2463 /* DRC - Fix for 64 bit systems. */ 2464 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2465 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2466 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2467 0, BNX_RX_CHAIN_PAGE_SZ, 2468 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2469 } 2470 2471 /* 2472 * Create DMA maps for the Rx buffer mbufs. 2473 */ 2474 for (i = 0; i < TOTAL_RX_BD; i++) { 2475 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2476 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2477 &sc->rx_mbuf_map[i])) { 2478 aprint_error_dev(sc->bnx_dev, 2479 "Could not create Rx mbuf %d DMA map!\n", i); 2480 rc = ENOMEM; 2481 goto bnx_dma_alloc_exit; 2482 } 2483 } 2484 2485 bnx_dma_alloc_exit: 2486 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2487 2488 return rc; 2489 } 2490 2491 /****************************************************************************/ 2492 /* Release all resources used by the driver. */ 2493 /* */ 2494 /* Releases all resources acquired by the driver including interrupts, */ 2495 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2496 /* */ 2497 /* Returns: */ 2498 /* Nothing. */ 2499 /****************************************************************************/ 2500 void 2501 bnx_release_resources(struct bnx_softc *sc) 2502 { 2503 struct pci_attach_args *pa = &(sc->bnx_pa); 2504 2505 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2506 2507 bnx_dma_free(sc); 2508 2509 if (sc->bnx_intrhand != NULL) 2510 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2511 2512 if (sc->bnx_size) 2513 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2514 2515 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2516 } 2517 2518 /****************************************************************************/ 2519 /* Firmware synchronization. */ 2520 /* */ 2521 /* Before performing certain events such as a chip reset, synchronize with */ 2522 /* the firmware first. */ 2523 /* */ 2524 /* Returns: */ 2525 /* 0 for success, positive value for failure. */ 2526 /****************************************************************************/ 2527 int 2528 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2529 { 2530 int i, rc = 0; 2531 uint32_t val; 2532 2533 /* Don't waste any time if we've timed out before. */ 2534 if (sc->bnx_fw_timed_out) { 2535 rc = EBUSY; 2536 goto bnx_fw_sync_exit; 2537 } 2538 2539 /* Increment the message sequence number. */ 2540 sc->bnx_fw_wr_seq++; 2541 msg_data |= sc->bnx_fw_wr_seq; 2542 2543 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2544 msg_data); 2545 2546 /* Send the message to the bootcode driver mailbox. */ 2547 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2548 2549 /* Wait for the bootcode to acknowledge the message. */ 2550 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2551 /* Check for a response in the bootcode firmware mailbox. */ 2552 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2553 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2554 break; 2555 DELAY(1000); 2556 } 2557 2558 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2559 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2560 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2561 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2562 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2563 2564 msg_data &= ~BNX_DRV_MSG_CODE; 2565 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2566 2567 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2568 2569 sc->bnx_fw_timed_out = 1; 2570 rc = EBUSY; 2571 } 2572 2573 bnx_fw_sync_exit: 2574 return rc; 2575 } 2576 2577 /****************************************************************************/ 2578 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2579 /* */ 2580 /* Returns: */ 2581 /* Nothing. */ 2582 /****************************************************************************/ 2583 void 2584 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2585 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2586 { 2587 int i; 2588 uint32_t val; 2589 2590 /* Set the page size used by RV2P. */ 2591 if (rv2p_proc == RV2P_PROC2) { 2592 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2593 USABLE_RX_BD_PER_PAGE); 2594 } 2595 2596 for (i = 0; i < rv2p_code_len; i += 8) { 2597 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2598 rv2p_code++; 2599 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2600 rv2p_code++; 2601 2602 if (rv2p_proc == RV2P_PROC1) { 2603 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2604 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2605 } else { 2606 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2607 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2608 } 2609 } 2610 2611 /* Reset the processor, un-stall is done later. */ 2612 if (rv2p_proc == RV2P_PROC1) 2613 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2614 else 2615 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2616 } 2617 2618 /****************************************************************************/ 2619 /* Load RISC processor firmware. */ 2620 /* */ 2621 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2622 /* associated with a particular processor. */ 2623 /* */ 2624 /* Returns: */ 2625 /* Nothing. */ 2626 /****************************************************************************/ 2627 void 2628 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2629 struct fw_info *fw) 2630 { 2631 uint32_t offset; 2632 uint32_t val; 2633 2634 /* Halt the CPU. */ 2635 val = REG_RD_IND(sc, cpu_reg->mode); 2636 val |= cpu_reg->mode_value_halt; 2637 REG_WR_IND(sc, cpu_reg->mode, val); 2638 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2639 2640 /* Load the Text area. */ 2641 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2642 if (fw->text) { 2643 int j; 2644 2645 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2646 REG_WR_IND(sc, offset, fw->text[j]); 2647 } 2648 2649 /* Load the Data area. */ 2650 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2651 if (fw->data) { 2652 int j; 2653 2654 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2655 REG_WR_IND(sc, offset, fw->data[j]); 2656 } 2657 2658 /* Load the SBSS area. */ 2659 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2660 if (fw->sbss) { 2661 int j; 2662 2663 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2664 REG_WR_IND(sc, offset, fw->sbss[j]); 2665 } 2666 2667 /* Load the BSS area. */ 2668 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2669 if (fw->bss) { 2670 int j; 2671 2672 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2673 REG_WR_IND(sc, offset, fw->bss[j]); 2674 } 2675 2676 /* Load the Read-Only area. */ 2677 offset = cpu_reg->spad_base + 2678 (fw->rodata_addr - cpu_reg->mips_view_base); 2679 if (fw->rodata) { 2680 int j; 2681 2682 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2683 REG_WR_IND(sc, offset, fw->rodata[j]); 2684 } 2685 2686 /* Clear the pre-fetch instruction. */ 2687 REG_WR_IND(sc, cpu_reg->inst, 0); 2688 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2689 2690 /* Start the CPU. */ 2691 val = REG_RD_IND(sc, cpu_reg->mode); 2692 val &= ~cpu_reg->mode_value_halt; 2693 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2694 REG_WR_IND(sc, cpu_reg->mode, val); 2695 } 2696 2697 /****************************************************************************/ 2698 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2699 /* */ 2700 /* Loads the firmware for each CPU and starts the CPU. */ 2701 /* */ 2702 /* Returns: */ 2703 /* Nothing. */ 2704 /****************************************************************************/ 2705 void 2706 bnx_init_cpus(struct bnx_softc *sc) 2707 { 2708 struct cpu_reg cpu_reg; 2709 struct fw_info fw; 2710 2711 switch(BNX_CHIP_NUM(sc)) { 2712 case BNX_CHIP_NUM_5709: 2713 /* Initialize the RV2P processor. */ 2714 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2715 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2716 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2717 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2718 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2719 } else { 2720 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2721 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2722 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2723 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2724 } 2725 2726 /* Initialize the RX Processor. */ 2727 cpu_reg.mode = BNX_RXP_CPU_MODE; 2728 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2729 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2730 cpu_reg.state = BNX_RXP_CPU_STATE; 2731 cpu_reg.state_value_clear = 0xffffff; 2732 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2733 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2734 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2735 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2736 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2737 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2738 cpu_reg.mips_view_base = 0x8000000; 2739 2740 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2741 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2742 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2743 fw.start_addr = bnx_RXP_b09FwStartAddr; 2744 2745 fw.text_addr = bnx_RXP_b09FwTextAddr; 2746 fw.text_len = bnx_RXP_b09FwTextLen; 2747 fw.text_index = 0; 2748 fw.text = bnx_RXP_b09FwText; 2749 2750 fw.data_addr = bnx_RXP_b09FwDataAddr; 2751 fw.data_len = bnx_RXP_b09FwDataLen; 2752 fw.data_index = 0; 2753 fw.data = bnx_RXP_b09FwData; 2754 2755 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2756 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2757 fw.sbss_index = 0; 2758 fw.sbss = bnx_RXP_b09FwSbss; 2759 2760 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2761 fw.bss_len = bnx_RXP_b09FwBssLen; 2762 fw.bss_index = 0; 2763 fw.bss = bnx_RXP_b09FwBss; 2764 2765 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2766 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2767 fw.rodata_index = 0; 2768 fw.rodata = bnx_RXP_b09FwRodata; 2769 2770 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2771 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2772 2773 /* Initialize the TX Processor. */ 2774 cpu_reg.mode = BNX_TXP_CPU_MODE; 2775 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2776 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2777 cpu_reg.state = BNX_TXP_CPU_STATE; 2778 cpu_reg.state_value_clear = 0xffffff; 2779 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2780 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2781 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2782 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2783 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2784 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2785 cpu_reg.mips_view_base = 0x8000000; 2786 2787 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2788 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2789 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2790 fw.start_addr = bnx_TXP_b09FwStartAddr; 2791 2792 fw.text_addr = bnx_TXP_b09FwTextAddr; 2793 fw.text_len = bnx_TXP_b09FwTextLen; 2794 fw.text_index = 0; 2795 fw.text = bnx_TXP_b09FwText; 2796 2797 fw.data_addr = bnx_TXP_b09FwDataAddr; 2798 fw.data_len = bnx_TXP_b09FwDataLen; 2799 fw.data_index = 0; 2800 fw.data = bnx_TXP_b09FwData; 2801 2802 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2803 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2804 fw.sbss_index = 0; 2805 fw.sbss = bnx_TXP_b09FwSbss; 2806 2807 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2808 fw.bss_len = bnx_TXP_b09FwBssLen; 2809 fw.bss_index = 0; 2810 fw.bss = bnx_TXP_b09FwBss; 2811 2812 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2813 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2814 fw.rodata_index = 0; 2815 fw.rodata = bnx_TXP_b09FwRodata; 2816 2817 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2818 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2819 2820 /* Initialize the TX Patch-up Processor. */ 2821 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2822 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2823 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2824 cpu_reg.state = BNX_TPAT_CPU_STATE; 2825 cpu_reg.state_value_clear = 0xffffff; 2826 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2827 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2828 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2829 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2830 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2831 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2832 cpu_reg.mips_view_base = 0x8000000; 2833 2834 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2835 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2836 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2837 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2838 2839 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2840 fw.text_len = bnx_TPAT_b09FwTextLen; 2841 fw.text_index = 0; 2842 fw.text = bnx_TPAT_b09FwText; 2843 2844 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2845 fw.data_len = bnx_TPAT_b09FwDataLen; 2846 fw.data_index = 0; 2847 fw.data = bnx_TPAT_b09FwData; 2848 2849 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2850 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2851 fw.sbss_index = 0; 2852 fw.sbss = bnx_TPAT_b09FwSbss; 2853 2854 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2855 fw.bss_len = bnx_TPAT_b09FwBssLen; 2856 fw.bss_index = 0; 2857 fw.bss = bnx_TPAT_b09FwBss; 2858 2859 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2860 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2861 fw.rodata_index = 0; 2862 fw.rodata = bnx_TPAT_b09FwRodata; 2863 2864 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2865 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2866 2867 /* Initialize the Completion Processor. */ 2868 cpu_reg.mode = BNX_COM_CPU_MODE; 2869 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2870 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2871 cpu_reg.state = BNX_COM_CPU_STATE; 2872 cpu_reg.state_value_clear = 0xffffff; 2873 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2874 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2875 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2876 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2877 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2878 cpu_reg.spad_base = BNX_COM_SCRATCH; 2879 cpu_reg.mips_view_base = 0x8000000; 2880 2881 fw.ver_major = bnx_COM_b09FwReleaseMajor; 2882 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 2883 fw.ver_fix = bnx_COM_b09FwReleaseFix; 2884 fw.start_addr = bnx_COM_b09FwStartAddr; 2885 2886 fw.text_addr = bnx_COM_b09FwTextAddr; 2887 fw.text_len = bnx_COM_b09FwTextLen; 2888 fw.text_index = 0; 2889 fw.text = bnx_COM_b09FwText; 2890 2891 fw.data_addr = bnx_COM_b09FwDataAddr; 2892 fw.data_len = bnx_COM_b09FwDataLen; 2893 fw.data_index = 0; 2894 fw.data = bnx_COM_b09FwData; 2895 2896 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 2897 fw.sbss_len = bnx_COM_b09FwSbssLen; 2898 fw.sbss_index = 0; 2899 fw.sbss = bnx_COM_b09FwSbss; 2900 2901 fw.bss_addr = bnx_COM_b09FwBssAddr; 2902 fw.bss_len = bnx_COM_b09FwBssLen; 2903 fw.bss_index = 0; 2904 fw.bss = bnx_COM_b09FwBss; 2905 2906 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 2907 fw.rodata_len = bnx_COM_b09FwRodataLen; 2908 fw.rodata_index = 0; 2909 fw.rodata = bnx_COM_b09FwRodata; 2910 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 2911 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2912 break; 2913 default: 2914 /* Initialize the RV2P processor. */ 2915 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 2916 RV2P_PROC1); 2917 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 2918 RV2P_PROC2); 2919 2920 /* Initialize the RX Processor. */ 2921 cpu_reg.mode = BNX_RXP_CPU_MODE; 2922 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2923 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2924 cpu_reg.state = BNX_RXP_CPU_STATE; 2925 cpu_reg.state_value_clear = 0xffffff; 2926 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2927 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2928 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2929 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2930 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2931 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2932 cpu_reg.mips_view_base = 0x8000000; 2933 2934 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 2935 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 2936 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 2937 fw.start_addr = bnx_RXP_b06FwStartAddr; 2938 2939 fw.text_addr = bnx_RXP_b06FwTextAddr; 2940 fw.text_len = bnx_RXP_b06FwTextLen; 2941 fw.text_index = 0; 2942 fw.text = bnx_RXP_b06FwText; 2943 2944 fw.data_addr = bnx_RXP_b06FwDataAddr; 2945 fw.data_len = bnx_RXP_b06FwDataLen; 2946 fw.data_index = 0; 2947 fw.data = bnx_RXP_b06FwData; 2948 2949 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 2950 fw.sbss_len = bnx_RXP_b06FwSbssLen; 2951 fw.sbss_index = 0; 2952 fw.sbss = bnx_RXP_b06FwSbss; 2953 2954 fw.bss_addr = bnx_RXP_b06FwBssAddr; 2955 fw.bss_len = bnx_RXP_b06FwBssLen; 2956 fw.bss_index = 0; 2957 fw.bss = bnx_RXP_b06FwBss; 2958 2959 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 2960 fw.rodata_len = bnx_RXP_b06FwRodataLen; 2961 fw.rodata_index = 0; 2962 fw.rodata = bnx_RXP_b06FwRodata; 2963 2964 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2965 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2966 2967 /* Initialize the TX Processor. */ 2968 cpu_reg.mode = BNX_TXP_CPU_MODE; 2969 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2970 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2971 cpu_reg.state = BNX_TXP_CPU_STATE; 2972 cpu_reg.state_value_clear = 0xffffff; 2973 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2974 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2975 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2976 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2977 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2978 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2979 cpu_reg.mips_view_base = 0x8000000; 2980 2981 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 2982 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 2983 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 2984 fw.start_addr = bnx_TXP_b06FwStartAddr; 2985 2986 fw.text_addr = bnx_TXP_b06FwTextAddr; 2987 fw.text_len = bnx_TXP_b06FwTextLen; 2988 fw.text_index = 0; 2989 fw.text = bnx_TXP_b06FwText; 2990 2991 fw.data_addr = bnx_TXP_b06FwDataAddr; 2992 fw.data_len = bnx_TXP_b06FwDataLen; 2993 fw.data_index = 0; 2994 fw.data = bnx_TXP_b06FwData; 2995 2996 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 2997 fw.sbss_len = bnx_TXP_b06FwSbssLen; 2998 fw.sbss_index = 0; 2999 fw.sbss = bnx_TXP_b06FwSbss; 3000 3001 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3002 fw.bss_len = bnx_TXP_b06FwBssLen; 3003 fw.bss_index = 0; 3004 fw.bss = bnx_TXP_b06FwBss; 3005 3006 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3007 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3008 fw.rodata_index = 0; 3009 fw.rodata = bnx_TXP_b06FwRodata; 3010 3011 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3012 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3013 3014 /* Initialize the TX Patch-up Processor. */ 3015 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3016 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3017 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3018 cpu_reg.state = BNX_TPAT_CPU_STATE; 3019 cpu_reg.state_value_clear = 0xffffff; 3020 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3021 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3022 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3023 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3024 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3025 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3026 cpu_reg.mips_view_base = 0x8000000; 3027 3028 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3029 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3030 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3031 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3032 3033 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3034 fw.text_len = bnx_TPAT_b06FwTextLen; 3035 fw.text_index = 0; 3036 fw.text = bnx_TPAT_b06FwText; 3037 3038 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3039 fw.data_len = bnx_TPAT_b06FwDataLen; 3040 fw.data_index = 0; 3041 fw.data = bnx_TPAT_b06FwData; 3042 3043 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3044 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3045 fw.sbss_index = 0; 3046 fw.sbss = bnx_TPAT_b06FwSbss; 3047 3048 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3049 fw.bss_len = bnx_TPAT_b06FwBssLen; 3050 fw.bss_index = 0; 3051 fw.bss = bnx_TPAT_b06FwBss; 3052 3053 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3054 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3055 fw.rodata_index = 0; 3056 fw.rodata = bnx_TPAT_b06FwRodata; 3057 3058 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3059 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3060 3061 /* Initialize the Completion Processor. */ 3062 cpu_reg.mode = BNX_COM_CPU_MODE; 3063 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3064 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3065 cpu_reg.state = BNX_COM_CPU_STATE; 3066 cpu_reg.state_value_clear = 0xffffff; 3067 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3068 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3069 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3070 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3071 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3072 cpu_reg.spad_base = BNX_COM_SCRATCH; 3073 cpu_reg.mips_view_base = 0x8000000; 3074 3075 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3076 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3077 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3078 fw.start_addr = bnx_COM_b06FwStartAddr; 3079 3080 fw.text_addr = bnx_COM_b06FwTextAddr; 3081 fw.text_len = bnx_COM_b06FwTextLen; 3082 fw.text_index = 0; 3083 fw.text = bnx_COM_b06FwText; 3084 3085 fw.data_addr = bnx_COM_b06FwDataAddr; 3086 fw.data_len = bnx_COM_b06FwDataLen; 3087 fw.data_index = 0; 3088 fw.data = bnx_COM_b06FwData; 3089 3090 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3091 fw.sbss_len = bnx_COM_b06FwSbssLen; 3092 fw.sbss_index = 0; 3093 fw.sbss = bnx_COM_b06FwSbss; 3094 3095 fw.bss_addr = bnx_COM_b06FwBssAddr; 3096 fw.bss_len = bnx_COM_b06FwBssLen; 3097 fw.bss_index = 0; 3098 fw.bss = bnx_COM_b06FwBss; 3099 3100 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3101 fw.rodata_len = bnx_COM_b06FwRodataLen; 3102 fw.rodata_index = 0; 3103 fw.rodata = bnx_COM_b06FwRodata; 3104 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3105 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3106 break; 3107 } 3108 } 3109 3110 /****************************************************************************/ 3111 /* Initialize context memory. */ 3112 /* */ 3113 /* Clears the memory associated with each Context ID (CID). */ 3114 /* */ 3115 /* Returns: */ 3116 /* Nothing. */ 3117 /****************************************************************************/ 3118 void 3119 bnx_init_context(struct bnx_softc *sc) 3120 { 3121 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3122 /* DRC: Replace this constant value with a #define. */ 3123 int i, retry_cnt = 10; 3124 uint32_t val; 3125 3126 /* 3127 * BCM5709 context memory may be cached 3128 * in host memory so prepare the host memory 3129 * for access. 3130 */ 3131 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3132 | (1 << 12); 3133 val |= (BCM_PAGE_BITS - 8) << 16; 3134 REG_WR(sc, BNX_CTX_COMMAND, val); 3135 3136 /* Wait for mem init command to complete. */ 3137 for (i = 0; i < retry_cnt; i++) { 3138 val = REG_RD(sc, BNX_CTX_COMMAND); 3139 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3140 break; 3141 DELAY(2); 3142 } 3143 3144 /* ToDo: Consider returning an error here. */ 3145 3146 for (i = 0; i < sc->ctx_pages; i++) { 3147 int j; 3148 3149 /* Set the physaddr of the context memory cache. */ 3150 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3151 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3152 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3153 val = (uint32_t) 3154 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3155 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3156 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3157 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3158 3159 /* Verify that the context memory write was successful. */ 3160 for (j = 0; j < retry_cnt; j++) { 3161 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3162 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3163 break; 3164 DELAY(5); 3165 } 3166 3167 /* ToDo: Consider returning an error here. */ 3168 } 3169 } else { 3170 uint32_t vcid_addr, offset; 3171 3172 /* 3173 * For the 5706/5708, context memory is local to 3174 * the controller, so initialize the controller 3175 * context memory. 3176 */ 3177 3178 vcid_addr = GET_CID_ADDR(96); 3179 while (vcid_addr) { 3180 3181 vcid_addr -= BNX_PHY_CTX_SIZE; 3182 3183 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3184 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3185 3186 for(offset = 0; offset < BNX_PHY_CTX_SIZE; offset += 4) { 3187 CTX_WR(sc, 0x00, offset, 0); 3188 } 3189 3190 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3191 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3192 } 3193 } 3194 } 3195 3196 /****************************************************************************/ 3197 /* Fetch the permanent MAC address of the controller. */ 3198 /* */ 3199 /* Returns: */ 3200 /* Nothing. */ 3201 /****************************************************************************/ 3202 void 3203 bnx_get_mac_addr(struct bnx_softc *sc) 3204 { 3205 uint32_t mac_lo = 0, mac_hi = 0; 3206 3207 /* 3208 * The NetXtreme II bootcode populates various NIC 3209 * power-on and runtime configuration items in a 3210 * shared memory area. The factory configured MAC 3211 * address is available from both NVRAM and the 3212 * shared memory area so we'll read the value from 3213 * shared memory for speed. 3214 */ 3215 3216 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3217 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3218 3219 if ((mac_lo == 0) && (mac_hi == 0)) { 3220 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3221 __FILE__, __LINE__); 3222 } else { 3223 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3224 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3225 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3226 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3227 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3228 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3229 } 3230 3231 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3232 "%s\n", ether_sprintf(sc->eaddr)); 3233 } 3234 3235 /****************************************************************************/ 3236 /* Program the MAC address. */ 3237 /* */ 3238 /* Returns: */ 3239 /* Nothing. */ 3240 /****************************************************************************/ 3241 void 3242 bnx_set_mac_addr(struct bnx_softc *sc) 3243 { 3244 uint32_t val; 3245 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3246 3247 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3248 "%s\n", ether_sprintf(sc->eaddr)); 3249 3250 val = (mac_addr[0] << 8) | mac_addr[1]; 3251 3252 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3253 3254 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3255 (mac_addr[4] << 8) | mac_addr[5]; 3256 3257 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3258 } 3259 3260 /****************************************************************************/ 3261 /* Stop the controller. */ 3262 /* */ 3263 /* Returns: */ 3264 /* Nothing. */ 3265 /****************************************************************************/ 3266 void 3267 bnx_stop(struct ifnet *ifp, int disable) 3268 { 3269 struct bnx_softc *sc = ifp->if_softc; 3270 3271 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3272 3273 if ((ifp->if_flags & IFF_RUNNING) == 0) 3274 return; 3275 3276 callout_stop(&sc->bnx_timeout); 3277 3278 mii_down(&sc->bnx_mii); 3279 3280 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3281 3282 /* Disable the transmit/receive blocks. */ 3283 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3284 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3285 DELAY(20); 3286 3287 bnx_disable_intr(sc); 3288 3289 /* Tell firmware that the driver is going away. */ 3290 if (disable) 3291 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3292 else 3293 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3294 3295 /* Free RX buffers. */ 3296 bnx_free_rx_chain(sc); 3297 3298 /* Free TX buffers. */ 3299 bnx_free_tx_chain(sc); 3300 3301 ifp->if_timer = 0; 3302 3303 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3304 3305 } 3306 3307 int 3308 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3309 { 3310 struct pci_attach_args *pa = &(sc->bnx_pa); 3311 uint32_t val; 3312 int i, rc = 0; 3313 3314 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3315 3316 /* Wait for pending PCI transactions to complete. */ 3317 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3318 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3319 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3320 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3321 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3322 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3323 DELAY(5); 3324 3325 /* Disable DMA */ 3326 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3327 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3328 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3329 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3330 } 3331 3332 /* Assume bootcode is running. */ 3333 sc->bnx_fw_timed_out = 0; 3334 3335 /* Give the firmware a chance to prepare for the reset. */ 3336 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3337 if (rc) 3338 goto bnx_reset_exit; 3339 3340 /* Set a firmware reminder that this is a soft reset. */ 3341 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3342 BNX_DRV_RESET_SIGNATURE_MAGIC); 3343 3344 /* Dummy read to force the chip to complete all current transactions. */ 3345 val = REG_RD(sc, BNX_MISC_ID); 3346 3347 /* Chip reset. */ 3348 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3349 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3350 REG_RD(sc, BNX_MISC_COMMAND); 3351 DELAY(5); 3352 3353 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3354 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3355 3356 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3357 val); 3358 } else { 3359 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3360 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3361 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3362 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3363 3364 /* Allow up to 30us for reset to complete. */ 3365 for (i = 0; i < 10; i++) { 3366 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3367 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3368 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3369 break; 3370 } 3371 DELAY(10); 3372 } 3373 3374 /* Check that reset completed successfully. */ 3375 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3376 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3377 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3378 __FILE__, __LINE__); 3379 rc = EBUSY; 3380 goto bnx_reset_exit; 3381 } 3382 } 3383 3384 /* Make sure byte swapping is properly configured. */ 3385 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3386 if (val != 0x01020304) { 3387 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3388 __FILE__, __LINE__); 3389 rc = ENODEV; 3390 goto bnx_reset_exit; 3391 } 3392 3393 /* Just completed a reset, assume that firmware is running again. */ 3394 sc->bnx_fw_timed_out = 0; 3395 3396 /* Wait for the firmware to finish its initialization. */ 3397 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3398 if (rc) 3399 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3400 "initialization!\n", __FILE__, __LINE__); 3401 3402 bnx_reset_exit: 3403 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3404 3405 return rc; 3406 } 3407 3408 int 3409 bnx_chipinit(struct bnx_softc *sc) 3410 { 3411 struct pci_attach_args *pa = &(sc->bnx_pa); 3412 uint32_t val; 3413 int rc = 0; 3414 3415 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3416 3417 /* Make sure the interrupt is not active. */ 3418 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3419 3420 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3421 /* channels and PCI clock compensation delay. */ 3422 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3423 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3424 #if BYTE_ORDER == BIG_ENDIAN 3425 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3426 #endif 3427 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3428 DMA_READ_CHANS << 12 | 3429 DMA_WRITE_CHANS << 16; 3430 3431 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3432 3433 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3434 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3435 3436 /* 3437 * This setting resolves a problem observed on certain Intel PCI 3438 * chipsets that cannot handle multiple outstanding DMA operations. 3439 * See errata E9_5706A1_65. 3440 */ 3441 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3442 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3443 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3444 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3445 3446 REG_WR(sc, BNX_DMA_CONFIG, val); 3447 3448 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3449 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3450 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3451 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3452 val & ~0x20000); 3453 } 3454 3455 /* Enable the RX_V2P and Context state machines before access. */ 3456 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3457 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3458 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3459 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3460 3461 /* Initialize context mapping and zero out the quick contexts. */ 3462 bnx_init_context(sc); 3463 3464 /* Initialize the on-boards CPUs */ 3465 bnx_init_cpus(sc); 3466 3467 /* Prepare NVRAM for access. */ 3468 if (bnx_init_nvram(sc)) { 3469 rc = ENODEV; 3470 goto bnx_chipinit_exit; 3471 } 3472 3473 /* Set the kernel bypass block size */ 3474 val = REG_RD(sc, BNX_MQ_CONFIG); 3475 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3476 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3477 3478 /* Enable bins used on the 5709. */ 3479 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3480 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3481 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3482 val |= BNX_MQ_CONFIG_HALT_DIS; 3483 } 3484 3485 REG_WR(sc, BNX_MQ_CONFIG, val); 3486 3487 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3488 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3489 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3490 3491 val = (BCM_PAGE_BITS - 8) << 24; 3492 REG_WR(sc, BNX_RV2P_CONFIG, val); 3493 3494 /* Configure page size. */ 3495 val = REG_RD(sc, BNX_TBDR_CONFIG); 3496 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3497 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3498 REG_WR(sc, BNX_TBDR_CONFIG, val); 3499 3500 #if 0 3501 /* Set the perfect match control register to default. */ 3502 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3503 #endif 3504 3505 bnx_chipinit_exit: 3506 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3507 3508 return rc; 3509 } 3510 3511 /****************************************************************************/ 3512 /* Initialize the controller in preparation to send/receive traffic. */ 3513 /* */ 3514 /* Returns: */ 3515 /* 0 for success, positive value for failure. */ 3516 /****************************************************************************/ 3517 int 3518 bnx_blockinit(struct bnx_softc *sc) 3519 { 3520 uint32_t reg, val; 3521 int rc = 0; 3522 3523 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3524 3525 /* Load the hardware default MAC address. */ 3526 bnx_set_mac_addr(sc); 3527 3528 /* Set the Ethernet backoff seed value */ 3529 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3530 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3531 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3532 3533 sc->last_status_idx = 0; 3534 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3535 3536 /* Set up link change interrupt generation. */ 3537 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3538 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3539 3540 /* Program the physical address of the status block. */ 3541 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3542 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3543 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3544 3545 /* Program the physical address of the statistics block. */ 3546 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3547 (uint32_t)(sc->stats_block_paddr)); 3548 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3549 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3550 3551 /* Program various host coalescing parameters. */ 3552 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3553 << 16) | sc->bnx_tx_quick_cons_trip); 3554 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3555 << 16) | sc->bnx_rx_quick_cons_trip); 3556 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3557 sc->bnx_comp_prod_trip); 3558 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3559 sc->bnx_tx_ticks); 3560 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3561 sc->bnx_rx_ticks); 3562 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3563 sc->bnx_com_ticks); 3564 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3565 sc->bnx_cmd_ticks); 3566 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3567 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3568 REG_WR(sc, BNX_HC_CONFIG, 3569 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3570 BNX_HC_CONFIG_COLLECT_STATS)); 3571 3572 /* Clear the internal statistics counters. */ 3573 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3574 3575 /* Verify that bootcode is running. */ 3576 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3577 3578 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3579 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3580 __FILE__, __LINE__); reg = 0); 3581 3582 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3583 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3584 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3585 "Expected: 08%08X\n", __FILE__, __LINE__, 3586 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3587 BNX_DEV_INFO_SIGNATURE_MAGIC); 3588 rc = ENODEV; 3589 goto bnx_blockinit_exit; 3590 } 3591 3592 /* Check if any management firmware is running. */ 3593 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3594 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3595 BNX_PORT_FEATURE_IMD_ENABLED)) { 3596 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3597 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3598 } 3599 3600 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3601 BNX_DEV_INFO_BC_REV); 3602 3603 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3604 3605 /* Enable DMA */ 3606 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3607 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3608 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3609 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3610 } 3611 3612 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3613 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3614 3615 /* Enable link state change interrupt generation. */ 3616 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3617 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3618 BNX_MISC_ENABLE_DEFAULT_XI); 3619 } else 3620 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3621 3622 /* Enable all remaining blocks in the MAC. */ 3623 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3624 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3625 DELAY(20); 3626 3627 bnx_blockinit_exit: 3628 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3629 3630 return rc; 3631 } 3632 3633 static int 3634 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3635 uint16_t *chain_prod, uint32_t *prod_bseq) 3636 { 3637 bus_dmamap_t map; 3638 struct rx_bd *rxbd; 3639 uint32_t addr; 3640 int i; 3641 #ifdef BNX_DEBUG 3642 uint16_t debug_chain_prod = *chain_prod; 3643 #endif 3644 uint16_t first_chain_prod; 3645 3646 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3647 3648 /* Map the mbuf cluster into device memory. */ 3649 map = sc->rx_mbuf_map[*chain_prod]; 3650 first_chain_prod = *chain_prod; 3651 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3652 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3653 __FILE__, __LINE__); 3654 3655 m_freem(m_new); 3656 3657 DBRUNIF(1, sc->rx_mbuf_alloc--); 3658 3659 return ENOBUFS; 3660 } 3661 /* Make sure there is room in the receive chain. */ 3662 if (map->dm_nsegs > sc->free_rx_bd) { 3663 bus_dmamap_unload(sc->bnx_dmatag, map); 3664 m_freem(m_new); 3665 return EFBIG; 3666 } 3667 #ifdef BNX_DEBUG 3668 /* Track the distribution of buffer segments. */ 3669 sc->rx_mbuf_segs[map->dm_nsegs]++; 3670 #endif 3671 3672 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3673 BUS_DMASYNC_PREREAD); 3674 3675 /* Update some debug statistics counters */ 3676 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3677 sc->rx_low_watermark = sc->free_rx_bd); 3678 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3679 3680 /* 3681 * Setup the rx_bd for the first segment 3682 */ 3683 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3684 3685 addr = (uint32_t)map->dm_segs[0].ds_addr; 3686 rxbd->rx_bd_haddr_lo = addr; 3687 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3688 rxbd->rx_bd_haddr_hi = addr; 3689 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3690 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3691 *prod_bseq += map->dm_segs[0].ds_len; 3692 bus_dmamap_sync(sc->bnx_dmatag, 3693 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3694 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3695 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3696 3697 for (i = 1; i < map->dm_nsegs; i++) { 3698 *prod = NEXT_RX_BD(*prod); 3699 *chain_prod = RX_CHAIN_IDX(*prod); 3700 3701 rxbd = 3702 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3703 3704 addr = (uint32_t)map->dm_segs[i].ds_addr; 3705 rxbd->rx_bd_haddr_lo = addr; 3706 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3707 rxbd->rx_bd_haddr_hi = addr; 3708 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3709 rxbd->rx_bd_flags = 0; 3710 *prod_bseq += map->dm_segs[i].ds_len; 3711 bus_dmamap_sync(sc->bnx_dmatag, 3712 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3713 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3714 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3715 } 3716 3717 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3718 bus_dmamap_sync(sc->bnx_dmatag, 3719 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3720 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3721 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3722 3723 /* 3724 * Save the mbuf, adjust the map pointer (swap map for first and 3725 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3726 * and update our counter. 3727 */ 3728 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3729 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3730 sc->rx_mbuf_map[*chain_prod] = map; 3731 sc->free_rx_bd -= map->dm_nsegs; 3732 3733 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3734 map->dm_nsegs)); 3735 *prod = NEXT_RX_BD(*prod); 3736 *chain_prod = RX_CHAIN_IDX(*prod); 3737 3738 return 0; 3739 } 3740 3741 /****************************************************************************/ 3742 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3743 /* */ 3744 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3745 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3746 /* necessary. */ 3747 /* */ 3748 /* Returns: */ 3749 /* 0 for success, positive value for failure. */ 3750 /****************************************************************************/ 3751 int 3752 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3753 uint16_t *chain_prod, uint32_t *prod_bseq) 3754 { 3755 struct mbuf *m_new = NULL; 3756 int rc = 0; 3757 uint16_t min_free_bd; 3758 3759 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3760 __func__); 3761 3762 /* Make sure the inputs are valid. */ 3763 DBRUNIF((*chain_prod > MAX_RX_BD), 3764 aprint_error_dev(sc->bnx_dev, 3765 "RX producer out of range: 0x%04X > 0x%04X\n", 3766 *chain_prod, (uint16_t)MAX_RX_BD)); 3767 3768 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3769 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3770 *prod_bseq); 3771 3772 /* try to get in as many mbufs as possible */ 3773 if (sc->mbuf_alloc_size == MCLBYTES) 3774 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3775 else 3776 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3777 while (sc->free_rx_bd >= min_free_bd) { 3778 /* Simulate an mbuf allocation failure. */ 3779 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3780 aprint_error_dev(sc->bnx_dev, 3781 "Simulating mbuf allocation failure.\n"); 3782 sc->mbuf_sim_alloc_failed++; 3783 rc = ENOBUFS; 3784 goto bnx_get_buf_exit); 3785 3786 /* This is a new mbuf allocation. */ 3787 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3788 if (m_new == NULL) { 3789 DBPRINT(sc, BNX_WARN, 3790 "%s(%d): RX mbuf header allocation failed!\n", 3791 __FILE__, __LINE__); 3792 3793 sc->mbuf_alloc_failed++; 3794 3795 rc = ENOBUFS; 3796 goto bnx_get_buf_exit; 3797 } 3798 3799 DBRUNIF(1, sc->rx_mbuf_alloc++); 3800 3801 /* Simulate an mbuf cluster allocation failure. */ 3802 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3803 m_freem(m_new); 3804 sc->rx_mbuf_alloc--; 3805 sc->mbuf_alloc_failed++; 3806 sc->mbuf_sim_alloc_failed++; 3807 rc = ENOBUFS; 3808 goto bnx_get_buf_exit); 3809 3810 if (sc->mbuf_alloc_size == MCLBYTES) 3811 MCLGET(m_new, M_DONTWAIT); 3812 else 3813 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3814 M_DONTWAIT); 3815 if (!(m_new->m_flags & M_EXT)) { 3816 DBPRINT(sc, BNX_WARN, 3817 "%s(%d): RX mbuf chain allocation failed!\n", 3818 __FILE__, __LINE__); 3819 3820 m_freem(m_new); 3821 3822 DBRUNIF(1, sc->rx_mbuf_alloc--); 3823 sc->mbuf_alloc_failed++; 3824 3825 rc = ENOBUFS; 3826 goto bnx_get_buf_exit; 3827 } 3828 3829 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3830 if (rc != 0) 3831 goto bnx_get_buf_exit; 3832 } 3833 3834 bnx_get_buf_exit: 3835 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3836 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3837 *chain_prod, *prod_bseq); 3838 3839 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3840 __func__); 3841 3842 return rc; 3843 } 3844 3845 void 3846 bnx_alloc_pkts(struct work * unused, void * arg) 3847 { 3848 struct bnx_softc *sc = arg; 3849 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3850 struct bnx_pkt *pkt; 3851 int i, s; 3852 3853 for (i = 0; i < 4; i++) { /* magic! */ 3854 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 3855 if (pkt == NULL) 3856 break; 3857 3858 if (bus_dmamap_create(sc->bnx_dmatag, 3859 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3860 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3861 &pkt->pkt_dmamap) != 0) 3862 goto put; 3863 3864 if (!ISSET(ifp->if_flags, IFF_UP)) 3865 goto stopping; 3866 3867 mutex_enter(&sc->tx_pkt_mtx); 3868 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3869 sc->tx_pkt_count++; 3870 mutex_exit(&sc->tx_pkt_mtx); 3871 } 3872 3873 mutex_enter(&sc->tx_pkt_mtx); 3874 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 3875 mutex_exit(&sc->tx_pkt_mtx); 3876 3877 /* fire-up TX now that allocations have been done */ 3878 s = splnet(); 3879 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3880 bnx_start(ifp); 3881 splx(s); 3882 3883 return; 3884 3885 stopping: 3886 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3887 put: 3888 pool_put(bnx_tx_pool, pkt); 3889 return; 3890 } 3891 3892 /****************************************************************************/ 3893 /* Initialize the TX context memory. */ 3894 /* */ 3895 /* Returns: */ 3896 /* Nothing */ 3897 /****************************************************************************/ 3898 void 3899 bnx_init_tx_context(struct bnx_softc *sc) 3900 { 3901 uint32_t val; 3902 3903 /* Initialize the context ID for an L2 TX chain. */ 3904 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3905 /* Set the CID type to support an L2 connection. */ 3906 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3907 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 3908 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3909 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 3910 3911 /* Point the hardware to the first page in the chain. */ 3912 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 3913 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3914 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 3915 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 3916 CTX_WR(sc, GET_CID_ADDR(TX_CID), 3917 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 3918 } else { 3919 /* Set the CID type to support an L2 connection. */ 3920 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3921 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 3922 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3923 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 3924 3925 /* Point the hardware to the first page in the chain. */ 3926 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 3927 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 3928 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 3929 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 3930 } 3931 } 3932 3933 3934 /****************************************************************************/ 3935 /* Allocate memory and initialize the TX data structures. */ 3936 /* */ 3937 /* Returns: */ 3938 /* 0 for success, positive value for failure. */ 3939 /****************************************************************************/ 3940 int 3941 bnx_init_tx_chain(struct bnx_softc *sc) 3942 { 3943 struct tx_bd *txbd; 3944 uint32_t addr; 3945 int i, rc = 0; 3946 3947 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3948 3949 /* Force an allocation of some dmamaps for tx up front */ 3950 bnx_alloc_pkts(NULL, sc); 3951 3952 /* Set the initial TX producer/consumer indices. */ 3953 sc->tx_prod = 0; 3954 sc->tx_cons = 0; 3955 sc->tx_prod_bseq = 0; 3956 sc->used_tx_bd = 0; 3957 sc->max_tx_bd = USABLE_TX_BD; 3958 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3959 DBRUNIF(1, sc->tx_full_count = 0); 3960 3961 /* 3962 * The NetXtreme II supports a linked-list structure called 3963 * a Buffer Descriptor Chain (or BD chain). A BD chain 3964 * consists of a series of 1 or more chain pages, each of which 3965 * consists of a fixed number of BD entries. 3966 * The last BD entry on each page is a pointer to the next page 3967 * in the chain, and the last pointer in the BD chain 3968 * points back to the beginning of the chain. 3969 */ 3970 3971 /* Set the TX next pointer chain entries. */ 3972 for (i = 0; i < TX_PAGES; i++) { 3973 int j; 3974 3975 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3976 3977 /* Check if we've reached the last page. */ 3978 if (i == (TX_PAGES - 1)) 3979 j = 0; 3980 else 3981 j = i + 1; 3982 3983 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 3984 txbd->tx_bd_haddr_lo = addr; 3985 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 3986 txbd->tx_bd_haddr_hi = addr; 3987 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 3988 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 3989 } 3990 3991 /* 3992 * Initialize the context ID for an L2 TX chain. 3993 */ 3994 bnx_init_tx_context(sc); 3995 3996 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3997 3998 return rc; 3999 } 4000 4001 /****************************************************************************/ 4002 /* Free memory and clear the TX data structures. */ 4003 /* */ 4004 /* Returns: */ 4005 /* Nothing. */ 4006 /****************************************************************************/ 4007 void 4008 bnx_free_tx_chain(struct bnx_softc *sc) 4009 { 4010 struct bnx_pkt *pkt; 4011 int i; 4012 4013 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4014 4015 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4016 mutex_enter(&sc->tx_pkt_mtx); 4017 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4018 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4019 mutex_exit(&sc->tx_pkt_mtx); 4020 4021 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4022 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4023 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4024 4025 m_freem(pkt->pkt_mbuf); 4026 DBRUNIF(1, sc->tx_mbuf_alloc--); 4027 4028 mutex_enter(&sc->tx_pkt_mtx); 4029 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4030 } 4031 4032 /* Destroy all the dmamaps we allocated for TX */ 4033 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4034 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4035 sc->tx_pkt_count--; 4036 mutex_exit(&sc->tx_pkt_mtx); 4037 4038 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4039 pool_put(bnx_tx_pool, pkt); 4040 4041 mutex_enter(&sc->tx_pkt_mtx); 4042 } 4043 mutex_exit(&sc->tx_pkt_mtx); 4044 4045 4046 4047 /* Clear each TX chain page. */ 4048 for (i = 0; i < TX_PAGES; i++) { 4049 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4050 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4051 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4052 } 4053 4054 sc->used_tx_bd = 0; 4055 4056 /* Check if we lost any mbufs in the process. */ 4057 DBRUNIF((sc->tx_mbuf_alloc), 4058 aprint_error_dev(sc->bnx_dev, 4059 "Memory leak! Lost %d mbufs from tx chain!\n", 4060 sc->tx_mbuf_alloc)); 4061 4062 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4063 } 4064 4065 /****************************************************************************/ 4066 /* Initialize the RX context memory. */ 4067 /* */ 4068 /* Returns: */ 4069 /* Nothing */ 4070 /****************************************************************************/ 4071 void 4072 bnx_init_rx_context(struct bnx_softc *sc) 4073 { 4074 uint32_t val; 4075 4076 /* Initialize the context ID for an L2 RX chain. */ 4077 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4078 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4079 4080 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4081 uint32_t lo_water, hi_water; 4082 4083 lo_water = BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT; 4084 hi_water = USABLE_RX_BD / 4; 4085 4086 lo_water /= BNX_L2CTX_RX_LO_WATER_MARK_SCALE; 4087 hi_water /= BNX_L2CTX_RX_HI_WATER_MARK_SCALE; 4088 4089 if (hi_water > 0xf) 4090 hi_water = 0xf; 4091 else if (hi_water == 0) 4092 lo_water = 0; 4093 val |= lo_water | 4094 (hi_water << BNX_L2CTX_RX_HI_WATER_MARK_SHIFT); 4095 } 4096 4097 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4098 4099 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4100 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4101 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4102 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4103 } 4104 4105 /* Point the hardware to the first page in the chain. */ 4106 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4107 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4108 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4109 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4110 } 4111 4112 /****************************************************************************/ 4113 /* Allocate memory and initialize the RX data structures. */ 4114 /* */ 4115 /* Returns: */ 4116 /* 0 for success, positive value for failure. */ 4117 /****************************************************************************/ 4118 int 4119 bnx_init_rx_chain(struct bnx_softc *sc) 4120 { 4121 struct rx_bd *rxbd; 4122 int i, rc = 0; 4123 uint16_t prod, chain_prod; 4124 uint32_t prod_bseq, addr; 4125 4126 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4127 4128 /* Initialize the RX producer and consumer indices. */ 4129 sc->rx_prod = 0; 4130 sc->rx_cons = 0; 4131 sc->rx_prod_bseq = 0; 4132 sc->free_rx_bd = USABLE_RX_BD; 4133 sc->max_rx_bd = USABLE_RX_BD; 4134 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4135 DBRUNIF(1, sc->rx_empty_count = 0); 4136 4137 /* Initialize the RX next pointer chain entries. */ 4138 for (i = 0; i < RX_PAGES; i++) { 4139 int j; 4140 4141 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4142 4143 /* Check if we've reached the last page. */ 4144 if (i == (RX_PAGES - 1)) 4145 j = 0; 4146 else 4147 j = i + 1; 4148 4149 /* Setup the chain page pointers. */ 4150 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4151 rxbd->rx_bd_haddr_hi = addr; 4152 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4153 rxbd->rx_bd_haddr_lo = addr; 4154 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4155 0, BNX_RX_CHAIN_PAGE_SZ, 4156 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4157 } 4158 4159 /* Allocate mbuf clusters for the rx_bd chain. */ 4160 prod = prod_bseq = 0; 4161 chain_prod = RX_CHAIN_IDX(prod); 4162 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4163 BNX_PRINTF(sc, 4164 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4165 } 4166 4167 /* Save the RX chain producer index. */ 4168 sc->rx_prod = prod; 4169 sc->rx_prod_bseq = prod_bseq; 4170 4171 for (i = 0; i < RX_PAGES; i++) 4172 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4173 sc->rx_bd_chain_map[i]->dm_mapsize, 4174 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4175 4176 /* Tell the chip about the waiting rx_bd's. */ 4177 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4178 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4179 4180 bnx_init_rx_context(sc); 4181 4182 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4183 4184 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4185 4186 return rc; 4187 } 4188 4189 /****************************************************************************/ 4190 /* Free memory and clear the RX data structures. */ 4191 /* */ 4192 /* Returns: */ 4193 /* Nothing. */ 4194 /****************************************************************************/ 4195 void 4196 bnx_free_rx_chain(struct bnx_softc *sc) 4197 { 4198 int i; 4199 4200 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4201 4202 /* Free any mbufs still in the RX mbuf chain. */ 4203 for (i = 0; i < TOTAL_RX_BD; i++) { 4204 if (sc->rx_mbuf_ptr[i] != NULL) { 4205 if (sc->rx_mbuf_map[i] != NULL) { 4206 bus_dmamap_sync(sc->bnx_dmatag, 4207 sc->rx_mbuf_map[i], 0, 4208 sc->rx_mbuf_map[i]->dm_mapsize, 4209 BUS_DMASYNC_POSTREAD); 4210 bus_dmamap_unload(sc->bnx_dmatag, 4211 sc->rx_mbuf_map[i]); 4212 } 4213 m_freem(sc->rx_mbuf_ptr[i]); 4214 sc->rx_mbuf_ptr[i] = NULL; 4215 DBRUNIF(1, sc->rx_mbuf_alloc--); 4216 } 4217 } 4218 4219 /* Clear each RX chain page. */ 4220 for (i = 0; i < RX_PAGES; i++) 4221 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4222 4223 sc->free_rx_bd = sc->max_rx_bd; 4224 4225 /* Check if we lost any mbufs in the process. */ 4226 DBRUNIF((sc->rx_mbuf_alloc), 4227 aprint_error_dev(sc->bnx_dev, 4228 "Memory leak! Lost %d mbufs from rx chain!\n", 4229 sc->rx_mbuf_alloc)); 4230 4231 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4232 } 4233 4234 /****************************************************************************/ 4235 /* Handles PHY generated interrupt events. */ 4236 /* */ 4237 /* Returns: */ 4238 /* Nothing. */ 4239 /****************************************************************************/ 4240 void 4241 bnx_phy_intr(struct bnx_softc *sc) 4242 { 4243 uint32_t new_link_state, old_link_state; 4244 4245 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4246 BUS_DMASYNC_POSTREAD); 4247 new_link_state = sc->status_block->status_attn_bits & 4248 STATUS_ATTN_BITS_LINK_STATE; 4249 old_link_state = sc->status_block->status_attn_bits_ack & 4250 STATUS_ATTN_BITS_LINK_STATE; 4251 4252 /* Handle any changes if the link state has changed. */ 4253 if (new_link_state != old_link_state) { 4254 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4255 4256 callout_stop(&sc->bnx_timeout); 4257 bnx_tick(sc); 4258 4259 /* Update the status_attn_bits_ack field in the status block. */ 4260 if (new_link_state) { 4261 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4262 STATUS_ATTN_BITS_LINK_STATE); 4263 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4264 } else { 4265 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4266 STATUS_ATTN_BITS_LINK_STATE); 4267 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4268 } 4269 } 4270 4271 /* Acknowledge the link change interrupt. */ 4272 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4273 } 4274 4275 /****************************************************************************/ 4276 /* Handles received frame interrupt events. */ 4277 /* */ 4278 /* Returns: */ 4279 /* Nothing. */ 4280 /****************************************************************************/ 4281 void 4282 bnx_rx_intr(struct bnx_softc *sc) 4283 { 4284 struct status_block *sblk = sc->status_block; 4285 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4286 uint16_t hw_cons, sw_cons, sw_chain_cons; 4287 uint16_t sw_prod, sw_chain_prod; 4288 uint32_t sw_prod_bseq; 4289 struct l2_fhdr *l2fhdr; 4290 int i; 4291 4292 DBRUNIF(1, sc->rx_interrupts++); 4293 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4294 BUS_DMASYNC_POSTREAD); 4295 4296 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4297 for (i = 0; i < RX_PAGES; i++) 4298 bus_dmamap_sync(sc->bnx_dmatag, 4299 sc->rx_bd_chain_map[i], 0, 4300 sc->rx_bd_chain_map[i]->dm_mapsize, 4301 BUS_DMASYNC_POSTWRITE); 4302 4303 /* Get the hardware's view of the RX consumer index. */ 4304 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4305 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4306 hw_cons++; 4307 4308 /* Get working copies of the driver's view of the RX indices. */ 4309 sw_cons = sc->rx_cons; 4310 sw_prod = sc->rx_prod; 4311 sw_prod_bseq = sc->rx_prod_bseq; 4312 4313 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4314 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4315 __func__, sw_prod, sw_cons, sw_prod_bseq); 4316 4317 /* Prevent speculative reads from getting ahead of the status block. */ 4318 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4319 BUS_SPACE_BARRIER_READ); 4320 4321 /* Update some debug statistics counters */ 4322 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4323 sc->rx_low_watermark = sc->free_rx_bd); 4324 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4325 4326 /* 4327 * Scan through the receive chain as long 4328 * as there is work to do. 4329 */ 4330 while (sw_cons != hw_cons) { 4331 struct mbuf *m; 4332 struct rx_bd *rxbd __diagused; 4333 unsigned int len; 4334 uint32_t status; 4335 4336 /* Convert the producer/consumer indices to an actual 4337 * rx_bd index. 4338 */ 4339 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4340 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4341 4342 /* Get the used rx_bd. */ 4343 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4344 sc->free_rx_bd++; 4345 4346 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4347 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4348 4349 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4350 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4351 #ifdef DIAGNOSTIC 4352 /* Validate that this is the last rx_bd. */ 4353 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4354 printf("%s: Unexpected mbuf found in " 4355 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4356 sw_chain_cons); 4357 } 4358 #endif 4359 4360 /* DRC - ToDo: If the received packet is small, say less 4361 * than 128 bytes, allocate a new mbuf here, 4362 * copy the data to that mbuf, and recycle 4363 * the mapped jumbo frame. 4364 */ 4365 4366 /* Unmap the mbuf from DMA space. */ 4367 #ifdef DIAGNOSTIC 4368 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4369 printf("invalid map sw_cons 0x%x " 4370 "sw_prod 0x%x " 4371 "sw_chain_cons 0x%x " 4372 "sw_chain_prod 0x%x " 4373 "hw_cons 0x%x " 4374 "TOTAL_RX_BD_PER_PAGE 0x%x " 4375 "TOTAL_RX_BD 0x%x\n", 4376 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4377 hw_cons, 4378 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4379 } 4380 #endif 4381 bus_dmamap_sync(sc->bnx_dmatag, 4382 sc->rx_mbuf_map[sw_chain_cons], 0, 4383 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4384 BUS_DMASYNC_POSTREAD); 4385 bus_dmamap_unload(sc->bnx_dmatag, 4386 sc->rx_mbuf_map[sw_chain_cons]); 4387 4388 /* Remove the mbuf from the driver's chain. */ 4389 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4390 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4391 4392 /* 4393 * Frames received on the NetXteme II are prepended 4394 * with the l2_fhdr structure which provides status 4395 * information about the received frame (including 4396 * VLAN tags and checksum info) and are also 4397 * automatically adjusted to align the IP header 4398 * (i.e. two null bytes are inserted before the 4399 * Ethernet header). 4400 */ 4401 l2fhdr = mtod(m, struct l2_fhdr *); 4402 4403 len = l2fhdr->l2_fhdr_pkt_len; 4404 status = l2fhdr->l2_fhdr_status; 4405 4406 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4407 aprint_error("Simulating l2_fhdr status error.\n"); 4408 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4409 4410 /* Watch for unusual sized frames. */ 4411 DBRUNIF(((len < BNX_MIN_MTU) || 4412 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4413 aprint_error_dev(sc->bnx_dev, 4414 "Unusual frame size found. " 4415 "Min(%d), Actual(%d), Max(%d)\n", 4416 (int)BNX_MIN_MTU, len, 4417 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4418 4419 bnx_dump_mbuf(sc, m); 4420 bnx_breakpoint(sc)); 4421 4422 len -= ETHER_CRC_LEN; 4423 4424 /* Check the received frame for errors. */ 4425 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4426 L2_FHDR_ERRORS_PHY_DECODE | 4427 L2_FHDR_ERRORS_ALIGNMENT | 4428 L2_FHDR_ERRORS_TOO_SHORT | 4429 L2_FHDR_ERRORS_GIANT_FRAME)) || 4430 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4431 len > 4432 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4433 ifp->if_ierrors++; 4434 DBRUNIF(1, sc->l2fhdr_status_errors++); 4435 4436 /* Reuse the mbuf for a new frame. */ 4437 if (bnx_add_buf(sc, m, &sw_prod, 4438 &sw_chain_prod, &sw_prod_bseq)) { 4439 DBRUNIF(1, bnx_breakpoint(sc)); 4440 panic("%s: Can't reuse RX mbuf!\n", 4441 device_xname(sc->bnx_dev)); 4442 } 4443 continue; 4444 } 4445 4446 /* 4447 * Get a new mbuf for the rx_bd. If no new 4448 * mbufs are available then reuse the current mbuf, 4449 * log an ierror on the interface, and generate 4450 * an error in the system log. 4451 */ 4452 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4453 &sw_prod_bseq)) { 4454 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4455 "Failed to allocate " 4456 "new mbuf, incoming frame dropped!\n")); 4457 4458 ifp->if_ierrors++; 4459 4460 /* Try and reuse the exisitng mbuf. */ 4461 if (bnx_add_buf(sc, m, &sw_prod, 4462 &sw_chain_prod, &sw_prod_bseq)) { 4463 DBRUNIF(1, bnx_breakpoint(sc)); 4464 panic("%s: Double mbuf allocation " 4465 "failure!", 4466 device_xname(sc->bnx_dev)); 4467 } 4468 continue; 4469 } 4470 4471 /* Skip over the l2_fhdr when passing the data up 4472 * the stack. 4473 */ 4474 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4475 4476 /* Adjust the pckt length to match the received data. */ 4477 m->m_pkthdr.len = m->m_len = len; 4478 4479 /* Send the packet to the appropriate interface. */ 4480 m->m_pkthdr.rcvif = ifp; 4481 4482 DBRUN(BNX_VERBOSE_RECV, 4483 struct ether_header *eh; 4484 eh = mtod(m, struct ether_header *); 4485 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4486 __func__, ether_sprintf(eh->ether_dhost), 4487 ether_sprintf(eh->ether_shost), 4488 htons(eh->ether_type))); 4489 4490 /* Validate the checksum. */ 4491 4492 /* Check for an IP datagram. */ 4493 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4494 /* Check if the IP checksum is valid. */ 4495 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 4496 == 0) 4497 m->m_pkthdr.csum_flags |= 4498 M_CSUM_IPv4; 4499 #ifdef BNX_DEBUG 4500 else 4501 DBPRINT(sc, BNX_WARN_SEND, 4502 "%s(): Invalid IP checksum " 4503 "= 0x%04X!\n", 4504 __func__, 4505 l2fhdr->l2_fhdr_ip_xsum 4506 ); 4507 #endif 4508 } 4509 4510 /* Check for a valid TCP/UDP frame. */ 4511 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4512 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4513 /* Check for a good TCP/UDP checksum. */ 4514 if ((status & 4515 (L2_FHDR_ERRORS_TCP_XSUM | 4516 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4517 m->m_pkthdr.csum_flags |= 4518 M_CSUM_TCPv4 | 4519 M_CSUM_UDPv4; 4520 } else { 4521 DBPRINT(sc, BNX_WARN_SEND, 4522 "%s(): Invalid TCP/UDP " 4523 "checksum = 0x%04X!\n", 4524 __func__, 4525 l2fhdr->l2_fhdr_tcp_udp_xsum); 4526 } 4527 } 4528 4529 /* 4530 * If we received a packet with a vlan tag, 4531 * attach that information to the packet. 4532 */ 4533 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4534 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4535 VLAN_INPUT_TAG(ifp, m, 4536 l2fhdr->l2_fhdr_vlan_tag, 4537 continue); 4538 } 4539 4540 /* 4541 * Handle BPF listeners. Let the BPF 4542 * user see the packet. 4543 */ 4544 bpf_mtap(ifp, m); 4545 4546 /* Pass the mbuf off to the upper layers. */ 4547 ifp->if_ipackets++; 4548 DBPRINT(sc, BNX_VERBOSE_RECV, 4549 "%s(): Passing received frame up.\n", __func__); 4550 (*ifp->if_input)(ifp, m); 4551 DBRUNIF(1, sc->rx_mbuf_alloc--); 4552 4553 } 4554 4555 sw_cons = NEXT_RX_BD(sw_cons); 4556 4557 /* Refresh hw_cons to see if there's new work */ 4558 if (sw_cons == hw_cons) { 4559 hw_cons = sc->hw_rx_cons = 4560 sblk->status_rx_quick_consumer_index0; 4561 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4562 USABLE_RX_BD_PER_PAGE) 4563 hw_cons++; 4564 } 4565 4566 /* Prevent speculative reads from getting ahead of 4567 * the status block. 4568 */ 4569 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4570 BUS_SPACE_BARRIER_READ); 4571 } 4572 4573 for (i = 0; i < RX_PAGES; i++) 4574 bus_dmamap_sync(sc->bnx_dmatag, 4575 sc->rx_bd_chain_map[i], 0, 4576 sc->rx_bd_chain_map[i]->dm_mapsize, 4577 BUS_DMASYNC_PREWRITE); 4578 4579 sc->rx_cons = sw_cons; 4580 sc->rx_prod = sw_prod; 4581 sc->rx_prod_bseq = sw_prod_bseq; 4582 4583 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4584 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4585 4586 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4587 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4588 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4589 } 4590 4591 /****************************************************************************/ 4592 /* Handles transmit completion interrupt events. */ 4593 /* */ 4594 /* Returns: */ 4595 /* Nothing. */ 4596 /****************************************************************************/ 4597 void 4598 bnx_tx_intr(struct bnx_softc *sc) 4599 { 4600 struct status_block *sblk = sc->status_block; 4601 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4602 struct bnx_pkt *pkt; 4603 bus_dmamap_t map; 4604 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4605 4606 DBRUNIF(1, sc->tx_interrupts++); 4607 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4608 BUS_DMASYNC_POSTREAD); 4609 4610 /* Get the hardware's view of the TX consumer index. */ 4611 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4612 4613 /* Skip to the next entry if this is a chain page pointer. */ 4614 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4615 hw_tx_cons++; 4616 4617 sw_tx_cons = sc->tx_cons; 4618 4619 /* Prevent speculative reads from getting ahead of the status block. */ 4620 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4621 BUS_SPACE_BARRIER_READ); 4622 4623 /* Cycle through any completed TX chain page entries. */ 4624 while (sw_tx_cons != hw_tx_cons) { 4625 #ifdef BNX_DEBUG 4626 struct tx_bd *txbd = NULL; 4627 #endif 4628 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4629 4630 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4631 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4632 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4633 4634 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4635 aprint_error_dev(sc->bnx_dev, 4636 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4637 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4638 4639 DBRUNIF(1, txbd = &sc->tx_bd_chain 4640 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4641 4642 DBRUNIF((txbd == NULL), 4643 aprint_error_dev(sc->bnx_dev, 4644 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4645 bnx_breakpoint(sc)); 4646 4647 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4648 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4649 4650 4651 mutex_enter(&sc->tx_pkt_mtx); 4652 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4653 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4654 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4655 mutex_exit(&sc->tx_pkt_mtx); 4656 /* 4657 * Free the associated mbuf. Remember 4658 * that only the last tx_bd of a packet 4659 * has an mbuf pointer and DMA map. 4660 */ 4661 map = pkt->pkt_dmamap; 4662 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4663 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4664 bus_dmamap_unload(sc->bnx_dmatag, map); 4665 4666 m_freem(pkt->pkt_mbuf); 4667 DBRUNIF(1, sc->tx_mbuf_alloc--); 4668 4669 ifp->if_opackets++; 4670 4671 mutex_enter(&sc->tx_pkt_mtx); 4672 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4673 } 4674 mutex_exit(&sc->tx_pkt_mtx); 4675 4676 sc->used_tx_bd--; 4677 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4678 __FILE__, __LINE__, sc->used_tx_bd); 4679 4680 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4681 4682 /* Refresh hw_cons to see if there's new work. */ 4683 hw_tx_cons = sc->hw_tx_cons = 4684 sblk->status_tx_quick_consumer_index0; 4685 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4686 USABLE_TX_BD_PER_PAGE) 4687 hw_tx_cons++; 4688 4689 /* Prevent speculative reads from getting ahead of 4690 * the status block. 4691 */ 4692 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4693 BUS_SPACE_BARRIER_READ); 4694 } 4695 4696 /* Clear the TX timeout timer. */ 4697 ifp->if_timer = 0; 4698 4699 /* Clear the tx hardware queue full flag. */ 4700 if (sc->used_tx_bd < sc->max_tx_bd) { 4701 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4702 aprint_debug_dev(sc->bnx_dev, 4703 "Open TX chain! %d/%d (used/total)\n", 4704 sc->used_tx_bd, sc->max_tx_bd)); 4705 ifp->if_flags &= ~IFF_OACTIVE; 4706 } 4707 4708 sc->tx_cons = sw_tx_cons; 4709 } 4710 4711 /****************************************************************************/ 4712 /* Disables interrupt generation. */ 4713 /* */ 4714 /* Returns: */ 4715 /* Nothing. */ 4716 /****************************************************************************/ 4717 void 4718 bnx_disable_intr(struct bnx_softc *sc) 4719 { 4720 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4721 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4722 } 4723 4724 /****************************************************************************/ 4725 /* Enables interrupt generation. */ 4726 /* */ 4727 /* Returns: */ 4728 /* Nothing. */ 4729 /****************************************************************************/ 4730 void 4731 bnx_enable_intr(struct bnx_softc *sc) 4732 { 4733 uint32_t val; 4734 4735 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4736 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4737 4738 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4739 sc->last_status_idx); 4740 4741 val = REG_RD(sc, BNX_HC_COMMAND); 4742 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4743 } 4744 4745 /****************************************************************************/ 4746 /* Handles controller initialization. */ 4747 /* */ 4748 /****************************************************************************/ 4749 int 4750 bnx_init(struct ifnet *ifp) 4751 { 4752 struct bnx_softc *sc = ifp->if_softc; 4753 uint32_t ether_mtu; 4754 int s, error = 0; 4755 4756 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4757 4758 s = splnet(); 4759 4760 bnx_stop(ifp, 0); 4761 4762 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4763 aprint_error_dev(sc->bnx_dev, 4764 "Controller reset failed!\n"); 4765 goto bnx_init_exit; 4766 } 4767 4768 if ((error = bnx_chipinit(sc)) != 0) { 4769 aprint_error_dev(sc->bnx_dev, 4770 "Controller initialization failed!\n"); 4771 goto bnx_init_exit; 4772 } 4773 4774 if ((error = bnx_blockinit(sc)) != 0) { 4775 aprint_error_dev(sc->bnx_dev, 4776 "Block initialization failed!\n"); 4777 goto bnx_init_exit; 4778 } 4779 4780 /* Calculate and program the Ethernet MRU size. */ 4781 if (ifp->if_mtu <= ETHERMTU) { 4782 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4783 sc->mbuf_alloc_size = MCLBYTES; 4784 } else { 4785 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4786 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4787 } 4788 4789 4790 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4791 __func__, ether_mtu); 4792 4793 /* 4794 * Program the MRU and enable Jumbo frame 4795 * support. 4796 */ 4797 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4798 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4799 4800 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4801 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4802 4803 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4804 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4805 sc->mbuf_alloc_size, sc->max_frame_size); 4806 4807 /* Program appropriate promiscuous/multicast filtering. */ 4808 bnx_iff(sc); 4809 4810 /* Init RX buffer descriptor chain. */ 4811 bnx_init_rx_chain(sc); 4812 4813 /* Init TX buffer descriptor chain. */ 4814 bnx_init_tx_chain(sc); 4815 4816 /* Enable host interrupts. */ 4817 bnx_enable_intr(sc); 4818 4819 if ((error = ether_mediachange(ifp)) != 0) 4820 goto bnx_init_exit; 4821 4822 SET(ifp->if_flags, IFF_RUNNING); 4823 CLR(ifp->if_flags, IFF_OACTIVE); 4824 4825 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4826 4827 bnx_init_exit: 4828 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4829 4830 splx(s); 4831 4832 return error; 4833 } 4834 4835 /****************************************************************************/ 4836 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4837 /* memory visible to the controller. */ 4838 /* */ 4839 /* Returns: */ 4840 /* 0 for success, positive value for failure. */ 4841 /****************************************************************************/ 4842 int 4843 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4844 { 4845 struct bnx_pkt *pkt; 4846 bus_dmamap_t map; 4847 struct tx_bd *txbd = NULL; 4848 uint16_t vlan_tag = 0, flags = 0; 4849 uint16_t chain_prod, prod; 4850 #ifdef BNX_DEBUG 4851 uint16_t debug_prod; 4852 #endif 4853 uint32_t addr, prod_bseq; 4854 int i, error; 4855 struct m_tag *mtag; 4856 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 4857 4858 mutex_enter(&sc->tx_pkt_mtx); 4859 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 4860 if (pkt == NULL) { 4861 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 4862 mutex_exit(&sc->tx_pkt_mtx); 4863 return ENETDOWN; 4864 } 4865 4866 if (sc->tx_pkt_count <= TOTAL_TX_BD && 4867 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 4868 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 4869 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4870 } 4871 4872 mutex_exit(&sc->tx_pkt_mtx); 4873 return ENOMEM; 4874 } 4875 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4876 mutex_exit(&sc->tx_pkt_mtx); 4877 4878 /* Transfer any checksum offload flags to the bd. */ 4879 if (m->m_pkthdr.csum_flags) { 4880 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 4881 flags |= TX_BD_FLAGS_IP_CKSUM; 4882 if (m->m_pkthdr.csum_flags & 4883 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4884 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4885 } 4886 4887 /* Transfer any VLAN tags to the bd. */ 4888 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m); 4889 if (mtag != NULL) { 4890 flags |= TX_BD_FLAGS_VLAN_TAG; 4891 vlan_tag = VLAN_TAG_VALUE(mtag); 4892 } 4893 4894 /* Map the mbuf into DMAable memory. */ 4895 prod = sc->tx_prod; 4896 chain_prod = TX_CHAIN_IDX(prod); 4897 map = pkt->pkt_dmamap; 4898 4899 /* Map the mbuf into our DMA address space. */ 4900 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 4901 if (error != 0) { 4902 aprint_error_dev(sc->bnx_dev, 4903 "Error mapping mbuf into TX chain!\n"); 4904 sc->tx_dma_map_failures++; 4905 goto maperr; 4906 } 4907 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4908 BUS_DMASYNC_PREWRITE); 4909 /* Make sure there's room in the chain */ 4910 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 4911 goto nospace; 4912 4913 /* prod points to an empty tx_bd at this point. */ 4914 prod_bseq = sc->tx_prod_bseq; 4915 #ifdef BNX_DEBUG 4916 debug_prod = chain_prod; 4917 #endif 4918 DBPRINT(sc, BNX_INFO_SEND, 4919 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4920 "prod_bseq = 0x%08X\n", 4921 __func__, prod, chain_prod, prod_bseq); 4922 4923 /* 4924 * Cycle through each mbuf segment that makes up 4925 * the outgoing frame, gathering the mapping info 4926 * for that segment and creating a tx_bd for the 4927 * mbuf. 4928 */ 4929 for (i = 0; i < map->dm_nsegs ; i++) { 4930 chain_prod = TX_CHAIN_IDX(prod); 4931 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4932 4933 addr = (uint32_t)map->dm_segs[i].ds_addr; 4934 txbd->tx_bd_haddr_lo = addr; 4935 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 4936 txbd->tx_bd_haddr_hi = addr; 4937 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 4938 txbd->tx_bd_vlan_tag = vlan_tag; 4939 txbd->tx_bd_flags = flags; 4940 prod_bseq += map->dm_segs[i].ds_len; 4941 if (i == 0) 4942 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 4943 prod = NEXT_TX_BD(prod); 4944 } 4945 /* Set the END flag on the last TX buffer descriptor. */ 4946 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 4947 4948 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 4949 4950 DBPRINT(sc, BNX_INFO_SEND, 4951 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4952 "prod_bseq = 0x%08X\n", 4953 __func__, prod, chain_prod, prod_bseq); 4954 4955 pkt->pkt_mbuf = m; 4956 pkt->pkt_end_desc = chain_prod; 4957 4958 mutex_enter(&sc->tx_pkt_mtx); 4959 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 4960 mutex_exit(&sc->tx_pkt_mtx); 4961 4962 sc->used_tx_bd += map->dm_nsegs; 4963 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4964 __FILE__, __LINE__, sc->used_tx_bd); 4965 4966 /* Update some debug statistics counters */ 4967 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4968 sc->tx_hi_watermark = sc->used_tx_bd); 4969 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 4970 DBRUNIF(1, sc->tx_mbuf_alloc++); 4971 4972 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 4973 map->dm_nsegs)); 4974 4975 /* prod points to the next free tx_bd at this point. */ 4976 sc->tx_prod = prod; 4977 sc->tx_prod_bseq = prod_bseq; 4978 4979 return 0; 4980 4981 4982 nospace: 4983 bus_dmamap_unload(sc->bnx_dmatag, map); 4984 maperr: 4985 mutex_enter(&sc->tx_pkt_mtx); 4986 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4987 mutex_exit(&sc->tx_pkt_mtx); 4988 4989 return ENOMEM; 4990 } 4991 4992 /****************************************************************************/ 4993 /* Main transmit routine. */ 4994 /* */ 4995 /* Returns: */ 4996 /* Nothing. */ 4997 /****************************************************************************/ 4998 void 4999 bnx_start(struct ifnet *ifp) 5000 { 5001 struct bnx_softc *sc = ifp->if_softc; 5002 struct mbuf *m_head = NULL; 5003 int count = 0; 5004 #ifdef BNX_DEBUG 5005 uint16_t tx_chain_prod; 5006 #endif 5007 5008 /* If there's no link or the transmit queue is empty then just exit. */ 5009 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5010 DBPRINT(sc, BNX_INFO_SEND, 5011 "%s(): output active or device not running.\n", __func__); 5012 goto bnx_start_exit; 5013 } 5014 5015 /* prod points to the next free tx_bd. */ 5016 #ifdef BNX_DEBUG 5017 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5018 #endif 5019 5020 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5021 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5022 "used_tx %d max_tx %d\n", 5023 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5024 sc->used_tx_bd, sc->max_tx_bd); 5025 5026 /* 5027 * Keep adding entries while there is space in the ring. 5028 */ 5029 while (sc->used_tx_bd < sc->max_tx_bd) { 5030 /* Check for any frames to send. */ 5031 IFQ_POLL(&ifp->if_snd, m_head); 5032 if (m_head == NULL) 5033 break; 5034 5035 /* 5036 * Pack the data into the transmit ring. If we 5037 * don't have room, set the OACTIVE flag to wait 5038 * for the NIC to drain the chain. 5039 */ 5040 if (bnx_tx_encap(sc, m_head)) { 5041 ifp->if_flags |= IFF_OACTIVE; 5042 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5043 "business! Total tx_bd used = %d\n", 5044 sc->used_tx_bd); 5045 break; 5046 } 5047 5048 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5049 count++; 5050 5051 /* Send a copy of the frame to any BPF listeners. */ 5052 bpf_mtap(ifp, m_head); 5053 } 5054 5055 if (count == 0) { 5056 /* no packets were dequeued */ 5057 DBPRINT(sc, BNX_VERBOSE_SEND, 5058 "%s(): No packets were dequeued\n", __func__); 5059 goto bnx_start_exit; 5060 } 5061 5062 /* Update the driver's counters. */ 5063 #ifdef BNX_DEBUG 5064 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5065 #endif 5066 5067 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 5068 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, sc->tx_prod, 5069 tx_chain_prod, sc->tx_prod_bseq); 5070 5071 /* Start the transmit. */ 5072 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5073 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5074 5075 /* Set the tx timeout. */ 5076 ifp->if_timer = BNX_TX_TIMEOUT; 5077 5078 bnx_start_exit: 5079 return; 5080 } 5081 5082 /****************************************************************************/ 5083 /* Handles any IOCTL calls from the operating system. */ 5084 /* */ 5085 /* Returns: */ 5086 /* 0 for success, positive value for failure. */ 5087 /****************************************************************************/ 5088 int 5089 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5090 { 5091 struct bnx_softc *sc = ifp->if_softc; 5092 struct ifreq *ifr = (struct ifreq *) data; 5093 struct mii_data *mii = &sc->bnx_mii; 5094 int s, error = 0; 5095 5096 s = splnet(); 5097 5098 switch (command) { 5099 case SIOCSIFFLAGS: 5100 if ((error = ifioctl_common(ifp, command, data)) != 0) 5101 break; 5102 /* XXX set an ifflags callback and let ether_ioctl 5103 * handle all of this. 5104 */ 5105 if (ISSET(ifp->if_flags, IFF_UP)) { 5106 if (ifp->if_flags & IFF_RUNNING) 5107 error = ENETRESET; 5108 else 5109 bnx_init(ifp); 5110 } else if (ifp->if_flags & IFF_RUNNING) 5111 bnx_stop(ifp, 1); 5112 break; 5113 5114 case SIOCSIFMEDIA: 5115 case SIOCGIFMEDIA: 5116 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5117 sc->bnx_phy_flags); 5118 5119 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5120 break; 5121 5122 default: 5123 error = ether_ioctl(ifp, command, data); 5124 } 5125 5126 if (error == ENETRESET) { 5127 if (ifp->if_flags & IFF_RUNNING) 5128 bnx_iff(sc); 5129 error = 0; 5130 } 5131 5132 splx(s); 5133 return error; 5134 } 5135 5136 /****************************************************************************/ 5137 /* Transmit timeout handler. */ 5138 /* */ 5139 /* Returns: */ 5140 /* Nothing. */ 5141 /****************************************************************************/ 5142 void 5143 bnx_watchdog(struct ifnet *ifp) 5144 { 5145 struct bnx_softc *sc = ifp->if_softc; 5146 5147 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5148 bnx_dump_status_block(sc)); 5149 /* 5150 * If we are in this routine because of pause frames, then 5151 * don't reset the hardware. 5152 */ 5153 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5154 return; 5155 5156 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5157 5158 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5159 5160 bnx_init(ifp); 5161 5162 ifp->if_oerrors++; 5163 } 5164 5165 /* 5166 * Interrupt handler. 5167 */ 5168 /****************************************************************************/ 5169 /* Main interrupt entry point. Verifies that the controller generated the */ 5170 /* interrupt and then calls a separate routine for handle the various */ 5171 /* interrupt causes (PHY, TX, RX). */ 5172 /* */ 5173 /* Returns: */ 5174 /* 0 for success, positive value for failure. */ 5175 /****************************************************************************/ 5176 int 5177 bnx_intr(void *xsc) 5178 { 5179 struct bnx_softc *sc; 5180 struct ifnet *ifp; 5181 uint32_t status_attn_bits; 5182 const struct status_block *sblk; 5183 5184 sc = xsc; 5185 5186 ifp = &sc->bnx_ec.ec_if; 5187 5188 if (!device_is_active(sc->bnx_dev) || 5189 (ifp->if_flags & IFF_RUNNING) == 0) 5190 return 0; 5191 5192 DBRUNIF(1, sc->interrupts_generated++); 5193 5194 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5195 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 5196 5197 /* 5198 * If the hardware status block index 5199 * matches the last value read by the 5200 * driver and we haven't asserted our 5201 * interrupt then there's nothing to do. 5202 */ 5203 if ((sc->status_block->status_idx == sc->last_status_idx) && 5204 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 5205 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 5206 return 0; 5207 5208 /* Ack the interrupt and stop others from occuring. */ 5209 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5210 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5211 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5212 5213 /* Keep processing data as long as there is work to do. */ 5214 for (;;) { 5215 sblk = sc->status_block; 5216 status_attn_bits = sblk->status_attn_bits; 5217 5218 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5219 aprint_debug("Simulating unexpected status attention bit set."); 5220 status_attn_bits = status_attn_bits | 5221 STATUS_ATTN_BITS_PARITY_ERROR); 5222 5223 /* Was it a link change interrupt? */ 5224 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5225 (sblk->status_attn_bits_ack & 5226 STATUS_ATTN_BITS_LINK_STATE)) 5227 bnx_phy_intr(sc); 5228 5229 /* If any other attention is asserted then the chip is toast. */ 5230 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5231 (sblk->status_attn_bits_ack & 5232 ~STATUS_ATTN_BITS_LINK_STATE))) { 5233 DBRUN(1, sc->unexpected_attentions++); 5234 5235 BNX_PRINTF(sc, 5236 "Fatal attention detected: 0x%08X\n", 5237 sblk->status_attn_bits); 5238 5239 DBRUN(BNX_FATAL, 5240 if (bnx_debug_unexpected_attention == 0) 5241 bnx_breakpoint(sc)); 5242 5243 bnx_init(ifp); 5244 return 1; 5245 } 5246 5247 /* Check for any completed RX frames. */ 5248 if (sblk->status_rx_quick_consumer_index0 != 5249 sc->hw_rx_cons) 5250 bnx_rx_intr(sc); 5251 5252 /* Check for any completed TX frames. */ 5253 if (sblk->status_tx_quick_consumer_index0 != 5254 sc->hw_tx_cons) 5255 bnx_tx_intr(sc); 5256 5257 /* 5258 * Save the status block index value for use during the 5259 * next interrupt. 5260 */ 5261 sc->last_status_idx = sblk->status_idx; 5262 5263 /* Prevent speculative reads from getting ahead of the 5264 * status block. 5265 */ 5266 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 5267 BUS_SPACE_BARRIER_READ); 5268 5269 /* If there's no work left then exit the isr. */ 5270 if ((sblk->status_rx_quick_consumer_index0 == 5271 sc->hw_rx_cons) && 5272 (sblk->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5273 break; 5274 } 5275 5276 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5277 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 5278 5279 /* Re-enable interrupts. */ 5280 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5281 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5282 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5283 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5284 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5285 5286 /* Handle any frames that arrived while handling the interrupt. */ 5287 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 5288 bnx_start(ifp); 5289 5290 return 1; 5291 } 5292 5293 /****************************************************************************/ 5294 /* Programs the various packet receive modes (broadcast and multicast). */ 5295 /* */ 5296 /* Returns: */ 5297 /* Nothing. */ 5298 /****************************************************************************/ 5299 void 5300 bnx_iff(struct bnx_softc *sc) 5301 { 5302 struct ethercom *ec = &sc->bnx_ec; 5303 struct ifnet *ifp = &ec->ec_if; 5304 struct ether_multi *enm; 5305 struct ether_multistep step; 5306 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5307 uint32_t rx_mode, sort_mode; 5308 int h, i; 5309 5310 /* Initialize receive mode default settings. */ 5311 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5312 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5313 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5314 ifp->if_flags &= ~IFF_ALLMULTI; 5315 5316 /* 5317 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5318 * be enbled. 5319 */ 5320 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5321 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5322 5323 /* 5324 * Check for promiscuous, all multicast, or selected 5325 * multicast address filtering. 5326 */ 5327 if (ifp->if_flags & IFF_PROMISC) { 5328 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5329 5330 ifp->if_flags |= IFF_ALLMULTI; 5331 /* Enable promiscuous mode. */ 5332 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5333 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5334 } else if (ifp->if_flags & IFF_ALLMULTI) { 5335 allmulti: 5336 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5337 5338 ifp->if_flags |= IFF_ALLMULTI; 5339 /* Enable all multicast addresses. */ 5340 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5341 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5342 0xffffffff); 5343 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5344 } else { 5345 /* Accept one or more multicast(s). */ 5346 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5347 5348 ETHER_FIRST_MULTI(step, ec, enm); 5349 while (enm != NULL) { 5350 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5351 ETHER_ADDR_LEN)) { 5352 goto allmulti; 5353 } 5354 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5355 0xFF; 5356 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5357 ETHER_NEXT_MULTI(step, enm); 5358 } 5359 5360 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5361 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5362 hashes[i]); 5363 5364 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5365 } 5366 5367 /* Only make changes if the recive mode has actually changed. */ 5368 if (rx_mode != sc->rx_mode) { 5369 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5370 rx_mode); 5371 5372 sc->rx_mode = rx_mode; 5373 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5374 } 5375 5376 /* Disable and clear the exisitng sort before enabling a new sort. */ 5377 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5378 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5379 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5380 } 5381 5382 /****************************************************************************/ 5383 /* Called periodically to updates statistics from the controllers */ 5384 /* statistics block. */ 5385 /* */ 5386 /* Returns: */ 5387 /* Nothing. */ 5388 /****************************************************************************/ 5389 void 5390 bnx_stats_update(struct bnx_softc *sc) 5391 { 5392 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5393 struct statistics_block *stats; 5394 5395 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5396 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5397 BUS_DMASYNC_POSTREAD); 5398 5399 stats = (struct statistics_block *)sc->stats_block; 5400 5401 /* 5402 * Update the interface statistics from the 5403 * hardware statistics. 5404 */ 5405 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5406 5407 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5408 (u_long)stats->stat_EtherStatsOverrsizePkts + 5409 (u_long)stats->stat_IfInMBUFDiscards + 5410 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5411 (u_long)stats->stat_Dot3StatsFCSErrors; 5412 5413 ifp->if_oerrors = (u_long) 5414 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5415 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5416 (u_long)stats->stat_Dot3StatsLateCollisions; 5417 5418 /* 5419 * Certain controllers don't report 5420 * carrier sense errors correctly. 5421 * See errata E11_5708CA0_1165. 5422 */ 5423 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5424 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5425 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5426 5427 /* 5428 * Update the sysctl statistics from the 5429 * hardware statistics. 5430 */ 5431 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5432 (uint64_t) stats->stat_IfHCInOctets_lo; 5433 5434 sc->stat_IfHCInBadOctets = 5435 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5436 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5437 5438 sc->stat_IfHCOutOctets = 5439 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5440 (uint64_t) stats->stat_IfHCOutOctets_lo; 5441 5442 sc->stat_IfHCOutBadOctets = 5443 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5444 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5445 5446 sc->stat_IfHCInUcastPkts = 5447 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5448 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5449 5450 sc->stat_IfHCInMulticastPkts = 5451 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5452 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5453 5454 sc->stat_IfHCInBroadcastPkts = 5455 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5456 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5457 5458 sc->stat_IfHCOutUcastPkts = 5459 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5460 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5461 5462 sc->stat_IfHCOutMulticastPkts = 5463 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5464 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5465 5466 sc->stat_IfHCOutBroadcastPkts = 5467 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5468 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5469 5470 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5471 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5472 5473 sc->stat_Dot3StatsCarrierSenseErrors = 5474 stats->stat_Dot3StatsCarrierSenseErrors; 5475 5476 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5477 5478 sc->stat_Dot3StatsAlignmentErrors = 5479 stats->stat_Dot3StatsAlignmentErrors; 5480 5481 sc->stat_Dot3StatsSingleCollisionFrames = 5482 stats->stat_Dot3StatsSingleCollisionFrames; 5483 5484 sc->stat_Dot3StatsMultipleCollisionFrames = 5485 stats->stat_Dot3StatsMultipleCollisionFrames; 5486 5487 sc->stat_Dot3StatsDeferredTransmissions = 5488 stats->stat_Dot3StatsDeferredTransmissions; 5489 5490 sc->stat_Dot3StatsExcessiveCollisions = 5491 stats->stat_Dot3StatsExcessiveCollisions; 5492 5493 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5494 5495 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5496 5497 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5498 5499 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5500 5501 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5502 5503 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5504 5505 sc->stat_EtherStatsPktsRx64Octets = 5506 stats->stat_EtherStatsPktsRx64Octets; 5507 5508 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5509 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5510 5511 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5512 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5513 5514 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5515 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5516 5517 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5518 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5519 5520 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5521 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5522 5523 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5524 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5525 5526 sc->stat_EtherStatsPktsTx64Octets = 5527 stats->stat_EtherStatsPktsTx64Octets; 5528 5529 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5530 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5531 5532 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5533 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5534 5535 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5536 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5537 5538 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5539 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5540 5541 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5542 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5543 5544 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5545 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5546 5547 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5548 5549 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5550 5551 sc->stat_OutXonSent = stats->stat_OutXonSent; 5552 5553 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5554 5555 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5556 5557 sc->stat_MacControlFramesReceived = 5558 stats->stat_MacControlFramesReceived; 5559 5560 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5561 5562 sc->stat_IfInFramesL2FilterDiscards = 5563 stats->stat_IfInFramesL2FilterDiscards; 5564 5565 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5566 5567 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5568 5569 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5570 5571 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5572 5573 sc->stat_CatchupInRuleCheckerDiscards = 5574 stats->stat_CatchupInRuleCheckerDiscards; 5575 5576 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5577 5578 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5579 5580 sc->stat_CatchupInRuleCheckerP4Hit = 5581 stats->stat_CatchupInRuleCheckerP4Hit; 5582 5583 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5584 } 5585 5586 void 5587 bnx_tick(void *xsc) 5588 { 5589 struct bnx_softc *sc = xsc; 5590 struct mii_data *mii; 5591 uint32_t msg; 5592 uint16_t prod, chain_prod; 5593 uint32_t prod_bseq; 5594 int s = splnet(); 5595 5596 /* Tell the firmware that the driver is still running. */ 5597 #ifdef BNX_DEBUG 5598 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5599 #else 5600 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5601 #endif 5602 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5603 5604 /* Update the statistics from the hardware statistics block. */ 5605 bnx_stats_update(sc); 5606 5607 /* Schedule the next tick. */ 5608 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5609 5610 mii = &sc->bnx_mii; 5611 mii_tick(mii); 5612 5613 /* try to get more RX buffers, just in case */ 5614 prod = sc->rx_prod; 5615 prod_bseq = sc->rx_prod_bseq; 5616 chain_prod = RX_CHAIN_IDX(prod); 5617 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5618 sc->rx_prod = prod; 5619 sc->rx_prod_bseq = prod_bseq; 5620 splx(s); 5621 return; 5622 } 5623 5624 /****************************************************************************/ 5625 /* BNX Debug Routines */ 5626 /****************************************************************************/ 5627 #ifdef BNX_DEBUG 5628 5629 /****************************************************************************/ 5630 /* Prints out information about an mbuf. */ 5631 /* */ 5632 /* Returns: */ 5633 /* Nothing. */ 5634 /****************************************************************************/ 5635 void 5636 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5637 { 5638 struct mbuf *mp = m; 5639 5640 if (m == NULL) { 5641 /* Index out of range. */ 5642 aprint_error("mbuf ptr is null!\n"); 5643 return; 5644 } 5645 5646 while (mp) { 5647 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5648 mp, mp->m_len); 5649 5650 if (mp->m_flags & M_EXT) 5651 aprint_debug("M_EXT "); 5652 if (mp->m_flags & M_PKTHDR) 5653 aprint_debug("M_PKTHDR "); 5654 aprint_debug("\n"); 5655 5656 if (mp->m_flags & M_EXT) 5657 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 5658 mp, mp->m_ext.ext_size); 5659 5660 mp = mp->m_next; 5661 } 5662 } 5663 5664 /****************************************************************************/ 5665 /* Prints out the mbufs in the TX mbuf chain. */ 5666 /* */ 5667 /* Returns: */ 5668 /* Nothing. */ 5669 /****************************************************************************/ 5670 void 5671 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5672 { 5673 #if 0 5674 struct mbuf *m; 5675 int i; 5676 5677 aprint_debug_dev(sc->bnx_dev, 5678 "----------------------------" 5679 " tx mbuf data " 5680 "----------------------------\n"); 5681 5682 for (i = 0; i < count; i++) { 5683 m = sc->tx_mbuf_ptr[chain_prod]; 5684 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5685 bnx_dump_mbuf(sc, m); 5686 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5687 } 5688 5689 aprint_debug_dev(sc->bnx_dev, 5690 "--------------------------------------------" 5691 "----------------------------\n"); 5692 #endif 5693 } 5694 5695 /* 5696 * This routine prints the RX mbuf chain. 5697 */ 5698 void 5699 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5700 { 5701 struct mbuf *m; 5702 int i; 5703 5704 aprint_debug_dev(sc->bnx_dev, 5705 "----------------------------" 5706 " rx mbuf data " 5707 "----------------------------\n"); 5708 5709 for (i = 0; i < count; i++) { 5710 m = sc->rx_mbuf_ptr[chain_prod]; 5711 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5712 bnx_dump_mbuf(sc, m); 5713 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5714 } 5715 5716 5717 aprint_debug_dev(sc->bnx_dev, 5718 "--------------------------------------------" 5719 "----------------------------\n"); 5720 } 5721 5722 void 5723 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5724 { 5725 if (idx > MAX_TX_BD) 5726 /* Index out of range. */ 5727 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5728 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5729 /* TX Chain page pointer. */ 5730 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5731 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5732 txbd->tx_bd_haddr_lo); 5733 else 5734 /* Normal tx_bd entry. */ 5735 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5736 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5737 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5738 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5739 txbd->tx_bd_flags); 5740 } 5741 5742 void 5743 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5744 { 5745 if (idx > MAX_RX_BD) 5746 /* Index out of range. */ 5747 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5748 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5749 /* TX Chain page pointer. */ 5750 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5751 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5752 rxbd->rx_bd_haddr_lo); 5753 else 5754 /* Normal tx_bd entry. */ 5755 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5756 "0x%08X, flags = 0x%08X\n", idx, 5757 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5758 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5759 } 5760 5761 void 5762 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5763 { 5764 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5765 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5766 "tcp_udp_xsum = 0x%04X\n", idx, 5767 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5768 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5769 l2fhdr->l2_fhdr_tcp_udp_xsum); 5770 } 5771 5772 /* 5773 * This routine prints the TX chain. 5774 */ 5775 void 5776 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5777 { 5778 struct tx_bd *txbd; 5779 int i; 5780 5781 /* First some info about the tx_bd chain structure. */ 5782 aprint_debug_dev(sc->bnx_dev, 5783 "----------------------------" 5784 " tx_bd chain " 5785 "----------------------------\n"); 5786 5787 BNX_PRINTF(sc, 5788 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5789 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 5790 5791 BNX_PRINTF(sc, 5792 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5793 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 5794 5795 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5796 5797 aprint_error_dev(sc->bnx_dev, "" 5798 "-----------------------------" 5799 " tx_bd data " 5800 "-----------------------------\n"); 5801 5802 /* Now print out the tx_bd's themselves. */ 5803 for (i = 0; i < count; i++) { 5804 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5805 bnx_dump_txbd(sc, tx_prod, txbd); 5806 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5807 } 5808 5809 aprint_debug_dev(sc->bnx_dev, 5810 "-----------------------------" 5811 "--------------" 5812 "-----------------------------\n"); 5813 } 5814 5815 /* 5816 * This routine prints the RX chain. 5817 */ 5818 void 5819 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5820 { 5821 struct rx_bd *rxbd; 5822 int i; 5823 5824 /* First some info about the tx_bd chain structure. */ 5825 aprint_debug_dev(sc->bnx_dev, 5826 "----------------------------" 5827 " rx_bd chain " 5828 "----------------------------\n"); 5829 5830 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5831 5832 BNX_PRINTF(sc, 5833 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5834 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 5835 5836 BNX_PRINTF(sc, 5837 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5838 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 5839 5840 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5841 5842 aprint_error_dev(sc->bnx_dev, 5843 "----------------------------" 5844 " rx_bd data " 5845 "----------------------------\n"); 5846 5847 /* Now print out the rx_bd's themselves. */ 5848 for (i = 0; i < count; i++) { 5849 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5850 bnx_dump_rxbd(sc, rx_prod, rxbd); 5851 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5852 } 5853 5854 aprint_debug_dev(sc->bnx_dev, 5855 "----------------------------" 5856 "--------------" 5857 "----------------------------\n"); 5858 } 5859 5860 /* 5861 * This routine prints the status block. 5862 */ 5863 void 5864 bnx_dump_status_block(struct bnx_softc *sc) 5865 { 5866 struct status_block *sblk; 5867 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5868 BUS_DMASYNC_POSTREAD); 5869 5870 sblk = sc->status_block; 5871 5872 aprint_debug_dev(sc->bnx_dev, "----------------------------- Status Block " 5873 "-----------------------------\n"); 5874 5875 BNX_PRINTF(sc, 5876 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5877 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5878 sblk->status_idx); 5879 5880 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5881 sblk->status_rx_quick_consumer_index0, 5882 sblk->status_tx_quick_consumer_index0); 5883 5884 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5885 5886 /* Theses indices are not used for normal L2 drivers. */ 5887 if (sblk->status_rx_quick_consumer_index1 || 5888 sblk->status_tx_quick_consumer_index1) 5889 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5890 sblk->status_rx_quick_consumer_index1, 5891 sblk->status_tx_quick_consumer_index1); 5892 5893 if (sblk->status_rx_quick_consumer_index2 || 5894 sblk->status_tx_quick_consumer_index2) 5895 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5896 sblk->status_rx_quick_consumer_index2, 5897 sblk->status_tx_quick_consumer_index2); 5898 5899 if (sblk->status_rx_quick_consumer_index3 || 5900 sblk->status_tx_quick_consumer_index3) 5901 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5902 sblk->status_rx_quick_consumer_index3, 5903 sblk->status_tx_quick_consumer_index3); 5904 5905 if (sblk->status_rx_quick_consumer_index4 || 5906 sblk->status_rx_quick_consumer_index5) 5907 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5908 sblk->status_rx_quick_consumer_index4, 5909 sblk->status_rx_quick_consumer_index5); 5910 5911 if (sblk->status_rx_quick_consumer_index6 || 5912 sblk->status_rx_quick_consumer_index7) 5913 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5914 sblk->status_rx_quick_consumer_index6, 5915 sblk->status_rx_quick_consumer_index7); 5916 5917 if (sblk->status_rx_quick_consumer_index8 || 5918 sblk->status_rx_quick_consumer_index9) 5919 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5920 sblk->status_rx_quick_consumer_index8, 5921 sblk->status_rx_quick_consumer_index9); 5922 5923 if (sblk->status_rx_quick_consumer_index10 || 5924 sblk->status_rx_quick_consumer_index11) 5925 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 5926 sblk->status_rx_quick_consumer_index10, 5927 sblk->status_rx_quick_consumer_index11); 5928 5929 if (sblk->status_rx_quick_consumer_index12 || 5930 sblk->status_rx_quick_consumer_index13) 5931 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 5932 sblk->status_rx_quick_consumer_index12, 5933 sblk->status_rx_quick_consumer_index13); 5934 5935 if (sblk->status_rx_quick_consumer_index14 || 5936 sblk->status_rx_quick_consumer_index15) 5937 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 5938 sblk->status_rx_quick_consumer_index14, 5939 sblk->status_rx_quick_consumer_index15); 5940 5941 if (sblk->status_completion_producer_index || 5942 sblk->status_cmd_consumer_index) 5943 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 5944 sblk->status_completion_producer_index, 5945 sblk->status_cmd_consumer_index); 5946 5947 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 5948 "-----------------------------\n"); 5949 } 5950 5951 /* 5952 * This routine prints the statistics block. 5953 */ 5954 void 5955 bnx_dump_stats_block(struct bnx_softc *sc) 5956 { 5957 struct statistics_block *sblk; 5958 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5959 BUS_DMASYNC_POSTREAD); 5960 5961 sblk = sc->stats_block; 5962 5963 aprint_debug_dev(sc->bnx_dev, "" 5964 "-----------------------------" 5965 " Stats Block " 5966 "-----------------------------\n"); 5967 5968 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 5969 "IfHcInBadOctets = 0x%08X:%08X\n", 5970 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 5971 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 5972 5973 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 5974 "IfHcOutBadOctets = 0x%08X:%08X\n", 5975 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 5976 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 5977 5978 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 5979 "IfHcInMulticastPkts = 0x%08X:%08X\n", 5980 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 5981 sblk->stat_IfHCInMulticastPkts_hi, 5982 sblk->stat_IfHCInMulticastPkts_lo); 5983 5984 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 5985 "IfHcOutUcastPkts = 0x%08X:%08X\n", 5986 sblk->stat_IfHCInBroadcastPkts_hi, 5987 sblk->stat_IfHCInBroadcastPkts_lo, 5988 sblk->stat_IfHCOutUcastPkts_hi, 5989 sblk->stat_IfHCOutUcastPkts_lo); 5990 5991 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 5992 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 5993 sblk->stat_IfHCOutMulticastPkts_hi, 5994 sblk->stat_IfHCOutMulticastPkts_lo, 5995 sblk->stat_IfHCOutBroadcastPkts_hi, 5996 sblk->stat_IfHCOutBroadcastPkts_lo); 5997 5998 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 5999 BNX_PRINTF(sc, "0x%08X : " 6000 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6001 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6002 6003 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6004 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6005 sblk->stat_Dot3StatsCarrierSenseErrors); 6006 6007 if (sblk->stat_Dot3StatsFCSErrors) 6008 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6009 sblk->stat_Dot3StatsFCSErrors); 6010 6011 if (sblk->stat_Dot3StatsAlignmentErrors) 6012 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6013 sblk->stat_Dot3StatsAlignmentErrors); 6014 6015 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6016 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6017 sblk->stat_Dot3StatsSingleCollisionFrames); 6018 6019 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6020 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6021 sblk->stat_Dot3StatsMultipleCollisionFrames); 6022 6023 if (sblk->stat_Dot3StatsDeferredTransmissions) 6024 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6025 sblk->stat_Dot3StatsDeferredTransmissions); 6026 6027 if (sblk->stat_Dot3StatsExcessiveCollisions) 6028 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6029 sblk->stat_Dot3StatsExcessiveCollisions); 6030 6031 if (sblk->stat_Dot3StatsLateCollisions) 6032 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6033 sblk->stat_Dot3StatsLateCollisions); 6034 6035 if (sblk->stat_EtherStatsCollisions) 6036 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6037 sblk->stat_EtherStatsCollisions); 6038 6039 if (sblk->stat_EtherStatsFragments) 6040 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6041 sblk->stat_EtherStatsFragments); 6042 6043 if (sblk->stat_EtherStatsJabbers) 6044 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6045 sblk->stat_EtherStatsJabbers); 6046 6047 if (sblk->stat_EtherStatsUndersizePkts) 6048 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6049 sblk->stat_EtherStatsUndersizePkts); 6050 6051 if (sblk->stat_EtherStatsOverrsizePkts) 6052 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6053 sblk->stat_EtherStatsOverrsizePkts); 6054 6055 if (sblk->stat_EtherStatsPktsRx64Octets) 6056 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6057 sblk->stat_EtherStatsPktsRx64Octets); 6058 6059 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6060 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6061 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6062 6063 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6064 BNX_PRINTF(sc, "0x%08X : " 6065 "EtherStatsPktsRx128Octetsto255Octets\n", 6066 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6067 6068 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6069 BNX_PRINTF(sc, "0x%08X : " 6070 "EtherStatsPktsRx256Octetsto511Octets\n", 6071 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6072 6073 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6074 BNX_PRINTF(sc, "0x%08X : " 6075 "EtherStatsPktsRx512Octetsto1023Octets\n", 6076 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6077 6078 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6079 BNX_PRINTF(sc, "0x%08X : " 6080 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6081 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6082 6083 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6084 BNX_PRINTF(sc, "0x%08X : " 6085 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6086 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6087 6088 if (sblk->stat_EtherStatsPktsTx64Octets) 6089 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6090 sblk->stat_EtherStatsPktsTx64Octets); 6091 6092 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6093 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6094 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6095 6096 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6097 BNX_PRINTF(sc, "0x%08X : " 6098 "EtherStatsPktsTx128Octetsto255Octets\n", 6099 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6100 6101 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6102 BNX_PRINTF(sc, "0x%08X : " 6103 "EtherStatsPktsTx256Octetsto511Octets\n", 6104 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6105 6106 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6107 BNX_PRINTF(sc, "0x%08X : " 6108 "EtherStatsPktsTx512Octetsto1023Octets\n", 6109 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6110 6111 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6112 BNX_PRINTF(sc, "0x%08X : " 6113 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6114 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6115 6116 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6117 BNX_PRINTF(sc, "0x%08X : " 6118 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6119 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6120 6121 if (sblk->stat_XonPauseFramesReceived) 6122 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6123 sblk->stat_XonPauseFramesReceived); 6124 6125 if (sblk->stat_XoffPauseFramesReceived) 6126 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6127 sblk->stat_XoffPauseFramesReceived); 6128 6129 if (sblk->stat_OutXonSent) 6130 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6131 sblk->stat_OutXonSent); 6132 6133 if (sblk->stat_OutXoffSent) 6134 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6135 sblk->stat_OutXoffSent); 6136 6137 if (sblk->stat_FlowControlDone) 6138 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6139 sblk->stat_FlowControlDone); 6140 6141 if (sblk->stat_MacControlFramesReceived) 6142 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6143 sblk->stat_MacControlFramesReceived); 6144 6145 if (sblk->stat_XoffStateEntered) 6146 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6147 sblk->stat_XoffStateEntered); 6148 6149 if (sblk->stat_IfInFramesL2FilterDiscards) 6150 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6151 sblk->stat_IfInFramesL2FilterDiscards); 6152 6153 if (sblk->stat_IfInRuleCheckerDiscards) 6154 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6155 sblk->stat_IfInRuleCheckerDiscards); 6156 6157 if (sblk->stat_IfInFTQDiscards) 6158 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6159 sblk->stat_IfInFTQDiscards); 6160 6161 if (sblk->stat_IfInMBUFDiscards) 6162 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6163 sblk->stat_IfInMBUFDiscards); 6164 6165 if (sblk->stat_IfInRuleCheckerP4Hit) 6166 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6167 sblk->stat_IfInRuleCheckerP4Hit); 6168 6169 if (sblk->stat_CatchupInRuleCheckerDiscards) 6170 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6171 sblk->stat_CatchupInRuleCheckerDiscards); 6172 6173 if (sblk->stat_CatchupInFTQDiscards) 6174 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6175 sblk->stat_CatchupInFTQDiscards); 6176 6177 if (sblk->stat_CatchupInMBUFDiscards) 6178 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6179 sblk->stat_CatchupInMBUFDiscards); 6180 6181 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6182 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6183 sblk->stat_CatchupInRuleCheckerP4Hit); 6184 6185 aprint_debug_dev(sc->bnx_dev, 6186 "-----------------------------" 6187 "--------------" 6188 "-----------------------------\n"); 6189 } 6190 6191 void 6192 bnx_dump_driver_state(struct bnx_softc *sc) 6193 { 6194 aprint_debug_dev(sc->bnx_dev, 6195 "-----------------------------" 6196 " Driver State " 6197 "-----------------------------\n"); 6198 6199 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6200 "address\n", sc); 6201 6202 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6203 sc->status_block); 6204 6205 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6206 "address\n", sc->stats_block); 6207 6208 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6209 "adddress\n", sc->tx_bd_chain); 6210 6211 #if 0 6212 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6213 sc->rx_bd_chain); 6214 6215 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6216 sc->tx_mbuf_ptr); 6217 #endif 6218 6219 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6220 sc->rx_mbuf_ptr); 6221 6222 BNX_PRINTF(sc, 6223 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6224 sc->interrupts_generated); 6225 6226 BNX_PRINTF(sc, 6227 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6228 sc->rx_interrupts); 6229 6230 BNX_PRINTF(sc, 6231 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6232 sc->tx_interrupts); 6233 6234 BNX_PRINTF(sc, 6235 " 0x%08X - (sc->last_status_idx) status block index\n", 6236 sc->last_status_idx); 6237 6238 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6239 sc->tx_prod); 6240 6241 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6242 sc->tx_cons); 6243 6244 BNX_PRINTF(sc, 6245 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6246 sc->tx_prod_bseq); 6247 BNX_PRINTF(sc, 6248 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6249 sc->tx_mbuf_alloc); 6250 6251 BNX_PRINTF(sc, 6252 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6253 sc->used_tx_bd); 6254 6255 BNX_PRINTF(sc, 6256 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6257 sc->tx_hi_watermark, sc->max_tx_bd); 6258 6259 6260 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6261 sc->rx_prod); 6262 6263 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6264 sc->rx_cons); 6265 6266 BNX_PRINTF(sc, 6267 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6268 sc->rx_prod_bseq); 6269 6270 BNX_PRINTF(sc, 6271 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6272 sc->rx_mbuf_alloc); 6273 6274 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6275 sc->free_rx_bd); 6276 6277 BNX_PRINTF(sc, 6278 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6279 sc->rx_low_watermark, sc->max_rx_bd); 6280 6281 BNX_PRINTF(sc, 6282 " 0x%08X - (sc->mbuf_alloc_failed) " 6283 "mbuf alloc failures\n", 6284 sc->mbuf_alloc_failed); 6285 6286 BNX_PRINTF(sc, 6287 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6288 "simulated mbuf alloc failures\n", 6289 sc->mbuf_sim_alloc_failed); 6290 6291 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6292 "-----------------------------\n"); 6293 } 6294 6295 void 6296 bnx_dump_hw_state(struct bnx_softc *sc) 6297 { 6298 uint32_t val1; 6299 int i; 6300 6301 aprint_debug_dev(sc->bnx_dev, 6302 "----------------------------" 6303 " Hardware State " 6304 "----------------------------\n"); 6305 6306 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6307 6308 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6309 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6310 val1, BNX_MISC_ENABLE_STATUS_BITS); 6311 6312 val1 = REG_RD(sc, BNX_DMA_STATUS); 6313 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6314 6315 val1 = REG_RD(sc, BNX_CTX_STATUS); 6316 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6317 6318 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6319 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6320 BNX_EMAC_STATUS); 6321 6322 val1 = REG_RD(sc, BNX_RPM_STATUS); 6323 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6324 6325 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6326 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6327 BNX_TBDR_STATUS); 6328 6329 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6330 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6331 BNX_TDMA_STATUS); 6332 6333 val1 = REG_RD(sc, BNX_HC_STATUS); 6334 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6335 6336 aprint_debug_dev(sc->bnx_dev, 6337 "----------------------------" 6338 "----------------" 6339 "----------------------------\n"); 6340 6341 aprint_debug_dev(sc->bnx_dev, 6342 "----------------------------" 6343 " Register Dump " 6344 "----------------------------\n"); 6345 6346 for (i = 0x400; i < 0x8000; i += 0x10) 6347 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6348 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6349 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6350 6351 aprint_debug_dev(sc->bnx_dev, 6352 "----------------------------" 6353 "----------------" 6354 "----------------------------\n"); 6355 } 6356 6357 void 6358 bnx_breakpoint(struct bnx_softc *sc) 6359 { 6360 /* Unreachable code to shut the compiler up about unused functions. */ 6361 if (0) { 6362 bnx_dump_txbd(sc, 0, NULL); 6363 bnx_dump_rxbd(sc, 0, NULL); 6364 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6365 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6366 bnx_dump_l2fhdr(sc, 0, NULL); 6367 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6368 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6369 bnx_dump_status_block(sc); 6370 bnx_dump_stats_block(sc); 6371 bnx_dump_driver_state(sc); 6372 bnx_dump_hw_state(sc); 6373 } 6374 6375 bnx_dump_driver_state(sc); 6376 /* Print the important status block fields. */ 6377 bnx_dump_status_block(sc); 6378 6379 #if 0 6380 /* Call the debugger. */ 6381 breakpoint(); 6382 #endif 6383 6384 return; 6385 } 6386 #endif 6387
Indexes created Wed Sep 24 05:09:52 GMT 2025