if_bnx.c revision 1.60
1 /* $NetBSD: if_bnx.c,v 1.60 2016/12/08 01:12:01 ozaki-r Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.60 2016/12/08 01:12:01 ozaki-r Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 /****************************************************************************/ 180 /* Supported Flash NVRAM device data. */ 181 /****************************************************************************/ 182 static struct flash_spec flash_table[] = 183 { 184 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 185 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 186 /* Slow EEPROM */ 187 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 188 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 189 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 190 "EEPROM - slow"}, 191 /* Expansion entry 0001 */ 192 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0001"}, 196 /* Saifun SA25F010 (non-buffered flash) */ 197 /* strap, cfg1, & write1 need updates */ 198 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 201 "Non-buffered flash (128kB)"}, 202 /* Saifun SA25F020 (non-buffered flash) */ 203 /* strap, cfg1, & write1 need updates */ 204 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 205 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 206 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 207 "Non-buffered flash (256kB)"}, 208 /* Expansion entry 0100 */ 209 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 210 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 211 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 212 "Entry 0100"}, 213 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 214 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 216 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 217 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 218 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 219 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 221 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 222 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 223 /* Saifun SA25F005 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 228 "Non-buffered flash (64kB)"}, 229 /* Fast EEPROM */ 230 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 231 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 232 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 233 "EEPROM - fast"}, 234 /* Expansion entry 1001 */ 235 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 236 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 237 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 238 "Entry 1001"}, 239 /* Expansion entry 1010 */ 240 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 241 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 242 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 243 "Entry 1010"}, 244 /* ATMEL AT45DB011B (buffered flash) */ 245 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 246 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 247 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 248 "Buffered flash (128kB)"}, 249 /* Expansion entry 1100 */ 250 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 251 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 252 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 253 "Entry 1100"}, 254 /* Expansion entry 1101 */ 255 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 256 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 257 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 258 "Entry 1101"}, 259 /* Ateml Expansion entry 1110 */ 260 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 261 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 262 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 263 "Entry 1110 (Atmel)"}, 264 /* ATMEL AT45DB021B (buffered flash) */ 265 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 266 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 267 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 268 "Buffered flash (256kB)"}, 269 }; 270 271 /* 272 * The BCM5709 controllers transparently handle the 273 * differences between Atmel 264 byte pages and all 274 * flash devices which use 256 byte pages, so no 275 * logical-to-physical mapping is required in the 276 * driver. 277 */ 278 static struct flash_spec flash_5709 = { 279 .flags = BNX_NV_BUFFERED, 280 .page_bits = BCM5709_FLASH_PAGE_BITS, 281 .page_size = BCM5709_FLASH_PAGE_SIZE, 282 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 283 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 284 .name = "5709 buffered flash (256kB)", 285 }; 286 287 /****************************************************************************/ 288 /* OpenBSD device entry points. */ 289 /****************************************************************************/ 290 static int bnx_probe(device_t, cfdata_t, void *); 291 void bnx_attach(device_t, device_t, void *); 292 int bnx_detach(device_t, int); 293 294 /****************************************************************************/ 295 /* BNX Debug Data Structure Dump Routines */ 296 /****************************************************************************/ 297 #ifdef BNX_DEBUG 298 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 299 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 300 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 302 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 303 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 304 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 305 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_status_block(struct bnx_softc *); 307 void bnx_dump_stats_block(struct bnx_softc *); 308 void bnx_dump_driver_state(struct bnx_softc *); 309 void bnx_dump_hw_state(struct bnx_softc *); 310 void bnx_breakpoint(struct bnx_softc *); 311 #endif 312 313 /****************************************************************************/ 314 /* BNX Register/Memory Access Routines */ 315 /****************************************************************************/ 316 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 317 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 318 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 319 int bnx_miibus_read_reg(device_t, int, int); 320 void bnx_miibus_write_reg(device_t, int, int, int); 321 void bnx_miibus_statchg(struct ifnet *); 322 323 /****************************************************************************/ 324 /* BNX NVRAM Access Routines */ 325 /****************************************************************************/ 326 int bnx_acquire_nvram_lock(struct bnx_softc *); 327 int bnx_release_nvram_lock(struct bnx_softc *); 328 void bnx_enable_nvram_access(struct bnx_softc *); 329 void bnx_disable_nvram_access(struct bnx_softc *); 330 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 331 uint32_t); 332 int bnx_init_nvram(struct bnx_softc *); 333 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 334 int bnx_nvram_test(struct bnx_softc *); 335 #ifdef BNX_NVRAM_WRITE_SUPPORT 336 int bnx_enable_nvram_write(struct bnx_softc *); 337 void bnx_disable_nvram_write(struct bnx_softc *); 338 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 339 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 340 uint32_t); 341 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 342 #endif 343 344 /****************************************************************************/ 345 /* */ 346 /****************************************************************************/ 347 void bnx_get_media(struct bnx_softc *); 348 void bnx_init_media(struct bnx_softc *); 349 int bnx_dma_alloc(struct bnx_softc *); 350 void bnx_dma_free(struct bnx_softc *); 351 void bnx_release_resources(struct bnx_softc *); 352 353 /****************************************************************************/ 354 /* BNX Firmware Synchronization and Load */ 355 /****************************************************************************/ 356 int bnx_fw_sync(struct bnx_softc *, uint32_t); 357 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, 358 uint32_t); 359 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 360 struct fw_info *); 361 void bnx_init_cpus(struct bnx_softc *); 362 363 static void bnx_print_adapter_info(struct bnx_softc *); 364 static void bnx_probe_pci_caps(struct bnx_softc *); 365 void bnx_stop(struct ifnet *, int); 366 int bnx_reset(struct bnx_softc *, uint32_t); 367 int bnx_chipinit(struct bnx_softc *); 368 int bnx_blockinit(struct bnx_softc *); 369 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 370 uint16_t *, uint32_t *); 371 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 372 373 int bnx_init_tx_chain(struct bnx_softc *); 374 void bnx_init_tx_context(struct bnx_softc *); 375 int bnx_init_rx_chain(struct bnx_softc *); 376 void bnx_init_rx_context(struct bnx_softc *); 377 void bnx_free_rx_chain(struct bnx_softc *); 378 void bnx_free_tx_chain(struct bnx_softc *); 379 380 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 381 void bnx_start(struct ifnet *); 382 int bnx_ioctl(struct ifnet *, u_long, void *); 383 void bnx_watchdog(struct ifnet *); 384 int bnx_init(struct ifnet *); 385 386 void bnx_init_context(struct bnx_softc *); 387 void bnx_get_mac_addr(struct bnx_softc *); 388 void bnx_set_mac_addr(struct bnx_softc *); 389 void bnx_phy_intr(struct bnx_softc *); 390 void bnx_rx_intr(struct bnx_softc *); 391 void bnx_tx_intr(struct bnx_softc *); 392 void bnx_disable_intr(struct bnx_softc *); 393 void bnx_enable_intr(struct bnx_softc *); 394 395 int bnx_intr(void *); 396 void bnx_iff(struct bnx_softc *); 397 void bnx_stats_update(struct bnx_softc *); 398 void bnx_tick(void *); 399 400 struct pool *bnx_tx_pool = NULL; 401 void bnx_alloc_pkts(struct work *, void *); 402 403 /****************************************************************************/ 404 /* OpenBSD device dispatch table. */ 405 /****************************************************************************/ 406 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 407 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 408 409 /****************************************************************************/ 410 /* Device probe function. */ 411 /* */ 412 /* Compares the device to the driver's list of supported devices and */ 413 /* reports back to the OS whether this is the right driver for the device. */ 414 /* */ 415 /* Returns: */ 416 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 417 /****************************************************************************/ 418 static const struct bnx_product * 419 bnx_lookup(const struct pci_attach_args *pa) 420 { 421 int i; 422 pcireg_t subid; 423 424 for (i = 0; i < __arraycount(bnx_devices); i++) { 425 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 426 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 427 continue; 428 if (!bnx_devices[i].bp_subvendor) 429 return &bnx_devices[i]; 430 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 431 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 432 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 433 return &bnx_devices[i]; 434 } 435 436 return NULL; 437 } 438 static int 439 bnx_probe(device_t parent, cfdata_t match, void *aux) 440 { 441 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 442 443 if (bnx_lookup(pa) != NULL) 444 return 1; 445 446 return 0; 447 } 448 449 /****************************************************************************/ 450 /* PCI Capabilities Probe Function. */ 451 /* */ 452 /* Walks the PCI capabiites list for the device to find what features are */ 453 /* supported. */ 454 /* */ 455 /* Returns: */ 456 /* None. */ 457 /****************************************************************************/ 458 static void 459 bnx_print_adapter_info(struct bnx_softc *sc) 460 { 461 462 aprint_normal_dev(sc->bnx_dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 463 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 464 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 465 ? "Serdes " : "", sc->bnx_chipid); 466 467 /* Bus info. */ 468 if (sc->bnx_flags & BNX_PCIE_FLAG) { 469 aprint_normal_dev(sc->bnx_dev, "PCIe x%d ", 470 sc->link_width); 471 switch (sc->link_speed) { 472 case 1: aprint_normal("2.5Gbps\n"); break; 473 case 2: aprint_normal("5Gbps\n"); break; 474 default: aprint_normal("Unknown link speed\n"); 475 } 476 } else { 477 aprint_normal_dev(sc->bnx_dev, "PCI%s %dbit %dMHz\n", 478 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 479 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 480 sc->bus_speed_mhz); 481 } 482 483 aprint_normal_dev(sc->bnx_dev, 484 "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 485 sc->bnx_rx_quick_cons_trip_int, 486 sc->bnx_rx_quick_cons_trip, 487 sc->bnx_rx_ticks_int, 488 sc->bnx_rx_ticks, 489 sc->bnx_tx_quick_cons_trip_int, 490 sc->bnx_tx_quick_cons_trip, 491 sc->bnx_tx_ticks_int, 492 sc->bnx_tx_ticks); 493 } 494 495 496 /****************************************************************************/ 497 /* PCI Capabilities Probe Function. */ 498 /* */ 499 /* Walks the PCI capabiites list for the device to find what features are */ 500 /* supported. */ 501 /* */ 502 /* Returns: */ 503 /* None. */ 504 /****************************************************************************/ 505 static void 506 bnx_probe_pci_caps(struct bnx_softc *sc) 507 { 508 struct pci_attach_args *pa = &(sc->bnx_pa); 509 pcireg_t reg; 510 511 /* Check if PCI-X capability is enabled. */ 512 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 513 NULL) != 0) { 514 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 515 } 516 517 /* Check if PCIe capability is enabled. */ 518 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 519 NULL) != 0) { 520 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 521 reg + PCIE_LCSR); 522 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 523 "0x%08X\n", link_status); 524 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 525 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 526 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 527 sc->bnx_flags |= BNX_PCIE_FLAG; 528 } 529 530 /* Check if MSI capability is enabled. */ 531 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 532 NULL) != 0) 533 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 534 535 /* Check if MSI-X capability is enabled. */ 536 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 537 NULL) != 0) 538 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 539 } 540 541 542 /****************************************************************************/ 543 /* Device attach function. */ 544 /* */ 545 /* Allocates device resources, performs secondary chip identification, */ 546 /* resets and initializes the hardware, and initializes driver instance */ 547 /* variables. */ 548 /* */ 549 /* Returns: */ 550 /* 0 on success, positive value on failure. */ 551 /****************************************************************************/ 552 void 553 bnx_attach(device_t parent, device_t self, void *aux) 554 { 555 const struct bnx_product *bp; 556 struct bnx_softc *sc = device_private(self); 557 prop_dictionary_t dict; 558 struct pci_attach_args *pa = aux; 559 pci_chipset_tag_t pc = pa->pa_pc; 560 pci_intr_handle_t ih; 561 const char *intrstr = NULL; 562 uint32_t command; 563 struct ifnet *ifp; 564 uint32_t val; 565 int mii_flags = MIIF_FORCEANEG; 566 pcireg_t memtype; 567 char intrbuf[PCI_INTRSTR_LEN]; 568 569 if (bnx_tx_pool == NULL) { 570 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 571 if (bnx_tx_pool != NULL) { 572 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 573 0, 0, 0, "bnxpkts", NULL, IPL_NET); 574 } else { 575 aprint_error(": can't alloc bnx_tx_pool\n"); 576 return; 577 } 578 } 579 580 bp = bnx_lookup(pa); 581 if (bp == NULL) 582 panic("unknown device"); 583 584 sc->bnx_dev = self; 585 586 aprint_naive("\n"); 587 aprint_normal(": %s\n", bp->bp_name); 588 589 sc->bnx_pa = *pa; 590 591 /* 592 * Map control/status registers. 593 */ 594 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 595 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 596 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 597 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 598 599 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 600 aprint_error_dev(sc->bnx_dev, 601 "failed to enable memory mapping!\n"); 602 return; 603 } 604 605 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 606 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 607 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 608 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 609 return; 610 } 611 612 if (pci_intr_map(pa, &ih)) { 613 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 614 goto bnx_attach_fail; 615 } 616 617 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 618 619 /* 620 * Configure byte swap and enable indirect register access. 621 * Rely on CPU to do target byte swapping on big endian systems. 622 * Access to registers outside of PCI configurtion space are not 623 * valid until this is done. 624 */ 625 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 626 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 627 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 628 629 /* Save ASIC revsion info. */ 630 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 631 632 /* 633 * Find the base address for shared memory access. 634 * Newer versions of bootcode use a signature and offset 635 * while older versions use a fixed address. 636 */ 637 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 638 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 639 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 640 (sc->bnx_pa.pa_function << 2)); 641 else 642 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 643 644 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 645 646 /* Set initial device and PHY flags */ 647 sc->bnx_flags = 0; 648 sc->bnx_phy_flags = 0; 649 650 bnx_probe_pci_caps(sc); 651 652 /* Get PCI bus information (speed and type). */ 653 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 654 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 655 uint32_t clkreg; 656 657 sc->bnx_flags |= BNX_PCIX_FLAG; 658 659 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 660 661 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 662 switch (clkreg) { 663 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 664 sc->bus_speed_mhz = 133; 665 break; 666 667 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 668 sc->bus_speed_mhz = 100; 669 break; 670 671 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 672 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 673 sc->bus_speed_mhz = 66; 674 break; 675 676 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 677 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 678 sc->bus_speed_mhz = 50; 679 break; 680 681 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 682 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 683 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 684 sc->bus_speed_mhz = 33; 685 break; 686 } 687 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 688 sc->bus_speed_mhz = 66; 689 else 690 sc->bus_speed_mhz = 33; 691 692 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 693 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 694 695 /* Reset the controller. */ 696 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 697 goto bnx_attach_fail; 698 699 /* Initialize the controller. */ 700 if (bnx_chipinit(sc)) { 701 aprint_error_dev(sc->bnx_dev, 702 "Controller initialization failed!\n"); 703 goto bnx_attach_fail; 704 } 705 706 /* Perform NVRAM test. */ 707 if (bnx_nvram_test(sc)) { 708 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 709 goto bnx_attach_fail; 710 } 711 712 /* Fetch the permanent Ethernet MAC address. */ 713 bnx_get_mac_addr(sc); 714 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 715 ether_sprintf(sc->eaddr)); 716 717 /* 718 * Trip points control how many BDs 719 * should be ready before generating an 720 * interrupt while ticks control how long 721 * a BD can sit in the chain before 722 * generating an interrupt. Set the default 723 * values for the RX and TX rings. 724 */ 725 726 #ifdef BNX_DEBUG 727 /* Force more frequent interrupts. */ 728 sc->bnx_tx_quick_cons_trip_int = 1; 729 sc->bnx_tx_quick_cons_trip = 1; 730 sc->bnx_tx_ticks_int = 0; 731 sc->bnx_tx_ticks = 0; 732 733 sc->bnx_rx_quick_cons_trip_int = 1; 734 sc->bnx_rx_quick_cons_trip = 1; 735 sc->bnx_rx_ticks_int = 0; 736 sc->bnx_rx_ticks = 0; 737 #else 738 sc->bnx_tx_quick_cons_trip_int = 20; 739 sc->bnx_tx_quick_cons_trip = 20; 740 sc->bnx_tx_ticks_int = 80; 741 sc->bnx_tx_ticks = 80; 742 743 sc->bnx_rx_quick_cons_trip_int = 6; 744 sc->bnx_rx_quick_cons_trip = 6; 745 sc->bnx_rx_ticks_int = 18; 746 sc->bnx_rx_ticks = 18; 747 #endif 748 749 /* Update statistics once every second. */ 750 sc->bnx_stats_ticks = 1000000 & 0xffff00; 751 752 /* Find the media type for the adapter. */ 753 bnx_get_media(sc); 754 755 /* 756 * Store config data needed by the PHY driver for 757 * backplane applications 758 */ 759 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 760 BNX_SHARED_HW_CFG_CONFIG); 761 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 762 BNX_PORT_HW_CFG_CONFIG); 763 764 /* Allocate DMA memory resources. */ 765 sc->bnx_dmatag = pa->pa_dmat; 766 if (bnx_dma_alloc(sc)) { 767 aprint_error_dev(sc->bnx_dev, 768 "DMA resource allocation failed!\n"); 769 goto bnx_attach_fail; 770 } 771 772 /* Initialize the ifnet interface. */ 773 ifp = &sc->bnx_ec.ec_if; 774 ifp->if_softc = sc; 775 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 776 ifp->if_ioctl = bnx_ioctl; 777 ifp->if_stop = bnx_stop; 778 ifp->if_start = bnx_start; 779 ifp->if_init = bnx_init; 780 ifp->if_timer = 0; 781 ifp->if_watchdog = bnx_watchdog; 782 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 783 IFQ_SET_READY(&ifp->if_snd); 784 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 785 786 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 787 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 788 789 ifp->if_capabilities |= 790 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 791 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 792 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 793 794 /* Hookup IRQ last. */ 795 sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); 796 if (sc->bnx_intrhand == NULL) { 797 aprint_error_dev(self, "couldn't establish interrupt"); 798 if (intrstr != NULL) 799 aprint_error(" at %s", intrstr); 800 aprint_error("\n"); 801 goto bnx_attach_fail; 802 } 803 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 804 805 /* create workqueue to handle packet allocations */ 806 if (workqueue_create(&sc->bnx_wq, device_xname(self), 807 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 808 aprint_error_dev(self, "failed to create workqueue\n"); 809 goto bnx_attach_fail; 810 } 811 812 sc->bnx_mii.mii_ifp = ifp; 813 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 814 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 815 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 816 817 /* Handle any special PHY initialization for SerDes PHYs. */ 818 bnx_init_media(sc); 819 820 sc->bnx_ec.ec_mii = &sc->bnx_mii; 821 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 822 ether_mediastatus); 823 824 /* set phyflags and chipid before mii_attach() */ 825 dict = device_properties(self); 826 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 827 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 828 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 829 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 830 831 /* Print some useful adapter info */ 832 bnx_print_adapter_info(sc); 833 834 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 835 mii_flags |= MIIF_HAVEFIBER; 836 mii_attach(self, &sc->bnx_mii, 0xffffffff, 837 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 838 839 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 840 aprint_error_dev(self, "no PHY found!\n"); 841 ifmedia_add(&sc->bnx_mii.mii_media, 842 IFM_ETHER|IFM_MANUAL, 0, NULL); 843 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_MANUAL); 844 } else 845 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_AUTO); 846 847 /* Attach to the Ethernet interface list. */ 848 if_attach(ifp); 849 if_deferred_start_init(ifp, NULL); 850 ether_ifattach(ifp,sc->eaddr); 851 852 callout_init(&sc->bnx_timeout, 0); 853 854 if (pmf_device_register(self, NULL, NULL)) 855 pmf_class_network_register(self, ifp); 856 else 857 aprint_error_dev(self, "couldn't establish power handler\n"); 858 859 /* Print some important debugging info. */ 860 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 861 862 goto bnx_attach_exit; 863 864 bnx_attach_fail: 865 bnx_release_resources(sc); 866 867 bnx_attach_exit: 868 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 869 } 870 871 /****************************************************************************/ 872 /* Device detach function. */ 873 /* */ 874 /* Stops the controller, resets the controller, and releases resources. */ 875 /* */ 876 /* Returns: */ 877 /* 0 on success, positive value on failure. */ 878 /****************************************************************************/ 879 int 880 bnx_detach(device_t dev, int flags) 881 { 882 int s; 883 struct bnx_softc *sc; 884 struct ifnet *ifp; 885 886 sc = device_private(dev); 887 ifp = &sc->bnx_ec.ec_if; 888 889 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 890 891 /* Stop and reset the controller. */ 892 s = splnet(); 893 if (ifp->if_flags & IFF_RUNNING) 894 bnx_stop(ifp, 1); 895 else { 896 /* Disable the transmit/receive blocks. */ 897 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 898 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 899 DELAY(20); 900 bnx_disable_intr(sc); 901 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 902 } 903 904 splx(s); 905 906 pmf_device_deregister(dev); 907 callout_destroy(&sc->bnx_timeout); 908 ether_ifdetach(ifp); 909 workqueue_destroy(sc->bnx_wq); 910 911 /* Delete all remaining media. */ 912 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 913 914 if_detach(ifp); 915 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 916 917 /* Release all remaining resources. */ 918 bnx_release_resources(sc); 919 920 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 921 922 return 0; 923 } 924 925 /****************************************************************************/ 926 /* Indirect register read. */ 927 /* */ 928 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 929 /* configuration space. Using this mechanism avoids issues with posted */ 930 /* reads but is much slower than memory-mapped I/O. */ 931 /* */ 932 /* Returns: */ 933 /* The value of the register. */ 934 /****************************************************************************/ 935 uint32_t 936 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 937 { 938 struct pci_attach_args *pa = &(sc->bnx_pa); 939 940 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 941 offset); 942 #ifdef BNX_DEBUG 943 { 944 uint32_t val; 945 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 946 BNX_PCICFG_REG_WINDOW); 947 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 948 "val = 0x%08X\n", __func__, offset, val); 949 return val; 950 } 951 #else 952 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 953 #endif 954 } 955 956 /****************************************************************************/ 957 /* Indirect register write. */ 958 /* */ 959 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 960 /* configuration space. Using this mechanism avoids issues with posted */ 961 /* writes but is muchh slower than memory-mapped I/O. */ 962 /* */ 963 /* Returns: */ 964 /* Nothing. */ 965 /****************************************************************************/ 966 void 967 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 968 { 969 struct pci_attach_args *pa = &(sc->bnx_pa); 970 971 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 972 __func__, offset, val); 973 974 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 975 offset); 976 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 977 } 978 979 /****************************************************************************/ 980 /* Context memory write. */ 981 /* */ 982 /* The NetXtreme II controller uses context memory to track connection */ 983 /* information for L2 and higher network protocols. */ 984 /* */ 985 /* Returns: */ 986 /* Nothing. */ 987 /****************************************************************************/ 988 void 989 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 990 uint32_t ctx_val) 991 { 992 uint32_t idx, offset = ctx_offset + cid_addr; 993 uint32_t val, retry_cnt = 5; 994 995 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 996 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 997 REG_WR(sc, BNX_CTX_CTX_CTRL, 998 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 999 1000 for (idx = 0; idx < retry_cnt; idx++) { 1001 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1002 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1003 break; 1004 DELAY(5); 1005 } 1006 1007 #if 0 1008 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1009 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1010 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1011 __FILE__, __LINE__, cid_addr, ctx_offset); 1012 #endif 1013 1014 } else { 1015 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1016 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1017 } 1018 } 1019 1020 /****************************************************************************/ 1021 /* PHY register read. */ 1022 /* */ 1023 /* Implements register reads on the MII bus. */ 1024 /* */ 1025 /* Returns: */ 1026 /* The value of the register. */ 1027 /****************************************************************************/ 1028 int 1029 bnx_miibus_read_reg(device_t dev, int phy, int reg) 1030 { 1031 struct bnx_softc *sc = device_private(dev); 1032 uint32_t val; 1033 int i; 1034 1035 /* Make sure we are accessing the correct PHY address. */ 1036 if (phy != sc->bnx_phy_addr) { 1037 DBPRINT(sc, BNX_VERBOSE, 1038 "Invalid PHY address %d for PHY read!\n", phy); 1039 return 0; 1040 } 1041 1042 /* 1043 * The BCM5709S PHY is an IEEE Clause 45 PHY 1044 * with special mappings to work with IEEE 1045 * Clause 22 register accesses. 1046 */ 1047 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1048 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1049 reg += 0x10; 1050 } 1051 1052 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1053 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1054 val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1055 1056 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 1057 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1058 1059 DELAY(40); 1060 } 1061 1062 val = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1063 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1064 BNX_EMAC_MDIO_COMM_START_BUSY; 1065 REG_WR(sc, BNX_EMAC_MDIO_COMM, val); 1066 1067 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1068 DELAY(10); 1069 1070 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1071 if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1072 DELAY(5); 1073 1074 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1075 val &= BNX_EMAC_MDIO_COMM_DATA; 1076 1077 break; 1078 } 1079 } 1080 1081 if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { 1082 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1083 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1084 val = 0x0; 1085 } else 1086 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1087 1088 DBPRINT(sc, BNX_EXCESSIVE, 1089 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 1090 (uint16_t) reg & 0xffff, (uint16_t) val & 0xffff); 1091 1092 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1093 val = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1094 val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1095 1096 REG_WR(sc, BNX_EMAC_MDIO_MODE, val); 1097 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1098 1099 DELAY(40); 1100 } 1101 1102 return (val & 0xffff); 1103 } 1104 1105 /****************************************************************************/ 1106 /* PHY register write. */ 1107 /* */ 1108 /* Implements register writes on the MII bus. */ 1109 /* */ 1110 /* Returns: */ 1111 /* The value of the register. */ 1112 /****************************************************************************/ 1113 void 1114 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 1115 { 1116 struct bnx_softc *sc = device_private(dev); 1117 uint32_t val1; 1118 int i; 1119 1120 /* Make sure we are accessing the correct PHY address. */ 1121 if (phy != sc->bnx_phy_addr) { 1122 DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", 1123 phy); 1124 return; 1125 } 1126 1127 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1128 "val = 0x%04X\n", __func__, 1129 phy, (uint16_t) reg & 0xffff, (uint16_t) val & 0xffff); 1130 1131 /* 1132 * The BCM5709S PHY is an IEEE Clause 45 PHY 1133 * with special mappings to work with IEEE 1134 * Clause 22 register accesses. 1135 */ 1136 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1137 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1138 reg += 0x10; 1139 } 1140 1141 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1142 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1143 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1144 1145 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1146 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1147 1148 DELAY(40); 1149 } 1150 1151 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1152 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1153 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1154 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1155 1156 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1157 DELAY(10); 1158 1159 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1160 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1161 DELAY(5); 1162 break; 1163 } 1164 } 1165 1166 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1167 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1168 __LINE__); 1169 } 1170 1171 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1172 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1173 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1174 1175 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1176 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1177 1178 DELAY(40); 1179 } 1180 } 1181 1182 /****************************************************************************/ 1183 /* MII bus status change. */ 1184 /* */ 1185 /* Called by the MII bus driver when the PHY establishes link to set the */ 1186 /* MAC interface registers. */ 1187 /* */ 1188 /* Returns: */ 1189 /* Nothing. */ 1190 /****************************************************************************/ 1191 void 1192 bnx_miibus_statchg(struct ifnet *ifp) 1193 { 1194 struct bnx_softc *sc = ifp->if_softc; 1195 struct mii_data *mii = &sc->bnx_mii; 1196 int val; 1197 1198 val = REG_RD(sc, BNX_EMAC_MODE); 1199 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1200 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1201 BNX_EMAC_MODE_25G); 1202 1203 /* Set MII or GMII interface based on the speed 1204 * negotiated by the PHY. 1205 */ 1206 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1207 case IFM_10_T: 1208 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1209 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1210 val |= BNX_EMAC_MODE_PORT_MII_10; 1211 break; 1212 } 1213 /* FALLTHROUGH */ 1214 case IFM_100_TX: 1215 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1216 val |= BNX_EMAC_MODE_PORT_MII; 1217 break; 1218 case IFM_2500_SX: 1219 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1220 val |= BNX_EMAC_MODE_25G; 1221 /* FALLTHROUGH */ 1222 case IFM_1000_T: 1223 case IFM_1000_SX: 1224 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1225 val |= BNX_EMAC_MODE_PORT_GMII; 1226 break; 1227 default: 1228 val |= BNX_EMAC_MODE_PORT_GMII; 1229 break; 1230 } 1231 1232 /* Set half or full duplex based on the duplicity 1233 * negotiated by the PHY. 1234 */ 1235 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1236 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1237 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1238 } else { 1239 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1240 } 1241 1242 REG_WR(sc, BNX_EMAC_MODE, val); 1243 } 1244 1245 /****************************************************************************/ 1246 /* Acquire NVRAM lock. */ 1247 /* */ 1248 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1249 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1250 /* for use by the driver. */ 1251 /* */ 1252 /* Returns: */ 1253 /* 0 on success, positive value on failure. */ 1254 /****************************************************************************/ 1255 int 1256 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1257 { 1258 uint32_t val; 1259 int j; 1260 1261 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1262 1263 /* Request access to the flash interface. */ 1264 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1265 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1266 val = REG_RD(sc, BNX_NVM_SW_ARB); 1267 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1268 break; 1269 1270 DELAY(5); 1271 } 1272 1273 if (j >= NVRAM_TIMEOUT_COUNT) { 1274 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1275 return EBUSY; 1276 } 1277 1278 return 0; 1279 } 1280 1281 /****************************************************************************/ 1282 /* Release NVRAM lock. */ 1283 /* */ 1284 /* When the caller is finished accessing NVRAM the lock must be released. */ 1285 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1286 /* for use by the driver. */ 1287 /* */ 1288 /* Returns: */ 1289 /* 0 on success, positive value on failure. */ 1290 /****************************************************************************/ 1291 int 1292 bnx_release_nvram_lock(struct bnx_softc *sc) 1293 { 1294 int j; 1295 uint32_t val; 1296 1297 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1298 1299 /* Relinquish nvram interface. */ 1300 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1301 1302 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1303 val = REG_RD(sc, BNX_NVM_SW_ARB); 1304 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1305 break; 1306 1307 DELAY(5); 1308 } 1309 1310 if (j >= NVRAM_TIMEOUT_COUNT) { 1311 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1312 return EBUSY; 1313 } 1314 1315 return 0; 1316 } 1317 1318 #ifdef BNX_NVRAM_WRITE_SUPPORT 1319 /****************************************************************************/ 1320 /* Enable NVRAM write access. */ 1321 /* */ 1322 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1323 /* */ 1324 /* Returns: */ 1325 /* 0 on success, positive value on failure. */ 1326 /****************************************************************************/ 1327 int 1328 bnx_enable_nvram_write(struct bnx_softc *sc) 1329 { 1330 uint32_t val; 1331 1332 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1333 1334 val = REG_RD(sc, BNX_MISC_CFG); 1335 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1336 1337 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1338 int j; 1339 1340 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1341 REG_WR(sc, BNX_NVM_COMMAND, 1342 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1343 1344 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1345 DELAY(5); 1346 1347 val = REG_RD(sc, BNX_NVM_COMMAND); 1348 if (val & BNX_NVM_COMMAND_DONE) 1349 break; 1350 } 1351 1352 if (j >= NVRAM_TIMEOUT_COUNT) { 1353 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1354 return EBUSY; 1355 } 1356 } 1357 1358 return 0; 1359 } 1360 1361 /****************************************************************************/ 1362 /* Disable NVRAM write access. */ 1363 /* */ 1364 /* When the caller is finished writing to NVRAM write access must be */ 1365 /* disabled. */ 1366 /* */ 1367 /* Returns: */ 1368 /* Nothing. */ 1369 /****************************************************************************/ 1370 void 1371 bnx_disable_nvram_write(struct bnx_softc *sc) 1372 { 1373 uint32_t val; 1374 1375 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1376 1377 val = REG_RD(sc, BNX_MISC_CFG); 1378 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1379 } 1380 #endif 1381 1382 /****************************************************************************/ 1383 /* Enable NVRAM access. */ 1384 /* */ 1385 /* Before accessing NVRAM for read or write operations the caller must */ 1386 /* enabled NVRAM access. */ 1387 /* */ 1388 /* Returns: */ 1389 /* Nothing. */ 1390 /****************************************************************************/ 1391 void 1392 bnx_enable_nvram_access(struct bnx_softc *sc) 1393 { 1394 uint32_t val; 1395 1396 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1397 1398 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1399 /* Enable both bits, even on read. */ 1400 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1401 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1402 } 1403 1404 /****************************************************************************/ 1405 /* Disable NVRAM access. */ 1406 /* */ 1407 /* When the caller is finished accessing NVRAM access must be disabled. */ 1408 /* */ 1409 /* Returns: */ 1410 /* Nothing. */ 1411 /****************************************************************************/ 1412 void 1413 bnx_disable_nvram_access(struct bnx_softc *sc) 1414 { 1415 uint32_t val; 1416 1417 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1418 1419 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1420 1421 /* Disable both bits, even after read. */ 1422 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1423 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1424 } 1425 1426 #ifdef BNX_NVRAM_WRITE_SUPPORT 1427 /****************************************************************************/ 1428 /* Erase NVRAM page before writing. */ 1429 /* */ 1430 /* Non-buffered flash parts require that a page be erased before it is */ 1431 /* written. */ 1432 /* */ 1433 /* Returns: */ 1434 /* 0 on success, positive value on failure. */ 1435 /****************************************************************************/ 1436 int 1437 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1438 { 1439 uint32_t cmd; 1440 int j; 1441 1442 /* Buffered flash doesn't require an erase. */ 1443 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1444 return 0; 1445 1446 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1447 1448 /* Build an erase command. */ 1449 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1450 BNX_NVM_COMMAND_DOIT; 1451 1452 /* 1453 * Clear the DONE bit separately, set the NVRAM address to erase, 1454 * and issue the erase command. 1455 */ 1456 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1457 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1458 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1459 1460 /* Wait for completion. */ 1461 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1462 uint32_t val; 1463 1464 DELAY(5); 1465 1466 val = REG_RD(sc, BNX_NVM_COMMAND); 1467 if (val & BNX_NVM_COMMAND_DONE) 1468 break; 1469 } 1470 1471 if (j >= NVRAM_TIMEOUT_COUNT) { 1472 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1473 return EBUSY; 1474 } 1475 1476 return 0; 1477 } 1478 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1479 1480 /****************************************************************************/ 1481 /* Read a dword (32 bits) from NVRAM. */ 1482 /* */ 1483 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1484 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1485 /* */ 1486 /* Returns: */ 1487 /* 0 on success and the 32 bit value read, positive value on failure. */ 1488 /****************************************************************************/ 1489 int 1490 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1491 uint8_t *ret_val, uint32_t cmd_flags) 1492 { 1493 uint32_t cmd; 1494 int i, rc = 0; 1495 1496 /* Build the command word. */ 1497 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1498 1499 /* Calculate the offset for buffered flash if translation is used. */ 1500 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1501 offset = ((offset / sc->bnx_flash_info->page_size) << 1502 sc->bnx_flash_info->page_bits) + 1503 (offset % sc->bnx_flash_info->page_size); 1504 } 1505 1506 /* 1507 * Clear the DONE bit separately, set the address to read, 1508 * and issue the read. 1509 */ 1510 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1511 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1512 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1513 1514 /* Wait for completion. */ 1515 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1516 uint32_t val; 1517 1518 DELAY(5); 1519 1520 val = REG_RD(sc, BNX_NVM_COMMAND); 1521 if (val & BNX_NVM_COMMAND_DONE) { 1522 val = REG_RD(sc, BNX_NVM_READ); 1523 1524 val = bnx_be32toh(val); 1525 memcpy(ret_val, &val, 4); 1526 break; 1527 } 1528 } 1529 1530 /* Check for errors. */ 1531 if (i >= NVRAM_TIMEOUT_COUNT) { 1532 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1533 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1534 rc = EBUSY; 1535 } 1536 1537 return rc; 1538 } 1539 1540 #ifdef BNX_NVRAM_WRITE_SUPPORT 1541 /****************************************************************************/ 1542 /* Write a dword (32 bits) to NVRAM. */ 1543 /* */ 1544 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1545 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1546 /* enabled NVRAM write access. */ 1547 /* */ 1548 /* Returns: */ 1549 /* 0 on success, positive value on failure. */ 1550 /****************************************************************************/ 1551 int 1552 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1553 uint32_t cmd_flags) 1554 { 1555 uint32_t cmd, val32; 1556 int j; 1557 1558 /* Build the command word. */ 1559 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1560 1561 /* Calculate the offset for buffered flash if translation is used. */ 1562 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1563 offset = ((offset / sc->bnx_flash_info->page_size) << 1564 sc->bnx_flash_info->page_bits) + 1565 (offset % sc->bnx_flash_info->page_size); 1566 } 1567 1568 /* 1569 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1570 * set the NVRAM address to write, and issue the write command 1571 */ 1572 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1573 memcpy(&val32, val, 4); 1574 val32 = htobe32(val32); 1575 REG_WR(sc, BNX_NVM_WRITE, val32); 1576 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1577 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1578 1579 /* Wait for completion. */ 1580 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1581 DELAY(5); 1582 1583 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1584 break; 1585 } 1586 if (j >= NVRAM_TIMEOUT_COUNT) { 1587 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1588 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1589 return EBUSY; 1590 } 1591 1592 return 0; 1593 } 1594 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1595 1596 /****************************************************************************/ 1597 /* Initialize NVRAM access. */ 1598 /* */ 1599 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1600 /* access that device. */ 1601 /* */ 1602 /* Returns: */ 1603 /* 0 on success, positive value on failure. */ 1604 /****************************************************************************/ 1605 int 1606 bnx_init_nvram(struct bnx_softc *sc) 1607 { 1608 uint32_t val; 1609 int j, entry_count, rc = 0; 1610 struct flash_spec *flash; 1611 1612 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1613 1614 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1615 sc->bnx_flash_info = &flash_5709; 1616 goto bnx_init_nvram_get_flash_size; 1617 } 1618 1619 /* Determine the selected interface. */ 1620 val = REG_RD(sc, BNX_NVM_CFG1); 1621 1622 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1623 1624 /* 1625 * Flash reconfiguration is required to support additional 1626 * NVRAM devices not directly supported in hardware. 1627 * Check if the flash interface was reconfigured 1628 * by the bootcode. 1629 */ 1630 1631 if (val & 0x40000000) { 1632 /* Flash interface reconfigured by bootcode. */ 1633 1634 DBPRINT(sc,BNX_INFO_LOAD, 1635 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1636 1637 for (j = 0, flash = &flash_table[0]; j < entry_count; 1638 j++, flash++) { 1639 if ((val & FLASH_BACKUP_STRAP_MASK) == 1640 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1641 sc->bnx_flash_info = flash; 1642 break; 1643 } 1644 } 1645 } else { 1646 /* Flash interface not yet reconfigured. */ 1647 uint32_t mask; 1648 1649 DBPRINT(sc,BNX_INFO_LOAD, 1650 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1651 1652 if (val & (1 << 23)) 1653 mask = FLASH_BACKUP_STRAP_MASK; 1654 else 1655 mask = FLASH_STRAP_MASK; 1656 1657 /* Look for the matching NVRAM device configuration data. */ 1658 for (j = 0, flash = &flash_table[0]; j < entry_count; 1659 j++, flash++) { 1660 /* Check if the dev matches any of the known devices. */ 1661 if ((val & mask) == (flash->strapping & mask)) { 1662 /* Found a device match. */ 1663 sc->bnx_flash_info = flash; 1664 1665 /* Request access to the flash interface. */ 1666 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1667 return rc; 1668 1669 /* Reconfigure the flash interface. */ 1670 bnx_enable_nvram_access(sc); 1671 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1672 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1673 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1674 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1675 bnx_disable_nvram_access(sc); 1676 bnx_release_nvram_lock(sc); 1677 1678 break; 1679 } 1680 } 1681 } 1682 1683 /* Check if a matching device was found. */ 1684 if (j == entry_count) { 1685 sc->bnx_flash_info = NULL; 1686 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1687 __FILE__, __LINE__); 1688 rc = ENODEV; 1689 } 1690 1691 bnx_init_nvram_get_flash_size: 1692 /* Write the flash config data to the shared memory interface. */ 1693 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1694 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1695 if (val) 1696 sc->bnx_flash_size = val; 1697 else 1698 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1699 1700 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1701 "0x%08X\n", sc->bnx_flash_info->total_size); 1702 1703 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1704 1705 return rc; 1706 } 1707 1708 /****************************************************************************/ 1709 /* Read an arbitrary range of data from NVRAM. */ 1710 /* */ 1711 /* Prepares the NVRAM interface for access and reads the requested data */ 1712 /* into the supplied buffer. */ 1713 /* */ 1714 /* Returns: */ 1715 /* 0 on success and the data read, positive value on failure. */ 1716 /****************************************************************************/ 1717 int 1718 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1719 int buf_size) 1720 { 1721 int rc = 0; 1722 uint32_t cmd_flags, offset32, len32, extra; 1723 1724 if (buf_size == 0) 1725 return 0; 1726 1727 /* Request access to the flash interface. */ 1728 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1729 return rc; 1730 1731 /* Enable access to flash interface */ 1732 bnx_enable_nvram_access(sc); 1733 1734 len32 = buf_size; 1735 offset32 = offset; 1736 extra = 0; 1737 1738 cmd_flags = 0; 1739 1740 if (offset32 & 3) { 1741 uint8_t buf[4]; 1742 uint32_t pre_len; 1743 1744 offset32 &= ~3; 1745 pre_len = 4 - (offset & 3); 1746 1747 if (pre_len >= len32) { 1748 pre_len = len32; 1749 cmd_flags = 1750 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1751 } else 1752 cmd_flags = BNX_NVM_COMMAND_FIRST; 1753 1754 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1755 1756 if (rc) 1757 return rc; 1758 1759 memcpy(ret_buf, buf + (offset & 3), pre_len); 1760 1761 offset32 += 4; 1762 ret_buf += pre_len; 1763 len32 -= pre_len; 1764 } 1765 1766 if (len32 & 3) { 1767 extra = 4 - (len32 & 3); 1768 len32 = (len32 + 4) & ~3; 1769 } 1770 1771 if (len32 == 4) { 1772 uint8_t buf[4]; 1773 1774 if (cmd_flags) 1775 cmd_flags = BNX_NVM_COMMAND_LAST; 1776 else 1777 cmd_flags = 1778 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1779 1780 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1781 1782 memcpy(ret_buf, buf, 4 - extra); 1783 } else if (len32 > 0) { 1784 uint8_t buf[4]; 1785 1786 /* Read the first word. */ 1787 if (cmd_flags) 1788 cmd_flags = 0; 1789 else 1790 cmd_flags = BNX_NVM_COMMAND_FIRST; 1791 1792 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1793 1794 /* Advance to the next dword. */ 1795 offset32 += 4; 1796 ret_buf += 4; 1797 len32 -= 4; 1798 1799 while (len32 > 4 && rc == 0) { 1800 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1801 1802 /* Advance to the next dword. */ 1803 offset32 += 4; 1804 ret_buf += 4; 1805 len32 -= 4; 1806 } 1807 1808 if (rc) 1809 return rc; 1810 1811 cmd_flags = BNX_NVM_COMMAND_LAST; 1812 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1813 1814 memcpy(ret_buf, buf, 4 - extra); 1815 } 1816 1817 /* Disable access to flash interface and release the lock. */ 1818 bnx_disable_nvram_access(sc); 1819 bnx_release_nvram_lock(sc); 1820 1821 return rc; 1822 } 1823 1824 #ifdef BNX_NVRAM_WRITE_SUPPORT 1825 /****************************************************************************/ 1826 /* Write an arbitrary range of data from NVRAM. */ 1827 /* */ 1828 /* Prepares the NVRAM interface for write access and writes the requested */ 1829 /* data from the supplied buffer. The caller is responsible for */ 1830 /* calculating any appropriate CRCs. */ 1831 /* */ 1832 /* Returns: */ 1833 /* 0 on success, positive value on failure. */ 1834 /****************************************************************************/ 1835 int 1836 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1837 int buf_size) 1838 { 1839 uint32_t written, offset32, len32; 1840 uint8_t *buf, start[4], end[4]; 1841 int rc = 0; 1842 int align_start, align_end; 1843 1844 buf = data_buf; 1845 offset32 = offset; 1846 len32 = buf_size; 1847 align_start = align_end = 0; 1848 1849 if ((align_start = (offset32 & 3))) { 1850 offset32 &= ~3; 1851 len32 += align_start; 1852 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1853 return rc; 1854 } 1855 1856 if (len32 & 3) { 1857 if ((len32 > 4) || !align_start) { 1858 align_end = 4 - (len32 & 3); 1859 len32 += align_end; 1860 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1861 end, 4))) 1862 return rc; 1863 } 1864 } 1865 1866 if (align_start || align_end) { 1867 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1868 if (buf == 0) 1869 return ENOMEM; 1870 1871 if (align_start) 1872 memcpy(buf, start, 4); 1873 1874 if (align_end) 1875 memcpy(buf + len32 - 4, end, 4); 1876 1877 memcpy(buf + align_start, data_buf, buf_size); 1878 } 1879 1880 written = 0; 1881 while ((written < len32) && (rc == 0)) { 1882 uint32_t page_start, page_end, data_start, data_end; 1883 uint32_t addr, cmd_flags; 1884 int i; 1885 uint8_t flash_buffer[264]; 1886 1887 /* Find the page_start addr */ 1888 page_start = offset32 + written; 1889 page_start -= (page_start % sc->bnx_flash_info->page_size); 1890 /* Find the page_end addr */ 1891 page_end = page_start + sc->bnx_flash_info->page_size; 1892 /* Find the data_start addr */ 1893 data_start = (written == 0) ? offset32 : page_start; 1894 /* Find the data_end addr */ 1895 data_end = (page_end > offset32 + len32) ? 1896 (offset32 + len32) : page_end; 1897 1898 /* Request access to the flash interface. */ 1899 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1900 goto nvram_write_end; 1901 1902 /* Enable access to flash interface */ 1903 bnx_enable_nvram_access(sc); 1904 1905 cmd_flags = BNX_NVM_COMMAND_FIRST; 1906 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1907 int j; 1908 1909 /* Read the whole page into the buffer 1910 * (non-buffer flash only) */ 1911 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1912 if (j == (sc->bnx_flash_info->page_size - 4)) 1913 cmd_flags |= BNX_NVM_COMMAND_LAST; 1914 1915 rc = bnx_nvram_read_dword(sc, 1916 page_start + j, 1917 &flash_buffer[j], 1918 cmd_flags); 1919 1920 if (rc) 1921 goto nvram_write_end; 1922 1923 cmd_flags = 0; 1924 } 1925 } 1926 1927 /* Enable writes to flash interface (unlock write-protect) */ 1928 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1929 goto nvram_write_end; 1930 1931 /* Erase the page */ 1932 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1933 goto nvram_write_end; 1934 1935 /* Re-enable the write again for the actual write */ 1936 bnx_enable_nvram_write(sc); 1937 1938 /* Loop to write back the buffer data from page_start to 1939 * data_start */ 1940 i = 0; 1941 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1942 for (addr = page_start; addr < data_start; 1943 addr += 4, i += 4) { 1944 1945 rc = bnx_nvram_write_dword(sc, addr, 1946 &flash_buffer[i], cmd_flags); 1947 1948 if (rc != 0) 1949 goto nvram_write_end; 1950 1951 cmd_flags = 0; 1952 } 1953 } 1954 1955 /* Loop to write the new data from data_start to data_end */ 1956 for (addr = data_start; addr < data_end; addr += 4, i++) { 1957 if ((addr == page_end - 4) || 1958 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1959 && (addr == data_end - 4))) { 1960 1961 cmd_flags |= BNX_NVM_COMMAND_LAST; 1962 } 1963 1964 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1965 1966 if (rc != 0) 1967 goto nvram_write_end; 1968 1969 cmd_flags = 0; 1970 buf += 4; 1971 } 1972 1973 /* Loop to write back the buffer data from data_end 1974 * to page_end */ 1975 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1976 for (addr = data_end; addr < page_end; 1977 addr += 4, i += 4) { 1978 1979 if (addr == page_end-4) 1980 cmd_flags = BNX_NVM_COMMAND_LAST; 1981 1982 rc = bnx_nvram_write_dword(sc, addr, 1983 &flash_buffer[i], cmd_flags); 1984 1985 if (rc != 0) 1986 goto nvram_write_end; 1987 1988 cmd_flags = 0; 1989 } 1990 } 1991 1992 /* Disable writes to flash interface (lock write-protect) */ 1993 bnx_disable_nvram_write(sc); 1994 1995 /* Disable access to flash interface */ 1996 bnx_disable_nvram_access(sc); 1997 bnx_release_nvram_lock(sc); 1998 1999 /* Increment written */ 2000 written += data_end - data_start; 2001 } 2002 2003 nvram_write_end: 2004 if (align_start || align_end) 2005 free(buf, M_DEVBUF); 2006 2007 return rc; 2008 } 2009 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2010 2011 /****************************************************************************/ 2012 /* Verifies that NVRAM is accessible and contains valid data. */ 2013 /* */ 2014 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2015 /* correct. */ 2016 /* */ 2017 /* Returns: */ 2018 /* 0 on success, positive value on failure. */ 2019 /****************************************************************************/ 2020 int 2021 bnx_nvram_test(struct bnx_softc *sc) 2022 { 2023 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2024 uint8_t *data = (uint8_t *) buf; 2025 int rc = 0; 2026 uint32_t magic, csum; 2027 2028 /* 2029 * Check that the device NVRAM is valid by reading 2030 * the magic value at offset 0. 2031 */ 2032 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2033 goto bnx_nvram_test_done; 2034 2035 magic = bnx_be32toh(buf[0]); 2036 if (magic != BNX_NVRAM_MAGIC) { 2037 rc = ENODEV; 2038 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2039 "Expected: 0x%08X, Found: 0x%08X\n", 2040 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2041 goto bnx_nvram_test_done; 2042 } 2043 2044 /* 2045 * Verify that the device NVRAM includes valid 2046 * configuration data. 2047 */ 2048 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2049 goto bnx_nvram_test_done; 2050 2051 csum = ether_crc32_le(data, 0x100); 2052 if (csum != BNX_CRC32_RESIDUAL) { 2053 rc = ENODEV; 2054 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2055 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2056 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2057 goto bnx_nvram_test_done; 2058 } 2059 2060 csum = ether_crc32_le(data + 0x100, 0x100); 2061 if (csum != BNX_CRC32_RESIDUAL) { 2062 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2063 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2064 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2065 rc = ENODEV; 2066 } 2067 2068 bnx_nvram_test_done: 2069 return rc; 2070 } 2071 2072 /****************************************************************************/ 2073 /* Identifies the current media type of the controller and sets the PHY */ 2074 /* address. */ 2075 /* */ 2076 /* Returns: */ 2077 /* Nothing. */ 2078 /****************************************************************************/ 2079 void 2080 bnx_get_media(struct bnx_softc *sc) 2081 { 2082 sc->bnx_phy_addr = 1; 2083 2084 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2085 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2086 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2087 uint32_t strap; 2088 2089 /* 2090 * The BCM5709S is software configurable 2091 * for Copper or SerDes operation. 2092 */ 2093 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2094 DBPRINT(sc, BNX_INFO_LOAD, 2095 "5709 bonded for copper.\n"); 2096 goto bnx_get_media_exit; 2097 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2098 DBPRINT(sc, BNX_INFO_LOAD, 2099 "5709 bonded for dual media.\n"); 2100 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2101 goto bnx_get_media_exit; 2102 } 2103 2104 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2105 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2106 else { 2107 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2108 >> 8; 2109 } 2110 2111 if (sc->bnx_pa.pa_function == 0) { 2112 switch (strap) { 2113 case 0x4: 2114 case 0x5: 2115 case 0x6: 2116 DBPRINT(sc, BNX_INFO_LOAD, 2117 "BCM5709 s/w configured for SerDes.\n"); 2118 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2119 break; 2120 default: 2121 DBPRINT(sc, BNX_INFO_LOAD, 2122 "BCM5709 s/w configured for Copper.\n"); 2123 } 2124 } else { 2125 switch (strap) { 2126 case 0x1: 2127 case 0x2: 2128 case 0x4: 2129 DBPRINT(sc, BNX_INFO_LOAD, 2130 "BCM5709 s/w configured for SerDes.\n"); 2131 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2132 break; 2133 default: 2134 DBPRINT(sc, BNX_INFO_LOAD, 2135 "BCM5709 s/w configured for Copper.\n"); 2136 } 2137 } 2138 2139 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2140 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2141 2142 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2143 uint32_t val; 2144 2145 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2146 2147 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2148 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2149 2150 /* 2151 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2152 * separate PHY for SerDes. 2153 */ 2154 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2155 sc->bnx_phy_addr = 2; 2156 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2157 BNX_SHARED_HW_CFG_CONFIG); 2158 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2159 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2160 DBPRINT(sc, BNX_INFO_LOAD, 2161 "Found 2.5Gb capable adapter\n"); 2162 } 2163 } 2164 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2165 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2166 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2167 2168 bnx_get_media_exit: 2169 DBPRINT(sc, (BNX_INFO_LOAD), 2170 "Using PHY address %d.\n", sc->bnx_phy_addr); 2171 } 2172 2173 /****************************************************************************/ 2174 /* Performs PHY initialization required before MII drivers access the */ 2175 /* device. */ 2176 /* */ 2177 /* Returns: */ 2178 /* Nothing. */ 2179 /****************************************************************************/ 2180 void 2181 bnx_init_media(struct bnx_softc *sc) 2182 { 2183 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2184 /* 2185 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2186 * IEEE Clause 22 method. Otherwise we have no way to attach 2187 * the PHY to the mii(4) layer. PHY specific configuration 2188 * is done by the mii(4) layer. 2189 */ 2190 2191 /* Select auto-negotiation MMD of the PHY. */ 2192 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2193 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2194 2195 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2196 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2197 2198 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2199 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2200 } 2201 } 2202 2203 /****************************************************************************/ 2204 /* Free any DMA memory owned by the driver. */ 2205 /* */ 2206 /* Scans through each data structre that requires DMA memory and frees */ 2207 /* the memory if allocated. */ 2208 /* */ 2209 /* Returns: */ 2210 /* Nothing. */ 2211 /****************************************************************************/ 2212 void 2213 bnx_dma_free(struct bnx_softc *sc) 2214 { 2215 int i; 2216 2217 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2218 2219 /* Destroy the status block. */ 2220 if (sc->status_block != NULL && sc->status_map != NULL) { 2221 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2222 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2223 BNX_STATUS_BLK_SZ); 2224 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2225 sc->status_rseg); 2226 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2227 sc->status_block = NULL; 2228 sc->status_map = NULL; 2229 } 2230 2231 /* Destroy the statistics block. */ 2232 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2233 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2234 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2235 BNX_STATS_BLK_SZ); 2236 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2237 sc->stats_rseg); 2238 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2239 sc->stats_block = NULL; 2240 sc->stats_map = NULL; 2241 } 2242 2243 /* Free, unmap and destroy all context memory pages. */ 2244 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2245 for (i = 0; i < sc->ctx_pages; i++) { 2246 if (sc->ctx_block[i] != NULL) { 2247 bus_dmamap_unload(sc->bnx_dmatag, 2248 sc->ctx_map[i]); 2249 bus_dmamem_unmap(sc->bnx_dmatag, 2250 (void *)sc->ctx_block[i], 2251 BCM_PAGE_SIZE); 2252 bus_dmamem_free(sc->bnx_dmatag, 2253 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2254 bus_dmamap_destroy(sc->bnx_dmatag, 2255 sc->ctx_map[i]); 2256 sc->ctx_block[i] = NULL; 2257 } 2258 } 2259 } 2260 2261 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2262 for (i = 0; i < TX_PAGES; i++ ) { 2263 if (sc->tx_bd_chain[i] != NULL && 2264 sc->tx_bd_chain_map[i] != NULL) { 2265 bus_dmamap_unload(sc->bnx_dmatag, 2266 sc->tx_bd_chain_map[i]); 2267 bus_dmamem_unmap(sc->bnx_dmatag, 2268 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2269 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2270 sc->tx_bd_chain_rseg[i]); 2271 bus_dmamap_destroy(sc->bnx_dmatag, 2272 sc->tx_bd_chain_map[i]); 2273 sc->tx_bd_chain[i] = NULL; 2274 sc->tx_bd_chain_map[i] = NULL; 2275 } 2276 } 2277 2278 /* Destroy the TX dmamaps. */ 2279 /* This isn't necessary since we dont allocate them up front */ 2280 2281 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2282 for (i = 0; i < RX_PAGES; i++ ) { 2283 if (sc->rx_bd_chain[i] != NULL && 2284 sc->rx_bd_chain_map[i] != NULL) { 2285 bus_dmamap_unload(sc->bnx_dmatag, 2286 sc->rx_bd_chain_map[i]); 2287 bus_dmamem_unmap(sc->bnx_dmatag, 2288 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2289 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2290 sc->rx_bd_chain_rseg[i]); 2291 2292 bus_dmamap_destroy(sc->bnx_dmatag, 2293 sc->rx_bd_chain_map[i]); 2294 sc->rx_bd_chain[i] = NULL; 2295 sc->rx_bd_chain_map[i] = NULL; 2296 } 2297 } 2298 2299 /* Unload and destroy the RX mbuf maps. */ 2300 for (i = 0; i < TOTAL_RX_BD; i++) { 2301 if (sc->rx_mbuf_map[i] != NULL) { 2302 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2303 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2304 } 2305 } 2306 2307 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2308 } 2309 2310 /****************************************************************************/ 2311 /* Allocate any DMA memory needed by the driver. */ 2312 /* */ 2313 /* Allocates DMA memory needed for the various global structures needed by */ 2314 /* hardware. */ 2315 /* */ 2316 /* Returns: */ 2317 /* 0 for success, positive value for failure. */ 2318 /****************************************************************************/ 2319 int 2320 bnx_dma_alloc(struct bnx_softc *sc) 2321 { 2322 int i, rc = 0; 2323 2324 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2325 2326 /* 2327 * Allocate DMA memory for the status block, map the memory into DMA 2328 * space, and fetch the physical address of the block. 2329 */ 2330 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2331 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2332 aprint_error_dev(sc->bnx_dev, 2333 "Could not create status block DMA map!\n"); 2334 rc = ENOMEM; 2335 goto bnx_dma_alloc_exit; 2336 } 2337 2338 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2339 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2340 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2341 aprint_error_dev(sc->bnx_dev, 2342 "Could not allocate status block DMA memory!\n"); 2343 rc = ENOMEM; 2344 goto bnx_dma_alloc_exit; 2345 } 2346 2347 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2348 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2349 aprint_error_dev(sc->bnx_dev, 2350 "Could not map status block DMA memory!\n"); 2351 rc = ENOMEM; 2352 goto bnx_dma_alloc_exit; 2353 } 2354 2355 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2356 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2357 aprint_error_dev(sc->bnx_dev, 2358 "Could not load status block DMA memory!\n"); 2359 rc = ENOMEM; 2360 goto bnx_dma_alloc_exit; 2361 } 2362 2363 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2364 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2365 2366 /* DRC - Fix for 64 bit addresses. */ 2367 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2368 (uint32_t) sc->status_block_paddr); 2369 2370 /* BCM5709 uses host memory as cache for context memory. */ 2371 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2372 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2373 if (sc->ctx_pages == 0) 2374 sc->ctx_pages = 1; 2375 if (sc->ctx_pages > 4) /* XXX */ 2376 sc->ctx_pages = 4; 2377 2378 DBRUNIF((sc->ctx_pages > 512), 2379 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2380 __FILE__, __LINE__, sc->ctx_pages)); 2381 2382 2383 for (i = 0; i < sc->ctx_pages; i++) { 2384 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2385 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2386 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2387 &sc->ctx_map[i]) != 0) { 2388 rc = ENOMEM; 2389 goto bnx_dma_alloc_exit; 2390 } 2391 2392 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2393 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2394 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2395 rc = ENOMEM; 2396 goto bnx_dma_alloc_exit; 2397 } 2398 2399 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2400 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2401 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2402 rc = ENOMEM; 2403 goto bnx_dma_alloc_exit; 2404 } 2405 2406 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2407 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2408 BUS_DMA_NOWAIT) != 0) { 2409 rc = ENOMEM; 2410 goto bnx_dma_alloc_exit; 2411 } 2412 2413 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2414 } 2415 } 2416 2417 /* 2418 * Allocate DMA memory for the statistics block, map the memory into 2419 * DMA space, and fetch the physical address of the block. 2420 */ 2421 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2422 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2423 aprint_error_dev(sc->bnx_dev, 2424 "Could not create stats block DMA map!\n"); 2425 rc = ENOMEM; 2426 goto bnx_dma_alloc_exit; 2427 } 2428 2429 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2430 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2431 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2432 aprint_error_dev(sc->bnx_dev, 2433 "Could not allocate stats block DMA memory!\n"); 2434 rc = ENOMEM; 2435 goto bnx_dma_alloc_exit; 2436 } 2437 2438 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2439 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2440 aprint_error_dev(sc->bnx_dev, 2441 "Could not map stats block DMA memory!\n"); 2442 rc = ENOMEM; 2443 goto bnx_dma_alloc_exit; 2444 } 2445 2446 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2447 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2448 aprint_error_dev(sc->bnx_dev, 2449 "Could not load status block DMA memory!\n"); 2450 rc = ENOMEM; 2451 goto bnx_dma_alloc_exit; 2452 } 2453 2454 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2455 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2456 2457 /* DRC - Fix for 64 bit address. */ 2458 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2459 (uint32_t) sc->stats_block_paddr); 2460 2461 /* 2462 * Allocate DMA memory for the TX buffer descriptor chain, 2463 * and fetch the physical address of the block. 2464 */ 2465 for (i = 0; i < TX_PAGES; i++) { 2466 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2467 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2468 &sc->tx_bd_chain_map[i])) { 2469 aprint_error_dev(sc->bnx_dev, 2470 "Could not create Tx desc %d DMA map!\n", i); 2471 rc = ENOMEM; 2472 goto bnx_dma_alloc_exit; 2473 } 2474 2475 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2476 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2477 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2478 aprint_error_dev(sc->bnx_dev, 2479 "Could not allocate TX desc %d DMA memory!\n", 2480 i); 2481 rc = ENOMEM; 2482 goto bnx_dma_alloc_exit; 2483 } 2484 2485 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2486 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2487 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2488 aprint_error_dev(sc->bnx_dev, 2489 "Could not map TX desc %d DMA memory!\n", i); 2490 rc = ENOMEM; 2491 goto bnx_dma_alloc_exit; 2492 } 2493 2494 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2495 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2496 BUS_DMA_NOWAIT)) { 2497 aprint_error_dev(sc->bnx_dev, 2498 "Could not load TX desc %d DMA memory!\n", i); 2499 rc = ENOMEM; 2500 goto bnx_dma_alloc_exit; 2501 } 2502 2503 sc->tx_bd_chain_paddr[i] = 2504 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2505 2506 /* DRC - Fix for 64 bit systems. */ 2507 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2508 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2509 } 2510 2511 /* 2512 * Create lists to hold TX mbufs. 2513 */ 2514 TAILQ_INIT(&sc->tx_free_pkts); 2515 TAILQ_INIT(&sc->tx_used_pkts); 2516 sc->tx_pkt_count = 0; 2517 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2518 2519 /* 2520 * Allocate DMA memory for the Rx buffer descriptor chain, 2521 * and fetch the physical address of the block. 2522 */ 2523 for (i = 0; i < RX_PAGES; i++) { 2524 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2525 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2526 &sc->rx_bd_chain_map[i])) { 2527 aprint_error_dev(sc->bnx_dev, 2528 "Could not create Rx desc %d DMA map!\n", i); 2529 rc = ENOMEM; 2530 goto bnx_dma_alloc_exit; 2531 } 2532 2533 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2534 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2535 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2536 aprint_error_dev(sc->bnx_dev, 2537 "Could not allocate Rx desc %d DMA memory!\n", i); 2538 rc = ENOMEM; 2539 goto bnx_dma_alloc_exit; 2540 } 2541 2542 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2543 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2544 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2545 aprint_error_dev(sc->bnx_dev, 2546 "Could not map Rx desc %d DMA memory!\n", i); 2547 rc = ENOMEM; 2548 goto bnx_dma_alloc_exit; 2549 } 2550 2551 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2552 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2553 BUS_DMA_NOWAIT)) { 2554 aprint_error_dev(sc->bnx_dev, 2555 "Could not load Rx desc %d DMA memory!\n", i); 2556 rc = ENOMEM; 2557 goto bnx_dma_alloc_exit; 2558 } 2559 2560 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2561 sc->rx_bd_chain_paddr[i] = 2562 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2563 2564 /* DRC - Fix for 64 bit systems. */ 2565 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2566 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2567 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2568 0, BNX_RX_CHAIN_PAGE_SZ, 2569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2570 } 2571 2572 /* 2573 * Create DMA maps for the Rx buffer mbufs. 2574 */ 2575 for (i = 0; i < TOTAL_RX_BD; i++) { 2576 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2577 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2578 &sc->rx_mbuf_map[i])) { 2579 aprint_error_dev(sc->bnx_dev, 2580 "Could not create Rx mbuf %d DMA map!\n", i); 2581 rc = ENOMEM; 2582 goto bnx_dma_alloc_exit; 2583 } 2584 } 2585 2586 bnx_dma_alloc_exit: 2587 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2588 2589 return rc; 2590 } 2591 2592 /****************************************************************************/ 2593 /* Release all resources used by the driver. */ 2594 /* */ 2595 /* Releases all resources acquired by the driver including interrupts, */ 2596 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2597 /* */ 2598 /* Returns: */ 2599 /* Nothing. */ 2600 /****************************************************************************/ 2601 void 2602 bnx_release_resources(struct bnx_softc *sc) 2603 { 2604 struct pci_attach_args *pa = &(sc->bnx_pa); 2605 2606 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2607 2608 bnx_dma_free(sc); 2609 2610 if (sc->bnx_intrhand != NULL) 2611 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2612 2613 if (sc->bnx_size) 2614 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2615 2616 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2617 } 2618 2619 /****************************************************************************/ 2620 /* Firmware synchronization. */ 2621 /* */ 2622 /* Before performing certain events such as a chip reset, synchronize with */ 2623 /* the firmware first. */ 2624 /* */ 2625 /* Returns: */ 2626 /* 0 for success, positive value for failure. */ 2627 /****************************************************************************/ 2628 int 2629 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2630 { 2631 int i, rc = 0; 2632 uint32_t val; 2633 2634 /* Don't waste any time if we've timed out before. */ 2635 if (sc->bnx_fw_timed_out) { 2636 rc = EBUSY; 2637 goto bnx_fw_sync_exit; 2638 } 2639 2640 /* Increment the message sequence number. */ 2641 sc->bnx_fw_wr_seq++; 2642 msg_data |= sc->bnx_fw_wr_seq; 2643 2644 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2645 msg_data); 2646 2647 /* Send the message to the bootcode driver mailbox. */ 2648 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2649 2650 /* Wait for the bootcode to acknowledge the message. */ 2651 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2652 /* Check for a response in the bootcode firmware mailbox. */ 2653 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2654 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2655 break; 2656 DELAY(1000); 2657 } 2658 2659 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2660 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2661 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2662 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2663 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2664 2665 msg_data &= ~BNX_DRV_MSG_CODE; 2666 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2667 2668 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2669 2670 sc->bnx_fw_timed_out = 1; 2671 rc = EBUSY; 2672 } 2673 2674 bnx_fw_sync_exit: 2675 return rc; 2676 } 2677 2678 /****************************************************************************/ 2679 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2680 /* */ 2681 /* Returns: */ 2682 /* Nothing. */ 2683 /****************************************************************************/ 2684 void 2685 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2686 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2687 { 2688 int i; 2689 uint32_t val; 2690 2691 /* Set the page size used by RV2P. */ 2692 if (rv2p_proc == RV2P_PROC2) { 2693 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2694 USABLE_RX_BD_PER_PAGE); 2695 } 2696 2697 for (i = 0; i < rv2p_code_len; i += 8) { 2698 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2699 rv2p_code++; 2700 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2701 rv2p_code++; 2702 2703 if (rv2p_proc == RV2P_PROC1) { 2704 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2705 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2706 } else { 2707 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2708 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2709 } 2710 } 2711 2712 /* Reset the processor, un-stall is done later. */ 2713 if (rv2p_proc == RV2P_PROC1) 2714 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2715 else 2716 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2717 } 2718 2719 /****************************************************************************/ 2720 /* Load RISC processor firmware. */ 2721 /* */ 2722 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2723 /* associated with a particular processor. */ 2724 /* */ 2725 /* Returns: */ 2726 /* Nothing. */ 2727 /****************************************************************************/ 2728 void 2729 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2730 struct fw_info *fw) 2731 { 2732 uint32_t offset; 2733 uint32_t val; 2734 2735 /* Halt the CPU. */ 2736 val = REG_RD_IND(sc, cpu_reg->mode); 2737 val |= cpu_reg->mode_value_halt; 2738 REG_WR_IND(sc, cpu_reg->mode, val); 2739 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2740 2741 /* Load the Text area. */ 2742 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2743 if (fw->text) { 2744 int j; 2745 2746 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2747 REG_WR_IND(sc, offset, fw->text[j]); 2748 } 2749 2750 /* Load the Data area. */ 2751 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2752 if (fw->data) { 2753 int j; 2754 2755 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2756 REG_WR_IND(sc, offset, fw->data[j]); 2757 } 2758 2759 /* Load the SBSS area. */ 2760 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2761 if (fw->sbss) { 2762 int j; 2763 2764 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2765 REG_WR_IND(sc, offset, fw->sbss[j]); 2766 } 2767 2768 /* Load the BSS area. */ 2769 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2770 if (fw->bss) { 2771 int j; 2772 2773 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2774 REG_WR_IND(sc, offset, fw->bss[j]); 2775 } 2776 2777 /* Load the Read-Only area. */ 2778 offset = cpu_reg->spad_base + 2779 (fw->rodata_addr - cpu_reg->mips_view_base); 2780 if (fw->rodata) { 2781 int j; 2782 2783 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2784 REG_WR_IND(sc, offset, fw->rodata[j]); 2785 } 2786 2787 /* Clear the pre-fetch instruction. */ 2788 REG_WR_IND(sc, cpu_reg->inst, 0); 2789 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2790 2791 /* Start the CPU. */ 2792 val = REG_RD_IND(sc, cpu_reg->mode); 2793 val &= ~cpu_reg->mode_value_halt; 2794 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2795 REG_WR_IND(sc, cpu_reg->mode, val); 2796 } 2797 2798 /****************************************************************************/ 2799 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2800 /* */ 2801 /* Loads the firmware for each CPU and starts the CPU. */ 2802 /* */ 2803 /* Returns: */ 2804 /* Nothing. */ 2805 /****************************************************************************/ 2806 void 2807 bnx_init_cpus(struct bnx_softc *sc) 2808 { 2809 struct cpu_reg cpu_reg; 2810 struct fw_info fw; 2811 2812 switch(BNX_CHIP_NUM(sc)) { 2813 case BNX_CHIP_NUM_5709: 2814 /* Initialize the RV2P processor. */ 2815 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2816 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2817 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2818 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2819 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2820 } else { 2821 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2822 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2823 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2824 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2825 } 2826 2827 /* Initialize the RX Processor. */ 2828 cpu_reg.mode = BNX_RXP_CPU_MODE; 2829 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2830 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2831 cpu_reg.state = BNX_RXP_CPU_STATE; 2832 cpu_reg.state_value_clear = 0xffffff; 2833 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2834 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2835 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2836 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2837 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2838 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2839 cpu_reg.mips_view_base = 0x8000000; 2840 2841 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2842 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2843 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2844 fw.start_addr = bnx_RXP_b09FwStartAddr; 2845 2846 fw.text_addr = bnx_RXP_b09FwTextAddr; 2847 fw.text_len = bnx_RXP_b09FwTextLen; 2848 fw.text_index = 0; 2849 fw.text = bnx_RXP_b09FwText; 2850 2851 fw.data_addr = bnx_RXP_b09FwDataAddr; 2852 fw.data_len = bnx_RXP_b09FwDataLen; 2853 fw.data_index = 0; 2854 fw.data = bnx_RXP_b09FwData; 2855 2856 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2857 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2858 fw.sbss_index = 0; 2859 fw.sbss = bnx_RXP_b09FwSbss; 2860 2861 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2862 fw.bss_len = bnx_RXP_b09FwBssLen; 2863 fw.bss_index = 0; 2864 fw.bss = bnx_RXP_b09FwBss; 2865 2866 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2867 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2868 fw.rodata_index = 0; 2869 fw.rodata = bnx_RXP_b09FwRodata; 2870 2871 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2872 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2873 2874 /* Initialize the TX Processor. */ 2875 cpu_reg.mode = BNX_TXP_CPU_MODE; 2876 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2877 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2878 cpu_reg.state = BNX_TXP_CPU_STATE; 2879 cpu_reg.state_value_clear = 0xffffff; 2880 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2881 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2882 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2883 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2884 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2885 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2886 cpu_reg.mips_view_base = 0x8000000; 2887 2888 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2889 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2890 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2891 fw.start_addr = bnx_TXP_b09FwStartAddr; 2892 2893 fw.text_addr = bnx_TXP_b09FwTextAddr; 2894 fw.text_len = bnx_TXP_b09FwTextLen; 2895 fw.text_index = 0; 2896 fw.text = bnx_TXP_b09FwText; 2897 2898 fw.data_addr = bnx_TXP_b09FwDataAddr; 2899 fw.data_len = bnx_TXP_b09FwDataLen; 2900 fw.data_index = 0; 2901 fw.data = bnx_TXP_b09FwData; 2902 2903 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2904 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2905 fw.sbss_index = 0; 2906 fw.sbss = bnx_TXP_b09FwSbss; 2907 2908 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2909 fw.bss_len = bnx_TXP_b09FwBssLen; 2910 fw.bss_index = 0; 2911 fw.bss = bnx_TXP_b09FwBss; 2912 2913 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2914 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2915 fw.rodata_index = 0; 2916 fw.rodata = bnx_TXP_b09FwRodata; 2917 2918 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2919 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2920 2921 /* Initialize the TX Patch-up Processor. */ 2922 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2923 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2924 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2925 cpu_reg.state = BNX_TPAT_CPU_STATE; 2926 cpu_reg.state_value_clear = 0xffffff; 2927 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2928 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2929 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2930 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2931 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2932 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2933 cpu_reg.mips_view_base = 0x8000000; 2934 2935 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2936 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2937 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2938 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2939 2940 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2941 fw.text_len = bnx_TPAT_b09FwTextLen; 2942 fw.text_index = 0; 2943 fw.text = bnx_TPAT_b09FwText; 2944 2945 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2946 fw.data_len = bnx_TPAT_b09FwDataLen; 2947 fw.data_index = 0; 2948 fw.data = bnx_TPAT_b09FwData; 2949 2950 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2951 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2952 fw.sbss_index = 0; 2953 fw.sbss = bnx_TPAT_b09FwSbss; 2954 2955 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2956 fw.bss_len = bnx_TPAT_b09FwBssLen; 2957 fw.bss_index = 0; 2958 fw.bss = bnx_TPAT_b09FwBss; 2959 2960 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2961 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2962 fw.rodata_index = 0; 2963 fw.rodata = bnx_TPAT_b09FwRodata; 2964 2965 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2966 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2967 2968 /* Initialize the Completion Processor. */ 2969 cpu_reg.mode = BNX_COM_CPU_MODE; 2970 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2971 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2972 cpu_reg.state = BNX_COM_CPU_STATE; 2973 cpu_reg.state_value_clear = 0xffffff; 2974 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2975 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2976 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2977 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2978 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2979 cpu_reg.spad_base = BNX_COM_SCRATCH; 2980 cpu_reg.mips_view_base = 0x8000000; 2981 2982 fw.ver_major = bnx_COM_b09FwReleaseMajor; 2983 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 2984 fw.ver_fix = bnx_COM_b09FwReleaseFix; 2985 fw.start_addr = bnx_COM_b09FwStartAddr; 2986 2987 fw.text_addr = bnx_COM_b09FwTextAddr; 2988 fw.text_len = bnx_COM_b09FwTextLen; 2989 fw.text_index = 0; 2990 fw.text = bnx_COM_b09FwText; 2991 2992 fw.data_addr = bnx_COM_b09FwDataAddr; 2993 fw.data_len = bnx_COM_b09FwDataLen; 2994 fw.data_index = 0; 2995 fw.data = bnx_COM_b09FwData; 2996 2997 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 2998 fw.sbss_len = bnx_COM_b09FwSbssLen; 2999 fw.sbss_index = 0; 3000 fw.sbss = bnx_COM_b09FwSbss; 3001 3002 fw.bss_addr = bnx_COM_b09FwBssAddr; 3003 fw.bss_len = bnx_COM_b09FwBssLen; 3004 fw.bss_index = 0; 3005 fw.bss = bnx_COM_b09FwBss; 3006 3007 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3008 fw.rodata_len = bnx_COM_b09FwRodataLen; 3009 fw.rodata_index = 0; 3010 fw.rodata = bnx_COM_b09FwRodata; 3011 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3012 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3013 break; 3014 default: 3015 /* Initialize the RV2P processor. */ 3016 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3017 RV2P_PROC1); 3018 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3019 RV2P_PROC2); 3020 3021 /* Initialize the RX Processor. */ 3022 cpu_reg.mode = BNX_RXP_CPU_MODE; 3023 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3024 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3025 cpu_reg.state = BNX_RXP_CPU_STATE; 3026 cpu_reg.state_value_clear = 0xffffff; 3027 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3028 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3029 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3030 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3031 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3032 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3033 cpu_reg.mips_view_base = 0x8000000; 3034 3035 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3036 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3037 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3038 fw.start_addr = bnx_RXP_b06FwStartAddr; 3039 3040 fw.text_addr = bnx_RXP_b06FwTextAddr; 3041 fw.text_len = bnx_RXP_b06FwTextLen; 3042 fw.text_index = 0; 3043 fw.text = bnx_RXP_b06FwText; 3044 3045 fw.data_addr = bnx_RXP_b06FwDataAddr; 3046 fw.data_len = bnx_RXP_b06FwDataLen; 3047 fw.data_index = 0; 3048 fw.data = bnx_RXP_b06FwData; 3049 3050 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3051 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3052 fw.sbss_index = 0; 3053 fw.sbss = bnx_RXP_b06FwSbss; 3054 3055 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3056 fw.bss_len = bnx_RXP_b06FwBssLen; 3057 fw.bss_index = 0; 3058 fw.bss = bnx_RXP_b06FwBss; 3059 3060 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3061 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3062 fw.rodata_index = 0; 3063 fw.rodata = bnx_RXP_b06FwRodata; 3064 3065 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3066 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3067 3068 /* Initialize the TX Processor. */ 3069 cpu_reg.mode = BNX_TXP_CPU_MODE; 3070 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3071 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3072 cpu_reg.state = BNX_TXP_CPU_STATE; 3073 cpu_reg.state_value_clear = 0xffffff; 3074 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3075 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3076 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3077 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3078 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3079 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3080 cpu_reg.mips_view_base = 0x8000000; 3081 3082 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3083 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3084 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3085 fw.start_addr = bnx_TXP_b06FwStartAddr; 3086 3087 fw.text_addr = bnx_TXP_b06FwTextAddr; 3088 fw.text_len = bnx_TXP_b06FwTextLen; 3089 fw.text_index = 0; 3090 fw.text = bnx_TXP_b06FwText; 3091 3092 fw.data_addr = bnx_TXP_b06FwDataAddr; 3093 fw.data_len = bnx_TXP_b06FwDataLen; 3094 fw.data_index = 0; 3095 fw.data = bnx_TXP_b06FwData; 3096 3097 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3098 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3099 fw.sbss_index = 0; 3100 fw.sbss = bnx_TXP_b06FwSbss; 3101 3102 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3103 fw.bss_len = bnx_TXP_b06FwBssLen; 3104 fw.bss_index = 0; 3105 fw.bss = bnx_TXP_b06FwBss; 3106 3107 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3108 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3109 fw.rodata_index = 0; 3110 fw.rodata = bnx_TXP_b06FwRodata; 3111 3112 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3113 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3114 3115 /* Initialize the TX Patch-up Processor. */ 3116 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3117 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3118 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3119 cpu_reg.state = BNX_TPAT_CPU_STATE; 3120 cpu_reg.state_value_clear = 0xffffff; 3121 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3122 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3123 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3124 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3125 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3126 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3127 cpu_reg.mips_view_base = 0x8000000; 3128 3129 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3130 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3131 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3132 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3133 3134 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3135 fw.text_len = bnx_TPAT_b06FwTextLen; 3136 fw.text_index = 0; 3137 fw.text = bnx_TPAT_b06FwText; 3138 3139 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3140 fw.data_len = bnx_TPAT_b06FwDataLen; 3141 fw.data_index = 0; 3142 fw.data = bnx_TPAT_b06FwData; 3143 3144 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3145 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3146 fw.sbss_index = 0; 3147 fw.sbss = bnx_TPAT_b06FwSbss; 3148 3149 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3150 fw.bss_len = bnx_TPAT_b06FwBssLen; 3151 fw.bss_index = 0; 3152 fw.bss = bnx_TPAT_b06FwBss; 3153 3154 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3155 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3156 fw.rodata_index = 0; 3157 fw.rodata = bnx_TPAT_b06FwRodata; 3158 3159 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3160 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3161 3162 /* Initialize the Completion Processor. */ 3163 cpu_reg.mode = BNX_COM_CPU_MODE; 3164 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3165 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3166 cpu_reg.state = BNX_COM_CPU_STATE; 3167 cpu_reg.state_value_clear = 0xffffff; 3168 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3169 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3170 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3171 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3172 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3173 cpu_reg.spad_base = BNX_COM_SCRATCH; 3174 cpu_reg.mips_view_base = 0x8000000; 3175 3176 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3177 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3178 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3179 fw.start_addr = bnx_COM_b06FwStartAddr; 3180 3181 fw.text_addr = bnx_COM_b06FwTextAddr; 3182 fw.text_len = bnx_COM_b06FwTextLen; 3183 fw.text_index = 0; 3184 fw.text = bnx_COM_b06FwText; 3185 3186 fw.data_addr = bnx_COM_b06FwDataAddr; 3187 fw.data_len = bnx_COM_b06FwDataLen; 3188 fw.data_index = 0; 3189 fw.data = bnx_COM_b06FwData; 3190 3191 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3192 fw.sbss_len = bnx_COM_b06FwSbssLen; 3193 fw.sbss_index = 0; 3194 fw.sbss = bnx_COM_b06FwSbss; 3195 3196 fw.bss_addr = bnx_COM_b06FwBssAddr; 3197 fw.bss_len = bnx_COM_b06FwBssLen; 3198 fw.bss_index = 0; 3199 fw.bss = bnx_COM_b06FwBss; 3200 3201 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3202 fw.rodata_len = bnx_COM_b06FwRodataLen; 3203 fw.rodata_index = 0; 3204 fw.rodata = bnx_COM_b06FwRodata; 3205 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3206 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3207 break; 3208 } 3209 } 3210 3211 /****************************************************************************/ 3212 /* Initialize context memory. */ 3213 /* */ 3214 /* Clears the memory associated with each Context ID (CID). */ 3215 /* */ 3216 /* Returns: */ 3217 /* Nothing. */ 3218 /****************************************************************************/ 3219 void 3220 bnx_init_context(struct bnx_softc *sc) 3221 { 3222 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3223 /* DRC: Replace this constant value with a #define. */ 3224 int i, retry_cnt = 10; 3225 uint32_t val; 3226 3227 /* 3228 * BCM5709 context memory may be cached 3229 * in host memory so prepare the host memory 3230 * for access. 3231 */ 3232 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3233 | (1 << 12); 3234 val |= (BCM_PAGE_BITS - 8) << 16; 3235 REG_WR(sc, BNX_CTX_COMMAND, val); 3236 3237 /* Wait for mem init command to complete. */ 3238 for (i = 0; i < retry_cnt; i++) { 3239 val = REG_RD(sc, BNX_CTX_COMMAND); 3240 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3241 break; 3242 DELAY(2); 3243 } 3244 3245 /* ToDo: Consider returning an error here. */ 3246 3247 for (i = 0; i < sc->ctx_pages; i++) { 3248 int j; 3249 3250 /* Set the physaddr of the context memory cache. */ 3251 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3252 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3253 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3254 val = (uint32_t) 3255 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3256 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3257 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3258 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3259 3260 /* Verify that the context memory write was successful. */ 3261 for (j = 0; j < retry_cnt; j++) { 3262 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3263 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3264 break; 3265 DELAY(5); 3266 } 3267 3268 /* ToDo: Consider returning an error here. */ 3269 } 3270 } else { 3271 uint32_t vcid_addr, offset; 3272 3273 /* 3274 * For the 5706/5708, context memory is local to 3275 * the controller, so initialize the controller 3276 * context memory. 3277 */ 3278 3279 vcid_addr = GET_CID_ADDR(96); 3280 while (vcid_addr) { 3281 3282 vcid_addr -= BNX_PHY_CTX_SIZE; 3283 3284 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3285 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3286 3287 for(offset = 0; offset < BNX_PHY_CTX_SIZE; offset += 4) { 3288 CTX_WR(sc, 0x00, offset, 0); 3289 } 3290 3291 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3292 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3293 } 3294 } 3295 } 3296 3297 /****************************************************************************/ 3298 /* Fetch the permanent MAC address of the controller. */ 3299 /* */ 3300 /* Returns: */ 3301 /* Nothing. */ 3302 /****************************************************************************/ 3303 void 3304 bnx_get_mac_addr(struct bnx_softc *sc) 3305 { 3306 uint32_t mac_lo = 0, mac_hi = 0; 3307 3308 /* 3309 * The NetXtreme II bootcode populates various NIC 3310 * power-on and runtime configuration items in a 3311 * shared memory area. The factory configured MAC 3312 * address is available from both NVRAM and the 3313 * shared memory area so we'll read the value from 3314 * shared memory for speed. 3315 */ 3316 3317 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3318 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3319 3320 if ((mac_lo == 0) && (mac_hi == 0)) { 3321 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3322 __FILE__, __LINE__); 3323 } else { 3324 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3325 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3326 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3327 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3328 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3329 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3330 } 3331 3332 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3333 "%s\n", ether_sprintf(sc->eaddr)); 3334 } 3335 3336 /****************************************************************************/ 3337 /* Program the MAC address. */ 3338 /* */ 3339 /* Returns: */ 3340 /* Nothing. */ 3341 /****************************************************************************/ 3342 void 3343 bnx_set_mac_addr(struct bnx_softc *sc) 3344 { 3345 uint32_t val; 3346 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3347 3348 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3349 "%s\n", ether_sprintf(sc->eaddr)); 3350 3351 val = (mac_addr[0] << 8) | mac_addr[1]; 3352 3353 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3354 3355 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3356 (mac_addr[4] << 8) | mac_addr[5]; 3357 3358 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3359 } 3360 3361 /****************************************************************************/ 3362 /* Stop the controller. */ 3363 /* */ 3364 /* Returns: */ 3365 /* Nothing. */ 3366 /****************************************************************************/ 3367 void 3368 bnx_stop(struct ifnet *ifp, int disable) 3369 { 3370 struct bnx_softc *sc = ifp->if_softc; 3371 3372 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3373 3374 if ((ifp->if_flags & IFF_RUNNING) == 0) 3375 return; 3376 3377 callout_stop(&sc->bnx_timeout); 3378 3379 mii_down(&sc->bnx_mii); 3380 3381 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3382 3383 /* Disable the transmit/receive blocks. */ 3384 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3385 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3386 DELAY(20); 3387 3388 bnx_disable_intr(sc); 3389 3390 /* Tell firmware that the driver is going away. */ 3391 if (disable) 3392 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3393 else 3394 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3395 3396 /* Free RX buffers. */ 3397 bnx_free_rx_chain(sc); 3398 3399 /* Free TX buffers. */ 3400 bnx_free_tx_chain(sc); 3401 3402 ifp->if_timer = 0; 3403 3404 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3405 3406 } 3407 3408 int 3409 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3410 { 3411 struct pci_attach_args *pa = &(sc->bnx_pa); 3412 uint32_t val; 3413 int i, rc = 0; 3414 3415 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3416 3417 /* Wait for pending PCI transactions to complete. */ 3418 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3419 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3420 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3421 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3422 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3423 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3424 DELAY(5); 3425 3426 /* Disable DMA */ 3427 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3428 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3429 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3430 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3431 } 3432 3433 /* Assume bootcode is running. */ 3434 sc->bnx_fw_timed_out = 0; 3435 3436 /* Give the firmware a chance to prepare for the reset. */ 3437 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3438 if (rc) 3439 goto bnx_reset_exit; 3440 3441 /* Set a firmware reminder that this is a soft reset. */ 3442 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3443 BNX_DRV_RESET_SIGNATURE_MAGIC); 3444 3445 /* Dummy read to force the chip to complete all current transactions. */ 3446 val = REG_RD(sc, BNX_MISC_ID); 3447 3448 /* Chip reset. */ 3449 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3450 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3451 REG_RD(sc, BNX_MISC_COMMAND); 3452 DELAY(5); 3453 3454 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3455 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3456 3457 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3458 val); 3459 } else { 3460 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3461 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3462 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3463 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3464 3465 /* Allow up to 30us for reset to complete. */ 3466 for (i = 0; i < 10; i++) { 3467 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3468 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3469 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3470 break; 3471 } 3472 DELAY(10); 3473 } 3474 3475 /* Check that reset completed successfully. */ 3476 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3477 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3478 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3479 __FILE__, __LINE__); 3480 rc = EBUSY; 3481 goto bnx_reset_exit; 3482 } 3483 } 3484 3485 /* Make sure byte swapping is properly configured. */ 3486 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3487 if (val != 0x01020304) { 3488 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3489 __FILE__, __LINE__); 3490 rc = ENODEV; 3491 goto bnx_reset_exit; 3492 } 3493 3494 /* Just completed a reset, assume that firmware is running again. */ 3495 sc->bnx_fw_timed_out = 0; 3496 3497 /* Wait for the firmware to finish its initialization. */ 3498 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3499 if (rc) 3500 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3501 "initialization!\n", __FILE__, __LINE__); 3502 3503 bnx_reset_exit: 3504 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3505 3506 return rc; 3507 } 3508 3509 int 3510 bnx_chipinit(struct bnx_softc *sc) 3511 { 3512 struct pci_attach_args *pa = &(sc->bnx_pa); 3513 uint32_t val; 3514 int rc = 0; 3515 3516 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3517 3518 /* Make sure the interrupt is not active. */ 3519 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3520 3521 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3522 /* channels and PCI clock compensation delay. */ 3523 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3524 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3525 #if BYTE_ORDER == BIG_ENDIAN 3526 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3527 #endif 3528 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3529 DMA_READ_CHANS << 12 | 3530 DMA_WRITE_CHANS << 16; 3531 3532 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3533 3534 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3535 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3536 3537 /* 3538 * This setting resolves a problem observed on certain Intel PCI 3539 * chipsets that cannot handle multiple outstanding DMA operations. 3540 * See errata E9_5706A1_65. 3541 */ 3542 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3543 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3544 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3545 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3546 3547 REG_WR(sc, BNX_DMA_CONFIG, val); 3548 3549 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3550 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3551 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3552 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3553 val & ~0x20000); 3554 } 3555 3556 /* Enable the RX_V2P and Context state machines before access. */ 3557 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3558 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3559 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3560 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3561 3562 /* Initialize context mapping and zero out the quick contexts. */ 3563 bnx_init_context(sc); 3564 3565 /* Initialize the on-boards CPUs */ 3566 bnx_init_cpus(sc); 3567 3568 /* Prepare NVRAM for access. */ 3569 if (bnx_init_nvram(sc)) { 3570 rc = ENODEV; 3571 goto bnx_chipinit_exit; 3572 } 3573 3574 /* Set the kernel bypass block size */ 3575 val = REG_RD(sc, BNX_MQ_CONFIG); 3576 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3577 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3578 3579 /* Enable bins used on the 5709. */ 3580 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3581 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3582 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3583 val |= BNX_MQ_CONFIG_HALT_DIS; 3584 } 3585 3586 REG_WR(sc, BNX_MQ_CONFIG, val); 3587 3588 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3589 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3590 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3591 3592 val = (BCM_PAGE_BITS - 8) << 24; 3593 REG_WR(sc, BNX_RV2P_CONFIG, val); 3594 3595 /* Configure page size. */ 3596 val = REG_RD(sc, BNX_TBDR_CONFIG); 3597 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3598 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3599 REG_WR(sc, BNX_TBDR_CONFIG, val); 3600 3601 #if 0 3602 /* Set the perfect match control register to default. */ 3603 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3604 #endif 3605 3606 bnx_chipinit_exit: 3607 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3608 3609 return rc; 3610 } 3611 3612 /****************************************************************************/ 3613 /* Initialize the controller in preparation to send/receive traffic. */ 3614 /* */ 3615 /* Returns: */ 3616 /* 0 for success, positive value for failure. */ 3617 /****************************************************************************/ 3618 int 3619 bnx_blockinit(struct bnx_softc *sc) 3620 { 3621 uint32_t reg, val; 3622 int rc = 0; 3623 3624 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3625 3626 /* Load the hardware default MAC address. */ 3627 bnx_set_mac_addr(sc); 3628 3629 /* Set the Ethernet backoff seed value */ 3630 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3631 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3632 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3633 3634 sc->last_status_idx = 0; 3635 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3636 3637 /* Set up link change interrupt generation. */ 3638 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3639 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3640 3641 /* Program the physical address of the status block. */ 3642 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3643 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3644 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3645 3646 /* Program the physical address of the statistics block. */ 3647 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3648 (uint32_t)(sc->stats_block_paddr)); 3649 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3650 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3651 3652 /* Program various host coalescing parameters. */ 3653 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3654 << 16) | sc->bnx_tx_quick_cons_trip); 3655 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3656 << 16) | sc->bnx_rx_quick_cons_trip); 3657 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3658 sc->bnx_comp_prod_trip); 3659 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3660 sc->bnx_tx_ticks); 3661 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3662 sc->bnx_rx_ticks); 3663 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3664 sc->bnx_com_ticks); 3665 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3666 sc->bnx_cmd_ticks); 3667 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3668 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3669 REG_WR(sc, BNX_HC_CONFIG, 3670 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3671 BNX_HC_CONFIG_COLLECT_STATS)); 3672 3673 /* Clear the internal statistics counters. */ 3674 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3675 3676 /* Verify that bootcode is running. */ 3677 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3678 3679 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3680 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3681 __FILE__, __LINE__); reg = 0); 3682 3683 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3684 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3685 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3686 "Expected: 08%08X\n", __FILE__, __LINE__, 3687 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3688 BNX_DEV_INFO_SIGNATURE_MAGIC); 3689 rc = ENODEV; 3690 goto bnx_blockinit_exit; 3691 } 3692 3693 /* Check if any management firmware is running. */ 3694 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3695 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3696 BNX_PORT_FEATURE_IMD_ENABLED)) { 3697 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3698 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3699 } 3700 3701 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3702 BNX_DEV_INFO_BC_REV); 3703 3704 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3705 3706 /* Enable DMA */ 3707 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3708 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3709 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3710 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3711 } 3712 3713 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3714 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3715 3716 /* Enable link state change interrupt generation. */ 3717 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3718 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3719 BNX_MISC_ENABLE_DEFAULT_XI); 3720 } else 3721 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3722 3723 /* Enable all remaining blocks in the MAC. */ 3724 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3725 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3726 DELAY(20); 3727 3728 bnx_blockinit_exit: 3729 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3730 3731 return rc; 3732 } 3733 3734 static int 3735 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3736 uint16_t *chain_prod, uint32_t *prod_bseq) 3737 { 3738 bus_dmamap_t map; 3739 struct rx_bd *rxbd; 3740 uint32_t addr; 3741 int i; 3742 #ifdef BNX_DEBUG 3743 uint16_t debug_chain_prod = *chain_prod; 3744 #endif 3745 uint16_t first_chain_prod; 3746 3747 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3748 3749 /* Map the mbuf cluster into device memory. */ 3750 map = sc->rx_mbuf_map[*chain_prod]; 3751 first_chain_prod = *chain_prod; 3752 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3753 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3754 __FILE__, __LINE__); 3755 3756 m_freem(m_new); 3757 3758 DBRUNIF(1, sc->rx_mbuf_alloc--); 3759 3760 return ENOBUFS; 3761 } 3762 /* Make sure there is room in the receive chain. */ 3763 if (map->dm_nsegs > sc->free_rx_bd) { 3764 bus_dmamap_unload(sc->bnx_dmatag, map); 3765 m_freem(m_new); 3766 return EFBIG; 3767 } 3768 #ifdef BNX_DEBUG 3769 /* Track the distribution of buffer segments. */ 3770 sc->rx_mbuf_segs[map->dm_nsegs]++; 3771 #endif 3772 3773 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3774 BUS_DMASYNC_PREREAD); 3775 3776 /* Update some debug statistics counters */ 3777 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3778 sc->rx_low_watermark = sc->free_rx_bd); 3779 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3780 3781 /* 3782 * Setup the rx_bd for the first segment 3783 */ 3784 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3785 3786 addr = (uint32_t)map->dm_segs[0].ds_addr; 3787 rxbd->rx_bd_haddr_lo = addr; 3788 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3789 rxbd->rx_bd_haddr_hi = addr; 3790 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3791 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3792 *prod_bseq += map->dm_segs[0].ds_len; 3793 bus_dmamap_sync(sc->bnx_dmatag, 3794 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3795 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3796 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3797 3798 for (i = 1; i < map->dm_nsegs; i++) { 3799 *prod = NEXT_RX_BD(*prod); 3800 *chain_prod = RX_CHAIN_IDX(*prod); 3801 3802 rxbd = 3803 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3804 3805 addr = (uint32_t)map->dm_segs[i].ds_addr; 3806 rxbd->rx_bd_haddr_lo = addr; 3807 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3808 rxbd->rx_bd_haddr_hi = addr; 3809 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3810 rxbd->rx_bd_flags = 0; 3811 *prod_bseq += map->dm_segs[i].ds_len; 3812 bus_dmamap_sync(sc->bnx_dmatag, 3813 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3814 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3815 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3816 } 3817 3818 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3819 bus_dmamap_sync(sc->bnx_dmatag, 3820 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3821 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3822 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3823 3824 /* 3825 * Save the mbuf, adjust the map pointer (swap map for first and 3826 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3827 * and update our counter. 3828 */ 3829 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3830 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3831 sc->rx_mbuf_map[*chain_prod] = map; 3832 sc->free_rx_bd -= map->dm_nsegs; 3833 3834 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3835 map->dm_nsegs)); 3836 *prod = NEXT_RX_BD(*prod); 3837 *chain_prod = RX_CHAIN_IDX(*prod); 3838 3839 return 0; 3840 } 3841 3842 /****************************************************************************/ 3843 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3844 /* */ 3845 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3846 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3847 /* necessary. */ 3848 /* */ 3849 /* Returns: */ 3850 /* 0 for success, positive value for failure. */ 3851 /****************************************************************************/ 3852 int 3853 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3854 uint16_t *chain_prod, uint32_t *prod_bseq) 3855 { 3856 struct mbuf *m_new = NULL; 3857 int rc = 0; 3858 uint16_t min_free_bd; 3859 3860 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3861 __func__); 3862 3863 /* Make sure the inputs are valid. */ 3864 DBRUNIF((*chain_prod > MAX_RX_BD), 3865 aprint_error_dev(sc->bnx_dev, 3866 "RX producer out of range: 0x%04X > 0x%04X\n", 3867 *chain_prod, (uint16_t)MAX_RX_BD)); 3868 3869 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3870 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3871 *prod_bseq); 3872 3873 /* try to get in as many mbufs as possible */ 3874 if (sc->mbuf_alloc_size == MCLBYTES) 3875 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3876 else 3877 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3878 while (sc->free_rx_bd >= min_free_bd) { 3879 /* Simulate an mbuf allocation failure. */ 3880 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3881 aprint_error_dev(sc->bnx_dev, 3882 "Simulating mbuf allocation failure.\n"); 3883 sc->mbuf_sim_alloc_failed++; 3884 rc = ENOBUFS; 3885 goto bnx_get_buf_exit); 3886 3887 /* This is a new mbuf allocation. */ 3888 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3889 if (m_new == NULL) { 3890 DBPRINT(sc, BNX_WARN, 3891 "%s(%d): RX mbuf header allocation failed!\n", 3892 __FILE__, __LINE__); 3893 3894 sc->mbuf_alloc_failed++; 3895 3896 rc = ENOBUFS; 3897 goto bnx_get_buf_exit; 3898 } 3899 3900 DBRUNIF(1, sc->rx_mbuf_alloc++); 3901 3902 /* Simulate an mbuf cluster allocation failure. */ 3903 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3904 m_freem(m_new); 3905 sc->rx_mbuf_alloc--; 3906 sc->mbuf_alloc_failed++; 3907 sc->mbuf_sim_alloc_failed++; 3908 rc = ENOBUFS; 3909 goto bnx_get_buf_exit); 3910 3911 if (sc->mbuf_alloc_size == MCLBYTES) 3912 MCLGET(m_new, M_DONTWAIT); 3913 else 3914 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3915 M_DONTWAIT); 3916 if (!(m_new->m_flags & M_EXT)) { 3917 DBPRINT(sc, BNX_WARN, 3918 "%s(%d): RX mbuf chain allocation failed!\n", 3919 __FILE__, __LINE__); 3920 3921 m_freem(m_new); 3922 3923 DBRUNIF(1, sc->rx_mbuf_alloc--); 3924 sc->mbuf_alloc_failed++; 3925 3926 rc = ENOBUFS; 3927 goto bnx_get_buf_exit; 3928 } 3929 3930 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3931 if (rc != 0) 3932 goto bnx_get_buf_exit; 3933 } 3934 3935 bnx_get_buf_exit: 3936 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3937 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3938 *chain_prod, *prod_bseq); 3939 3940 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3941 __func__); 3942 3943 return rc; 3944 } 3945 3946 void 3947 bnx_alloc_pkts(struct work * unused, void * arg) 3948 { 3949 struct bnx_softc *sc = arg; 3950 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3951 struct bnx_pkt *pkt; 3952 int i, s; 3953 3954 for (i = 0; i < 4; i++) { /* magic! */ 3955 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 3956 if (pkt == NULL) 3957 break; 3958 3959 if (bus_dmamap_create(sc->bnx_dmatag, 3960 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3961 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3962 &pkt->pkt_dmamap) != 0) 3963 goto put; 3964 3965 if (!ISSET(ifp->if_flags, IFF_UP)) 3966 goto stopping; 3967 3968 mutex_enter(&sc->tx_pkt_mtx); 3969 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3970 sc->tx_pkt_count++; 3971 mutex_exit(&sc->tx_pkt_mtx); 3972 } 3973 3974 mutex_enter(&sc->tx_pkt_mtx); 3975 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 3976 mutex_exit(&sc->tx_pkt_mtx); 3977 3978 /* fire-up TX now that allocations have been done */ 3979 s = splnet(); 3980 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3981 bnx_start(ifp); 3982 splx(s); 3983 3984 return; 3985 3986 stopping: 3987 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3988 put: 3989 pool_put(bnx_tx_pool, pkt); 3990 return; 3991 } 3992 3993 /****************************************************************************/ 3994 /* Initialize the TX context memory. */ 3995 /* */ 3996 /* Returns: */ 3997 /* Nothing */ 3998 /****************************************************************************/ 3999 void 4000 bnx_init_tx_context(struct bnx_softc *sc) 4001 { 4002 uint32_t val; 4003 4004 /* Initialize the context ID for an L2 TX chain. */ 4005 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4006 /* Set the CID type to support an L2 connection. */ 4007 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4008 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4009 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4010 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4011 4012 /* Point the hardware to the first page in the chain. */ 4013 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4014 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4015 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4016 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4017 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4018 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4019 } else { 4020 /* Set the CID type to support an L2 connection. */ 4021 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4022 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4023 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4024 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4025 4026 /* Point the hardware to the first page in the chain. */ 4027 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4028 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4029 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4030 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4031 } 4032 } 4033 4034 4035 /****************************************************************************/ 4036 /* Allocate memory and initialize the TX data structures. */ 4037 /* */ 4038 /* Returns: */ 4039 /* 0 for success, positive value for failure. */ 4040 /****************************************************************************/ 4041 int 4042 bnx_init_tx_chain(struct bnx_softc *sc) 4043 { 4044 struct tx_bd *txbd; 4045 uint32_t addr; 4046 int i, rc = 0; 4047 4048 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4049 4050 /* Force an allocation of some dmamaps for tx up front */ 4051 bnx_alloc_pkts(NULL, sc); 4052 4053 /* Set the initial TX producer/consumer indices. */ 4054 sc->tx_prod = 0; 4055 sc->tx_cons = 0; 4056 sc->tx_prod_bseq = 0; 4057 sc->used_tx_bd = 0; 4058 sc->max_tx_bd = USABLE_TX_BD; 4059 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4060 DBRUNIF(1, sc->tx_full_count = 0); 4061 4062 /* 4063 * The NetXtreme II supports a linked-list structure called 4064 * a Buffer Descriptor Chain (or BD chain). A BD chain 4065 * consists of a series of 1 or more chain pages, each of which 4066 * consists of a fixed number of BD entries. 4067 * The last BD entry on each page is a pointer to the next page 4068 * in the chain, and the last pointer in the BD chain 4069 * points back to the beginning of the chain. 4070 */ 4071 4072 /* Set the TX next pointer chain entries. */ 4073 for (i = 0; i < TX_PAGES; i++) { 4074 int j; 4075 4076 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4077 4078 /* Check if we've reached the last page. */ 4079 if (i == (TX_PAGES - 1)) 4080 j = 0; 4081 else 4082 j = i + 1; 4083 4084 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4085 txbd->tx_bd_haddr_lo = addr; 4086 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4087 txbd->tx_bd_haddr_hi = addr; 4088 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4089 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4090 } 4091 4092 /* 4093 * Initialize the context ID for an L2 TX chain. 4094 */ 4095 bnx_init_tx_context(sc); 4096 4097 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4098 4099 return rc; 4100 } 4101 4102 /****************************************************************************/ 4103 /* Free memory and clear the TX data structures. */ 4104 /* */ 4105 /* Returns: */ 4106 /* Nothing. */ 4107 /****************************************************************************/ 4108 void 4109 bnx_free_tx_chain(struct bnx_softc *sc) 4110 { 4111 struct bnx_pkt *pkt; 4112 int i; 4113 4114 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4115 4116 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4117 mutex_enter(&sc->tx_pkt_mtx); 4118 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4119 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4120 mutex_exit(&sc->tx_pkt_mtx); 4121 4122 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4123 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4124 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4125 4126 m_freem(pkt->pkt_mbuf); 4127 DBRUNIF(1, sc->tx_mbuf_alloc--); 4128 4129 mutex_enter(&sc->tx_pkt_mtx); 4130 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4131 } 4132 4133 /* Destroy all the dmamaps we allocated for TX */ 4134 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4135 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4136 sc->tx_pkt_count--; 4137 mutex_exit(&sc->tx_pkt_mtx); 4138 4139 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4140 pool_put(bnx_tx_pool, pkt); 4141 4142 mutex_enter(&sc->tx_pkt_mtx); 4143 } 4144 mutex_exit(&sc->tx_pkt_mtx); 4145 4146 4147 4148 /* Clear each TX chain page. */ 4149 for (i = 0; i < TX_PAGES; i++) { 4150 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4151 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4152 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4153 } 4154 4155 sc->used_tx_bd = 0; 4156 4157 /* Check if we lost any mbufs in the process. */ 4158 DBRUNIF((sc->tx_mbuf_alloc), 4159 aprint_error_dev(sc->bnx_dev, 4160 "Memory leak! Lost %d mbufs from tx chain!\n", 4161 sc->tx_mbuf_alloc)); 4162 4163 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4164 } 4165 4166 /****************************************************************************/ 4167 /* Initialize the RX context memory. */ 4168 /* */ 4169 /* Returns: */ 4170 /* Nothing */ 4171 /****************************************************************************/ 4172 void 4173 bnx_init_rx_context(struct bnx_softc *sc) 4174 { 4175 uint32_t val; 4176 4177 /* Initialize the context ID for an L2 RX chain. */ 4178 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4179 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4180 4181 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4182 uint32_t lo_water, hi_water; 4183 4184 lo_water = BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT; 4185 hi_water = USABLE_RX_BD / 4; 4186 4187 lo_water /= BNX_L2CTX_RX_LO_WATER_MARK_SCALE; 4188 hi_water /= BNX_L2CTX_RX_HI_WATER_MARK_SCALE; 4189 4190 if (hi_water > 0xf) 4191 hi_water = 0xf; 4192 else if (hi_water == 0) 4193 lo_water = 0; 4194 val |= lo_water | 4195 (hi_water << BNX_L2CTX_RX_HI_WATER_MARK_SHIFT); 4196 } 4197 4198 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4199 4200 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4201 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4202 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4203 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4204 } 4205 4206 /* Point the hardware to the first page in the chain. */ 4207 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4208 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4209 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4210 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4211 } 4212 4213 /****************************************************************************/ 4214 /* Allocate memory and initialize the RX data structures. */ 4215 /* */ 4216 /* Returns: */ 4217 /* 0 for success, positive value for failure. */ 4218 /****************************************************************************/ 4219 int 4220 bnx_init_rx_chain(struct bnx_softc *sc) 4221 { 4222 struct rx_bd *rxbd; 4223 int i, rc = 0; 4224 uint16_t prod, chain_prod; 4225 uint32_t prod_bseq, addr; 4226 4227 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4228 4229 /* Initialize the RX producer and consumer indices. */ 4230 sc->rx_prod = 0; 4231 sc->rx_cons = 0; 4232 sc->rx_prod_bseq = 0; 4233 sc->free_rx_bd = USABLE_RX_BD; 4234 sc->max_rx_bd = USABLE_RX_BD; 4235 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4236 DBRUNIF(1, sc->rx_empty_count = 0); 4237 4238 /* Initialize the RX next pointer chain entries. */ 4239 for (i = 0; i < RX_PAGES; i++) { 4240 int j; 4241 4242 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4243 4244 /* Check if we've reached the last page. */ 4245 if (i == (RX_PAGES - 1)) 4246 j = 0; 4247 else 4248 j = i + 1; 4249 4250 /* Setup the chain page pointers. */ 4251 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4252 rxbd->rx_bd_haddr_hi = addr; 4253 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4254 rxbd->rx_bd_haddr_lo = addr; 4255 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4256 0, BNX_RX_CHAIN_PAGE_SZ, 4257 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4258 } 4259 4260 /* Allocate mbuf clusters for the rx_bd chain. */ 4261 prod = prod_bseq = 0; 4262 chain_prod = RX_CHAIN_IDX(prod); 4263 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4264 BNX_PRINTF(sc, 4265 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4266 } 4267 4268 /* Save the RX chain producer index. */ 4269 sc->rx_prod = prod; 4270 sc->rx_prod_bseq = prod_bseq; 4271 4272 for (i = 0; i < RX_PAGES; i++) 4273 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4274 sc->rx_bd_chain_map[i]->dm_mapsize, 4275 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4276 4277 /* Tell the chip about the waiting rx_bd's. */ 4278 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4279 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4280 4281 bnx_init_rx_context(sc); 4282 4283 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4284 4285 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4286 4287 return rc; 4288 } 4289 4290 /****************************************************************************/ 4291 /* Free memory and clear the RX data structures. */ 4292 /* */ 4293 /* Returns: */ 4294 /* Nothing. */ 4295 /****************************************************************************/ 4296 void 4297 bnx_free_rx_chain(struct bnx_softc *sc) 4298 { 4299 int i; 4300 4301 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4302 4303 /* Free any mbufs still in the RX mbuf chain. */ 4304 for (i = 0; i < TOTAL_RX_BD; i++) { 4305 if (sc->rx_mbuf_ptr[i] != NULL) { 4306 if (sc->rx_mbuf_map[i] != NULL) { 4307 bus_dmamap_sync(sc->bnx_dmatag, 4308 sc->rx_mbuf_map[i], 0, 4309 sc->rx_mbuf_map[i]->dm_mapsize, 4310 BUS_DMASYNC_POSTREAD); 4311 bus_dmamap_unload(sc->bnx_dmatag, 4312 sc->rx_mbuf_map[i]); 4313 } 4314 m_freem(sc->rx_mbuf_ptr[i]); 4315 sc->rx_mbuf_ptr[i] = NULL; 4316 DBRUNIF(1, sc->rx_mbuf_alloc--); 4317 } 4318 } 4319 4320 /* Clear each RX chain page. */ 4321 for (i = 0; i < RX_PAGES; i++) 4322 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4323 4324 sc->free_rx_bd = sc->max_rx_bd; 4325 4326 /* Check if we lost any mbufs in the process. */ 4327 DBRUNIF((sc->rx_mbuf_alloc), 4328 aprint_error_dev(sc->bnx_dev, 4329 "Memory leak! Lost %d mbufs from rx chain!\n", 4330 sc->rx_mbuf_alloc)); 4331 4332 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4333 } 4334 4335 /****************************************************************************/ 4336 /* Handles PHY generated interrupt events. */ 4337 /* */ 4338 /* Returns: */ 4339 /* Nothing. */ 4340 /****************************************************************************/ 4341 void 4342 bnx_phy_intr(struct bnx_softc *sc) 4343 { 4344 uint32_t new_link_state, old_link_state; 4345 4346 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4347 BUS_DMASYNC_POSTREAD); 4348 new_link_state = sc->status_block->status_attn_bits & 4349 STATUS_ATTN_BITS_LINK_STATE; 4350 old_link_state = sc->status_block->status_attn_bits_ack & 4351 STATUS_ATTN_BITS_LINK_STATE; 4352 4353 /* Handle any changes if the link state has changed. */ 4354 if (new_link_state != old_link_state) { 4355 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4356 4357 callout_stop(&sc->bnx_timeout); 4358 bnx_tick(sc); 4359 4360 /* Update the status_attn_bits_ack field in the status block. */ 4361 if (new_link_state) { 4362 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4363 STATUS_ATTN_BITS_LINK_STATE); 4364 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4365 } else { 4366 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4367 STATUS_ATTN_BITS_LINK_STATE); 4368 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4369 } 4370 } 4371 4372 /* Acknowledge the link change interrupt. */ 4373 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4374 } 4375 4376 /****************************************************************************/ 4377 /* Handles received frame interrupt events. */ 4378 /* */ 4379 /* Returns: */ 4380 /* Nothing. */ 4381 /****************************************************************************/ 4382 void 4383 bnx_rx_intr(struct bnx_softc *sc) 4384 { 4385 struct status_block *sblk = sc->status_block; 4386 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4387 uint16_t hw_cons, sw_cons, sw_chain_cons; 4388 uint16_t sw_prod, sw_chain_prod; 4389 uint32_t sw_prod_bseq; 4390 struct l2_fhdr *l2fhdr; 4391 int i; 4392 4393 DBRUNIF(1, sc->rx_interrupts++); 4394 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4395 BUS_DMASYNC_POSTREAD); 4396 4397 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4398 for (i = 0; i < RX_PAGES; i++) 4399 bus_dmamap_sync(sc->bnx_dmatag, 4400 sc->rx_bd_chain_map[i], 0, 4401 sc->rx_bd_chain_map[i]->dm_mapsize, 4402 BUS_DMASYNC_POSTWRITE); 4403 4404 /* Get the hardware's view of the RX consumer index. */ 4405 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4406 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4407 hw_cons++; 4408 4409 /* Get working copies of the driver's view of the RX indices. */ 4410 sw_cons = sc->rx_cons; 4411 sw_prod = sc->rx_prod; 4412 sw_prod_bseq = sc->rx_prod_bseq; 4413 4414 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4415 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4416 __func__, sw_prod, sw_cons, sw_prod_bseq); 4417 4418 /* Prevent speculative reads from getting ahead of the status block. */ 4419 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4420 BUS_SPACE_BARRIER_READ); 4421 4422 /* Update some debug statistics counters */ 4423 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4424 sc->rx_low_watermark = sc->free_rx_bd); 4425 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4426 4427 /* 4428 * Scan through the receive chain as long 4429 * as there is work to do. 4430 */ 4431 while (sw_cons != hw_cons) { 4432 struct mbuf *m; 4433 struct rx_bd *rxbd __diagused; 4434 unsigned int len; 4435 uint32_t status; 4436 4437 /* Convert the producer/consumer indices to an actual 4438 * rx_bd index. 4439 */ 4440 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4441 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4442 4443 /* Get the used rx_bd. */ 4444 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4445 sc->free_rx_bd++; 4446 4447 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4448 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4449 4450 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4451 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4452 #ifdef DIAGNOSTIC 4453 /* Validate that this is the last rx_bd. */ 4454 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4455 printf("%s: Unexpected mbuf found in " 4456 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4457 sw_chain_cons); 4458 } 4459 #endif 4460 4461 /* DRC - ToDo: If the received packet is small, say less 4462 * than 128 bytes, allocate a new mbuf here, 4463 * copy the data to that mbuf, and recycle 4464 * the mapped jumbo frame. 4465 */ 4466 4467 /* Unmap the mbuf from DMA space. */ 4468 #ifdef DIAGNOSTIC 4469 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4470 printf("invalid map sw_cons 0x%x " 4471 "sw_prod 0x%x " 4472 "sw_chain_cons 0x%x " 4473 "sw_chain_prod 0x%x " 4474 "hw_cons 0x%x " 4475 "TOTAL_RX_BD_PER_PAGE 0x%x " 4476 "TOTAL_RX_BD 0x%x\n", 4477 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4478 hw_cons, 4479 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4480 } 4481 #endif 4482 bus_dmamap_sync(sc->bnx_dmatag, 4483 sc->rx_mbuf_map[sw_chain_cons], 0, 4484 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4485 BUS_DMASYNC_POSTREAD); 4486 bus_dmamap_unload(sc->bnx_dmatag, 4487 sc->rx_mbuf_map[sw_chain_cons]); 4488 4489 /* Remove the mbuf from the driver's chain. */ 4490 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4491 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4492 4493 /* 4494 * Frames received on the NetXteme II are prepended 4495 * with the l2_fhdr structure which provides status 4496 * information about the received frame (including 4497 * VLAN tags and checksum info) and are also 4498 * automatically adjusted to align the IP header 4499 * (i.e. two null bytes are inserted before the 4500 * Ethernet header). 4501 */ 4502 l2fhdr = mtod(m, struct l2_fhdr *); 4503 4504 len = l2fhdr->l2_fhdr_pkt_len; 4505 status = l2fhdr->l2_fhdr_status; 4506 4507 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4508 aprint_error("Simulating l2_fhdr status error.\n"); 4509 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4510 4511 /* Watch for unusual sized frames. */ 4512 DBRUNIF(((len < BNX_MIN_MTU) || 4513 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4514 aprint_error_dev(sc->bnx_dev, 4515 "Unusual frame size found. " 4516 "Min(%d), Actual(%d), Max(%d)\n", 4517 (int)BNX_MIN_MTU, len, 4518 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4519 4520 bnx_dump_mbuf(sc, m); 4521 bnx_breakpoint(sc)); 4522 4523 len -= ETHER_CRC_LEN; 4524 4525 /* Check the received frame for errors. */ 4526 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4527 L2_FHDR_ERRORS_PHY_DECODE | 4528 L2_FHDR_ERRORS_ALIGNMENT | 4529 L2_FHDR_ERRORS_TOO_SHORT | 4530 L2_FHDR_ERRORS_GIANT_FRAME)) || 4531 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4532 len > 4533 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4534 ifp->if_ierrors++; 4535 DBRUNIF(1, sc->l2fhdr_status_errors++); 4536 4537 /* Reuse the mbuf for a new frame. */ 4538 if (bnx_add_buf(sc, m, &sw_prod, 4539 &sw_chain_prod, &sw_prod_bseq)) { 4540 DBRUNIF(1, bnx_breakpoint(sc)); 4541 panic("%s: Can't reuse RX mbuf!\n", 4542 device_xname(sc->bnx_dev)); 4543 } 4544 continue; 4545 } 4546 4547 /* 4548 * Get a new mbuf for the rx_bd. If no new 4549 * mbufs are available then reuse the current mbuf, 4550 * log an ierror on the interface, and generate 4551 * an error in the system log. 4552 */ 4553 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4554 &sw_prod_bseq)) { 4555 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4556 "Failed to allocate " 4557 "new mbuf, incoming frame dropped!\n")); 4558 4559 ifp->if_ierrors++; 4560 4561 /* Try and reuse the exisitng mbuf. */ 4562 if (bnx_add_buf(sc, m, &sw_prod, 4563 &sw_chain_prod, &sw_prod_bseq)) { 4564 DBRUNIF(1, bnx_breakpoint(sc)); 4565 panic("%s: Double mbuf allocation " 4566 "failure!", 4567 device_xname(sc->bnx_dev)); 4568 } 4569 continue; 4570 } 4571 4572 /* Skip over the l2_fhdr when passing the data up 4573 * the stack. 4574 */ 4575 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4576 4577 /* Adjust the pckt length to match the received data. */ 4578 m->m_pkthdr.len = m->m_len = len; 4579 4580 /* Send the packet to the appropriate interface. */ 4581 m_set_rcvif(m, ifp); 4582 4583 DBRUN(BNX_VERBOSE_RECV, 4584 struct ether_header *eh; 4585 eh = mtod(m, struct ether_header *); 4586 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4587 __func__, ether_sprintf(eh->ether_dhost), 4588 ether_sprintf(eh->ether_shost), 4589 htons(eh->ether_type))); 4590 4591 /* Validate the checksum. */ 4592 4593 /* Check for an IP datagram. */ 4594 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4595 /* Check if the IP checksum is valid. */ 4596 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) 4597 == 0) 4598 m->m_pkthdr.csum_flags |= 4599 M_CSUM_IPv4; 4600 #ifdef BNX_DEBUG 4601 else 4602 DBPRINT(sc, BNX_WARN_SEND, 4603 "%s(): Invalid IP checksum " 4604 "= 0x%04X!\n", 4605 __func__, 4606 l2fhdr->l2_fhdr_ip_xsum 4607 ); 4608 #endif 4609 } 4610 4611 /* Check for a valid TCP/UDP frame. */ 4612 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4613 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4614 /* Check for a good TCP/UDP checksum. */ 4615 if ((status & 4616 (L2_FHDR_ERRORS_TCP_XSUM | 4617 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4618 m->m_pkthdr.csum_flags |= 4619 M_CSUM_TCPv4 | 4620 M_CSUM_UDPv4; 4621 } else { 4622 DBPRINT(sc, BNX_WARN_SEND, 4623 "%s(): Invalid TCP/UDP " 4624 "checksum = 0x%04X!\n", 4625 __func__, 4626 l2fhdr->l2_fhdr_tcp_udp_xsum); 4627 } 4628 } 4629 4630 /* 4631 * If we received a packet with a vlan tag, 4632 * attach that information to the packet. 4633 */ 4634 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4635 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4636 VLAN_INPUT_TAG(ifp, m, 4637 l2fhdr->l2_fhdr_vlan_tag, 4638 continue); 4639 } 4640 4641 /* 4642 * Handle BPF listeners. Let the BPF 4643 * user see the packet. 4644 */ 4645 bpf_mtap(ifp, m); 4646 4647 /* Pass the mbuf off to the upper layers. */ 4648 ifp->if_ipackets++; 4649 DBPRINT(sc, BNX_VERBOSE_RECV, 4650 "%s(): Passing received frame up.\n", __func__); 4651 if_percpuq_enqueue(ifp->if_percpuq, m); 4652 DBRUNIF(1, sc->rx_mbuf_alloc--); 4653 4654 } 4655 4656 sw_cons = NEXT_RX_BD(sw_cons); 4657 4658 /* Refresh hw_cons to see if there's new work */ 4659 if (sw_cons == hw_cons) { 4660 hw_cons = sc->hw_rx_cons = 4661 sblk->status_rx_quick_consumer_index0; 4662 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4663 USABLE_RX_BD_PER_PAGE) 4664 hw_cons++; 4665 } 4666 4667 /* Prevent speculative reads from getting ahead of 4668 * the status block. 4669 */ 4670 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4671 BUS_SPACE_BARRIER_READ); 4672 } 4673 4674 for (i = 0; i < RX_PAGES; i++) 4675 bus_dmamap_sync(sc->bnx_dmatag, 4676 sc->rx_bd_chain_map[i], 0, 4677 sc->rx_bd_chain_map[i]->dm_mapsize, 4678 BUS_DMASYNC_PREWRITE); 4679 4680 sc->rx_cons = sw_cons; 4681 sc->rx_prod = sw_prod; 4682 sc->rx_prod_bseq = sw_prod_bseq; 4683 4684 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4685 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4686 4687 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4688 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4689 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4690 } 4691 4692 /****************************************************************************/ 4693 /* Handles transmit completion interrupt events. */ 4694 /* */ 4695 /* Returns: */ 4696 /* Nothing. */ 4697 /****************************************************************************/ 4698 void 4699 bnx_tx_intr(struct bnx_softc *sc) 4700 { 4701 struct status_block *sblk = sc->status_block; 4702 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4703 struct bnx_pkt *pkt; 4704 bus_dmamap_t map; 4705 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4706 4707 DBRUNIF(1, sc->tx_interrupts++); 4708 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4709 BUS_DMASYNC_POSTREAD); 4710 4711 /* Get the hardware's view of the TX consumer index. */ 4712 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4713 4714 /* Skip to the next entry if this is a chain page pointer. */ 4715 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4716 hw_tx_cons++; 4717 4718 sw_tx_cons = sc->tx_cons; 4719 4720 /* Prevent speculative reads from getting ahead of the status block. */ 4721 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4722 BUS_SPACE_BARRIER_READ); 4723 4724 /* Cycle through any completed TX chain page entries. */ 4725 while (sw_tx_cons != hw_tx_cons) { 4726 #ifdef BNX_DEBUG 4727 struct tx_bd *txbd = NULL; 4728 #endif 4729 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4730 4731 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4732 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4733 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4734 4735 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4736 aprint_error_dev(sc->bnx_dev, 4737 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4738 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4739 4740 DBRUNIF(1, txbd = &sc->tx_bd_chain 4741 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4742 4743 DBRUNIF((txbd == NULL), 4744 aprint_error_dev(sc->bnx_dev, 4745 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4746 bnx_breakpoint(sc)); 4747 4748 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4749 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4750 4751 4752 mutex_enter(&sc->tx_pkt_mtx); 4753 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4754 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4755 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4756 mutex_exit(&sc->tx_pkt_mtx); 4757 /* 4758 * Free the associated mbuf. Remember 4759 * that only the last tx_bd of a packet 4760 * has an mbuf pointer and DMA map. 4761 */ 4762 map = pkt->pkt_dmamap; 4763 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4764 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4765 bus_dmamap_unload(sc->bnx_dmatag, map); 4766 4767 m_freem(pkt->pkt_mbuf); 4768 DBRUNIF(1, sc->tx_mbuf_alloc--); 4769 4770 ifp->if_opackets++; 4771 4772 mutex_enter(&sc->tx_pkt_mtx); 4773 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4774 } 4775 mutex_exit(&sc->tx_pkt_mtx); 4776 4777 sc->used_tx_bd--; 4778 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4779 __FILE__, __LINE__, sc->used_tx_bd); 4780 4781 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4782 4783 /* Refresh hw_cons to see if there's new work. */ 4784 hw_tx_cons = sc->hw_tx_cons = 4785 sblk->status_tx_quick_consumer_index0; 4786 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4787 USABLE_TX_BD_PER_PAGE) 4788 hw_tx_cons++; 4789 4790 /* Prevent speculative reads from getting ahead of 4791 * the status block. 4792 */ 4793 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4794 BUS_SPACE_BARRIER_READ); 4795 } 4796 4797 /* Clear the TX timeout timer. */ 4798 ifp->if_timer = 0; 4799 4800 /* Clear the tx hardware queue full flag. */ 4801 if (sc->used_tx_bd < sc->max_tx_bd) { 4802 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4803 aprint_debug_dev(sc->bnx_dev, 4804 "Open TX chain! %d/%d (used/total)\n", 4805 sc->used_tx_bd, sc->max_tx_bd)); 4806 ifp->if_flags &= ~IFF_OACTIVE; 4807 } 4808 4809 sc->tx_cons = sw_tx_cons; 4810 } 4811 4812 /****************************************************************************/ 4813 /* Disables interrupt generation. */ 4814 /* */ 4815 /* Returns: */ 4816 /* Nothing. */ 4817 /****************************************************************************/ 4818 void 4819 bnx_disable_intr(struct bnx_softc *sc) 4820 { 4821 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4822 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4823 } 4824 4825 /****************************************************************************/ 4826 /* Enables interrupt generation. */ 4827 /* */ 4828 /* Returns: */ 4829 /* Nothing. */ 4830 /****************************************************************************/ 4831 void 4832 bnx_enable_intr(struct bnx_softc *sc) 4833 { 4834 uint32_t val; 4835 4836 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4837 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4838 4839 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4840 sc->last_status_idx); 4841 4842 val = REG_RD(sc, BNX_HC_COMMAND); 4843 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4844 } 4845 4846 /****************************************************************************/ 4847 /* Handles controller initialization. */ 4848 /* */ 4849 /****************************************************************************/ 4850 int 4851 bnx_init(struct ifnet *ifp) 4852 { 4853 struct bnx_softc *sc = ifp->if_softc; 4854 uint32_t ether_mtu; 4855 int s, error = 0; 4856 4857 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4858 4859 s = splnet(); 4860 4861 bnx_stop(ifp, 0); 4862 4863 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4864 aprint_error_dev(sc->bnx_dev, 4865 "Controller reset failed!\n"); 4866 goto bnx_init_exit; 4867 } 4868 4869 if ((error = bnx_chipinit(sc)) != 0) { 4870 aprint_error_dev(sc->bnx_dev, 4871 "Controller initialization failed!\n"); 4872 goto bnx_init_exit; 4873 } 4874 4875 if ((error = bnx_blockinit(sc)) != 0) { 4876 aprint_error_dev(sc->bnx_dev, 4877 "Block initialization failed!\n"); 4878 goto bnx_init_exit; 4879 } 4880 4881 /* Calculate and program the Ethernet MRU size. */ 4882 if (ifp->if_mtu <= ETHERMTU) { 4883 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4884 sc->mbuf_alloc_size = MCLBYTES; 4885 } else { 4886 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4887 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4888 } 4889 4890 4891 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", 4892 __func__, ether_mtu); 4893 4894 /* 4895 * Program the MRU and enable Jumbo frame 4896 * support. 4897 */ 4898 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4899 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4900 4901 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4902 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4903 4904 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4905 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4906 sc->mbuf_alloc_size, sc->max_frame_size); 4907 4908 /* Program appropriate promiscuous/multicast filtering. */ 4909 bnx_iff(sc); 4910 4911 /* Init RX buffer descriptor chain. */ 4912 bnx_init_rx_chain(sc); 4913 4914 /* Init TX buffer descriptor chain. */ 4915 bnx_init_tx_chain(sc); 4916 4917 /* Enable host interrupts. */ 4918 bnx_enable_intr(sc); 4919 4920 if ((error = ether_mediachange(ifp)) != 0) 4921 goto bnx_init_exit; 4922 4923 SET(ifp->if_flags, IFF_RUNNING); 4924 CLR(ifp->if_flags, IFF_OACTIVE); 4925 4926 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4927 4928 bnx_init_exit: 4929 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4930 4931 splx(s); 4932 4933 return error; 4934 } 4935 4936 /****************************************************************************/ 4937 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4938 /* memory visible to the controller. */ 4939 /* */ 4940 /* Returns: */ 4941 /* 0 for success, positive value for failure. */ 4942 /****************************************************************************/ 4943 int 4944 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4945 { 4946 struct bnx_pkt *pkt; 4947 bus_dmamap_t map; 4948 struct tx_bd *txbd = NULL; 4949 uint16_t vlan_tag = 0, flags = 0; 4950 uint16_t chain_prod, prod; 4951 #ifdef BNX_DEBUG 4952 uint16_t debug_prod; 4953 #endif 4954 uint32_t addr, prod_bseq; 4955 int i, error; 4956 struct m_tag *mtag; 4957 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 4958 4959 mutex_enter(&sc->tx_pkt_mtx); 4960 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 4961 if (pkt == NULL) { 4962 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 4963 mutex_exit(&sc->tx_pkt_mtx); 4964 return ENETDOWN; 4965 } 4966 4967 if (sc->tx_pkt_count <= TOTAL_TX_BD && 4968 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 4969 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 4970 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4971 } 4972 4973 mutex_exit(&sc->tx_pkt_mtx); 4974 return ENOMEM; 4975 } 4976 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4977 mutex_exit(&sc->tx_pkt_mtx); 4978 4979 /* Transfer any checksum offload flags to the bd. */ 4980 if (m->m_pkthdr.csum_flags) { 4981 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 4982 flags |= TX_BD_FLAGS_IP_CKSUM; 4983 if (m->m_pkthdr.csum_flags & 4984 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4985 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4986 } 4987 4988 /* Transfer any VLAN tags to the bd. */ 4989 mtag = VLAN_OUTPUT_TAG(&sc->bnx_ec, m); 4990 if (mtag != NULL) { 4991 flags |= TX_BD_FLAGS_VLAN_TAG; 4992 vlan_tag = VLAN_TAG_VALUE(mtag); 4993 } 4994 4995 /* Map the mbuf into DMAable memory. */ 4996 prod = sc->tx_prod; 4997 chain_prod = TX_CHAIN_IDX(prod); 4998 map = pkt->pkt_dmamap; 4999 5000 /* Map the mbuf into our DMA address space. */ 5001 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5002 if (error != 0) { 5003 aprint_error_dev(sc->bnx_dev, 5004 "Error mapping mbuf into TX chain!\n"); 5005 sc->tx_dma_map_failures++; 5006 goto maperr; 5007 } 5008 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5009 BUS_DMASYNC_PREWRITE); 5010 /* Make sure there's room in the chain */ 5011 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5012 goto nospace; 5013 5014 /* prod points to an empty tx_bd at this point. */ 5015 prod_bseq = sc->tx_prod_bseq; 5016 #ifdef BNX_DEBUG 5017 debug_prod = chain_prod; 5018 #endif 5019 DBPRINT(sc, BNX_INFO_SEND, 5020 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5021 "prod_bseq = 0x%08X\n", 5022 __func__, prod, chain_prod, prod_bseq); 5023 5024 /* 5025 * Cycle through each mbuf segment that makes up 5026 * the outgoing frame, gathering the mapping info 5027 * for that segment and creating a tx_bd for the 5028 * mbuf. 5029 */ 5030 for (i = 0; i < map->dm_nsegs ; i++) { 5031 chain_prod = TX_CHAIN_IDX(prod); 5032 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5033 5034 addr = (uint32_t)map->dm_segs[i].ds_addr; 5035 txbd->tx_bd_haddr_lo = addr; 5036 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5037 txbd->tx_bd_haddr_hi = addr; 5038 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5039 txbd->tx_bd_vlan_tag = vlan_tag; 5040 txbd->tx_bd_flags = flags; 5041 prod_bseq += map->dm_segs[i].ds_len; 5042 if (i == 0) 5043 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5044 prod = NEXT_TX_BD(prod); 5045 } 5046 /* Set the END flag on the last TX buffer descriptor. */ 5047 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5048 5049 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5050 5051 DBPRINT(sc, BNX_INFO_SEND, 5052 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5053 "prod_bseq = 0x%08X\n", 5054 __func__, prod, chain_prod, prod_bseq); 5055 5056 pkt->pkt_mbuf = m; 5057 pkt->pkt_end_desc = chain_prod; 5058 5059 mutex_enter(&sc->tx_pkt_mtx); 5060 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5061 mutex_exit(&sc->tx_pkt_mtx); 5062 5063 sc->used_tx_bd += map->dm_nsegs; 5064 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5065 __FILE__, __LINE__, sc->used_tx_bd); 5066 5067 /* Update some debug statistics counters */ 5068 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5069 sc->tx_hi_watermark = sc->used_tx_bd); 5070 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5071 DBRUNIF(1, sc->tx_mbuf_alloc++); 5072 5073 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5074 map->dm_nsegs)); 5075 5076 /* prod points to the next free tx_bd at this point. */ 5077 sc->tx_prod = prod; 5078 sc->tx_prod_bseq = prod_bseq; 5079 5080 return 0; 5081 5082 5083 nospace: 5084 bus_dmamap_unload(sc->bnx_dmatag, map); 5085 maperr: 5086 mutex_enter(&sc->tx_pkt_mtx); 5087 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5088 mutex_exit(&sc->tx_pkt_mtx); 5089 5090 return ENOMEM; 5091 } 5092 5093 /****************************************************************************/ 5094 /* Main transmit routine. */ 5095 /* */ 5096 /* Returns: */ 5097 /* Nothing. */ 5098 /****************************************************************************/ 5099 void 5100 bnx_start(struct ifnet *ifp) 5101 { 5102 struct bnx_softc *sc = ifp->if_softc; 5103 struct mbuf *m_head = NULL; 5104 int count = 0; 5105 #ifdef BNX_DEBUG 5106 uint16_t tx_chain_prod; 5107 #endif 5108 5109 /* If there's no link or the transmit queue is empty then just exit. */ 5110 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5111 DBPRINT(sc, BNX_INFO_SEND, 5112 "%s(): output active or device not running.\n", __func__); 5113 goto bnx_start_exit; 5114 } 5115 5116 /* prod points to the next free tx_bd. */ 5117 #ifdef BNX_DEBUG 5118 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5119 #endif 5120 5121 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5122 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5123 "used_tx %d max_tx %d\n", 5124 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5125 sc->used_tx_bd, sc->max_tx_bd); 5126 5127 /* 5128 * Keep adding entries while there is space in the ring. 5129 */ 5130 while (sc->used_tx_bd < sc->max_tx_bd) { 5131 /* Check for any frames to send. */ 5132 IFQ_POLL(&ifp->if_snd, m_head); 5133 if (m_head == NULL) 5134 break; 5135 5136 /* 5137 * Pack the data into the transmit ring. If we 5138 * don't have room, set the OACTIVE flag to wait 5139 * for the NIC to drain the chain. 5140 */ 5141 if (bnx_tx_encap(sc, m_head)) { 5142 ifp->if_flags |= IFF_OACTIVE; 5143 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5144 "business! Total tx_bd used = %d\n", 5145 sc->used_tx_bd); 5146 break; 5147 } 5148 5149 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5150 count++; 5151 5152 /* Send a copy of the frame to any BPF listeners. */ 5153 bpf_mtap(ifp, m_head); 5154 } 5155 5156 if (count == 0) { 5157 /* no packets were dequeued */ 5158 DBPRINT(sc, BNX_VERBOSE_SEND, 5159 "%s(): No packets were dequeued\n", __func__); 5160 goto bnx_start_exit; 5161 } 5162 5163 /* Update the driver's counters. */ 5164 #ifdef BNX_DEBUG 5165 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5166 #endif 5167 5168 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " 5169 "= 0x%04X, tx_prod_bseq = 0x%08X\n", __func__, sc->tx_prod, 5170 tx_chain_prod, sc->tx_prod_bseq); 5171 5172 /* Start the transmit. */ 5173 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5174 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5175 5176 /* Set the tx timeout. */ 5177 ifp->if_timer = BNX_TX_TIMEOUT; 5178 5179 bnx_start_exit: 5180 return; 5181 } 5182 5183 /****************************************************************************/ 5184 /* Handles any IOCTL calls from the operating system. */ 5185 /* */ 5186 /* Returns: */ 5187 /* 0 for success, positive value for failure. */ 5188 /****************************************************************************/ 5189 int 5190 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5191 { 5192 struct bnx_softc *sc = ifp->if_softc; 5193 struct ifreq *ifr = (struct ifreq *) data; 5194 struct mii_data *mii = &sc->bnx_mii; 5195 int s, error = 0; 5196 5197 s = splnet(); 5198 5199 switch (command) { 5200 case SIOCSIFFLAGS: 5201 if ((error = ifioctl_common(ifp, command, data)) != 0) 5202 break; 5203 /* XXX set an ifflags callback and let ether_ioctl 5204 * handle all of this. 5205 */ 5206 if (ISSET(ifp->if_flags, IFF_UP)) { 5207 if (ifp->if_flags & IFF_RUNNING) 5208 error = ENETRESET; 5209 else 5210 bnx_init(ifp); 5211 } else if (ifp->if_flags & IFF_RUNNING) 5212 bnx_stop(ifp, 1); 5213 break; 5214 5215 case SIOCSIFMEDIA: 5216 case SIOCGIFMEDIA: 5217 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5218 sc->bnx_phy_flags); 5219 5220 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5221 break; 5222 5223 default: 5224 error = ether_ioctl(ifp, command, data); 5225 } 5226 5227 if (error == ENETRESET) { 5228 if (ifp->if_flags & IFF_RUNNING) 5229 bnx_iff(sc); 5230 error = 0; 5231 } 5232 5233 splx(s); 5234 return error; 5235 } 5236 5237 /****************************************************************************/ 5238 /* Transmit timeout handler. */ 5239 /* */ 5240 /* Returns: */ 5241 /* Nothing. */ 5242 /****************************************************************************/ 5243 void 5244 bnx_watchdog(struct ifnet *ifp) 5245 { 5246 struct bnx_softc *sc = ifp->if_softc; 5247 5248 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5249 bnx_dump_status_block(sc)); 5250 /* 5251 * If we are in this routine because of pause frames, then 5252 * don't reset the hardware. 5253 */ 5254 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5255 return; 5256 5257 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5258 5259 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5260 5261 bnx_init(ifp); 5262 5263 ifp->if_oerrors++; 5264 } 5265 5266 /* 5267 * Interrupt handler. 5268 */ 5269 /****************************************************************************/ 5270 /* Main interrupt entry point. Verifies that the controller generated the */ 5271 /* interrupt and then calls a separate routine for handle the various */ 5272 /* interrupt causes (PHY, TX, RX). */ 5273 /* */ 5274 /* Returns: */ 5275 /* 0 for success, positive value for failure. */ 5276 /****************************************************************************/ 5277 int 5278 bnx_intr(void *xsc) 5279 { 5280 struct bnx_softc *sc; 5281 struct ifnet *ifp; 5282 uint32_t status_attn_bits; 5283 const struct status_block *sblk; 5284 5285 sc = xsc; 5286 5287 ifp = &sc->bnx_ec.ec_if; 5288 5289 if (!device_is_active(sc->bnx_dev) || 5290 (ifp->if_flags & IFF_RUNNING) == 0) 5291 return 0; 5292 5293 DBRUNIF(1, sc->interrupts_generated++); 5294 5295 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5296 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 5297 5298 /* 5299 * If the hardware status block index 5300 * matches the last value read by the 5301 * driver and we haven't asserted our 5302 * interrupt then there's nothing to do. 5303 */ 5304 if ((sc->status_block->status_idx == sc->last_status_idx) && 5305 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 5306 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 5307 return 0; 5308 5309 /* Ack the interrupt and stop others from occuring. */ 5310 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5311 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5312 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5313 5314 /* Keep processing data as long as there is work to do. */ 5315 for (;;) { 5316 sblk = sc->status_block; 5317 status_attn_bits = sblk->status_attn_bits; 5318 5319 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5320 aprint_debug("Simulating unexpected status attention bit set."); 5321 status_attn_bits = status_attn_bits | 5322 STATUS_ATTN_BITS_PARITY_ERROR); 5323 5324 /* Was it a link change interrupt? */ 5325 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5326 (sblk->status_attn_bits_ack & 5327 STATUS_ATTN_BITS_LINK_STATE)) 5328 bnx_phy_intr(sc); 5329 5330 /* If any other attention is asserted then the chip is toast. */ 5331 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5332 (sblk->status_attn_bits_ack & 5333 ~STATUS_ATTN_BITS_LINK_STATE))) { 5334 DBRUN(1, sc->unexpected_attentions++); 5335 5336 BNX_PRINTF(sc, 5337 "Fatal attention detected: 0x%08X\n", 5338 sblk->status_attn_bits); 5339 5340 DBRUN(BNX_FATAL, 5341 if (bnx_debug_unexpected_attention == 0) 5342 bnx_breakpoint(sc)); 5343 5344 bnx_init(ifp); 5345 return 1; 5346 } 5347 5348 /* Check for any completed RX frames. */ 5349 if (sblk->status_rx_quick_consumer_index0 != 5350 sc->hw_rx_cons) 5351 bnx_rx_intr(sc); 5352 5353 /* Check for any completed TX frames. */ 5354 if (sblk->status_tx_quick_consumer_index0 != 5355 sc->hw_tx_cons) 5356 bnx_tx_intr(sc); 5357 5358 /* 5359 * Save the status block index value for use during the 5360 * next interrupt. 5361 */ 5362 sc->last_status_idx = sblk->status_idx; 5363 5364 /* Prevent speculative reads from getting ahead of the 5365 * status block. 5366 */ 5367 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 5368 BUS_SPACE_BARRIER_READ); 5369 5370 /* If there's no work left then exit the isr. */ 5371 if ((sblk->status_rx_quick_consumer_index0 == 5372 sc->hw_rx_cons) && 5373 (sblk->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5374 break; 5375 } 5376 5377 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5378 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 5379 5380 /* Re-enable interrupts. */ 5381 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5382 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5383 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5384 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5385 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5386 5387 /* Handle any frames that arrived while handling the interrupt. */ 5388 if_schedule_deferred_start(ifp); 5389 5390 return 1; 5391 } 5392 5393 /****************************************************************************/ 5394 /* Programs the various packet receive modes (broadcast and multicast). */ 5395 /* */ 5396 /* Returns: */ 5397 /* Nothing. */ 5398 /****************************************************************************/ 5399 void 5400 bnx_iff(struct bnx_softc *sc) 5401 { 5402 struct ethercom *ec = &sc->bnx_ec; 5403 struct ifnet *ifp = &ec->ec_if; 5404 struct ether_multi *enm; 5405 struct ether_multistep step; 5406 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5407 uint32_t rx_mode, sort_mode; 5408 int h, i; 5409 5410 /* Initialize receive mode default settings. */ 5411 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5412 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5413 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5414 ifp->if_flags &= ~IFF_ALLMULTI; 5415 5416 /* 5417 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5418 * be enbled. 5419 */ 5420 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5421 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5422 5423 /* 5424 * Check for promiscuous, all multicast, or selected 5425 * multicast address filtering. 5426 */ 5427 if (ifp->if_flags & IFF_PROMISC) { 5428 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5429 5430 ifp->if_flags |= IFF_ALLMULTI; 5431 /* Enable promiscuous mode. */ 5432 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5433 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5434 } else if (ifp->if_flags & IFF_ALLMULTI) { 5435 allmulti: 5436 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5437 5438 ifp->if_flags |= IFF_ALLMULTI; 5439 /* Enable all multicast addresses. */ 5440 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5441 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5442 0xffffffff); 5443 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5444 } else { 5445 /* Accept one or more multicast(s). */ 5446 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5447 5448 ETHER_FIRST_MULTI(step, ec, enm); 5449 while (enm != NULL) { 5450 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5451 ETHER_ADDR_LEN)) { 5452 goto allmulti; 5453 } 5454 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5455 0xFF; 5456 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5457 ETHER_NEXT_MULTI(step, enm); 5458 } 5459 5460 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5461 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5462 hashes[i]); 5463 5464 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5465 } 5466 5467 /* Only make changes if the recive mode has actually changed. */ 5468 if (rx_mode != sc->rx_mode) { 5469 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5470 rx_mode); 5471 5472 sc->rx_mode = rx_mode; 5473 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5474 } 5475 5476 /* Disable and clear the exisitng sort before enabling a new sort. */ 5477 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5478 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5479 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5480 } 5481 5482 /****************************************************************************/ 5483 /* Called periodically to updates statistics from the controllers */ 5484 /* statistics block. */ 5485 /* */ 5486 /* Returns: */ 5487 /* Nothing. */ 5488 /****************************************************************************/ 5489 void 5490 bnx_stats_update(struct bnx_softc *sc) 5491 { 5492 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5493 struct statistics_block *stats; 5494 5495 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5496 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5497 BUS_DMASYNC_POSTREAD); 5498 5499 stats = (struct statistics_block *)sc->stats_block; 5500 5501 /* 5502 * Update the interface statistics from the 5503 * hardware statistics. 5504 */ 5505 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5506 5507 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5508 (u_long)stats->stat_EtherStatsOverrsizePkts + 5509 (u_long)stats->stat_IfInMBUFDiscards + 5510 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5511 (u_long)stats->stat_Dot3StatsFCSErrors; 5512 5513 ifp->if_oerrors = (u_long) 5514 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5515 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5516 (u_long)stats->stat_Dot3StatsLateCollisions; 5517 5518 /* 5519 * Certain controllers don't report 5520 * carrier sense errors correctly. 5521 * See errata E11_5708CA0_1165. 5522 */ 5523 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5524 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5525 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5526 5527 /* 5528 * Update the sysctl statistics from the 5529 * hardware statistics. 5530 */ 5531 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5532 (uint64_t) stats->stat_IfHCInOctets_lo; 5533 5534 sc->stat_IfHCInBadOctets = 5535 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5536 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5537 5538 sc->stat_IfHCOutOctets = 5539 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5540 (uint64_t) stats->stat_IfHCOutOctets_lo; 5541 5542 sc->stat_IfHCOutBadOctets = 5543 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5544 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5545 5546 sc->stat_IfHCInUcastPkts = 5547 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5548 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5549 5550 sc->stat_IfHCInMulticastPkts = 5551 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5552 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5553 5554 sc->stat_IfHCInBroadcastPkts = 5555 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5556 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5557 5558 sc->stat_IfHCOutUcastPkts = 5559 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5560 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5561 5562 sc->stat_IfHCOutMulticastPkts = 5563 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5564 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5565 5566 sc->stat_IfHCOutBroadcastPkts = 5567 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5568 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5569 5570 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5571 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5572 5573 sc->stat_Dot3StatsCarrierSenseErrors = 5574 stats->stat_Dot3StatsCarrierSenseErrors; 5575 5576 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5577 5578 sc->stat_Dot3StatsAlignmentErrors = 5579 stats->stat_Dot3StatsAlignmentErrors; 5580 5581 sc->stat_Dot3StatsSingleCollisionFrames = 5582 stats->stat_Dot3StatsSingleCollisionFrames; 5583 5584 sc->stat_Dot3StatsMultipleCollisionFrames = 5585 stats->stat_Dot3StatsMultipleCollisionFrames; 5586 5587 sc->stat_Dot3StatsDeferredTransmissions = 5588 stats->stat_Dot3StatsDeferredTransmissions; 5589 5590 sc->stat_Dot3StatsExcessiveCollisions = 5591 stats->stat_Dot3StatsExcessiveCollisions; 5592 5593 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5594 5595 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5596 5597 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5598 5599 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5600 5601 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5602 5603 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5604 5605 sc->stat_EtherStatsPktsRx64Octets = 5606 stats->stat_EtherStatsPktsRx64Octets; 5607 5608 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5609 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5610 5611 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5612 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5613 5614 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5615 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5616 5617 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5618 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5619 5620 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5621 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5622 5623 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5624 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5625 5626 sc->stat_EtherStatsPktsTx64Octets = 5627 stats->stat_EtherStatsPktsTx64Octets; 5628 5629 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5630 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5631 5632 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5633 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5634 5635 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5636 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5637 5638 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5639 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5640 5641 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5642 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5643 5644 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5645 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5646 5647 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5648 5649 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5650 5651 sc->stat_OutXonSent = stats->stat_OutXonSent; 5652 5653 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5654 5655 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5656 5657 sc->stat_MacControlFramesReceived = 5658 stats->stat_MacControlFramesReceived; 5659 5660 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5661 5662 sc->stat_IfInFramesL2FilterDiscards = 5663 stats->stat_IfInFramesL2FilterDiscards; 5664 5665 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5666 5667 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5668 5669 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5670 5671 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5672 5673 sc->stat_CatchupInRuleCheckerDiscards = 5674 stats->stat_CatchupInRuleCheckerDiscards; 5675 5676 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5677 5678 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5679 5680 sc->stat_CatchupInRuleCheckerP4Hit = 5681 stats->stat_CatchupInRuleCheckerP4Hit; 5682 5683 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5684 } 5685 5686 void 5687 bnx_tick(void *xsc) 5688 { 5689 struct bnx_softc *sc = xsc; 5690 struct mii_data *mii; 5691 uint32_t msg; 5692 uint16_t prod, chain_prod; 5693 uint32_t prod_bseq; 5694 int s = splnet(); 5695 5696 /* Tell the firmware that the driver is still running. */ 5697 #ifdef BNX_DEBUG 5698 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5699 #else 5700 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5701 #endif 5702 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5703 5704 /* Update the statistics from the hardware statistics block. */ 5705 bnx_stats_update(sc); 5706 5707 /* Schedule the next tick. */ 5708 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5709 5710 mii = &sc->bnx_mii; 5711 mii_tick(mii); 5712 5713 /* try to get more RX buffers, just in case */ 5714 prod = sc->rx_prod; 5715 prod_bseq = sc->rx_prod_bseq; 5716 chain_prod = RX_CHAIN_IDX(prod); 5717 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5718 sc->rx_prod = prod; 5719 sc->rx_prod_bseq = prod_bseq; 5720 splx(s); 5721 return; 5722 } 5723 5724 /****************************************************************************/ 5725 /* BNX Debug Routines */ 5726 /****************************************************************************/ 5727 #ifdef BNX_DEBUG 5728 5729 /****************************************************************************/ 5730 /* Prints out information about an mbuf. */ 5731 /* */ 5732 /* Returns: */ 5733 /* Nothing. */ 5734 /****************************************************************************/ 5735 void 5736 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5737 { 5738 struct mbuf *mp = m; 5739 5740 if (m == NULL) { 5741 /* Index out of range. */ 5742 aprint_error("mbuf ptr is null!\n"); 5743 return; 5744 } 5745 5746 while (mp) { 5747 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5748 mp, mp->m_len); 5749 5750 if (mp->m_flags & M_EXT) 5751 aprint_debug("M_EXT "); 5752 if (mp->m_flags & M_PKTHDR) 5753 aprint_debug("M_PKTHDR "); 5754 aprint_debug("\n"); 5755 5756 if (mp->m_flags & M_EXT) 5757 aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", 5758 mp, mp->m_ext.ext_size); 5759 5760 mp = mp->m_next; 5761 } 5762 } 5763 5764 /****************************************************************************/ 5765 /* Prints out the mbufs in the TX mbuf chain. */ 5766 /* */ 5767 /* Returns: */ 5768 /* Nothing. */ 5769 /****************************************************************************/ 5770 void 5771 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5772 { 5773 #if 0 5774 struct mbuf *m; 5775 int i; 5776 5777 aprint_debug_dev(sc->bnx_dev, 5778 "----------------------------" 5779 " tx mbuf data " 5780 "----------------------------\n"); 5781 5782 for (i = 0; i < count; i++) { 5783 m = sc->tx_mbuf_ptr[chain_prod]; 5784 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5785 bnx_dump_mbuf(sc, m); 5786 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5787 } 5788 5789 aprint_debug_dev(sc->bnx_dev, 5790 "--------------------------------------------" 5791 "----------------------------\n"); 5792 #endif 5793 } 5794 5795 /* 5796 * This routine prints the RX mbuf chain. 5797 */ 5798 void 5799 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5800 { 5801 struct mbuf *m; 5802 int i; 5803 5804 aprint_debug_dev(sc->bnx_dev, 5805 "----------------------------" 5806 " rx mbuf data " 5807 "----------------------------\n"); 5808 5809 for (i = 0; i < count; i++) { 5810 m = sc->rx_mbuf_ptr[chain_prod]; 5811 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5812 bnx_dump_mbuf(sc, m); 5813 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5814 } 5815 5816 5817 aprint_debug_dev(sc->bnx_dev, 5818 "--------------------------------------------" 5819 "----------------------------\n"); 5820 } 5821 5822 void 5823 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5824 { 5825 if (idx > MAX_TX_BD) 5826 /* Index out of range. */ 5827 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5828 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5829 /* TX Chain page pointer. */ 5830 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5831 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5832 txbd->tx_bd_haddr_lo); 5833 else 5834 /* Normal tx_bd entry. */ 5835 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5836 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5837 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5838 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5839 txbd->tx_bd_flags); 5840 } 5841 5842 void 5843 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5844 { 5845 if (idx > MAX_RX_BD) 5846 /* Index out of range. */ 5847 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5848 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5849 /* TX Chain page pointer. */ 5850 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5851 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5852 rxbd->rx_bd_haddr_lo); 5853 else 5854 /* Normal tx_bd entry. */ 5855 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5856 "0x%08X, flags = 0x%08X\n", idx, 5857 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5858 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5859 } 5860 5861 void 5862 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5863 { 5864 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5865 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5866 "tcp_udp_xsum = 0x%04X\n", idx, 5867 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5868 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5869 l2fhdr->l2_fhdr_tcp_udp_xsum); 5870 } 5871 5872 /* 5873 * This routine prints the TX chain. 5874 */ 5875 void 5876 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5877 { 5878 struct tx_bd *txbd; 5879 int i; 5880 5881 /* First some info about the tx_bd chain structure. */ 5882 aprint_debug_dev(sc->bnx_dev, 5883 "----------------------------" 5884 " tx_bd chain " 5885 "----------------------------\n"); 5886 5887 BNX_PRINTF(sc, 5888 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5889 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 5890 5891 BNX_PRINTF(sc, 5892 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5893 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 5894 5895 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5896 5897 aprint_error_dev(sc->bnx_dev, "" 5898 "-----------------------------" 5899 " tx_bd data " 5900 "-----------------------------\n"); 5901 5902 /* Now print out the tx_bd's themselves. */ 5903 for (i = 0; i < count; i++) { 5904 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5905 bnx_dump_txbd(sc, tx_prod, txbd); 5906 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5907 } 5908 5909 aprint_debug_dev(sc->bnx_dev, 5910 "-----------------------------" 5911 "--------------" 5912 "-----------------------------\n"); 5913 } 5914 5915 /* 5916 * This routine prints the RX chain. 5917 */ 5918 void 5919 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5920 { 5921 struct rx_bd *rxbd; 5922 int i; 5923 5924 /* First some info about the tx_bd chain structure. */ 5925 aprint_debug_dev(sc->bnx_dev, 5926 "----------------------------" 5927 " rx_bd chain " 5928 "----------------------------\n"); 5929 5930 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5931 5932 BNX_PRINTF(sc, 5933 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5934 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 5935 5936 BNX_PRINTF(sc, 5937 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5938 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 5939 5940 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5941 5942 aprint_error_dev(sc->bnx_dev, 5943 "----------------------------" 5944 " rx_bd data " 5945 "----------------------------\n"); 5946 5947 /* Now print out the rx_bd's themselves. */ 5948 for (i = 0; i < count; i++) { 5949 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5950 bnx_dump_rxbd(sc, rx_prod, rxbd); 5951 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5952 } 5953 5954 aprint_debug_dev(sc->bnx_dev, 5955 "----------------------------" 5956 "--------------" 5957 "----------------------------\n"); 5958 } 5959 5960 /* 5961 * This routine prints the status block. 5962 */ 5963 void 5964 bnx_dump_status_block(struct bnx_softc *sc) 5965 { 5966 struct status_block *sblk; 5967 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5968 BUS_DMASYNC_POSTREAD); 5969 5970 sblk = sc->status_block; 5971 5972 aprint_debug_dev(sc->bnx_dev, "----------------------------- Status Block " 5973 "-----------------------------\n"); 5974 5975 BNX_PRINTF(sc, 5976 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5977 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5978 sblk->status_idx); 5979 5980 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5981 sblk->status_rx_quick_consumer_index0, 5982 sblk->status_tx_quick_consumer_index0); 5983 5984 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5985 5986 /* Theses indices are not used for normal L2 drivers. */ 5987 if (sblk->status_rx_quick_consumer_index1 || 5988 sblk->status_tx_quick_consumer_index1) 5989 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5990 sblk->status_rx_quick_consumer_index1, 5991 sblk->status_tx_quick_consumer_index1); 5992 5993 if (sblk->status_rx_quick_consumer_index2 || 5994 sblk->status_tx_quick_consumer_index2) 5995 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5996 sblk->status_rx_quick_consumer_index2, 5997 sblk->status_tx_quick_consumer_index2); 5998 5999 if (sblk->status_rx_quick_consumer_index3 || 6000 sblk->status_tx_quick_consumer_index3) 6001 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6002 sblk->status_rx_quick_consumer_index3, 6003 sblk->status_tx_quick_consumer_index3); 6004 6005 if (sblk->status_rx_quick_consumer_index4 || 6006 sblk->status_rx_quick_consumer_index5) 6007 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6008 sblk->status_rx_quick_consumer_index4, 6009 sblk->status_rx_quick_consumer_index5); 6010 6011 if (sblk->status_rx_quick_consumer_index6 || 6012 sblk->status_rx_quick_consumer_index7) 6013 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6014 sblk->status_rx_quick_consumer_index6, 6015 sblk->status_rx_quick_consumer_index7); 6016 6017 if (sblk->status_rx_quick_consumer_index8 || 6018 sblk->status_rx_quick_consumer_index9) 6019 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6020 sblk->status_rx_quick_consumer_index8, 6021 sblk->status_rx_quick_consumer_index9); 6022 6023 if (sblk->status_rx_quick_consumer_index10 || 6024 sblk->status_rx_quick_consumer_index11) 6025 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6026 sblk->status_rx_quick_consumer_index10, 6027 sblk->status_rx_quick_consumer_index11); 6028 6029 if (sblk->status_rx_quick_consumer_index12 || 6030 sblk->status_rx_quick_consumer_index13) 6031 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6032 sblk->status_rx_quick_consumer_index12, 6033 sblk->status_rx_quick_consumer_index13); 6034 6035 if (sblk->status_rx_quick_consumer_index14 || 6036 sblk->status_rx_quick_consumer_index15) 6037 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6038 sblk->status_rx_quick_consumer_index14, 6039 sblk->status_rx_quick_consumer_index15); 6040 6041 if (sblk->status_completion_producer_index || 6042 sblk->status_cmd_consumer_index) 6043 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6044 sblk->status_completion_producer_index, 6045 sblk->status_cmd_consumer_index); 6046 6047 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6048 "-----------------------------\n"); 6049 } 6050 6051 /* 6052 * This routine prints the statistics block. 6053 */ 6054 void 6055 bnx_dump_stats_block(struct bnx_softc *sc) 6056 { 6057 struct statistics_block *sblk; 6058 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6059 BUS_DMASYNC_POSTREAD); 6060 6061 sblk = sc->stats_block; 6062 6063 aprint_debug_dev(sc->bnx_dev, "" 6064 "-----------------------------" 6065 " Stats Block " 6066 "-----------------------------\n"); 6067 6068 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6069 "IfHcInBadOctets = 0x%08X:%08X\n", 6070 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6071 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6072 6073 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6074 "IfHcOutBadOctets = 0x%08X:%08X\n", 6075 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6076 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6077 6078 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6079 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6080 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6081 sblk->stat_IfHCInMulticastPkts_hi, 6082 sblk->stat_IfHCInMulticastPkts_lo); 6083 6084 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6085 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6086 sblk->stat_IfHCInBroadcastPkts_hi, 6087 sblk->stat_IfHCInBroadcastPkts_lo, 6088 sblk->stat_IfHCOutUcastPkts_hi, 6089 sblk->stat_IfHCOutUcastPkts_lo); 6090 6091 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6092 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6093 sblk->stat_IfHCOutMulticastPkts_hi, 6094 sblk->stat_IfHCOutMulticastPkts_lo, 6095 sblk->stat_IfHCOutBroadcastPkts_hi, 6096 sblk->stat_IfHCOutBroadcastPkts_lo); 6097 6098 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6099 BNX_PRINTF(sc, "0x%08X : " 6100 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6101 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6102 6103 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6104 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6105 sblk->stat_Dot3StatsCarrierSenseErrors); 6106 6107 if (sblk->stat_Dot3StatsFCSErrors) 6108 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6109 sblk->stat_Dot3StatsFCSErrors); 6110 6111 if (sblk->stat_Dot3StatsAlignmentErrors) 6112 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6113 sblk->stat_Dot3StatsAlignmentErrors); 6114 6115 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6116 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6117 sblk->stat_Dot3StatsSingleCollisionFrames); 6118 6119 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6120 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6121 sblk->stat_Dot3StatsMultipleCollisionFrames); 6122 6123 if (sblk->stat_Dot3StatsDeferredTransmissions) 6124 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6125 sblk->stat_Dot3StatsDeferredTransmissions); 6126 6127 if (sblk->stat_Dot3StatsExcessiveCollisions) 6128 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6129 sblk->stat_Dot3StatsExcessiveCollisions); 6130 6131 if (sblk->stat_Dot3StatsLateCollisions) 6132 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6133 sblk->stat_Dot3StatsLateCollisions); 6134 6135 if (sblk->stat_EtherStatsCollisions) 6136 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6137 sblk->stat_EtherStatsCollisions); 6138 6139 if (sblk->stat_EtherStatsFragments) 6140 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6141 sblk->stat_EtherStatsFragments); 6142 6143 if (sblk->stat_EtherStatsJabbers) 6144 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6145 sblk->stat_EtherStatsJabbers); 6146 6147 if (sblk->stat_EtherStatsUndersizePkts) 6148 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6149 sblk->stat_EtherStatsUndersizePkts); 6150 6151 if (sblk->stat_EtherStatsOverrsizePkts) 6152 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6153 sblk->stat_EtherStatsOverrsizePkts); 6154 6155 if (sblk->stat_EtherStatsPktsRx64Octets) 6156 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6157 sblk->stat_EtherStatsPktsRx64Octets); 6158 6159 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6160 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6161 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6162 6163 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6164 BNX_PRINTF(sc, "0x%08X : " 6165 "EtherStatsPktsRx128Octetsto255Octets\n", 6166 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6167 6168 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6169 BNX_PRINTF(sc, "0x%08X : " 6170 "EtherStatsPktsRx256Octetsto511Octets\n", 6171 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6172 6173 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6174 BNX_PRINTF(sc, "0x%08X : " 6175 "EtherStatsPktsRx512Octetsto1023Octets\n", 6176 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6177 6178 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6179 BNX_PRINTF(sc, "0x%08X : " 6180 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6181 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6182 6183 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6184 BNX_PRINTF(sc, "0x%08X : " 6185 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6186 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6187 6188 if (sblk->stat_EtherStatsPktsTx64Octets) 6189 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6190 sblk->stat_EtherStatsPktsTx64Octets); 6191 6192 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6193 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6194 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6195 6196 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6197 BNX_PRINTF(sc, "0x%08X : " 6198 "EtherStatsPktsTx128Octetsto255Octets\n", 6199 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6200 6201 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6202 BNX_PRINTF(sc, "0x%08X : " 6203 "EtherStatsPktsTx256Octetsto511Octets\n", 6204 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6205 6206 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6207 BNX_PRINTF(sc, "0x%08X : " 6208 "EtherStatsPktsTx512Octetsto1023Octets\n", 6209 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6210 6211 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6212 BNX_PRINTF(sc, "0x%08X : " 6213 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6214 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6215 6216 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6217 BNX_PRINTF(sc, "0x%08X : " 6218 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6219 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6220 6221 if (sblk->stat_XonPauseFramesReceived) 6222 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6223 sblk->stat_XonPauseFramesReceived); 6224 6225 if (sblk->stat_XoffPauseFramesReceived) 6226 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6227 sblk->stat_XoffPauseFramesReceived); 6228 6229 if (sblk->stat_OutXonSent) 6230 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6231 sblk->stat_OutXonSent); 6232 6233 if (sblk->stat_OutXoffSent) 6234 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6235 sblk->stat_OutXoffSent); 6236 6237 if (sblk->stat_FlowControlDone) 6238 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6239 sblk->stat_FlowControlDone); 6240 6241 if (sblk->stat_MacControlFramesReceived) 6242 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6243 sblk->stat_MacControlFramesReceived); 6244 6245 if (sblk->stat_XoffStateEntered) 6246 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6247 sblk->stat_XoffStateEntered); 6248 6249 if (sblk->stat_IfInFramesL2FilterDiscards) 6250 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6251 sblk->stat_IfInFramesL2FilterDiscards); 6252 6253 if (sblk->stat_IfInRuleCheckerDiscards) 6254 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6255 sblk->stat_IfInRuleCheckerDiscards); 6256 6257 if (sblk->stat_IfInFTQDiscards) 6258 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6259 sblk->stat_IfInFTQDiscards); 6260 6261 if (sblk->stat_IfInMBUFDiscards) 6262 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6263 sblk->stat_IfInMBUFDiscards); 6264 6265 if (sblk->stat_IfInRuleCheckerP4Hit) 6266 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6267 sblk->stat_IfInRuleCheckerP4Hit); 6268 6269 if (sblk->stat_CatchupInRuleCheckerDiscards) 6270 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6271 sblk->stat_CatchupInRuleCheckerDiscards); 6272 6273 if (sblk->stat_CatchupInFTQDiscards) 6274 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6275 sblk->stat_CatchupInFTQDiscards); 6276 6277 if (sblk->stat_CatchupInMBUFDiscards) 6278 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6279 sblk->stat_CatchupInMBUFDiscards); 6280 6281 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6282 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6283 sblk->stat_CatchupInRuleCheckerP4Hit); 6284 6285 aprint_debug_dev(sc->bnx_dev, 6286 "-----------------------------" 6287 "--------------" 6288 "-----------------------------\n"); 6289 } 6290 6291 void 6292 bnx_dump_driver_state(struct bnx_softc *sc) 6293 { 6294 aprint_debug_dev(sc->bnx_dev, 6295 "-----------------------------" 6296 " Driver State " 6297 "-----------------------------\n"); 6298 6299 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6300 "address\n", sc); 6301 6302 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6303 sc->status_block); 6304 6305 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6306 "address\n", sc->stats_block); 6307 6308 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6309 "adddress\n", sc->tx_bd_chain); 6310 6311 #if 0 6312 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6313 sc->rx_bd_chain); 6314 6315 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6316 sc->tx_mbuf_ptr); 6317 #endif 6318 6319 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6320 sc->rx_mbuf_ptr); 6321 6322 BNX_PRINTF(sc, 6323 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6324 sc->interrupts_generated); 6325 6326 BNX_PRINTF(sc, 6327 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6328 sc->rx_interrupts); 6329 6330 BNX_PRINTF(sc, 6331 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6332 sc->tx_interrupts); 6333 6334 BNX_PRINTF(sc, 6335 " 0x%08X - (sc->last_status_idx) status block index\n", 6336 sc->last_status_idx); 6337 6338 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6339 sc->tx_prod); 6340 6341 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6342 sc->tx_cons); 6343 6344 BNX_PRINTF(sc, 6345 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6346 sc->tx_prod_bseq); 6347 BNX_PRINTF(sc, 6348 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6349 sc->tx_mbuf_alloc); 6350 6351 BNX_PRINTF(sc, 6352 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6353 sc->used_tx_bd); 6354 6355 BNX_PRINTF(sc, 6356 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6357 sc->tx_hi_watermark, sc->max_tx_bd); 6358 6359 6360 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6361 sc->rx_prod); 6362 6363 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6364 sc->rx_cons); 6365 6366 BNX_PRINTF(sc, 6367 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6368 sc->rx_prod_bseq); 6369 6370 BNX_PRINTF(sc, 6371 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6372 sc->rx_mbuf_alloc); 6373 6374 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6375 sc->free_rx_bd); 6376 6377 BNX_PRINTF(sc, 6378 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6379 sc->rx_low_watermark, sc->max_rx_bd); 6380 6381 BNX_PRINTF(sc, 6382 " 0x%08X - (sc->mbuf_alloc_failed) " 6383 "mbuf alloc failures\n", 6384 sc->mbuf_alloc_failed); 6385 6386 BNX_PRINTF(sc, 6387 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6388 "simulated mbuf alloc failures\n", 6389 sc->mbuf_sim_alloc_failed); 6390 6391 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6392 "-----------------------------\n"); 6393 } 6394 6395 void 6396 bnx_dump_hw_state(struct bnx_softc *sc) 6397 { 6398 uint32_t val1; 6399 int i; 6400 6401 aprint_debug_dev(sc->bnx_dev, 6402 "----------------------------" 6403 " Hardware State " 6404 "----------------------------\n"); 6405 6406 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6407 6408 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6409 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6410 val1, BNX_MISC_ENABLE_STATUS_BITS); 6411 6412 val1 = REG_RD(sc, BNX_DMA_STATUS); 6413 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6414 6415 val1 = REG_RD(sc, BNX_CTX_STATUS); 6416 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6417 6418 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6419 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6420 BNX_EMAC_STATUS); 6421 6422 val1 = REG_RD(sc, BNX_RPM_STATUS); 6423 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6424 6425 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6426 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6427 BNX_TBDR_STATUS); 6428 6429 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6430 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6431 BNX_TDMA_STATUS); 6432 6433 val1 = REG_RD(sc, BNX_HC_STATUS); 6434 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6435 6436 aprint_debug_dev(sc->bnx_dev, 6437 "----------------------------" 6438 "----------------" 6439 "----------------------------\n"); 6440 6441 aprint_debug_dev(sc->bnx_dev, 6442 "----------------------------" 6443 " Register Dump " 6444 "----------------------------\n"); 6445 6446 for (i = 0x400; i < 0x8000; i += 0x10) 6447 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6448 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6449 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6450 6451 aprint_debug_dev(sc->bnx_dev, 6452 "----------------------------" 6453 "----------------" 6454 "----------------------------\n"); 6455 } 6456 6457 void 6458 bnx_breakpoint(struct bnx_softc *sc) 6459 { 6460 /* Unreachable code to shut the compiler up about unused functions. */ 6461 if (0) { 6462 bnx_dump_txbd(sc, 0, NULL); 6463 bnx_dump_rxbd(sc, 0, NULL); 6464 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6465 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6466 bnx_dump_l2fhdr(sc, 0, NULL); 6467 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6468 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6469 bnx_dump_status_block(sc); 6470 bnx_dump_stats_block(sc); 6471 bnx_dump_driver_state(sc); 6472 bnx_dump_hw_state(sc); 6473 } 6474 6475 bnx_dump_driver_state(sc); 6476 /* Print the important status block fields. */ 6477 bnx_dump_status_block(sc); 6478 6479 #if 0 6480 /* Call the debugger. */ 6481 breakpoint(); 6482 #endif 6483 6484 return; 6485 } 6486 #endif 6487
Indexes created Tue Sep 23 02:09:52 GMT 2025