if_bnx.c revision 1.63.2.3
1 /* $NetBSD: if_bnx.c,v 1.63.2.3 2019/01/18 08:50:27 pgoyette Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.85 2009/11/09 14:32:41 dlg Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.63.2.3 2019/01/18 08:50:27 pgoyette Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 /****************************************************************************/ 180 /* Supported Flash NVRAM device data. */ 181 /****************************************************************************/ 182 static struct flash_spec flash_table[] = 183 { 184 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 185 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 186 /* Slow EEPROM */ 187 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 188 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 189 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 190 "EEPROM - slow"}, 191 /* Expansion entry 0001 */ 192 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0001"}, 196 /* Saifun SA25F010 (non-buffered flash) */ 197 /* strap, cfg1, & write1 need updates */ 198 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 201 "Non-buffered flash (128kB)"}, 202 /* Saifun SA25F020 (non-buffered flash) */ 203 /* strap, cfg1, & write1 need updates */ 204 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 205 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 206 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 207 "Non-buffered flash (256kB)"}, 208 /* Expansion entry 0100 */ 209 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 210 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 211 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 212 "Entry 0100"}, 213 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 214 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 216 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 217 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 218 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 219 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 221 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 222 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 223 /* Saifun SA25F005 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 228 "Non-buffered flash (64kB)"}, 229 /* Fast EEPROM */ 230 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 231 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 232 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 233 "EEPROM - fast"}, 234 /* Expansion entry 1001 */ 235 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 236 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 237 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 238 "Entry 1001"}, 239 /* Expansion entry 1010 */ 240 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 241 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 242 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 243 "Entry 1010"}, 244 /* ATMEL AT45DB011B (buffered flash) */ 245 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 246 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 247 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 248 "Buffered flash (128kB)"}, 249 /* Expansion entry 1100 */ 250 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 251 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 252 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 253 "Entry 1100"}, 254 /* Expansion entry 1101 */ 255 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 256 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 257 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 258 "Entry 1101"}, 259 /* Ateml Expansion entry 1110 */ 260 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 261 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 262 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 263 "Entry 1110 (Atmel)"}, 264 /* ATMEL AT45DB021B (buffered flash) */ 265 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 266 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 267 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 268 "Buffered flash (256kB)"}, 269 }; 270 271 /* 272 * The BCM5709 controllers transparently handle the 273 * differences between Atmel 264 byte pages and all 274 * flash devices which use 256 byte pages, so no 275 * logical-to-physical mapping is required in the 276 * driver. 277 */ 278 static struct flash_spec flash_5709 = { 279 .flags = BNX_NV_BUFFERED, 280 .page_bits = BCM5709_FLASH_PAGE_BITS, 281 .page_size = BCM5709_FLASH_PAGE_SIZE, 282 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 283 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 284 .name = "5709 buffered flash (256kB)", 285 }; 286 287 /****************************************************************************/ 288 /* OpenBSD device entry points. */ 289 /****************************************************************************/ 290 static int bnx_probe(device_t, cfdata_t, void *); 291 void bnx_attach(device_t, device_t, void *); 292 int bnx_detach(device_t, int); 293 294 /****************************************************************************/ 295 /* BNX Debug Data Structure Dump Routines */ 296 /****************************************************************************/ 297 #ifdef BNX_DEBUG 298 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 299 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 300 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 302 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 303 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 304 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 305 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_status_block(struct bnx_softc *); 307 void bnx_dump_stats_block(struct bnx_softc *); 308 void bnx_dump_driver_state(struct bnx_softc *); 309 void bnx_dump_hw_state(struct bnx_softc *); 310 void bnx_breakpoint(struct bnx_softc *); 311 #endif 312 313 /****************************************************************************/ 314 /* BNX Register/Memory Access Routines */ 315 /****************************************************************************/ 316 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 317 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 318 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 319 int bnx_miibus_read_reg(device_t, int, int); 320 void bnx_miibus_write_reg(device_t, int, int, int); 321 void bnx_miibus_statchg(struct ifnet *); 322 323 /****************************************************************************/ 324 /* BNX NVRAM Access Routines */ 325 /****************************************************************************/ 326 int bnx_acquire_nvram_lock(struct bnx_softc *); 327 int bnx_release_nvram_lock(struct bnx_softc *); 328 void bnx_enable_nvram_access(struct bnx_softc *); 329 void bnx_disable_nvram_access(struct bnx_softc *); 330 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 331 uint32_t); 332 int bnx_init_nvram(struct bnx_softc *); 333 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 334 int bnx_nvram_test(struct bnx_softc *); 335 #ifdef BNX_NVRAM_WRITE_SUPPORT 336 int bnx_enable_nvram_write(struct bnx_softc *); 337 void bnx_disable_nvram_write(struct bnx_softc *); 338 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 339 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 340 uint32_t); 341 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 342 #endif 343 344 /****************************************************************************/ 345 /* */ 346 /****************************************************************************/ 347 void bnx_get_media(struct bnx_softc *); 348 void bnx_init_media(struct bnx_softc *); 349 int bnx_dma_alloc(struct bnx_softc *); 350 void bnx_dma_free(struct bnx_softc *); 351 void bnx_release_resources(struct bnx_softc *); 352 353 /****************************************************************************/ 354 /* BNX Firmware Synchronization and Load */ 355 /****************************************************************************/ 356 int bnx_fw_sync(struct bnx_softc *, uint32_t); 357 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 358 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 359 struct fw_info *); 360 void bnx_init_cpus(struct bnx_softc *); 361 362 static void bnx_print_adapter_info(struct bnx_softc *); 363 static void bnx_probe_pci_caps(struct bnx_softc *); 364 void bnx_stop(struct ifnet *, int); 365 int bnx_reset(struct bnx_softc *, uint32_t); 366 int bnx_chipinit(struct bnx_softc *); 367 int bnx_blockinit(struct bnx_softc *); 368 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 369 uint16_t *, uint32_t *); 370 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 371 372 int bnx_init_tx_chain(struct bnx_softc *); 373 void bnx_init_tx_context(struct bnx_softc *); 374 int bnx_init_rx_chain(struct bnx_softc *); 375 void bnx_init_rx_context(struct bnx_softc *); 376 void bnx_free_rx_chain(struct bnx_softc *); 377 void bnx_free_tx_chain(struct bnx_softc *); 378 379 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 380 void bnx_start(struct ifnet *); 381 int bnx_ioctl(struct ifnet *, u_long, void *); 382 void bnx_watchdog(struct ifnet *); 383 int bnx_init(struct ifnet *); 384 385 void bnx_init_context(struct bnx_softc *); 386 void bnx_get_mac_addr(struct bnx_softc *); 387 void bnx_set_mac_addr(struct bnx_softc *); 388 void bnx_phy_intr(struct bnx_softc *); 389 void bnx_rx_intr(struct bnx_softc *); 390 void bnx_tx_intr(struct bnx_softc *); 391 void bnx_disable_intr(struct bnx_softc *); 392 void bnx_enable_intr(struct bnx_softc *); 393 394 int bnx_intr(void *); 395 void bnx_iff(struct bnx_softc *); 396 void bnx_stats_update(struct bnx_softc *); 397 void bnx_tick(void *); 398 399 struct pool *bnx_tx_pool = NULL; 400 void bnx_alloc_pkts(struct work *, void *); 401 402 /****************************************************************************/ 403 /* OpenBSD device dispatch table. */ 404 /****************************************************************************/ 405 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 406 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 407 408 /****************************************************************************/ 409 /* Device probe function. */ 410 /* */ 411 /* Compares the device to the driver's list of supported devices and */ 412 /* reports back to the OS whether this is the right driver for the device. */ 413 /* */ 414 /* Returns: */ 415 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 416 /****************************************************************************/ 417 static const struct bnx_product * 418 bnx_lookup(const struct pci_attach_args *pa) 419 { 420 int i; 421 pcireg_t subid; 422 423 for (i = 0; i < __arraycount(bnx_devices); i++) { 424 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 425 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 426 continue; 427 if (!bnx_devices[i].bp_subvendor) 428 return &bnx_devices[i]; 429 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 430 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 431 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 432 return &bnx_devices[i]; 433 } 434 435 return NULL; 436 } 437 static int 438 bnx_probe(device_t parent, cfdata_t match, void *aux) 439 { 440 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 441 442 if (bnx_lookup(pa) != NULL) 443 return 1; 444 445 return 0; 446 } 447 448 /****************************************************************************/ 449 /* PCI Capabilities Probe Function. */ 450 /* */ 451 /* Walks the PCI capabiites list for the device to find what features are */ 452 /* supported. */ 453 /* */ 454 /* Returns: */ 455 /* None. */ 456 /****************************************************************************/ 457 static void 458 bnx_print_adapter_info(struct bnx_softc *sc) 459 { 460 461 aprint_normal_dev(sc->bnx_dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 462 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 463 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 464 ? "Serdes " : "", sc->bnx_chipid); 465 466 /* Bus info. */ 467 if (sc->bnx_flags & BNX_PCIE_FLAG) { 468 aprint_normal_dev(sc->bnx_dev, "PCIe x%d ", 469 sc->link_width); 470 switch (sc->link_speed) { 471 case 1: aprint_normal("2.5Gbps\n"); break; 472 case 2: aprint_normal("5Gbps\n"); break; 473 default: aprint_normal("Unknown link speed\n"); 474 } 475 } else { 476 aprint_normal_dev(sc->bnx_dev, "PCI%s %dbit %dMHz\n", 477 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 478 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 479 sc->bus_speed_mhz); 480 } 481 482 aprint_normal_dev(sc->bnx_dev, 483 "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 484 sc->bnx_rx_quick_cons_trip_int, 485 sc->bnx_rx_quick_cons_trip, 486 sc->bnx_rx_ticks_int, 487 sc->bnx_rx_ticks, 488 sc->bnx_tx_quick_cons_trip_int, 489 sc->bnx_tx_quick_cons_trip, 490 sc->bnx_tx_ticks_int, 491 sc->bnx_tx_ticks); 492 } 493 494 495 /****************************************************************************/ 496 /* PCI Capabilities Probe Function. */ 497 /* */ 498 /* Walks the PCI capabiites list for the device to find what features are */ 499 /* supported. */ 500 /* */ 501 /* Returns: */ 502 /* None. */ 503 /****************************************************************************/ 504 static void 505 bnx_probe_pci_caps(struct bnx_softc *sc) 506 { 507 struct pci_attach_args *pa = &(sc->bnx_pa); 508 pcireg_t reg; 509 510 /* Check if PCI-X capability is enabled. */ 511 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 512 NULL) != 0) { 513 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 514 } 515 516 /* Check if PCIe capability is enabled. */ 517 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 518 NULL) != 0) { 519 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 520 reg + PCIE_LCSR); 521 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 522 "0x%08X\n", link_status); 523 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 524 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 525 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 526 sc->bnx_flags |= BNX_PCIE_FLAG; 527 } 528 529 /* Check if MSI capability is enabled. */ 530 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 531 NULL) != 0) 532 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 533 534 /* Check if MSI-X capability is enabled. */ 535 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 536 NULL) != 0) 537 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 538 } 539 540 541 /****************************************************************************/ 542 /* Device attach function. */ 543 /* */ 544 /* Allocates device resources, performs secondary chip identification, */ 545 /* resets and initializes the hardware, and initializes driver instance */ 546 /* variables. */ 547 /* */ 548 /* Returns: */ 549 /* 0 on success, positive value on failure. */ 550 /****************************************************************************/ 551 void 552 bnx_attach(device_t parent, device_t self, void *aux) 553 { 554 const struct bnx_product *bp; 555 struct bnx_softc *sc = device_private(self); 556 prop_dictionary_t dict; 557 struct pci_attach_args *pa = aux; 558 pci_chipset_tag_t pc = pa->pa_pc; 559 pci_intr_handle_t ih; 560 const char *intrstr = NULL; 561 uint32_t command; 562 struct ifnet *ifp; 563 uint32_t val; 564 int mii_flags = MIIF_FORCEANEG; 565 pcireg_t memtype; 566 char intrbuf[PCI_INTRSTR_LEN]; 567 568 if (bnx_tx_pool == NULL) { 569 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 570 if (bnx_tx_pool != NULL) { 571 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 572 0, 0, 0, "bnxpkts", NULL, IPL_NET); 573 } else { 574 aprint_error(": can't alloc bnx_tx_pool\n"); 575 return; 576 } 577 } 578 579 bp = bnx_lookup(pa); 580 if (bp == NULL) 581 panic("unknown device"); 582 583 sc->bnx_dev = self; 584 585 aprint_naive("\n"); 586 aprint_normal(": %s\n", bp->bp_name); 587 588 sc->bnx_pa = *pa; 589 590 /* 591 * Map control/status registers. 592 */ 593 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 594 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 595 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 596 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 597 598 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 599 aprint_error_dev(sc->bnx_dev, 600 "failed to enable memory mapping!\n"); 601 return; 602 } 603 604 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 605 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 606 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 607 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 608 return; 609 } 610 611 if (pci_intr_map(pa, &ih)) { 612 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 613 goto bnx_attach_fail; 614 } 615 616 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 617 618 /* 619 * Configure byte swap and enable indirect register access. 620 * Rely on CPU to do target byte swapping on big endian systems. 621 * Access to registers outside of PCI configurtion space are not 622 * valid until this is done. 623 */ 624 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 625 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 626 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 627 628 /* Save ASIC revsion info. */ 629 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 630 631 /* 632 * Find the base address for shared memory access. 633 * Newer versions of bootcode use a signature and offset 634 * while older versions use a fixed address. 635 */ 636 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 637 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 638 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 639 (sc->bnx_pa.pa_function << 2)); 640 else 641 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 642 643 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 644 645 /* Set initial device and PHY flags */ 646 sc->bnx_flags = 0; 647 sc->bnx_phy_flags = 0; 648 649 bnx_probe_pci_caps(sc); 650 651 /* Get PCI bus information (speed and type). */ 652 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 653 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 654 uint32_t clkreg; 655 656 sc->bnx_flags |= BNX_PCIX_FLAG; 657 658 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 659 660 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 661 switch (clkreg) { 662 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 663 sc->bus_speed_mhz = 133; 664 break; 665 666 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 667 sc->bus_speed_mhz = 100; 668 break; 669 670 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 671 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 672 sc->bus_speed_mhz = 66; 673 break; 674 675 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 676 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 677 sc->bus_speed_mhz = 50; 678 break; 679 680 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 681 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 682 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 683 sc->bus_speed_mhz = 33; 684 break; 685 } 686 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 687 sc->bus_speed_mhz = 66; 688 else 689 sc->bus_speed_mhz = 33; 690 691 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 692 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 693 694 /* Reset the controller. */ 695 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 696 goto bnx_attach_fail; 697 698 /* Initialize the controller. */ 699 if (bnx_chipinit(sc)) { 700 aprint_error_dev(sc->bnx_dev, 701 "Controller initialization failed!\n"); 702 goto bnx_attach_fail; 703 } 704 705 /* Perform NVRAM test. */ 706 if (bnx_nvram_test(sc)) { 707 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 708 goto bnx_attach_fail; 709 } 710 711 /* Fetch the permanent Ethernet MAC address. */ 712 bnx_get_mac_addr(sc); 713 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 714 ether_sprintf(sc->eaddr)); 715 716 /* 717 * Trip points control how many BDs 718 * should be ready before generating an 719 * interrupt while ticks control how long 720 * a BD can sit in the chain before 721 * generating an interrupt. Set the default 722 * values for the RX and TX rings. 723 */ 724 725 #ifdef BNX_DEBUG 726 /* Force more frequent interrupts. */ 727 sc->bnx_tx_quick_cons_trip_int = 1; 728 sc->bnx_tx_quick_cons_trip = 1; 729 sc->bnx_tx_ticks_int = 0; 730 sc->bnx_tx_ticks = 0; 731 732 sc->bnx_rx_quick_cons_trip_int = 1; 733 sc->bnx_rx_quick_cons_trip = 1; 734 sc->bnx_rx_ticks_int = 0; 735 sc->bnx_rx_ticks = 0; 736 #else 737 sc->bnx_tx_quick_cons_trip_int = 20; 738 sc->bnx_tx_quick_cons_trip = 20; 739 sc->bnx_tx_ticks_int = 80; 740 sc->bnx_tx_ticks = 80; 741 742 sc->bnx_rx_quick_cons_trip_int = 6; 743 sc->bnx_rx_quick_cons_trip = 6; 744 sc->bnx_rx_ticks_int = 18; 745 sc->bnx_rx_ticks = 18; 746 #endif 747 748 /* Update statistics once every second. */ 749 sc->bnx_stats_ticks = 1000000 & 0xffff00; 750 751 /* Find the media type for the adapter. */ 752 bnx_get_media(sc); 753 754 /* 755 * Store config data needed by the PHY driver for 756 * backplane applications 757 */ 758 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 759 BNX_SHARED_HW_CFG_CONFIG); 760 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 761 BNX_PORT_HW_CFG_CONFIG); 762 763 /* Allocate DMA memory resources. */ 764 sc->bnx_dmatag = pa->pa_dmat; 765 if (bnx_dma_alloc(sc)) { 766 aprint_error_dev(sc->bnx_dev, 767 "DMA resource allocation failed!\n"); 768 goto bnx_attach_fail; 769 } 770 771 /* Initialize the ifnet interface. */ 772 ifp = &sc->bnx_ec.ec_if; 773 ifp->if_softc = sc; 774 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 775 ifp->if_ioctl = bnx_ioctl; 776 ifp->if_stop = bnx_stop; 777 ifp->if_start = bnx_start; 778 ifp->if_init = bnx_init; 779 ifp->if_timer = 0; 780 ifp->if_watchdog = bnx_watchdog; 781 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 782 IFQ_SET_READY(&ifp->if_snd); 783 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 784 785 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 786 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 787 788 ifp->if_capabilities |= 789 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 790 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 791 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 792 793 /* Hookup IRQ last. */ 794 sc->bnx_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bnx_intr, 795 sc, device_xname(self)); 796 if (sc->bnx_intrhand == NULL) { 797 aprint_error_dev(self, "couldn't establish interrupt"); 798 if (intrstr != NULL) 799 aprint_error(" at %s", intrstr); 800 aprint_error("\n"); 801 goto bnx_attach_fail; 802 } 803 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 804 805 /* create workqueue to handle packet allocations */ 806 if (workqueue_create(&sc->bnx_wq, device_xname(self), 807 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 808 aprint_error_dev(self, "failed to create workqueue\n"); 809 goto bnx_attach_fail; 810 } 811 812 sc->bnx_mii.mii_ifp = ifp; 813 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 814 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 815 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 816 817 /* Handle any special PHY initialization for SerDes PHYs. */ 818 bnx_init_media(sc); 819 820 sc->bnx_ec.ec_mii = &sc->bnx_mii; 821 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 822 ether_mediastatus); 823 824 /* set phyflags and chipid before mii_attach() */ 825 dict = device_properties(self); 826 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 827 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 828 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 829 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 830 831 /* Print some useful adapter info */ 832 bnx_print_adapter_info(sc); 833 834 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 835 mii_flags |= MIIF_HAVEFIBER; 836 mii_attach(self, &sc->bnx_mii, 0xffffffff, 837 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 838 839 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 840 aprint_error_dev(self, "no PHY found!\n"); 841 ifmedia_add(&sc->bnx_mii.mii_media, 842 IFM_ETHER|IFM_MANUAL, 0, NULL); 843 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_MANUAL); 844 } else 845 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_AUTO); 846 847 /* Attach to the Ethernet interface list. */ 848 if_attach(ifp); 849 if_deferred_start_init(ifp, NULL); 850 ether_ifattach(ifp,sc->eaddr); 851 852 callout_init(&sc->bnx_timeout, 0); 853 854 if (pmf_device_register(self, NULL, NULL)) 855 pmf_class_network_register(self, ifp); 856 else 857 aprint_error_dev(self, "couldn't establish power handler\n"); 858 859 /* Print some important debugging info. */ 860 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 861 862 goto bnx_attach_exit; 863 864 bnx_attach_fail: 865 bnx_release_resources(sc); 866 867 bnx_attach_exit: 868 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 869 } 870 871 /****************************************************************************/ 872 /* Device detach function. */ 873 /* */ 874 /* Stops the controller, resets the controller, and releases resources. */ 875 /* */ 876 /* Returns: */ 877 /* 0 on success, positive value on failure. */ 878 /****************************************************************************/ 879 int 880 bnx_detach(device_t dev, int flags) 881 { 882 int s; 883 struct bnx_softc *sc; 884 struct ifnet *ifp; 885 886 sc = device_private(dev); 887 ifp = &sc->bnx_ec.ec_if; 888 889 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 890 891 /* Stop and reset the controller. */ 892 s = splnet(); 893 bnx_stop(ifp, 1); 894 splx(s); 895 896 pmf_device_deregister(dev); 897 callout_destroy(&sc->bnx_timeout); 898 ether_ifdetach(ifp); 899 workqueue_destroy(sc->bnx_wq); 900 901 /* Delete all remaining media. */ 902 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 903 904 if_detach(ifp); 905 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 906 907 /* Release all remaining resources. */ 908 bnx_release_resources(sc); 909 910 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 911 912 return 0; 913 } 914 915 /****************************************************************************/ 916 /* Indirect register read. */ 917 /* */ 918 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 919 /* configuration space. Using this mechanism avoids issues with posted */ 920 /* reads but is much slower than memory-mapped I/O. */ 921 /* */ 922 /* Returns: */ 923 /* The value of the register. */ 924 /****************************************************************************/ 925 uint32_t 926 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 927 { 928 struct pci_attach_args *pa = &(sc->bnx_pa); 929 930 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 931 offset); 932 #ifdef BNX_DEBUG 933 { 934 uint32_t val; 935 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 936 BNX_PCICFG_REG_WINDOW); 937 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 938 "val = 0x%08X\n", __func__, offset, val); 939 return val; 940 } 941 #else 942 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 943 #endif 944 } 945 946 /****************************************************************************/ 947 /* Indirect register write. */ 948 /* */ 949 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 950 /* configuration space. Using this mechanism avoids issues with posted */ 951 /* writes but is muchh slower than memory-mapped I/O. */ 952 /* */ 953 /* Returns: */ 954 /* Nothing. */ 955 /****************************************************************************/ 956 void 957 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 958 { 959 struct pci_attach_args *pa = &(sc->bnx_pa); 960 961 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 962 __func__, offset, val); 963 964 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 965 offset); 966 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 967 } 968 969 /****************************************************************************/ 970 /* Context memory write. */ 971 /* */ 972 /* The NetXtreme II controller uses context memory to track connection */ 973 /* information for L2 and higher network protocols. */ 974 /* */ 975 /* Returns: */ 976 /* Nothing. */ 977 /****************************************************************************/ 978 void 979 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 980 uint32_t ctx_val) 981 { 982 uint32_t idx, offset = ctx_offset + cid_addr; 983 uint32_t val, retry_cnt = 5; 984 985 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 986 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 987 REG_WR(sc, BNX_CTX_CTX_CTRL, 988 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 989 990 for (idx = 0; idx < retry_cnt; idx++) { 991 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 992 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 993 break; 994 DELAY(5); 995 } 996 997 #if 0 998 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 999 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1000 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1001 __FILE__, __LINE__, cid_addr, ctx_offset); 1002 #endif 1003 1004 } else { 1005 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1006 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1007 } 1008 } 1009 1010 /****************************************************************************/ 1011 /* PHY register read. */ 1012 /* */ 1013 /* Implements register reads on the MII bus. */ 1014 /* */ 1015 /* Returns: */ 1016 /* The value of the register. */ 1017 /****************************************************************************/ 1018 int 1019 bnx_miibus_read_reg(device_t dev, int phy, int reg) 1020 { 1021 struct bnx_softc *sc = device_private(dev); 1022 uint32_t val, data; 1023 int i; 1024 1025 /* Make sure we are accessing the correct PHY address. */ 1026 if (phy != sc->bnx_phy_addr) { 1027 DBPRINT(sc, BNX_VERBOSE, 1028 "Invalid PHY address %d for PHY read!\n", phy); 1029 return 0; 1030 } 1031 1032 /* 1033 * The BCM5709S PHY is an IEEE Clause 45 PHY 1034 * with special mappings to work with IEEE 1035 * Clause 22 register accesses. 1036 */ 1037 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1038 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1039 reg += 0x10; 1040 } 1041 1042 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1043 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1044 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1045 1046 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1047 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1048 1049 DELAY(40); 1050 } 1051 1052 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1053 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1054 BNX_EMAC_MDIO_COMM_START_BUSY; 1055 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1056 1057 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1058 DELAY(10); 1059 1060 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1061 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1062 DELAY(5); 1063 1064 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1065 data &= BNX_EMAC_MDIO_COMM_DATA; 1066 1067 break; 1068 } 1069 } 1070 1071 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1072 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1073 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1074 val = 0x0; 1075 } else 1076 val = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1077 1078 DBPRINT(sc, BNX_EXCESSIVE, 1079 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __func__, phy, 1080 (uint16_t) reg & 0xffff, (uint16_t) val & 0xffff); 1081 1082 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1083 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1084 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1085 1086 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1087 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1088 1089 DELAY(40); 1090 } 1091 1092 return (val & 0xffff); 1093 } 1094 1095 /****************************************************************************/ 1096 /* PHY register write. */ 1097 /* */ 1098 /* Implements register writes on the MII bus. */ 1099 /* */ 1100 /* Returns: */ 1101 /* The value of the register. */ 1102 /****************************************************************************/ 1103 void 1104 bnx_miibus_write_reg(device_t dev, int phy, int reg, int val) 1105 { 1106 struct bnx_softc *sc = device_private(dev); 1107 uint32_t val1; 1108 int i; 1109 1110 /* Make sure we are accessing the correct PHY address. */ 1111 if (phy != sc->bnx_phy_addr) { 1112 DBPRINT(sc, BNX_WARN, 1113 "Invalid PHY address %d for PHY write!\n", phy); 1114 return; 1115 } 1116 1117 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1118 "val = 0x%04X\n", __func__, 1119 phy, (uint16_t) reg & 0xffff, (uint16_t) val & 0xffff); 1120 1121 /* 1122 * The BCM5709S PHY is an IEEE Clause 45 PHY 1123 * with special mappings to work with IEEE 1124 * Clause 22 register accesses. 1125 */ 1126 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1127 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1128 reg += 0x10; 1129 } 1130 1131 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1132 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1133 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1134 1135 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1136 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1137 1138 DELAY(40); 1139 } 1140 1141 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1142 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1143 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1144 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1145 1146 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1147 DELAY(10); 1148 1149 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1150 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1151 DELAY(5); 1152 break; 1153 } 1154 } 1155 1156 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1157 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1158 __LINE__); 1159 } 1160 1161 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1162 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1163 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1164 1165 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1166 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1167 1168 DELAY(40); 1169 } 1170 } 1171 1172 /****************************************************************************/ 1173 /* MII bus status change. */ 1174 /* */ 1175 /* Called by the MII bus driver when the PHY establishes link to set the */ 1176 /* MAC interface registers. */ 1177 /* */ 1178 /* Returns: */ 1179 /* Nothing. */ 1180 /****************************************************************************/ 1181 void 1182 bnx_miibus_statchg(struct ifnet *ifp) 1183 { 1184 struct bnx_softc *sc = ifp->if_softc; 1185 struct mii_data *mii = &sc->bnx_mii; 1186 int val; 1187 1188 val = REG_RD(sc, BNX_EMAC_MODE); 1189 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1190 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1191 BNX_EMAC_MODE_25G); 1192 1193 /* Set MII or GMII interface based on the speed 1194 * negotiated by the PHY. 1195 */ 1196 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1197 case IFM_10_T: 1198 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1199 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1200 val |= BNX_EMAC_MODE_PORT_MII_10; 1201 break; 1202 } 1203 /* FALLTHROUGH */ 1204 case IFM_100_TX: 1205 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1206 val |= BNX_EMAC_MODE_PORT_MII; 1207 break; 1208 case IFM_2500_SX: 1209 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1210 val |= BNX_EMAC_MODE_25G; 1211 /* FALLTHROUGH */ 1212 case IFM_1000_T: 1213 case IFM_1000_SX: 1214 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1215 val |= BNX_EMAC_MODE_PORT_GMII; 1216 break; 1217 default: 1218 val |= BNX_EMAC_MODE_PORT_GMII; 1219 break; 1220 } 1221 1222 /* Set half or full duplex based on the duplicity 1223 * negotiated by the PHY. 1224 */ 1225 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1226 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1227 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1228 } else { 1229 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1230 } 1231 1232 REG_WR(sc, BNX_EMAC_MODE, val); 1233 } 1234 1235 /****************************************************************************/ 1236 /* Acquire NVRAM lock. */ 1237 /* */ 1238 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1239 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1240 /* for use by the driver. */ 1241 /* */ 1242 /* Returns: */ 1243 /* 0 on success, positive value on failure. */ 1244 /****************************************************************************/ 1245 int 1246 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1247 { 1248 uint32_t val; 1249 int j; 1250 1251 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1252 1253 /* Request access to the flash interface. */ 1254 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1255 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1256 val = REG_RD(sc, BNX_NVM_SW_ARB); 1257 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1258 break; 1259 1260 DELAY(5); 1261 } 1262 1263 if (j >= NVRAM_TIMEOUT_COUNT) { 1264 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1265 return EBUSY; 1266 } 1267 1268 return 0; 1269 } 1270 1271 /****************************************************************************/ 1272 /* Release NVRAM lock. */ 1273 /* */ 1274 /* When the caller is finished accessing NVRAM the lock must be released. */ 1275 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1276 /* for use by the driver. */ 1277 /* */ 1278 /* Returns: */ 1279 /* 0 on success, positive value on failure. */ 1280 /****************************************************************************/ 1281 int 1282 bnx_release_nvram_lock(struct bnx_softc *sc) 1283 { 1284 int j; 1285 uint32_t val; 1286 1287 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1288 1289 /* Relinquish nvram interface. */ 1290 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1291 1292 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1293 val = REG_RD(sc, BNX_NVM_SW_ARB); 1294 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1295 break; 1296 1297 DELAY(5); 1298 } 1299 1300 if (j >= NVRAM_TIMEOUT_COUNT) { 1301 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1302 return EBUSY; 1303 } 1304 1305 return 0; 1306 } 1307 1308 #ifdef BNX_NVRAM_WRITE_SUPPORT 1309 /****************************************************************************/ 1310 /* Enable NVRAM write access. */ 1311 /* */ 1312 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1313 /* */ 1314 /* Returns: */ 1315 /* 0 on success, positive value on failure. */ 1316 /****************************************************************************/ 1317 int 1318 bnx_enable_nvram_write(struct bnx_softc *sc) 1319 { 1320 uint32_t val; 1321 1322 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1323 1324 val = REG_RD(sc, BNX_MISC_CFG); 1325 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1326 1327 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1328 int j; 1329 1330 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1331 REG_WR(sc, BNX_NVM_COMMAND, 1332 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1333 1334 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1335 DELAY(5); 1336 1337 val = REG_RD(sc, BNX_NVM_COMMAND); 1338 if (val & BNX_NVM_COMMAND_DONE) 1339 break; 1340 } 1341 1342 if (j >= NVRAM_TIMEOUT_COUNT) { 1343 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1344 return EBUSY; 1345 } 1346 } 1347 1348 return 0; 1349 } 1350 1351 /****************************************************************************/ 1352 /* Disable NVRAM write access. */ 1353 /* */ 1354 /* When the caller is finished writing to NVRAM write access must be */ 1355 /* disabled. */ 1356 /* */ 1357 /* Returns: */ 1358 /* Nothing. */ 1359 /****************************************************************************/ 1360 void 1361 bnx_disable_nvram_write(struct bnx_softc *sc) 1362 { 1363 uint32_t val; 1364 1365 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1366 1367 val = REG_RD(sc, BNX_MISC_CFG); 1368 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1369 } 1370 #endif 1371 1372 /****************************************************************************/ 1373 /* Enable NVRAM access. */ 1374 /* */ 1375 /* Before accessing NVRAM for read or write operations the caller must */ 1376 /* enabled NVRAM access. */ 1377 /* */ 1378 /* Returns: */ 1379 /* Nothing. */ 1380 /****************************************************************************/ 1381 void 1382 bnx_enable_nvram_access(struct bnx_softc *sc) 1383 { 1384 uint32_t val; 1385 1386 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1387 1388 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1389 /* Enable both bits, even on read. */ 1390 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1391 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1392 } 1393 1394 /****************************************************************************/ 1395 /* Disable NVRAM access. */ 1396 /* */ 1397 /* When the caller is finished accessing NVRAM access must be disabled. */ 1398 /* */ 1399 /* Returns: */ 1400 /* Nothing. */ 1401 /****************************************************************************/ 1402 void 1403 bnx_disable_nvram_access(struct bnx_softc *sc) 1404 { 1405 uint32_t val; 1406 1407 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1408 1409 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1410 1411 /* Disable both bits, even after read. */ 1412 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1413 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1414 } 1415 1416 #ifdef BNX_NVRAM_WRITE_SUPPORT 1417 /****************************************************************************/ 1418 /* Erase NVRAM page before writing. */ 1419 /* */ 1420 /* Non-buffered flash parts require that a page be erased before it is */ 1421 /* written. */ 1422 /* */ 1423 /* Returns: */ 1424 /* 0 on success, positive value on failure. */ 1425 /****************************************************************************/ 1426 int 1427 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1428 { 1429 uint32_t cmd; 1430 int j; 1431 1432 /* Buffered flash doesn't require an erase. */ 1433 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1434 return 0; 1435 1436 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1437 1438 /* Build an erase command. */ 1439 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1440 BNX_NVM_COMMAND_DOIT; 1441 1442 /* 1443 * Clear the DONE bit separately, set the NVRAM address to erase, 1444 * and issue the erase command. 1445 */ 1446 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1447 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1448 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1449 1450 /* Wait for completion. */ 1451 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1452 uint32_t val; 1453 1454 DELAY(5); 1455 1456 val = REG_RD(sc, BNX_NVM_COMMAND); 1457 if (val & BNX_NVM_COMMAND_DONE) 1458 break; 1459 } 1460 1461 if (j >= NVRAM_TIMEOUT_COUNT) { 1462 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1463 return EBUSY; 1464 } 1465 1466 return 0; 1467 } 1468 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1469 1470 /****************************************************************************/ 1471 /* Read a dword (32 bits) from NVRAM. */ 1472 /* */ 1473 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1474 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1475 /* */ 1476 /* Returns: */ 1477 /* 0 on success and the 32 bit value read, positive value on failure. */ 1478 /****************************************************************************/ 1479 int 1480 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1481 uint8_t *ret_val, uint32_t cmd_flags) 1482 { 1483 uint32_t cmd; 1484 int i, rc = 0; 1485 1486 /* Build the command word. */ 1487 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1488 1489 /* Calculate the offset for buffered flash if translation is used. */ 1490 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1491 offset = ((offset / sc->bnx_flash_info->page_size) << 1492 sc->bnx_flash_info->page_bits) + 1493 (offset % sc->bnx_flash_info->page_size); 1494 } 1495 1496 /* 1497 * Clear the DONE bit separately, set the address to read, 1498 * and issue the read. 1499 */ 1500 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1501 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1502 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1503 1504 /* Wait for completion. */ 1505 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1506 uint32_t val; 1507 1508 DELAY(5); 1509 1510 val = REG_RD(sc, BNX_NVM_COMMAND); 1511 if (val & BNX_NVM_COMMAND_DONE) { 1512 val = REG_RD(sc, BNX_NVM_READ); 1513 1514 val = bnx_be32toh(val); 1515 memcpy(ret_val, &val, 4); 1516 break; 1517 } 1518 } 1519 1520 /* Check for errors. */ 1521 if (i >= NVRAM_TIMEOUT_COUNT) { 1522 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1523 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1524 rc = EBUSY; 1525 } 1526 1527 return rc; 1528 } 1529 1530 #ifdef BNX_NVRAM_WRITE_SUPPORT 1531 /****************************************************************************/ 1532 /* Write a dword (32 bits) to NVRAM. */ 1533 /* */ 1534 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1535 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1536 /* enabled NVRAM write access. */ 1537 /* */ 1538 /* Returns: */ 1539 /* 0 on success, positive value on failure. */ 1540 /****************************************************************************/ 1541 int 1542 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1543 uint32_t cmd_flags) 1544 { 1545 uint32_t cmd, val32; 1546 int j; 1547 1548 /* Build the command word. */ 1549 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1550 1551 /* Calculate the offset for buffered flash if translation is used. */ 1552 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1553 offset = ((offset / sc->bnx_flash_info->page_size) << 1554 sc->bnx_flash_info->page_bits) + 1555 (offset % sc->bnx_flash_info->page_size); 1556 } 1557 1558 /* 1559 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1560 * set the NVRAM address to write, and issue the write command 1561 */ 1562 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1563 memcpy(&val32, val, 4); 1564 val32 = htobe32(val32); 1565 REG_WR(sc, BNX_NVM_WRITE, val32); 1566 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1567 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1568 1569 /* Wait for completion. */ 1570 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1571 DELAY(5); 1572 1573 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1574 break; 1575 } 1576 if (j >= NVRAM_TIMEOUT_COUNT) { 1577 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1578 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1579 return EBUSY; 1580 } 1581 1582 return 0; 1583 } 1584 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1585 1586 /****************************************************************************/ 1587 /* Initialize NVRAM access. */ 1588 /* */ 1589 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1590 /* access that device. */ 1591 /* */ 1592 /* Returns: */ 1593 /* 0 on success, positive value on failure. */ 1594 /****************************************************************************/ 1595 int 1596 bnx_init_nvram(struct bnx_softc *sc) 1597 { 1598 uint32_t val; 1599 int j, entry_count, rc = 0; 1600 struct flash_spec *flash; 1601 1602 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1603 1604 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1605 sc->bnx_flash_info = &flash_5709; 1606 goto bnx_init_nvram_get_flash_size; 1607 } 1608 1609 /* Determine the selected interface. */ 1610 val = REG_RD(sc, BNX_NVM_CFG1); 1611 1612 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1613 1614 /* 1615 * Flash reconfiguration is required to support additional 1616 * NVRAM devices not directly supported in hardware. 1617 * Check if the flash interface was reconfigured 1618 * by the bootcode. 1619 */ 1620 1621 if (val & 0x40000000) { 1622 /* Flash interface reconfigured by bootcode. */ 1623 1624 DBPRINT(sc,BNX_INFO_LOAD, 1625 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1626 1627 for (j = 0, flash = &flash_table[0]; j < entry_count; 1628 j++, flash++) { 1629 if ((val & FLASH_BACKUP_STRAP_MASK) == 1630 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1631 sc->bnx_flash_info = flash; 1632 break; 1633 } 1634 } 1635 } else { 1636 /* Flash interface not yet reconfigured. */ 1637 uint32_t mask; 1638 1639 DBPRINT(sc,BNX_INFO_LOAD, 1640 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1641 1642 if (val & (1 << 23)) 1643 mask = FLASH_BACKUP_STRAP_MASK; 1644 else 1645 mask = FLASH_STRAP_MASK; 1646 1647 /* Look for the matching NVRAM device configuration data. */ 1648 for (j = 0, flash = &flash_table[0]; j < entry_count; 1649 j++, flash++) { 1650 /* Check if the dev matches any of the known devices. */ 1651 if ((val & mask) == (flash->strapping & mask)) { 1652 /* Found a device match. */ 1653 sc->bnx_flash_info = flash; 1654 1655 /* Request access to the flash interface. */ 1656 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1657 return rc; 1658 1659 /* Reconfigure the flash interface. */ 1660 bnx_enable_nvram_access(sc); 1661 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1662 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1663 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1664 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1665 bnx_disable_nvram_access(sc); 1666 bnx_release_nvram_lock(sc); 1667 1668 break; 1669 } 1670 } 1671 } 1672 1673 /* Check if a matching device was found. */ 1674 if (j == entry_count) { 1675 sc->bnx_flash_info = NULL; 1676 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1677 __FILE__, __LINE__); 1678 rc = ENODEV; 1679 } 1680 1681 bnx_init_nvram_get_flash_size: 1682 /* Write the flash config data to the shared memory interface. */ 1683 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1684 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1685 if (val) 1686 sc->bnx_flash_size = val; 1687 else 1688 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1689 1690 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1691 "0x%08X\n", sc->bnx_flash_info->total_size); 1692 1693 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1694 1695 return rc; 1696 } 1697 1698 /****************************************************************************/ 1699 /* Read an arbitrary range of data from NVRAM. */ 1700 /* */ 1701 /* Prepares the NVRAM interface for access and reads the requested data */ 1702 /* into the supplied buffer. */ 1703 /* */ 1704 /* Returns: */ 1705 /* 0 on success and the data read, positive value on failure. */ 1706 /****************************************************************************/ 1707 int 1708 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1709 int buf_size) 1710 { 1711 int rc = 0; 1712 uint32_t cmd_flags, offset32, len32, extra; 1713 1714 if (buf_size == 0) 1715 return 0; 1716 1717 /* Request access to the flash interface. */ 1718 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1719 return rc; 1720 1721 /* Enable access to flash interface */ 1722 bnx_enable_nvram_access(sc); 1723 1724 len32 = buf_size; 1725 offset32 = offset; 1726 extra = 0; 1727 1728 cmd_flags = 0; 1729 1730 if (offset32 & 3) { 1731 uint8_t buf[4]; 1732 uint32_t pre_len; 1733 1734 offset32 &= ~3; 1735 pre_len = 4 - (offset & 3); 1736 1737 if (pre_len >= len32) { 1738 pre_len = len32; 1739 cmd_flags = 1740 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1741 } else 1742 cmd_flags = BNX_NVM_COMMAND_FIRST; 1743 1744 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1745 1746 if (rc) 1747 return rc; 1748 1749 memcpy(ret_buf, buf + (offset & 3), pre_len); 1750 1751 offset32 += 4; 1752 ret_buf += pre_len; 1753 len32 -= pre_len; 1754 } 1755 1756 if (len32 & 3) { 1757 extra = 4 - (len32 & 3); 1758 len32 = (len32 + 4) & ~3; 1759 } 1760 1761 if (len32 == 4) { 1762 uint8_t buf[4]; 1763 1764 if (cmd_flags) 1765 cmd_flags = BNX_NVM_COMMAND_LAST; 1766 else 1767 cmd_flags = 1768 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1769 1770 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1771 1772 memcpy(ret_buf, buf, 4 - extra); 1773 } else if (len32 > 0) { 1774 uint8_t buf[4]; 1775 1776 /* Read the first word. */ 1777 if (cmd_flags) 1778 cmd_flags = 0; 1779 else 1780 cmd_flags = BNX_NVM_COMMAND_FIRST; 1781 1782 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1783 1784 /* Advance to the next dword. */ 1785 offset32 += 4; 1786 ret_buf += 4; 1787 len32 -= 4; 1788 1789 while (len32 > 4 && rc == 0) { 1790 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1791 1792 /* Advance to the next dword. */ 1793 offset32 += 4; 1794 ret_buf += 4; 1795 len32 -= 4; 1796 } 1797 1798 if (rc) 1799 return rc; 1800 1801 cmd_flags = BNX_NVM_COMMAND_LAST; 1802 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1803 1804 memcpy(ret_buf, buf, 4 - extra); 1805 } 1806 1807 /* Disable access to flash interface and release the lock. */ 1808 bnx_disable_nvram_access(sc); 1809 bnx_release_nvram_lock(sc); 1810 1811 return rc; 1812 } 1813 1814 #ifdef BNX_NVRAM_WRITE_SUPPORT 1815 /****************************************************************************/ 1816 /* Write an arbitrary range of data from NVRAM. */ 1817 /* */ 1818 /* Prepares the NVRAM interface for write access and writes the requested */ 1819 /* data from the supplied buffer. The caller is responsible for */ 1820 /* calculating any appropriate CRCs. */ 1821 /* */ 1822 /* Returns: */ 1823 /* 0 on success, positive value on failure. */ 1824 /****************************************************************************/ 1825 int 1826 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1827 int buf_size) 1828 { 1829 uint32_t written, offset32, len32; 1830 uint8_t *buf, start[4], end[4]; 1831 int rc = 0; 1832 int align_start, align_end; 1833 1834 buf = data_buf; 1835 offset32 = offset; 1836 len32 = buf_size; 1837 align_start = align_end = 0; 1838 1839 if ((align_start = (offset32 & 3))) { 1840 offset32 &= ~3; 1841 len32 += align_start; 1842 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1843 return rc; 1844 } 1845 1846 if (len32 & 3) { 1847 if ((len32 > 4) || !align_start) { 1848 align_end = 4 - (len32 & 3); 1849 len32 += align_end; 1850 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1851 end, 4))) 1852 return rc; 1853 } 1854 } 1855 1856 if (align_start || align_end) { 1857 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1858 if (buf == 0) 1859 return ENOMEM; 1860 1861 if (align_start) 1862 memcpy(buf, start, 4); 1863 1864 if (align_end) 1865 memcpy(buf + len32 - 4, end, 4); 1866 1867 memcpy(buf + align_start, data_buf, buf_size); 1868 } 1869 1870 written = 0; 1871 while ((written < len32) && (rc == 0)) { 1872 uint32_t page_start, page_end, data_start, data_end; 1873 uint32_t addr, cmd_flags; 1874 int i; 1875 uint8_t flash_buffer[264]; 1876 1877 /* Find the page_start addr */ 1878 page_start = offset32 + written; 1879 page_start -= (page_start % sc->bnx_flash_info->page_size); 1880 /* Find the page_end addr */ 1881 page_end = page_start + sc->bnx_flash_info->page_size; 1882 /* Find the data_start addr */ 1883 data_start = (written == 0) ? offset32 : page_start; 1884 /* Find the data_end addr */ 1885 data_end = (page_end > offset32 + len32) ? 1886 (offset32 + len32) : page_end; 1887 1888 /* Request access to the flash interface. */ 1889 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1890 goto nvram_write_end; 1891 1892 /* Enable access to flash interface */ 1893 bnx_enable_nvram_access(sc); 1894 1895 cmd_flags = BNX_NVM_COMMAND_FIRST; 1896 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1897 int j; 1898 1899 /* Read the whole page into the buffer 1900 * (non-buffer flash only) */ 1901 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1902 if (j == (sc->bnx_flash_info->page_size - 4)) 1903 cmd_flags |= BNX_NVM_COMMAND_LAST; 1904 1905 rc = bnx_nvram_read_dword(sc, 1906 page_start + j, 1907 &flash_buffer[j], 1908 cmd_flags); 1909 1910 if (rc) 1911 goto nvram_write_end; 1912 1913 cmd_flags = 0; 1914 } 1915 } 1916 1917 /* Enable writes to flash interface (unlock write-protect) */ 1918 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1919 goto nvram_write_end; 1920 1921 /* Erase the page */ 1922 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1923 goto nvram_write_end; 1924 1925 /* Re-enable the write again for the actual write */ 1926 bnx_enable_nvram_write(sc); 1927 1928 /* Loop to write back the buffer data from page_start to 1929 * data_start */ 1930 i = 0; 1931 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1932 for (addr = page_start; addr < data_start; 1933 addr += 4, i += 4) { 1934 1935 rc = bnx_nvram_write_dword(sc, addr, 1936 &flash_buffer[i], cmd_flags); 1937 1938 if (rc != 0) 1939 goto nvram_write_end; 1940 1941 cmd_flags = 0; 1942 } 1943 } 1944 1945 /* Loop to write the new data from data_start to data_end */ 1946 for (addr = data_start; addr < data_end; addr += 4, i++) { 1947 if ((addr == page_end - 4) || 1948 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1949 && (addr == data_end - 4))) { 1950 1951 cmd_flags |= BNX_NVM_COMMAND_LAST; 1952 } 1953 1954 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1955 1956 if (rc != 0) 1957 goto nvram_write_end; 1958 1959 cmd_flags = 0; 1960 buf += 4; 1961 } 1962 1963 /* Loop to write back the buffer data from data_end 1964 * to page_end */ 1965 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1966 for (addr = data_end; addr < page_end; 1967 addr += 4, i += 4) { 1968 1969 if (addr == page_end-4) 1970 cmd_flags = BNX_NVM_COMMAND_LAST; 1971 1972 rc = bnx_nvram_write_dword(sc, addr, 1973 &flash_buffer[i], cmd_flags); 1974 1975 if (rc != 0) 1976 goto nvram_write_end; 1977 1978 cmd_flags = 0; 1979 } 1980 } 1981 1982 /* Disable writes to flash interface (lock write-protect) */ 1983 bnx_disable_nvram_write(sc); 1984 1985 /* Disable access to flash interface */ 1986 bnx_disable_nvram_access(sc); 1987 bnx_release_nvram_lock(sc); 1988 1989 /* Increment written */ 1990 written += data_end - data_start; 1991 } 1992 1993 nvram_write_end: 1994 if (align_start || align_end) 1995 free(buf, M_DEVBUF); 1996 1997 return rc; 1998 } 1999 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2000 2001 /****************************************************************************/ 2002 /* Verifies that NVRAM is accessible and contains valid data. */ 2003 /* */ 2004 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2005 /* correct. */ 2006 /* */ 2007 /* Returns: */ 2008 /* 0 on success, positive value on failure. */ 2009 /****************************************************************************/ 2010 int 2011 bnx_nvram_test(struct bnx_softc *sc) 2012 { 2013 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2014 uint8_t *data = (uint8_t *) buf; 2015 int rc = 0; 2016 uint32_t magic, csum; 2017 2018 /* 2019 * Check that the device NVRAM is valid by reading 2020 * the magic value at offset 0. 2021 */ 2022 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2023 goto bnx_nvram_test_done; 2024 2025 magic = bnx_be32toh(buf[0]); 2026 if (magic != BNX_NVRAM_MAGIC) { 2027 rc = ENODEV; 2028 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2029 "Expected: 0x%08X, Found: 0x%08X\n", 2030 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2031 goto bnx_nvram_test_done; 2032 } 2033 2034 /* 2035 * Verify that the device NVRAM includes valid 2036 * configuration data. 2037 */ 2038 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2039 goto bnx_nvram_test_done; 2040 2041 csum = ether_crc32_le(data, 0x100); 2042 if (csum != BNX_CRC32_RESIDUAL) { 2043 rc = ENODEV; 2044 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2045 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2046 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2047 goto bnx_nvram_test_done; 2048 } 2049 2050 csum = ether_crc32_le(data + 0x100, 0x100); 2051 if (csum != BNX_CRC32_RESIDUAL) { 2052 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2053 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2054 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2055 rc = ENODEV; 2056 } 2057 2058 bnx_nvram_test_done: 2059 return rc; 2060 } 2061 2062 /****************************************************************************/ 2063 /* Identifies the current media type of the controller and sets the PHY */ 2064 /* address. */ 2065 /* */ 2066 /* Returns: */ 2067 /* Nothing. */ 2068 /****************************************************************************/ 2069 void 2070 bnx_get_media(struct bnx_softc *sc) 2071 { 2072 sc->bnx_phy_addr = 1; 2073 2074 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2075 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2076 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2077 uint32_t strap; 2078 2079 /* 2080 * The BCM5709S is software configurable 2081 * for Copper or SerDes operation. 2082 */ 2083 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2084 DBPRINT(sc, BNX_INFO_LOAD, 2085 "5709 bonded for copper.\n"); 2086 goto bnx_get_media_exit; 2087 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2088 DBPRINT(sc, BNX_INFO_LOAD, 2089 "5709 bonded for dual media.\n"); 2090 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2091 goto bnx_get_media_exit; 2092 } 2093 2094 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2095 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2096 else { 2097 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2098 >> 8; 2099 } 2100 2101 if (sc->bnx_pa.pa_function == 0) { 2102 switch (strap) { 2103 case 0x4: 2104 case 0x5: 2105 case 0x6: 2106 DBPRINT(sc, BNX_INFO_LOAD, 2107 "BCM5709 s/w configured for SerDes.\n"); 2108 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2109 break; 2110 default: 2111 DBPRINT(sc, BNX_INFO_LOAD, 2112 "BCM5709 s/w configured for Copper.\n"); 2113 } 2114 } else { 2115 switch (strap) { 2116 case 0x1: 2117 case 0x2: 2118 case 0x4: 2119 DBPRINT(sc, BNX_INFO_LOAD, 2120 "BCM5709 s/w configured for SerDes.\n"); 2121 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2122 break; 2123 default: 2124 DBPRINT(sc, BNX_INFO_LOAD, 2125 "BCM5709 s/w configured for Copper.\n"); 2126 } 2127 } 2128 2129 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2130 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2131 2132 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2133 uint32_t val; 2134 2135 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2136 2137 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2138 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2139 2140 /* 2141 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2142 * separate PHY for SerDes. 2143 */ 2144 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2145 sc->bnx_phy_addr = 2; 2146 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2147 BNX_SHARED_HW_CFG_CONFIG); 2148 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2149 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2150 DBPRINT(sc, BNX_INFO_LOAD, 2151 "Found 2.5Gb capable adapter\n"); 2152 } 2153 } 2154 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2155 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2156 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2157 2158 bnx_get_media_exit: 2159 DBPRINT(sc, (BNX_INFO_LOAD), 2160 "Using PHY address %d.\n", sc->bnx_phy_addr); 2161 } 2162 2163 /****************************************************************************/ 2164 /* Performs PHY initialization required before MII drivers access the */ 2165 /* device. */ 2166 /* */ 2167 /* Returns: */ 2168 /* Nothing. */ 2169 /****************************************************************************/ 2170 void 2171 bnx_init_media(struct bnx_softc *sc) 2172 { 2173 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2174 /* 2175 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2176 * IEEE Clause 22 method. Otherwise we have no way to attach 2177 * the PHY to the mii(4) layer. PHY specific configuration 2178 * is done by the mii(4) layer. 2179 */ 2180 2181 /* Select auto-negotiation MMD of the PHY. */ 2182 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2183 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2184 2185 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2186 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2187 2188 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2189 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2190 } 2191 } 2192 2193 /****************************************************************************/ 2194 /* Free any DMA memory owned by the driver. */ 2195 /* */ 2196 /* Scans through each data structre that requires DMA memory and frees */ 2197 /* the memory if allocated. */ 2198 /* */ 2199 /* Returns: */ 2200 /* Nothing. */ 2201 /****************************************************************************/ 2202 void 2203 bnx_dma_free(struct bnx_softc *sc) 2204 { 2205 int i; 2206 2207 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2208 2209 /* Destroy the status block. */ 2210 if (sc->status_block != NULL && sc->status_map != NULL) { 2211 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2212 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2213 BNX_STATUS_BLK_SZ); 2214 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2215 sc->status_rseg); 2216 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2217 sc->status_block = NULL; 2218 sc->status_map = NULL; 2219 } 2220 2221 /* Destroy the statistics block. */ 2222 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2223 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2224 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2225 BNX_STATS_BLK_SZ); 2226 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2227 sc->stats_rseg); 2228 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2229 sc->stats_block = NULL; 2230 sc->stats_map = NULL; 2231 } 2232 2233 /* Free, unmap and destroy all context memory pages. */ 2234 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2235 for (i = 0; i < sc->ctx_pages; i++) { 2236 if (sc->ctx_block[i] != NULL) { 2237 bus_dmamap_unload(sc->bnx_dmatag, 2238 sc->ctx_map[i]); 2239 bus_dmamem_unmap(sc->bnx_dmatag, 2240 (void *)sc->ctx_block[i], 2241 BCM_PAGE_SIZE); 2242 bus_dmamem_free(sc->bnx_dmatag, 2243 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2244 bus_dmamap_destroy(sc->bnx_dmatag, 2245 sc->ctx_map[i]); 2246 sc->ctx_block[i] = NULL; 2247 } 2248 } 2249 } 2250 2251 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2252 for (i = 0; i < TX_PAGES; i++ ) { 2253 if (sc->tx_bd_chain[i] != NULL && 2254 sc->tx_bd_chain_map[i] != NULL) { 2255 bus_dmamap_unload(sc->bnx_dmatag, 2256 sc->tx_bd_chain_map[i]); 2257 bus_dmamem_unmap(sc->bnx_dmatag, 2258 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2259 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2260 sc->tx_bd_chain_rseg[i]); 2261 bus_dmamap_destroy(sc->bnx_dmatag, 2262 sc->tx_bd_chain_map[i]); 2263 sc->tx_bd_chain[i] = NULL; 2264 sc->tx_bd_chain_map[i] = NULL; 2265 } 2266 } 2267 2268 /* Destroy the TX dmamaps. */ 2269 /* This isn't necessary since we dont allocate them up front */ 2270 2271 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2272 for (i = 0; i < RX_PAGES; i++ ) { 2273 if (sc->rx_bd_chain[i] != NULL && 2274 sc->rx_bd_chain_map[i] != NULL) { 2275 bus_dmamap_unload(sc->bnx_dmatag, 2276 sc->rx_bd_chain_map[i]); 2277 bus_dmamem_unmap(sc->bnx_dmatag, 2278 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2279 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2280 sc->rx_bd_chain_rseg[i]); 2281 2282 bus_dmamap_destroy(sc->bnx_dmatag, 2283 sc->rx_bd_chain_map[i]); 2284 sc->rx_bd_chain[i] = NULL; 2285 sc->rx_bd_chain_map[i] = NULL; 2286 } 2287 } 2288 2289 /* Unload and destroy the RX mbuf maps. */ 2290 for (i = 0; i < TOTAL_RX_BD; i++) { 2291 if (sc->rx_mbuf_map[i] != NULL) { 2292 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2293 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2294 } 2295 } 2296 2297 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2298 } 2299 2300 /****************************************************************************/ 2301 /* Allocate any DMA memory needed by the driver. */ 2302 /* */ 2303 /* Allocates DMA memory needed for the various global structures needed by */ 2304 /* hardware. */ 2305 /* */ 2306 /* Returns: */ 2307 /* 0 for success, positive value for failure. */ 2308 /****************************************************************************/ 2309 int 2310 bnx_dma_alloc(struct bnx_softc *sc) 2311 { 2312 int i, rc = 0; 2313 2314 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2315 2316 /* 2317 * Allocate DMA memory for the status block, map the memory into DMA 2318 * space, and fetch the physical address of the block. 2319 */ 2320 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2321 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2322 aprint_error_dev(sc->bnx_dev, 2323 "Could not create status block DMA map!\n"); 2324 rc = ENOMEM; 2325 goto bnx_dma_alloc_exit; 2326 } 2327 2328 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2329 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2330 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2331 aprint_error_dev(sc->bnx_dev, 2332 "Could not allocate status block DMA memory!\n"); 2333 rc = ENOMEM; 2334 goto bnx_dma_alloc_exit; 2335 } 2336 2337 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2338 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2339 aprint_error_dev(sc->bnx_dev, 2340 "Could not map status block DMA memory!\n"); 2341 rc = ENOMEM; 2342 goto bnx_dma_alloc_exit; 2343 } 2344 2345 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2346 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2347 aprint_error_dev(sc->bnx_dev, 2348 "Could not load status block DMA memory!\n"); 2349 rc = ENOMEM; 2350 goto bnx_dma_alloc_exit; 2351 } 2352 2353 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2354 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2355 2356 /* DRC - Fix for 64 bit addresses. */ 2357 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2358 (uint32_t) sc->status_block_paddr); 2359 2360 /* BCM5709 uses host memory as cache for context memory. */ 2361 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2362 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2363 if (sc->ctx_pages == 0) 2364 sc->ctx_pages = 1; 2365 if (sc->ctx_pages > 4) /* XXX */ 2366 sc->ctx_pages = 4; 2367 2368 DBRUNIF((sc->ctx_pages > 512), 2369 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2370 __FILE__, __LINE__, sc->ctx_pages)); 2371 2372 2373 for (i = 0; i < sc->ctx_pages; i++) { 2374 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2375 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2376 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2377 &sc->ctx_map[i]) != 0) { 2378 rc = ENOMEM; 2379 goto bnx_dma_alloc_exit; 2380 } 2381 2382 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2383 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2384 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2385 rc = ENOMEM; 2386 goto bnx_dma_alloc_exit; 2387 } 2388 2389 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2390 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2391 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2392 rc = ENOMEM; 2393 goto bnx_dma_alloc_exit; 2394 } 2395 2396 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2397 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2398 BUS_DMA_NOWAIT) != 0) { 2399 rc = ENOMEM; 2400 goto bnx_dma_alloc_exit; 2401 } 2402 2403 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2404 } 2405 } 2406 2407 /* 2408 * Allocate DMA memory for the statistics block, map the memory into 2409 * DMA space, and fetch the physical address of the block. 2410 */ 2411 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2412 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2413 aprint_error_dev(sc->bnx_dev, 2414 "Could not create stats block DMA map!\n"); 2415 rc = ENOMEM; 2416 goto bnx_dma_alloc_exit; 2417 } 2418 2419 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2420 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2421 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2422 aprint_error_dev(sc->bnx_dev, 2423 "Could not allocate stats block DMA memory!\n"); 2424 rc = ENOMEM; 2425 goto bnx_dma_alloc_exit; 2426 } 2427 2428 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2429 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2430 aprint_error_dev(sc->bnx_dev, 2431 "Could not map stats block DMA memory!\n"); 2432 rc = ENOMEM; 2433 goto bnx_dma_alloc_exit; 2434 } 2435 2436 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2437 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2438 aprint_error_dev(sc->bnx_dev, 2439 "Could not load status block DMA memory!\n"); 2440 rc = ENOMEM; 2441 goto bnx_dma_alloc_exit; 2442 } 2443 2444 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2445 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2446 2447 /* DRC - Fix for 64 bit address. */ 2448 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2449 (uint32_t) sc->stats_block_paddr); 2450 2451 /* 2452 * Allocate DMA memory for the TX buffer descriptor chain, 2453 * and fetch the physical address of the block. 2454 */ 2455 for (i = 0; i < TX_PAGES; i++) { 2456 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2457 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2458 &sc->tx_bd_chain_map[i])) { 2459 aprint_error_dev(sc->bnx_dev, 2460 "Could not create Tx desc %d DMA map!\n", i); 2461 rc = ENOMEM; 2462 goto bnx_dma_alloc_exit; 2463 } 2464 2465 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2466 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2467 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2468 aprint_error_dev(sc->bnx_dev, 2469 "Could not allocate TX desc %d DMA memory!\n", 2470 i); 2471 rc = ENOMEM; 2472 goto bnx_dma_alloc_exit; 2473 } 2474 2475 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2476 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2477 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2478 aprint_error_dev(sc->bnx_dev, 2479 "Could not map TX desc %d DMA memory!\n", i); 2480 rc = ENOMEM; 2481 goto bnx_dma_alloc_exit; 2482 } 2483 2484 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2485 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2486 BUS_DMA_NOWAIT)) { 2487 aprint_error_dev(sc->bnx_dev, 2488 "Could not load TX desc %d DMA memory!\n", i); 2489 rc = ENOMEM; 2490 goto bnx_dma_alloc_exit; 2491 } 2492 2493 sc->tx_bd_chain_paddr[i] = 2494 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2495 2496 /* DRC - Fix for 64 bit systems. */ 2497 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2498 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2499 } 2500 2501 /* 2502 * Create lists to hold TX mbufs. 2503 */ 2504 TAILQ_INIT(&sc->tx_free_pkts); 2505 TAILQ_INIT(&sc->tx_used_pkts); 2506 sc->tx_pkt_count = 0; 2507 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2508 2509 /* 2510 * Allocate DMA memory for the Rx buffer descriptor chain, 2511 * and fetch the physical address of the block. 2512 */ 2513 for (i = 0; i < RX_PAGES; i++) { 2514 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2515 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2516 &sc->rx_bd_chain_map[i])) { 2517 aprint_error_dev(sc->bnx_dev, 2518 "Could not create Rx desc %d DMA map!\n", i); 2519 rc = ENOMEM; 2520 goto bnx_dma_alloc_exit; 2521 } 2522 2523 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2524 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2525 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2526 aprint_error_dev(sc->bnx_dev, 2527 "Could not allocate Rx desc %d DMA memory!\n", i); 2528 rc = ENOMEM; 2529 goto bnx_dma_alloc_exit; 2530 } 2531 2532 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2533 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2534 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2535 aprint_error_dev(sc->bnx_dev, 2536 "Could not map Rx desc %d DMA memory!\n", i); 2537 rc = ENOMEM; 2538 goto bnx_dma_alloc_exit; 2539 } 2540 2541 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2542 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2543 BUS_DMA_NOWAIT)) { 2544 aprint_error_dev(sc->bnx_dev, 2545 "Could not load Rx desc %d DMA memory!\n", i); 2546 rc = ENOMEM; 2547 goto bnx_dma_alloc_exit; 2548 } 2549 2550 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2551 sc->rx_bd_chain_paddr[i] = 2552 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2553 2554 /* DRC - Fix for 64 bit systems. */ 2555 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2556 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2557 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2558 0, BNX_RX_CHAIN_PAGE_SZ, 2559 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2560 } 2561 2562 /* 2563 * Create DMA maps for the Rx buffer mbufs. 2564 */ 2565 for (i = 0; i < TOTAL_RX_BD; i++) { 2566 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2567 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2568 &sc->rx_mbuf_map[i])) { 2569 aprint_error_dev(sc->bnx_dev, 2570 "Could not create Rx mbuf %d DMA map!\n", i); 2571 rc = ENOMEM; 2572 goto bnx_dma_alloc_exit; 2573 } 2574 } 2575 2576 bnx_dma_alloc_exit: 2577 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2578 2579 return rc; 2580 } 2581 2582 /****************************************************************************/ 2583 /* Release all resources used by the driver. */ 2584 /* */ 2585 /* Releases all resources acquired by the driver including interrupts, */ 2586 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2587 /* */ 2588 /* Returns: */ 2589 /* Nothing. */ 2590 /****************************************************************************/ 2591 void 2592 bnx_release_resources(struct bnx_softc *sc) 2593 { 2594 struct pci_attach_args *pa = &(sc->bnx_pa); 2595 2596 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2597 2598 bnx_dma_free(sc); 2599 2600 if (sc->bnx_intrhand != NULL) 2601 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2602 2603 if (sc->bnx_size) 2604 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2605 2606 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2607 } 2608 2609 /****************************************************************************/ 2610 /* Firmware synchronization. */ 2611 /* */ 2612 /* Before performing certain events such as a chip reset, synchronize with */ 2613 /* the firmware first. */ 2614 /* */ 2615 /* Returns: */ 2616 /* 0 for success, positive value for failure. */ 2617 /****************************************************************************/ 2618 int 2619 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2620 { 2621 int i, rc = 0; 2622 uint32_t val; 2623 2624 /* Don't waste any time if we've timed out before. */ 2625 if (sc->bnx_fw_timed_out) { 2626 rc = EBUSY; 2627 goto bnx_fw_sync_exit; 2628 } 2629 2630 /* Increment the message sequence number. */ 2631 sc->bnx_fw_wr_seq++; 2632 msg_data |= sc->bnx_fw_wr_seq; 2633 2634 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2635 msg_data); 2636 2637 /* Send the message to the bootcode driver mailbox. */ 2638 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2639 2640 /* Wait for the bootcode to acknowledge the message. */ 2641 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2642 /* Check for a response in the bootcode firmware mailbox. */ 2643 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2644 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2645 break; 2646 DELAY(1000); 2647 } 2648 2649 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2650 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2651 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2652 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2653 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2654 2655 msg_data &= ~BNX_DRV_MSG_CODE; 2656 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2657 2658 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2659 2660 sc->bnx_fw_timed_out = 1; 2661 rc = EBUSY; 2662 } 2663 2664 bnx_fw_sync_exit: 2665 return rc; 2666 } 2667 2668 /****************************************************************************/ 2669 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2670 /* */ 2671 /* Returns: */ 2672 /* Nothing. */ 2673 /****************************************************************************/ 2674 void 2675 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2676 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2677 { 2678 int i; 2679 uint32_t val; 2680 2681 /* Set the page size used by RV2P. */ 2682 if (rv2p_proc == RV2P_PROC2) { 2683 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2684 USABLE_RX_BD_PER_PAGE); 2685 } 2686 2687 for (i = 0; i < rv2p_code_len; i += 8) { 2688 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2689 rv2p_code++; 2690 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2691 rv2p_code++; 2692 2693 if (rv2p_proc == RV2P_PROC1) { 2694 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2695 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2696 } else { 2697 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2698 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2699 } 2700 } 2701 2702 /* Reset the processor, un-stall is done later. */ 2703 if (rv2p_proc == RV2P_PROC1) 2704 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2705 else 2706 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2707 } 2708 2709 /****************************************************************************/ 2710 /* Load RISC processor firmware. */ 2711 /* */ 2712 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2713 /* associated with a particular processor. */ 2714 /* */ 2715 /* Returns: */ 2716 /* Nothing. */ 2717 /****************************************************************************/ 2718 void 2719 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2720 struct fw_info *fw) 2721 { 2722 uint32_t offset; 2723 uint32_t val; 2724 2725 /* Halt the CPU. */ 2726 val = REG_RD_IND(sc, cpu_reg->mode); 2727 val |= cpu_reg->mode_value_halt; 2728 REG_WR_IND(sc, cpu_reg->mode, val); 2729 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2730 2731 /* Load the Text area. */ 2732 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2733 if (fw->text) { 2734 int j; 2735 2736 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2737 REG_WR_IND(sc, offset, fw->text[j]); 2738 } 2739 2740 /* Load the Data area. */ 2741 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2742 if (fw->data) { 2743 int j; 2744 2745 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2746 REG_WR_IND(sc, offset, fw->data[j]); 2747 } 2748 2749 /* Load the SBSS area. */ 2750 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2751 if (fw->sbss) { 2752 int j; 2753 2754 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2755 REG_WR_IND(sc, offset, fw->sbss[j]); 2756 } 2757 2758 /* Load the BSS area. */ 2759 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2760 if (fw->bss) { 2761 int j; 2762 2763 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2764 REG_WR_IND(sc, offset, fw->bss[j]); 2765 } 2766 2767 /* Load the Read-Only area. */ 2768 offset = cpu_reg->spad_base + 2769 (fw->rodata_addr - cpu_reg->mips_view_base); 2770 if (fw->rodata) { 2771 int j; 2772 2773 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2774 REG_WR_IND(sc, offset, fw->rodata[j]); 2775 } 2776 2777 /* Clear the pre-fetch instruction. */ 2778 REG_WR_IND(sc, cpu_reg->inst, 0); 2779 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2780 2781 /* Start the CPU. */ 2782 val = REG_RD_IND(sc, cpu_reg->mode); 2783 val &= ~cpu_reg->mode_value_halt; 2784 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2785 REG_WR_IND(sc, cpu_reg->mode, val); 2786 } 2787 2788 /****************************************************************************/ 2789 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2790 /* */ 2791 /* Loads the firmware for each CPU and starts the CPU. */ 2792 /* */ 2793 /* Returns: */ 2794 /* Nothing. */ 2795 /****************************************************************************/ 2796 void 2797 bnx_init_cpus(struct bnx_softc *sc) 2798 { 2799 struct cpu_reg cpu_reg; 2800 struct fw_info fw; 2801 2802 switch(BNX_CHIP_NUM(sc)) { 2803 case BNX_CHIP_NUM_5709: 2804 /* Initialize the RV2P processor. */ 2805 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2806 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2807 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2808 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2809 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2810 } else { 2811 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2812 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2813 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2814 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2815 } 2816 2817 /* Initialize the RX Processor. */ 2818 cpu_reg.mode = BNX_RXP_CPU_MODE; 2819 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2820 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2821 cpu_reg.state = BNX_RXP_CPU_STATE; 2822 cpu_reg.state_value_clear = 0xffffff; 2823 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2824 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2825 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2826 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2827 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2828 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2829 cpu_reg.mips_view_base = 0x8000000; 2830 2831 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2832 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2833 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2834 fw.start_addr = bnx_RXP_b09FwStartAddr; 2835 2836 fw.text_addr = bnx_RXP_b09FwTextAddr; 2837 fw.text_len = bnx_RXP_b09FwTextLen; 2838 fw.text_index = 0; 2839 fw.text = bnx_RXP_b09FwText; 2840 2841 fw.data_addr = bnx_RXP_b09FwDataAddr; 2842 fw.data_len = bnx_RXP_b09FwDataLen; 2843 fw.data_index = 0; 2844 fw.data = bnx_RXP_b09FwData; 2845 2846 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2847 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2848 fw.sbss_index = 0; 2849 fw.sbss = bnx_RXP_b09FwSbss; 2850 2851 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2852 fw.bss_len = bnx_RXP_b09FwBssLen; 2853 fw.bss_index = 0; 2854 fw.bss = bnx_RXP_b09FwBss; 2855 2856 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2857 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2858 fw.rodata_index = 0; 2859 fw.rodata = bnx_RXP_b09FwRodata; 2860 2861 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2862 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2863 2864 /* Initialize the TX Processor. */ 2865 cpu_reg.mode = BNX_TXP_CPU_MODE; 2866 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2867 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2868 cpu_reg.state = BNX_TXP_CPU_STATE; 2869 cpu_reg.state_value_clear = 0xffffff; 2870 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2871 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2872 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2873 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2874 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2875 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2876 cpu_reg.mips_view_base = 0x8000000; 2877 2878 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2879 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2880 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2881 fw.start_addr = bnx_TXP_b09FwStartAddr; 2882 2883 fw.text_addr = bnx_TXP_b09FwTextAddr; 2884 fw.text_len = bnx_TXP_b09FwTextLen; 2885 fw.text_index = 0; 2886 fw.text = bnx_TXP_b09FwText; 2887 2888 fw.data_addr = bnx_TXP_b09FwDataAddr; 2889 fw.data_len = bnx_TXP_b09FwDataLen; 2890 fw.data_index = 0; 2891 fw.data = bnx_TXP_b09FwData; 2892 2893 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2894 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2895 fw.sbss_index = 0; 2896 fw.sbss = bnx_TXP_b09FwSbss; 2897 2898 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2899 fw.bss_len = bnx_TXP_b09FwBssLen; 2900 fw.bss_index = 0; 2901 fw.bss = bnx_TXP_b09FwBss; 2902 2903 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2904 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2905 fw.rodata_index = 0; 2906 fw.rodata = bnx_TXP_b09FwRodata; 2907 2908 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2909 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2910 2911 /* Initialize the TX Patch-up Processor. */ 2912 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2913 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2914 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2915 cpu_reg.state = BNX_TPAT_CPU_STATE; 2916 cpu_reg.state_value_clear = 0xffffff; 2917 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2918 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2919 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2920 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2921 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2922 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2923 cpu_reg.mips_view_base = 0x8000000; 2924 2925 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2926 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2927 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2928 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2929 2930 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2931 fw.text_len = bnx_TPAT_b09FwTextLen; 2932 fw.text_index = 0; 2933 fw.text = bnx_TPAT_b09FwText; 2934 2935 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2936 fw.data_len = bnx_TPAT_b09FwDataLen; 2937 fw.data_index = 0; 2938 fw.data = bnx_TPAT_b09FwData; 2939 2940 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2941 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2942 fw.sbss_index = 0; 2943 fw.sbss = bnx_TPAT_b09FwSbss; 2944 2945 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2946 fw.bss_len = bnx_TPAT_b09FwBssLen; 2947 fw.bss_index = 0; 2948 fw.bss = bnx_TPAT_b09FwBss; 2949 2950 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2951 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2952 fw.rodata_index = 0; 2953 fw.rodata = bnx_TPAT_b09FwRodata; 2954 2955 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2956 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2957 2958 /* Initialize the Completion Processor. */ 2959 cpu_reg.mode = BNX_COM_CPU_MODE; 2960 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 2961 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 2962 cpu_reg.state = BNX_COM_CPU_STATE; 2963 cpu_reg.state_value_clear = 0xffffff; 2964 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 2965 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 2966 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 2967 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 2968 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 2969 cpu_reg.spad_base = BNX_COM_SCRATCH; 2970 cpu_reg.mips_view_base = 0x8000000; 2971 2972 fw.ver_major = bnx_COM_b09FwReleaseMajor; 2973 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 2974 fw.ver_fix = bnx_COM_b09FwReleaseFix; 2975 fw.start_addr = bnx_COM_b09FwStartAddr; 2976 2977 fw.text_addr = bnx_COM_b09FwTextAddr; 2978 fw.text_len = bnx_COM_b09FwTextLen; 2979 fw.text_index = 0; 2980 fw.text = bnx_COM_b09FwText; 2981 2982 fw.data_addr = bnx_COM_b09FwDataAddr; 2983 fw.data_len = bnx_COM_b09FwDataLen; 2984 fw.data_index = 0; 2985 fw.data = bnx_COM_b09FwData; 2986 2987 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 2988 fw.sbss_len = bnx_COM_b09FwSbssLen; 2989 fw.sbss_index = 0; 2990 fw.sbss = bnx_COM_b09FwSbss; 2991 2992 fw.bss_addr = bnx_COM_b09FwBssAddr; 2993 fw.bss_len = bnx_COM_b09FwBssLen; 2994 fw.bss_index = 0; 2995 fw.bss = bnx_COM_b09FwBss; 2996 2997 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 2998 fw.rodata_len = bnx_COM_b09FwRodataLen; 2999 fw.rodata_index = 0; 3000 fw.rodata = bnx_COM_b09FwRodata; 3001 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3002 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3003 break; 3004 default: 3005 /* Initialize the RV2P processor. */ 3006 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3007 RV2P_PROC1); 3008 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3009 RV2P_PROC2); 3010 3011 /* Initialize the RX Processor. */ 3012 cpu_reg.mode = BNX_RXP_CPU_MODE; 3013 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3014 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3015 cpu_reg.state = BNX_RXP_CPU_STATE; 3016 cpu_reg.state_value_clear = 0xffffff; 3017 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3018 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3019 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3020 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3021 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3022 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3023 cpu_reg.mips_view_base = 0x8000000; 3024 3025 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3026 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3027 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3028 fw.start_addr = bnx_RXP_b06FwStartAddr; 3029 3030 fw.text_addr = bnx_RXP_b06FwTextAddr; 3031 fw.text_len = bnx_RXP_b06FwTextLen; 3032 fw.text_index = 0; 3033 fw.text = bnx_RXP_b06FwText; 3034 3035 fw.data_addr = bnx_RXP_b06FwDataAddr; 3036 fw.data_len = bnx_RXP_b06FwDataLen; 3037 fw.data_index = 0; 3038 fw.data = bnx_RXP_b06FwData; 3039 3040 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3041 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3042 fw.sbss_index = 0; 3043 fw.sbss = bnx_RXP_b06FwSbss; 3044 3045 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3046 fw.bss_len = bnx_RXP_b06FwBssLen; 3047 fw.bss_index = 0; 3048 fw.bss = bnx_RXP_b06FwBss; 3049 3050 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3051 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3052 fw.rodata_index = 0; 3053 fw.rodata = bnx_RXP_b06FwRodata; 3054 3055 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3056 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3057 3058 /* Initialize the TX Processor. */ 3059 cpu_reg.mode = BNX_TXP_CPU_MODE; 3060 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3061 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3062 cpu_reg.state = BNX_TXP_CPU_STATE; 3063 cpu_reg.state_value_clear = 0xffffff; 3064 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3065 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3066 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3067 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3068 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3069 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3070 cpu_reg.mips_view_base = 0x8000000; 3071 3072 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3073 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3074 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3075 fw.start_addr = bnx_TXP_b06FwStartAddr; 3076 3077 fw.text_addr = bnx_TXP_b06FwTextAddr; 3078 fw.text_len = bnx_TXP_b06FwTextLen; 3079 fw.text_index = 0; 3080 fw.text = bnx_TXP_b06FwText; 3081 3082 fw.data_addr = bnx_TXP_b06FwDataAddr; 3083 fw.data_len = bnx_TXP_b06FwDataLen; 3084 fw.data_index = 0; 3085 fw.data = bnx_TXP_b06FwData; 3086 3087 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3088 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3089 fw.sbss_index = 0; 3090 fw.sbss = bnx_TXP_b06FwSbss; 3091 3092 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3093 fw.bss_len = bnx_TXP_b06FwBssLen; 3094 fw.bss_index = 0; 3095 fw.bss = bnx_TXP_b06FwBss; 3096 3097 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3098 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3099 fw.rodata_index = 0; 3100 fw.rodata = bnx_TXP_b06FwRodata; 3101 3102 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3103 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3104 3105 /* Initialize the TX Patch-up Processor. */ 3106 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3107 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3108 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3109 cpu_reg.state = BNX_TPAT_CPU_STATE; 3110 cpu_reg.state_value_clear = 0xffffff; 3111 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3112 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3113 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3114 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3115 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3116 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3117 cpu_reg.mips_view_base = 0x8000000; 3118 3119 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3120 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3121 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3122 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3123 3124 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3125 fw.text_len = bnx_TPAT_b06FwTextLen; 3126 fw.text_index = 0; 3127 fw.text = bnx_TPAT_b06FwText; 3128 3129 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3130 fw.data_len = bnx_TPAT_b06FwDataLen; 3131 fw.data_index = 0; 3132 fw.data = bnx_TPAT_b06FwData; 3133 3134 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3135 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3136 fw.sbss_index = 0; 3137 fw.sbss = bnx_TPAT_b06FwSbss; 3138 3139 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3140 fw.bss_len = bnx_TPAT_b06FwBssLen; 3141 fw.bss_index = 0; 3142 fw.bss = bnx_TPAT_b06FwBss; 3143 3144 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3145 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3146 fw.rodata_index = 0; 3147 fw.rodata = bnx_TPAT_b06FwRodata; 3148 3149 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3150 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3151 3152 /* Initialize the Completion Processor. */ 3153 cpu_reg.mode = BNX_COM_CPU_MODE; 3154 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3155 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3156 cpu_reg.state = BNX_COM_CPU_STATE; 3157 cpu_reg.state_value_clear = 0xffffff; 3158 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3159 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3160 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3161 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3162 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3163 cpu_reg.spad_base = BNX_COM_SCRATCH; 3164 cpu_reg.mips_view_base = 0x8000000; 3165 3166 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3167 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3168 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3169 fw.start_addr = bnx_COM_b06FwStartAddr; 3170 3171 fw.text_addr = bnx_COM_b06FwTextAddr; 3172 fw.text_len = bnx_COM_b06FwTextLen; 3173 fw.text_index = 0; 3174 fw.text = bnx_COM_b06FwText; 3175 3176 fw.data_addr = bnx_COM_b06FwDataAddr; 3177 fw.data_len = bnx_COM_b06FwDataLen; 3178 fw.data_index = 0; 3179 fw.data = bnx_COM_b06FwData; 3180 3181 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3182 fw.sbss_len = bnx_COM_b06FwSbssLen; 3183 fw.sbss_index = 0; 3184 fw.sbss = bnx_COM_b06FwSbss; 3185 3186 fw.bss_addr = bnx_COM_b06FwBssAddr; 3187 fw.bss_len = bnx_COM_b06FwBssLen; 3188 fw.bss_index = 0; 3189 fw.bss = bnx_COM_b06FwBss; 3190 3191 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3192 fw.rodata_len = bnx_COM_b06FwRodataLen; 3193 fw.rodata_index = 0; 3194 fw.rodata = bnx_COM_b06FwRodata; 3195 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3196 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3197 break; 3198 } 3199 } 3200 3201 /****************************************************************************/ 3202 /* Initialize context memory. */ 3203 /* */ 3204 /* Clears the memory associated with each Context ID (CID). */ 3205 /* */ 3206 /* Returns: */ 3207 /* Nothing. */ 3208 /****************************************************************************/ 3209 void 3210 bnx_init_context(struct bnx_softc *sc) 3211 { 3212 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3213 /* DRC: Replace this constant value with a #define. */ 3214 int i, retry_cnt = 10; 3215 uint32_t val; 3216 3217 /* 3218 * BCM5709 context memory may be cached 3219 * in host memory so prepare the host memory 3220 * for access. 3221 */ 3222 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3223 | (1 << 12); 3224 val |= (BCM_PAGE_BITS - 8) << 16; 3225 REG_WR(sc, BNX_CTX_COMMAND, val); 3226 3227 /* Wait for mem init command to complete. */ 3228 for (i = 0; i < retry_cnt; i++) { 3229 val = REG_RD(sc, BNX_CTX_COMMAND); 3230 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3231 break; 3232 DELAY(2); 3233 } 3234 3235 /* ToDo: Consider returning an error here. */ 3236 3237 for (i = 0; i < sc->ctx_pages; i++) { 3238 int j; 3239 3240 /* Set the physaddr of the context memory cache. */ 3241 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3242 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3243 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3244 val = (uint32_t) 3245 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3246 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3247 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3248 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3249 3250 /* Verify that the context memory write was successful. */ 3251 for (j = 0; j < retry_cnt; j++) { 3252 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3253 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3254 break; 3255 DELAY(5); 3256 } 3257 3258 /* ToDo: Consider returning an error here. */ 3259 } 3260 } else { 3261 uint32_t vcid_addr, offset; 3262 3263 /* 3264 * For the 5706/5708, context memory is local to the 3265 * controller, so initialize the controller context memory. 3266 */ 3267 3268 vcid_addr = GET_CID_ADDR(96); 3269 while (vcid_addr) { 3270 3271 vcid_addr -= BNX_PHY_CTX_SIZE; 3272 3273 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3274 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3275 3276 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3277 offset += 4) 3278 CTX_WR(sc, 0x00, offset, 0); 3279 3280 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3281 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3282 } 3283 } 3284 } 3285 3286 /****************************************************************************/ 3287 /* Fetch the permanent MAC address of the controller. */ 3288 /* */ 3289 /* Returns: */ 3290 /* Nothing. */ 3291 /****************************************************************************/ 3292 void 3293 bnx_get_mac_addr(struct bnx_softc *sc) 3294 { 3295 uint32_t mac_lo = 0, mac_hi = 0; 3296 3297 /* 3298 * The NetXtreme II bootcode populates various NIC 3299 * power-on and runtime configuration items in a 3300 * shared memory area. The factory configured MAC 3301 * address is available from both NVRAM and the 3302 * shared memory area so we'll read the value from 3303 * shared memory for speed. 3304 */ 3305 3306 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3307 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3308 3309 if ((mac_lo == 0) && (mac_hi == 0)) { 3310 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3311 __FILE__, __LINE__); 3312 } else { 3313 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3314 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3315 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3316 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3317 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3318 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3319 } 3320 3321 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3322 "%s\n", ether_sprintf(sc->eaddr)); 3323 } 3324 3325 /****************************************************************************/ 3326 /* Program the MAC address. */ 3327 /* */ 3328 /* Returns: */ 3329 /* Nothing. */ 3330 /****************************************************************************/ 3331 void 3332 bnx_set_mac_addr(struct bnx_softc *sc) 3333 { 3334 uint32_t val; 3335 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3336 3337 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3338 "%s\n", ether_sprintf(sc->eaddr)); 3339 3340 val = (mac_addr[0] << 8) | mac_addr[1]; 3341 3342 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3343 3344 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3345 (mac_addr[4] << 8) | mac_addr[5]; 3346 3347 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3348 } 3349 3350 /****************************************************************************/ 3351 /* Stop the controller. */ 3352 /* */ 3353 /* Returns: */ 3354 /* Nothing. */ 3355 /****************************************************************************/ 3356 void 3357 bnx_stop(struct ifnet *ifp, int disable) 3358 { 3359 struct bnx_softc *sc = ifp->if_softc; 3360 3361 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3362 3363 if (disable) { 3364 sc->bnx_detaching = 1; 3365 callout_halt(&sc->bnx_timeout, NULL); 3366 } else 3367 callout_stop(&sc->bnx_timeout); 3368 3369 mii_down(&sc->bnx_mii); 3370 3371 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3372 3373 /* Disable the transmit/receive blocks. */ 3374 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3375 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3376 DELAY(20); 3377 3378 bnx_disable_intr(sc); 3379 3380 /* Tell firmware that the driver is going away. */ 3381 if (disable) 3382 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3383 else 3384 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3385 3386 /* Free RX buffers. */ 3387 bnx_free_rx_chain(sc); 3388 3389 /* Free TX buffers. */ 3390 bnx_free_tx_chain(sc); 3391 3392 ifp->if_timer = 0; 3393 3394 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3395 3396 } 3397 3398 int 3399 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3400 { 3401 struct pci_attach_args *pa = &(sc->bnx_pa); 3402 uint32_t val; 3403 int i, rc = 0; 3404 3405 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3406 3407 /* Wait for pending PCI transactions to complete. */ 3408 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3409 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3410 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3411 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3412 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3413 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3414 DELAY(5); 3415 3416 /* Disable DMA */ 3417 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3418 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3419 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3420 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3421 } 3422 3423 /* Assume bootcode is running. */ 3424 sc->bnx_fw_timed_out = 0; 3425 3426 /* Give the firmware a chance to prepare for the reset. */ 3427 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3428 if (rc) 3429 goto bnx_reset_exit; 3430 3431 /* Set a firmware reminder that this is a soft reset. */ 3432 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3433 BNX_DRV_RESET_SIGNATURE_MAGIC); 3434 3435 /* Dummy read to force the chip to complete all current transactions. */ 3436 val = REG_RD(sc, BNX_MISC_ID); 3437 3438 /* Chip reset. */ 3439 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3440 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3441 REG_RD(sc, BNX_MISC_COMMAND); 3442 DELAY(5); 3443 3444 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3445 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3446 3447 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3448 val); 3449 } else { 3450 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3451 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3452 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3453 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3454 3455 /* Allow up to 30us for reset to complete. */ 3456 for (i = 0; i < 10; i++) { 3457 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3458 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3459 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3460 break; 3461 } 3462 DELAY(10); 3463 } 3464 3465 /* Check that reset completed successfully. */ 3466 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3467 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3468 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3469 __FILE__, __LINE__); 3470 rc = EBUSY; 3471 goto bnx_reset_exit; 3472 } 3473 } 3474 3475 /* Make sure byte swapping is properly configured. */ 3476 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3477 if (val != 0x01020304) { 3478 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3479 __FILE__, __LINE__); 3480 rc = ENODEV; 3481 goto bnx_reset_exit; 3482 } 3483 3484 /* Just completed a reset, assume that firmware is running again. */ 3485 sc->bnx_fw_timed_out = 0; 3486 3487 /* Wait for the firmware to finish its initialization. */ 3488 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3489 if (rc) 3490 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3491 "initialization!\n", __FILE__, __LINE__); 3492 3493 bnx_reset_exit: 3494 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3495 3496 return rc; 3497 } 3498 3499 int 3500 bnx_chipinit(struct bnx_softc *sc) 3501 { 3502 struct pci_attach_args *pa = &(sc->bnx_pa); 3503 uint32_t val; 3504 int rc = 0; 3505 3506 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3507 3508 /* Make sure the interrupt is not active. */ 3509 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3510 3511 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3512 /* channels and PCI clock compensation delay. */ 3513 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3514 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3515 #if BYTE_ORDER == BIG_ENDIAN 3516 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3517 #endif 3518 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3519 DMA_READ_CHANS << 12 | 3520 DMA_WRITE_CHANS << 16; 3521 3522 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3523 3524 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3525 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3526 3527 /* 3528 * This setting resolves a problem observed on certain Intel PCI 3529 * chipsets that cannot handle multiple outstanding DMA operations. 3530 * See errata E9_5706A1_65. 3531 */ 3532 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3533 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3534 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3535 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3536 3537 REG_WR(sc, BNX_DMA_CONFIG, val); 3538 3539 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3540 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3541 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3542 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3543 val & ~0x20000); 3544 } 3545 3546 /* Enable the RX_V2P and Context state machines before access. */ 3547 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3548 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3549 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3550 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3551 3552 /* Initialize context mapping and zero out the quick contexts. */ 3553 bnx_init_context(sc); 3554 3555 /* Initialize the on-boards CPUs */ 3556 bnx_init_cpus(sc); 3557 3558 /* Prepare NVRAM for access. */ 3559 if (bnx_init_nvram(sc)) { 3560 rc = ENODEV; 3561 goto bnx_chipinit_exit; 3562 } 3563 3564 /* Set the kernel bypass block size */ 3565 val = REG_RD(sc, BNX_MQ_CONFIG); 3566 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3567 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3568 3569 /* Enable bins used on the 5709. */ 3570 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3571 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3572 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3573 val |= BNX_MQ_CONFIG_HALT_DIS; 3574 } 3575 3576 REG_WR(sc, BNX_MQ_CONFIG, val); 3577 3578 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3579 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3580 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3581 3582 val = (BCM_PAGE_BITS - 8) << 24; 3583 REG_WR(sc, BNX_RV2P_CONFIG, val); 3584 3585 /* Configure page size. */ 3586 val = REG_RD(sc, BNX_TBDR_CONFIG); 3587 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3588 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3589 REG_WR(sc, BNX_TBDR_CONFIG, val); 3590 3591 #if 0 3592 /* Set the perfect match control register to default. */ 3593 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3594 #endif 3595 3596 bnx_chipinit_exit: 3597 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3598 3599 return rc; 3600 } 3601 3602 /****************************************************************************/ 3603 /* Initialize the controller in preparation to send/receive traffic. */ 3604 /* */ 3605 /* Returns: */ 3606 /* 0 for success, positive value for failure. */ 3607 /****************************************************************************/ 3608 int 3609 bnx_blockinit(struct bnx_softc *sc) 3610 { 3611 uint32_t reg, val; 3612 int rc = 0; 3613 3614 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3615 3616 /* Load the hardware default MAC address. */ 3617 bnx_set_mac_addr(sc); 3618 3619 /* Set the Ethernet backoff seed value */ 3620 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3621 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3622 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3623 3624 sc->last_status_idx = 0; 3625 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3626 3627 /* Set up link change interrupt generation. */ 3628 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3629 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3630 3631 /* Program the physical address of the status block. */ 3632 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3633 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3634 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3635 3636 /* Program the physical address of the statistics block. */ 3637 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3638 (uint32_t)(sc->stats_block_paddr)); 3639 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3640 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3641 3642 /* Program various host coalescing parameters. */ 3643 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3644 << 16) | sc->bnx_tx_quick_cons_trip); 3645 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3646 << 16) | sc->bnx_rx_quick_cons_trip); 3647 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3648 sc->bnx_comp_prod_trip); 3649 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3650 sc->bnx_tx_ticks); 3651 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3652 sc->bnx_rx_ticks); 3653 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3654 sc->bnx_com_ticks); 3655 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3656 sc->bnx_cmd_ticks); 3657 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3658 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3659 REG_WR(sc, BNX_HC_CONFIG, 3660 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3661 BNX_HC_CONFIG_COLLECT_STATS)); 3662 3663 /* Clear the internal statistics counters. */ 3664 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3665 3666 /* Verify that bootcode is running. */ 3667 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3668 3669 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3670 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3671 __FILE__, __LINE__); reg = 0); 3672 3673 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3674 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3675 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3676 "Expected: 08%08X\n", __FILE__, __LINE__, 3677 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3678 BNX_DEV_INFO_SIGNATURE_MAGIC); 3679 rc = ENODEV; 3680 goto bnx_blockinit_exit; 3681 } 3682 3683 /* Check if any management firmware is running. */ 3684 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3685 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3686 BNX_PORT_FEATURE_IMD_ENABLED)) { 3687 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3688 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3689 } 3690 3691 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3692 BNX_DEV_INFO_BC_REV); 3693 3694 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3695 3696 /* Enable DMA */ 3697 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3698 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3699 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3700 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3701 } 3702 3703 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3704 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3705 3706 /* Enable link state change interrupt generation. */ 3707 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3708 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3709 BNX_MISC_ENABLE_DEFAULT_XI); 3710 } else 3711 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3712 3713 /* Enable all remaining blocks in the MAC. */ 3714 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3715 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3716 DELAY(20); 3717 3718 bnx_blockinit_exit: 3719 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3720 3721 return rc; 3722 } 3723 3724 static int 3725 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3726 uint16_t *chain_prod, uint32_t *prod_bseq) 3727 { 3728 bus_dmamap_t map; 3729 struct rx_bd *rxbd; 3730 uint32_t addr; 3731 int i; 3732 #ifdef BNX_DEBUG 3733 uint16_t debug_chain_prod = *chain_prod; 3734 #endif 3735 uint16_t first_chain_prod; 3736 3737 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3738 3739 /* Map the mbuf cluster into device memory. */ 3740 map = sc->rx_mbuf_map[*chain_prod]; 3741 first_chain_prod = *chain_prod; 3742 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3743 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3744 __FILE__, __LINE__); 3745 3746 m_freem(m_new); 3747 3748 DBRUNIF(1, sc->rx_mbuf_alloc--); 3749 3750 return ENOBUFS; 3751 } 3752 /* Make sure there is room in the receive chain. */ 3753 if (map->dm_nsegs > sc->free_rx_bd) { 3754 bus_dmamap_unload(sc->bnx_dmatag, map); 3755 m_freem(m_new); 3756 return EFBIG; 3757 } 3758 #ifdef BNX_DEBUG 3759 /* Track the distribution of buffer segments. */ 3760 sc->rx_mbuf_segs[map->dm_nsegs]++; 3761 #endif 3762 3763 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3764 BUS_DMASYNC_PREREAD); 3765 3766 /* Update some debug statistics counters */ 3767 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3768 sc->rx_low_watermark = sc->free_rx_bd); 3769 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3770 3771 /* 3772 * Setup the rx_bd for the first segment 3773 */ 3774 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3775 3776 addr = (uint32_t)map->dm_segs[0].ds_addr; 3777 rxbd->rx_bd_haddr_lo = addr; 3778 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3779 rxbd->rx_bd_haddr_hi = addr; 3780 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3781 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3782 *prod_bseq += map->dm_segs[0].ds_len; 3783 bus_dmamap_sync(sc->bnx_dmatag, 3784 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3785 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3786 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3787 3788 for (i = 1; i < map->dm_nsegs; i++) { 3789 *prod = NEXT_RX_BD(*prod); 3790 *chain_prod = RX_CHAIN_IDX(*prod); 3791 3792 rxbd = 3793 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3794 3795 addr = (uint32_t)map->dm_segs[i].ds_addr; 3796 rxbd->rx_bd_haddr_lo = addr; 3797 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3798 rxbd->rx_bd_haddr_hi = addr; 3799 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3800 rxbd->rx_bd_flags = 0; 3801 *prod_bseq += map->dm_segs[i].ds_len; 3802 bus_dmamap_sync(sc->bnx_dmatag, 3803 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3804 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3805 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3806 } 3807 3808 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3809 bus_dmamap_sync(sc->bnx_dmatag, 3810 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3811 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3812 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3813 3814 /* 3815 * Save the mbuf, adjust the map pointer (swap map for first and 3816 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3817 * and update our counter. 3818 */ 3819 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3820 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3821 sc->rx_mbuf_map[*chain_prod] = map; 3822 sc->free_rx_bd -= map->dm_nsegs; 3823 3824 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3825 map->dm_nsegs)); 3826 *prod = NEXT_RX_BD(*prod); 3827 *chain_prod = RX_CHAIN_IDX(*prod); 3828 3829 return 0; 3830 } 3831 3832 /****************************************************************************/ 3833 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3834 /* */ 3835 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3836 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3837 /* necessary. */ 3838 /* */ 3839 /* Returns: */ 3840 /* 0 for success, positive value for failure. */ 3841 /****************************************************************************/ 3842 int 3843 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3844 uint16_t *chain_prod, uint32_t *prod_bseq) 3845 { 3846 struct mbuf *m_new = NULL; 3847 int rc = 0; 3848 uint16_t min_free_bd; 3849 3850 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3851 __func__); 3852 3853 /* Make sure the inputs are valid. */ 3854 DBRUNIF((*chain_prod > MAX_RX_BD), 3855 aprint_error_dev(sc->bnx_dev, 3856 "RX producer out of range: 0x%04X > 0x%04X\n", 3857 *chain_prod, (uint16_t)MAX_RX_BD)); 3858 3859 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3860 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3861 *prod_bseq); 3862 3863 /* try to get in as many mbufs as possible */ 3864 if (sc->mbuf_alloc_size == MCLBYTES) 3865 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3866 else 3867 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3868 while (sc->free_rx_bd >= min_free_bd) { 3869 /* Simulate an mbuf allocation failure. */ 3870 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3871 aprint_error_dev(sc->bnx_dev, 3872 "Simulating mbuf allocation failure.\n"); 3873 sc->mbuf_sim_alloc_failed++; 3874 rc = ENOBUFS; 3875 goto bnx_get_buf_exit); 3876 3877 /* This is a new mbuf allocation. */ 3878 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3879 if (m_new == NULL) { 3880 DBPRINT(sc, BNX_WARN, 3881 "%s(%d): RX mbuf header allocation failed!\n", 3882 __FILE__, __LINE__); 3883 3884 sc->mbuf_alloc_failed++; 3885 3886 rc = ENOBUFS; 3887 goto bnx_get_buf_exit; 3888 } 3889 3890 DBRUNIF(1, sc->rx_mbuf_alloc++); 3891 3892 /* Simulate an mbuf cluster allocation failure. */ 3893 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3894 m_freem(m_new); 3895 sc->rx_mbuf_alloc--; 3896 sc->mbuf_alloc_failed++; 3897 sc->mbuf_sim_alloc_failed++; 3898 rc = ENOBUFS; 3899 goto bnx_get_buf_exit); 3900 3901 if (sc->mbuf_alloc_size == MCLBYTES) 3902 MCLGET(m_new, M_DONTWAIT); 3903 else 3904 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3905 M_DONTWAIT); 3906 if (!(m_new->m_flags & M_EXT)) { 3907 DBPRINT(sc, BNX_WARN, 3908 "%s(%d): RX mbuf chain allocation failed!\n", 3909 __FILE__, __LINE__); 3910 3911 m_freem(m_new); 3912 3913 DBRUNIF(1, sc->rx_mbuf_alloc--); 3914 sc->mbuf_alloc_failed++; 3915 3916 rc = ENOBUFS; 3917 goto bnx_get_buf_exit; 3918 } 3919 3920 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3921 if (rc != 0) 3922 goto bnx_get_buf_exit; 3923 } 3924 3925 bnx_get_buf_exit: 3926 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3927 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3928 *chain_prod, *prod_bseq); 3929 3930 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3931 __func__); 3932 3933 return rc; 3934 } 3935 3936 void 3937 bnx_alloc_pkts(struct work * unused, void * arg) 3938 { 3939 struct bnx_softc *sc = arg; 3940 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3941 struct bnx_pkt *pkt; 3942 int i, s; 3943 3944 for (i = 0; i < 4; i++) { /* magic! */ 3945 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 3946 if (pkt == NULL) 3947 break; 3948 3949 if (bus_dmamap_create(sc->bnx_dmatag, 3950 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3951 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3952 &pkt->pkt_dmamap) != 0) 3953 goto put; 3954 3955 if (!ISSET(ifp->if_flags, IFF_UP)) 3956 goto stopping; 3957 3958 mutex_enter(&sc->tx_pkt_mtx); 3959 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 3960 sc->tx_pkt_count++; 3961 mutex_exit(&sc->tx_pkt_mtx); 3962 } 3963 3964 mutex_enter(&sc->tx_pkt_mtx); 3965 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 3966 mutex_exit(&sc->tx_pkt_mtx); 3967 3968 /* fire-up TX now that allocations have been done */ 3969 s = splnet(); 3970 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3971 bnx_start(ifp); 3972 splx(s); 3973 3974 return; 3975 3976 stopping: 3977 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 3978 put: 3979 pool_put(bnx_tx_pool, pkt); 3980 return; 3981 } 3982 3983 /****************************************************************************/ 3984 /* Initialize the TX context memory. */ 3985 /* */ 3986 /* Returns: */ 3987 /* Nothing */ 3988 /****************************************************************************/ 3989 void 3990 bnx_init_tx_context(struct bnx_softc *sc) 3991 { 3992 uint32_t val; 3993 3994 /* Initialize the context ID for an L2 TX chain. */ 3995 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3996 /* Set the CID type to support an L2 connection. */ 3997 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 3998 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 3999 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4000 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4001 4002 /* Point the hardware to the first page in the chain. */ 4003 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4004 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4005 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4006 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4007 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4008 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4009 } else { 4010 /* Set the CID type to support an L2 connection. */ 4011 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4012 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4013 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4014 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4015 4016 /* Point the hardware to the first page in the chain. */ 4017 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4018 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4019 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4020 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4021 } 4022 } 4023 4024 4025 /****************************************************************************/ 4026 /* Allocate memory and initialize the TX data structures. */ 4027 /* */ 4028 /* Returns: */ 4029 /* 0 for success, positive value for failure. */ 4030 /****************************************************************************/ 4031 int 4032 bnx_init_tx_chain(struct bnx_softc *sc) 4033 { 4034 struct tx_bd *txbd; 4035 uint32_t addr; 4036 int i, rc = 0; 4037 4038 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4039 4040 /* Force an allocation of some dmamaps for tx up front */ 4041 bnx_alloc_pkts(NULL, sc); 4042 4043 /* Set the initial TX producer/consumer indices. */ 4044 sc->tx_prod = 0; 4045 sc->tx_cons = 0; 4046 sc->tx_prod_bseq = 0; 4047 sc->used_tx_bd = 0; 4048 sc->max_tx_bd = USABLE_TX_BD; 4049 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4050 DBRUNIF(1, sc->tx_full_count = 0); 4051 4052 /* 4053 * The NetXtreme II supports a linked-list structure called 4054 * a Buffer Descriptor Chain (or BD chain). A BD chain 4055 * consists of a series of 1 or more chain pages, each of which 4056 * consists of a fixed number of BD entries. 4057 * The last BD entry on each page is a pointer to the next page 4058 * in the chain, and the last pointer in the BD chain 4059 * points back to the beginning of the chain. 4060 */ 4061 4062 /* Set the TX next pointer chain entries. */ 4063 for (i = 0; i < TX_PAGES; i++) { 4064 int j; 4065 4066 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4067 4068 /* Check if we've reached the last page. */ 4069 if (i == (TX_PAGES - 1)) 4070 j = 0; 4071 else 4072 j = i + 1; 4073 4074 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4075 txbd->tx_bd_haddr_lo = addr; 4076 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4077 txbd->tx_bd_haddr_hi = addr; 4078 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4079 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4080 } 4081 4082 /* 4083 * Initialize the context ID for an L2 TX chain. 4084 */ 4085 bnx_init_tx_context(sc); 4086 4087 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4088 4089 return rc; 4090 } 4091 4092 /****************************************************************************/ 4093 /* Free memory and clear the TX data structures. */ 4094 /* */ 4095 /* Returns: */ 4096 /* Nothing. */ 4097 /****************************************************************************/ 4098 void 4099 bnx_free_tx_chain(struct bnx_softc *sc) 4100 { 4101 struct bnx_pkt *pkt; 4102 int i; 4103 4104 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4105 4106 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4107 mutex_enter(&sc->tx_pkt_mtx); 4108 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4109 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4110 mutex_exit(&sc->tx_pkt_mtx); 4111 4112 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4113 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4114 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4115 4116 m_freem(pkt->pkt_mbuf); 4117 DBRUNIF(1, sc->tx_mbuf_alloc--); 4118 4119 mutex_enter(&sc->tx_pkt_mtx); 4120 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4121 } 4122 4123 /* Destroy all the dmamaps we allocated for TX */ 4124 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4125 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4126 sc->tx_pkt_count--; 4127 mutex_exit(&sc->tx_pkt_mtx); 4128 4129 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4130 pool_put(bnx_tx_pool, pkt); 4131 4132 mutex_enter(&sc->tx_pkt_mtx); 4133 } 4134 mutex_exit(&sc->tx_pkt_mtx); 4135 4136 4137 4138 /* Clear each TX chain page. */ 4139 for (i = 0; i < TX_PAGES; i++) { 4140 memset((char *)sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4141 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4142 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4143 } 4144 4145 sc->used_tx_bd = 0; 4146 4147 /* Check if we lost any mbufs in the process. */ 4148 DBRUNIF((sc->tx_mbuf_alloc), 4149 aprint_error_dev(sc->bnx_dev, 4150 "Memory leak! Lost %d mbufs from tx chain!\n", 4151 sc->tx_mbuf_alloc)); 4152 4153 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4154 } 4155 4156 /****************************************************************************/ 4157 /* Initialize the RX context memory. */ 4158 /* */ 4159 /* Returns: */ 4160 /* Nothing */ 4161 /****************************************************************************/ 4162 void 4163 bnx_init_rx_context(struct bnx_softc *sc) 4164 { 4165 uint32_t val; 4166 4167 /* Initialize the context ID for an L2 RX chain. */ 4168 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4169 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4170 4171 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4172 uint32_t lo_water, hi_water; 4173 4174 lo_water = BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT; 4175 hi_water = USABLE_RX_BD / 4; 4176 4177 lo_water /= BNX_L2CTX_RX_LO_WATER_MARK_SCALE; 4178 hi_water /= BNX_L2CTX_RX_HI_WATER_MARK_SCALE; 4179 4180 if (hi_water > 0xf) 4181 hi_water = 0xf; 4182 else if (hi_water == 0) 4183 lo_water = 0; 4184 val |= lo_water | 4185 (hi_water << BNX_L2CTX_RX_HI_WATER_MARK_SHIFT); 4186 } 4187 4188 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4189 4190 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4191 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4192 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4193 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4194 } 4195 4196 /* Point the hardware to the first page in the chain. */ 4197 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4198 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4199 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4200 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4201 } 4202 4203 /****************************************************************************/ 4204 /* Allocate memory and initialize the RX data structures. */ 4205 /* */ 4206 /* Returns: */ 4207 /* 0 for success, positive value for failure. */ 4208 /****************************************************************************/ 4209 int 4210 bnx_init_rx_chain(struct bnx_softc *sc) 4211 { 4212 struct rx_bd *rxbd; 4213 int i, rc = 0; 4214 uint16_t prod, chain_prod; 4215 uint32_t prod_bseq, addr; 4216 4217 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4218 4219 /* Initialize the RX producer and consumer indices. */ 4220 sc->rx_prod = 0; 4221 sc->rx_cons = 0; 4222 sc->rx_prod_bseq = 0; 4223 sc->free_rx_bd = USABLE_RX_BD; 4224 sc->max_rx_bd = USABLE_RX_BD; 4225 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4226 DBRUNIF(1, sc->rx_empty_count = 0); 4227 4228 /* Initialize the RX next pointer chain entries. */ 4229 for (i = 0; i < RX_PAGES; i++) { 4230 int j; 4231 4232 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4233 4234 /* Check if we've reached the last page. */ 4235 if (i == (RX_PAGES - 1)) 4236 j = 0; 4237 else 4238 j = i + 1; 4239 4240 /* Setup the chain page pointers. */ 4241 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4242 rxbd->rx_bd_haddr_hi = addr; 4243 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4244 rxbd->rx_bd_haddr_lo = addr; 4245 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4246 0, BNX_RX_CHAIN_PAGE_SZ, 4247 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4248 } 4249 4250 /* Allocate mbuf clusters for the rx_bd chain. */ 4251 prod = prod_bseq = 0; 4252 chain_prod = RX_CHAIN_IDX(prod); 4253 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4254 BNX_PRINTF(sc, 4255 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4256 } 4257 4258 /* Save the RX chain producer index. */ 4259 sc->rx_prod = prod; 4260 sc->rx_prod_bseq = prod_bseq; 4261 4262 for (i = 0; i < RX_PAGES; i++) 4263 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4264 sc->rx_bd_chain_map[i]->dm_mapsize, 4265 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4266 4267 /* Tell the chip about the waiting rx_bd's. */ 4268 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4269 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4270 4271 bnx_init_rx_context(sc); 4272 4273 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4274 4275 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4276 4277 return rc; 4278 } 4279 4280 /****************************************************************************/ 4281 /* Free memory and clear the RX data structures. */ 4282 /* */ 4283 /* Returns: */ 4284 /* Nothing. */ 4285 /****************************************************************************/ 4286 void 4287 bnx_free_rx_chain(struct bnx_softc *sc) 4288 { 4289 int i; 4290 4291 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4292 4293 /* Free any mbufs still in the RX mbuf chain. */ 4294 for (i = 0; i < TOTAL_RX_BD; i++) { 4295 if (sc->rx_mbuf_ptr[i] != NULL) { 4296 if (sc->rx_mbuf_map[i] != NULL) { 4297 bus_dmamap_sync(sc->bnx_dmatag, 4298 sc->rx_mbuf_map[i], 0, 4299 sc->rx_mbuf_map[i]->dm_mapsize, 4300 BUS_DMASYNC_POSTREAD); 4301 bus_dmamap_unload(sc->bnx_dmatag, 4302 sc->rx_mbuf_map[i]); 4303 } 4304 m_freem(sc->rx_mbuf_ptr[i]); 4305 sc->rx_mbuf_ptr[i] = NULL; 4306 DBRUNIF(1, sc->rx_mbuf_alloc--); 4307 } 4308 } 4309 4310 /* Clear each RX chain page. */ 4311 for (i = 0; i < RX_PAGES; i++) 4312 memset((char *)sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4313 4314 sc->free_rx_bd = sc->max_rx_bd; 4315 4316 /* Check if we lost any mbufs in the process. */ 4317 DBRUNIF((sc->rx_mbuf_alloc), 4318 aprint_error_dev(sc->bnx_dev, 4319 "Memory leak! Lost %d mbufs from rx chain!\n", 4320 sc->rx_mbuf_alloc)); 4321 4322 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4323 } 4324 4325 /****************************************************************************/ 4326 /* Handles PHY generated interrupt events. */ 4327 /* */ 4328 /* Returns: */ 4329 /* Nothing. */ 4330 /****************************************************************************/ 4331 void 4332 bnx_phy_intr(struct bnx_softc *sc) 4333 { 4334 uint32_t new_link_state, old_link_state; 4335 4336 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4337 BUS_DMASYNC_POSTREAD); 4338 new_link_state = sc->status_block->status_attn_bits & 4339 STATUS_ATTN_BITS_LINK_STATE; 4340 old_link_state = sc->status_block->status_attn_bits_ack & 4341 STATUS_ATTN_BITS_LINK_STATE; 4342 4343 /* Handle any changes if the link state has changed. */ 4344 if (new_link_state != old_link_state) { 4345 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4346 4347 callout_stop(&sc->bnx_timeout); 4348 bnx_tick(sc); 4349 4350 /* Update the status_attn_bits_ack field in the status block. */ 4351 if (new_link_state) { 4352 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4353 STATUS_ATTN_BITS_LINK_STATE); 4354 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4355 } else { 4356 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4357 STATUS_ATTN_BITS_LINK_STATE); 4358 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4359 } 4360 } 4361 4362 /* Acknowledge the link change interrupt. */ 4363 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4364 } 4365 4366 /****************************************************************************/ 4367 /* Handles received frame interrupt events. */ 4368 /* */ 4369 /* Returns: */ 4370 /* Nothing. */ 4371 /****************************************************************************/ 4372 void 4373 bnx_rx_intr(struct bnx_softc *sc) 4374 { 4375 struct status_block *sblk = sc->status_block; 4376 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4377 uint16_t hw_cons, sw_cons, sw_chain_cons; 4378 uint16_t sw_prod, sw_chain_prod; 4379 uint32_t sw_prod_bseq; 4380 struct l2_fhdr *l2fhdr; 4381 int i; 4382 4383 DBRUNIF(1, sc->rx_interrupts++); 4384 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4385 BUS_DMASYNC_POSTREAD); 4386 4387 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4388 for (i = 0; i < RX_PAGES; i++) 4389 bus_dmamap_sync(sc->bnx_dmatag, 4390 sc->rx_bd_chain_map[i], 0, 4391 sc->rx_bd_chain_map[i]->dm_mapsize, 4392 BUS_DMASYNC_POSTWRITE); 4393 4394 /* Get the hardware's view of the RX consumer index. */ 4395 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4396 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4397 hw_cons++; 4398 4399 /* Get working copies of the driver's view of the RX indices. */ 4400 sw_cons = sc->rx_cons; 4401 sw_prod = sc->rx_prod; 4402 sw_prod_bseq = sc->rx_prod_bseq; 4403 4404 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4405 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4406 __func__, sw_prod, sw_cons, sw_prod_bseq); 4407 4408 /* Prevent speculative reads from getting ahead of the status block. */ 4409 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4410 BUS_SPACE_BARRIER_READ); 4411 4412 /* Update some debug statistics counters */ 4413 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4414 sc->rx_low_watermark = sc->free_rx_bd); 4415 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4416 4417 /* 4418 * Scan through the receive chain as long 4419 * as there is work to do. 4420 */ 4421 while (sw_cons != hw_cons) { 4422 struct mbuf *m; 4423 struct rx_bd *rxbd __diagused; 4424 unsigned int len; 4425 uint32_t status; 4426 4427 /* Convert the producer/consumer indices to an actual 4428 * rx_bd index. 4429 */ 4430 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4431 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4432 4433 /* Get the used rx_bd. */ 4434 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4435 sc->free_rx_bd++; 4436 4437 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4438 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4439 4440 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4441 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4442 #ifdef DIAGNOSTIC 4443 /* Validate that this is the last rx_bd. */ 4444 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4445 printf("%s: Unexpected mbuf found in " 4446 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4447 sw_chain_cons); 4448 } 4449 #endif 4450 4451 /* DRC - ToDo: If the received packet is small, say 4452 * less than 128 bytes, allocate a new mbuf 4453 * here, copy the data to that mbuf, and 4454 * recycle the mapped jumbo frame. 4455 */ 4456 4457 /* Unmap the mbuf from DMA space. */ 4458 #ifdef DIAGNOSTIC 4459 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4460 printf("invalid map sw_cons 0x%x " 4461 "sw_prod 0x%x " 4462 "sw_chain_cons 0x%x " 4463 "sw_chain_prod 0x%x " 4464 "hw_cons 0x%x " 4465 "TOTAL_RX_BD_PER_PAGE 0x%x " 4466 "TOTAL_RX_BD 0x%x\n", 4467 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4468 hw_cons, 4469 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4470 } 4471 #endif 4472 bus_dmamap_sync(sc->bnx_dmatag, 4473 sc->rx_mbuf_map[sw_chain_cons], 0, 4474 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4475 BUS_DMASYNC_POSTREAD); 4476 bus_dmamap_unload(sc->bnx_dmatag, 4477 sc->rx_mbuf_map[sw_chain_cons]); 4478 4479 /* Remove the mbuf from the driver's chain. */ 4480 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4481 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4482 4483 /* 4484 * Frames received on the NetXteme II are prepended 4485 * with the l2_fhdr structure which provides status 4486 * information about the received frame (including 4487 * VLAN tags and checksum info) and are also 4488 * automatically adjusted to align the IP header 4489 * (i.e. two null bytes are inserted before the 4490 * Ethernet header). 4491 */ 4492 l2fhdr = mtod(m, struct l2_fhdr *); 4493 4494 len = l2fhdr->l2_fhdr_pkt_len; 4495 status = l2fhdr->l2_fhdr_status; 4496 4497 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4498 aprint_error("Simulating l2_fhdr status error.\n"); 4499 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4500 4501 /* Watch for unusual sized frames. */ 4502 DBRUNIF(((len < BNX_MIN_MTU) || 4503 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4504 aprint_error_dev(sc->bnx_dev, 4505 "Unusual frame size found. " 4506 "Min(%d), Actual(%d), Max(%d)\n", 4507 (int)BNX_MIN_MTU, len, 4508 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4509 4510 bnx_dump_mbuf(sc, m); 4511 bnx_breakpoint(sc)); 4512 4513 len -= ETHER_CRC_LEN; 4514 4515 /* Check the received frame for errors. */ 4516 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4517 L2_FHDR_ERRORS_PHY_DECODE | 4518 L2_FHDR_ERRORS_ALIGNMENT | 4519 L2_FHDR_ERRORS_TOO_SHORT | 4520 L2_FHDR_ERRORS_GIANT_FRAME)) || 4521 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4522 len > 4523 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4524 ifp->if_ierrors++; 4525 DBRUNIF(1, sc->l2fhdr_status_errors++); 4526 4527 /* Reuse the mbuf for a new frame. */ 4528 if (bnx_add_buf(sc, m, &sw_prod, 4529 &sw_chain_prod, &sw_prod_bseq)) { 4530 DBRUNIF(1, bnx_breakpoint(sc)); 4531 panic("%s: Can't reuse RX mbuf!\n", 4532 device_xname(sc->bnx_dev)); 4533 } 4534 continue; 4535 } 4536 4537 /* 4538 * Get a new mbuf for the rx_bd. If no new 4539 * mbufs are available then reuse the current mbuf, 4540 * log an ierror on the interface, and generate 4541 * an error in the system log. 4542 */ 4543 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4544 &sw_prod_bseq)) { 4545 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4546 "Failed to allocate " 4547 "new mbuf, incoming frame dropped!\n")); 4548 4549 ifp->if_ierrors++; 4550 4551 /* Try and reuse the exisitng mbuf. */ 4552 if (bnx_add_buf(sc, m, &sw_prod, 4553 &sw_chain_prod, &sw_prod_bseq)) { 4554 DBRUNIF(1, bnx_breakpoint(sc)); 4555 panic("%s: Double mbuf allocation " 4556 "failure!", 4557 device_xname(sc->bnx_dev)); 4558 } 4559 continue; 4560 } 4561 4562 /* Skip over the l2_fhdr when passing the data up 4563 * the stack. 4564 */ 4565 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4566 4567 /* Adjust the pckt length to match the received data. */ 4568 m->m_pkthdr.len = m->m_len = len; 4569 4570 /* Send the packet to the appropriate interface. */ 4571 m_set_rcvif(m, ifp); 4572 4573 DBRUN(BNX_VERBOSE_RECV, 4574 struct ether_header *eh; 4575 eh = mtod(m, struct ether_header *); 4576 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4577 __func__, ether_sprintf(eh->ether_dhost), 4578 ether_sprintf(eh->ether_shost), 4579 htons(eh->ether_type))); 4580 4581 /* Validate the checksum. */ 4582 4583 /* Check for an IP datagram. */ 4584 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4585 /* Check if the IP checksum is valid. */ 4586 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4587 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4588 #ifdef BNX_DEBUG 4589 else 4590 DBPRINT(sc, BNX_WARN_SEND, 4591 "%s(): Invalid IP checksum " 4592 "= 0x%04X!\n", 4593 __func__, 4594 l2fhdr->l2_fhdr_ip_xsum 4595 ); 4596 #endif 4597 } 4598 4599 /* Check for a valid TCP/UDP frame. */ 4600 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4601 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4602 /* Check for a good TCP/UDP checksum. */ 4603 if ((status & 4604 (L2_FHDR_ERRORS_TCP_XSUM | 4605 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4606 m->m_pkthdr.csum_flags |= 4607 M_CSUM_TCPv4 | 4608 M_CSUM_UDPv4; 4609 } else { 4610 DBPRINT(sc, BNX_WARN_SEND, 4611 "%s(): Invalid TCP/UDP " 4612 "checksum = 0x%04X!\n", 4613 __func__, 4614 l2fhdr->l2_fhdr_tcp_udp_xsum); 4615 } 4616 } 4617 4618 /* 4619 * If we received a packet with a vlan tag, 4620 * attach that information to the packet. 4621 */ 4622 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4623 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4624 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4625 } 4626 4627 /* Pass the mbuf off to the upper layers. */ 4628 4629 DBPRINT(sc, BNX_VERBOSE_RECV, 4630 "%s(): Passing received frame up.\n", __func__); 4631 if_percpuq_enqueue(ifp->if_percpuq, m); 4632 DBRUNIF(1, sc->rx_mbuf_alloc--); 4633 4634 } 4635 4636 sw_cons = NEXT_RX_BD(sw_cons); 4637 4638 /* Refresh hw_cons to see if there's new work */ 4639 if (sw_cons == hw_cons) { 4640 hw_cons = sc->hw_rx_cons = 4641 sblk->status_rx_quick_consumer_index0; 4642 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4643 USABLE_RX_BD_PER_PAGE) 4644 hw_cons++; 4645 } 4646 4647 /* Prevent speculative reads from getting ahead of 4648 * the status block. 4649 */ 4650 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4651 BUS_SPACE_BARRIER_READ); 4652 } 4653 4654 for (i = 0; i < RX_PAGES; i++) 4655 bus_dmamap_sync(sc->bnx_dmatag, 4656 sc->rx_bd_chain_map[i], 0, 4657 sc->rx_bd_chain_map[i]->dm_mapsize, 4658 BUS_DMASYNC_PREWRITE); 4659 4660 sc->rx_cons = sw_cons; 4661 sc->rx_prod = sw_prod; 4662 sc->rx_prod_bseq = sw_prod_bseq; 4663 4664 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4665 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4666 4667 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4668 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4669 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4670 } 4671 4672 /****************************************************************************/ 4673 /* Handles transmit completion interrupt events. */ 4674 /* */ 4675 /* Returns: */ 4676 /* Nothing. */ 4677 /****************************************************************************/ 4678 void 4679 bnx_tx_intr(struct bnx_softc *sc) 4680 { 4681 struct status_block *sblk = sc->status_block; 4682 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4683 struct bnx_pkt *pkt; 4684 bus_dmamap_t map; 4685 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4686 4687 DBRUNIF(1, sc->tx_interrupts++); 4688 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4689 BUS_DMASYNC_POSTREAD); 4690 4691 /* Get the hardware's view of the TX consumer index. */ 4692 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4693 4694 /* Skip to the next entry if this is a chain page pointer. */ 4695 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4696 hw_tx_cons++; 4697 4698 sw_tx_cons = sc->tx_cons; 4699 4700 /* Prevent speculative reads from getting ahead of the status block. */ 4701 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4702 BUS_SPACE_BARRIER_READ); 4703 4704 /* Cycle through any completed TX chain page entries. */ 4705 while (sw_tx_cons != hw_tx_cons) { 4706 #ifdef BNX_DEBUG 4707 struct tx_bd *txbd = NULL; 4708 #endif 4709 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4710 4711 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4712 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4713 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4714 4715 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4716 aprint_error_dev(sc->bnx_dev, 4717 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4718 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4719 4720 DBRUNIF(1, txbd = &sc->tx_bd_chain 4721 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4722 4723 DBRUNIF((txbd == NULL), 4724 aprint_error_dev(sc->bnx_dev, 4725 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4726 bnx_breakpoint(sc)); 4727 4728 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4729 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4730 4731 4732 mutex_enter(&sc->tx_pkt_mtx); 4733 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4734 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4735 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4736 mutex_exit(&sc->tx_pkt_mtx); 4737 /* 4738 * Free the associated mbuf. Remember 4739 * that only the last tx_bd of a packet 4740 * has an mbuf pointer and DMA map. 4741 */ 4742 map = pkt->pkt_dmamap; 4743 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4744 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4745 bus_dmamap_unload(sc->bnx_dmatag, map); 4746 4747 m_freem(pkt->pkt_mbuf); 4748 DBRUNIF(1, sc->tx_mbuf_alloc--); 4749 4750 ifp->if_opackets++; 4751 4752 mutex_enter(&sc->tx_pkt_mtx); 4753 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4754 } 4755 mutex_exit(&sc->tx_pkt_mtx); 4756 4757 sc->used_tx_bd--; 4758 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4759 __FILE__, __LINE__, sc->used_tx_bd); 4760 4761 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4762 4763 /* Refresh hw_cons to see if there's new work. */ 4764 hw_tx_cons = sc->hw_tx_cons = 4765 sblk->status_tx_quick_consumer_index0; 4766 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4767 USABLE_TX_BD_PER_PAGE) 4768 hw_tx_cons++; 4769 4770 /* Prevent speculative reads from getting ahead of 4771 * the status block. 4772 */ 4773 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4774 BUS_SPACE_BARRIER_READ); 4775 } 4776 4777 /* Clear the TX timeout timer. */ 4778 ifp->if_timer = 0; 4779 4780 /* Clear the tx hardware queue full flag. */ 4781 if (sc->used_tx_bd < sc->max_tx_bd) { 4782 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4783 aprint_debug_dev(sc->bnx_dev, 4784 "Open TX chain! %d/%d (used/total)\n", 4785 sc->used_tx_bd, sc->max_tx_bd)); 4786 ifp->if_flags &= ~IFF_OACTIVE; 4787 } 4788 4789 sc->tx_cons = sw_tx_cons; 4790 } 4791 4792 /****************************************************************************/ 4793 /* Disables interrupt generation. */ 4794 /* */ 4795 /* Returns: */ 4796 /* Nothing. */ 4797 /****************************************************************************/ 4798 void 4799 bnx_disable_intr(struct bnx_softc *sc) 4800 { 4801 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4802 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4803 } 4804 4805 /****************************************************************************/ 4806 /* Enables interrupt generation. */ 4807 /* */ 4808 /* Returns: */ 4809 /* Nothing. */ 4810 /****************************************************************************/ 4811 void 4812 bnx_enable_intr(struct bnx_softc *sc) 4813 { 4814 uint32_t val; 4815 4816 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4817 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4818 4819 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4820 sc->last_status_idx); 4821 4822 val = REG_RD(sc, BNX_HC_COMMAND); 4823 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4824 } 4825 4826 /****************************************************************************/ 4827 /* Handles controller initialization. */ 4828 /* */ 4829 /****************************************************************************/ 4830 int 4831 bnx_init(struct ifnet *ifp) 4832 { 4833 struct bnx_softc *sc = ifp->if_softc; 4834 uint32_t ether_mtu; 4835 int s, error = 0; 4836 4837 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4838 4839 s = splnet(); 4840 4841 bnx_stop(ifp, 0); 4842 4843 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4844 aprint_error_dev(sc->bnx_dev, 4845 "Controller reset failed!\n"); 4846 goto bnx_init_exit; 4847 } 4848 4849 if ((error = bnx_chipinit(sc)) != 0) { 4850 aprint_error_dev(sc->bnx_dev, 4851 "Controller initialization failed!\n"); 4852 goto bnx_init_exit; 4853 } 4854 4855 if ((error = bnx_blockinit(sc)) != 0) { 4856 aprint_error_dev(sc->bnx_dev, 4857 "Block initialization failed!\n"); 4858 goto bnx_init_exit; 4859 } 4860 4861 /* Calculate and program the Ethernet MRU size. */ 4862 if (ifp->if_mtu <= ETHERMTU) { 4863 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4864 sc->mbuf_alloc_size = MCLBYTES; 4865 } else { 4866 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4867 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4868 } 4869 4870 4871 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 4872 4873 /* 4874 * Program the MRU and enable Jumbo frame 4875 * support. 4876 */ 4877 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4878 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4879 4880 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4881 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4882 4883 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4884 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4885 sc->mbuf_alloc_size, sc->max_frame_size); 4886 4887 /* Program appropriate promiscuous/multicast filtering. */ 4888 bnx_iff(sc); 4889 4890 /* Init RX buffer descriptor chain. */ 4891 bnx_init_rx_chain(sc); 4892 4893 /* Init TX buffer descriptor chain. */ 4894 bnx_init_tx_chain(sc); 4895 4896 /* Enable host interrupts. */ 4897 bnx_enable_intr(sc); 4898 4899 if ((error = ether_mediachange(ifp)) != 0) 4900 goto bnx_init_exit; 4901 4902 SET(ifp->if_flags, IFF_RUNNING); 4903 CLR(ifp->if_flags, IFF_OACTIVE); 4904 4905 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4906 4907 bnx_init_exit: 4908 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4909 4910 splx(s); 4911 4912 return error; 4913 } 4914 4915 /****************************************************************************/ 4916 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4917 /* memory visible to the controller. */ 4918 /* */ 4919 /* Returns: */ 4920 /* 0 for success, positive value for failure. */ 4921 /****************************************************************************/ 4922 int 4923 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4924 { 4925 struct bnx_pkt *pkt; 4926 bus_dmamap_t map; 4927 struct tx_bd *txbd = NULL; 4928 uint16_t vlan_tag = 0, flags = 0; 4929 uint16_t chain_prod, prod; 4930 #ifdef BNX_DEBUG 4931 uint16_t debug_prod; 4932 #endif 4933 uint32_t addr, prod_bseq; 4934 int i, error; 4935 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 4936 4937 mutex_enter(&sc->tx_pkt_mtx); 4938 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 4939 if (pkt == NULL) { 4940 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 4941 mutex_exit(&sc->tx_pkt_mtx); 4942 return ENETDOWN; 4943 } 4944 4945 if (sc->tx_pkt_count <= TOTAL_TX_BD && 4946 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 4947 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 4948 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4949 } 4950 4951 mutex_exit(&sc->tx_pkt_mtx); 4952 return ENOMEM; 4953 } 4954 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4955 mutex_exit(&sc->tx_pkt_mtx); 4956 4957 /* Transfer any checksum offload flags to the bd. */ 4958 if (m->m_pkthdr.csum_flags) { 4959 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 4960 flags |= TX_BD_FLAGS_IP_CKSUM; 4961 if (m->m_pkthdr.csum_flags & 4962 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 4963 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4964 } 4965 4966 /* Transfer any VLAN tags to the bd. */ 4967 if (vlan_has_tag(m)) { 4968 flags |= TX_BD_FLAGS_VLAN_TAG; 4969 vlan_tag = vlan_get_tag(m); 4970 } 4971 4972 /* Map the mbuf into DMAable memory. */ 4973 prod = sc->tx_prod; 4974 chain_prod = TX_CHAIN_IDX(prod); 4975 map = pkt->pkt_dmamap; 4976 4977 /* Map the mbuf into our DMA address space. */ 4978 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 4979 if (error != 0) { 4980 aprint_error_dev(sc->bnx_dev, 4981 "Error mapping mbuf into TX chain!\n"); 4982 sc->tx_dma_map_failures++; 4983 goto maperr; 4984 } 4985 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 4986 BUS_DMASYNC_PREWRITE); 4987 /* Make sure there's room in the chain */ 4988 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 4989 goto nospace; 4990 4991 /* prod points to an empty tx_bd at this point. */ 4992 prod_bseq = sc->tx_prod_bseq; 4993 #ifdef BNX_DEBUG 4994 debug_prod = chain_prod; 4995 #endif 4996 DBPRINT(sc, BNX_INFO_SEND, 4997 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4998 "prod_bseq = 0x%08X\n", 4999 __func__, prod, chain_prod, prod_bseq); 5000 5001 /* 5002 * Cycle through each mbuf segment that makes up 5003 * the outgoing frame, gathering the mapping info 5004 * for that segment and creating a tx_bd for the 5005 * mbuf. 5006 */ 5007 for (i = 0; i < map->dm_nsegs ; i++) { 5008 chain_prod = TX_CHAIN_IDX(prod); 5009 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5010 5011 addr = (uint32_t)map->dm_segs[i].ds_addr; 5012 txbd->tx_bd_haddr_lo = addr; 5013 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5014 txbd->tx_bd_haddr_hi = addr; 5015 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5016 txbd->tx_bd_vlan_tag = vlan_tag; 5017 txbd->tx_bd_flags = flags; 5018 prod_bseq += map->dm_segs[i].ds_len; 5019 if (i == 0) 5020 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5021 prod = NEXT_TX_BD(prod); 5022 } 5023 /* Set the END flag on the last TX buffer descriptor. */ 5024 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5025 5026 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5027 5028 DBPRINT(sc, BNX_INFO_SEND, 5029 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5030 "prod_bseq = 0x%08X\n", 5031 __func__, prod, chain_prod, prod_bseq); 5032 5033 pkt->pkt_mbuf = m; 5034 pkt->pkt_end_desc = chain_prod; 5035 5036 mutex_enter(&sc->tx_pkt_mtx); 5037 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5038 mutex_exit(&sc->tx_pkt_mtx); 5039 5040 sc->used_tx_bd += map->dm_nsegs; 5041 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5042 __FILE__, __LINE__, sc->used_tx_bd); 5043 5044 /* Update some debug statistics counters */ 5045 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5046 sc->tx_hi_watermark = sc->used_tx_bd); 5047 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5048 DBRUNIF(1, sc->tx_mbuf_alloc++); 5049 5050 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5051 map->dm_nsegs)); 5052 5053 /* prod points to the next free tx_bd at this point. */ 5054 sc->tx_prod = prod; 5055 sc->tx_prod_bseq = prod_bseq; 5056 5057 return 0; 5058 5059 5060 nospace: 5061 bus_dmamap_unload(sc->bnx_dmatag, map); 5062 maperr: 5063 mutex_enter(&sc->tx_pkt_mtx); 5064 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5065 mutex_exit(&sc->tx_pkt_mtx); 5066 5067 return ENOMEM; 5068 } 5069 5070 /****************************************************************************/ 5071 /* Main transmit routine. */ 5072 /* */ 5073 /* Returns: */ 5074 /* Nothing. */ 5075 /****************************************************************************/ 5076 void 5077 bnx_start(struct ifnet *ifp) 5078 { 5079 struct bnx_softc *sc = ifp->if_softc; 5080 struct mbuf *m_head = NULL; 5081 int count = 0; 5082 #ifdef BNX_DEBUG 5083 uint16_t tx_chain_prod; 5084 #endif 5085 5086 /* If there's no link or the transmit queue is empty then just exit. */ 5087 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5088 DBPRINT(sc, BNX_INFO_SEND, 5089 "%s(): output active or device not running.\n", __func__); 5090 goto bnx_start_exit; 5091 } 5092 5093 /* prod points to the next free tx_bd. */ 5094 #ifdef BNX_DEBUG 5095 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5096 #endif 5097 5098 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5099 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5100 "used_tx %d max_tx %d\n", 5101 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5102 sc->used_tx_bd, sc->max_tx_bd); 5103 5104 /* 5105 * Keep adding entries while there is space in the ring. 5106 */ 5107 while (sc->used_tx_bd < sc->max_tx_bd) { 5108 /* Check for any frames to send. */ 5109 IFQ_POLL(&ifp->if_snd, m_head); 5110 if (m_head == NULL) 5111 break; 5112 5113 /* 5114 * Pack the data into the transmit ring. If we 5115 * don't have room, set the OACTIVE flag to wait 5116 * for the NIC to drain the chain. 5117 */ 5118 if (bnx_tx_encap(sc, m_head)) { 5119 ifp->if_flags |= IFF_OACTIVE; 5120 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5121 "business! Total tx_bd used = %d\n", 5122 sc->used_tx_bd); 5123 break; 5124 } 5125 5126 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5127 count++; 5128 5129 /* Send a copy of the frame to any BPF listeners. */ 5130 bpf_mtap(ifp, m_head, BPF_D_OUT); 5131 } 5132 5133 if (count == 0) { 5134 /* no packets were dequeued */ 5135 DBPRINT(sc, BNX_VERBOSE_SEND, 5136 "%s(): No packets were dequeued\n", __func__); 5137 goto bnx_start_exit; 5138 } 5139 5140 /* Update the driver's counters. */ 5141 #ifdef BNX_DEBUG 5142 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5143 #endif 5144 5145 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5146 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5147 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5148 5149 /* Start the transmit. */ 5150 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5151 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5152 5153 /* Set the tx timeout. */ 5154 ifp->if_timer = BNX_TX_TIMEOUT; 5155 5156 bnx_start_exit: 5157 return; 5158 } 5159 5160 /****************************************************************************/ 5161 /* Handles any IOCTL calls from the operating system. */ 5162 /* */ 5163 /* Returns: */ 5164 /* 0 for success, positive value for failure. */ 5165 /****************************************************************************/ 5166 int 5167 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5168 { 5169 struct bnx_softc *sc = ifp->if_softc; 5170 struct ifreq *ifr = (struct ifreq *) data; 5171 struct mii_data *mii = &sc->bnx_mii; 5172 int s, error = 0; 5173 5174 s = splnet(); 5175 5176 switch (command) { 5177 case SIOCSIFFLAGS: 5178 if ((error = ifioctl_common(ifp, command, data)) != 0) 5179 break; 5180 /* XXX set an ifflags callback and let ether_ioctl 5181 * handle all of this. 5182 */ 5183 if (ISSET(ifp->if_flags, IFF_UP)) { 5184 if (ifp->if_flags & IFF_RUNNING) 5185 error = ENETRESET; 5186 else 5187 bnx_init(ifp); 5188 } else if (ifp->if_flags & IFF_RUNNING) 5189 bnx_stop(ifp, 1); 5190 break; 5191 5192 case SIOCSIFMEDIA: 5193 case SIOCGIFMEDIA: 5194 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5195 sc->bnx_phy_flags); 5196 5197 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5198 break; 5199 5200 default: 5201 error = ether_ioctl(ifp, command, data); 5202 } 5203 5204 if (error == ENETRESET) { 5205 if (ifp->if_flags & IFF_RUNNING) 5206 bnx_iff(sc); 5207 error = 0; 5208 } 5209 5210 splx(s); 5211 return error; 5212 } 5213 5214 /****************************************************************************/ 5215 /* Transmit timeout handler. */ 5216 /* */ 5217 /* Returns: */ 5218 /* Nothing. */ 5219 /****************************************************************************/ 5220 void 5221 bnx_watchdog(struct ifnet *ifp) 5222 { 5223 struct bnx_softc *sc = ifp->if_softc; 5224 5225 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5226 bnx_dump_status_block(sc)); 5227 /* 5228 * If we are in this routine because of pause frames, then 5229 * don't reset the hardware. 5230 */ 5231 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5232 return; 5233 5234 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5235 5236 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5237 5238 bnx_init(ifp); 5239 5240 ifp->if_oerrors++; 5241 } 5242 5243 /* 5244 * Interrupt handler. 5245 */ 5246 /****************************************************************************/ 5247 /* Main interrupt entry point. Verifies that the controller generated the */ 5248 /* interrupt and then calls a separate routine for handle the various */ 5249 /* interrupt causes (PHY, TX, RX). */ 5250 /* */ 5251 /* Returns: */ 5252 /* 0 for success, positive value for failure. */ 5253 /****************************************************************************/ 5254 int 5255 bnx_intr(void *xsc) 5256 { 5257 struct bnx_softc *sc; 5258 struct ifnet *ifp; 5259 uint32_t status_attn_bits; 5260 const struct status_block *sblk; 5261 5262 sc = xsc; 5263 5264 ifp = &sc->bnx_ec.ec_if; 5265 5266 if (!device_is_active(sc->bnx_dev) || 5267 (ifp->if_flags & IFF_RUNNING) == 0) 5268 return 0; 5269 5270 DBRUNIF(1, sc->interrupts_generated++); 5271 5272 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5273 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 5274 5275 /* 5276 * If the hardware status block index 5277 * matches the last value read by the 5278 * driver and we haven't asserted our 5279 * interrupt then there's nothing to do. 5280 */ 5281 if ((sc->status_block->status_idx == sc->last_status_idx) && 5282 (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & 5283 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) 5284 return 0; 5285 5286 /* Ack the interrupt and stop others from occurring. */ 5287 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5288 BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5289 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5290 5291 /* Keep processing data as long as there is work to do. */ 5292 for (;;) { 5293 sblk = sc->status_block; 5294 status_attn_bits = sblk->status_attn_bits; 5295 5296 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5297 aprint_debug("Simulating unexpected status attention bit set."); 5298 status_attn_bits = status_attn_bits | 5299 STATUS_ATTN_BITS_PARITY_ERROR); 5300 5301 /* Was it a link change interrupt? */ 5302 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5303 (sblk->status_attn_bits_ack & 5304 STATUS_ATTN_BITS_LINK_STATE)) 5305 bnx_phy_intr(sc); 5306 5307 /* If any other attention is asserted then the chip is toast. */ 5308 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5309 (sblk->status_attn_bits_ack & 5310 ~STATUS_ATTN_BITS_LINK_STATE))) { 5311 DBRUN(1, sc->unexpected_attentions++); 5312 5313 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5314 sblk->status_attn_bits); 5315 5316 DBRUN(BNX_FATAL, 5317 if (bnx_debug_unexpected_attention == 0) 5318 bnx_breakpoint(sc)); 5319 5320 bnx_init(ifp); 5321 return 1; 5322 } 5323 5324 /* Check for any completed RX frames. */ 5325 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5326 bnx_rx_intr(sc); 5327 5328 /* Check for any completed TX frames. */ 5329 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5330 bnx_tx_intr(sc); 5331 5332 /* 5333 * Save the status block index value for use during the 5334 * next interrupt. 5335 */ 5336 sc->last_status_idx = sblk->status_idx; 5337 5338 /* Prevent speculative reads from getting ahead of the 5339 * status block. 5340 */ 5341 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 5342 BUS_SPACE_BARRIER_READ); 5343 5344 /* If there's no work left then exit the isr. */ 5345 if ((sblk->status_rx_quick_consumer_index0 == 5346 sc->hw_rx_cons) && 5347 (sblk->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5348 break; 5349 } 5350 5351 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5352 sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 5353 5354 /* Re-enable interrupts. */ 5355 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5356 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5357 BNX_PCICFG_INT_ACK_CMD_MASK_INT); 5358 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5359 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5360 5361 /* Handle any frames that arrived while handling the interrupt. */ 5362 if_schedule_deferred_start(ifp); 5363 5364 return 1; 5365 } 5366 5367 /****************************************************************************/ 5368 /* Programs the various packet receive modes (broadcast and multicast). */ 5369 /* */ 5370 /* Returns: */ 5371 /* Nothing. */ 5372 /****************************************************************************/ 5373 void 5374 bnx_iff(struct bnx_softc *sc) 5375 { 5376 struct ethercom *ec = &sc->bnx_ec; 5377 struct ifnet *ifp = &ec->ec_if; 5378 struct ether_multi *enm; 5379 struct ether_multistep step; 5380 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5381 uint32_t rx_mode, sort_mode; 5382 int h, i; 5383 5384 /* Initialize receive mode default settings. */ 5385 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5386 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5387 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5388 ifp->if_flags &= ~IFF_ALLMULTI; 5389 5390 /* 5391 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5392 * be enbled. 5393 */ 5394 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5395 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5396 5397 /* 5398 * Check for promiscuous, all multicast, or selected 5399 * multicast address filtering. 5400 */ 5401 if (ifp->if_flags & IFF_PROMISC) { 5402 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5403 5404 ifp->if_flags |= IFF_ALLMULTI; 5405 /* Enable promiscuous mode. */ 5406 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5407 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5408 } else if (ifp->if_flags & IFF_ALLMULTI) { 5409 allmulti: 5410 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5411 5412 ifp->if_flags |= IFF_ALLMULTI; 5413 /* Enable all multicast addresses. */ 5414 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5415 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5416 0xffffffff); 5417 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5418 } else { 5419 /* Accept one or more multicast(s). */ 5420 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5421 5422 ETHER_FIRST_MULTI(step, ec, enm); 5423 while (enm != NULL) { 5424 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5425 ETHER_ADDR_LEN)) { 5426 goto allmulti; 5427 } 5428 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5429 0xFF; 5430 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5431 ETHER_NEXT_MULTI(step, enm); 5432 } 5433 5434 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5435 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5436 hashes[i]); 5437 5438 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5439 } 5440 5441 /* Only make changes if the recive mode has actually changed. */ 5442 if (rx_mode != sc->rx_mode) { 5443 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5444 rx_mode); 5445 5446 sc->rx_mode = rx_mode; 5447 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5448 } 5449 5450 /* Disable and clear the exisitng sort before enabling a new sort. */ 5451 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5452 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5453 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5454 } 5455 5456 /****************************************************************************/ 5457 /* Called periodically to updates statistics from the controllers */ 5458 /* statistics block. */ 5459 /* */ 5460 /* Returns: */ 5461 /* Nothing. */ 5462 /****************************************************************************/ 5463 void 5464 bnx_stats_update(struct bnx_softc *sc) 5465 { 5466 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5467 struct statistics_block *stats; 5468 5469 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5470 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5471 BUS_DMASYNC_POSTREAD); 5472 5473 stats = (struct statistics_block *)sc->stats_block; 5474 5475 /* 5476 * Update the interface statistics from the 5477 * hardware statistics. 5478 */ 5479 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5480 5481 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5482 (u_long)stats->stat_EtherStatsOverrsizePkts + 5483 (u_long)stats->stat_IfInMBUFDiscards + 5484 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5485 (u_long)stats->stat_Dot3StatsFCSErrors; 5486 5487 ifp->if_oerrors = (u_long) 5488 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5489 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5490 (u_long)stats->stat_Dot3StatsLateCollisions; 5491 5492 /* 5493 * Certain controllers don't report 5494 * carrier sense errors correctly. 5495 * See errata E11_5708CA0_1165. 5496 */ 5497 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5498 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5499 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5500 5501 /* 5502 * Update the sysctl statistics from the 5503 * hardware statistics. 5504 */ 5505 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5506 (uint64_t) stats->stat_IfHCInOctets_lo; 5507 5508 sc->stat_IfHCInBadOctets = 5509 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5510 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5511 5512 sc->stat_IfHCOutOctets = 5513 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5514 (uint64_t) stats->stat_IfHCOutOctets_lo; 5515 5516 sc->stat_IfHCOutBadOctets = 5517 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5518 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5519 5520 sc->stat_IfHCInUcastPkts = 5521 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5522 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5523 5524 sc->stat_IfHCInMulticastPkts = 5525 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5526 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5527 5528 sc->stat_IfHCInBroadcastPkts = 5529 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5530 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5531 5532 sc->stat_IfHCOutUcastPkts = 5533 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5534 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5535 5536 sc->stat_IfHCOutMulticastPkts = 5537 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5538 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5539 5540 sc->stat_IfHCOutBroadcastPkts = 5541 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5542 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5543 5544 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5545 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5546 5547 sc->stat_Dot3StatsCarrierSenseErrors = 5548 stats->stat_Dot3StatsCarrierSenseErrors; 5549 5550 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5551 5552 sc->stat_Dot3StatsAlignmentErrors = 5553 stats->stat_Dot3StatsAlignmentErrors; 5554 5555 sc->stat_Dot3StatsSingleCollisionFrames = 5556 stats->stat_Dot3StatsSingleCollisionFrames; 5557 5558 sc->stat_Dot3StatsMultipleCollisionFrames = 5559 stats->stat_Dot3StatsMultipleCollisionFrames; 5560 5561 sc->stat_Dot3StatsDeferredTransmissions = 5562 stats->stat_Dot3StatsDeferredTransmissions; 5563 5564 sc->stat_Dot3StatsExcessiveCollisions = 5565 stats->stat_Dot3StatsExcessiveCollisions; 5566 5567 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5568 5569 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5570 5571 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5572 5573 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5574 5575 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5576 5577 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5578 5579 sc->stat_EtherStatsPktsRx64Octets = 5580 stats->stat_EtherStatsPktsRx64Octets; 5581 5582 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5583 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5584 5585 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5586 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5587 5588 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5589 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5590 5591 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5592 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5593 5594 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5595 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5596 5597 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5598 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5599 5600 sc->stat_EtherStatsPktsTx64Octets = 5601 stats->stat_EtherStatsPktsTx64Octets; 5602 5603 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5604 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5605 5606 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5607 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5608 5609 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5610 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5611 5612 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5613 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5614 5615 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5616 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5617 5618 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5619 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5620 5621 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5622 5623 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5624 5625 sc->stat_OutXonSent = stats->stat_OutXonSent; 5626 5627 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5628 5629 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5630 5631 sc->stat_MacControlFramesReceived = 5632 stats->stat_MacControlFramesReceived; 5633 5634 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5635 5636 sc->stat_IfInFramesL2FilterDiscards = 5637 stats->stat_IfInFramesL2FilterDiscards; 5638 5639 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5640 5641 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5642 5643 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5644 5645 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5646 5647 sc->stat_CatchupInRuleCheckerDiscards = 5648 stats->stat_CatchupInRuleCheckerDiscards; 5649 5650 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5651 5652 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5653 5654 sc->stat_CatchupInRuleCheckerP4Hit = 5655 stats->stat_CatchupInRuleCheckerP4Hit; 5656 5657 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5658 } 5659 5660 void 5661 bnx_tick(void *xsc) 5662 { 5663 struct bnx_softc *sc = xsc; 5664 struct mii_data *mii; 5665 uint32_t msg; 5666 uint16_t prod, chain_prod; 5667 uint32_t prod_bseq; 5668 int s = splnet(); 5669 5670 /* Tell the firmware that the driver is still running. */ 5671 #ifdef BNX_DEBUG 5672 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5673 #else 5674 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5675 #endif 5676 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5677 5678 /* Update the statistics from the hardware statistics block. */ 5679 bnx_stats_update(sc); 5680 5681 mii = &sc->bnx_mii; 5682 mii_tick(mii); 5683 5684 /* try to get more RX buffers, just in case */ 5685 prod = sc->rx_prod; 5686 prod_bseq = sc->rx_prod_bseq; 5687 chain_prod = RX_CHAIN_IDX(prod); 5688 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5689 sc->rx_prod = prod; 5690 sc->rx_prod_bseq = prod_bseq; 5691 5692 /* Schedule the next tick. */ 5693 if (!sc->bnx_detaching) 5694 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5695 5696 splx(s); 5697 return; 5698 } 5699 5700 /****************************************************************************/ 5701 /* BNX Debug Routines */ 5702 /****************************************************************************/ 5703 #ifdef BNX_DEBUG 5704 5705 /****************************************************************************/ 5706 /* Prints out information about an mbuf. */ 5707 /* */ 5708 /* Returns: */ 5709 /* Nothing. */ 5710 /****************************************************************************/ 5711 void 5712 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5713 { 5714 struct mbuf *mp = m; 5715 5716 if (m == NULL) { 5717 /* Index out of range. */ 5718 aprint_error("mbuf ptr is null!\n"); 5719 return; 5720 } 5721 5722 while (mp) { 5723 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5724 mp, mp->m_len); 5725 5726 if (mp->m_flags & M_EXT) 5727 aprint_debug("M_EXT "); 5728 if (mp->m_flags & M_PKTHDR) 5729 aprint_debug("M_PKTHDR "); 5730 aprint_debug("\n"); 5731 5732 if (mp->m_flags & M_EXT) 5733 aprint_debug("- m_ext: vaddr = %p, " 5734 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5735 5736 mp = mp->m_next; 5737 } 5738 } 5739 5740 /****************************************************************************/ 5741 /* Prints out the mbufs in the TX mbuf chain. */ 5742 /* */ 5743 /* Returns: */ 5744 /* Nothing. */ 5745 /****************************************************************************/ 5746 void 5747 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5748 { 5749 #if 0 5750 struct mbuf *m; 5751 int i; 5752 5753 aprint_debug_dev(sc->bnx_dev, 5754 "----------------------------" 5755 " tx mbuf data " 5756 "----------------------------\n"); 5757 5758 for (i = 0; i < count; i++) { 5759 m = sc->tx_mbuf_ptr[chain_prod]; 5760 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5761 bnx_dump_mbuf(sc, m); 5762 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5763 } 5764 5765 aprint_debug_dev(sc->bnx_dev, 5766 "--------------------------------------------" 5767 "----------------------------\n"); 5768 #endif 5769 } 5770 5771 /* 5772 * This routine prints the RX mbuf chain. 5773 */ 5774 void 5775 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5776 { 5777 struct mbuf *m; 5778 int i; 5779 5780 aprint_debug_dev(sc->bnx_dev, 5781 "----------------------------" 5782 " rx mbuf data " 5783 "----------------------------\n"); 5784 5785 for (i = 0; i < count; i++) { 5786 m = sc->rx_mbuf_ptr[chain_prod]; 5787 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5788 bnx_dump_mbuf(sc, m); 5789 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5790 } 5791 5792 5793 aprint_debug_dev(sc->bnx_dev, 5794 "--------------------------------------------" 5795 "----------------------------\n"); 5796 } 5797 5798 void 5799 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5800 { 5801 if (idx > MAX_TX_BD) 5802 /* Index out of range. */ 5803 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5804 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5805 /* TX Chain page pointer. */ 5806 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5807 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5808 txbd->tx_bd_haddr_lo); 5809 else 5810 /* Normal tx_bd entry. */ 5811 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5812 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5813 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5814 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5815 txbd->tx_bd_flags); 5816 } 5817 5818 void 5819 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5820 { 5821 if (idx > MAX_RX_BD) 5822 /* Index out of range. */ 5823 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5824 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5825 /* TX Chain page pointer. */ 5826 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5827 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5828 rxbd->rx_bd_haddr_lo); 5829 else 5830 /* Normal tx_bd entry. */ 5831 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5832 "0x%08X, flags = 0x%08X\n", idx, 5833 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5834 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5835 } 5836 5837 void 5838 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5839 { 5840 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5841 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5842 "tcp_udp_xsum = 0x%04X\n", idx, 5843 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5844 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5845 l2fhdr->l2_fhdr_tcp_udp_xsum); 5846 } 5847 5848 /* 5849 * This routine prints the TX chain. 5850 */ 5851 void 5852 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5853 { 5854 struct tx_bd *txbd; 5855 int i; 5856 5857 /* First some info about the tx_bd chain structure. */ 5858 aprint_debug_dev(sc->bnx_dev, 5859 "----------------------------" 5860 " tx_bd chain " 5861 "----------------------------\n"); 5862 5863 BNX_PRINTF(sc, 5864 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5865 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 5866 5867 BNX_PRINTF(sc, 5868 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5869 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 5870 5871 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5872 5873 aprint_error_dev(sc->bnx_dev, "" 5874 "-----------------------------" 5875 " tx_bd data " 5876 "-----------------------------\n"); 5877 5878 /* Now print out the tx_bd's themselves. */ 5879 for (i = 0; i < count; i++) { 5880 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5881 bnx_dump_txbd(sc, tx_prod, txbd); 5882 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5883 } 5884 5885 aprint_debug_dev(sc->bnx_dev, 5886 "-----------------------------" 5887 "--------------" 5888 "-----------------------------\n"); 5889 } 5890 5891 /* 5892 * This routine prints the RX chain. 5893 */ 5894 void 5895 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5896 { 5897 struct rx_bd *rxbd; 5898 int i; 5899 5900 /* First some info about the tx_bd chain structure. */ 5901 aprint_debug_dev(sc->bnx_dev, 5902 "----------------------------" 5903 " rx_bd chain " 5904 "----------------------------\n"); 5905 5906 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5907 5908 BNX_PRINTF(sc, 5909 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5910 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 5911 5912 BNX_PRINTF(sc, 5913 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5914 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 5915 5916 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5917 5918 aprint_error_dev(sc->bnx_dev, 5919 "----------------------------" 5920 " rx_bd data " 5921 "----------------------------\n"); 5922 5923 /* Now print out the rx_bd's themselves. */ 5924 for (i = 0; i < count; i++) { 5925 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5926 bnx_dump_rxbd(sc, rx_prod, rxbd); 5927 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5928 } 5929 5930 aprint_debug_dev(sc->bnx_dev, 5931 "----------------------------" 5932 "--------------" 5933 "----------------------------\n"); 5934 } 5935 5936 /* 5937 * This routine prints the status block. 5938 */ 5939 void 5940 bnx_dump_status_block(struct bnx_softc *sc) 5941 { 5942 struct status_block *sblk; 5943 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5944 BUS_DMASYNC_POSTREAD); 5945 5946 sblk = sc->status_block; 5947 5948 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 5949 "Status Block -----------------------------\n"); 5950 5951 BNX_PRINTF(sc, 5952 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 5953 sblk->status_attn_bits, sblk->status_attn_bits_ack, 5954 sblk->status_idx); 5955 5956 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 5957 sblk->status_rx_quick_consumer_index0, 5958 sblk->status_tx_quick_consumer_index0); 5959 5960 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 5961 5962 /* Theses indices are not used for normal L2 drivers. */ 5963 if (sblk->status_rx_quick_consumer_index1 || 5964 sblk->status_tx_quick_consumer_index1) 5965 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 5966 sblk->status_rx_quick_consumer_index1, 5967 sblk->status_tx_quick_consumer_index1); 5968 5969 if (sblk->status_rx_quick_consumer_index2 || 5970 sblk->status_tx_quick_consumer_index2) 5971 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 5972 sblk->status_rx_quick_consumer_index2, 5973 sblk->status_tx_quick_consumer_index2); 5974 5975 if (sblk->status_rx_quick_consumer_index3 || 5976 sblk->status_tx_quick_consumer_index3) 5977 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 5978 sblk->status_rx_quick_consumer_index3, 5979 sblk->status_tx_quick_consumer_index3); 5980 5981 if (sblk->status_rx_quick_consumer_index4 || 5982 sblk->status_rx_quick_consumer_index5) 5983 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 5984 sblk->status_rx_quick_consumer_index4, 5985 sblk->status_rx_quick_consumer_index5); 5986 5987 if (sblk->status_rx_quick_consumer_index6 || 5988 sblk->status_rx_quick_consumer_index7) 5989 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 5990 sblk->status_rx_quick_consumer_index6, 5991 sblk->status_rx_quick_consumer_index7); 5992 5993 if (sblk->status_rx_quick_consumer_index8 || 5994 sblk->status_rx_quick_consumer_index9) 5995 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 5996 sblk->status_rx_quick_consumer_index8, 5997 sblk->status_rx_quick_consumer_index9); 5998 5999 if (sblk->status_rx_quick_consumer_index10 || 6000 sblk->status_rx_quick_consumer_index11) 6001 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6002 sblk->status_rx_quick_consumer_index10, 6003 sblk->status_rx_quick_consumer_index11); 6004 6005 if (sblk->status_rx_quick_consumer_index12 || 6006 sblk->status_rx_quick_consumer_index13) 6007 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6008 sblk->status_rx_quick_consumer_index12, 6009 sblk->status_rx_quick_consumer_index13); 6010 6011 if (sblk->status_rx_quick_consumer_index14 || 6012 sblk->status_rx_quick_consumer_index15) 6013 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6014 sblk->status_rx_quick_consumer_index14, 6015 sblk->status_rx_quick_consumer_index15); 6016 6017 if (sblk->status_completion_producer_index || 6018 sblk->status_cmd_consumer_index) 6019 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6020 sblk->status_completion_producer_index, 6021 sblk->status_cmd_consumer_index); 6022 6023 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6024 "-----------------------------\n"); 6025 } 6026 6027 /* 6028 * This routine prints the statistics block. 6029 */ 6030 void 6031 bnx_dump_stats_block(struct bnx_softc *sc) 6032 { 6033 struct statistics_block *sblk; 6034 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6035 BUS_DMASYNC_POSTREAD); 6036 6037 sblk = sc->stats_block; 6038 6039 aprint_debug_dev(sc->bnx_dev, "" 6040 "-----------------------------" 6041 " Stats Block " 6042 "-----------------------------\n"); 6043 6044 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6045 "IfHcInBadOctets = 0x%08X:%08X\n", 6046 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6047 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6048 6049 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6050 "IfHcOutBadOctets = 0x%08X:%08X\n", 6051 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6052 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6053 6054 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6055 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6056 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6057 sblk->stat_IfHCInMulticastPkts_hi, 6058 sblk->stat_IfHCInMulticastPkts_lo); 6059 6060 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6061 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6062 sblk->stat_IfHCInBroadcastPkts_hi, 6063 sblk->stat_IfHCInBroadcastPkts_lo, 6064 sblk->stat_IfHCOutUcastPkts_hi, 6065 sblk->stat_IfHCOutUcastPkts_lo); 6066 6067 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6068 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6069 sblk->stat_IfHCOutMulticastPkts_hi, 6070 sblk->stat_IfHCOutMulticastPkts_lo, 6071 sblk->stat_IfHCOutBroadcastPkts_hi, 6072 sblk->stat_IfHCOutBroadcastPkts_lo); 6073 6074 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6075 BNX_PRINTF(sc, "0x%08X : " 6076 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6077 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6078 6079 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6080 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6081 sblk->stat_Dot3StatsCarrierSenseErrors); 6082 6083 if (sblk->stat_Dot3StatsFCSErrors) 6084 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6085 sblk->stat_Dot3StatsFCSErrors); 6086 6087 if (sblk->stat_Dot3StatsAlignmentErrors) 6088 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6089 sblk->stat_Dot3StatsAlignmentErrors); 6090 6091 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6092 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6093 sblk->stat_Dot3StatsSingleCollisionFrames); 6094 6095 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6096 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6097 sblk->stat_Dot3StatsMultipleCollisionFrames); 6098 6099 if (sblk->stat_Dot3StatsDeferredTransmissions) 6100 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6101 sblk->stat_Dot3StatsDeferredTransmissions); 6102 6103 if (sblk->stat_Dot3StatsExcessiveCollisions) 6104 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6105 sblk->stat_Dot3StatsExcessiveCollisions); 6106 6107 if (sblk->stat_Dot3StatsLateCollisions) 6108 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6109 sblk->stat_Dot3StatsLateCollisions); 6110 6111 if (sblk->stat_EtherStatsCollisions) 6112 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6113 sblk->stat_EtherStatsCollisions); 6114 6115 if (sblk->stat_EtherStatsFragments) 6116 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6117 sblk->stat_EtherStatsFragments); 6118 6119 if (sblk->stat_EtherStatsJabbers) 6120 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6121 sblk->stat_EtherStatsJabbers); 6122 6123 if (sblk->stat_EtherStatsUndersizePkts) 6124 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6125 sblk->stat_EtherStatsUndersizePkts); 6126 6127 if (sblk->stat_EtherStatsOverrsizePkts) 6128 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6129 sblk->stat_EtherStatsOverrsizePkts); 6130 6131 if (sblk->stat_EtherStatsPktsRx64Octets) 6132 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6133 sblk->stat_EtherStatsPktsRx64Octets); 6134 6135 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6136 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6137 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6138 6139 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6140 BNX_PRINTF(sc, "0x%08X : " 6141 "EtherStatsPktsRx128Octetsto255Octets\n", 6142 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6143 6144 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6145 BNX_PRINTF(sc, "0x%08X : " 6146 "EtherStatsPktsRx256Octetsto511Octets\n", 6147 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6148 6149 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6150 BNX_PRINTF(sc, "0x%08X : " 6151 "EtherStatsPktsRx512Octetsto1023Octets\n", 6152 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6153 6154 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6155 BNX_PRINTF(sc, "0x%08X : " 6156 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6157 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6158 6159 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6160 BNX_PRINTF(sc, "0x%08X : " 6161 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6162 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6163 6164 if (sblk->stat_EtherStatsPktsTx64Octets) 6165 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6166 sblk->stat_EtherStatsPktsTx64Octets); 6167 6168 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6169 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6170 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6171 6172 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6173 BNX_PRINTF(sc, "0x%08X : " 6174 "EtherStatsPktsTx128Octetsto255Octets\n", 6175 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6176 6177 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6178 BNX_PRINTF(sc, "0x%08X : " 6179 "EtherStatsPktsTx256Octetsto511Octets\n", 6180 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6181 6182 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6183 BNX_PRINTF(sc, "0x%08X : " 6184 "EtherStatsPktsTx512Octetsto1023Octets\n", 6185 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6186 6187 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6188 BNX_PRINTF(sc, "0x%08X : " 6189 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6190 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6191 6192 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6193 BNX_PRINTF(sc, "0x%08X : " 6194 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6195 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6196 6197 if (sblk->stat_XonPauseFramesReceived) 6198 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6199 sblk->stat_XonPauseFramesReceived); 6200 6201 if (sblk->stat_XoffPauseFramesReceived) 6202 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6203 sblk->stat_XoffPauseFramesReceived); 6204 6205 if (sblk->stat_OutXonSent) 6206 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6207 sblk->stat_OutXonSent); 6208 6209 if (sblk->stat_OutXoffSent) 6210 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6211 sblk->stat_OutXoffSent); 6212 6213 if (sblk->stat_FlowControlDone) 6214 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6215 sblk->stat_FlowControlDone); 6216 6217 if (sblk->stat_MacControlFramesReceived) 6218 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6219 sblk->stat_MacControlFramesReceived); 6220 6221 if (sblk->stat_XoffStateEntered) 6222 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6223 sblk->stat_XoffStateEntered); 6224 6225 if (sblk->stat_IfInFramesL2FilterDiscards) 6226 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6227 sblk->stat_IfInFramesL2FilterDiscards); 6228 6229 if (sblk->stat_IfInRuleCheckerDiscards) 6230 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6231 sblk->stat_IfInRuleCheckerDiscards); 6232 6233 if (sblk->stat_IfInFTQDiscards) 6234 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6235 sblk->stat_IfInFTQDiscards); 6236 6237 if (sblk->stat_IfInMBUFDiscards) 6238 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6239 sblk->stat_IfInMBUFDiscards); 6240 6241 if (sblk->stat_IfInRuleCheckerP4Hit) 6242 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6243 sblk->stat_IfInRuleCheckerP4Hit); 6244 6245 if (sblk->stat_CatchupInRuleCheckerDiscards) 6246 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6247 sblk->stat_CatchupInRuleCheckerDiscards); 6248 6249 if (sblk->stat_CatchupInFTQDiscards) 6250 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6251 sblk->stat_CatchupInFTQDiscards); 6252 6253 if (sblk->stat_CatchupInMBUFDiscards) 6254 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6255 sblk->stat_CatchupInMBUFDiscards); 6256 6257 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6258 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6259 sblk->stat_CatchupInRuleCheckerP4Hit); 6260 6261 aprint_debug_dev(sc->bnx_dev, 6262 "-----------------------------" 6263 "--------------" 6264 "-----------------------------\n"); 6265 } 6266 6267 void 6268 bnx_dump_driver_state(struct bnx_softc *sc) 6269 { 6270 aprint_debug_dev(sc->bnx_dev, 6271 "-----------------------------" 6272 " Driver State " 6273 "-----------------------------\n"); 6274 6275 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6276 "address\n", sc); 6277 6278 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6279 sc->status_block); 6280 6281 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6282 "address\n", sc->stats_block); 6283 6284 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6285 "adddress\n", sc->tx_bd_chain); 6286 6287 #if 0 6288 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6289 sc->rx_bd_chain); 6290 6291 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6292 sc->tx_mbuf_ptr); 6293 #endif 6294 6295 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6296 sc->rx_mbuf_ptr); 6297 6298 BNX_PRINTF(sc, 6299 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6300 sc->interrupts_generated); 6301 6302 BNX_PRINTF(sc, 6303 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6304 sc->rx_interrupts); 6305 6306 BNX_PRINTF(sc, 6307 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6308 sc->tx_interrupts); 6309 6310 BNX_PRINTF(sc, 6311 " 0x%08X - (sc->last_status_idx) status block index\n", 6312 sc->last_status_idx); 6313 6314 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6315 sc->tx_prod); 6316 6317 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6318 sc->tx_cons); 6319 6320 BNX_PRINTF(sc, 6321 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6322 sc->tx_prod_bseq); 6323 BNX_PRINTF(sc, 6324 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6325 sc->tx_mbuf_alloc); 6326 6327 BNX_PRINTF(sc, 6328 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6329 sc->used_tx_bd); 6330 6331 BNX_PRINTF(sc, 6332 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6333 sc->tx_hi_watermark, sc->max_tx_bd); 6334 6335 6336 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6337 sc->rx_prod); 6338 6339 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6340 sc->rx_cons); 6341 6342 BNX_PRINTF(sc, 6343 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6344 sc->rx_prod_bseq); 6345 6346 BNX_PRINTF(sc, 6347 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6348 sc->rx_mbuf_alloc); 6349 6350 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6351 sc->free_rx_bd); 6352 6353 BNX_PRINTF(sc, 6354 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6355 sc->rx_low_watermark, sc->max_rx_bd); 6356 6357 BNX_PRINTF(sc, 6358 " 0x%08X - (sc->mbuf_alloc_failed) " 6359 "mbuf alloc failures\n", 6360 sc->mbuf_alloc_failed); 6361 6362 BNX_PRINTF(sc, 6363 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6364 "simulated mbuf alloc failures\n", 6365 sc->mbuf_sim_alloc_failed); 6366 6367 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6368 "-----------------------------\n"); 6369 } 6370 6371 void 6372 bnx_dump_hw_state(struct bnx_softc *sc) 6373 { 6374 uint32_t val1; 6375 int i; 6376 6377 aprint_debug_dev(sc->bnx_dev, 6378 "----------------------------" 6379 " Hardware State " 6380 "----------------------------\n"); 6381 6382 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6383 6384 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6385 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6386 val1, BNX_MISC_ENABLE_STATUS_BITS); 6387 6388 val1 = REG_RD(sc, BNX_DMA_STATUS); 6389 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6390 6391 val1 = REG_RD(sc, BNX_CTX_STATUS); 6392 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6393 6394 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6395 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6396 BNX_EMAC_STATUS); 6397 6398 val1 = REG_RD(sc, BNX_RPM_STATUS); 6399 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6400 6401 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6402 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6403 BNX_TBDR_STATUS); 6404 6405 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6406 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6407 BNX_TDMA_STATUS); 6408 6409 val1 = REG_RD(sc, BNX_HC_STATUS); 6410 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6411 6412 aprint_debug_dev(sc->bnx_dev, 6413 "----------------------------" 6414 "----------------" 6415 "----------------------------\n"); 6416 6417 aprint_debug_dev(sc->bnx_dev, 6418 "----------------------------" 6419 " Register Dump " 6420 "----------------------------\n"); 6421 6422 for (i = 0x400; i < 0x8000; i += 0x10) 6423 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6424 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6425 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6426 6427 aprint_debug_dev(sc->bnx_dev, 6428 "----------------------------" 6429 "----------------" 6430 "----------------------------\n"); 6431 } 6432 6433 void 6434 bnx_breakpoint(struct bnx_softc *sc) 6435 { 6436 /* Unreachable code to shut the compiler up about unused functions. */ 6437 if (0) { 6438 bnx_dump_txbd(sc, 0, NULL); 6439 bnx_dump_rxbd(sc, 0, NULL); 6440 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6441 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6442 bnx_dump_l2fhdr(sc, 0, NULL); 6443 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6444 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6445 bnx_dump_status_block(sc); 6446 bnx_dump_stats_block(sc); 6447 bnx_dump_driver_state(sc); 6448 bnx_dump_hw_state(sc); 6449 } 6450 6451 bnx_dump_driver_state(sc); 6452 /* Print the important status block fields. */ 6453 bnx_dump_status_block(sc); 6454 6455 #if 0 6456 /* Call the debugger. */ 6457 breakpoint(); 6458 #endif 6459 6460 return; 6461 } 6462 #endif 6463
Indexes created Wed Oct 15 16:09:53 GMT 2025