if_bnx.c revision 1.72
1 /* $NetBSD: if_bnx.c,v 1.72 2019/03/28 02:50:27 msaitoh Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.100 2013/01/13 05:45:10 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.72 2019/03/28 02:50:27 msaitoh Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 /****************************************************************************/ 180 /* Supported Flash NVRAM device data. */ 181 /****************************************************************************/ 182 static struct flash_spec flash_table[] = 183 { 184 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 185 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 186 /* Slow EEPROM */ 187 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 188 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 189 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 190 "EEPROM - slow"}, 191 /* Expansion entry 0001 */ 192 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0001"}, 196 /* Saifun SA25F010 (non-buffered flash) */ 197 /* strap, cfg1, & write1 need updates */ 198 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 201 "Non-buffered flash (128kB)"}, 202 /* Saifun SA25F020 (non-buffered flash) */ 203 /* strap, cfg1, & write1 need updates */ 204 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 205 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 206 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 207 "Non-buffered flash (256kB)"}, 208 /* Expansion entry 0100 */ 209 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 210 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 211 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 212 "Entry 0100"}, 213 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 214 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 216 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 217 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 218 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 219 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 221 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 222 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 223 /* Saifun SA25F005 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 228 "Non-buffered flash (64kB)"}, 229 /* Fast EEPROM */ 230 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 231 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 232 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 233 "EEPROM - fast"}, 234 /* Expansion entry 1001 */ 235 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 236 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 237 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 238 "Entry 1001"}, 239 /* Expansion entry 1010 */ 240 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 241 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 242 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 243 "Entry 1010"}, 244 /* ATMEL AT45DB011B (buffered flash) */ 245 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 246 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 247 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 248 "Buffered flash (128kB)"}, 249 /* Expansion entry 1100 */ 250 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 251 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 252 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 253 "Entry 1100"}, 254 /* Expansion entry 1101 */ 255 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 256 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 257 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 258 "Entry 1101"}, 259 /* Ateml Expansion entry 1110 */ 260 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 261 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 262 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 263 "Entry 1110 (Atmel)"}, 264 /* ATMEL AT45DB021B (buffered flash) */ 265 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 266 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 267 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 268 "Buffered flash (256kB)"}, 269 }; 270 271 /* 272 * The BCM5709 controllers transparently handle the 273 * differences between Atmel 264 byte pages and all 274 * flash devices which use 256 byte pages, so no 275 * logical-to-physical mapping is required in the 276 * driver. 277 */ 278 static struct flash_spec flash_5709 = { 279 .flags = BNX_NV_BUFFERED, 280 .page_bits = BCM5709_FLASH_PAGE_BITS, 281 .page_size = BCM5709_FLASH_PAGE_SIZE, 282 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 283 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 284 .name = "5709 buffered flash (256kB)", 285 }; 286 287 /****************************************************************************/ 288 /* OpenBSD device entry points. */ 289 /****************************************************************************/ 290 static int bnx_probe(device_t, cfdata_t, void *); 291 void bnx_attach(device_t, device_t, void *); 292 int bnx_detach(device_t, int); 293 294 /****************************************************************************/ 295 /* BNX Debug Data Structure Dump Routines */ 296 /****************************************************************************/ 297 #ifdef BNX_DEBUG 298 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 299 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 300 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 301 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 302 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 303 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 304 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 305 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 306 void bnx_dump_status_block(struct bnx_softc *); 307 void bnx_dump_stats_block(struct bnx_softc *); 308 void bnx_dump_driver_state(struct bnx_softc *); 309 void bnx_dump_hw_state(struct bnx_softc *); 310 void bnx_breakpoint(struct bnx_softc *); 311 #endif 312 313 /****************************************************************************/ 314 /* BNX Register/Memory Access Routines */ 315 /****************************************************************************/ 316 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 317 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 318 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 319 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 320 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 321 void bnx_miibus_statchg(struct ifnet *); 322 323 /****************************************************************************/ 324 /* BNX NVRAM Access Routines */ 325 /****************************************************************************/ 326 int bnx_acquire_nvram_lock(struct bnx_softc *); 327 int bnx_release_nvram_lock(struct bnx_softc *); 328 void bnx_enable_nvram_access(struct bnx_softc *); 329 void bnx_disable_nvram_access(struct bnx_softc *); 330 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 331 uint32_t); 332 int bnx_init_nvram(struct bnx_softc *); 333 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 334 int bnx_nvram_test(struct bnx_softc *); 335 #ifdef BNX_NVRAM_WRITE_SUPPORT 336 int bnx_enable_nvram_write(struct bnx_softc *); 337 void bnx_disable_nvram_write(struct bnx_softc *); 338 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 339 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 340 uint32_t); 341 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 342 #endif 343 344 /****************************************************************************/ 345 /* */ 346 /****************************************************************************/ 347 void bnx_get_media(struct bnx_softc *); 348 void bnx_init_media(struct bnx_softc *); 349 int bnx_dma_alloc(struct bnx_softc *); 350 void bnx_dma_free(struct bnx_softc *); 351 void bnx_release_resources(struct bnx_softc *); 352 353 /****************************************************************************/ 354 /* BNX Firmware Synchronization and Load */ 355 /****************************************************************************/ 356 int bnx_fw_sync(struct bnx_softc *, uint32_t); 357 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 358 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 359 struct fw_info *); 360 void bnx_init_cpus(struct bnx_softc *); 361 362 static void bnx_print_adapter_info(struct bnx_softc *); 363 static void bnx_probe_pci_caps(struct bnx_softc *); 364 void bnx_stop(struct ifnet *, int); 365 int bnx_reset(struct bnx_softc *, uint32_t); 366 int bnx_chipinit(struct bnx_softc *); 367 int bnx_blockinit(struct bnx_softc *); 368 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 369 uint16_t *, uint32_t *); 370 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 371 372 int bnx_init_tx_chain(struct bnx_softc *); 373 void bnx_init_tx_context(struct bnx_softc *); 374 int bnx_init_rx_chain(struct bnx_softc *); 375 void bnx_init_rx_context(struct bnx_softc *); 376 void bnx_free_rx_chain(struct bnx_softc *); 377 void bnx_free_tx_chain(struct bnx_softc *); 378 379 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 380 void bnx_start(struct ifnet *); 381 int bnx_ioctl(struct ifnet *, u_long, void *); 382 void bnx_watchdog(struct ifnet *); 383 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 384 int bnx_init(struct ifnet *); 385 386 void bnx_init_context(struct bnx_softc *); 387 void bnx_get_mac_addr(struct bnx_softc *); 388 void bnx_set_mac_addr(struct bnx_softc *); 389 void bnx_phy_intr(struct bnx_softc *); 390 void bnx_rx_intr(struct bnx_softc *); 391 void bnx_tx_intr(struct bnx_softc *); 392 void bnx_disable_intr(struct bnx_softc *); 393 void bnx_enable_intr(struct bnx_softc *); 394 395 int bnx_intr(void *); 396 void bnx_iff(struct bnx_softc *); 397 void bnx_stats_update(struct bnx_softc *); 398 void bnx_tick(void *); 399 400 struct pool *bnx_tx_pool = NULL; 401 void bnx_alloc_pkts(struct work *, void *); 402 403 /****************************************************************************/ 404 /* OpenBSD device dispatch table. */ 405 /****************************************************************************/ 406 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 407 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 408 409 /****************************************************************************/ 410 /* Device probe function. */ 411 /* */ 412 /* Compares the device to the driver's list of supported devices and */ 413 /* reports back to the OS whether this is the right driver for the device. */ 414 /* */ 415 /* Returns: */ 416 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 417 /****************************************************************************/ 418 static const struct bnx_product * 419 bnx_lookup(const struct pci_attach_args *pa) 420 { 421 int i; 422 pcireg_t subid; 423 424 for (i = 0; i < __arraycount(bnx_devices); i++) { 425 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 426 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 427 continue; 428 if (!bnx_devices[i].bp_subvendor) 429 return &bnx_devices[i]; 430 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 431 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 432 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 433 return &bnx_devices[i]; 434 } 435 436 return NULL; 437 } 438 static int 439 bnx_probe(device_t parent, cfdata_t match, void *aux) 440 { 441 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 442 443 if (bnx_lookup(pa) != NULL) 444 return 1; 445 446 return 0; 447 } 448 449 /****************************************************************************/ 450 /* PCI Capabilities Probe Function. */ 451 /* */ 452 /* Walks the PCI capabiites list for the device to find what features are */ 453 /* supported. */ 454 /* */ 455 /* Returns: */ 456 /* None. */ 457 /****************************************************************************/ 458 static void 459 bnx_print_adapter_info(struct bnx_softc *sc) 460 { 461 462 aprint_normal_dev(sc->bnx_dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 463 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 464 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 465 ? "Serdes " : "", sc->bnx_chipid); 466 467 /* Bus info. */ 468 if (sc->bnx_flags & BNX_PCIE_FLAG) { 469 aprint_normal_dev(sc->bnx_dev, "PCIe x%d ", 470 sc->link_width); 471 switch (sc->link_speed) { 472 case 1: aprint_normal("2.5Gbps\n"); break; 473 case 2: aprint_normal("5Gbps\n"); break; 474 default: aprint_normal("Unknown link speed\n"); 475 } 476 } else { 477 aprint_normal_dev(sc->bnx_dev, "PCI%s %dbit %dMHz\n", 478 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 479 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 480 sc->bus_speed_mhz); 481 } 482 483 aprint_normal_dev(sc->bnx_dev, 484 "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 485 sc->bnx_rx_quick_cons_trip_int, 486 sc->bnx_rx_quick_cons_trip, 487 sc->bnx_rx_ticks_int, 488 sc->bnx_rx_ticks, 489 sc->bnx_tx_quick_cons_trip_int, 490 sc->bnx_tx_quick_cons_trip, 491 sc->bnx_tx_ticks_int, 492 sc->bnx_tx_ticks); 493 } 494 495 496 /****************************************************************************/ 497 /* PCI Capabilities Probe Function. */ 498 /* */ 499 /* Walks the PCI capabiites list for the device to find what features are */ 500 /* supported. */ 501 /* */ 502 /* Returns: */ 503 /* None. */ 504 /****************************************************************************/ 505 static void 506 bnx_probe_pci_caps(struct bnx_softc *sc) 507 { 508 struct pci_attach_args *pa = &(sc->bnx_pa); 509 pcireg_t reg; 510 511 /* Check if PCI-X capability is enabled. */ 512 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 513 NULL) != 0) { 514 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 515 } 516 517 /* Check if PCIe capability is enabled. */ 518 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 519 NULL) != 0) { 520 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 521 reg + PCIE_LCSR); 522 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 523 "0x%08X\n", link_status); 524 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 525 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 526 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 527 sc->bnx_flags |= BNX_PCIE_FLAG; 528 } 529 530 /* Check if MSI capability is enabled. */ 531 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 532 NULL) != 0) 533 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 534 535 /* Check if MSI-X capability is enabled. */ 536 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 537 NULL) != 0) 538 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 539 } 540 541 542 /****************************************************************************/ 543 /* Device attach function. */ 544 /* */ 545 /* Allocates device resources, performs secondary chip identification, */ 546 /* resets and initializes the hardware, and initializes driver instance */ 547 /* variables. */ 548 /* */ 549 /* Returns: */ 550 /* 0 on success, positive value on failure. */ 551 /****************************************************************************/ 552 void 553 bnx_attach(device_t parent, device_t self, void *aux) 554 { 555 const struct bnx_product *bp; 556 struct bnx_softc *sc = device_private(self); 557 prop_dictionary_t dict; 558 struct pci_attach_args *pa = aux; 559 pci_chipset_tag_t pc = pa->pa_pc; 560 pci_intr_handle_t ih; 561 const char *intrstr = NULL; 562 uint32_t command; 563 struct ifnet *ifp; 564 uint32_t val; 565 int mii_flags = MIIF_FORCEANEG; 566 pcireg_t memtype; 567 char intrbuf[PCI_INTRSTR_LEN]; 568 569 if (bnx_tx_pool == NULL) { 570 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 571 if (bnx_tx_pool != NULL) { 572 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 573 0, 0, 0, "bnxpkts", NULL, IPL_NET); 574 } else { 575 aprint_error(": can't alloc bnx_tx_pool\n"); 576 return; 577 } 578 } 579 580 bp = bnx_lookup(pa); 581 if (bp == NULL) 582 panic("unknown device"); 583 584 sc->bnx_dev = self; 585 586 aprint_naive("\n"); 587 aprint_normal(": %s\n", bp->bp_name); 588 589 sc->bnx_pa = *pa; 590 591 /* 592 * Map control/status registers. 593 */ 594 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 595 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 596 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 597 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 598 599 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 600 aprint_error_dev(sc->bnx_dev, 601 "failed to enable memory mapping!\n"); 602 return; 603 } 604 605 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 606 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 607 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 608 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 609 return; 610 } 611 612 if (pci_intr_map(pa, &ih)) { 613 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 614 goto bnx_attach_fail; 615 } 616 617 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 618 619 /* 620 * Configure byte swap and enable indirect register access. 621 * Rely on CPU to do target byte swapping on big endian systems. 622 * Access to registers outside of PCI configurtion space are not 623 * valid until this is done. 624 */ 625 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 626 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 627 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 628 629 /* Save ASIC revsion info. */ 630 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 631 632 /* 633 * Find the base address for shared memory access. 634 * Newer versions of bootcode use a signature and offset 635 * while older versions use a fixed address. 636 */ 637 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 638 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 639 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 640 (sc->bnx_pa.pa_function << 2)); 641 else 642 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 643 644 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 645 646 /* Set initial device and PHY flags */ 647 sc->bnx_flags = 0; 648 sc->bnx_phy_flags = 0; 649 650 bnx_probe_pci_caps(sc); 651 652 /* Get PCI bus information (speed and type). */ 653 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 654 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 655 uint32_t clkreg; 656 657 sc->bnx_flags |= BNX_PCIX_FLAG; 658 659 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 660 661 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 662 switch (clkreg) { 663 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 664 sc->bus_speed_mhz = 133; 665 break; 666 667 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 668 sc->bus_speed_mhz = 100; 669 break; 670 671 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 672 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 673 sc->bus_speed_mhz = 66; 674 break; 675 676 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 677 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 678 sc->bus_speed_mhz = 50; 679 break; 680 681 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 682 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 683 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 684 sc->bus_speed_mhz = 33; 685 break; 686 } 687 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 688 sc->bus_speed_mhz = 66; 689 else 690 sc->bus_speed_mhz = 33; 691 692 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 693 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 694 695 /* Reset the controller. */ 696 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 697 goto bnx_attach_fail; 698 699 /* Initialize the controller. */ 700 if (bnx_chipinit(sc)) { 701 aprint_error_dev(sc->bnx_dev, 702 "Controller initialization failed!\n"); 703 goto bnx_attach_fail; 704 } 705 706 /* Perform NVRAM test. */ 707 if (bnx_nvram_test(sc)) { 708 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 709 goto bnx_attach_fail; 710 } 711 712 /* Fetch the permanent Ethernet MAC address. */ 713 bnx_get_mac_addr(sc); 714 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 715 ether_sprintf(sc->eaddr)); 716 717 /* 718 * Trip points control how many BDs 719 * should be ready before generating an 720 * interrupt while ticks control how long 721 * a BD can sit in the chain before 722 * generating an interrupt. Set the default 723 * values for the RX and TX rings. 724 */ 725 726 #ifdef BNX_DEBUG 727 /* Force more frequent interrupts. */ 728 sc->bnx_tx_quick_cons_trip_int = 1; 729 sc->bnx_tx_quick_cons_trip = 1; 730 sc->bnx_tx_ticks_int = 0; 731 sc->bnx_tx_ticks = 0; 732 733 sc->bnx_rx_quick_cons_trip_int = 1; 734 sc->bnx_rx_quick_cons_trip = 1; 735 sc->bnx_rx_ticks_int = 0; 736 sc->bnx_rx_ticks = 0; 737 #else 738 sc->bnx_tx_quick_cons_trip_int = 20; 739 sc->bnx_tx_quick_cons_trip = 20; 740 sc->bnx_tx_ticks_int = 80; 741 sc->bnx_tx_ticks = 80; 742 743 sc->bnx_rx_quick_cons_trip_int = 6; 744 sc->bnx_rx_quick_cons_trip = 6; 745 sc->bnx_rx_ticks_int = 18; 746 sc->bnx_rx_ticks = 18; 747 #endif 748 749 /* Update statistics once every second. */ 750 sc->bnx_stats_ticks = 1000000 & 0xffff00; 751 752 /* Find the media type for the adapter. */ 753 bnx_get_media(sc); 754 755 /* 756 * Store config data needed by the PHY driver for 757 * backplane applications 758 */ 759 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 760 BNX_SHARED_HW_CFG_CONFIG); 761 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 762 BNX_PORT_HW_CFG_CONFIG); 763 764 /* Allocate DMA memory resources. */ 765 sc->bnx_dmatag = pa->pa_dmat; 766 if (bnx_dma_alloc(sc)) { 767 aprint_error_dev(sc->bnx_dev, 768 "DMA resource allocation failed!\n"); 769 goto bnx_attach_fail; 770 } 771 772 /* Initialize the ifnet interface. */ 773 ifp = &sc->bnx_ec.ec_if; 774 ifp->if_softc = sc; 775 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 776 ifp->if_ioctl = bnx_ioctl; 777 ifp->if_stop = bnx_stop; 778 ifp->if_start = bnx_start; 779 ifp->if_init = bnx_init; 780 ifp->if_timer = 0; 781 ifp->if_watchdog = bnx_watchdog; 782 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 783 IFQ_SET_READY(&ifp->if_snd); 784 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 785 786 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 787 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 788 789 ifp->if_capabilities |= 790 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 791 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 792 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 793 794 /* Hookup IRQ last. */ 795 sc->bnx_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bnx_intr, 796 sc, device_xname(self)); 797 if (sc->bnx_intrhand == NULL) { 798 aprint_error_dev(self, "couldn't establish interrupt"); 799 if (intrstr != NULL) 800 aprint_error(" at %s", intrstr); 801 aprint_error("\n"); 802 goto bnx_attach_fail; 803 } 804 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 805 806 /* create workqueue to handle packet allocations */ 807 if (workqueue_create(&sc->bnx_wq, device_xname(self), 808 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 809 aprint_error_dev(self, "failed to create workqueue\n"); 810 goto bnx_attach_fail; 811 } 812 813 sc->bnx_mii.mii_ifp = ifp; 814 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 815 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 816 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 817 818 /* Handle any special PHY initialization for SerDes PHYs. */ 819 bnx_init_media(sc); 820 821 sc->bnx_ec.ec_mii = &sc->bnx_mii; 822 ifmedia_init(&sc->bnx_mii.mii_media, 0, ether_mediachange, 823 bnx_ifmedia_sts); 824 825 /* set phyflags and chipid before mii_attach() */ 826 dict = device_properties(self); 827 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 828 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 829 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 830 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 831 832 /* Print some useful adapter info */ 833 bnx_print_adapter_info(sc); 834 835 mii_flags |= MIIF_DOPAUSE; 836 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 837 mii_flags |= MIIF_HAVEFIBER; 838 mii_attach(self, &sc->bnx_mii, 0xffffffff, 839 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 840 841 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 842 aprint_error_dev(self, "no PHY found!\n"); 843 ifmedia_add(&sc->bnx_mii.mii_media, 844 IFM_ETHER|IFM_MANUAL, 0, NULL); 845 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_MANUAL); 846 } else 847 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_AUTO); 848 849 /* Attach to the Ethernet interface list. */ 850 if_attach(ifp); 851 if_deferred_start_init(ifp, NULL); 852 ether_ifattach(ifp,sc->eaddr); 853 854 callout_init(&sc->bnx_timeout, 0); 855 856 if (pmf_device_register(self, NULL, NULL)) 857 pmf_class_network_register(self, ifp); 858 else 859 aprint_error_dev(self, "couldn't establish power handler\n"); 860 861 /* Print some important debugging info. */ 862 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 863 864 goto bnx_attach_exit; 865 866 bnx_attach_fail: 867 bnx_release_resources(sc); 868 869 bnx_attach_exit: 870 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 871 } 872 873 /****************************************************************************/ 874 /* Device detach function. */ 875 /* */ 876 /* Stops the controller, resets the controller, and releases resources. */ 877 /* */ 878 /* Returns: */ 879 /* 0 on success, positive value on failure. */ 880 /****************************************************************************/ 881 int 882 bnx_detach(device_t dev, int flags) 883 { 884 int s; 885 struct bnx_softc *sc; 886 struct ifnet *ifp; 887 888 sc = device_private(dev); 889 ifp = &sc->bnx_ec.ec_if; 890 891 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 892 893 /* Stop and reset the controller. */ 894 s = splnet(); 895 bnx_stop(ifp, 1); 896 splx(s); 897 898 pmf_device_deregister(dev); 899 callout_destroy(&sc->bnx_timeout); 900 ether_ifdetach(ifp); 901 workqueue_destroy(sc->bnx_wq); 902 903 /* Delete all remaining media. */ 904 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 905 906 if_detach(ifp); 907 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 908 909 /* Release all remaining resources. */ 910 bnx_release_resources(sc); 911 912 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 913 914 return 0; 915 } 916 917 /****************************************************************************/ 918 /* Indirect register read. */ 919 /* */ 920 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 921 /* configuration space. Using this mechanism avoids issues with posted */ 922 /* reads but is much slower than memory-mapped I/O. */ 923 /* */ 924 /* Returns: */ 925 /* The value of the register. */ 926 /****************************************************************************/ 927 uint32_t 928 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 929 { 930 struct pci_attach_args *pa = &(sc->bnx_pa); 931 932 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 933 offset); 934 #ifdef BNX_DEBUG 935 { 936 uint32_t val; 937 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 938 BNX_PCICFG_REG_WINDOW); 939 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 940 "val = 0x%08X\n", __func__, offset, val); 941 return val; 942 } 943 #else 944 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 945 #endif 946 } 947 948 /****************************************************************************/ 949 /* Indirect register write. */ 950 /* */ 951 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 952 /* configuration space. Using this mechanism avoids issues with posted */ 953 /* writes but is muchh slower than memory-mapped I/O. */ 954 /* */ 955 /* Returns: */ 956 /* Nothing. */ 957 /****************************************************************************/ 958 void 959 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 960 { 961 struct pci_attach_args *pa = &(sc->bnx_pa); 962 963 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 964 __func__, offset, val); 965 966 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 967 offset); 968 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 969 } 970 971 /****************************************************************************/ 972 /* Context memory write. */ 973 /* */ 974 /* The NetXtreme II controller uses context memory to track connection */ 975 /* information for L2 and higher network protocols. */ 976 /* */ 977 /* Returns: */ 978 /* Nothing. */ 979 /****************************************************************************/ 980 void 981 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 982 uint32_t ctx_val) 983 { 984 uint32_t idx, offset = ctx_offset + cid_addr; 985 uint32_t val, retry_cnt = 5; 986 987 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 988 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 989 REG_WR(sc, BNX_CTX_CTX_CTRL, 990 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 991 992 for (idx = 0; idx < retry_cnt; idx++) { 993 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 994 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 995 break; 996 DELAY(5); 997 } 998 999 #if 0 1000 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1001 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1002 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1003 __FILE__, __LINE__, cid_addr, ctx_offset); 1004 #endif 1005 1006 } else { 1007 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1008 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1009 } 1010 } 1011 1012 /****************************************************************************/ 1013 /* PHY register read. */ 1014 /* */ 1015 /* Implements register reads on the MII bus. */ 1016 /* */ 1017 /* Returns: */ 1018 /* The value of the register. */ 1019 /****************************************************************************/ 1020 int 1021 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1022 { 1023 struct bnx_softc *sc = device_private(dev); 1024 uint32_t data; 1025 int i, rv = 0; 1026 1027 /* Make sure we are accessing the correct PHY address. */ 1028 if (phy != sc->bnx_phy_addr) { 1029 DBPRINT(sc, BNX_VERBOSE, 1030 "Invalid PHY address %d for PHY read!\n", phy); 1031 return -1; 1032 } 1033 1034 /* 1035 * The BCM5709S PHY is an IEEE Clause 45 PHY 1036 * with special mappings to work with IEEE 1037 * Clause 22 register accesses. 1038 */ 1039 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1040 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1041 reg += 0x10; 1042 } 1043 1044 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1045 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1046 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1047 1048 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1049 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1050 1051 DELAY(40); 1052 } 1053 1054 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1055 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1056 BNX_EMAC_MDIO_COMM_START_BUSY; 1057 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1058 1059 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1060 DELAY(10); 1061 1062 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1063 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1064 DELAY(5); 1065 1066 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1067 data &= BNX_EMAC_MDIO_COMM_DATA; 1068 1069 break; 1070 } 1071 } 1072 1073 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1074 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1075 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1076 rv = ETIMEDOUT; 1077 } else { 1078 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1079 *val = data & 0xffff; 1080 1081 DBPRINT(sc, BNX_EXCESSIVE, 1082 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1083 phy, (uint16_t) reg & 0xffff, *val); 1084 } 1085 1086 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1087 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1088 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1089 1090 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1091 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1092 1093 DELAY(40); 1094 } 1095 1096 return rv; 1097 } 1098 1099 /****************************************************************************/ 1100 /* PHY register write. */ 1101 /* */ 1102 /* Implements register writes on the MII bus. */ 1103 /* */ 1104 /* Returns: */ 1105 /* The value of the register. */ 1106 /****************************************************************************/ 1107 int 1108 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1109 { 1110 struct bnx_softc *sc = device_private(dev); 1111 uint32_t val1; 1112 int i, rv = 0; 1113 1114 /* Make sure we are accessing the correct PHY address. */ 1115 if (phy != sc->bnx_phy_addr) { 1116 DBPRINT(sc, BNX_WARN, 1117 "Invalid PHY address %d for PHY write!\n", phy); 1118 return -1; 1119 } 1120 1121 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1122 "val = 0x%04hX\n", __func__, 1123 phy, (uint16_t) reg & 0xffff, val); 1124 1125 /* 1126 * The BCM5709S PHY is an IEEE Clause 45 PHY 1127 * with special mappings to work with IEEE 1128 * Clause 22 register accesses. 1129 */ 1130 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1131 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1132 reg += 0x10; 1133 } 1134 1135 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1136 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1137 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1138 1139 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1140 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1141 1142 DELAY(40); 1143 } 1144 1145 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1146 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1147 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1148 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1149 1150 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1151 DELAY(10); 1152 1153 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1154 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1155 DELAY(5); 1156 break; 1157 } 1158 } 1159 1160 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1161 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1162 __LINE__); 1163 rv = ETIMEDOUT; 1164 } 1165 1166 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1167 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1168 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1169 1170 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1171 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1172 1173 DELAY(40); 1174 } 1175 1176 return rv; 1177 } 1178 1179 /****************************************************************************/ 1180 /* MII bus status change. */ 1181 /* */ 1182 /* Called by the MII bus driver when the PHY establishes link to set the */ 1183 /* MAC interface registers. */ 1184 /* */ 1185 /* Returns: */ 1186 /* Nothing. */ 1187 /****************************************************************************/ 1188 void 1189 bnx_miibus_statchg(struct ifnet *ifp) 1190 { 1191 struct bnx_softc *sc = ifp->if_softc; 1192 struct mii_data *mii = &sc->bnx_mii; 1193 uint32_t rx_mode = sc->rx_mode; 1194 int val; 1195 1196 val = REG_RD(sc, BNX_EMAC_MODE); 1197 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1198 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1199 BNX_EMAC_MODE_25G); 1200 1201 /* 1202 * Get flow control negotiation result. 1203 */ 1204 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1205 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1206 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1207 mii->mii_media_active &= ~IFM_ETH_FMASK; 1208 } 1209 1210 /* Set MII or GMII interface based on the speed 1211 * negotiated by the PHY. 1212 */ 1213 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1214 case IFM_10_T: 1215 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1216 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1217 val |= BNX_EMAC_MODE_PORT_MII_10; 1218 break; 1219 } 1220 /* FALLTHROUGH */ 1221 case IFM_100_TX: 1222 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1223 val |= BNX_EMAC_MODE_PORT_MII; 1224 break; 1225 case IFM_2500_SX: 1226 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1227 val |= BNX_EMAC_MODE_25G; 1228 /* FALLTHROUGH */ 1229 case IFM_1000_T: 1230 case IFM_1000_SX: 1231 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1232 val |= BNX_EMAC_MODE_PORT_GMII; 1233 break; 1234 default: 1235 val |= BNX_EMAC_MODE_PORT_GMII; 1236 break; 1237 } 1238 1239 /* Set half or full duplex based on the duplicity 1240 * negotiated by the PHY. 1241 */ 1242 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1243 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1244 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1245 } else { 1246 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1247 } 1248 1249 REG_WR(sc, BNX_EMAC_MODE, val); 1250 1251 /* 1252 * 802.3x flow control 1253 */ 1254 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1255 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1256 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1257 } else { 1258 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1259 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1260 } 1261 1262 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1263 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1264 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1265 } else { 1266 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1267 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1268 } 1269 1270 /* Only make changes if the recive mode has actually changed. */ 1271 if (rx_mode != sc->rx_mode) { 1272 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1273 rx_mode); 1274 1275 sc->rx_mode = rx_mode; 1276 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1277 1278 bnx_init_rx_context(sc); 1279 } 1280 } 1281 1282 /****************************************************************************/ 1283 /* Acquire NVRAM lock. */ 1284 /* */ 1285 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1286 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1287 /* for use by the driver. */ 1288 /* */ 1289 /* Returns: */ 1290 /* 0 on success, positive value on failure. */ 1291 /****************************************************************************/ 1292 int 1293 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1294 { 1295 uint32_t val; 1296 int j; 1297 1298 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1299 1300 /* Request access to the flash interface. */ 1301 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1302 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1303 val = REG_RD(sc, BNX_NVM_SW_ARB); 1304 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1305 break; 1306 1307 DELAY(5); 1308 } 1309 1310 if (j >= NVRAM_TIMEOUT_COUNT) { 1311 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1312 return EBUSY; 1313 } 1314 1315 return 0; 1316 } 1317 1318 /****************************************************************************/ 1319 /* Release NVRAM lock. */ 1320 /* */ 1321 /* When the caller is finished accessing NVRAM the lock must be released. */ 1322 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1323 /* for use by the driver. */ 1324 /* */ 1325 /* Returns: */ 1326 /* 0 on success, positive value on failure. */ 1327 /****************************************************************************/ 1328 int 1329 bnx_release_nvram_lock(struct bnx_softc *sc) 1330 { 1331 int j; 1332 uint32_t val; 1333 1334 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1335 1336 /* Relinquish nvram interface. */ 1337 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1338 1339 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1340 val = REG_RD(sc, BNX_NVM_SW_ARB); 1341 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1342 break; 1343 1344 DELAY(5); 1345 } 1346 1347 if (j >= NVRAM_TIMEOUT_COUNT) { 1348 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1349 return EBUSY; 1350 } 1351 1352 return 0; 1353 } 1354 1355 #ifdef BNX_NVRAM_WRITE_SUPPORT 1356 /****************************************************************************/ 1357 /* Enable NVRAM write access. */ 1358 /* */ 1359 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1360 /* */ 1361 /* Returns: */ 1362 /* 0 on success, positive value on failure. */ 1363 /****************************************************************************/ 1364 int 1365 bnx_enable_nvram_write(struct bnx_softc *sc) 1366 { 1367 uint32_t val; 1368 1369 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1370 1371 val = REG_RD(sc, BNX_MISC_CFG); 1372 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1373 1374 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1375 int j; 1376 1377 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1378 REG_WR(sc, BNX_NVM_COMMAND, 1379 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1380 1381 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1382 DELAY(5); 1383 1384 val = REG_RD(sc, BNX_NVM_COMMAND); 1385 if (val & BNX_NVM_COMMAND_DONE) 1386 break; 1387 } 1388 1389 if (j >= NVRAM_TIMEOUT_COUNT) { 1390 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1391 return EBUSY; 1392 } 1393 } 1394 1395 return 0; 1396 } 1397 1398 /****************************************************************************/ 1399 /* Disable NVRAM write access. */ 1400 /* */ 1401 /* When the caller is finished writing to NVRAM write access must be */ 1402 /* disabled. */ 1403 /* */ 1404 /* Returns: */ 1405 /* Nothing. */ 1406 /****************************************************************************/ 1407 void 1408 bnx_disable_nvram_write(struct bnx_softc *sc) 1409 { 1410 uint32_t val; 1411 1412 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1413 1414 val = REG_RD(sc, BNX_MISC_CFG); 1415 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1416 } 1417 #endif 1418 1419 /****************************************************************************/ 1420 /* Enable NVRAM access. */ 1421 /* */ 1422 /* Before accessing NVRAM for read or write operations the caller must */ 1423 /* enabled NVRAM access. */ 1424 /* */ 1425 /* Returns: */ 1426 /* Nothing. */ 1427 /****************************************************************************/ 1428 void 1429 bnx_enable_nvram_access(struct bnx_softc *sc) 1430 { 1431 uint32_t val; 1432 1433 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1434 1435 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1436 /* Enable both bits, even on read. */ 1437 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1438 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1439 } 1440 1441 /****************************************************************************/ 1442 /* Disable NVRAM access. */ 1443 /* */ 1444 /* When the caller is finished accessing NVRAM access must be disabled. */ 1445 /* */ 1446 /* Returns: */ 1447 /* Nothing. */ 1448 /****************************************************************************/ 1449 void 1450 bnx_disable_nvram_access(struct bnx_softc *sc) 1451 { 1452 uint32_t val; 1453 1454 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1455 1456 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1457 1458 /* Disable both bits, even after read. */ 1459 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1460 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1461 } 1462 1463 #ifdef BNX_NVRAM_WRITE_SUPPORT 1464 /****************************************************************************/ 1465 /* Erase NVRAM page before writing. */ 1466 /* */ 1467 /* Non-buffered flash parts require that a page be erased before it is */ 1468 /* written. */ 1469 /* */ 1470 /* Returns: */ 1471 /* 0 on success, positive value on failure. */ 1472 /****************************************************************************/ 1473 int 1474 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1475 { 1476 uint32_t cmd; 1477 int j; 1478 1479 /* Buffered flash doesn't require an erase. */ 1480 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1481 return 0; 1482 1483 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1484 1485 /* Build an erase command. */ 1486 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1487 BNX_NVM_COMMAND_DOIT; 1488 1489 /* 1490 * Clear the DONE bit separately, set the NVRAM address to erase, 1491 * and issue the erase command. 1492 */ 1493 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1494 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1495 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1496 1497 /* Wait for completion. */ 1498 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1499 uint32_t val; 1500 1501 DELAY(5); 1502 1503 val = REG_RD(sc, BNX_NVM_COMMAND); 1504 if (val & BNX_NVM_COMMAND_DONE) 1505 break; 1506 } 1507 1508 if (j >= NVRAM_TIMEOUT_COUNT) { 1509 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1510 return EBUSY; 1511 } 1512 1513 return 0; 1514 } 1515 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1516 1517 /****************************************************************************/ 1518 /* Read a dword (32 bits) from NVRAM. */ 1519 /* */ 1520 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1521 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1522 /* */ 1523 /* Returns: */ 1524 /* 0 on success and the 32 bit value read, positive value on failure. */ 1525 /****************************************************************************/ 1526 int 1527 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1528 uint8_t *ret_val, uint32_t cmd_flags) 1529 { 1530 uint32_t cmd; 1531 int i, rc = 0; 1532 1533 /* Build the command word. */ 1534 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1535 1536 /* Calculate the offset for buffered flash if translation is used. */ 1537 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1538 offset = ((offset / sc->bnx_flash_info->page_size) << 1539 sc->bnx_flash_info->page_bits) + 1540 (offset % sc->bnx_flash_info->page_size); 1541 } 1542 1543 /* 1544 * Clear the DONE bit separately, set the address to read, 1545 * and issue the read. 1546 */ 1547 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1548 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1549 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1550 1551 /* Wait for completion. */ 1552 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1553 uint32_t val; 1554 1555 DELAY(5); 1556 1557 val = REG_RD(sc, BNX_NVM_COMMAND); 1558 if (val & BNX_NVM_COMMAND_DONE) { 1559 val = REG_RD(sc, BNX_NVM_READ); 1560 1561 val = bnx_be32toh(val); 1562 memcpy(ret_val, &val, 4); 1563 break; 1564 } 1565 } 1566 1567 /* Check for errors. */ 1568 if (i >= NVRAM_TIMEOUT_COUNT) { 1569 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1570 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1571 rc = EBUSY; 1572 } 1573 1574 return rc; 1575 } 1576 1577 #ifdef BNX_NVRAM_WRITE_SUPPORT 1578 /****************************************************************************/ 1579 /* Write a dword (32 bits) to NVRAM. */ 1580 /* */ 1581 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1582 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1583 /* enabled NVRAM write access. */ 1584 /* */ 1585 /* Returns: */ 1586 /* 0 on success, positive value on failure. */ 1587 /****************************************************************************/ 1588 int 1589 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1590 uint32_t cmd_flags) 1591 { 1592 uint32_t cmd, val32; 1593 int j; 1594 1595 /* Build the command word. */ 1596 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1597 1598 /* Calculate the offset for buffered flash if translation is used. */ 1599 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1600 offset = ((offset / sc->bnx_flash_info->page_size) << 1601 sc->bnx_flash_info->page_bits) + 1602 (offset % sc->bnx_flash_info->page_size); 1603 } 1604 1605 /* 1606 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1607 * set the NVRAM address to write, and issue the write command 1608 */ 1609 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1610 memcpy(&val32, val, 4); 1611 val32 = htobe32(val32); 1612 REG_WR(sc, BNX_NVM_WRITE, val32); 1613 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1614 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1615 1616 /* Wait for completion. */ 1617 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1618 DELAY(5); 1619 1620 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1621 break; 1622 } 1623 if (j >= NVRAM_TIMEOUT_COUNT) { 1624 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1625 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1626 return EBUSY; 1627 } 1628 1629 return 0; 1630 } 1631 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1632 1633 /****************************************************************************/ 1634 /* Initialize NVRAM access. */ 1635 /* */ 1636 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1637 /* access that device. */ 1638 /* */ 1639 /* Returns: */ 1640 /* 0 on success, positive value on failure. */ 1641 /****************************************************************************/ 1642 int 1643 bnx_init_nvram(struct bnx_softc *sc) 1644 { 1645 uint32_t val; 1646 int j, entry_count, rc = 0; 1647 struct flash_spec *flash; 1648 1649 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1650 1651 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1652 sc->bnx_flash_info = &flash_5709; 1653 goto bnx_init_nvram_get_flash_size; 1654 } 1655 1656 /* Determine the selected interface. */ 1657 val = REG_RD(sc, BNX_NVM_CFG1); 1658 1659 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1660 1661 /* 1662 * Flash reconfiguration is required to support additional 1663 * NVRAM devices not directly supported in hardware. 1664 * Check if the flash interface was reconfigured 1665 * by the bootcode. 1666 */ 1667 1668 if (val & 0x40000000) { 1669 /* Flash interface reconfigured by bootcode. */ 1670 1671 DBPRINT(sc,BNX_INFO_LOAD, 1672 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1673 1674 for (j = 0, flash = &flash_table[0]; j < entry_count; 1675 j++, flash++) { 1676 if ((val & FLASH_BACKUP_STRAP_MASK) == 1677 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1678 sc->bnx_flash_info = flash; 1679 break; 1680 } 1681 } 1682 } else { 1683 /* Flash interface not yet reconfigured. */ 1684 uint32_t mask; 1685 1686 DBPRINT(sc,BNX_INFO_LOAD, 1687 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1688 1689 if (val & (1 << 23)) 1690 mask = FLASH_BACKUP_STRAP_MASK; 1691 else 1692 mask = FLASH_STRAP_MASK; 1693 1694 /* Look for the matching NVRAM device configuration data. */ 1695 for (j = 0, flash = &flash_table[0]; j < entry_count; 1696 j++, flash++) { 1697 /* Check if the dev matches any of the known devices. */ 1698 if ((val & mask) == (flash->strapping & mask)) { 1699 /* Found a device match. */ 1700 sc->bnx_flash_info = flash; 1701 1702 /* Request access to the flash interface. */ 1703 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1704 return rc; 1705 1706 /* Reconfigure the flash interface. */ 1707 bnx_enable_nvram_access(sc); 1708 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1709 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1710 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1711 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1712 bnx_disable_nvram_access(sc); 1713 bnx_release_nvram_lock(sc); 1714 1715 break; 1716 } 1717 } 1718 } 1719 1720 /* Check if a matching device was found. */ 1721 if (j == entry_count) { 1722 sc->bnx_flash_info = NULL; 1723 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1724 __FILE__, __LINE__); 1725 rc = ENODEV; 1726 } 1727 1728 bnx_init_nvram_get_flash_size: 1729 /* Write the flash config data to the shared memory interface. */ 1730 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1731 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1732 if (val) 1733 sc->bnx_flash_size = val; 1734 else 1735 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1736 1737 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1738 "0x%08X\n", sc->bnx_flash_info->total_size); 1739 1740 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1741 1742 return rc; 1743 } 1744 1745 /****************************************************************************/ 1746 /* Read an arbitrary range of data from NVRAM. */ 1747 /* */ 1748 /* Prepares the NVRAM interface for access and reads the requested data */ 1749 /* into the supplied buffer. */ 1750 /* */ 1751 /* Returns: */ 1752 /* 0 on success and the data read, positive value on failure. */ 1753 /****************************************************************************/ 1754 int 1755 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1756 int buf_size) 1757 { 1758 int rc = 0; 1759 uint32_t cmd_flags, offset32, len32, extra; 1760 1761 if (buf_size == 0) 1762 return 0; 1763 1764 /* Request access to the flash interface. */ 1765 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1766 return rc; 1767 1768 /* Enable access to flash interface */ 1769 bnx_enable_nvram_access(sc); 1770 1771 len32 = buf_size; 1772 offset32 = offset; 1773 extra = 0; 1774 1775 cmd_flags = 0; 1776 1777 if (offset32 & 3) { 1778 uint8_t buf[4]; 1779 uint32_t pre_len; 1780 1781 offset32 &= ~3; 1782 pre_len = 4 - (offset & 3); 1783 1784 if (pre_len >= len32) { 1785 pre_len = len32; 1786 cmd_flags = 1787 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1788 } else 1789 cmd_flags = BNX_NVM_COMMAND_FIRST; 1790 1791 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1792 1793 if (rc) 1794 return rc; 1795 1796 memcpy(ret_buf, buf + (offset & 3), pre_len); 1797 1798 offset32 += 4; 1799 ret_buf += pre_len; 1800 len32 -= pre_len; 1801 } 1802 1803 if (len32 & 3) { 1804 extra = 4 - (len32 & 3); 1805 len32 = (len32 + 4) & ~3; 1806 } 1807 1808 if (len32 == 4) { 1809 uint8_t buf[4]; 1810 1811 if (cmd_flags) 1812 cmd_flags = BNX_NVM_COMMAND_LAST; 1813 else 1814 cmd_flags = 1815 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1816 1817 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1818 1819 memcpy(ret_buf, buf, 4 - extra); 1820 } else if (len32 > 0) { 1821 uint8_t buf[4]; 1822 1823 /* Read the first word. */ 1824 if (cmd_flags) 1825 cmd_flags = 0; 1826 else 1827 cmd_flags = BNX_NVM_COMMAND_FIRST; 1828 1829 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1830 1831 /* Advance to the next dword. */ 1832 offset32 += 4; 1833 ret_buf += 4; 1834 len32 -= 4; 1835 1836 while (len32 > 4 && rc == 0) { 1837 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1838 1839 /* Advance to the next dword. */ 1840 offset32 += 4; 1841 ret_buf += 4; 1842 len32 -= 4; 1843 } 1844 1845 if (rc) 1846 return rc; 1847 1848 cmd_flags = BNX_NVM_COMMAND_LAST; 1849 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1850 1851 memcpy(ret_buf, buf, 4 - extra); 1852 } 1853 1854 /* Disable access to flash interface and release the lock. */ 1855 bnx_disable_nvram_access(sc); 1856 bnx_release_nvram_lock(sc); 1857 1858 return rc; 1859 } 1860 1861 #ifdef BNX_NVRAM_WRITE_SUPPORT 1862 /****************************************************************************/ 1863 /* Write an arbitrary range of data from NVRAM. */ 1864 /* */ 1865 /* Prepares the NVRAM interface for write access and writes the requested */ 1866 /* data from the supplied buffer. The caller is responsible for */ 1867 /* calculating any appropriate CRCs. */ 1868 /* */ 1869 /* Returns: */ 1870 /* 0 on success, positive value on failure. */ 1871 /****************************************************************************/ 1872 int 1873 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1874 int buf_size) 1875 { 1876 uint32_t written, offset32, len32; 1877 uint8_t *buf, start[4], end[4]; 1878 int rc = 0; 1879 int align_start, align_end; 1880 1881 buf = data_buf; 1882 offset32 = offset; 1883 len32 = buf_size; 1884 align_start = align_end = 0; 1885 1886 if ((align_start = (offset32 & 3))) { 1887 offset32 &= ~3; 1888 len32 += align_start; 1889 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1890 return rc; 1891 } 1892 1893 if (len32 & 3) { 1894 if ((len32 > 4) || !align_start) { 1895 align_end = 4 - (len32 & 3); 1896 len32 += align_end; 1897 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1898 end, 4))) 1899 return rc; 1900 } 1901 } 1902 1903 if (align_start || align_end) { 1904 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1905 if (buf == 0) 1906 return ENOMEM; 1907 1908 if (align_start) 1909 memcpy(buf, start, 4); 1910 1911 if (align_end) 1912 memcpy(buf + len32 - 4, end, 4); 1913 1914 memcpy(buf + align_start, data_buf, buf_size); 1915 } 1916 1917 written = 0; 1918 while ((written < len32) && (rc == 0)) { 1919 uint32_t page_start, page_end, data_start, data_end; 1920 uint32_t addr, cmd_flags; 1921 int i; 1922 uint8_t flash_buffer[264]; 1923 1924 /* Find the page_start addr */ 1925 page_start = offset32 + written; 1926 page_start -= (page_start % sc->bnx_flash_info->page_size); 1927 /* Find the page_end addr */ 1928 page_end = page_start + sc->bnx_flash_info->page_size; 1929 /* Find the data_start addr */ 1930 data_start = (written == 0) ? offset32 : page_start; 1931 /* Find the data_end addr */ 1932 data_end = (page_end > offset32 + len32) ? 1933 (offset32 + len32) : page_end; 1934 1935 /* Request access to the flash interface. */ 1936 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1937 goto nvram_write_end; 1938 1939 /* Enable access to flash interface */ 1940 bnx_enable_nvram_access(sc); 1941 1942 cmd_flags = BNX_NVM_COMMAND_FIRST; 1943 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1944 int j; 1945 1946 /* Read the whole page into the buffer 1947 * (non-buffer flash only) */ 1948 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1949 if (j == (sc->bnx_flash_info->page_size - 4)) 1950 cmd_flags |= BNX_NVM_COMMAND_LAST; 1951 1952 rc = bnx_nvram_read_dword(sc, 1953 page_start + j, 1954 &flash_buffer[j], 1955 cmd_flags); 1956 1957 if (rc) 1958 goto nvram_write_end; 1959 1960 cmd_flags = 0; 1961 } 1962 } 1963 1964 /* Enable writes to flash interface (unlock write-protect) */ 1965 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1966 goto nvram_write_end; 1967 1968 /* Erase the page */ 1969 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1970 goto nvram_write_end; 1971 1972 /* Re-enable the write again for the actual write */ 1973 bnx_enable_nvram_write(sc); 1974 1975 /* Loop to write back the buffer data from page_start to 1976 * data_start */ 1977 i = 0; 1978 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1979 for (addr = page_start; addr < data_start; 1980 addr += 4, i += 4) { 1981 1982 rc = bnx_nvram_write_dword(sc, addr, 1983 &flash_buffer[i], cmd_flags); 1984 1985 if (rc != 0) 1986 goto nvram_write_end; 1987 1988 cmd_flags = 0; 1989 } 1990 } 1991 1992 /* Loop to write the new data from data_start to data_end */ 1993 for (addr = data_start; addr < data_end; addr += 4, i++) { 1994 if ((addr == page_end - 4) || 1995 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1996 && (addr == data_end - 4))) { 1997 1998 cmd_flags |= BNX_NVM_COMMAND_LAST; 1999 } 2000 2001 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2002 2003 if (rc != 0) 2004 goto nvram_write_end; 2005 2006 cmd_flags = 0; 2007 buf += 4; 2008 } 2009 2010 /* Loop to write back the buffer data from data_end 2011 * to page_end */ 2012 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2013 for (addr = data_end; addr < page_end; 2014 addr += 4, i += 4) { 2015 2016 if (addr == page_end-4) 2017 cmd_flags = BNX_NVM_COMMAND_LAST; 2018 2019 rc = bnx_nvram_write_dword(sc, addr, 2020 &flash_buffer[i], cmd_flags); 2021 2022 if (rc != 0) 2023 goto nvram_write_end; 2024 2025 cmd_flags = 0; 2026 } 2027 } 2028 2029 /* Disable writes to flash interface (lock write-protect) */ 2030 bnx_disable_nvram_write(sc); 2031 2032 /* Disable access to flash interface */ 2033 bnx_disable_nvram_access(sc); 2034 bnx_release_nvram_lock(sc); 2035 2036 /* Increment written */ 2037 written += data_end - data_start; 2038 } 2039 2040 nvram_write_end: 2041 if (align_start || align_end) 2042 free(buf, M_DEVBUF); 2043 2044 return rc; 2045 } 2046 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2047 2048 /****************************************************************************/ 2049 /* Verifies that NVRAM is accessible and contains valid data. */ 2050 /* */ 2051 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2052 /* correct. */ 2053 /* */ 2054 /* Returns: */ 2055 /* 0 on success, positive value on failure. */ 2056 /****************************************************************************/ 2057 int 2058 bnx_nvram_test(struct bnx_softc *sc) 2059 { 2060 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2061 uint8_t *data = (uint8_t *) buf; 2062 int rc = 0; 2063 uint32_t magic, csum; 2064 2065 /* 2066 * Check that the device NVRAM is valid by reading 2067 * the magic value at offset 0. 2068 */ 2069 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2070 goto bnx_nvram_test_done; 2071 2072 magic = bnx_be32toh(buf[0]); 2073 if (magic != BNX_NVRAM_MAGIC) { 2074 rc = ENODEV; 2075 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2076 "Expected: 0x%08X, Found: 0x%08X\n", 2077 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2078 goto bnx_nvram_test_done; 2079 } 2080 2081 /* 2082 * Verify that the device NVRAM includes valid 2083 * configuration data. 2084 */ 2085 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2086 goto bnx_nvram_test_done; 2087 2088 csum = ether_crc32_le(data, 0x100); 2089 if (csum != BNX_CRC32_RESIDUAL) { 2090 rc = ENODEV; 2091 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2092 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2093 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2094 goto bnx_nvram_test_done; 2095 } 2096 2097 csum = ether_crc32_le(data + 0x100, 0x100); 2098 if (csum != BNX_CRC32_RESIDUAL) { 2099 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2100 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2101 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2102 rc = ENODEV; 2103 } 2104 2105 bnx_nvram_test_done: 2106 return rc; 2107 } 2108 2109 /****************************************************************************/ 2110 /* Identifies the current media type of the controller and sets the PHY */ 2111 /* address. */ 2112 /* */ 2113 /* Returns: */ 2114 /* Nothing. */ 2115 /****************************************************************************/ 2116 void 2117 bnx_get_media(struct bnx_softc *sc) 2118 { 2119 sc->bnx_phy_addr = 1; 2120 2121 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2122 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2123 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2124 uint32_t strap; 2125 2126 /* 2127 * The BCM5709S is software configurable 2128 * for Copper or SerDes operation. 2129 */ 2130 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2131 DBPRINT(sc, BNX_INFO_LOAD, 2132 "5709 bonded for copper.\n"); 2133 goto bnx_get_media_exit; 2134 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2135 DBPRINT(sc, BNX_INFO_LOAD, 2136 "5709 bonded for dual media.\n"); 2137 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2138 goto bnx_get_media_exit; 2139 } 2140 2141 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2142 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2143 else { 2144 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2145 >> 8; 2146 } 2147 2148 if (sc->bnx_pa.pa_function == 0) { 2149 switch (strap) { 2150 case 0x4: 2151 case 0x5: 2152 case 0x6: 2153 DBPRINT(sc, BNX_INFO_LOAD, 2154 "BCM5709 s/w configured for SerDes.\n"); 2155 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2156 break; 2157 default: 2158 DBPRINT(sc, BNX_INFO_LOAD, 2159 "BCM5709 s/w configured for Copper.\n"); 2160 } 2161 } else { 2162 switch (strap) { 2163 case 0x1: 2164 case 0x2: 2165 case 0x4: 2166 DBPRINT(sc, BNX_INFO_LOAD, 2167 "BCM5709 s/w configured for SerDes.\n"); 2168 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2169 break; 2170 default: 2171 DBPRINT(sc, BNX_INFO_LOAD, 2172 "BCM5709 s/w configured for Copper.\n"); 2173 } 2174 } 2175 2176 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2177 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2178 2179 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2180 uint32_t val; 2181 2182 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2183 2184 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2185 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2186 2187 /* 2188 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2189 * separate PHY for SerDes. 2190 */ 2191 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2192 sc->bnx_phy_addr = 2; 2193 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2194 BNX_SHARED_HW_CFG_CONFIG); 2195 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2196 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2197 DBPRINT(sc, BNX_INFO_LOAD, 2198 "Found 2.5Gb capable adapter\n"); 2199 } 2200 } 2201 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2202 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2203 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2204 2205 bnx_get_media_exit: 2206 DBPRINT(sc, (BNX_INFO_LOAD), 2207 "Using PHY address %d.\n", sc->bnx_phy_addr); 2208 } 2209 2210 /****************************************************************************/ 2211 /* Performs PHY initialization required before MII drivers access the */ 2212 /* device. */ 2213 /* */ 2214 /* Returns: */ 2215 /* Nothing. */ 2216 /****************************************************************************/ 2217 void 2218 bnx_init_media(struct bnx_softc *sc) 2219 { 2220 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2221 /* 2222 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2223 * IEEE Clause 22 method. Otherwise we have no way to attach 2224 * the PHY to the mii(4) layer. PHY specific configuration 2225 * is done by the mii(4) layer. 2226 */ 2227 2228 /* Select auto-negotiation MMD of the PHY. */ 2229 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2230 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2231 2232 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2233 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2234 2235 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2236 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2237 } 2238 } 2239 2240 /****************************************************************************/ 2241 /* Free any DMA memory owned by the driver. */ 2242 /* */ 2243 /* Scans through each data structre that requires DMA memory and frees */ 2244 /* the memory if allocated. */ 2245 /* */ 2246 /* Returns: */ 2247 /* Nothing. */ 2248 /****************************************************************************/ 2249 void 2250 bnx_dma_free(struct bnx_softc *sc) 2251 { 2252 int i; 2253 2254 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2255 2256 /* Destroy the status block. */ 2257 if (sc->status_block != NULL && sc->status_map != NULL) { 2258 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2259 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2260 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2261 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2262 BNX_STATUS_BLK_SZ); 2263 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2264 sc->status_rseg); 2265 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2266 sc->status_block = NULL; 2267 sc->status_map = NULL; 2268 } 2269 2270 /* Destroy the statistics block. */ 2271 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2272 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2273 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2274 BNX_STATS_BLK_SZ); 2275 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2276 sc->stats_rseg); 2277 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2278 sc->stats_block = NULL; 2279 sc->stats_map = NULL; 2280 } 2281 2282 /* Free, unmap and destroy all context memory pages. */ 2283 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2284 for (i = 0; i < sc->ctx_pages; i++) { 2285 if (sc->ctx_block[i] != NULL) { 2286 bus_dmamap_unload(sc->bnx_dmatag, 2287 sc->ctx_map[i]); 2288 bus_dmamem_unmap(sc->bnx_dmatag, 2289 (void *)sc->ctx_block[i], 2290 BCM_PAGE_SIZE); 2291 bus_dmamem_free(sc->bnx_dmatag, 2292 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2293 bus_dmamap_destroy(sc->bnx_dmatag, 2294 sc->ctx_map[i]); 2295 sc->ctx_block[i] = NULL; 2296 } 2297 } 2298 } 2299 2300 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2301 for (i = 0; i < TX_PAGES; i++ ) { 2302 if (sc->tx_bd_chain[i] != NULL && 2303 sc->tx_bd_chain_map[i] != NULL) { 2304 bus_dmamap_unload(sc->bnx_dmatag, 2305 sc->tx_bd_chain_map[i]); 2306 bus_dmamem_unmap(sc->bnx_dmatag, 2307 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2308 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2309 sc->tx_bd_chain_rseg[i]); 2310 bus_dmamap_destroy(sc->bnx_dmatag, 2311 sc->tx_bd_chain_map[i]); 2312 sc->tx_bd_chain[i] = NULL; 2313 sc->tx_bd_chain_map[i] = NULL; 2314 } 2315 } 2316 2317 /* Destroy the TX dmamaps. */ 2318 /* This isn't necessary since we dont allocate them up front */ 2319 2320 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2321 for (i = 0; i < RX_PAGES; i++ ) { 2322 if (sc->rx_bd_chain[i] != NULL && 2323 sc->rx_bd_chain_map[i] != NULL) { 2324 bus_dmamap_unload(sc->bnx_dmatag, 2325 sc->rx_bd_chain_map[i]); 2326 bus_dmamem_unmap(sc->bnx_dmatag, 2327 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2328 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2329 sc->rx_bd_chain_rseg[i]); 2330 2331 bus_dmamap_destroy(sc->bnx_dmatag, 2332 sc->rx_bd_chain_map[i]); 2333 sc->rx_bd_chain[i] = NULL; 2334 sc->rx_bd_chain_map[i] = NULL; 2335 } 2336 } 2337 2338 /* Unload and destroy the RX mbuf maps. */ 2339 for (i = 0; i < TOTAL_RX_BD; i++) { 2340 if (sc->rx_mbuf_map[i] != NULL) { 2341 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2342 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2343 } 2344 } 2345 2346 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2347 } 2348 2349 /****************************************************************************/ 2350 /* Allocate any DMA memory needed by the driver. */ 2351 /* */ 2352 /* Allocates DMA memory needed for the various global structures needed by */ 2353 /* hardware. */ 2354 /* */ 2355 /* Returns: */ 2356 /* 0 for success, positive value for failure. */ 2357 /****************************************************************************/ 2358 int 2359 bnx_dma_alloc(struct bnx_softc *sc) 2360 { 2361 int i, rc = 0; 2362 2363 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2364 2365 /* 2366 * Allocate DMA memory for the status block, map the memory into DMA 2367 * space, and fetch the physical address of the block. 2368 */ 2369 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2370 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2371 aprint_error_dev(sc->bnx_dev, 2372 "Could not create status block DMA map!\n"); 2373 rc = ENOMEM; 2374 goto bnx_dma_alloc_exit; 2375 } 2376 2377 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2378 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2379 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2380 aprint_error_dev(sc->bnx_dev, 2381 "Could not allocate status block DMA memory!\n"); 2382 rc = ENOMEM; 2383 goto bnx_dma_alloc_exit; 2384 } 2385 2386 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2387 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2388 aprint_error_dev(sc->bnx_dev, 2389 "Could not map status block DMA memory!\n"); 2390 rc = ENOMEM; 2391 goto bnx_dma_alloc_exit; 2392 } 2393 2394 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2395 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2396 aprint_error_dev(sc->bnx_dev, 2397 "Could not load status block DMA memory!\n"); 2398 rc = ENOMEM; 2399 goto bnx_dma_alloc_exit; 2400 } 2401 2402 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2403 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2404 2405 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2406 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2407 2408 /* DRC - Fix for 64 bit addresses. */ 2409 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2410 (uint32_t) sc->status_block_paddr); 2411 2412 /* BCM5709 uses host memory as cache for context memory. */ 2413 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2414 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2415 if (sc->ctx_pages == 0) 2416 sc->ctx_pages = 1; 2417 if (sc->ctx_pages > 4) /* XXX */ 2418 sc->ctx_pages = 4; 2419 2420 DBRUNIF((sc->ctx_pages > 512), 2421 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2422 __FILE__, __LINE__, sc->ctx_pages)); 2423 2424 2425 for (i = 0; i < sc->ctx_pages; i++) { 2426 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2427 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2428 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2429 &sc->ctx_map[i]) != 0) { 2430 rc = ENOMEM; 2431 goto bnx_dma_alloc_exit; 2432 } 2433 2434 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2435 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2436 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2437 rc = ENOMEM; 2438 goto bnx_dma_alloc_exit; 2439 } 2440 2441 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2442 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2443 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2444 rc = ENOMEM; 2445 goto bnx_dma_alloc_exit; 2446 } 2447 2448 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2449 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2450 BUS_DMA_NOWAIT) != 0) { 2451 rc = ENOMEM; 2452 goto bnx_dma_alloc_exit; 2453 } 2454 2455 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2456 } 2457 } 2458 2459 /* 2460 * Allocate DMA memory for the statistics block, map the memory into 2461 * DMA space, and fetch the physical address of the block. 2462 */ 2463 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2464 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2465 aprint_error_dev(sc->bnx_dev, 2466 "Could not create stats block DMA map!\n"); 2467 rc = ENOMEM; 2468 goto bnx_dma_alloc_exit; 2469 } 2470 2471 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2472 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2473 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2474 aprint_error_dev(sc->bnx_dev, 2475 "Could not allocate stats block DMA memory!\n"); 2476 rc = ENOMEM; 2477 goto bnx_dma_alloc_exit; 2478 } 2479 2480 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2481 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2482 aprint_error_dev(sc->bnx_dev, 2483 "Could not map stats block DMA memory!\n"); 2484 rc = ENOMEM; 2485 goto bnx_dma_alloc_exit; 2486 } 2487 2488 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2489 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2490 aprint_error_dev(sc->bnx_dev, 2491 "Could not load status block DMA memory!\n"); 2492 rc = ENOMEM; 2493 goto bnx_dma_alloc_exit; 2494 } 2495 2496 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2497 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2498 2499 /* DRC - Fix for 64 bit address. */ 2500 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2501 (uint32_t) sc->stats_block_paddr); 2502 2503 /* 2504 * Allocate DMA memory for the TX buffer descriptor chain, 2505 * and fetch the physical address of the block. 2506 */ 2507 for (i = 0; i < TX_PAGES; i++) { 2508 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2509 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2510 &sc->tx_bd_chain_map[i])) { 2511 aprint_error_dev(sc->bnx_dev, 2512 "Could not create Tx desc %d DMA map!\n", i); 2513 rc = ENOMEM; 2514 goto bnx_dma_alloc_exit; 2515 } 2516 2517 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2518 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2519 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2520 aprint_error_dev(sc->bnx_dev, 2521 "Could not allocate TX desc %d DMA memory!\n", 2522 i); 2523 rc = ENOMEM; 2524 goto bnx_dma_alloc_exit; 2525 } 2526 2527 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2528 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2529 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2530 aprint_error_dev(sc->bnx_dev, 2531 "Could not map TX desc %d DMA memory!\n", i); 2532 rc = ENOMEM; 2533 goto bnx_dma_alloc_exit; 2534 } 2535 2536 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2537 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2538 BUS_DMA_NOWAIT)) { 2539 aprint_error_dev(sc->bnx_dev, 2540 "Could not load TX desc %d DMA memory!\n", i); 2541 rc = ENOMEM; 2542 goto bnx_dma_alloc_exit; 2543 } 2544 2545 sc->tx_bd_chain_paddr[i] = 2546 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2547 2548 /* DRC - Fix for 64 bit systems. */ 2549 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2550 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2551 } 2552 2553 /* 2554 * Create lists to hold TX mbufs. 2555 */ 2556 TAILQ_INIT(&sc->tx_free_pkts); 2557 TAILQ_INIT(&sc->tx_used_pkts); 2558 sc->tx_pkt_count = 0; 2559 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2560 2561 /* 2562 * Allocate DMA memory for the Rx buffer descriptor chain, 2563 * and fetch the physical address of the block. 2564 */ 2565 for (i = 0; i < RX_PAGES; i++) { 2566 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2567 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2568 &sc->rx_bd_chain_map[i])) { 2569 aprint_error_dev(sc->bnx_dev, 2570 "Could not create Rx desc %d DMA map!\n", i); 2571 rc = ENOMEM; 2572 goto bnx_dma_alloc_exit; 2573 } 2574 2575 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2576 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2577 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2578 aprint_error_dev(sc->bnx_dev, 2579 "Could not allocate Rx desc %d DMA memory!\n", i); 2580 rc = ENOMEM; 2581 goto bnx_dma_alloc_exit; 2582 } 2583 2584 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2585 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2586 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2587 aprint_error_dev(sc->bnx_dev, 2588 "Could not map Rx desc %d DMA memory!\n", i); 2589 rc = ENOMEM; 2590 goto bnx_dma_alloc_exit; 2591 } 2592 2593 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2594 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2595 BUS_DMA_NOWAIT)) { 2596 aprint_error_dev(sc->bnx_dev, 2597 "Could not load Rx desc %d DMA memory!\n", i); 2598 rc = ENOMEM; 2599 goto bnx_dma_alloc_exit; 2600 } 2601 2602 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2603 sc->rx_bd_chain_paddr[i] = 2604 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2605 2606 /* DRC - Fix for 64 bit systems. */ 2607 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2608 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2609 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2610 0, BNX_RX_CHAIN_PAGE_SZ, 2611 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2612 } 2613 2614 /* 2615 * Create DMA maps for the Rx buffer mbufs. 2616 */ 2617 for (i = 0; i < TOTAL_RX_BD; i++) { 2618 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2619 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2620 &sc->rx_mbuf_map[i])) { 2621 aprint_error_dev(sc->bnx_dev, 2622 "Could not create Rx mbuf %d DMA map!\n", i); 2623 rc = ENOMEM; 2624 goto bnx_dma_alloc_exit; 2625 } 2626 } 2627 2628 bnx_dma_alloc_exit: 2629 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2630 2631 return rc; 2632 } 2633 2634 /****************************************************************************/ 2635 /* Release all resources used by the driver. */ 2636 /* */ 2637 /* Releases all resources acquired by the driver including interrupts, */ 2638 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2639 /* */ 2640 /* Returns: */ 2641 /* Nothing. */ 2642 /****************************************************************************/ 2643 void 2644 bnx_release_resources(struct bnx_softc *sc) 2645 { 2646 struct pci_attach_args *pa = &(sc->bnx_pa); 2647 2648 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2649 2650 bnx_dma_free(sc); 2651 2652 if (sc->bnx_intrhand != NULL) 2653 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2654 2655 if (sc->bnx_size) 2656 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2657 2658 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2659 } 2660 2661 /****************************************************************************/ 2662 /* Firmware synchronization. */ 2663 /* */ 2664 /* Before performing certain events such as a chip reset, synchronize with */ 2665 /* the firmware first. */ 2666 /* */ 2667 /* Returns: */ 2668 /* 0 for success, positive value for failure. */ 2669 /****************************************************************************/ 2670 int 2671 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2672 { 2673 int i, rc = 0; 2674 uint32_t val; 2675 2676 /* Don't waste any time if we've timed out before. */ 2677 if (sc->bnx_fw_timed_out) { 2678 rc = EBUSY; 2679 goto bnx_fw_sync_exit; 2680 } 2681 2682 /* Increment the message sequence number. */ 2683 sc->bnx_fw_wr_seq++; 2684 msg_data |= sc->bnx_fw_wr_seq; 2685 2686 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2687 msg_data); 2688 2689 /* Send the message to the bootcode driver mailbox. */ 2690 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2691 2692 /* Wait for the bootcode to acknowledge the message. */ 2693 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2694 /* Check for a response in the bootcode firmware mailbox. */ 2695 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2696 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2697 break; 2698 DELAY(1000); 2699 } 2700 2701 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2702 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2703 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2704 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2705 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2706 2707 msg_data &= ~BNX_DRV_MSG_CODE; 2708 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2709 2710 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2711 2712 sc->bnx_fw_timed_out = 1; 2713 rc = EBUSY; 2714 } 2715 2716 bnx_fw_sync_exit: 2717 return rc; 2718 } 2719 2720 /****************************************************************************/ 2721 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2722 /* */ 2723 /* Returns: */ 2724 /* Nothing. */ 2725 /****************************************************************************/ 2726 void 2727 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2728 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2729 { 2730 int i; 2731 uint32_t val; 2732 2733 /* Set the page size used by RV2P. */ 2734 if (rv2p_proc == RV2P_PROC2) { 2735 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2736 USABLE_RX_BD_PER_PAGE); 2737 } 2738 2739 for (i = 0; i < rv2p_code_len; i += 8) { 2740 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2741 rv2p_code++; 2742 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2743 rv2p_code++; 2744 2745 if (rv2p_proc == RV2P_PROC1) { 2746 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2747 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2748 } else { 2749 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2750 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2751 } 2752 } 2753 2754 /* Reset the processor, un-stall is done later. */ 2755 if (rv2p_proc == RV2P_PROC1) 2756 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2757 else 2758 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2759 } 2760 2761 /****************************************************************************/ 2762 /* Load RISC processor firmware. */ 2763 /* */ 2764 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2765 /* associated with a particular processor. */ 2766 /* */ 2767 /* Returns: */ 2768 /* Nothing. */ 2769 /****************************************************************************/ 2770 void 2771 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2772 struct fw_info *fw) 2773 { 2774 uint32_t offset; 2775 uint32_t val; 2776 2777 /* Halt the CPU. */ 2778 val = REG_RD_IND(sc, cpu_reg->mode); 2779 val |= cpu_reg->mode_value_halt; 2780 REG_WR_IND(sc, cpu_reg->mode, val); 2781 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2782 2783 /* Load the Text area. */ 2784 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2785 if (fw->text) { 2786 int j; 2787 2788 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2789 REG_WR_IND(sc, offset, fw->text[j]); 2790 } 2791 2792 /* Load the Data area. */ 2793 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2794 if (fw->data) { 2795 int j; 2796 2797 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2798 REG_WR_IND(sc, offset, fw->data[j]); 2799 } 2800 2801 /* Load the SBSS area. */ 2802 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2803 if (fw->sbss) { 2804 int j; 2805 2806 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2807 REG_WR_IND(sc, offset, fw->sbss[j]); 2808 } 2809 2810 /* Load the BSS area. */ 2811 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2812 if (fw->bss) { 2813 int j; 2814 2815 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2816 REG_WR_IND(sc, offset, fw->bss[j]); 2817 } 2818 2819 /* Load the Read-Only area. */ 2820 offset = cpu_reg->spad_base + 2821 (fw->rodata_addr - cpu_reg->mips_view_base); 2822 if (fw->rodata) { 2823 int j; 2824 2825 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2826 REG_WR_IND(sc, offset, fw->rodata[j]); 2827 } 2828 2829 /* Clear the pre-fetch instruction. */ 2830 REG_WR_IND(sc, cpu_reg->inst, 0); 2831 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2832 2833 /* Start the CPU. */ 2834 val = REG_RD_IND(sc, cpu_reg->mode); 2835 val &= ~cpu_reg->mode_value_halt; 2836 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2837 REG_WR_IND(sc, cpu_reg->mode, val); 2838 } 2839 2840 /****************************************************************************/ 2841 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2842 /* */ 2843 /* Loads the firmware for each CPU and starts the CPU. */ 2844 /* */ 2845 /* Returns: */ 2846 /* Nothing. */ 2847 /****************************************************************************/ 2848 void 2849 bnx_init_cpus(struct bnx_softc *sc) 2850 { 2851 struct cpu_reg cpu_reg; 2852 struct fw_info fw; 2853 2854 switch(BNX_CHIP_NUM(sc)) { 2855 case BNX_CHIP_NUM_5709: 2856 /* Initialize the RV2P processor. */ 2857 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2858 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2859 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2860 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2861 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2862 } else { 2863 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2864 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2865 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2866 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2867 } 2868 2869 /* Initialize the RX Processor. */ 2870 cpu_reg.mode = BNX_RXP_CPU_MODE; 2871 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2872 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2873 cpu_reg.state = BNX_RXP_CPU_STATE; 2874 cpu_reg.state_value_clear = 0xffffff; 2875 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2876 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2877 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2878 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2879 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2880 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2881 cpu_reg.mips_view_base = 0x8000000; 2882 2883 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2884 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2885 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2886 fw.start_addr = bnx_RXP_b09FwStartAddr; 2887 2888 fw.text_addr = bnx_RXP_b09FwTextAddr; 2889 fw.text_len = bnx_RXP_b09FwTextLen; 2890 fw.text_index = 0; 2891 fw.text = bnx_RXP_b09FwText; 2892 2893 fw.data_addr = bnx_RXP_b09FwDataAddr; 2894 fw.data_len = bnx_RXP_b09FwDataLen; 2895 fw.data_index = 0; 2896 fw.data = bnx_RXP_b09FwData; 2897 2898 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2899 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2900 fw.sbss_index = 0; 2901 fw.sbss = bnx_RXP_b09FwSbss; 2902 2903 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2904 fw.bss_len = bnx_RXP_b09FwBssLen; 2905 fw.bss_index = 0; 2906 fw.bss = bnx_RXP_b09FwBss; 2907 2908 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2909 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2910 fw.rodata_index = 0; 2911 fw.rodata = bnx_RXP_b09FwRodata; 2912 2913 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2914 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2915 2916 /* Initialize the TX Processor. */ 2917 cpu_reg.mode = BNX_TXP_CPU_MODE; 2918 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2919 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2920 cpu_reg.state = BNX_TXP_CPU_STATE; 2921 cpu_reg.state_value_clear = 0xffffff; 2922 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2923 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2924 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2925 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2926 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2927 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2928 cpu_reg.mips_view_base = 0x8000000; 2929 2930 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2931 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2932 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2933 fw.start_addr = bnx_TXP_b09FwStartAddr; 2934 2935 fw.text_addr = bnx_TXP_b09FwTextAddr; 2936 fw.text_len = bnx_TXP_b09FwTextLen; 2937 fw.text_index = 0; 2938 fw.text = bnx_TXP_b09FwText; 2939 2940 fw.data_addr = bnx_TXP_b09FwDataAddr; 2941 fw.data_len = bnx_TXP_b09FwDataLen; 2942 fw.data_index = 0; 2943 fw.data = bnx_TXP_b09FwData; 2944 2945 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2946 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2947 fw.sbss_index = 0; 2948 fw.sbss = bnx_TXP_b09FwSbss; 2949 2950 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2951 fw.bss_len = bnx_TXP_b09FwBssLen; 2952 fw.bss_index = 0; 2953 fw.bss = bnx_TXP_b09FwBss; 2954 2955 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2956 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2957 fw.rodata_index = 0; 2958 fw.rodata = bnx_TXP_b09FwRodata; 2959 2960 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2961 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2962 2963 /* Initialize the TX Patch-up Processor. */ 2964 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2965 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2966 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2967 cpu_reg.state = BNX_TPAT_CPU_STATE; 2968 cpu_reg.state_value_clear = 0xffffff; 2969 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2970 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2971 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2972 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2973 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2974 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2975 cpu_reg.mips_view_base = 0x8000000; 2976 2977 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2978 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2979 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2980 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2981 2982 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2983 fw.text_len = bnx_TPAT_b09FwTextLen; 2984 fw.text_index = 0; 2985 fw.text = bnx_TPAT_b09FwText; 2986 2987 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2988 fw.data_len = bnx_TPAT_b09FwDataLen; 2989 fw.data_index = 0; 2990 fw.data = bnx_TPAT_b09FwData; 2991 2992 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2993 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2994 fw.sbss_index = 0; 2995 fw.sbss = bnx_TPAT_b09FwSbss; 2996 2997 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2998 fw.bss_len = bnx_TPAT_b09FwBssLen; 2999 fw.bss_index = 0; 3000 fw.bss = bnx_TPAT_b09FwBss; 3001 3002 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3003 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3004 fw.rodata_index = 0; 3005 fw.rodata = bnx_TPAT_b09FwRodata; 3006 3007 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3008 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3009 3010 /* Initialize the Completion Processor. */ 3011 cpu_reg.mode = BNX_COM_CPU_MODE; 3012 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3013 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3014 cpu_reg.state = BNX_COM_CPU_STATE; 3015 cpu_reg.state_value_clear = 0xffffff; 3016 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3017 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3018 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3019 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3020 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3021 cpu_reg.spad_base = BNX_COM_SCRATCH; 3022 cpu_reg.mips_view_base = 0x8000000; 3023 3024 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3025 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3026 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3027 fw.start_addr = bnx_COM_b09FwStartAddr; 3028 3029 fw.text_addr = bnx_COM_b09FwTextAddr; 3030 fw.text_len = bnx_COM_b09FwTextLen; 3031 fw.text_index = 0; 3032 fw.text = bnx_COM_b09FwText; 3033 3034 fw.data_addr = bnx_COM_b09FwDataAddr; 3035 fw.data_len = bnx_COM_b09FwDataLen; 3036 fw.data_index = 0; 3037 fw.data = bnx_COM_b09FwData; 3038 3039 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3040 fw.sbss_len = bnx_COM_b09FwSbssLen; 3041 fw.sbss_index = 0; 3042 fw.sbss = bnx_COM_b09FwSbss; 3043 3044 fw.bss_addr = bnx_COM_b09FwBssAddr; 3045 fw.bss_len = bnx_COM_b09FwBssLen; 3046 fw.bss_index = 0; 3047 fw.bss = bnx_COM_b09FwBss; 3048 3049 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3050 fw.rodata_len = bnx_COM_b09FwRodataLen; 3051 fw.rodata_index = 0; 3052 fw.rodata = bnx_COM_b09FwRodata; 3053 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3054 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3055 break; 3056 default: 3057 /* Initialize the RV2P processor. */ 3058 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3059 RV2P_PROC1); 3060 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3061 RV2P_PROC2); 3062 3063 /* Initialize the RX Processor. */ 3064 cpu_reg.mode = BNX_RXP_CPU_MODE; 3065 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3066 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3067 cpu_reg.state = BNX_RXP_CPU_STATE; 3068 cpu_reg.state_value_clear = 0xffffff; 3069 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3070 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3071 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3072 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3073 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3074 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3075 cpu_reg.mips_view_base = 0x8000000; 3076 3077 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3078 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3079 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3080 fw.start_addr = bnx_RXP_b06FwStartAddr; 3081 3082 fw.text_addr = bnx_RXP_b06FwTextAddr; 3083 fw.text_len = bnx_RXP_b06FwTextLen; 3084 fw.text_index = 0; 3085 fw.text = bnx_RXP_b06FwText; 3086 3087 fw.data_addr = bnx_RXP_b06FwDataAddr; 3088 fw.data_len = bnx_RXP_b06FwDataLen; 3089 fw.data_index = 0; 3090 fw.data = bnx_RXP_b06FwData; 3091 3092 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3093 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3094 fw.sbss_index = 0; 3095 fw.sbss = bnx_RXP_b06FwSbss; 3096 3097 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3098 fw.bss_len = bnx_RXP_b06FwBssLen; 3099 fw.bss_index = 0; 3100 fw.bss = bnx_RXP_b06FwBss; 3101 3102 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3103 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3104 fw.rodata_index = 0; 3105 fw.rodata = bnx_RXP_b06FwRodata; 3106 3107 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3108 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3109 3110 /* Initialize the TX Processor. */ 3111 cpu_reg.mode = BNX_TXP_CPU_MODE; 3112 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3113 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3114 cpu_reg.state = BNX_TXP_CPU_STATE; 3115 cpu_reg.state_value_clear = 0xffffff; 3116 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3117 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3118 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3119 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3120 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3121 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3122 cpu_reg.mips_view_base = 0x8000000; 3123 3124 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3125 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3126 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3127 fw.start_addr = bnx_TXP_b06FwStartAddr; 3128 3129 fw.text_addr = bnx_TXP_b06FwTextAddr; 3130 fw.text_len = bnx_TXP_b06FwTextLen; 3131 fw.text_index = 0; 3132 fw.text = bnx_TXP_b06FwText; 3133 3134 fw.data_addr = bnx_TXP_b06FwDataAddr; 3135 fw.data_len = bnx_TXP_b06FwDataLen; 3136 fw.data_index = 0; 3137 fw.data = bnx_TXP_b06FwData; 3138 3139 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3140 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3141 fw.sbss_index = 0; 3142 fw.sbss = bnx_TXP_b06FwSbss; 3143 3144 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3145 fw.bss_len = bnx_TXP_b06FwBssLen; 3146 fw.bss_index = 0; 3147 fw.bss = bnx_TXP_b06FwBss; 3148 3149 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3150 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3151 fw.rodata_index = 0; 3152 fw.rodata = bnx_TXP_b06FwRodata; 3153 3154 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3155 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3156 3157 /* Initialize the TX Patch-up Processor. */ 3158 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3159 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3160 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3161 cpu_reg.state = BNX_TPAT_CPU_STATE; 3162 cpu_reg.state_value_clear = 0xffffff; 3163 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3164 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3165 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3166 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3167 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3168 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3169 cpu_reg.mips_view_base = 0x8000000; 3170 3171 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3172 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3173 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3174 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3175 3176 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3177 fw.text_len = bnx_TPAT_b06FwTextLen; 3178 fw.text_index = 0; 3179 fw.text = bnx_TPAT_b06FwText; 3180 3181 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3182 fw.data_len = bnx_TPAT_b06FwDataLen; 3183 fw.data_index = 0; 3184 fw.data = bnx_TPAT_b06FwData; 3185 3186 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3187 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3188 fw.sbss_index = 0; 3189 fw.sbss = bnx_TPAT_b06FwSbss; 3190 3191 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3192 fw.bss_len = bnx_TPAT_b06FwBssLen; 3193 fw.bss_index = 0; 3194 fw.bss = bnx_TPAT_b06FwBss; 3195 3196 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3197 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3198 fw.rodata_index = 0; 3199 fw.rodata = bnx_TPAT_b06FwRodata; 3200 3201 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3202 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3203 3204 /* Initialize the Completion Processor. */ 3205 cpu_reg.mode = BNX_COM_CPU_MODE; 3206 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3207 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3208 cpu_reg.state = BNX_COM_CPU_STATE; 3209 cpu_reg.state_value_clear = 0xffffff; 3210 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3211 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3212 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3213 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3214 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3215 cpu_reg.spad_base = BNX_COM_SCRATCH; 3216 cpu_reg.mips_view_base = 0x8000000; 3217 3218 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3219 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3220 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3221 fw.start_addr = bnx_COM_b06FwStartAddr; 3222 3223 fw.text_addr = bnx_COM_b06FwTextAddr; 3224 fw.text_len = bnx_COM_b06FwTextLen; 3225 fw.text_index = 0; 3226 fw.text = bnx_COM_b06FwText; 3227 3228 fw.data_addr = bnx_COM_b06FwDataAddr; 3229 fw.data_len = bnx_COM_b06FwDataLen; 3230 fw.data_index = 0; 3231 fw.data = bnx_COM_b06FwData; 3232 3233 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3234 fw.sbss_len = bnx_COM_b06FwSbssLen; 3235 fw.sbss_index = 0; 3236 fw.sbss = bnx_COM_b06FwSbss; 3237 3238 fw.bss_addr = bnx_COM_b06FwBssAddr; 3239 fw.bss_len = bnx_COM_b06FwBssLen; 3240 fw.bss_index = 0; 3241 fw.bss = bnx_COM_b06FwBss; 3242 3243 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3244 fw.rodata_len = bnx_COM_b06FwRodataLen; 3245 fw.rodata_index = 0; 3246 fw.rodata = bnx_COM_b06FwRodata; 3247 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3248 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3249 break; 3250 } 3251 } 3252 3253 /****************************************************************************/ 3254 /* Initialize context memory. */ 3255 /* */ 3256 /* Clears the memory associated with each Context ID (CID). */ 3257 /* */ 3258 /* Returns: */ 3259 /* Nothing. */ 3260 /****************************************************************************/ 3261 void 3262 bnx_init_context(struct bnx_softc *sc) 3263 { 3264 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3265 /* DRC: Replace this constant value with a #define. */ 3266 int i, retry_cnt = 10; 3267 uint32_t val; 3268 3269 /* 3270 * BCM5709 context memory may be cached 3271 * in host memory so prepare the host memory 3272 * for access. 3273 */ 3274 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3275 | (1 << 12); 3276 val |= (BCM_PAGE_BITS - 8) << 16; 3277 REG_WR(sc, BNX_CTX_COMMAND, val); 3278 3279 /* Wait for mem init command to complete. */ 3280 for (i = 0; i < retry_cnt; i++) { 3281 val = REG_RD(sc, BNX_CTX_COMMAND); 3282 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3283 break; 3284 DELAY(2); 3285 } 3286 3287 /* ToDo: Consider returning an error here. */ 3288 3289 for (i = 0; i < sc->ctx_pages; i++) { 3290 int j; 3291 3292 /* Set the physaddr of the context memory cache. */ 3293 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3294 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3295 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3296 val = (uint32_t) 3297 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3298 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3299 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3300 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3301 3302 /* Verify that the context memory write was successful. */ 3303 for (j = 0; j < retry_cnt; j++) { 3304 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3305 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3306 break; 3307 DELAY(5); 3308 } 3309 3310 /* ToDo: Consider returning an error here. */ 3311 } 3312 } else { 3313 uint32_t vcid_addr, offset; 3314 3315 /* 3316 * For the 5706/5708, context memory is local to the 3317 * controller, so initialize the controller context memory. 3318 */ 3319 3320 vcid_addr = GET_CID_ADDR(96); 3321 while (vcid_addr) { 3322 3323 vcid_addr -= BNX_PHY_CTX_SIZE; 3324 3325 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3326 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3327 3328 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3329 offset += 4) 3330 CTX_WR(sc, 0x00, offset, 0); 3331 3332 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3333 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3334 } 3335 } 3336 } 3337 3338 /****************************************************************************/ 3339 /* Fetch the permanent MAC address of the controller. */ 3340 /* */ 3341 /* Returns: */ 3342 /* Nothing. */ 3343 /****************************************************************************/ 3344 void 3345 bnx_get_mac_addr(struct bnx_softc *sc) 3346 { 3347 uint32_t mac_lo = 0, mac_hi = 0; 3348 3349 /* 3350 * The NetXtreme II bootcode populates various NIC 3351 * power-on and runtime configuration items in a 3352 * shared memory area. The factory configured MAC 3353 * address is available from both NVRAM and the 3354 * shared memory area so we'll read the value from 3355 * shared memory for speed. 3356 */ 3357 3358 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3359 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3360 3361 if ((mac_lo == 0) && (mac_hi == 0)) { 3362 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3363 __FILE__, __LINE__); 3364 } else { 3365 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3366 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3367 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3368 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3369 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3370 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3371 } 3372 3373 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3374 "%s\n", ether_sprintf(sc->eaddr)); 3375 } 3376 3377 /****************************************************************************/ 3378 /* Program the MAC address. */ 3379 /* */ 3380 /* Returns: */ 3381 /* Nothing. */ 3382 /****************************************************************************/ 3383 void 3384 bnx_set_mac_addr(struct bnx_softc *sc) 3385 { 3386 uint32_t val; 3387 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3388 3389 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3390 "%s\n", ether_sprintf(sc->eaddr)); 3391 3392 val = (mac_addr[0] << 8) | mac_addr[1]; 3393 3394 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3395 3396 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3397 (mac_addr[4] << 8) | mac_addr[5]; 3398 3399 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3400 } 3401 3402 /****************************************************************************/ 3403 /* Stop the controller. */ 3404 /* */ 3405 /* Returns: */ 3406 /* Nothing. */ 3407 /****************************************************************************/ 3408 void 3409 bnx_stop(struct ifnet *ifp, int disable) 3410 { 3411 struct bnx_softc *sc = ifp->if_softc; 3412 3413 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3414 3415 if (disable) { 3416 sc->bnx_detaching = 1; 3417 callout_halt(&sc->bnx_timeout, NULL); 3418 } else 3419 callout_stop(&sc->bnx_timeout); 3420 3421 mii_down(&sc->bnx_mii); 3422 3423 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3424 3425 /* Disable the transmit/receive blocks. */ 3426 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3427 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3428 DELAY(20); 3429 3430 bnx_disable_intr(sc); 3431 3432 /* Tell firmware that the driver is going away. */ 3433 if (disable) 3434 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3435 else 3436 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3437 3438 /* Free RX buffers. */ 3439 bnx_free_rx_chain(sc); 3440 3441 /* Free TX buffers. */ 3442 bnx_free_tx_chain(sc); 3443 3444 ifp->if_timer = 0; 3445 3446 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3447 3448 } 3449 3450 int 3451 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3452 { 3453 struct pci_attach_args *pa = &(sc->bnx_pa); 3454 uint32_t val; 3455 int i, rc = 0; 3456 3457 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3458 3459 /* Wait for pending PCI transactions to complete. */ 3460 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3461 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3462 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3463 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3464 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3465 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3466 DELAY(5); 3467 3468 /* Disable DMA */ 3469 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3470 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3471 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3472 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3473 } 3474 3475 /* Assume bootcode is running. */ 3476 sc->bnx_fw_timed_out = 0; 3477 3478 /* Give the firmware a chance to prepare for the reset. */ 3479 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3480 if (rc) 3481 goto bnx_reset_exit; 3482 3483 /* Set a firmware reminder that this is a soft reset. */ 3484 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3485 BNX_DRV_RESET_SIGNATURE_MAGIC); 3486 3487 /* Dummy read to force the chip to complete all current transactions. */ 3488 val = REG_RD(sc, BNX_MISC_ID); 3489 3490 /* Chip reset. */ 3491 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3492 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3493 REG_RD(sc, BNX_MISC_COMMAND); 3494 DELAY(5); 3495 3496 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3497 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3498 3499 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3500 val); 3501 } else { 3502 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3503 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3504 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3505 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3506 3507 /* Allow up to 30us for reset to complete. */ 3508 for (i = 0; i < 10; i++) { 3509 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3510 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3511 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3512 break; 3513 } 3514 DELAY(10); 3515 } 3516 3517 /* Check that reset completed successfully. */ 3518 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3519 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3520 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3521 __FILE__, __LINE__); 3522 rc = EBUSY; 3523 goto bnx_reset_exit; 3524 } 3525 } 3526 3527 /* Make sure byte swapping is properly configured. */ 3528 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3529 if (val != 0x01020304) { 3530 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3531 __FILE__, __LINE__); 3532 rc = ENODEV; 3533 goto bnx_reset_exit; 3534 } 3535 3536 /* Just completed a reset, assume that firmware is running again. */ 3537 sc->bnx_fw_timed_out = 0; 3538 3539 /* Wait for the firmware to finish its initialization. */ 3540 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3541 if (rc) 3542 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3543 "initialization!\n", __FILE__, __LINE__); 3544 3545 bnx_reset_exit: 3546 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3547 3548 return rc; 3549 } 3550 3551 int 3552 bnx_chipinit(struct bnx_softc *sc) 3553 { 3554 struct pci_attach_args *pa = &(sc->bnx_pa); 3555 uint32_t val; 3556 int rc = 0; 3557 3558 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3559 3560 /* Make sure the interrupt is not active. */ 3561 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3562 3563 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3564 /* channels and PCI clock compensation delay. */ 3565 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3566 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3567 #if BYTE_ORDER == BIG_ENDIAN 3568 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3569 #endif 3570 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3571 DMA_READ_CHANS << 12 | 3572 DMA_WRITE_CHANS << 16; 3573 3574 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3575 3576 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3577 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3578 3579 /* 3580 * This setting resolves a problem observed on certain Intel PCI 3581 * chipsets that cannot handle multiple outstanding DMA operations. 3582 * See errata E9_5706A1_65. 3583 */ 3584 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3585 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3586 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3587 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3588 3589 REG_WR(sc, BNX_DMA_CONFIG, val); 3590 3591 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3592 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3593 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3594 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3595 val & ~0x20000); 3596 } 3597 3598 /* Enable the RX_V2P and Context state machines before access. */ 3599 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3600 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3601 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3602 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3603 3604 /* Initialize context mapping and zero out the quick contexts. */ 3605 bnx_init_context(sc); 3606 3607 /* Initialize the on-boards CPUs */ 3608 bnx_init_cpus(sc); 3609 3610 /* Prepare NVRAM for access. */ 3611 if (bnx_init_nvram(sc)) { 3612 rc = ENODEV; 3613 goto bnx_chipinit_exit; 3614 } 3615 3616 /* Set the kernel bypass block size */ 3617 val = REG_RD(sc, BNX_MQ_CONFIG); 3618 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3619 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3620 3621 /* Enable bins used on the 5709. */ 3622 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3623 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3624 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3625 val |= BNX_MQ_CONFIG_HALT_DIS; 3626 } 3627 3628 REG_WR(sc, BNX_MQ_CONFIG, val); 3629 3630 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3631 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3632 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3633 3634 val = (BCM_PAGE_BITS - 8) << 24; 3635 REG_WR(sc, BNX_RV2P_CONFIG, val); 3636 3637 /* Configure page size. */ 3638 val = REG_RD(sc, BNX_TBDR_CONFIG); 3639 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3640 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3641 REG_WR(sc, BNX_TBDR_CONFIG, val); 3642 3643 #if 0 3644 /* Set the perfect match control register to default. */ 3645 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3646 #endif 3647 3648 bnx_chipinit_exit: 3649 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3650 3651 return rc; 3652 } 3653 3654 /****************************************************************************/ 3655 /* Initialize the controller in preparation to send/receive traffic. */ 3656 /* */ 3657 /* Returns: */ 3658 /* 0 for success, positive value for failure. */ 3659 /****************************************************************************/ 3660 int 3661 bnx_blockinit(struct bnx_softc *sc) 3662 { 3663 uint32_t reg, val; 3664 int rc = 0; 3665 3666 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3667 3668 /* Load the hardware default MAC address. */ 3669 bnx_set_mac_addr(sc); 3670 3671 /* Set the Ethernet backoff seed value */ 3672 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3673 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3674 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3675 3676 sc->last_status_idx = 0; 3677 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3678 3679 /* Set up link change interrupt generation. */ 3680 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3681 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3682 3683 /* Program the physical address of the status block. */ 3684 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3685 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3686 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3687 3688 /* Program the physical address of the statistics block. */ 3689 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3690 (uint32_t)(sc->stats_block_paddr)); 3691 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3692 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3693 3694 /* Program various host coalescing parameters. */ 3695 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3696 << 16) | sc->bnx_tx_quick_cons_trip); 3697 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3698 << 16) | sc->bnx_rx_quick_cons_trip); 3699 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3700 sc->bnx_comp_prod_trip); 3701 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3702 sc->bnx_tx_ticks); 3703 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3704 sc->bnx_rx_ticks); 3705 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3706 sc->bnx_com_ticks); 3707 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3708 sc->bnx_cmd_ticks); 3709 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3710 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3711 REG_WR(sc, BNX_HC_CONFIG, 3712 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3713 BNX_HC_CONFIG_COLLECT_STATS)); 3714 3715 /* Clear the internal statistics counters. */ 3716 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3717 3718 /* Verify that bootcode is running. */ 3719 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3720 3721 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3722 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3723 __FILE__, __LINE__); reg = 0); 3724 3725 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3726 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3727 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3728 "Expected: 08%08X\n", __FILE__, __LINE__, 3729 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3730 BNX_DEV_INFO_SIGNATURE_MAGIC); 3731 rc = ENODEV; 3732 goto bnx_blockinit_exit; 3733 } 3734 3735 /* Check if any management firmware is running. */ 3736 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3737 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3738 BNX_PORT_FEATURE_IMD_ENABLED)) { 3739 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3740 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3741 } 3742 3743 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3744 BNX_DEV_INFO_BC_REV); 3745 3746 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3747 3748 /* Enable DMA */ 3749 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3750 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3751 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3752 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3753 } 3754 3755 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3756 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3757 3758 /* Enable link state change interrupt generation. */ 3759 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3760 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3761 BNX_MISC_ENABLE_DEFAULT_XI); 3762 } else 3763 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3764 3765 /* Enable all remaining blocks in the MAC. */ 3766 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3767 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3768 DELAY(20); 3769 3770 bnx_blockinit_exit: 3771 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3772 3773 return rc; 3774 } 3775 3776 static int 3777 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3778 uint16_t *chain_prod, uint32_t *prod_bseq) 3779 { 3780 bus_dmamap_t map; 3781 struct rx_bd *rxbd; 3782 uint32_t addr; 3783 int i; 3784 #ifdef BNX_DEBUG 3785 uint16_t debug_chain_prod = *chain_prod; 3786 #endif 3787 uint16_t first_chain_prod; 3788 3789 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3790 3791 /* Map the mbuf cluster into device memory. */ 3792 map = sc->rx_mbuf_map[*chain_prod]; 3793 first_chain_prod = *chain_prod; 3794 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3795 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3796 __FILE__, __LINE__); 3797 3798 m_freem(m_new); 3799 3800 DBRUNIF(1, sc->rx_mbuf_alloc--); 3801 3802 return ENOBUFS; 3803 } 3804 /* Make sure there is room in the receive chain. */ 3805 if (map->dm_nsegs > sc->free_rx_bd) { 3806 bus_dmamap_unload(sc->bnx_dmatag, map); 3807 m_freem(m_new); 3808 return EFBIG; 3809 } 3810 #ifdef BNX_DEBUG 3811 /* Track the distribution of buffer segments. */ 3812 sc->rx_mbuf_segs[map->dm_nsegs]++; 3813 #endif 3814 3815 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3816 BUS_DMASYNC_PREREAD); 3817 3818 /* Update some debug statistics counters */ 3819 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3820 sc->rx_low_watermark = sc->free_rx_bd); 3821 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3822 3823 /* 3824 * Setup the rx_bd for the first segment 3825 */ 3826 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3827 3828 addr = (uint32_t)map->dm_segs[0].ds_addr; 3829 rxbd->rx_bd_haddr_lo = addr; 3830 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3831 rxbd->rx_bd_haddr_hi = addr; 3832 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3833 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3834 *prod_bseq += map->dm_segs[0].ds_len; 3835 bus_dmamap_sync(sc->bnx_dmatag, 3836 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3837 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3838 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3839 3840 for (i = 1; i < map->dm_nsegs; i++) { 3841 *prod = NEXT_RX_BD(*prod); 3842 *chain_prod = RX_CHAIN_IDX(*prod); 3843 3844 rxbd = 3845 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3846 3847 addr = (uint32_t)map->dm_segs[i].ds_addr; 3848 rxbd->rx_bd_haddr_lo = addr; 3849 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3850 rxbd->rx_bd_haddr_hi = addr; 3851 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3852 rxbd->rx_bd_flags = 0; 3853 *prod_bseq += map->dm_segs[i].ds_len; 3854 bus_dmamap_sync(sc->bnx_dmatag, 3855 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3856 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3857 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3858 } 3859 3860 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3861 bus_dmamap_sync(sc->bnx_dmatag, 3862 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3863 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3864 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3865 3866 /* 3867 * Save the mbuf, adjust the map pointer (swap map for first and 3868 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3869 * and update our counter. 3870 */ 3871 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3872 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3873 sc->rx_mbuf_map[*chain_prod] = map; 3874 sc->free_rx_bd -= map->dm_nsegs; 3875 3876 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3877 map->dm_nsegs)); 3878 *prod = NEXT_RX_BD(*prod); 3879 *chain_prod = RX_CHAIN_IDX(*prod); 3880 3881 return 0; 3882 } 3883 3884 /****************************************************************************/ 3885 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3886 /* */ 3887 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3888 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3889 /* necessary. */ 3890 /* */ 3891 /* Returns: */ 3892 /* 0 for success, positive value for failure. */ 3893 /****************************************************************************/ 3894 int 3895 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3896 uint16_t *chain_prod, uint32_t *prod_bseq) 3897 { 3898 struct mbuf *m_new = NULL; 3899 int rc = 0; 3900 uint16_t min_free_bd; 3901 3902 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3903 __func__); 3904 3905 /* Make sure the inputs are valid. */ 3906 DBRUNIF((*chain_prod > MAX_RX_BD), 3907 aprint_error_dev(sc->bnx_dev, 3908 "RX producer out of range: 0x%04X > 0x%04X\n", 3909 *chain_prod, (uint16_t)MAX_RX_BD)); 3910 3911 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3912 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3913 *prod_bseq); 3914 3915 /* try to get in as many mbufs as possible */ 3916 if (sc->mbuf_alloc_size == MCLBYTES) 3917 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3918 else 3919 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3920 while (sc->free_rx_bd >= min_free_bd) { 3921 /* Simulate an mbuf allocation failure. */ 3922 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3923 aprint_error_dev(sc->bnx_dev, 3924 "Simulating mbuf allocation failure.\n"); 3925 sc->mbuf_sim_alloc_failed++; 3926 rc = ENOBUFS; 3927 goto bnx_get_buf_exit); 3928 3929 /* This is a new mbuf allocation. */ 3930 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3931 if (m_new == NULL) { 3932 DBPRINT(sc, BNX_WARN, 3933 "%s(%d): RX mbuf header allocation failed!\n", 3934 __FILE__, __LINE__); 3935 3936 sc->mbuf_alloc_failed++; 3937 3938 rc = ENOBUFS; 3939 goto bnx_get_buf_exit; 3940 } 3941 3942 DBRUNIF(1, sc->rx_mbuf_alloc++); 3943 3944 /* Simulate an mbuf cluster allocation failure. */ 3945 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3946 m_freem(m_new); 3947 sc->rx_mbuf_alloc--; 3948 sc->mbuf_alloc_failed++; 3949 sc->mbuf_sim_alloc_failed++; 3950 rc = ENOBUFS; 3951 goto bnx_get_buf_exit); 3952 3953 if (sc->mbuf_alloc_size == MCLBYTES) 3954 MCLGET(m_new, M_DONTWAIT); 3955 else 3956 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3957 M_DONTWAIT); 3958 if (!(m_new->m_flags & M_EXT)) { 3959 DBPRINT(sc, BNX_WARN, 3960 "%s(%d): RX mbuf chain allocation failed!\n", 3961 __FILE__, __LINE__); 3962 3963 m_freem(m_new); 3964 3965 DBRUNIF(1, sc->rx_mbuf_alloc--); 3966 sc->mbuf_alloc_failed++; 3967 3968 rc = ENOBUFS; 3969 goto bnx_get_buf_exit; 3970 } 3971 3972 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3973 if (rc != 0) 3974 goto bnx_get_buf_exit; 3975 } 3976 3977 bnx_get_buf_exit: 3978 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3979 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3980 *chain_prod, *prod_bseq); 3981 3982 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3983 __func__); 3984 3985 return rc; 3986 } 3987 3988 void 3989 bnx_alloc_pkts(struct work * unused, void * arg) 3990 { 3991 struct bnx_softc *sc = arg; 3992 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3993 struct bnx_pkt *pkt; 3994 int i, s; 3995 3996 for (i = 0; i < 4; i++) { /* magic! */ 3997 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 3998 if (pkt == NULL) 3999 break; 4000 4001 if (bus_dmamap_create(sc->bnx_dmatag, 4002 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4003 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4004 &pkt->pkt_dmamap) != 0) 4005 goto put; 4006 4007 if (!ISSET(ifp->if_flags, IFF_UP)) 4008 goto stopping; 4009 4010 mutex_enter(&sc->tx_pkt_mtx); 4011 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4012 sc->tx_pkt_count++; 4013 mutex_exit(&sc->tx_pkt_mtx); 4014 } 4015 4016 mutex_enter(&sc->tx_pkt_mtx); 4017 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4018 mutex_exit(&sc->tx_pkt_mtx); 4019 4020 /* fire-up TX now that allocations have been done */ 4021 s = splnet(); 4022 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4023 bnx_start(ifp); 4024 splx(s); 4025 4026 return; 4027 4028 stopping: 4029 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4030 put: 4031 pool_put(bnx_tx_pool, pkt); 4032 return; 4033 } 4034 4035 /****************************************************************************/ 4036 /* Initialize the TX context memory. */ 4037 /* */ 4038 /* Returns: */ 4039 /* Nothing */ 4040 /****************************************************************************/ 4041 void 4042 bnx_init_tx_context(struct bnx_softc *sc) 4043 { 4044 uint32_t val; 4045 4046 /* Initialize the context ID for an L2 TX chain. */ 4047 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4048 /* Set the CID type to support an L2 connection. */ 4049 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4050 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4051 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4052 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4053 4054 /* Point the hardware to the first page in the chain. */ 4055 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4056 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4057 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4058 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4059 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4060 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4061 } else { 4062 /* Set the CID type to support an L2 connection. */ 4063 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4064 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4065 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4066 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4067 4068 /* Point the hardware to the first page in the chain. */ 4069 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4070 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4071 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4072 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4073 } 4074 } 4075 4076 4077 /****************************************************************************/ 4078 /* Allocate memory and initialize the TX data structures. */ 4079 /* */ 4080 /* Returns: */ 4081 /* 0 for success, positive value for failure. */ 4082 /****************************************************************************/ 4083 int 4084 bnx_init_tx_chain(struct bnx_softc *sc) 4085 { 4086 struct tx_bd *txbd; 4087 uint32_t addr; 4088 int i, rc = 0; 4089 4090 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4091 4092 /* Force an allocation of some dmamaps for tx up front */ 4093 bnx_alloc_pkts(NULL, sc); 4094 4095 /* Set the initial TX producer/consumer indices. */ 4096 sc->tx_prod = 0; 4097 sc->tx_cons = 0; 4098 sc->tx_prod_bseq = 0; 4099 sc->used_tx_bd = 0; 4100 sc->max_tx_bd = USABLE_TX_BD; 4101 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4102 DBRUNIF(1, sc->tx_full_count = 0); 4103 4104 /* 4105 * The NetXtreme II supports a linked-list structure called 4106 * a Buffer Descriptor Chain (or BD chain). A BD chain 4107 * consists of a series of 1 or more chain pages, each of which 4108 * consists of a fixed number of BD entries. 4109 * The last BD entry on each page is a pointer to the next page 4110 * in the chain, and the last pointer in the BD chain 4111 * points back to the beginning of the chain. 4112 */ 4113 4114 /* Set the TX next pointer chain entries. */ 4115 for (i = 0; i < TX_PAGES; i++) { 4116 int j; 4117 4118 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4119 4120 /* Check if we've reached the last page. */ 4121 if (i == (TX_PAGES - 1)) 4122 j = 0; 4123 else 4124 j = i + 1; 4125 4126 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4127 txbd->tx_bd_haddr_lo = addr; 4128 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4129 txbd->tx_bd_haddr_hi = addr; 4130 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4131 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4132 } 4133 4134 /* 4135 * Initialize the context ID for an L2 TX chain. 4136 */ 4137 bnx_init_tx_context(sc); 4138 4139 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4140 4141 return rc; 4142 } 4143 4144 /****************************************************************************/ 4145 /* Free memory and clear the TX data structures. */ 4146 /* */ 4147 /* Returns: */ 4148 /* Nothing. */ 4149 /****************************************************************************/ 4150 void 4151 bnx_free_tx_chain(struct bnx_softc *sc) 4152 { 4153 struct bnx_pkt *pkt; 4154 int i; 4155 4156 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4157 4158 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4159 mutex_enter(&sc->tx_pkt_mtx); 4160 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4161 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4162 mutex_exit(&sc->tx_pkt_mtx); 4163 4164 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4165 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4166 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4167 4168 m_freem(pkt->pkt_mbuf); 4169 DBRUNIF(1, sc->tx_mbuf_alloc--); 4170 4171 mutex_enter(&sc->tx_pkt_mtx); 4172 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4173 } 4174 4175 /* Destroy all the dmamaps we allocated for TX */ 4176 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4177 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4178 sc->tx_pkt_count--; 4179 mutex_exit(&sc->tx_pkt_mtx); 4180 4181 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4182 pool_put(bnx_tx_pool, pkt); 4183 4184 mutex_enter(&sc->tx_pkt_mtx); 4185 } 4186 mutex_exit(&sc->tx_pkt_mtx); 4187 4188 4189 4190 /* Clear each TX chain page. */ 4191 for (i = 0; i < TX_PAGES; i++) { 4192 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4193 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4194 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4195 } 4196 4197 sc->used_tx_bd = 0; 4198 4199 /* Check if we lost any mbufs in the process. */ 4200 DBRUNIF((sc->tx_mbuf_alloc), 4201 aprint_error_dev(sc->bnx_dev, 4202 "Memory leak! Lost %d mbufs from tx chain!\n", 4203 sc->tx_mbuf_alloc)); 4204 4205 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4206 } 4207 4208 /****************************************************************************/ 4209 /* Initialize the RX context memory. */ 4210 /* */ 4211 /* Returns: */ 4212 /* Nothing */ 4213 /****************************************************************************/ 4214 void 4215 bnx_init_rx_context(struct bnx_softc *sc) 4216 { 4217 uint32_t val; 4218 4219 /* Initialize the context ID for an L2 RX chain. */ 4220 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4221 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4222 4223 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4224 val |= 0x000000ff; 4225 4226 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4227 4228 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4229 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4230 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4231 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4232 } 4233 4234 /* Point the hardware to the first page in the chain. */ 4235 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4236 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4237 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4238 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4239 } 4240 4241 /****************************************************************************/ 4242 /* Allocate memory and initialize the RX data structures. */ 4243 /* */ 4244 /* Returns: */ 4245 /* 0 for success, positive value for failure. */ 4246 /****************************************************************************/ 4247 int 4248 bnx_init_rx_chain(struct bnx_softc *sc) 4249 { 4250 struct rx_bd *rxbd; 4251 int i, rc = 0; 4252 uint16_t prod, chain_prod; 4253 uint32_t prod_bseq, addr; 4254 4255 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4256 4257 /* Initialize the RX producer and consumer indices. */ 4258 sc->rx_prod = 0; 4259 sc->rx_cons = 0; 4260 sc->rx_prod_bseq = 0; 4261 sc->free_rx_bd = USABLE_RX_BD; 4262 sc->max_rx_bd = USABLE_RX_BD; 4263 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4264 DBRUNIF(1, sc->rx_empty_count = 0); 4265 4266 /* Initialize the RX next pointer chain entries. */ 4267 for (i = 0; i < RX_PAGES; i++) { 4268 int j; 4269 4270 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4271 4272 /* Check if we've reached the last page. */ 4273 if (i == (RX_PAGES - 1)) 4274 j = 0; 4275 else 4276 j = i + 1; 4277 4278 /* Setup the chain page pointers. */ 4279 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4280 rxbd->rx_bd_haddr_hi = addr; 4281 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4282 rxbd->rx_bd_haddr_lo = addr; 4283 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4284 0, BNX_RX_CHAIN_PAGE_SZ, 4285 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4286 } 4287 4288 /* Allocate mbuf clusters for the rx_bd chain. */ 4289 prod = prod_bseq = 0; 4290 chain_prod = RX_CHAIN_IDX(prod); 4291 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4292 BNX_PRINTF(sc, 4293 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4294 } 4295 4296 /* Save the RX chain producer index. */ 4297 sc->rx_prod = prod; 4298 sc->rx_prod_bseq = prod_bseq; 4299 4300 for (i = 0; i < RX_PAGES; i++) 4301 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4302 sc->rx_bd_chain_map[i]->dm_mapsize, 4303 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4304 4305 /* Tell the chip about the waiting rx_bd's. */ 4306 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4307 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4308 4309 bnx_init_rx_context(sc); 4310 4311 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4312 4313 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4314 4315 return rc; 4316 } 4317 4318 /****************************************************************************/ 4319 /* Free memory and clear the RX data structures. */ 4320 /* */ 4321 /* Returns: */ 4322 /* Nothing. */ 4323 /****************************************************************************/ 4324 void 4325 bnx_free_rx_chain(struct bnx_softc *sc) 4326 { 4327 int i; 4328 4329 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4330 4331 /* Free any mbufs still in the RX mbuf chain. */ 4332 for (i = 0; i < TOTAL_RX_BD; i++) { 4333 if (sc->rx_mbuf_ptr[i] != NULL) { 4334 if (sc->rx_mbuf_map[i] != NULL) { 4335 bus_dmamap_sync(sc->bnx_dmatag, 4336 sc->rx_mbuf_map[i], 0, 4337 sc->rx_mbuf_map[i]->dm_mapsize, 4338 BUS_DMASYNC_POSTREAD); 4339 bus_dmamap_unload(sc->bnx_dmatag, 4340 sc->rx_mbuf_map[i]); 4341 } 4342 m_freem(sc->rx_mbuf_ptr[i]); 4343 sc->rx_mbuf_ptr[i] = NULL; 4344 DBRUNIF(1, sc->rx_mbuf_alloc--); 4345 } 4346 } 4347 4348 /* Clear each RX chain page. */ 4349 for (i = 0; i < RX_PAGES; i++) 4350 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4351 4352 sc->free_rx_bd = sc->max_rx_bd; 4353 4354 /* Check if we lost any mbufs in the process. */ 4355 DBRUNIF((sc->rx_mbuf_alloc), 4356 aprint_error_dev(sc->bnx_dev, 4357 "Memory leak! Lost %d mbufs from rx chain!\n", 4358 sc->rx_mbuf_alloc)); 4359 4360 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4361 } 4362 4363 /****************************************************************************/ 4364 /* Reports current media status. */ 4365 /* */ 4366 /* Returns: */ 4367 /* Nothing. */ 4368 /****************************************************************************/ 4369 void 4370 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4371 { 4372 struct bnx_softc *sc; 4373 struct mii_data *mii; 4374 int s; 4375 4376 sc = ifp->if_softc; 4377 4378 s = splnet(); 4379 4380 mii = &sc->bnx_mii; 4381 4382 mii_pollstat(mii); 4383 ifmr->ifm_status = mii->mii_media_status; 4384 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4385 sc->bnx_flowflags; 4386 4387 splx(s); 4388 } 4389 4390 /****************************************************************************/ 4391 /* Handles PHY generated interrupt events. */ 4392 /* */ 4393 /* Returns: */ 4394 /* Nothing. */ 4395 /****************************************************************************/ 4396 void 4397 bnx_phy_intr(struct bnx_softc *sc) 4398 { 4399 uint32_t new_link_state, old_link_state; 4400 4401 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4402 BUS_DMASYNC_POSTREAD); 4403 new_link_state = sc->status_block->status_attn_bits & 4404 STATUS_ATTN_BITS_LINK_STATE; 4405 old_link_state = sc->status_block->status_attn_bits_ack & 4406 STATUS_ATTN_BITS_LINK_STATE; 4407 4408 /* Handle any changes if the link state has changed. */ 4409 if (new_link_state != old_link_state) { 4410 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4411 4412 callout_stop(&sc->bnx_timeout); 4413 bnx_tick(sc); 4414 4415 /* Update the status_attn_bits_ack field in the status block. */ 4416 if (new_link_state) { 4417 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4418 STATUS_ATTN_BITS_LINK_STATE); 4419 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4420 } else { 4421 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4422 STATUS_ATTN_BITS_LINK_STATE); 4423 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4424 } 4425 } 4426 4427 /* Acknowledge the link change interrupt. */ 4428 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4429 } 4430 4431 /****************************************************************************/ 4432 /* Handles received frame interrupt events. */ 4433 /* */ 4434 /* Returns: */ 4435 /* Nothing. */ 4436 /****************************************************************************/ 4437 void 4438 bnx_rx_intr(struct bnx_softc *sc) 4439 { 4440 struct status_block *sblk = sc->status_block; 4441 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4442 uint16_t hw_cons, sw_cons, sw_chain_cons; 4443 uint16_t sw_prod, sw_chain_prod; 4444 uint32_t sw_prod_bseq; 4445 struct l2_fhdr *l2fhdr; 4446 int i; 4447 4448 DBRUNIF(1, sc->rx_interrupts++); 4449 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4450 BUS_DMASYNC_POSTREAD); 4451 4452 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4453 for (i = 0; i < RX_PAGES; i++) 4454 bus_dmamap_sync(sc->bnx_dmatag, 4455 sc->rx_bd_chain_map[i], 0, 4456 sc->rx_bd_chain_map[i]->dm_mapsize, 4457 BUS_DMASYNC_POSTWRITE); 4458 4459 /* Get the hardware's view of the RX consumer index. */ 4460 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4461 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4462 hw_cons++; 4463 4464 /* Get working copies of the driver's view of the RX indices. */ 4465 sw_cons = sc->rx_cons; 4466 sw_prod = sc->rx_prod; 4467 sw_prod_bseq = sc->rx_prod_bseq; 4468 4469 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4470 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4471 __func__, sw_prod, sw_cons, sw_prod_bseq); 4472 4473 /* Prevent speculative reads from getting ahead of the status block. */ 4474 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4475 BUS_SPACE_BARRIER_READ); 4476 4477 /* Update some debug statistics counters */ 4478 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4479 sc->rx_low_watermark = sc->free_rx_bd); 4480 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4481 4482 /* 4483 * Scan through the receive chain as long 4484 * as there is work to do. 4485 */ 4486 while (sw_cons != hw_cons) { 4487 struct mbuf *m; 4488 struct rx_bd *rxbd __diagused; 4489 unsigned int len; 4490 uint32_t status; 4491 4492 /* Convert the producer/consumer indices to an actual 4493 * rx_bd index. 4494 */ 4495 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4496 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4497 4498 /* Get the used rx_bd. */ 4499 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4500 sc->free_rx_bd++; 4501 4502 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4503 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4504 4505 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4506 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4507 #ifdef DIAGNOSTIC 4508 /* Validate that this is the last rx_bd. */ 4509 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4510 printf("%s: Unexpected mbuf found in " 4511 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4512 sw_chain_cons); 4513 } 4514 #endif 4515 4516 /* DRC - ToDo: If the received packet is small, say 4517 * less than 128 bytes, allocate a new mbuf 4518 * here, copy the data to that mbuf, and 4519 * recycle the mapped jumbo frame. 4520 */ 4521 4522 /* Unmap the mbuf from DMA space. */ 4523 #ifdef DIAGNOSTIC 4524 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4525 printf("invalid map sw_cons 0x%x " 4526 "sw_prod 0x%x " 4527 "sw_chain_cons 0x%x " 4528 "sw_chain_prod 0x%x " 4529 "hw_cons 0x%x " 4530 "TOTAL_RX_BD_PER_PAGE 0x%x " 4531 "TOTAL_RX_BD 0x%x\n", 4532 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4533 hw_cons, 4534 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4535 } 4536 #endif 4537 bus_dmamap_sync(sc->bnx_dmatag, 4538 sc->rx_mbuf_map[sw_chain_cons], 0, 4539 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4540 BUS_DMASYNC_POSTREAD); 4541 bus_dmamap_unload(sc->bnx_dmatag, 4542 sc->rx_mbuf_map[sw_chain_cons]); 4543 4544 /* Remove the mbuf from the driver's chain. */ 4545 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4546 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4547 4548 /* 4549 * Frames received on the NetXteme II are prepended 4550 * with the l2_fhdr structure which provides status 4551 * information about the received frame (including 4552 * VLAN tags and checksum info) and are also 4553 * automatically adjusted to align the IP header 4554 * (i.e. two null bytes are inserted before the 4555 * Ethernet header). 4556 */ 4557 l2fhdr = mtod(m, struct l2_fhdr *); 4558 4559 len = l2fhdr->l2_fhdr_pkt_len; 4560 status = l2fhdr->l2_fhdr_status; 4561 4562 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4563 aprint_error("Simulating l2_fhdr status error.\n"); 4564 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4565 4566 /* Watch for unusual sized frames. */ 4567 DBRUNIF(((len < BNX_MIN_MTU) || 4568 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4569 aprint_error_dev(sc->bnx_dev, 4570 "Unusual frame size found. " 4571 "Min(%d), Actual(%d), Max(%d)\n", 4572 (int)BNX_MIN_MTU, len, 4573 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4574 4575 bnx_dump_mbuf(sc, m); 4576 bnx_breakpoint(sc)); 4577 4578 len -= ETHER_CRC_LEN; 4579 4580 /* Check the received frame for errors. */ 4581 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4582 L2_FHDR_ERRORS_PHY_DECODE | 4583 L2_FHDR_ERRORS_ALIGNMENT | 4584 L2_FHDR_ERRORS_TOO_SHORT | 4585 L2_FHDR_ERRORS_GIANT_FRAME)) || 4586 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4587 len > 4588 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4589 ifp->if_ierrors++; 4590 DBRUNIF(1, sc->l2fhdr_status_errors++); 4591 4592 /* Reuse the mbuf for a new frame. */ 4593 if (bnx_add_buf(sc, m, &sw_prod, 4594 &sw_chain_prod, &sw_prod_bseq)) { 4595 DBRUNIF(1, bnx_breakpoint(sc)); 4596 panic("%s: Can't reuse RX mbuf!\n", 4597 device_xname(sc->bnx_dev)); 4598 } 4599 continue; 4600 } 4601 4602 /* 4603 * Get a new mbuf for the rx_bd. If no new 4604 * mbufs are available then reuse the current mbuf, 4605 * log an ierror on the interface, and generate 4606 * an error in the system log. 4607 */ 4608 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4609 &sw_prod_bseq)) { 4610 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4611 "Failed to allocate " 4612 "new mbuf, incoming frame dropped!\n")); 4613 4614 ifp->if_ierrors++; 4615 4616 /* Try and reuse the exisitng mbuf. */ 4617 if (bnx_add_buf(sc, m, &sw_prod, 4618 &sw_chain_prod, &sw_prod_bseq)) { 4619 DBRUNIF(1, bnx_breakpoint(sc)); 4620 panic("%s: Double mbuf allocation " 4621 "failure!", 4622 device_xname(sc->bnx_dev)); 4623 } 4624 continue; 4625 } 4626 4627 /* Skip over the l2_fhdr when passing the data up 4628 * the stack. 4629 */ 4630 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4631 4632 /* Adjust the pckt length to match the received data. */ 4633 m->m_pkthdr.len = m->m_len = len; 4634 4635 /* Send the packet to the appropriate interface. */ 4636 m_set_rcvif(m, ifp); 4637 4638 DBRUN(BNX_VERBOSE_RECV, 4639 struct ether_header *eh; 4640 eh = mtod(m, struct ether_header *); 4641 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4642 __func__, ether_sprintf(eh->ether_dhost), 4643 ether_sprintf(eh->ether_shost), 4644 htons(eh->ether_type))); 4645 4646 /* Validate the checksum. */ 4647 4648 /* Check for an IP datagram. */ 4649 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4650 /* Check if the IP checksum is valid. */ 4651 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4652 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4653 #ifdef BNX_DEBUG 4654 else 4655 DBPRINT(sc, BNX_WARN_SEND, 4656 "%s(): Invalid IP checksum " 4657 "= 0x%04X!\n", 4658 __func__, 4659 l2fhdr->l2_fhdr_ip_xsum 4660 ); 4661 #endif 4662 } 4663 4664 /* Check for a valid TCP/UDP frame. */ 4665 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4666 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4667 /* Check for a good TCP/UDP checksum. */ 4668 if ((status & 4669 (L2_FHDR_ERRORS_TCP_XSUM | 4670 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4671 m->m_pkthdr.csum_flags |= 4672 M_CSUM_TCPv4 | 4673 M_CSUM_UDPv4; 4674 } else { 4675 DBPRINT(sc, BNX_WARN_SEND, 4676 "%s(): Invalid TCP/UDP " 4677 "checksum = 0x%04X!\n", 4678 __func__, 4679 l2fhdr->l2_fhdr_tcp_udp_xsum); 4680 } 4681 } 4682 4683 /* 4684 * If we received a packet with a vlan tag, 4685 * attach that information to the packet. 4686 */ 4687 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4688 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4689 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4690 } 4691 4692 /* Pass the mbuf off to the upper layers. */ 4693 4694 DBPRINT(sc, BNX_VERBOSE_RECV, 4695 "%s(): Passing received frame up.\n", __func__); 4696 if_percpuq_enqueue(ifp->if_percpuq, m); 4697 DBRUNIF(1, sc->rx_mbuf_alloc--); 4698 4699 } 4700 4701 sw_cons = NEXT_RX_BD(sw_cons); 4702 4703 /* Refresh hw_cons to see if there's new work */ 4704 if (sw_cons == hw_cons) { 4705 hw_cons = sc->hw_rx_cons = 4706 sblk->status_rx_quick_consumer_index0; 4707 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4708 USABLE_RX_BD_PER_PAGE) 4709 hw_cons++; 4710 } 4711 4712 /* Prevent speculative reads from getting ahead of 4713 * the status block. 4714 */ 4715 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4716 BUS_SPACE_BARRIER_READ); 4717 } 4718 4719 for (i = 0; i < RX_PAGES; i++) 4720 bus_dmamap_sync(sc->bnx_dmatag, 4721 sc->rx_bd_chain_map[i], 0, 4722 sc->rx_bd_chain_map[i]->dm_mapsize, 4723 BUS_DMASYNC_PREWRITE); 4724 4725 sc->rx_cons = sw_cons; 4726 sc->rx_prod = sw_prod; 4727 sc->rx_prod_bseq = sw_prod_bseq; 4728 4729 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4730 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4731 4732 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4733 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4734 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4735 } 4736 4737 /****************************************************************************/ 4738 /* Handles transmit completion interrupt events. */ 4739 /* */ 4740 /* Returns: */ 4741 /* Nothing. */ 4742 /****************************************************************************/ 4743 void 4744 bnx_tx_intr(struct bnx_softc *sc) 4745 { 4746 struct status_block *sblk = sc->status_block; 4747 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4748 struct bnx_pkt *pkt; 4749 bus_dmamap_t map; 4750 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4751 4752 DBRUNIF(1, sc->tx_interrupts++); 4753 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4754 BUS_DMASYNC_POSTREAD); 4755 4756 /* Get the hardware's view of the TX consumer index. */ 4757 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4758 4759 /* Skip to the next entry if this is a chain page pointer. */ 4760 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4761 hw_tx_cons++; 4762 4763 sw_tx_cons = sc->tx_cons; 4764 4765 /* Prevent speculative reads from getting ahead of the status block. */ 4766 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4767 BUS_SPACE_BARRIER_READ); 4768 4769 /* Cycle through any completed TX chain page entries. */ 4770 while (sw_tx_cons != hw_tx_cons) { 4771 #ifdef BNX_DEBUG 4772 struct tx_bd *txbd = NULL; 4773 #endif 4774 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4775 4776 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4777 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4778 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4779 4780 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4781 aprint_error_dev(sc->bnx_dev, 4782 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4783 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4784 4785 DBRUNIF(1, txbd = &sc->tx_bd_chain 4786 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4787 4788 DBRUNIF((txbd == NULL), 4789 aprint_error_dev(sc->bnx_dev, 4790 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4791 bnx_breakpoint(sc)); 4792 4793 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4794 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4795 4796 4797 mutex_enter(&sc->tx_pkt_mtx); 4798 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4799 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4800 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4801 mutex_exit(&sc->tx_pkt_mtx); 4802 /* 4803 * Free the associated mbuf. Remember 4804 * that only the last tx_bd of a packet 4805 * has an mbuf pointer and DMA map. 4806 */ 4807 map = pkt->pkt_dmamap; 4808 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4809 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4810 bus_dmamap_unload(sc->bnx_dmatag, map); 4811 4812 m_freem(pkt->pkt_mbuf); 4813 DBRUNIF(1, sc->tx_mbuf_alloc--); 4814 4815 ifp->if_opackets++; 4816 4817 mutex_enter(&sc->tx_pkt_mtx); 4818 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4819 } 4820 mutex_exit(&sc->tx_pkt_mtx); 4821 4822 sc->used_tx_bd--; 4823 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4824 __FILE__, __LINE__, sc->used_tx_bd); 4825 4826 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4827 4828 /* Refresh hw_cons to see if there's new work. */ 4829 hw_tx_cons = sc->hw_tx_cons = 4830 sblk->status_tx_quick_consumer_index0; 4831 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4832 USABLE_TX_BD_PER_PAGE) 4833 hw_tx_cons++; 4834 4835 /* Prevent speculative reads from getting ahead of 4836 * the status block. 4837 */ 4838 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4839 BUS_SPACE_BARRIER_READ); 4840 } 4841 4842 /* Clear the TX timeout timer. */ 4843 ifp->if_timer = 0; 4844 4845 /* Clear the tx hardware queue full flag. */ 4846 if (sc->used_tx_bd < sc->max_tx_bd) { 4847 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4848 aprint_debug_dev(sc->bnx_dev, 4849 "Open TX chain! %d/%d (used/total)\n", 4850 sc->used_tx_bd, sc->max_tx_bd)); 4851 ifp->if_flags &= ~IFF_OACTIVE; 4852 } 4853 4854 sc->tx_cons = sw_tx_cons; 4855 } 4856 4857 /****************************************************************************/ 4858 /* Disables interrupt generation. */ 4859 /* */ 4860 /* Returns: */ 4861 /* Nothing. */ 4862 /****************************************************************************/ 4863 void 4864 bnx_disable_intr(struct bnx_softc *sc) 4865 { 4866 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4867 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4868 } 4869 4870 /****************************************************************************/ 4871 /* Enables interrupt generation. */ 4872 /* */ 4873 /* Returns: */ 4874 /* Nothing. */ 4875 /****************************************************************************/ 4876 void 4877 bnx_enable_intr(struct bnx_softc *sc) 4878 { 4879 uint32_t val; 4880 4881 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4882 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4883 4884 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4885 sc->last_status_idx); 4886 4887 val = REG_RD(sc, BNX_HC_COMMAND); 4888 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4889 } 4890 4891 /****************************************************************************/ 4892 /* Handles controller initialization. */ 4893 /* */ 4894 /****************************************************************************/ 4895 int 4896 bnx_init(struct ifnet *ifp) 4897 { 4898 struct bnx_softc *sc = ifp->if_softc; 4899 uint32_t ether_mtu; 4900 int s, error = 0; 4901 4902 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4903 4904 s = splnet(); 4905 4906 bnx_stop(ifp, 0); 4907 4908 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4909 aprint_error_dev(sc->bnx_dev, 4910 "Controller reset failed!\n"); 4911 goto bnx_init_exit; 4912 } 4913 4914 if ((error = bnx_chipinit(sc)) != 0) { 4915 aprint_error_dev(sc->bnx_dev, 4916 "Controller initialization failed!\n"); 4917 goto bnx_init_exit; 4918 } 4919 4920 if ((error = bnx_blockinit(sc)) != 0) { 4921 aprint_error_dev(sc->bnx_dev, 4922 "Block initialization failed!\n"); 4923 goto bnx_init_exit; 4924 } 4925 4926 /* Calculate and program the Ethernet MRU size. */ 4927 if (ifp->if_mtu <= ETHERMTU) { 4928 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4929 sc->mbuf_alloc_size = MCLBYTES; 4930 } else { 4931 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4932 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4933 } 4934 4935 4936 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 4937 4938 /* 4939 * Program the MRU and enable Jumbo frame 4940 * support. 4941 */ 4942 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4943 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4944 4945 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4946 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4947 4948 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4949 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4950 sc->mbuf_alloc_size, sc->max_frame_size); 4951 4952 /* Program appropriate promiscuous/multicast filtering. */ 4953 bnx_iff(sc); 4954 4955 /* Init RX buffer descriptor chain. */ 4956 bnx_init_rx_chain(sc); 4957 4958 /* Init TX buffer descriptor chain. */ 4959 bnx_init_tx_chain(sc); 4960 4961 /* Enable host interrupts. */ 4962 bnx_enable_intr(sc); 4963 4964 if ((error = ether_mediachange(ifp)) != 0) 4965 goto bnx_init_exit; 4966 4967 SET(ifp->if_flags, IFF_RUNNING); 4968 CLR(ifp->if_flags, IFF_OACTIVE); 4969 4970 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4971 4972 bnx_init_exit: 4973 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4974 4975 splx(s); 4976 4977 return error; 4978 } 4979 4980 /****************************************************************************/ 4981 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4982 /* memory visible to the controller. */ 4983 /* */ 4984 /* Returns: */ 4985 /* 0 for success, positive value for failure. */ 4986 /****************************************************************************/ 4987 int 4988 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 4989 { 4990 struct bnx_pkt *pkt; 4991 bus_dmamap_t map; 4992 struct tx_bd *txbd = NULL; 4993 uint16_t vlan_tag = 0, flags = 0; 4994 uint16_t chain_prod, prod; 4995 #ifdef BNX_DEBUG 4996 uint16_t debug_prod; 4997 #endif 4998 uint32_t addr, prod_bseq; 4999 int i, error; 5000 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 5001 5002 mutex_enter(&sc->tx_pkt_mtx); 5003 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5004 if (pkt == NULL) { 5005 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5006 mutex_exit(&sc->tx_pkt_mtx); 5007 return ENETDOWN; 5008 } 5009 5010 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5011 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5012 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 5013 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5014 } 5015 5016 mutex_exit(&sc->tx_pkt_mtx); 5017 return ENOMEM; 5018 } 5019 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5020 mutex_exit(&sc->tx_pkt_mtx); 5021 5022 /* Transfer any checksum offload flags to the bd. */ 5023 if (m->m_pkthdr.csum_flags) { 5024 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5025 flags |= TX_BD_FLAGS_IP_CKSUM; 5026 if (m->m_pkthdr.csum_flags & 5027 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5028 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5029 } 5030 5031 /* Transfer any VLAN tags to the bd. */ 5032 if (vlan_has_tag(m)) { 5033 flags |= TX_BD_FLAGS_VLAN_TAG; 5034 vlan_tag = vlan_get_tag(m); 5035 } 5036 5037 /* Map the mbuf into DMAable memory. */ 5038 prod = sc->tx_prod; 5039 chain_prod = TX_CHAIN_IDX(prod); 5040 map = pkt->pkt_dmamap; 5041 5042 /* Map the mbuf into our DMA address space. */ 5043 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5044 if (error != 0) { 5045 aprint_error_dev(sc->bnx_dev, 5046 "Error mapping mbuf into TX chain!\n"); 5047 sc->tx_dma_map_failures++; 5048 goto maperr; 5049 } 5050 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5051 BUS_DMASYNC_PREWRITE); 5052 /* Make sure there's room in the chain */ 5053 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5054 goto nospace; 5055 5056 /* prod points to an empty tx_bd at this point. */ 5057 prod_bseq = sc->tx_prod_bseq; 5058 #ifdef BNX_DEBUG 5059 debug_prod = chain_prod; 5060 #endif 5061 DBPRINT(sc, BNX_INFO_SEND, 5062 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5063 "prod_bseq = 0x%08X\n", 5064 __func__, prod, chain_prod, prod_bseq); 5065 5066 /* 5067 * Cycle through each mbuf segment that makes up 5068 * the outgoing frame, gathering the mapping info 5069 * for that segment and creating a tx_bd for the 5070 * mbuf. 5071 */ 5072 for (i = 0; i < map->dm_nsegs ; i++) { 5073 chain_prod = TX_CHAIN_IDX(prod); 5074 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5075 5076 addr = (uint32_t)map->dm_segs[i].ds_addr; 5077 txbd->tx_bd_haddr_lo = addr; 5078 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5079 txbd->tx_bd_haddr_hi = addr; 5080 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5081 txbd->tx_bd_vlan_tag = vlan_tag; 5082 txbd->tx_bd_flags = flags; 5083 prod_bseq += map->dm_segs[i].ds_len; 5084 if (i == 0) 5085 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5086 prod = NEXT_TX_BD(prod); 5087 } 5088 /* Set the END flag on the last TX buffer descriptor. */ 5089 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5090 5091 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5092 5093 DBPRINT(sc, BNX_INFO_SEND, 5094 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5095 "prod_bseq = 0x%08X\n", 5096 __func__, prod, chain_prod, prod_bseq); 5097 5098 pkt->pkt_mbuf = m; 5099 pkt->pkt_end_desc = chain_prod; 5100 5101 mutex_enter(&sc->tx_pkt_mtx); 5102 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5103 mutex_exit(&sc->tx_pkt_mtx); 5104 5105 sc->used_tx_bd += map->dm_nsegs; 5106 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5107 __FILE__, __LINE__, sc->used_tx_bd); 5108 5109 /* Update some debug statistics counters */ 5110 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5111 sc->tx_hi_watermark = sc->used_tx_bd); 5112 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5113 DBRUNIF(1, sc->tx_mbuf_alloc++); 5114 5115 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5116 map->dm_nsegs)); 5117 5118 /* prod points to the next free tx_bd at this point. */ 5119 sc->tx_prod = prod; 5120 sc->tx_prod_bseq = prod_bseq; 5121 5122 return 0; 5123 5124 5125 nospace: 5126 bus_dmamap_unload(sc->bnx_dmatag, map); 5127 maperr: 5128 mutex_enter(&sc->tx_pkt_mtx); 5129 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5130 mutex_exit(&sc->tx_pkt_mtx); 5131 5132 return ENOMEM; 5133 } 5134 5135 /****************************************************************************/ 5136 /* Main transmit routine. */ 5137 /* */ 5138 /* Returns: */ 5139 /* Nothing. */ 5140 /****************************************************************************/ 5141 void 5142 bnx_start(struct ifnet *ifp) 5143 { 5144 struct bnx_softc *sc = ifp->if_softc; 5145 struct mbuf *m_head = NULL; 5146 int count = 0; 5147 #ifdef BNX_DEBUG 5148 uint16_t tx_chain_prod; 5149 #endif 5150 5151 /* If there's no link or the transmit queue is empty then just exit. */ 5152 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5153 DBPRINT(sc, BNX_INFO_SEND, 5154 "%s(): output active or device not running.\n", __func__); 5155 goto bnx_start_exit; 5156 } 5157 5158 /* prod points to the next free tx_bd. */ 5159 #ifdef BNX_DEBUG 5160 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5161 #endif 5162 5163 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5164 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5165 "used_tx %d max_tx %d\n", 5166 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5167 sc->used_tx_bd, sc->max_tx_bd); 5168 5169 /* 5170 * Keep adding entries while there is space in the ring. 5171 */ 5172 while (sc->used_tx_bd < sc->max_tx_bd) { 5173 /* Check for any frames to send. */ 5174 IFQ_POLL(&ifp->if_snd, m_head); 5175 if (m_head == NULL) 5176 break; 5177 5178 /* 5179 * Pack the data into the transmit ring. If we 5180 * don't have room, set the OACTIVE flag to wait 5181 * for the NIC to drain the chain. 5182 */ 5183 if (bnx_tx_encap(sc, m_head)) { 5184 ifp->if_flags |= IFF_OACTIVE; 5185 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5186 "business! Total tx_bd used = %d\n", 5187 sc->used_tx_bd); 5188 break; 5189 } 5190 5191 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5192 count++; 5193 5194 /* Send a copy of the frame to any BPF listeners. */ 5195 bpf_mtap(ifp, m_head, BPF_D_OUT); 5196 } 5197 5198 if (count == 0) { 5199 /* no packets were dequeued */ 5200 DBPRINT(sc, BNX_VERBOSE_SEND, 5201 "%s(): No packets were dequeued\n", __func__); 5202 goto bnx_start_exit; 5203 } 5204 5205 /* Update the driver's counters. */ 5206 #ifdef BNX_DEBUG 5207 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5208 #endif 5209 5210 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5211 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5212 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5213 5214 /* Start the transmit. */ 5215 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5216 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5217 5218 /* Set the tx timeout. */ 5219 ifp->if_timer = BNX_TX_TIMEOUT; 5220 5221 bnx_start_exit: 5222 return; 5223 } 5224 5225 /****************************************************************************/ 5226 /* Handles any IOCTL calls from the operating system. */ 5227 /* */ 5228 /* Returns: */ 5229 /* 0 for success, positive value for failure. */ 5230 /****************************************************************************/ 5231 int 5232 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5233 { 5234 struct bnx_softc *sc = ifp->if_softc; 5235 struct ifreq *ifr = (struct ifreq *) data; 5236 struct mii_data *mii = &sc->bnx_mii; 5237 int s, error = 0; 5238 5239 s = splnet(); 5240 5241 switch (command) { 5242 case SIOCSIFFLAGS: 5243 if ((error = ifioctl_common(ifp, command, data)) != 0) 5244 break; 5245 /* XXX set an ifflags callback and let ether_ioctl 5246 * handle all of this. 5247 */ 5248 if (ISSET(ifp->if_flags, IFF_UP)) { 5249 if (ifp->if_flags & IFF_RUNNING) 5250 error = ENETRESET; 5251 else 5252 bnx_init(ifp); 5253 } else if (ifp->if_flags & IFF_RUNNING) 5254 bnx_stop(ifp, 1); 5255 break; 5256 5257 case SIOCSIFMEDIA: 5258 /* Flow control requires full-duplex mode. */ 5259 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5260 (ifr->ifr_media & IFM_FDX) == 0) 5261 ifr->ifr_media &= ~IFM_ETH_FMASK; 5262 5263 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5264 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5265 /* We can do both TXPAUSE and RXPAUSE. */ 5266 ifr->ifr_media |= 5267 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5268 } 5269 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5270 } 5271 /* FALLTHROUGH */ 5272 case SIOCGIFMEDIA: 5273 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5274 sc->bnx_phy_flags); 5275 5276 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5277 break; 5278 5279 default: 5280 error = ether_ioctl(ifp, command, data); 5281 } 5282 5283 if (error == ENETRESET) { 5284 if (ifp->if_flags & IFF_RUNNING) 5285 bnx_iff(sc); 5286 error = 0; 5287 } 5288 5289 splx(s); 5290 return error; 5291 } 5292 5293 /****************************************************************************/ 5294 /* Transmit timeout handler. */ 5295 /* */ 5296 /* Returns: */ 5297 /* Nothing. */ 5298 /****************************************************************************/ 5299 void 5300 bnx_watchdog(struct ifnet *ifp) 5301 { 5302 struct bnx_softc *sc = ifp->if_softc; 5303 5304 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5305 bnx_dump_status_block(sc)); 5306 /* 5307 * If we are in this routine because of pause frames, then 5308 * don't reset the hardware. 5309 */ 5310 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5311 return; 5312 5313 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5314 5315 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5316 5317 bnx_init(ifp); 5318 5319 ifp->if_oerrors++; 5320 } 5321 5322 /* 5323 * Interrupt handler. 5324 */ 5325 /****************************************************************************/ 5326 /* Main interrupt entry point. Verifies that the controller generated the */ 5327 /* interrupt and then calls a separate routine for handle the various */ 5328 /* interrupt causes (PHY, TX, RX). */ 5329 /* */ 5330 /* Returns: */ 5331 /* 0 for success, positive value for failure. */ 5332 /****************************************************************************/ 5333 int 5334 bnx_intr(void *xsc) 5335 { 5336 struct bnx_softc *sc = xsc; 5337 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5338 uint32_t status_attn_bits; 5339 uint16_t status_idx; 5340 const struct status_block *sblk; 5341 int rv = 0; 5342 5343 if (!device_is_active(sc->bnx_dev) || 5344 (ifp->if_flags & IFF_RUNNING) == 0) 5345 return 0; 5346 5347 DBRUNIF(1, sc->interrupts_generated++); 5348 5349 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5350 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5351 5352 sblk = sc->status_block; 5353 /* 5354 * If the hardware status block index 5355 * matches the last value read by the 5356 * driver and we haven't asserted our 5357 * interrupt then there's nothing to do. 5358 */ 5359 status_idx = sblk->status_idx; 5360 if ((status_idx != sc->last_status_idx) || 5361 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5362 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5363 rv = 1; 5364 5365 /* Ack the interrupt */ 5366 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5367 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5368 5369 status_attn_bits = sblk->status_attn_bits; 5370 5371 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5372 aprint_debug("Simulating unexpected status attention bit set."); 5373 status_attn_bits = status_attn_bits | 5374 STATUS_ATTN_BITS_PARITY_ERROR); 5375 5376 /* Was it a link change interrupt? */ 5377 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5378 (sblk->status_attn_bits_ack & 5379 STATUS_ATTN_BITS_LINK_STATE)) 5380 bnx_phy_intr(sc); 5381 5382 /* If any other attention is asserted then the chip is toast. */ 5383 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5384 (sblk->status_attn_bits_ack & 5385 ~STATUS_ATTN_BITS_LINK_STATE))) { 5386 DBRUN(1, sc->unexpected_attentions++); 5387 5388 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5389 sblk->status_attn_bits); 5390 5391 DBRUN(BNX_FATAL, 5392 if (bnx_debug_unexpected_attention == 0) 5393 bnx_breakpoint(sc)); 5394 5395 bnx_init(ifp); 5396 goto out; 5397 } 5398 5399 /* Check for any completed RX frames. */ 5400 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5401 bnx_rx_intr(sc); 5402 5403 /* Check for any completed TX frames. */ 5404 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5405 bnx_tx_intr(sc); 5406 5407 /* 5408 * Save the status block index value for use during the 5409 * next interrupt. 5410 */ 5411 sc->last_status_idx = status_idx; 5412 5413 /* Start moving packets again */ 5414 if (ifp->if_flags & IFF_RUNNING) 5415 if_schedule_deferred_start(ifp); 5416 } 5417 5418 out: 5419 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5420 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5421 5422 return rv; 5423 } 5424 5425 /****************************************************************************/ 5426 /* Programs the various packet receive modes (broadcast and multicast). */ 5427 /* */ 5428 /* Returns: */ 5429 /* Nothing. */ 5430 /****************************************************************************/ 5431 void 5432 bnx_iff(struct bnx_softc *sc) 5433 { 5434 struct ethercom *ec = &sc->bnx_ec; 5435 struct ifnet *ifp = &ec->ec_if; 5436 struct ether_multi *enm; 5437 struct ether_multistep step; 5438 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5439 uint32_t rx_mode, sort_mode; 5440 int h, i; 5441 5442 /* Initialize receive mode default settings. */ 5443 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5444 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5445 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5446 ifp->if_flags &= ~IFF_ALLMULTI; 5447 5448 /* 5449 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5450 * be enbled. 5451 */ 5452 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5453 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5454 5455 /* 5456 * Check for promiscuous, all multicast, or selected 5457 * multicast address filtering. 5458 */ 5459 if (ifp->if_flags & IFF_PROMISC) { 5460 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5461 5462 ifp->if_flags |= IFF_ALLMULTI; 5463 /* Enable promiscuous mode. */ 5464 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5465 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5466 } else if (ifp->if_flags & IFF_ALLMULTI) { 5467 allmulti: 5468 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5469 5470 ifp->if_flags |= IFF_ALLMULTI; 5471 /* Enable all multicast addresses. */ 5472 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5473 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5474 0xffffffff); 5475 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5476 } else { 5477 /* Accept one or more multicast(s). */ 5478 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5479 5480 ETHER_FIRST_MULTI(step, ec, enm); 5481 while (enm != NULL) { 5482 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5483 ETHER_ADDR_LEN)) { 5484 goto allmulti; 5485 } 5486 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5487 0xFF; 5488 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5489 ETHER_NEXT_MULTI(step, enm); 5490 } 5491 5492 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5493 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5494 hashes[i]); 5495 5496 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5497 } 5498 5499 /* Only make changes if the recive mode has actually changed. */ 5500 if (rx_mode != sc->rx_mode) { 5501 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5502 rx_mode); 5503 5504 sc->rx_mode = rx_mode; 5505 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5506 } 5507 5508 /* Disable and clear the exisitng sort before enabling a new sort. */ 5509 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5510 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5511 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5512 } 5513 5514 /****************************************************************************/ 5515 /* Called periodically to updates statistics from the controllers */ 5516 /* statistics block. */ 5517 /* */ 5518 /* Returns: */ 5519 /* Nothing. */ 5520 /****************************************************************************/ 5521 void 5522 bnx_stats_update(struct bnx_softc *sc) 5523 { 5524 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5525 struct statistics_block *stats; 5526 5527 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5528 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5529 BUS_DMASYNC_POSTREAD); 5530 5531 stats = (struct statistics_block *)sc->stats_block; 5532 5533 /* 5534 * Update the interface statistics from the 5535 * hardware statistics. 5536 */ 5537 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5538 5539 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5540 (u_long)stats->stat_EtherStatsOverrsizePkts + 5541 (u_long)stats->stat_IfInMBUFDiscards + 5542 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5543 (u_long)stats->stat_Dot3StatsFCSErrors; 5544 5545 ifp->if_oerrors = (u_long) 5546 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5547 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5548 (u_long)stats->stat_Dot3StatsLateCollisions; 5549 5550 /* 5551 * Certain controllers don't report 5552 * carrier sense errors correctly. 5553 * See errata E11_5708CA0_1165. 5554 */ 5555 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5556 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5557 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5558 5559 /* 5560 * Update the sysctl statistics from the 5561 * hardware statistics. 5562 */ 5563 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5564 (uint64_t) stats->stat_IfHCInOctets_lo; 5565 5566 sc->stat_IfHCInBadOctets = 5567 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5568 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5569 5570 sc->stat_IfHCOutOctets = 5571 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5572 (uint64_t) stats->stat_IfHCOutOctets_lo; 5573 5574 sc->stat_IfHCOutBadOctets = 5575 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5576 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5577 5578 sc->stat_IfHCInUcastPkts = 5579 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5580 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5581 5582 sc->stat_IfHCInMulticastPkts = 5583 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5584 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5585 5586 sc->stat_IfHCInBroadcastPkts = 5587 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5588 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5589 5590 sc->stat_IfHCOutUcastPkts = 5591 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5592 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5593 5594 sc->stat_IfHCOutMulticastPkts = 5595 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5596 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5597 5598 sc->stat_IfHCOutBroadcastPkts = 5599 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5600 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5601 5602 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5603 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5604 5605 sc->stat_Dot3StatsCarrierSenseErrors = 5606 stats->stat_Dot3StatsCarrierSenseErrors; 5607 5608 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5609 5610 sc->stat_Dot3StatsAlignmentErrors = 5611 stats->stat_Dot3StatsAlignmentErrors; 5612 5613 sc->stat_Dot3StatsSingleCollisionFrames = 5614 stats->stat_Dot3StatsSingleCollisionFrames; 5615 5616 sc->stat_Dot3StatsMultipleCollisionFrames = 5617 stats->stat_Dot3StatsMultipleCollisionFrames; 5618 5619 sc->stat_Dot3StatsDeferredTransmissions = 5620 stats->stat_Dot3StatsDeferredTransmissions; 5621 5622 sc->stat_Dot3StatsExcessiveCollisions = 5623 stats->stat_Dot3StatsExcessiveCollisions; 5624 5625 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5626 5627 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5628 5629 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5630 5631 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5632 5633 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5634 5635 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5636 5637 sc->stat_EtherStatsPktsRx64Octets = 5638 stats->stat_EtherStatsPktsRx64Octets; 5639 5640 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5641 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5642 5643 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5644 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5645 5646 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5647 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5648 5649 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5650 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5651 5652 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5653 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5654 5655 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5656 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5657 5658 sc->stat_EtherStatsPktsTx64Octets = 5659 stats->stat_EtherStatsPktsTx64Octets; 5660 5661 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5662 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5663 5664 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5665 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5666 5667 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5668 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5669 5670 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5671 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5672 5673 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5674 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5675 5676 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5677 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5678 5679 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5680 5681 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5682 5683 sc->stat_OutXonSent = stats->stat_OutXonSent; 5684 5685 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5686 5687 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5688 5689 sc->stat_MacControlFramesReceived = 5690 stats->stat_MacControlFramesReceived; 5691 5692 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5693 5694 sc->stat_IfInFramesL2FilterDiscards = 5695 stats->stat_IfInFramesL2FilterDiscards; 5696 5697 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5698 5699 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5700 5701 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5702 5703 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5704 5705 sc->stat_CatchupInRuleCheckerDiscards = 5706 stats->stat_CatchupInRuleCheckerDiscards; 5707 5708 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5709 5710 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5711 5712 sc->stat_CatchupInRuleCheckerP4Hit = 5713 stats->stat_CatchupInRuleCheckerP4Hit; 5714 5715 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5716 } 5717 5718 void 5719 bnx_tick(void *xsc) 5720 { 5721 struct bnx_softc *sc = xsc; 5722 struct mii_data *mii; 5723 uint32_t msg; 5724 uint16_t prod, chain_prod; 5725 uint32_t prod_bseq; 5726 int s = splnet(); 5727 5728 /* Tell the firmware that the driver is still running. */ 5729 #ifdef BNX_DEBUG 5730 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5731 #else 5732 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5733 #endif 5734 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5735 5736 /* Update the statistics from the hardware statistics block. */ 5737 bnx_stats_update(sc); 5738 5739 mii = &sc->bnx_mii; 5740 mii_tick(mii); 5741 5742 /* try to get more RX buffers, just in case */ 5743 prod = sc->rx_prod; 5744 prod_bseq = sc->rx_prod_bseq; 5745 chain_prod = RX_CHAIN_IDX(prod); 5746 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5747 sc->rx_prod = prod; 5748 sc->rx_prod_bseq = prod_bseq; 5749 5750 /* Schedule the next tick. */ 5751 if (!sc->bnx_detaching) 5752 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5753 5754 splx(s); 5755 return; 5756 } 5757 5758 /****************************************************************************/ 5759 /* BNX Debug Routines */ 5760 /****************************************************************************/ 5761 #ifdef BNX_DEBUG 5762 5763 /****************************************************************************/ 5764 /* Prints out information about an mbuf. */ 5765 /* */ 5766 /* Returns: */ 5767 /* Nothing. */ 5768 /****************************************************************************/ 5769 void 5770 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5771 { 5772 struct mbuf *mp = m; 5773 5774 if (m == NULL) { 5775 /* Index out of range. */ 5776 aprint_error("mbuf ptr is null!\n"); 5777 return; 5778 } 5779 5780 while (mp) { 5781 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5782 mp, mp->m_len); 5783 5784 if (mp->m_flags & M_EXT) 5785 aprint_debug("M_EXT "); 5786 if (mp->m_flags & M_PKTHDR) 5787 aprint_debug("M_PKTHDR "); 5788 aprint_debug("\n"); 5789 5790 if (mp->m_flags & M_EXT) 5791 aprint_debug("- m_ext: vaddr = %p, " 5792 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5793 5794 mp = mp->m_next; 5795 } 5796 } 5797 5798 /****************************************************************************/ 5799 /* Prints out the mbufs in the TX mbuf chain. */ 5800 /* */ 5801 /* Returns: */ 5802 /* Nothing. */ 5803 /****************************************************************************/ 5804 void 5805 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5806 { 5807 #if 0 5808 struct mbuf *m; 5809 int i; 5810 5811 aprint_debug_dev(sc->bnx_dev, 5812 "----------------------------" 5813 " tx mbuf data " 5814 "----------------------------\n"); 5815 5816 for (i = 0; i < count; i++) { 5817 m = sc->tx_mbuf_ptr[chain_prod]; 5818 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5819 bnx_dump_mbuf(sc, m); 5820 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5821 } 5822 5823 aprint_debug_dev(sc->bnx_dev, 5824 "--------------------------------------------" 5825 "----------------------------\n"); 5826 #endif 5827 } 5828 5829 /* 5830 * This routine prints the RX mbuf chain. 5831 */ 5832 void 5833 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5834 { 5835 struct mbuf *m; 5836 int i; 5837 5838 aprint_debug_dev(sc->bnx_dev, 5839 "----------------------------" 5840 " rx mbuf data " 5841 "----------------------------\n"); 5842 5843 for (i = 0; i < count; i++) { 5844 m = sc->rx_mbuf_ptr[chain_prod]; 5845 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5846 bnx_dump_mbuf(sc, m); 5847 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5848 } 5849 5850 5851 aprint_debug_dev(sc->bnx_dev, 5852 "--------------------------------------------" 5853 "----------------------------\n"); 5854 } 5855 5856 void 5857 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5858 { 5859 if (idx > MAX_TX_BD) 5860 /* Index out of range. */ 5861 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5862 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5863 /* TX Chain page pointer. */ 5864 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5865 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5866 txbd->tx_bd_haddr_lo); 5867 else 5868 /* Normal tx_bd entry. */ 5869 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5870 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5871 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5872 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5873 txbd->tx_bd_flags); 5874 } 5875 5876 void 5877 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5878 { 5879 if (idx > MAX_RX_BD) 5880 /* Index out of range. */ 5881 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5882 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5883 /* TX Chain page pointer. */ 5884 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5885 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5886 rxbd->rx_bd_haddr_lo); 5887 else 5888 /* Normal tx_bd entry. */ 5889 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5890 "0x%08X, flags = 0x%08X\n", idx, 5891 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5892 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5893 } 5894 5895 void 5896 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5897 { 5898 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5899 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5900 "tcp_udp_xsum = 0x%04X\n", idx, 5901 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5902 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5903 l2fhdr->l2_fhdr_tcp_udp_xsum); 5904 } 5905 5906 /* 5907 * This routine prints the TX chain. 5908 */ 5909 void 5910 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5911 { 5912 struct tx_bd *txbd; 5913 int i; 5914 5915 /* First some info about the tx_bd chain structure. */ 5916 aprint_debug_dev(sc->bnx_dev, 5917 "----------------------------" 5918 " tx_bd chain " 5919 "----------------------------\n"); 5920 5921 BNX_PRINTF(sc, 5922 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5923 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 5924 5925 BNX_PRINTF(sc, 5926 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 5927 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 5928 5929 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", TOTAL_TX_BD); 5930 5931 aprint_error_dev(sc->bnx_dev, "" 5932 "-----------------------------" 5933 " tx_bd data " 5934 "-----------------------------\n"); 5935 5936 /* Now print out the tx_bd's themselves. */ 5937 for (i = 0; i < count; i++) { 5938 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 5939 bnx_dump_txbd(sc, tx_prod, txbd); 5940 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 5941 } 5942 5943 aprint_debug_dev(sc->bnx_dev, 5944 "-----------------------------" 5945 "--------------" 5946 "-----------------------------\n"); 5947 } 5948 5949 /* 5950 * This routine prints the RX chain. 5951 */ 5952 void 5953 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 5954 { 5955 struct rx_bd *rxbd; 5956 int i; 5957 5958 /* First some info about the tx_bd chain structure. */ 5959 aprint_debug_dev(sc->bnx_dev, 5960 "----------------------------" 5961 " rx_bd chain " 5962 "----------------------------\n"); 5963 5964 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 5965 5966 BNX_PRINTF(sc, 5967 "page size = 0x%08X, rx chain pages = 0x%08X\n", 5968 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 5969 5970 BNX_PRINTF(sc, 5971 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 5972 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 5973 5974 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", TOTAL_RX_BD); 5975 5976 aprint_error_dev(sc->bnx_dev, 5977 "----------------------------" 5978 " rx_bd data " 5979 "----------------------------\n"); 5980 5981 /* Now print out the rx_bd's themselves. */ 5982 for (i = 0; i < count; i++) { 5983 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 5984 bnx_dump_rxbd(sc, rx_prod, rxbd); 5985 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 5986 } 5987 5988 aprint_debug_dev(sc->bnx_dev, 5989 "----------------------------" 5990 "--------------" 5991 "----------------------------\n"); 5992 } 5993 5994 /* 5995 * This routine prints the status block. 5996 */ 5997 void 5998 bnx_dump_status_block(struct bnx_softc *sc) 5999 { 6000 struct status_block *sblk; 6001 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6002 BUS_DMASYNC_POSTREAD); 6003 6004 sblk = sc->status_block; 6005 6006 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6007 "Status Block -----------------------------\n"); 6008 6009 BNX_PRINTF(sc, 6010 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6011 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6012 sblk->status_idx); 6013 6014 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6015 sblk->status_rx_quick_consumer_index0, 6016 sblk->status_tx_quick_consumer_index0); 6017 6018 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6019 6020 /* Theses indices are not used for normal L2 drivers. */ 6021 if (sblk->status_rx_quick_consumer_index1 || 6022 sblk->status_tx_quick_consumer_index1) 6023 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6024 sblk->status_rx_quick_consumer_index1, 6025 sblk->status_tx_quick_consumer_index1); 6026 6027 if (sblk->status_rx_quick_consumer_index2 || 6028 sblk->status_tx_quick_consumer_index2) 6029 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6030 sblk->status_rx_quick_consumer_index2, 6031 sblk->status_tx_quick_consumer_index2); 6032 6033 if (sblk->status_rx_quick_consumer_index3 || 6034 sblk->status_tx_quick_consumer_index3) 6035 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6036 sblk->status_rx_quick_consumer_index3, 6037 sblk->status_tx_quick_consumer_index3); 6038 6039 if (sblk->status_rx_quick_consumer_index4 || 6040 sblk->status_rx_quick_consumer_index5) 6041 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6042 sblk->status_rx_quick_consumer_index4, 6043 sblk->status_rx_quick_consumer_index5); 6044 6045 if (sblk->status_rx_quick_consumer_index6 || 6046 sblk->status_rx_quick_consumer_index7) 6047 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6048 sblk->status_rx_quick_consumer_index6, 6049 sblk->status_rx_quick_consumer_index7); 6050 6051 if (sblk->status_rx_quick_consumer_index8 || 6052 sblk->status_rx_quick_consumer_index9) 6053 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6054 sblk->status_rx_quick_consumer_index8, 6055 sblk->status_rx_quick_consumer_index9); 6056 6057 if (sblk->status_rx_quick_consumer_index10 || 6058 sblk->status_rx_quick_consumer_index11) 6059 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6060 sblk->status_rx_quick_consumer_index10, 6061 sblk->status_rx_quick_consumer_index11); 6062 6063 if (sblk->status_rx_quick_consumer_index12 || 6064 sblk->status_rx_quick_consumer_index13) 6065 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6066 sblk->status_rx_quick_consumer_index12, 6067 sblk->status_rx_quick_consumer_index13); 6068 6069 if (sblk->status_rx_quick_consumer_index14 || 6070 sblk->status_rx_quick_consumer_index15) 6071 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6072 sblk->status_rx_quick_consumer_index14, 6073 sblk->status_rx_quick_consumer_index15); 6074 6075 if (sblk->status_completion_producer_index || 6076 sblk->status_cmd_consumer_index) 6077 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6078 sblk->status_completion_producer_index, 6079 sblk->status_cmd_consumer_index); 6080 6081 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6082 "-----------------------------\n"); 6083 } 6084 6085 /* 6086 * This routine prints the statistics block. 6087 */ 6088 void 6089 bnx_dump_stats_block(struct bnx_softc *sc) 6090 { 6091 struct statistics_block *sblk; 6092 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6093 BUS_DMASYNC_POSTREAD); 6094 6095 sblk = sc->stats_block; 6096 6097 aprint_debug_dev(sc->bnx_dev, "" 6098 "-----------------------------" 6099 " Stats Block " 6100 "-----------------------------\n"); 6101 6102 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6103 "IfHcInBadOctets = 0x%08X:%08X\n", 6104 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6105 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6106 6107 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6108 "IfHcOutBadOctets = 0x%08X:%08X\n", 6109 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6110 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6111 6112 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6113 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6114 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6115 sblk->stat_IfHCInMulticastPkts_hi, 6116 sblk->stat_IfHCInMulticastPkts_lo); 6117 6118 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6119 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6120 sblk->stat_IfHCInBroadcastPkts_hi, 6121 sblk->stat_IfHCInBroadcastPkts_lo, 6122 sblk->stat_IfHCOutUcastPkts_hi, 6123 sblk->stat_IfHCOutUcastPkts_lo); 6124 6125 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6126 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6127 sblk->stat_IfHCOutMulticastPkts_hi, 6128 sblk->stat_IfHCOutMulticastPkts_lo, 6129 sblk->stat_IfHCOutBroadcastPkts_hi, 6130 sblk->stat_IfHCOutBroadcastPkts_lo); 6131 6132 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6133 BNX_PRINTF(sc, "0x%08X : " 6134 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6135 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6136 6137 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6138 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6139 sblk->stat_Dot3StatsCarrierSenseErrors); 6140 6141 if (sblk->stat_Dot3StatsFCSErrors) 6142 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6143 sblk->stat_Dot3StatsFCSErrors); 6144 6145 if (sblk->stat_Dot3StatsAlignmentErrors) 6146 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6147 sblk->stat_Dot3StatsAlignmentErrors); 6148 6149 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6150 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6151 sblk->stat_Dot3StatsSingleCollisionFrames); 6152 6153 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6154 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6155 sblk->stat_Dot3StatsMultipleCollisionFrames); 6156 6157 if (sblk->stat_Dot3StatsDeferredTransmissions) 6158 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6159 sblk->stat_Dot3StatsDeferredTransmissions); 6160 6161 if (sblk->stat_Dot3StatsExcessiveCollisions) 6162 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6163 sblk->stat_Dot3StatsExcessiveCollisions); 6164 6165 if (sblk->stat_Dot3StatsLateCollisions) 6166 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6167 sblk->stat_Dot3StatsLateCollisions); 6168 6169 if (sblk->stat_EtherStatsCollisions) 6170 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6171 sblk->stat_EtherStatsCollisions); 6172 6173 if (sblk->stat_EtherStatsFragments) 6174 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6175 sblk->stat_EtherStatsFragments); 6176 6177 if (sblk->stat_EtherStatsJabbers) 6178 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6179 sblk->stat_EtherStatsJabbers); 6180 6181 if (sblk->stat_EtherStatsUndersizePkts) 6182 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6183 sblk->stat_EtherStatsUndersizePkts); 6184 6185 if (sblk->stat_EtherStatsOverrsizePkts) 6186 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6187 sblk->stat_EtherStatsOverrsizePkts); 6188 6189 if (sblk->stat_EtherStatsPktsRx64Octets) 6190 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6191 sblk->stat_EtherStatsPktsRx64Octets); 6192 6193 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6194 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6195 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6196 6197 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6198 BNX_PRINTF(sc, "0x%08X : " 6199 "EtherStatsPktsRx128Octetsto255Octets\n", 6200 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6201 6202 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6203 BNX_PRINTF(sc, "0x%08X : " 6204 "EtherStatsPktsRx256Octetsto511Octets\n", 6205 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6206 6207 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6208 BNX_PRINTF(sc, "0x%08X : " 6209 "EtherStatsPktsRx512Octetsto1023Octets\n", 6210 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6211 6212 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6213 BNX_PRINTF(sc, "0x%08X : " 6214 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6215 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6216 6217 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6218 BNX_PRINTF(sc, "0x%08X : " 6219 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6220 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6221 6222 if (sblk->stat_EtherStatsPktsTx64Octets) 6223 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6224 sblk->stat_EtherStatsPktsTx64Octets); 6225 6226 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6227 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6228 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6229 6230 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6231 BNX_PRINTF(sc, "0x%08X : " 6232 "EtherStatsPktsTx128Octetsto255Octets\n", 6233 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6234 6235 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6236 BNX_PRINTF(sc, "0x%08X : " 6237 "EtherStatsPktsTx256Octetsto511Octets\n", 6238 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6239 6240 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6241 BNX_PRINTF(sc, "0x%08X : " 6242 "EtherStatsPktsTx512Octetsto1023Octets\n", 6243 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6244 6245 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6246 BNX_PRINTF(sc, "0x%08X : " 6247 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6248 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6249 6250 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6251 BNX_PRINTF(sc, "0x%08X : " 6252 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6253 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6254 6255 if (sblk->stat_XonPauseFramesReceived) 6256 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6257 sblk->stat_XonPauseFramesReceived); 6258 6259 if (sblk->stat_XoffPauseFramesReceived) 6260 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6261 sblk->stat_XoffPauseFramesReceived); 6262 6263 if (sblk->stat_OutXonSent) 6264 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6265 sblk->stat_OutXonSent); 6266 6267 if (sblk->stat_OutXoffSent) 6268 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6269 sblk->stat_OutXoffSent); 6270 6271 if (sblk->stat_FlowControlDone) 6272 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6273 sblk->stat_FlowControlDone); 6274 6275 if (sblk->stat_MacControlFramesReceived) 6276 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6277 sblk->stat_MacControlFramesReceived); 6278 6279 if (sblk->stat_XoffStateEntered) 6280 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6281 sblk->stat_XoffStateEntered); 6282 6283 if (sblk->stat_IfInFramesL2FilterDiscards) 6284 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6285 sblk->stat_IfInFramesL2FilterDiscards); 6286 6287 if (sblk->stat_IfInRuleCheckerDiscards) 6288 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6289 sblk->stat_IfInRuleCheckerDiscards); 6290 6291 if (sblk->stat_IfInFTQDiscards) 6292 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6293 sblk->stat_IfInFTQDiscards); 6294 6295 if (sblk->stat_IfInMBUFDiscards) 6296 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6297 sblk->stat_IfInMBUFDiscards); 6298 6299 if (sblk->stat_IfInRuleCheckerP4Hit) 6300 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6301 sblk->stat_IfInRuleCheckerP4Hit); 6302 6303 if (sblk->stat_CatchupInRuleCheckerDiscards) 6304 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6305 sblk->stat_CatchupInRuleCheckerDiscards); 6306 6307 if (sblk->stat_CatchupInFTQDiscards) 6308 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6309 sblk->stat_CatchupInFTQDiscards); 6310 6311 if (sblk->stat_CatchupInMBUFDiscards) 6312 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6313 sblk->stat_CatchupInMBUFDiscards); 6314 6315 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6316 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6317 sblk->stat_CatchupInRuleCheckerP4Hit); 6318 6319 aprint_debug_dev(sc->bnx_dev, 6320 "-----------------------------" 6321 "--------------" 6322 "-----------------------------\n"); 6323 } 6324 6325 void 6326 bnx_dump_driver_state(struct bnx_softc *sc) 6327 { 6328 aprint_debug_dev(sc->bnx_dev, 6329 "-----------------------------" 6330 " Driver State " 6331 "-----------------------------\n"); 6332 6333 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6334 "address\n", sc); 6335 6336 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6337 sc->status_block); 6338 6339 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6340 "address\n", sc->stats_block); 6341 6342 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6343 "adddress\n", sc->tx_bd_chain); 6344 6345 #if 0 6346 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6347 sc->rx_bd_chain); 6348 6349 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6350 sc->tx_mbuf_ptr); 6351 #endif 6352 6353 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6354 sc->rx_mbuf_ptr); 6355 6356 BNX_PRINTF(sc, 6357 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6358 sc->interrupts_generated); 6359 6360 BNX_PRINTF(sc, 6361 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6362 sc->rx_interrupts); 6363 6364 BNX_PRINTF(sc, 6365 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6366 sc->tx_interrupts); 6367 6368 BNX_PRINTF(sc, 6369 " 0x%08X - (sc->last_status_idx) status block index\n", 6370 sc->last_status_idx); 6371 6372 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6373 sc->tx_prod); 6374 6375 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6376 sc->tx_cons); 6377 6378 BNX_PRINTF(sc, 6379 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6380 sc->tx_prod_bseq); 6381 BNX_PRINTF(sc, 6382 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6383 sc->tx_mbuf_alloc); 6384 6385 BNX_PRINTF(sc, 6386 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6387 sc->used_tx_bd); 6388 6389 BNX_PRINTF(sc, 6390 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6391 sc->tx_hi_watermark, sc->max_tx_bd); 6392 6393 6394 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6395 sc->rx_prod); 6396 6397 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6398 sc->rx_cons); 6399 6400 BNX_PRINTF(sc, 6401 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6402 sc->rx_prod_bseq); 6403 6404 BNX_PRINTF(sc, 6405 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6406 sc->rx_mbuf_alloc); 6407 6408 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6409 sc->free_rx_bd); 6410 6411 BNX_PRINTF(sc, 6412 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6413 sc->rx_low_watermark, sc->max_rx_bd); 6414 6415 BNX_PRINTF(sc, 6416 " 0x%08X - (sc->mbuf_alloc_failed) " 6417 "mbuf alloc failures\n", 6418 sc->mbuf_alloc_failed); 6419 6420 BNX_PRINTF(sc, 6421 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6422 "simulated mbuf alloc failures\n", 6423 sc->mbuf_sim_alloc_failed); 6424 6425 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6426 "-----------------------------\n"); 6427 } 6428 6429 void 6430 bnx_dump_hw_state(struct bnx_softc *sc) 6431 { 6432 uint32_t val1; 6433 int i; 6434 6435 aprint_debug_dev(sc->bnx_dev, 6436 "----------------------------" 6437 " Hardware State " 6438 "----------------------------\n"); 6439 6440 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6441 6442 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6443 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6444 val1, BNX_MISC_ENABLE_STATUS_BITS); 6445 6446 val1 = REG_RD(sc, BNX_DMA_STATUS); 6447 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6448 6449 val1 = REG_RD(sc, BNX_CTX_STATUS); 6450 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6451 6452 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6453 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6454 BNX_EMAC_STATUS); 6455 6456 val1 = REG_RD(sc, BNX_RPM_STATUS); 6457 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6458 6459 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6460 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6461 BNX_TBDR_STATUS); 6462 6463 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6464 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6465 BNX_TDMA_STATUS); 6466 6467 val1 = REG_RD(sc, BNX_HC_STATUS); 6468 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6469 6470 aprint_debug_dev(sc->bnx_dev, 6471 "----------------------------" 6472 "----------------" 6473 "----------------------------\n"); 6474 6475 aprint_debug_dev(sc->bnx_dev, 6476 "----------------------------" 6477 " Register Dump " 6478 "----------------------------\n"); 6479 6480 for (i = 0x400; i < 0x8000; i += 0x10) 6481 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6482 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6483 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6484 6485 aprint_debug_dev(sc->bnx_dev, 6486 "----------------------------" 6487 "----------------" 6488 "----------------------------\n"); 6489 } 6490 6491 void 6492 bnx_breakpoint(struct bnx_softc *sc) 6493 { 6494 /* Unreachable code to shut the compiler up about unused functions. */ 6495 if (0) { 6496 bnx_dump_txbd(sc, 0, NULL); 6497 bnx_dump_rxbd(sc, 0, NULL); 6498 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6499 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6500 bnx_dump_l2fhdr(sc, 0, NULL); 6501 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6502 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6503 bnx_dump_status_block(sc); 6504 bnx_dump_stats_block(sc); 6505 bnx_dump_driver_state(sc); 6506 bnx_dump_hw_state(sc); 6507 } 6508 6509 bnx_dump_driver_state(sc); 6510 /* Print the important status block fields. */ 6511 bnx_dump_status_block(sc); 6512 6513 #if 0 6514 /* Call the debugger. */ 6515 breakpoint(); 6516 #endif 6517 6518 return; 6519 } 6520 #endif 6521
Indexes created Thu Sep 25 08:09:54 GMT 2025