if_bnx.c revision 1.76
1 /* $NetBSD: if_bnx.c,v 1.76 2019/04/04 08:16:24 msaitoh Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.76 2019/04/04 08:16:24 msaitoh Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 466 aprint_normal_dev(sc->bnx_dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 467 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 468 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 469 ? "Serdes " : "", sc->bnx_chipid); 470 471 /* Bus info. */ 472 if (sc->bnx_flags & BNX_PCIE_FLAG) { 473 aprint_normal_dev(sc->bnx_dev, "PCIe x%d ", 474 sc->link_width); 475 switch (sc->link_speed) { 476 case 1: aprint_normal("2.5Gbps\n"); break; 477 case 2: aprint_normal("5Gbps\n"); break; 478 default: aprint_normal("Unknown link speed\n"); 479 } 480 } else { 481 aprint_normal_dev(sc->bnx_dev, "PCI%s %dbit %dMHz\n", 482 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 483 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 484 sc->bus_speed_mhz); 485 } 486 487 aprint_normal_dev(sc->bnx_dev, 488 "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 489 sc->bnx_rx_quick_cons_trip_int, 490 sc->bnx_rx_quick_cons_trip, 491 sc->bnx_rx_ticks_int, 492 sc->bnx_rx_ticks, 493 sc->bnx_tx_quick_cons_trip_int, 494 sc->bnx_tx_quick_cons_trip, 495 sc->bnx_tx_ticks_int, 496 sc->bnx_tx_ticks); 497 } 498 499 500 /****************************************************************************/ 501 /* PCI Capabilities Probe Function. */ 502 /* */ 503 /* Walks the PCI capabiites list for the device to find what features are */ 504 /* supported. */ 505 /* */ 506 /* Returns: */ 507 /* None. */ 508 /****************************************************************************/ 509 static void 510 bnx_probe_pci_caps(struct bnx_softc *sc) 511 { 512 struct pci_attach_args *pa = &(sc->bnx_pa); 513 pcireg_t reg; 514 515 /* Check if PCI-X capability is enabled. */ 516 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 517 NULL) != 0) { 518 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 519 } 520 521 /* Check if PCIe capability is enabled. */ 522 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 523 NULL) != 0) { 524 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 525 reg + PCIE_LCSR); 526 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 527 "0x%08X\n", link_status); 528 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 529 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 530 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 531 sc->bnx_flags |= BNX_PCIE_FLAG; 532 } 533 534 /* Check if MSI capability is enabled. */ 535 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 536 NULL) != 0) 537 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 538 539 /* Check if MSI-X capability is enabled. */ 540 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 541 NULL) != 0) 542 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 543 } 544 545 546 /****************************************************************************/ 547 /* Device attach function. */ 548 /* */ 549 /* Allocates device resources, performs secondary chip identification, */ 550 /* resets and initializes the hardware, and initializes driver instance */ 551 /* variables. */ 552 /* */ 553 /* Returns: */ 554 /* 0 on success, positive value on failure. */ 555 /****************************************************************************/ 556 void 557 bnx_attach(device_t parent, device_t self, void *aux) 558 { 559 const struct bnx_product *bp; 560 struct bnx_softc *sc = device_private(self); 561 prop_dictionary_t dict; 562 struct pci_attach_args *pa = aux; 563 pci_chipset_tag_t pc = pa->pa_pc; 564 pci_intr_handle_t ih; 565 const char *intrstr = NULL; 566 uint32_t command; 567 struct ifnet *ifp; 568 uint32_t val; 569 int mii_flags = MIIF_FORCEANEG; 570 pcireg_t memtype; 571 char intrbuf[PCI_INTRSTR_LEN]; 572 573 if (bnx_tx_pool == NULL) { 574 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 575 if (bnx_tx_pool != NULL) { 576 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 577 0, 0, 0, "bnxpkts", NULL, IPL_NET); 578 } else { 579 aprint_error(": can't alloc bnx_tx_pool\n"); 580 return; 581 } 582 } 583 584 bp = bnx_lookup(pa); 585 if (bp == NULL) 586 panic("unknown device"); 587 588 sc->bnx_dev = self; 589 590 aprint_naive("\n"); 591 aprint_normal(": %s\n", bp->bp_name); 592 593 sc->bnx_pa = *pa; 594 595 /* 596 * Map control/status registers. 597 */ 598 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 599 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 600 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 601 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 602 603 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 604 aprint_error_dev(sc->bnx_dev, 605 "failed to enable memory mapping!\n"); 606 return; 607 } 608 609 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 610 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 611 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 612 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 613 return; 614 } 615 616 if (pci_intr_map(pa, &ih)) { 617 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 618 goto bnx_attach_fail; 619 } 620 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 621 622 /* 623 * Configure byte swap and enable indirect register access. 624 * Rely on CPU to do target byte swapping on big endian systems. 625 * Access to registers outside of PCI configurtion space are not 626 * valid until this is done. 627 */ 628 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 629 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 630 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 631 632 /* Save ASIC revsion info. */ 633 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 634 635 /* 636 * Find the base address for shared memory access. 637 * Newer versions of bootcode use a signature and offset 638 * while older versions use a fixed address. 639 */ 640 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 641 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 642 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 643 (sc->bnx_pa.pa_function << 2)); 644 else 645 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 646 647 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 648 649 /* Set initial device and PHY flags */ 650 sc->bnx_flags = 0; 651 sc->bnx_phy_flags = 0; 652 653 bnx_probe_pci_caps(sc); 654 655 /* Get PCI bus information (speed and type). */ 656 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 657 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 658 uint32_t clkreg; 659 660 sc->bnx_flags |= BNX_PCIX_FLAG; 661 662 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 663 664 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 665 switch (clkreg) { 666 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 667 sc->bus_speed_mhz = 133; 668 break; 669 670 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 671 sc->bus_speed_mhz = 100; 672 break; 673 674 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 675 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 676 sc->bus_speed_mhz = 66; 677 break; 678 679 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 680 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 681 sc->bus_speed_mhz = 50; 682 break; 683 684 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 685 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 686 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 687 sc->bus_speed_mhz = 33; 688 break; 689 } 690 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 691 sc->bus_speed_mhz = 66; 692 else 693 sc->bus_speed_mhz = 33; 694 695 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 696 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 697 698 /* Reset the controller. */ 699 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 700 goto bnx_attach_fail; 701 702 /* Initialize the controller. */ 703 if (bnx_chipinit(sc)) { 704 aprint_error_dev(sc->bnx_dev, 705 "Controller initialization failed!\n"); 706 goto bnx_attach_fail; 707 } 708 709 /* Perform NVRAM test. */ 710 if (bnx_nvram_test(sc)) { 711 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 712 goto bnx_attach_fail; 713 } 714 715 /* Fetch the permanent Ethernet MAC address. */ 716 bnx_get_mac_addr(sc); 717 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 718 ether_sprintf(sc->eaddr)); 719 720 /* 721 * Trip points control how many BDs 722 * should be ready before generating an 723 * interrupt while ticks control how long 724 * a BD can sit in the chain before 725 * generating an interrupt. Set the default 726 * values for the RX and TX rings. 727 */ 728 729 #ifdef BNX_DEBUG 730 /* Force more frequent interrupts. */ 731 sc->bnx_tx_quick_cons_trip_int = 1; 732 sc->bnx_tx_quick_cons_trip = 1; 733 sc->bnx_tx_ticks_int = 0; 734 sc->bnx_tx_ticks = 0; 735 736 sc->bnx_rx_quick_cons_trip_int = 1; 737 sc->bnx_rx_quick_cons_trip = 1; 738 sc->bnx_rx_ticks_int = 0; 739 sc->bnx_rx_ticks = 0; 740 #else 741 sc->bnx_tx_quick_cons_trip_int = 20; 742 sc->bnx_tx_quick_cons_trip = 20; 743 sc->bnx_tx_ticks_int = 80; 744 sc->bnx_tx_ticks = 80; 745 746 sc->bnx_rx_quick_cons_trip_int = 6; 747 sc->bnx_rx_quick_cons_trip = 6; 748 sc->bnx_rx_ticks_int = 18; 749 sc->bnx_rx_ticks = 18; 750 #endif 751 752 /* Update statistics once every second. */ 753 sc->bnx_stats_ticks = 1000000 & 0xffff00; 754 755 /* Find the media type for the adapter. */ 756 bnx_get_media(sc); 757 758 /* 759 * Store config data needed by the PHY driver for 760 * backplane applications 761 */ 762 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 763 BNX_SHARED_HW_CFG_CONFIG); 764 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 765 BNX_PORT_HW_CFG_CONFIG); 766 767 /* Allocate DMA memory resources. */ 768 sc->bnx_dmatag = pa->pa_dmat; 769 if (bnx_dma_alloc(sc)) { 770 aprint_error_dev(sc->bnx_dev, 771 "DMA resource allocation failed!\n"); 772 goto bnx_attach_fail; 773 } 774 775 /* Initialize the ifnet interface. */ 776 ifp = &sc->bnx_ec.ec_if; 777 ifp->if_softc = sc; 778 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 779 ifp->if_ioctl = bnx_ioctl; 780 ifp->if_stop = bnx_stop; 781 ifp->if_start = bnx_start; 782 ifp->if_init = bnx_init; 783 ifp->if_watchdog = bnx_watchdog; 784 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 785 IFQ_SET_READY(&ifp->if_snd); 786 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 787 788 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 789 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 790 791 ifp->if_capabilities |= 792 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 793 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 794 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 795 796 /* create workqueue to handle packet allocations */ 797 if (workqueue_create(&sc->bnx_wq, device_xname(self), 798 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 799 aprint_error_dev(self, "failed to create workqueue\n"); 800 goto bnx_attach_fail; 801 } 802 803 sc->bnx_mii.mii_ifp = ifp; 804 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 805 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 806 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 807 808 /* Handle any special PHY initialization for SerDes PHYs. */ 809 bnx_init_media(sc); 810 811 sc->bnx_ec.ec_mii = &sc->bnx_mii; 812 ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, 813 bnx_ifmedia_sts); 814 815 /* set phyflags and chipid before mii_attach() */ 816 dict = device_properties(self); 817 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 818 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 819 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 820 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 821 822 /* Print some useful adapter info */ 823 bnx_print_adapter_info(sc); 824 825 mii_flags |= MIIF_DOPAUSE; 826 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 827 mii_flags |= MIIF_HAVEFIBER; 828 mii_attach(self, &sc->bnx_mii, 0xffffffff, 829 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 830 831 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 832 aprint_error_dev(self, "no PHY found!\n"); 833 ifmedia_add(&sc->bnx_mii.mii_media, 834 IFM_ETHER|IFM_MANUAL, 0, NULL); 835 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_MANUAL); 836 } else 837 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_AUTO); 838 839 /* Attach to the Ethernet interface list. */ 840 if_attach(ifp); 841 if_deferred_start_init(ifp, NULL); 842 ether_ifattach(ifp,sc->eaddr); 843 844 callout_init(&sc->bnx_timeout, 0); 845 846 /* Hookup IRQ last. */ 847 sc->bnx_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bnx_intr, 848 sc, device_xname(self)); 849 if (sc->bnx_intrhand == NULL) { 850 aprint_error_dev(self, "couldn't establish interrupt"); 851 if (intrstr != NULL) 852 aprint_error(" at %s", intrstr); 853 aprint_error("\n"); 854 goto bnx_attach_fail; 855 } 856 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 857 858 if (pmf_device_register(self, NULL, NULL)) 859 pmf_class_network_register(self, ifp); 860 else 861 aprint_error_dev(self, "couldn't establish power handler\n"); 862 863 /* Print some important debugging info. */ 864 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 865 866 /* Get the firmware running so ASF still works. */ 867 bnx_mgmt_init(sc); 868 869 goto bnx_attach_exit; 870 871 bnx_attach_fail: 872 bnx_release_resources(sc); 873 874 bnx_attach_exit: 875 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 876 } 877 878 /****************************************************************************/ 879 /* Device detach function. */ 880 /* */ 881 /* Stops the controller, resets the controller, and releases resources. */ 882 /* */ 883 /* Returns: */ 884 /* 0 on success, positive value on failure. */ 885 /****************************************************************************/ 886 int 887 bnx_detach(device_t dev, int flags) 888 { 889 int s; 890 struct bnx_softc *sc; 891 struct ifnet *ifp; 892 893 sc = device_private(dev); 894 ifp = &sc->bnx_ec.ec_if; 895 896 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 897 898 /* Stop and reset the controller. */ 899 s = splnet(); 900 bnx_stop(ifp, 1); 901 splx(s); 902 903 pmf_device_deregister(dev); 904 callout_destroy(&sc->bnx_timeout); 905 ether_ifdetach(ifp); 906 workqueue_destroy(sc->bnx_wq); 907 908 /* Delete all remaining media. */ 909 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 910 911 if_detach(ifp); 912 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 913 914 /* Release all remaining resources. */ 915 bnx_release_resources(sc); 916 917 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 918 919 return 0; 920 } 921 922 /****************************************************************************/ 923 /* Indirect register read. */ 924 /* */ 925 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 926 /* configuration space. Using this mechanism avoids issues with posted */ 927 /* reads but is much slower than memory-mapped I/O. */ 928 /* */ 929 /* Returns: */ 930 /* The value of the register. */ 931 /****************************************************************************/ 932 uint32_t 933 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 934 { 935 struct pci_attach_args *pa = &(sc->bnx_pa); 936 937 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 938 offset); 939 #ifdef BNX_DEBUG 940 { 941 uint32_t val; 942 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 943 BNX_PCICFG_REG_WINDOW); 944 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 945 "val = 0x%08X\n", __func__, offset, val); 946 return val; 947 } 948 #else 949 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 950 #endif 951 } 952 953 /****************************************************************************/ 954 /* Indirect register write. */ 955 /* */ 956 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 957 /* configuration space. Using this mechanism avoids issues with posted */ 958 /* writes but is muchh slower than memory-mapped I/O. */ 959 /* */ 960 /* Returns: */ 961 /* Nothing. */ 962 /****************************************************************************/ 963 void 964 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 965 { 966 struct pci_attach_args *pa = &(sc->bnx_pa); 967 968 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 969 __func__, offset, val); 970 971 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 972 offset); 973 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 974 } 975 976 /****************************************************************************/ 977 /* Context memory write. */ 978 /* */ 979 /* The NetXtreme II controller uses context memory to track connection */ 980 /* information for L2 and higher network protocols. */ 981 /* */ 982 /* Returns: */ 983 /* Nothing. */ 984 /****************************************************************************/ 985 void 986 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 987 uint32_t ctx_val) 988 { 989 uint32_t idx, offset = ctx_offset + cid_addr; 990 uint32_t val, retry_cnt = 5; 991 992 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 993 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 994 REG_WR(sc, BNX_CTX_CTX_CTRL, 995 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 996 997 for (idx = 0; idx < retry_cnt; idx++) { 998 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 999 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1000 break; 1001 DELAY(5); 1002 } 1003 1004 #if 0 1005 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1006 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1007 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1008 __FILE__, __LINE__, cid_addr, ctx_offset); 1009 #endif 1010 1011 } else { 1012 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1013 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1014 } 1015 } 1016 1017 /****************************************************************************/ 1018 /* PHY register read. */ 1019 /* */ 1020 /* Implements register reads on the MII bus. */ 1021 /* */ 1022 /* Returns: */ 1023 /* The value of the register. */ 1024 /****************************************************************************/ 1025 int 1026 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1027 { 1028 struct bnx_softc *sc = device_private(dev); 1029 uint32_t data; 1030 int i, rv = 0; 1031 1032 /* 1033 * The BCM5709S PHY is an IEEE Clause 45 PHY 1034 * with special mappings to work with IEEE 1035 * Clause 22 register accesses. 1036 */ 1037 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1038 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1039 reg += 0x10; 1040 } 1041 1042 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1043 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1044 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1045 1046 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1047 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1048 1049 DELAY(40); 1050 } 1051 1052 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1053 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1054 BNX_EMAC_MDIO_COMM_START_BUSY; 1055 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1056 1057 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1058 DELAY(10); 1059 1060 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1061 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1062 DELAY(5); 1063 1064 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1065 data &= BNX_EMAC_MDIO_COMM_DATA; 1066 1067 break; 1068 } 1069 } 1070 1071 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1072 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1073 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1074 rv = ETIMEDOUT; 1075 } else { 1076 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1077 *val = data & 0xffff; 1078 1079 DBPRINT(sc, BNX_EXCESSIVE, 1080 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1081 phy, (uint16_t) reg & 0xffff, *val); 1082 } 1083 1084 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1085 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1086 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1087 1088 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1089 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1090 1091 DELAY(40); 1092 } 1093 1094 return rv; 1095 } 1096 1097 /****************************************************************************/ 1098 /* PHY register write. */ 1099 /* */ 1100 /* Implements register writes on the MII bus. */ 1101 /* */ 1102 /* Returns: */ 1103 /* The value of the register. */ 1104 /****************************************************************************/ 1105 int 1106 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1107 { 1108 struct bnx_softc *sc = device_private(dev); 1109 uint32_t val1; 1110 int i, rv = 0; 1111 1112 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1113 "val = 0x%04hX\n", __func__, 1114 phy, (uint16_t) reg & 0xffff, val); 1115 1116 /* 1117 * The BCM5709S PHY is an IEEE Clause 45 PHY 1118 * with special mappings to work with IEEE 1119 * Clause 22 register accesses. 1120 */ 1121 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1122 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1123 reg += 0x10; 1124 } 1125 1126 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1127 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1128 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1129 1130 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1131 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1132 1133 DELAY(40); 1134 } 1135 1136 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1137 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1138 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1139 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1140 1141 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1142 DELAY(10); 1143 1144 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1145 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1146 DELAY(5); 1147 break; 1148 } 1149 } 1150 1151 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1152 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1153 __LINE__); 1154 rv = ETIMEDOUT; 1155 } 1156 1157 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1158 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1159 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1160 1161 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1162 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1163 1164 DELAY(40); 1165 } 1166 1167 return rv; 1168 } 1169 1170 /****************************************************************************/ 1171 /* MII bus status change. */ 1172 /* */ 1173 /* Called by the MII bus driver when the PHY establishes link to set the */ 1174 /* MAC interface registers. */ 1175 /* */ 1176 /* Returns: */ 1177 /* Nothing. */ 1178 /****************************************************************************/ 1179 void 1180 bnx_miibus_statchg(struct ifnet *ifp) 1181 { 1182 struct bnx_softc *sc = ifp->if_softc; 1183 struct mii_data *mii = &sc->bnx_mii; 1184 uint32_t rx_mode = sc->rx_mode; 1185 int val; 1186 1187 val = REG_RD(sc, BNX_EMAC_MODE); 1188 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1189 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1190 BNX_EMAC_MODE_25G); 1191 1192 /* 1193 * Get flow control negotiation result. 1194 */ 1195 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1196 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1197 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1198 mii->mii_media_active &= ~IFM_ETH_FMASK; 1199 } 1200 1201 /* Set MII or GMII interface based on the speed 1202 * negotiated by the PHY. 1203 */ 1204 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1205 case IFM_10_T: 1206 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1207 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1208 val |= BNX_EMAC_MODE_PORT_MII_10; 1209 break; 1210 } 1211 /* FALLTHROUGH */ 1212 case IFM_100_TX: 1213 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1214 val |= BNX_EMAC_MODE_PORT_MII; 1215 break; 1216 case IFM_2500_SX: 1217 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1218 val |= BNX_EMAC_MODE_25G; 1219 /* FALLTHROUGH */ 1220 case IFM_1000_T: 1221 case IFM_1000_SX: 1222 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1223 val |= BNX_EMAC_MODE_PORT_GMII; 1224 break; 1225 default: 1226 val |= BNX_EMAC_MODE_PORT_GMII; 1227 break; 1228 } 1229 1230 /* Set half or full duplex based on the duplicity 1231 * negotiated by the PHY. 1232 */ 1233 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1234 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1235 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1236 } else 1237 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1238 1239 REG_WR(sc, BNX_EMAC_MODE, val); 1240 1241 /* 1242 * 802.3x flow control 1243 */ 1244 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1245 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1246 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1247 } else { 1248 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1249 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1250 } 1251 1252 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1253 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1254 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1255 } else { 1256 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1257 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1258 } 1259 1260 /* Only make changes if the recive mode has actually changed. */ 1261 if (rx_mode != sc->rx_mode) { 1262 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1263 rx_mode); 1264 1265 sc->rx_mode = rx_mode; 1266 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1267 1268 bnx_init_rx_context(sc); 1269 } 1270 } 1271 1272 /****************************************************************************/ 1273 /* Acquire NVRAM lock. */ 1274 /* */ 1275 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1276 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1277 /* for use by the driver. */ 1278 /* */ 1279 /* Returns: */ 1280 /* 0 on success, positive value on failure. */ 1281 /****************************************************************************/ 1282 int 1283 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1284 { 1285 uint32_t val; 1286 int j; 1287 1288 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1289 1290 /* Request access to the flash interface. */ 1291 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1292 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1293 val = REG_RD(sc, BNX_NVM_SW_ARB); 1294 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1295 break; 1296 1297 DELAY(5); 1298 } 1299 1300 if (j >= NVRAM_TIMEOUT_COUNT) { 1301 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1302 return EBUSY; 1303 } 1304 1305 return 0; 1306 } 1307 1308 /****************************************************************************/ 1309 /* Release NVRAM lock. */ 1310 /* */ 1311 /* When the caller is finished accessing NVRAM the lock must be released. */ 1312 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1313 /* for use by the driver. */ 1314 /* */ 1315 /* Returns: */ 1316 /* 0 on success, positive value on failure. */ 1317 /****************************************************************************/ 1318 int 1319 bnx_release_nvram_lock(struct bnx_softc *sc) 1320 { 1321 int j; 1322 uint32_t val; 1323 1324 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1325 1326 /* Relinquish nvram interface. */ 1327 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1328 1329 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1330 val = REG_RD(sc, BNX_NVM_SW_ARB); 1331 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1332 break; 1333 1334 DELAY(5); 1335 } 1336 1337 if (j >= NVRAM_TIMEOUT_COUNT) { 1338 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1339 return EBUSY; 1340 } 1341 1342 return 0; 1343 } 1344 1345 #ifdef BNX_NVRAM_WRITE_SUPPORT 1346 /****************************************************************************/ 1347 /* Enable NVRAM write access. */ 1348 /* */ 1349 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1350 /* */ 1351 /* Returns: */ 1352 /* 0 on success, positive value on failure. */ 1353 /****************************************************************************/ 1354 int 1355 bnx_enable_nvram_write(struct bnx_softc *sc) 1356 { 1357 uint32_t val; 1358 1359 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1360 1361 val = REG_RD(sc, BNX_MISC_CFG); 1362 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1363 1364 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1365 int j; 1366 1367 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1368 REG_WR(sc, BNX_NVM_COMMAND, 1369 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1370 1371 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1372 DELAY(5); 1373 1374 val = REG_RD(sc, BNX_NVM_COMMAND); 1375 if (val & BNX_NVM_COMMAND_DONE) 1376 break; 1377 } 1378 1379 if (j >= NVRAM_TIMEOUT_COUNT) { 1380 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1381 return EBUSY; 1382 } 1383 } 1384 1385 return 0; 1386 } 1387 1388 /****************************************************************************/ 1389 /* Disable NVRAM write access. */ 1390 /* */ 1391 /* When the caller is finished writing to NVRAM write access must be */ 1392 /* disabled. */ 1393 /* */ 1394 /* Returns: */ 1395 /* Nothing. */ 1396 /****************************************************************************/ 1397 void 1398 bnx_disable_nvram_write(struct bnx_softc *sc) 1399 { 1400 uint32_t val; 1401 1402 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1403 1404 val = REG_RD(sc, BNX_MISC_CFG); 1405 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1406 } 1407 #endif 1408 1409 /****************************************************************************/ 1410 /* Enable NVRAM access. */ 1411 /* */ 1412 /* Before accessing NVRAM for read or write operations the caller must */ 1413 /* enabled NVRAM access. */ 1414 /* */ 1415 /* Returns: */ 1416 /* Nothing. */ 1417 /****************************************************************************/ 1418 void 1419 bnx_enable_nvram_access(struct bnx_softc *sc) 1420 { 1421 uint32_t val; 1422 1423 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1424 1425 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1426 /* Enable both bits, even on read. */ 1427 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1428 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1429 } 1430 1431 /****************************************************************************/ 1432 /* Disable NVRAM access. */ 1433 /* */ 1434 /* When the caller is finished accessing NVRAM access must be disabled. */ 1435 /* */ 1436 /* Returns: */ 1437 /* Nothing. */ 1438 /****************************************************************************/ 1439 void 1440 bnx_disable_nvram_access(struct bnx_softc *sc) 1441 { 1442 uint32_t val; 1443 1444 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1445 1446 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1447 1448 /* Disable both bits, even after read. */ 1449 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1450 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1451 } 1452 1453 #ifdef BNX_NVRAM_WRITE_SUPPORT 1454 /****************************************************************************/ 1455 /* Erase NVRAM page before writing. */ 1456 /* */ 1457 /* Non-buffered flash parts require that a page be erased before it is */ 1458 /* written. */ 1459 /* */ 1460 /* Returns: */ 1461 /* 0 on success, positive value on failure. */ 1462 /****************************************************************************/ 1463 int 1464 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1465 { 1466 uint32_t cmd; 1467 int j; 1468 1469 /* Buffered flash doesn't require an erase. */ 1470 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1471 return 0; 1472 1473 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1474 1475 /* Build an erase command. */ 1476 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1477 BNX_NVM_COMMAND_DOIT; 1478 1479 /* 1480 * Clear the DONE bit separately, set the NVRAM address to erase, 1481 * and issue the erase command. 1482 */ 1483 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1484 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1485 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1486 1487 /* Wait for completion. */ 1488 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1489 uint32_t val; 1490 1491 DELAY(5); 1492 1493 val = REG_RD(sc, BNX_NVM_COMMAND); 1494 if (val & BNX_NVM_COMMAND_DONE) 1495 break; 1496 } 1497 1498 if (j >= NVRAM_TIMEOUT_COUNT) { 1499 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1500 return EBUSY; 1501 } 1502 1503 return 0; 1504 } 1505 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1506 1507 /****************************************************************************/ 1508 /* Read a dword (32 bits) from NVRAM. */ 1509 /* */ 1510 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1511 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1512 /* */ 1513 /* Returns: */ 1514 /* 0 on success and the 32 bit value read, positive value on failure. */ 1515 /****************************************************************************/ 1516 int 1517 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1518 uint8_t *ret_val, uint32_t cmd_flags) 1519 { 1520 uint32_t cmd; 1521 int i, rc = 0; 1522 1523 /* Build the command word. */ 1524 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1525 1526 /* Calculate the offset for buffered flash if translation is used. */ 1527 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1528 offset = ((offset / sc->bnx_flash_info->page_size) << 1529 sc->bnx_flash_info->page_bits) + 1530 (offset % sc->bnx_flash_info->page_size); 1531 } 1532 1533 /* 1534 * Clear the DONE bit separately, set the address to read, 1535 * and issue the read. 1536 */ 1537 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1538 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1539 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1540 1541 /* Wait for completion. */ 1542 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1543 uint32_t val; 1544 1545 DELAY(5); 1546 1547 val = REG_RD(sc, BNX_NVM_COMMAND); 1548 if (val & BNX_NVM_COMMAND_DONE) { 1549 val = REG_RD(sc, BNX_NVM_READ); 1550 1551 val = bnx_be32toh(val); 1552 memcpy(ret_val, &val, 4); 1553 break; 1554 } 1555 } 1556 1557 /* Check for errors. */ 1558 if (i >= NVRAM_TIMEOUT_COUNT) { 1559 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1560 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1561 rc = EBUSY; 1562 } 1563 1564 return rc; 1565 } 1566 1567 #ifdef BNX_NVRAM_WRITE_SUPPORT 1568 /****************************************************************************/ 1569 /* Write a dword (32 bits) to NVRAM. */ 1570 /* */ 1571 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1572 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1573 /* enabled NVRAM write access. */ 1574 /* */ 1575 /* Returns: */ 1576 /* 0 on success, positive value on failure. */ 1577 /****************************************************************************/ 1578 int 1579 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1580 uint32_t cmd_flags) 1581 { 1582 uint32_t cmd, val32; 1583 int j; 1584 1585 /* Build the command word. */ 1586 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1587 1588 /* Calculate the offset for buffered flash if translation is used. */ 1589 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1590 offset = ((offset / sc->bnx_flash_info->page_size) << 1591 sc->bnx_flash_info->page_bits) + 1592 (offset % sc->bnx_flash_info->page_size); 1593 } 1594 1595 /* 1596 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1597 * set the NVRAM address to write, and issue the write command 1598 */ 1599 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1600 memcpy(&val32, val, 4); 1601 val32 = htobe32(val32); 1602 REG_WR(sc, BNX_NVM_WRITE, val32); 1603 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1604 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1605 1606 /* Wait for completion. */ 1607 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1608 DELAY(5); 1609 1610 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1611 break; 1612 } 1613 if (j >= NVRAM_TIMEOUT_COUNT) { 1614 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1615 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1616 return EBUSY; 1617 } 1618 1619 return 0; 1620 } 1621 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1622 1623 /****************************************************************************/ 1624 /* Initialize NVRAM access. */ 1625 /* */ 1626 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1627 /* access that device. */ 1628 /* */ 1629 /* Returns: */ 1630 /* 0 on success, positive value on failure. */ 1631 /****************************************************************************/ 1632 int 1633 bnx_init_nvram(struct bnx_softc *sc) 1634 { 1635 uint32_t val; 1636 int j, entry_count, rc = 0; 1637 struct flash_spec *flash; 1638 1639 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1640 1641 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1642 sc->bnx_flash_info = &flash_5709; 1643 goto bnx_init_nvram_get_flash_size; 1644 } 1645 1646 /* Determine the selected interface. */ 1647 val = REG_RD(sc, BNX_NVM_CFG1); 1648 1649 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1650 1651 /* 1652 * Flash reconfiguration is required to support additional 1653 * NVRAM devices not directly supported in hardware. 1654 * Check if the flash interface was reconfigured 1655 * by the bootcode. 1656 */ 1657 1658 if (val & 0x40000000) { 1659 /* Flash interface reconfigured by bootcode. */ 1660 1661 DBPRINT(sc,BNX_INFO_LOAD, 1662 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1663 1664 for (j = 0, flash = &flash_table[0]; j < entry_count; 1665 j++, flash++) { 1666 if ((val & FLASH_BACKUP_STRAP_MASK) == 1667 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1668 sc->bnx_flash_info = flash; 1669 break; 1670 } 1671 } 1672 } else { 1673 /* Flash interface not yet reconfigured. */ 1674 uint32_t mask; 1675 1676 DBPRINT(sc,BNX_INFO_LOAD, 1677 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1678 1679 if (val & (1 << 23)) 1680 mask = FLASH_BACKUP_STRAP_MASK; 1681 else 1682 mask = FLASH_STRAP_MASK; 1683 1684 /* Look for the matching NVRAM device configuration data. */ 1685 for (j = 0, flash = &flash_table[0]; j < entry_count; 1686 j++, flash++) { 1687 /* Check if the dev matches any of the known devices. */ 1688 if ((val & mask) == (flash->strapping & mask)) { 1689 /* Found a device match. */ 1690 sc->bnx_flash_info = flash; 1691 1692 /* Request access to the flash interface. */ 1693 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1694 return rc; 1695 1696 /* Reconfigure the flash interface. */ 1697 bnx_enable_nvram_access(sc); 1698 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1699 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1700 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1701 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1702 bnx_disable_nvram_access(sc); 1703 bnx_release_nvram_lock(sc); 1704 1705 break; 1706 } 1707 } 1708 } 1709 1710 /* Check if a matching device was found. */ 1711 if (j == entry_count) { 1712 sc->bnx_flash_info = NULL; 1713 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1714 __FILE__, __LINE__); 1715 rc = ENODEV; 1716 } 1717 1718 bnx_init_nvram_get_flash_size: 1719 /* Write the flash config data to the shared memory interface. */ 1720 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1721 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1722 if (val) 1723 sc->bnx_flash_size = val; 1724 else 1725 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1726 1727 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1728 "0x%08X\n", sc->bnx_flash_info->total_size); 1729 1730 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1731 1732 return rc; 1733 } 1734 1735 /****************************************************************************/ 1736 /* Read an arbitrary range of data from NVRAM. */ 1737 /* */ 1738 /* Prepares the NVRAM interface for access and reads the requested data */ 1739 /* into the supplied buffer. */ 1740 /* */ 1741 /* Returns: */ 1742 /* 0 on success and the data read, positive value on failure. */ 1743 /****************************************************************************/ 1744 int 1745 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1746 int buf_size) 1747 { 1748 int rc = 0; 1749 uint32_t cmd_flags, offset32, len32, extra; 1750 1751 if (buf_size == 0) 1752 return 0; 1753 1754 /* Request access to the flash interface. */ 1755 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1756 return rc; 1757 1758 /* Enable access to flash interface */ 1759 bnx_enable_nvram_access(sc); 1760 1761 len32 = buf_size; 1762 offset32 = offset; 1763 extra = 0; 1764 1765 cmd_flags = 0; 1766 1767 if (offset32 & 3) { 1768 uint8_t buf[4]; 1769 uint32_t pre_len; 1770 1771 offset32 &= ~3; 1772 pre_len = 4 - (offset & 3); 1773 1774 if (pre_len >= len32) { 1775 pre_len = len32; 1776 cmd_flags = 1777 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1778 } else 1779 cmd_flags = BNX_NVM_COMMAND_FIRST; 1780 1781 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1782 1783 if (rc) 1784 return rc; 1785 1786 memcpy(ret_buf, buf + (offset & 3), pre_len); 1787 1788 offset32 += 4; 1789 ret_buf += pre_len; 1790 len32 -= pre_len; 1791 } 1792 1793 if (len32 & 3) { 1794 extra = 4 - (len32 & 3); 1795 len32 = (len32 + 4) & ~3; 1796 } 1797 1798 if (len32 == 4) { 1799 uint8_t buf[4]; 1800 1801 if (cmd_flags) 1802 cmd_flags = BNX_NVM_COMMAND_LAST; 1803 else 1804 cmd_flags = 1805 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1806 1807 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1808 1809 memcpy(ret_buf, buf, 4 - extra); 1810 } else if (len32 > 0) { 1811 uint8_t buf[4]; 1812 1813 /* Read the first word. */ 1814 if (cmd_flags) 1815 cmd_flags = 0; 1816 else 1817 cmd_flags = BNX_NVM_COMMAND_FIRST; 1818 1819 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1820 1821 /* Advance to the next dword. */ 1822 offset32 += 4; 1823 ret_buf += 4; 1824 len32 -= 4; 1825 1826 while (len32 > 4 && rc == 0) { 1827 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1828 1829 /* Advance to the next dword. */ 1830 offset32 += 4; 1831 ret_buf += 4; 1832 len32 -= 4; 1833 } 1834 1835 if (rc) 1836 return rc; 1837 1838 cmd_flags = BNX_NVM_COMMAND_LAST; 1839 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1840 1841 memcpy(ret_buf, buf, 4 - extra); 1842 } 1843 1844 /* Disable access to flash interface and release the lock. */ 1845 bnx_disable_nvram_access(sc); 1846 bnx_release_nvram_lock(sc); 1847 1848 return rc; 1849 } 1850 1851 #ifdef BNX_NVRAM_WRITE_SUPPORT 1852 /****************************************************************************/ 1853 /* Write an arbitrary range of data from NVRAM. */ 1854 /* */ 1855 /* Prepares the NVRAM interface for write access and writes the requested */ 1856 /* data from the supplied buffer. The caller is responsible for */ 1857 /* calculating any appropriate CRCs. */ 1858 /* */ 1859 /* Returns: */ 1860 /* 0 on success, positive value on failure. */ 1861 /****************************************************************************/ 1862 int 1863 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1864 int buf_size) 1865 { 1866 uint32_t written, offset32, len32; 1867 uint8_t *buf, start[4], end[4]; 1868 int rc = 0; 1869 int align_start, align_end; 1870 1871 buf = data_buf; 1872 offset32 = offset; 1873 len32 = buf_size; 1874 align_start = align_end = 0; 1875 1876 if ((align_start = (offset32 & 3))) { 1877 offset32 &= ~3; 1878 len32 += align_start; 1879 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1880 return rc; 1881 } 1882 1883 if (len32 & 3) { 1884 if ((len32 > 4) || !align_start) { 1885 align_end = 4 - (len32 & 3); 1886 len32 += align_end; 1887 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1888 end, 4))) 1889 return rc; 1890 } 1891 } 1892 1893 if (align_start || align_end) { 1894 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1895 if (buf == NULL) 1896 return ENOMEM; 1897 1898 if (align_start) 1899 memcpy(buf, start, 4); 1900 1901 if (align_end) 1902 memcpy(buf + len32 - 4, end, 4); 1903 1904 memcpy(buf + align_start, data_buf, buf_size); 1905 } 1906 1907 written = 0; 1908 while ((written < len32) && (rc == 0)) { 1909 uint32_t page_start, page_end, data_start, data_end; 1910 uint32_t addr, cmd_flags; 1911 int i; 1912 uint8_t flash_buffer[264]; 1913 1914 /* Find the page_start addr */ 1915 page_start = offset32 + written; 1916 page_start -= (page_start % sc->bnx_flash_info->page_size); 1917 /* Find the page_end addr */ 1918 page_end = page_start + sc->bnx_flash_info->page_size; 1919 /* Find the data_start addr */ 1920 data_start = (written == 0) ? offset32 : page_start; 1921 /* Find the data_end addr */ 1922 data_end = (page_end > offset32 + len32) ? 1923 (offset32 + len32) : page_end; 1924 1925 /* Request access to the flash interface. */ 1926 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1927 goto nvram_write_end; 1928 1929 /* Enable access to flash interface */ 1930 bnx_enable_nvram_access(sc); 1931 1932 cmd_flags = BNX_NVM_COMMAND_FIRST; 1933 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1934 int j; 1935 1936 /* Read the whole page into the buffer 1937 * (non-buffer flash only) */ 1938 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 1939 if (j == (sc->bnx_flash_info->page_size - 4)) 1940 cmd_flags |= BNX_NVM_COMMAND_LAST; 1941 1942 rc = bnx_nvram_read_dword(sc, 1943 page_start + j, 1944 &flash_buffer[j], 1945 cmd_flags); 1946 1947 if (rc) 1948 goto nvram_write_end; 1949 1950 cmd_flags = 0; 1951 } 1952 } 1953 1954 /* Enable writes to flash interface (unlock write-protect) */ 1955 if ((rc = bnx_enable_nvram_write(sc)) != 0) 1956 goto nvram_write_end; 1957 1958 /* Erase the page */ 1959 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 1960 goto nvram_write_end; 1961 1962 /* Re-enable the write again for the actual write */ 1963 bnx_enable_nvram_write(sc); 1964 1965 /* Loop to write back the buffer data from page_start to 1966 * data_start */ 1967 i = 0; 1968 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1969 for (addr = page_start; addr < data_start; 1970 addr += 4, i += 4) { 1971 1972 rc = bnx_nvram_write_dword(sc, addr, 1973 &flash_buffer[i], cmd_flags); 1974 1975 if (rc != 0) 1976 goto nvram_write_end; 1977 1978 cmd_flags = 0; 1979 } 1980 } 1981 1982 /* Loop to write the new data from data_start to data_end */ 1983 for (addr = data_start; addr < data_end; addr += 4, i++) { 1984 if ((addr == page_end - 4) || 1985 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 1986 && (addr == data_end - 4))) { 1987 1988 cmd_flags |= BNX_NVM_COMMAND_LAST; 1989 } 1990 1991 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 1992 1993 if (rc != 0) 1994 goto nvram_write_end; 1995 1996 cmd_flags = 0; 1997 buf += 4; 1998 } 1999 2000 /* Loop to write back the buffer data from data_end 2001 * to page_end */ 2002 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2003 for (addr = data_end; addr < page_end; 2004 addr += 4, i += 4) { 2005 2006 if (addr == page_end-4) 2007 cmd_flags = BNX_NVM_COMMAND_LAST; 2008 2009 rc = bnx_nvram_write_dword(sc, addr, 2010 &flash_buffer[i], cmd_flags); 2011 2012 if (rc != 0) 2013 goto nvram_write_end; 2014 2015 cmd_flags = 0; 2016 } 2017 } 2018 2019 /* Disable writes to flash interface (lock write-protect) */ 2020 bnx_disable_nvram_write(sc); 2021 2022 /* Disable access to flash interface */ 2023 bnx_disable_nvram_access(sc); 2024 bnx_release_nvram_lock(sc); 2025 2026 /* Increment written */ 2027 written += data_end - data_start; 2028 } 2029 2030 nvram_write_end: 2031 if (align_start || align_end) 2032 free(buf, M_DEVBUF); 2033 2034 return rc; 2035 } 2036 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2037 2038 /****************************************************************************/ 2039 /* Verifies that NVRAM is accessible and contains valid data. */ 2040 /* */ 2041 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2042 /* correct. */ 2043 /* */ 2044 /* Returns: */ 2045 /* 0 on success, positive value on failure. */ 2046 /****************************************************************************/ 2047 int 2048 bnx_nvram_test(struct bnx_softc *sc) 2049 { 2050 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2051 uint8_t *data = (uint8_t *) buf; 2052 int rc = 0; 2053 uint32_t magic, csum; 2054 2055 /* 2056 * Check that the device NVRAM is valid by reading 2057 * the magic value at offset 0. 2058 */ 2059 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2060 goto bnx_nvram_test_done; 2061 2062 magic = bnx_be32toh(buf[0]); 2063 if (magic != BNX_NVRAM_MAGIC) { 2064 rc = ENODEV; 2065 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2066 "Expected: 0x%08X, Found: 0x%08X\n", 2067 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2068 goto bnx_nvram_test_done; 2069 } 2070 2071 /* 2072 * Verify that the device NVRAM includes valid 2073 * configuration data. 2074 */ 2075 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2076 goto bnx_nvram_test_done; 2077 2078 csum = ether_crc32_le(data, 0x100); 2079 if (csum != BNX_CRC32_RESIDUAL) { 2080 rc = ENODEV; 2081 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2082 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2083 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2084 goto bnx_nvram_test_done; 2085 } 2086 2087 csum = ether_crc32_le(data + 0x100, 0x100); 2088 if (csum != BNX_CRC32_RESIDUAL) { 2089 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2090 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2091 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2092 rc = ENODEV; 2093 } 2094 2095 bnx_nvram_test_done: 2096 return rc; 2097 } 2098 2099 /****************************************************************************/ 2100 /* Identifies the current media type of the controller and sets the PHY */ 2101 /* address. */ 2102 /* */ 2103 /* Returns: */ 2104 /* Nothing. */ 2105 /****************************************************************************/ 2106 void 2107 bnx_get_media(struct bnx_softc *sc) 2108 { 2109 sc->bnx_phy_addr = 1; 2110 2111 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2112 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2113 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2114 uint32_t strap; 2115 2116 /* 2117 * The BCM5709S is software configurable 2118 * for Copper or SerDes operation. 2119 */ 2120 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2121 DBPRINT(sc, BNX_INFO_LOAD, 2122 "5709 bonded for copper.\n"); 2123 goto bnx_get_media_exit; 2124 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2125 DBPRINT(sc, BNX_INFO_LOAD, 2126 "5709 bonded for dual media.\n"); 2127 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2128 goto bnx_get_media_exit; 2129 } 2130 2131 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2132 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2133 else { 2134 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2135 >> 8; 2136 } 2137 2138 if (sc->bnx_pa.pa_function == 0) { 2139 switch (strap) { 2140 case 0x4: 2141 case 0x5: 2142 case 0x6: 2143 DBPRINT(sc, BNX_INFO_LOAD, 2144 "BCM5709 s/w configured for SerDes.\n"); 2145 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2146 break; 2147 default: 2148 DBPRINT(sc, BNX_INFO_LOAD, 2149 "BCM5709 s/w configured for Copper.\n"); 2150 } 2151 } else { 2152 switch (strap) { 2153 case 0x1: 2154 case 0x2: 2155 case 0x4: 2156 DBPRINT(sc, BNX_INFO_LOAD, 2157 "BCM5709 s/w configured for SerDes.\n"); 2158 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2159 break; 2160 default: 2161 DBPRINT(sc, BNX_INFO_LOAD, 2162 "BCM5709 s/w configured for Copper.\n"); 2163 } 2164 } 2165 2166 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2167 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2168 2169 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2170 uint32_t val; 2171 2172 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2173 2174 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2175 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2176 2177 /* 2178 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2179 * separate PHY for SerDes. 2180 */ 2181 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2182 sc->bnx_phy_addr = 2; 2183 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2184 BNX_SHARED_HW_CFG_CONFIG); 2185 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2186 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2187 DBPRINT(sc, BNX_INFO_LOAD, 2188 "Found 2.5Gb capable adapter\n"); 2189 } 2190 } 2191 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2192 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2193 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2194 2195 bnx_get_media_exit: 2196 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2197 "Using PHY address %d.\n", sc->bnx_phy_addr); 2198 } 2199 2200 /****************************************************************************/ 2201 /* Performs PHY initialization required before MII drivers access the */ 2202 /* device. */ 2203 /* */ 2204 /* Returns: */ 2205 /* Nothing. */ 2206 /****************************************************************************/ 2207 void 2208 bnx_init_media(struct bnx_softc *sc) 2209 { 2210 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2211 /* 2212 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2213 * IEEE Clause 22 method. Otherwise we have no way to attach 2214 * the PHY to the mii(4) layer. PHY specific configuration 2215 * is done by the mii(4) layer. 2216 */ 2217 2218 /* Select auto-negotiation MMD of the PHY. */ 2219 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2220 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2221 2222 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2223 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2224 2225 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2226 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2227 } 2228 } 2229 2230 /****************************************************************************/ 2231 /* Free any DMA memory owned by the driver. */ 2232 /* */ 2233 /* Scans through each data structre that requires DMA memory and frees */ 2234 /* the memory if allocated. */ 2235 /* */ 2236 /* Returns: */ 2237 /* Nothing. */ 2238 /****************************************************************************/ 2239 void 2240 bnx_dma_free(struct bnx_softc *sc) 2241 { 2242 int i; 2243 2244 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2245 2246 /* Destroy the status block. */ 2247 if (sc->status_block != NULL && sc->status_map != NULL) { 2248 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2249 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2250 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2251 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2252 BNX_STATUS_BLK_SZ); 2253 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2254 sc->status_rseg); 2255 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2256 sc->status_block = NULL; 2257 sc->status_map = NULL; 2258 } 2259 2260 /* Destroy the statistics block. */ 2261 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2262 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2263 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2264 BNX_STATS_BLK_SZ); 2265 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2266 sc->stats_rseg); 2267 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2268 sc->stats_block = NULL; 2269 sc->stats_map = NULL; 2270 } 2271 2272 /* Free, unmap and destroy all context memory pages. */ 2273 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2274 for (i = 0; i < sc->ctx_pages; i++) { 2275 if (sc->ctx_block[i] != NULL) { 2276 bus_dmamap_unload(sc->bnx_dmatag, 2277 sc->ctx_map[i]); 2278 bus_dmamem_unmap(sc->bnx_dmatag, 2279 (void *)sc->ctx_block[i], 2280 BCM_PAGE_SIZE); 2281 bus_dmamem_free(sc->bnx_dmatag, 2282 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2283 bus_dmamap_destroy(sc->bnx_dmatag, 2284 sc->ctx_map[i]); 2285 sc->ctx_block[i] = NULL; 2286 } 2287 } 2288 } 2289 2290 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2291 for (i = 0; i < TX_PAGES; i++ ) { 2292 if (sc->tx_bd_chain[i] != NULL && 2293 sc->tx_bd_chain_map[i] != NULL) { 2294 bus_dmamap_unload(sc->bnx_dmatag, 2295 sc->tx_bd_chain_map[i]); 2296 bus_dmamem_unmap(sc->bnx_dmatag, 2297 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2298 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2299 sc->tx_bd_chain_rseg[i]); 2300 bus_dmamap_destroy(sc->bnx_dmatag, 2301 sc->tx_bd_chain_map[i]); 2302 sc->tx_bd_chain[i] = NULL; 2303 sc->tx_bd_chain_map[i] = NULL; 2304 } 2305 } 2306 2307 /* Destroy the TX dmamaps. */ 2308 /* This isn't necessary since we dont allocate them up front */ 2309 2310 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2311 for (i = 0; i < RX_PAGES; i++ ) { 2312 if (sc->rx_bd_chain[i] != NULL && 2313 sc->rx_bd_chain_map[i] != NULL) { 2314 bus_dmamap_unload(sc->bnx_dmatag, 2315 sc->rx_bd_chain_map[i]); 2316 bus_dmamem_unmap(sc->bnx_dmatag, 2317 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2318 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2319 sc->rx_bd_chain_rseg[i]); 2320 2321 bus_dmamap_destroy(sc->bnx_dmatag, 2322 sc->rx_bd_chain_map[i]); 2323 sc->rx_bd_chain[i] = NULL; 2324 sc->rx_bd_chain_map[i] = NULL; 2325 } 2326 } 2327 2328 /* Unload and destroy the RX mbuf maps. */ 2329 for (i = 0; i < TOTAL_RX_BD; i++) { 2330 if (sc->rx_mbuf_map[i] != NULL) { 2331 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2332 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2333 } 2334 } 2335 2336 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2337 } 2338 2339 /****************************************************************************/ 2340 /* Allocate any DMA memory needed by the driver. */ 2341 /* */ 2342 /* Allocates DMA memory needed for the various global structures needed by */ 2343 /* hardware. */ 2344 /* */ 2345 /* Returns: */ 2346 /* 0 for success, positive value for failure. */ 2347 /****************************************************************************/ 2348 int 2349 bnx_dma_alloc(struct bnx_softc *sc) 2350 { 2351 int i, rc = 0; 2352 2353 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2354 2355 /* 2356 * Allocate DMA memory for the status block, map the memory into DMA 2357 * space, and fetch the physical address of the block. 2358 */ 2359 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2360 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2361 aprint_error_dev(sc->bnx_dev, 2362 "Could not create status block DMA map!\n"); 2363 rc = ENOMEM; 2364 goto bnx_dma_alloc_exit; 2365 } 2366 2367 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2368 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2369 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2370 aprint_error_dev(sc->bnx_dev, 2371 "Could not allocate status block DMA memory!\n"); 2372 rc = ENOMEM; 2373 goto bnx_dma_alloc_exit; 2374 } 2375 2376 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2377 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2378 aprint_error_dev(sc->bnx_dev, 2379 "Could not map status block DMA memory!\n"); 2380 rc = ENOMEM; 2381 goto bnx_dma_alloc_exit; 2382 } 2383 2384 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2385 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2386 aprint_error_dev(sc->bnx_dev, 2387 "Could not load status block DMA memory!\n"); 2388 rc = ENOMEM; 2389 goto bnx_dma_alloc_exit; 2390 } 2391 2392 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2393 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2394 2395 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2396 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2397 2398 /* DRC - Fix for 64 bit addresses. */ 2399 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2400 (uint32_t) sc->status_block_paddr); 2401 2402 /* BCM5709 uses host memory as cache for context memory. */ 2403 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2404 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2405 if (sc->ctx_pages == 0) 2406 sc->ctx_pages = 1; 2407 if (sc->ctx_pages > 4) /* XXX */ 2408 sc->ctx_pages = 4; 2409 2410 DBRUNIF((sc->ctx_pages > 512), 2411 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2412 __FILE__, __LINE__, sc->ctx_pages)); 2413 2414 2415 for (i = 0; i < sc->ctx_pages; i++) { 2416 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2417 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2418 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2419 &sc->ctx_map[i]) != 0) { 2420 rc = ENOMEM; 2421 goto bnx_dma_alloc_exit; 2422 } 2423 2424 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2425 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2426 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2427 rc = ENOMEM; 2428 goto bnx_dma_alloc_exit; 2429 } 2430 2431 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2432 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2433 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2434 rc = ENOMEM; 2435 goto bnx_dma_alloc_exit; 2436 } 2437 2438 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2439 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2440 BUS_DMA_NOWAIT) != 0) { 2441 rc = ENOMEM; 2442 goto bnx_dma_alloc_exit; 2443 } 2444 2445 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2446 } 2447 } 2448 2449 /* 2450 * Allocate DMA memory for the statistics block, map the memory into 2451 * DMA space, and fetch the physical address of the block. 2452 */ 2453 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2454 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2455 aprint_error_dev(sc->bnx_dev, 2456 "Could not create stats block DMA map!\n"); 2457 rc = ENOMEM; 2458 goto bnx_dma_alloc_exit; 2459 } 2460 2461 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2462 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2463 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2464 aprint_error_dev(sc->bnx_dev, 2465 "Could not allocate stats block DMA memory!\n"); 2466 rc = ENOMEM; 2467 goto bnx_dma_alloc_exit; 2468 } 2469 2470 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2471 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2472 aprint_error_dev(sc->bnx_dev, 2473 "Could not map stats block DMA memory!\n"); 2474 rc = ENOMEM; 2475 goto bnx_dma_alloc_exit; 2476 } 2477 2478 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2479 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2480 aprint_error_dev(sc->bnx_dev, 2481 "Could not load status block DMA memory!\n"); 2482 rc = ENOMEM; 2483 goto bnx_dma_alloc_exit; 2484 } 2485 2486 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2487 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2488 2489 /* DRC - Fix for 64 bit address. */ 2490 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2491 (uint32_t) sc->stats_block_paddr); 2492 2493 /* 2494 * Allocate DMA memory for the TX buffer descriptor chain, 2495 * and fetch the physical address of the block. 2496 */ 2497 for (i = 0; i < TX_PAGES; i++) { 2498 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2499 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2500 &sc->tx_bd_chain_map[i])) { 2501 aprint_error_dev(sc->bnx_dev, 2502 "Could not create Tx desc %d DMA map!\n", i); 2503 rc = ENOMEM; 2504 goto bnx_dma_alloc_exit; 2505 } 2506 2507 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2508 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2509 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2510 aprint_error_dev(sc->bnx_dev, 2511 "Could not allocate TX desc %d DMA memory!\n", 2512 i); 2513 rc = ENOMEM; 2514 goto bnx_dma_alloc_exit; 2515 } 2516 2517 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2518 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2519 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2520 aprint_error_dev(sc->bnx_dev, 2521 "Could not map TX desc %d DMA memory!\n", i); 2522 rc = ENOMEM; 2523 goto bnx_dma_alloc_exit; 2524 } 2525 2526 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2527 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2528 BUS_DMA_NOWAIT)) { 2529 aprint_error_dev(sc->bnx_dev, 2530 "Could not load TX desc %d DMA memory!\n", i); 2531 rc = ENOMEM; 2532 goto bnx_dma_alloc_exit; 2533 } 2534 2535 sc->tx_bd_chain_paddr[i] = 2536 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2537 2538 /* DRC - Fix for 64 bit systems. */ 2539 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2540 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2541 } 2542 2543 /* 2544 * Create lists to hold TX mbufs. 2545 */ 2546 TAILQ_INIT(&sc->tx_free_pkts); 2547 TAILQ_INIT(&sc->tx_used_pkts); 2548 sc->tx_pkt_count = 0; 2549 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2550 2551 /* 2552 * Allocate DMA memory for the Rx buffer descriptor chain, 2553 * and fetch the physical address of the block. 2554 */ 2555 for (i = 0; i < RX_PAGES; i++) { 2556 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2557 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2558 &sc->rx_bd_chain_map[i])) { 2559 aprint_error_dev(sc->bnx_dev, 2560 "Could not create Rx desc %d DMA map!\n", i); 2561 rc = ENOMEM; 2562 goto bnx_dma_alloc_exit; 2563 } 2564 2565 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2566 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2567 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2568 aprint_error_dev(sc->bnx_dev, 2569 "Could not allocate Rx desc %d DMA memory!\n", i); 2570 rc = ENOMEM; 2571 goto bnx_dma_alloc_exit; 2572 } 2573 2574 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2575 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2576 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2577 aprint_error_dev(sc->bnx_dev, 2578 "Could not map Rx desc %d DMA memory!\n", i); 2579 rc = ENOMEM; 2580 goto bnx_dma_alloc_exit; 2581 } 2582 2583 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2584 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2585 BUS_DMA_NOWAIT)) { 2586 aprint_error_dev(sc->bnx_dev, 2587 "Could not load Rx desc %d DMA memory!\n", i); 2588 rc = ENOMEM; 2589 goto bnx_dma_alloc_exit; 2590 } 2591 2592 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2593 sc->rx_bd_chain_paddr[i] = 2594 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2595 2596 /* DRC - Fix for 64 bit systems. */ 2597 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2598 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2599 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2600 0, BNX_RX_CHAIN_PAGE_SZ, 2601 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2602 } 2603 2604 /* 2605 * Create DMA maps for the Rx buffer mbufs. 2606 */ 2607 for (i = 0; i < TOTAL_RX_BD; i++) { 2608 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2609 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2610 &sc->rx_mbuf_map[i])) { 2611 aprint_error_dev(sc->bnx_dev, 2612 "Could not create Rx mbuf %d DMA map!\n", i); 2613 rc = ENOMEM; 2614 goto bnx_dma_alloc_exit; 2615 } 2616 } 2617 2618 bnx_dma_alloc_exit: 2619 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2620 2621 return rc; 2622 } 2623 2624 /****************************************************************************/ 2625 /* Release all resources used by the driver. */ 2626 /* */ 2627 /* Releases all resources acquired by the driver including interrupts, */ 2628 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2629 /* */ 2630 /* Returns: */ 2631 /* Nothing. */ 2632 /****************************************************************************/ 2633 void 2634 bnx_release_resources(struct bnx_softc *sc) 2635 { 2636 struct pci_attach_args *pa = &(sc->bnx_pa); 2637 2638 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2639 2640 bnx_dma_free(sc); 2641 2642 if (sc->bnx_intrhand != NULL) 2643 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2644 2645 if (sc->bnx_size) 2646 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2647 2648 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2649 } 2650 2651 /****************************************************************************/ 2652 /* Firmware synchronization. */ 2653 /* */ 2654 /* Before performing certain events such as a chip reset, synchronize with */ 2655 /* the firmware first. */ 2656 /* */ 2657 /* Returns: */ 2658 /* 0 for success, positive value for failure. */ 2659 /****************************************************************************/ 2660 int 2661 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2662 { 2663 int i, rc = 0; 2664 uint32_t val; 2665 2666 /* Don't waste any time if we've timed out before. */ 2667 if (sc->bnx_fw_timed_out) { 2668 rc = EBUSY; 2669 goto bnx_fw_sync_exit; 2670 } 2671 2672 /* Increment the message sequence number. */ 2673 sc->bnx_fw_wr_seq++; 2674 msg_data |= sc->bnx_fw_wr_seq; 2675 2676 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2677 msg_data); 2678 2679 /* Send the message to the bootcode driver mailbox. */ 2680 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2681 2682 /* Wait for the bootcode to acknowledge the message. */ 2683 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2684 /* Check for a response in the bootcode firmware mailbox. */ 2685 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2686 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2687 break; 2688 DELAY(1000); 2689 } 2690 2691 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2692 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2693 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2694 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2695 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2696 2697 msg_data &= ~BNX_DRV_MSG_CODE; 2698 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2699 2700 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2701 2702 sc->bnx_fw_timed_out = 1; 2703 rc = EBUSY; 2704 } 2705 2706 bnx_fw_sync_exit: 2707 return rc; 2708 } 2709 2710 /****************************************************************************/ 2711 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2712 /* */ 2713 /* Returns: */ 2714 /* Nothing. */ 2715 /****************************************************************************/ 2716 void 2717 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2718 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2719 { 2720 int i; 2721 uint32_t val; 2722 2723 /* Set the page size used by RV2P. */ 2724 if (rv2p_proc == RV2P_PROC2) { 2725 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2726 USABLE_RX_BD_PER_PAGE); 2727 } 2728 2729 for (i = 0; i < rv2p_code_len; i += 8) { 2730 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2731 rv2p_code++; 2732 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2733 rv2p_code++; 2734 2735 if (rv2p_proc == RV2P_PROC1) { 2736 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2737 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2738 } else { 2739 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2740 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2741 } 2742 } 2743 2744 /* Reset the processor, un-stall is done later. */ 2745 if (rv2p_proc == RV2P_PROC1) 2746 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2747 else 2748 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2749 } 2750 2751 /****************************************************************************/ 2752 /* Load RISC processor firmware. */ 2753 /* */ 2754 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2755 /* associated with a particular processor. */ 2756 /* */ 2757 /* Returns: */ 2758 /* Nothing. */ 2759 /****************************************************************************/ 2760 void 2761 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2762 struct fw_info *fw) 2763 { 2764 uint32_t offset; 2765 uint32_t val; 2766 2767 /* Halt the CPU. */ 2768 val = REG_RD_IND(sc, cpu_reg->mode); 2769 val |= cpu_reg->mode_value_halt; 2770 REG_WR_IND(sc, cpu_reg->mode, val); 2771 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2772 2773 /* Load the Text area. */ 2774 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2775 if (fw->text) { 2776 int j; 2777 2778 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2779 REG_WR_IND(sc, offset, fw->text[j]); 2780 } 2781 2782 /* Load the Data area. */ 2783 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2784 if (fw->data) { 2785 int j; 2786 2787 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2788 REG_WR_IND(sc, offset, fw->data[j]); 2789 } 2790 2791 /* Load the SBSS area. */ 2792 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2793 if (fw->sbss) { 2794 int j; 2795 2796 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2797 REG_WR_IND(sc, offset, fw->sbss[j]); 2798 } 2799 2800 /* Load the BSS area. */ 2801 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2802 if (fw->bss) { 2803 int j; 2804 2805 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2806 REG_WR_IND(sc, offset, fw->bss[j]); 2807 } 2808 2809 /* Load the Read-Only area. */ 2810 offset = cpu_reg->spad_base + 2811 (fw->rodata_addr - cpu_reg->mips_view_base); 2812 if (fw->rodata) { 2813 int j; 2814 2815 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2816 REG_WR_IND(sc, offset, fw->rodata[j]); 2817 } 2818 2819 /* Clear the pre-fetch instruction. */ 2820 REG_WR_IND(sc, cpu_reg->inst, 0); 2821 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2822 2823 /* Start the CPU. */ 2824 val = REG_RD_IND(sc, cpu_reg->mode); 2825 val &= ~cpu_reg->mode_value_halt; 2826 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2827 REG_WR_IND(sc, cpu_reg->mode, val); 2828 } 2829 2830 /****************************************************************************/ 2831 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2832 /* */ 2833 /* Loads the firmware for each CPU and starts the CPU. */ 2834 /* */ 2835 /* Returns: */ 2836 /* Nothing. */ 2837 /****************************************************************************/ 2838 void 2839 bnx_init_cpus(struct bnx_softc *sc) 2840 { 2841 struct cpu_reg cpu_reg; 2842 struct fw_info fw; 2843 2844 switch(BNX_CHIP_NUM(sc)) { 2845 case BNX_CHIP_NUM_5709: 2846 /* Initialize the RV2P processor. */ 2847 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2848 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2849 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2850 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2851 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2852 } else { 2853 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2854 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2855 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2856 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2857 } 2858 2859 /* Initialize the RX Processor. */ 2860 cpu_reg.mode = BNX_RXP_CPU_MODE; 2861 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2862 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2863 cpu_reg.state = BNX_RXP_CPU_STATE; 2864 cpu_reg.state_value_clear = 0xffffff; 2865 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2866 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2867 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2868 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2869 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2870 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2871 cpu_reg.mips_view_base = 0x8000000; 2872 2873 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2874 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2875 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2876 fw.start_addr = bnx_RXP_b09FwStartAddr; 2877 2878 fw.text_addr = bnx_RXP_b09FwTextAddr; 2879 fw.text_len = bnx_RXP_b09FwTextLen; 2880 fw.text_index = 0; 2881 fw.text = bnx_RXP_b09FwText; 2882 2883 fw.data_addr = bnx_RXP_b09FwDataAddr; 2884 fw.data_len = bnx_RXP_b09FwDataLen; 2885 fw.data_index = 0; 2886 fw.data = bnx_RXP_b09FwData; 2887 2888 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2889 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2890 fw.sbss_index = 0; 2891 fw.sbss = bnx_RXP_b09FwSbss; 2892 2893 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2894 fw.bss_len = bnx_RXP_b09FwBssLen; 2895 fw.bss_index = 0; 2896 fw.bss = bnx_RXP_b09FwBss; 2897 2898 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2899 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2900 fw.rodata_index = 0; 2901 fw.rodata = bnx_RXP_b09FwRodata; 2902 2903 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2904 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2905 2906 /* Initialize the TX Processor. */ 2907 cpu_reg.mode = BNX_TXP_CPU_MODE; 2908 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2909 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2910 cpu_reg.state = BNX_TXP_CPU_STATE; 2911 cpu_reg.state_value_clear = 0xffffff; 2912 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2913 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2914 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2915 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2916 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2917 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2918 cpu_reg.mips_view_base = 0x8000000; 2919 2920 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2921 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2922 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2923 fw.start_addr = bnx_TXP_b09FwStartAddr; 2924 2925 fw.text_addr = bnx_TXP_b09FwTextAddr; 2926 fw.text_len = bnx_TXP_b09FwTextLen; 2927 fw.text_index = 0; 2928 fw.text = bnx_TXP_b09FwText; 2929 2930 fw.data_addr = bnx_TXP_b09FwDataAddr; 2931 fw.data_len = bnx_TXP_b09FwDataLen; 2932 fw.data_index = 0; 2933 fw.data = bnx_TXP_b09FwData; 2934 2935 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 2936 fw.sbss_len = bnx_TXP_b09FwSbssLen; 2937 fw.sbss_index = 0; 2938 fw.sbss = bnx_TXP_b09FwSbss; 2939 2940 fw.bss_addr = bnx_TXP_b09FwBssAddr; 2941 fw.bss_len = bnx_TXP_b09FwBssLen; 2942 fw.bss_index = 0; 2943 fw.bss = bnx_TXP_b09FwBss; 2944 2945 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 2946 fw.rodata_len = bnx_TXP_b09FwRodataLen; 2947 fw.rodata_index = 0; 2948 fw.rodata = bnx_TXP_b09FwRodata; 2949 2950 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 2951 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2952 2953 /* Initialize the TX Patch-up Processor. */ 2954 cpu_reg.mode = BNX_TPAT_CPU_MODE; 2955 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 2956 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 2957 cpu_reg.state = BNX_TPAT_CPU_STATE; 2958 cpu_reg.state_value_clear = 0xffffff; 2959 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 2960 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 2961 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 2962 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 2963 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 2964 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 2965 cpu_reg.mips_view_base = 0x8000000; 2966 2967 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 2968 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 2969 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 2970 fw.start_addr = bnx_TPAT_b09FwStartAddr; 2971 2972 fw.text_addr = bnx_TPAT_b09FwTextAddr; 2973 fw.text_len = bnx_TPAT_b09FwTextLen; 2974 fw.text_index = 0; 2975 fw.text = bnx_TPAT_b09FwText; 2976 2977 fw.data_addr = bnx_TPAT_b09FwDataAddr; 2978 fw.data_len = bnx_TPAT_b09FwDataLen; 2979 fw.data_index = 0; 2980 fw.data = bnx_TPAT_b09FwData; 2981 2982 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 2983 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 2984 fw.sbss_index = 0; 2985 fw.sbss = bnx_TPAT_b09FwSbss; 2986 2987 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 2988 fw.bss_len = bnx_TPAT_b09FwBssLen; 2989 fw.bss_index = 0; 2990 fw.bss = bnx_TPAT_b09FwBss; 2991 2992 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 2993 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 2994 fw.rodata_index = 0; 2995 fw.rodata = bnx_TPAT_b09FwRodata; 2996 2997 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 2998 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2999 3000 /* Initialize the Completion Processor. */ 3001 cpu_reg.mode = BNX_COM_CPU_MODE; 3002 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3003 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3004 cpu_reg.state = BNX_COM_CPU_STATE; 3005 cpu_reg.state_value_clear = 0xffffff; 3006 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3007 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3008 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3009 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3010 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3011 cpu_reg.spad_base = BNX_COM_SCRATCH; 3012 cpu_reg.mips_view_base = 0x8000000; 3013 3014 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3015 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3016 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3017 fw.start_addr = bnx_COM_b09FwStartAddr; 3018 3019 fw.text_addr = bnx_COM_b09FwTextAddr; 3020 fw.text_len = bnx_COM_b09FwTextLen; 3021 fw.text_index = 0; 3022 fw.text = bnx_COM_b09FwText; 3023 3024 fw.data_addr = bnx_COM_b09FwDataAddr; 3025 fw.data_len = bnx_COM_b09FwDataLen; 3026 fw.data_index = 0; 3027 fw.data = bnx_COM_b09FwData; 3028 3029 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3030 fw.sbss_len = bnx_COM_b09FwSbssLen; 3031 fw.sbss_index = 0; 3032 fw.sbss = bnx_COM_b09FwSbss; 3033 3034 fw.bss_addr = bnx_COM_b09FwBssAddr; 3035 fw.bss_len = bnx_COM_b09FwBssLen; 3036 fw.bss_index = 0; 3037 fw.bss = bnx_COM_b09FwBss; 3038 3039 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3040 fw.rodata_len = bnx_COM_b09FwRodataLen; 3041 fw.rodata_index = 0; 3042 fw.rodata = bnx_COM_b09FwRodata; 3043 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3044 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3045 break; 3046 default: 3047 /* Initialize the RV2P processor. */ 3048 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3049 RV2P_PROC1); 3050 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3051 RV2P_PROC2); 3052 3053 /* Initialize the RX Processor. */ 3054 cpu_reg.mode = BNX_RXP_CPU_MODE; 3055 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3056 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3057 cpu_reg.state = BNX_RXP_CPU_STATE; 3058 cpu_reg.state_value_clear = 0xffffff; 3059 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3060 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3061 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3062 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3063 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3064 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3065 cpu_reg.mips_view_base = 0x8000000; 3066 3067 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3068 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3069 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3070 fw.start_addr = bnx_RXP_b06FwStartAddr; 3071 3072 fw.text_addr = bnx_RXP_b06FwTextAddr; 3073 fw.text_len = bnx_RXP_b06FwTextLen; 3074 fw.text_index = 0; 3075 fw.text = bnx_RXP_b06FwText; 3076 3077 fw.data_addr = bnx_RXP_b06FwDataAddr; 3078 fw.data_len = bnx_RXP_b06FwDataLen; 3079 fw.data_index = 0; 3080 fw.data = bnx_RXP_b06FwData; 3081 3082 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3083 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3084 fw.sbss_index = 0; 3085 fw.sbss = bnx_RXP_b06FwSbss; 3086 3087 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3088 fw.bss_len = bnx_RXP_b06FwBssLen; 3089 fw.bss_index = 0; 3090 fw.bss = bnx_RXP_b06FwBss; 3091 3092 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3093 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3094 fw.rodata_index = 0; 3095 fw.rodata = bnx_RXP_b06FwRodata; 3096 3097 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3098 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3099 3100 /* Initialize the TX Processor. */ 3101 cpu_reg.mode = BNX_TXP_CPU_MODE; 3102 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3103 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3104 cpu_reg.state = BNX_TXP_CPU_STATE; 3105 cpu_reg.state_value_clear = 0xffffff; 3106 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3107 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3108 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3109 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3110 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3111 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3112 cpu_reg.mips_view_base = 0x8000000; 3113 3114 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3115 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3116 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3117 fw.start_addr = bnx_TXP_b06FwStartAddr; 3118 3119 fw.text_addr = bnx_TXP_b06FwTextAddr; 3120 fw.text_len = bnx_TXP_b06FwTextLen; 3121 fw.text_index = 0; 3122 fw.text = bnx_TXP_b06FwText; 3123 3124 fw.data_addr = bnx_TXP_b06FwDataAddr; 3125 fw.data_len = bnx_TXP_b06FwDataLen; 3126 fw.data_index = 0; 3127 fw.data = bnx_TXP_b06FwData; 3128 3129 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3130 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3131 fw.sbss_index = 0; 3132 fw.sbss = bnx_TXP_b06FwSbss; 3133 3134 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3135 fw.bss_len = bnx_TXP_b06FwBssLen; 3136 fw.bss_index = 0; 3137 fw.bss = bnx_TXP_b06FwBss; 3138 3139 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3140 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3141 fw.rodata_index = 0; 3142 fw.rodata = bnx_TXP_b06FwRodata; 3143 3144 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3145 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3146 3147 /* Initialize the TX Patch-up Processor. */ 3148 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3149 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3150 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3151 cpu_reg.state = BNX_TPAT_CPU_STATE; 3152 cpu_reg.state_value_clear = 0xffffff; 3153 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3154 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3155 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3156 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3157 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3158 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3159 cpu_reg.mips_view_base = 0x8000000; 3160 3161 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3162 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3163 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3164 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3165 3166 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3167 fw.text_len = bnx_TPAT_b06FwTextLen; 3168 fw.text_index = 0; 3169 fw.text = bnx_TPAT_b06FwText; 3170 3171 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3172 fw.data_len = bnx_TPAT_b06FwDataLen; 3173 fw.data_index = 0; 3174 fw.data = bnx_TPAT_b06FwData; 3175 3176 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3177 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3178 fw.sbss_index = 0; 3179 fw.sbss = bnx_TPAT_b06FwSbss; 3180 3181 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3182 fw.bss_len = bnx_TPAT_b06FwBssLen; 3183 fw.bss_index = 0; 3184 fw.bss = bnx_TPAT_b06FwBss; 3185 3186 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3187 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3188 fw.rodata_index = 0; 3189 fw.rodata = bnx_TPAT_b06FwRodata; 3190 3191 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3192 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3193 3194 /* Initialize the Completion Processor. */ 3195 cpu_reg.mode = BNX_COM_CPU_MODE; 3196 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3197 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3198 cpu_reg.state = BNX_COM_CPU_STATE; 3199 cpu_reg.state_value_clear = 0xffffff; 3200 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3201 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3202 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3203 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3204 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3205 cpu_reg.spad_base = BNX_COM_SCRATCH; 3206 cpu_reg.mips_view_base = 0x8000000; 3207 3208 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3209 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3210 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3211 fw.start_addr = bnx_COM_b06FwStartAddr; 3212 3213 fw.text_addr = bnx_COM_b06FwTextAddr; 3214 fw.text_len = bnx_COM_b06FwTextLen; 3215 fw.text_index = 0; 3216 fw.text = bnx_COM_b06FwText; 3217 3218 fw.data_addr = bnx_COM_b06FwDataAddr; 3219 fw.data_len = bnx_COM_b06FwDataLen; 3220 fw.data_index = 0; 3221 fw.data = bnx_COM_b06FwData; 3222 3223 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3224 fw.sbss_len = bnx_COM_b06FwSbssLen; 3225 fw.sbss_index = 0; 3226 fw.sbss = bnx_COM_b06FwSbss; 3227 3228 fw.bss_addr = bnx_COM_b06FwBssAddr; 3229 fw.bss_len = bnx_COM_b06FwBssLen; 3230 fw.bss_index = 0; 3231 fw.bss = bnx_COM_b06FwBss; 3232 3233 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3234 fw.rodata_len = bnx_COM_b06FwRodataLen; 3235 fw.rodata_index = 0; 3236 fw.rodata = bnx_COM_b06FwRodata; 3237 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3238 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3239 break; 3240 } 3241 } 3242 3243 /****************************************************************************/ 3244 /* Initialize context memory. */ 3245 /* */ 3246 /* Clears the memory associated with each Context ID (CID). */ 3247 /* */ 3248 /* Returns: */ 3249 /* Nothing. */ 3250 /****************************************************************************/ 3251 void 3252 bnx_init_context(struct bnx_softc *sc) 3253 { 3254 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3255 /* DRC: Replace this constant value with a #define. */ 3256 int i, retry_cnt = 10; 3257 uint32_t val; 3258 3259 /* 3260 * BCM5709 context memory may be cached 3261 * in host memory so prepare the host memory 3262 * for access. 3263 */ 3264 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3265 | (1 << 12); 3266 val |= (BCM_PAGE_BITS - 8) << 16; 3267 REG_WR(sc, BNX_CTX_COMMAND, val); 3268 3269 /* Wait for mem init command to complete. */ 3270 for (i = 0; i < retry_cnt; i++) { 3271 val = REG_RD(sc, BNX_CTX_COMMAND); 3272 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3273 break; 3274 DELAY(2); 3275 } 3276 3277 /* ToDo: Consider returning an error here. */ 3278 3279 for (i = 0; i < sc->ctx_pages; i++) { 3280 int j; 3281 3282 /* Set the physaddr of the context memory cache. */ 3283 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3284 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3285 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3286 val = (uint32_t) 3287 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3288 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3289 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3290 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3291 3292 /* Verify that the context memory write was successful. */ 3293 for (j = 0; j < retry_cnt; j++) { 3294 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3295 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3296 break; 3297 DELAY(5); 3298 } 3299 3300 /* ToDo: Consider returning an error here. */ 3301 } 3302 } else { 3303 uint32_t vcid_addr, offset; 3304 3305 /* 3306 * For the 5706/5708, context memory is local to the 3307 * controller, so initialize the controller context memory. 3308 */ 3309 3310 vcid_addr = GET_CID_ADDR(96); 3311 while (vcid_addr) { 3312 3313 vcid_addr -= BNX_PHY_CTX_SIZE; 3314 3315 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3316 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3317 3318 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3319 offset += 4) 3320 CTX_WR(sc, 0x00, offset, 0); 3321 3322 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3323 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3324 } 3325 } 3326 } 3327 3328 /****************************************************************************/ 3329 /* Fetch the permanent MAC address of the controller. */ 3330 /* */ 3331 /* Returns: */ 3332 /* Nothing. */ 3333 /****************************************************************************/ 3334 void 3335 bnx_get_mac_addr(struct bnx_softc *sc) 3336 { 3337 uint32_t mac_lo = 0, mac_hi = 0; 3338 3339 /* 3340 * The NetXtreme II bootcode populates various NIC 3341 * power-on and runtime configuration items in a 3342 * shared memory area. The factory configured MAC 3343 * address is available from both NVRAM and the 3344 * shared memory area so we'll read the value from 3345 * shared memory for speed. 3346 */ 3347 3348 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3349 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3350 3351 if ((mac_lo == 0) && (mac_hi == 0)) { 3352 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3353 __FILE__, __LINE__); 3354 } else { 3355 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3356 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3357 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3358 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3359 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3360 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3361 } 3362 3363 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3364 "%s\n", ether_sprintf(sc->eaddr)); 3365 } 3366 3367 /****************************************************************************/ 3368 /* Program the MAC address. */ 3369 /* */ 3370 /* Returns: */ 3371 /* Nothing. */ 3372 /****************************************************************************/ 3373 void 3374 bnx_set_mac_addr(struct bnx_softc *sc) 3375 { 3376 uint32_t val; 3377 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3378 3379 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3380 "%s\n", ether_sprintf(sc->eaddr)); 3381 3382 val = (mac_addr[0] << 8) | mac_addr[1]; 3383 3384 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3385 3386 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3387 (mac_addr[4] << 8) | mac_addr[5]; 3388 3389 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3390 } 3391 3392 /****************************************************************************/ 3393 /* Stop the controller. */ 3394 /* */ 3395 /* Returns: */ 3396 /* Nothing. */ 3397 /****************************************************************************/ 3398 void 3399 bnx_stop(struct ifnet *ifp, int disable) 3400 { 3401 struct bnx_softc *sc = ifp->if_softc; 3402 3403 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3404 3405 if (disable) { 3406 sc->bnx_detaching = 1; 3407 callout_halt(&sc->bnx_timeout, NULL); 3408 } else 3409 callout_stop(&sc->bnx_timeout); 3410 3411 mii_down(&sc->bnx_mii); 3412 3413 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3414 3415 /* Disable the transmit/receive blocks. */ 3416 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3417 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3418 DELAY(20); 3419 3420 bnx_disable_intr(sc); 3421 3422 /* Tell firmware that the driver is going away. */ 3423 if (disable) 3424 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3425 else 3426 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3427 3428 /* Free RX buffers. */ 3429 bnx_free_rx_chain(sc); 3430 3431 /* Free TX buffers. */ 3432 bnx_free_tx_chain(sc); 3433 3434 ifp->if_timer = 0; 3435 3436 sc->bnx_link = 0; 3437 3438 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3439 3440 bnx_mgmt_init(sc); 3441 } 3442 3443 int 3444 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3445 { 3446 struct pci_attach_args *pa = &(sc->bnx_pa); 3447 uint32_t val; 3448 int i, rc = 0; 3449 3450 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3451 3452 /* Wait for pending PCI transactions to complete. */ 3453 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3454 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3455 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3456 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3457 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3458 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3459 DELAY(5); 3460 3461 /* Disable DMA */ 3462 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3463 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3464 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3465 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3466 } 3467 3468 /* Assume bootcode is running. */ 3469 sc->bnx_fw_timed_out = 0; 3470 3471 /* Give the firmware a chance to prepare for the reset. */ 3472 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3473 if (rc) 3474 goto bnx_reset_exit; 3475 3476 /* Set a firmware reminder that this is a soft reset. */ 3477 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3478 BNX_DRV_RESET_SIGNATURE_MAGIC); 3479 3480 /* Dummy read to force the chip to complete all current transactions. */ 3481 val = REG_RD(sc, BNX_MISC_ID); 3482 3483 /* Chip reset. */ 3484 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3485 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3486 REG_RD(sc, BNX_MISC_COMMAND); 3487 DELAY(5); 3488 3489 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3490 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3491 3492 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3493 val); 3494 } else { 3495 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3496 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3497 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3498 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3499 3500 /* Allow up to 30us for reset to complete. */ 3501 for (i = 0; i < 10; i++) { 3502 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3503 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3504 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3505 break; 3506 } 3507 DELAY(10); 3508 } 3509 3510 /* Check that reset completed successfully. */ 3511 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3512 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3513 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3514 __FILE__, __LINE__); 3515 rc = EBUSY; 3516 goto bnx_reset_exit; 3517 } 3518 } 3519 3520 /* Make sure byte swapping is properly configured. */ 3521 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3522 if (val != 0x01020304) { 3523 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3524 __FILE__, __LINE__); 3525 rc = ENODEV; 3526 goto bnx_reset_exit; 3527 } 3528 3529 /* Just completed a reset, assume that firmware is running again. */ 3530 sc->bnx_fw_timed_out = 0; 3531 3532 /* Wait for the firmware to finish its initialization. */ 3533 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3534 if (rc) 3535 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3536 "initialization!\n", __FILE__, __LINE__); 3537 3538 bnx_reset_exit: 3539 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3540 3541 return rc; 3542 } 3543 3544 int 3545 bnx_chipinit(struct bnx_softc *sc) 3546 { 3547 struct pci_attach_args *pa = &(sc->bnx_pa); 3548 uint32_t val; 3549 int rc = 0; 3550 3551 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3552 3553 /* Make sure the interrupt is not active. */ 3554 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3555 3556 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3557 /* channels and PCI clock compensation delay. */ 3558 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3559 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3560 #if BYTE_ORDER == BIG_ENDIAN 3561 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3562 #endif 3563 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3564 DMA_READ_CHANS << 12 | 3565 DMA_WRITE_CHANS << 16; 3566 3567 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3568 3569 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3570 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3571 3572 /* 3573 * This setting resolves a problem observed on certain Intel PCI 3574 * chipsets that cannot handle multiple outstanding DMA operations. 3575 * See errata E9_5706A1_65. 3576 */ 3577 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3578 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3579 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3580 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3581 3582 REG_WR(sc, BNX_DMA_CONFIG, val); 3583 3584 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3585 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3586 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3587 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3588 val & ~0x20000); 3589 } 3590 3591 /* Enable the RX_V2P and Context state machines before access. */ 3592 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3593 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3594 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3595 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3596 3597 /* Initialize context mapping and zero out the quick contexts. */ 3598 bnx_init_context(sc); 3599 3600 /* Initialize the on-boards CPUs */ 3601 bnx_init_cpus(sc); 3602 3603 /* Prepare NVRAM for access. */ 3604 if (bnx_init_nvram(sc)) { 3605 rc = ENODEV; 3606 goto bnx_chipinit_exit; 3607 } 3608 3609 /* Set the kernel bypass block size */ 3610 val = REG_RD(sc, BNX_MQ_CONFIG); 3611 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3612 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3613 3614 /* Enable bins used on the 5709. */ 3615 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3616 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3617 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3618 val |= BNX_MQ_CONFIG_HALT_DIS; 3619 } 3620 3621 REG_WR(sc, BNX_MQ_CONFIG, val); 3622 3623 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3624 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3625 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3626 3627 val = (BCM_PAGE_BITS - 8) << 24; 3628 REG_WR(sc, BNX_RV2P_CONFIG, val); 3629 3630 /* Configure page size. */ 3631 val = REG_RD(sc, BNX_TBDR_CONFIG); 3632 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3633 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3634 REG_WR(sc, BNX_TBDR_CONFIG, val); 3635 3636 #if 0 3637 /* Set the perfect match control register to default. */ 3638 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3639 #endif 3640 3641 bnx_chipinit_exit: 3642 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3643 3644 return rc; 3645 } 3646 3647 /****************************************************************************/ 3648 /* Initialize the controller in preparation to send/receive traffic. */ 3649 /* */ 3650 /* Returns: */ 3651 /* 0 for success, positive value for failure. */ 3652 /****************************************************************************/ 3653 int 3654 bnx_blockinit(struct bnx_softc *sc) 3655 { 3656 uint32_t reg, val; 3657 int rc = 0; 3658 3659 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3660 3661 /* Load the hardware default MAC address. */ 3662 bnx_set_mac_addr(sc); 3663 3664 /* Set the Ethernet backoff seed value */ 3665 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3666 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3667 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3668 3669 sc->last_status_idx = 0; 3670 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3671 3672 /* Set up link change interrupt generation. */ 3673 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3674 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3675 3676 /* Program the physical address of the status block. */ 3677 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3678 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3679 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3680 3681 /* Program the physical address of the statistics block. */ 3682 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3683 (uint32_t)(sc->stats_block_paddr)); 3684 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3685 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3686 3687 /* Program various host coalescing parameters. */ 3688 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3689 << 16) | sc->bnx_tx_quick_cons_trip); 3690 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3691 << 16) | sc->bnx_rx_quick_cons_trip); 3692 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3693 sc->bnx_comp_prod_trip); 3694 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3695 sc->bnx_tx_ticks); 3696 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3697 sc->bnx_rx_ticks); 3698 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3699 sc->bnx_com_ticks); 3700 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3701 sc->bnx_cmd_ticks); 3702 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3703 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3704 REG_WR(sc, BNX_HC_CONFIG, 3705 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3706 BNX_HC_CONFIG_COLLECT_STATS)); 3707 3708 /* Clear the internal statistics counters. */ 3709 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3710 3711 /* Verify that bootcode is running. */ 3712 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3713 3714 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3715 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3716 __FILE__, __LINE__); reg = 0); 3717 3718 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3719 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3720 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3721 "Expected: 08%08X\n", __FILE__, __LINE__, 3722 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3723 BNX_DEV_INFO_SIGNATURE_MAGIC); 3724 rc = ENODEV; 3725 goto bnx_blockinit_exit; 3726 } 3727 3728 /* Check if any management firmware is running. */ 3729 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 3730 if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | 3731 BNX_PORT_FEATURE_IMD_ENABLED)) { 3732 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 3733 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 3734 } 3735 3736 sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + 3737 BNX_DEV_INFO_BC_REV); 3738 3739 DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); 3740 3741 /* Enable DMA */ 3742 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3743 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3744 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3745 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3746 } 3747 3748 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3749 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3750 3751 /* Enable link state change interrupt generation. */ 3752 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3753 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3754 BNX_MISC_ENABLE_DEFAULT_XI); 3755 } else 3756 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3757 3758 /* Enable all remaining blocks in the MAC. */ 3759 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); 3760 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3761 DELAY(20); 3762 3763 bnx_blockinit_exit: 3764 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3765 3766 return rc; 3767 } 3768 3769 static int 3770 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3771 uint16_t *chain_prod, uint32_t *prod_bseq) 3772 { 3773 bus_dmamap_t map; 3774 struct rx_bd *rxbd; 3775 uint32_t addr; 3776 int i; 3777 #ifdef BNX_DEBUG 3778 uint16_t debug_chain_prod = *chain_prod; 3779 #endif 3780 uint16_t first_chain_prod; 3781 3782 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3783 3784 /* Map the mbuf cluster into device memory. */ 3785 map = sc->rx_mbuf_map[*chain_prod]; 3786 first_chain_prod = *chain_prod; 3787 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3788 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3789 __FILE__, __LINE__); 3790 3791 m_freem(m_new); 3792 3793 DBRUNIF(1, sc->rx_mbuf_alloc--); 3794 3795 return ENOBUFS; 3796 } 3797 /* Make sure there is room in the receive chain. */ 3798 if (map->dm_nsegs > sc->free_rx_bd) { 3799 bus_dmamap_unload(sc->bnx_dmatag, map); 3800 m_freem(m_new); 3801 return EFBIG; 3802 } 3803 #ifdef BNX_DEBUG 3804 /* Track the distribution of buffer segments. */ 3805 sc->rx_mbuf_segs[map->dm_nsegs]++; 3806 #endif 3807 3808 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3809 BUS_DMASYNC_PREREAD); 3810 3811 /* Update some debug statistics counters */ 3812 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3813 sc->rx_low_watermark = sc->free_rx_bd); 3814 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3815 3816 /* 3817 * Setup the rx_bd for the first segment 3818 */ 3819 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3820 3821 addr = (uint32_t)map->dm_segs[0].ds_addr; 3822 rxbd->rx_bd_haddr_lo = addr; 3823 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3824 rxbd->rx_bd_haddr_hi = addr; 3825 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3826 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3827 *prod_bseq += map->dm_segs[0].ds_len; 3828 bus_dmamap_sync(sc->bnx_dmatag, 3829 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3830 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3831 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3832 3833 for (i = 1; i < map->dm_nsegs; i++) { 3834 *prod = NEXT_RX_BD(*prod); 3835 *chain_prod = RX_CHAIN_IDX(*prod); 3836 3837 rxbd = 3838 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3839 3840 addr = (uint32_t)map->dm_segs[i].ds_addr; 3841 rxbd->rx_bd_haddr_lo = addr; 3842 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3843 rxbd->rx_bd_haddr_hi = addr; 3844 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3845 rxbd->rx_bd_flags = 0; 3846 *prod_bseq += map->dm_segs[i].ds_len; 3847 bus_dmamap_sync(sc->bnx_dmatag, 3848 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3849 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3850 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3851 } 3852 3853 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3854 bus_dmamap_sync(sc->bnx_dmatag, 3855 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3856 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3857 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3858 3859 /* 3860 * Save the mbuf, adjust the map pointer (swap map for first and 3861 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3862 * and update our counter. 3863 */ 3864 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3865 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3866 sc->rx_mbuf_map[*chain_prod] = map; 3867 sc->free_rx_bd -= map->dm_nsegs; 3868 3869 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3870 map->dm_nsegs)); 3871 *prod = NEXT_RX_BD(*prod); 3872 *chain_prod = RX_CHAIN_IDX(*prod); 3873 3874 return 0; 3875 } 3876 3877 /****************************************************************************/ 3878 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3879 /* */ 3880 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3881 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3882 /* necessary. */ 3883 /* */ 3884 /* Returns: */ 3885 /* 0 for success, positive value for failure. */ 3886 /****************************************************************************/ 3887 int 3888 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3889 uint16_t *chain_prod, uint32_t *prod_bseq) 3890 { 3891 struct mbuf *m_new = NULL; 3892 int rc = 0; 3893 uint16_t min_free_bd; 3894 3895 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3896 __func__); 3897 3898 /* Make sure the inputs are valid. */ 3899 DBRUNIF((*chain_prod > MAX_RX_BD), 3900 aprint_error_dev(sc->bnx_dev, 3901 "RX producer out of range: 0x%04X > 0x%04X\n", 3902 *chain_prod, (uint16_t)MAX_RX_BD)); 3903 3904 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3905 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3906 *prod_bseq); 3907 3908 /* try to get in as many mbufs as possible */ 3909 if (sc->mbuf_alloc_size == MCLBYTES) 3910 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3911 else 3912 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3913 while (sc->free_rx_bd >= min_free_bd) { 3914 /* Simulate an mbuf allocation failure. */ 3915 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3916 aprint_error_dev(sc->bnx_dev, 3917 "Simulating mbuf allocation failure.\n"); 3918 sc->mbuf_sim_alloc_failed++; 3919 rc = ENOBUFS; 3920 goto bnx_get_buf_exit); 3921 3922 /* This is a new mbuf allocation. */ 3923 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3924 if (m_new == NULL) { 3925 DBPRINT(sc, BNX_WARN, 3926 "%s(%d): RX mbuf header allocation failed!\n", 3927 __FILE__, __LINE__); 3928 3929 sc->mbuf_alloc_failed++; 3930 3931 rc = ENOBUFS; 3932 goto bnx_get_buf_exit; 3933 } 3934 3935 DBRUNIF(1, sc->rx_mbuf_alloc++); 3936 3937 /* Simulate an mbuf cluster allocation failure. */ 3938 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3939 m_freem(m_new); 3940 sc->rx_mbuf_alloc--; 3941 sc->mbuf_alloc_failed++; 3942 sc->mbuf_sim_alloc_failed++; 3943 rc = ENOBUFS; 3944 goto bnx_get_buf_exit); 3945 3946 if (sc->mbuf_alloc_size == MCLBYTES) 3947 MCLGET(m_new, M_DONTWAIT); 3948 else 3949 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 3950 M_DONTWAIT); 3951 if (!(m_new->m_flags & M_EXT)) { 3952 DBPRINT(sc, BNX_WARN, 3953 "%s(%d): RX mbuf chain allocation failed!\n", 3954 __FILE__, __LINE__); 3955 3956 m_freem(m_new); 3957 3958 DBRUNIF(1, sc->rx_mbuf_alloc--); 3959 sc->mbuf_alloc_failed++; 3960 3961 rc = ENOBUFS; 3962 goto bnx_get_buf_exit; 3963 } 3964 3965 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 3966 if (rc != 0) 3967 goto bnx_get_buf_exit; 3968 } 3969 3970 bnx_get_buf_exit: 3971 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 3972 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 3973 *chain_prod, *prod_bseq); 3974 3975 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 3976 __func__); 3977 3978 return rc; 3979 } 3980 3981 void 3982 bnx_alloc_pkts(struct work * unused, void * arg) 3983 { 3984 struct bnx_softc *sc = arg; 3985 struct ifnet *ifp = &sc->bnx_ec.ec_if; 3986 struct bnx_pkt *pkt; 3987 int i, s; 3988 3989 for (i = 0; i < 4; i++) { /* magic! */ 3990 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 3991 if (pkt == NULL) 3992 break; 3993 3994 if (bus_dmamap_create(sc->bnx_dmatag, 3995 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 3996 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3997 &pkt->pkt_dmamap) != 0) 3998 goto put; 3999 4000 if (!ISSET(ifp->if_flags, IFF_UP)) 4001 goto stopping; 4002 4003 mutex_enter(&sc->tx_pkt_mtx); 4004 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4005 sc->tx_pkt_count++; 4006 mutex_exit(&sc->tx_pkt_mtx); 4007 } 4008 4009 mutex_enter(&sc->tx_pkt_mtx); 4010 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4011 mutex_exit(&sc->tx_pkt_mtx); 4012 4013 /* fire-up TX now that allocations have been done */ 4014 s = splnet(); 4015 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4016 bnx_start(ifp); 4017 splx(s); 4018 4019 return; 4020 4021 stopping: 4022 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4023 put: 4024 pool_put(bnx_tx_pool, pkt); 4025 return; 4026 } 4027 4028 /****************************************************************************/ 4029 /* Initialize the TX context memory. */ 4030 /* */ 4031 /* Returns: */ 4032 /* Nothing */ 4033 /****************************************************************************/ 4034 void 4035 bnx_init_tx_context(struct bnx_softc *sc) 4036 { 4037 uint32_t val; 4038 4039 /* Initialize the context ID for an L2 TX chain. */ 4040 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4041 /* Set the CID type to support an L2 connection. */ 4042 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4043 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4044 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4045 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4046 4047 /* Point the hardware to the first page in the chain. */ 4048 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4049 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4050 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4051 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4052 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4053 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4054 } else { 4055 /* Set the CID type to support an L2 connection. */ 4056 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4057 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4058 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4059 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4060 4061 /* Point the hardware to the first page in the chain. */ 4062 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4063 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4064 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4065 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4066 } 4067 } 4068 4069 4070 /****************************************************************************/ 4071 /* Allocate memory and initialize the TX data structures. */ 4072 /* */ 4073 /* Returns: */ 4074 /* 0 for success, positive value for failure. */ 4075 /****************************************************************************/ 4076 int 4077 bnx_init_tx_chain(struct bnx_softc *sc) 4078 { 4079 struct tx_bd *txbd; 4080 uint32_t addr; 4081 int i, rc = 0; 4082 4083 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4084 4085 /* Force an allocation of some dmamaps for tx up front */ 4086 bnx_alloc_pkts(NULL, sc); 4087 4088 /* Set the initial TX producer/consumer indices. */ 4089 sc->tx_prod = 0; 4090 sc->tx_cons = 0; 4091 sc->tx_prod_bseq = 0; 4092 sc->used_tx_bd = 0; 4093 sc->max_tx_bd = USABLE_TX_BD; 4094 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4095 DBRUNIF(1, sc->tx_full_count = 0); 4096 4097 /* 4098 * The NetXtreme II supports a linked-list structure called 4099 * a Buffer Descriptor Chain (or BD chain). A BD chain 4100 * consists of a series of 1 or more chain pages, each of which 4101 * consists of a fixed number of BD entries. 4102 * The last BD entry on each page is a pointer to the next page 4103 * in the chain, and the last pointer in the BD chain 4104 * points back to the beginning of the chain. 4105 */ 4106 4107 /* Set the TX next pointer chain entries. */ 4108 for (i = 0; i < TX_PAGES; i++) { 4109 int j; 4110 4111 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4112 4113 /* Check if we've reached the last page. */ 4114 if (i == (TX_PAGES - 1)) 4115 j = 0; 4116 else 4117 j = i + 1; 4118 4119 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4120 txbd->tx_bd_haddr_lo = addr; 4121 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4122 txbd->tx_bd_haddr_hi = addr; 4123 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4124 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4125 } 4126 4127 /* 4128 * Initialize the context ID for an L2 TX chain. 4129 */ 4130 bnx_init_tx_context(sc); 4131 4132 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4133 4134 return rc; 4135 } 4136 4137 /****************************************************************************/ 4138 /* Free memory and clear the TX data structures. */ 4139 /* */ 4140 /* Returns: */ 4141 /* Nothing. */ 4142 /****************************************************************************/ 4143 void 4144 bnx_free_tx_chain(struct bnx_softc *sc) 4145 { 4146 struct bnx_pkt *pkt; 4147 int i; 4148 4149 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4150 4151 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4152 mutex_enter(&sc->tx_pkt_mtx); 4153 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4154 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4155 mutex_exit(&sc->tx_pkt_mtx); 4156 4157 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4158 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4159 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4160 4161 m_freem(pkt->pkt_mbuf); 4162 DBRUNIF(1, sc->tx_mbuf_alloc--); 4163 4164 mutex_enter(&sc->tx_pkt_mtx); 4165 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4166 } 4167 4168 /* Destroy all the dmamaps we allocated for TX */ 4169 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4170 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4171 sc->tx_pkt_count--; 4172 mutex_exit(&sc->tx_pkt_mtx); 4173 4174 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4175 pool_put(bnx_tx_pool, pkt); 4176 4177 mutex_enter(&sc->tx_pkt_mtx); 4178 } 4179 mutex_exit(&sc->tx_pkt_mtx); 4180 4181 4182 4183 /* Clear each TX chain page. */ 4184 for (i = 0; i < TX_PAGES; i++) { 4185 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4186 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4187 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4188 } 4189 4190 sc->used_tx_bd = 0; 4191 4192 /* Check if we lost any mbufs in the process. */ 4193 DBRUNIF((sc->tx_mbuf_alloc), 4194 aprint_error_dev(sc->bnx_dev, 4195 "Memory leak! Lost %d mbufs from tx chain!\n", 4196 sc->tx_mbuf_alloc)); 4197 4198 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4199 } 4200 4201 /****************************************************************************/ 4202 /* Initialize the RX context memory. */ 4203 /* */ 4204 /* Returns: */ 4205 /* Nothing */ 4206 /****************************************************************************/ 4207 void 4208 bnx_init_rx_context(struct bnx_softc *sc) 4209 { 4210 uint32_t val; 4211 4212 /* Initialize the context ID for an L2 RX chain. */ 4213 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4214 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4215 4216 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4217 val |= 0x000000ff; 4218 4219 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4220 4221 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4222 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4223 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4224 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4225 } 4226 4227 /* Point the hardware to the first page in the chain. */ 4228 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4229 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4230 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4231 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4232 } 4233 4234 /****************************************************************************/ 4235 /* Allocate memory and initialize the RX data structures. */ 4236 /* */ 4237 /* Returns: */ 4238 /* 0 for success, positive value for failure. */ 4239 /****************************************************************************/ 4240 int 4241 bnx_init_rx_chain(struct bnx_softc *sc) 4242 { 4243 struct rx_bd *rxbd; 4244 int i, rc = 0; 4245 uint16_t prod, chain_prod; 4246 uint32_t prod_bseq, addr; 4247 4248 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4249 4250 /* Initialize the RX producer and consumer indices. */ 4251 sc->rx_prod = 0; 4252 sc->rx_cons = 0; 4253 sc->rx_prod_bseq = 0; 4254 sc->free_rx_bd = USABLE_RX_BD; 4255 sc->max_rx_bd = USABLE_RX_BD; 4256 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4257 DBRUNIF(1, sc->rx_empty_count = 0); 4258 4259 /* Initialize the RX next pointer chain entries. */ 4260 for (i = 0; i < RX_PAGES; i++) { 4261 int j; 4262 4263 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4264 4265 /* Check if we've reached the last page. */ 4266 if (i == (RX_PAGES - 1)) 4267 j = 0; 4268 else 4269 j = i + 1; 4270 4271 /* Setup the chain page pointers. */ 4272 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4273 rxbd->rx_bd_haddr_hi = addr; 4274 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4275 rxbd->rx_bd_haddr_lo = addr; 4276 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4277 0, BNX_RX_CHAIN_PAGE_SZ, 4278 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4279 } 4280 4281 /* Allocate mbuf clusters for the rx_bd chain. */ 4282 prod = prod_bseq = 0; 4283 chain_prod = RX_CHAIN_IDX(prod); 4284 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4285 BNX_PRINTF(sc, 4286 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4287 } 4288 4289 /* Save the RX chain producer index. */ 4290 sc->rx_prod = prod; 4291 sc->rx_prod_bseq = prod_bseq; 4292 4293 for (i = 0; i < RX_PAGES; i++) 4294 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4295 sc->rx_bd_chain_map[i]->dm_mapsize, 4296 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4297 4298 /* Tell the chip about the waiting rx_bd's. */ 4299 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4300 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4301 4302 bnx_init_rx_context(sc); 4303 4304 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4305 4306 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4307 4308 return rc; 4309 } 4310 4311 /****************************************************************************/ 4312 /* Free memory and clear the RX data structures. */ 4313 /* */ 4314 /* Returns: */ 4315 /* Nothing. */ 4316 /****************************************************************************/ 4317 void 4318 bnx_free_rx_chain(struct bnx_softc *sc) 4319 { 4320 int i; 4321 4322 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4323 4324 /* Free any mbufs still in the RX mbuf chain. */ 4325 for (i = 0; i < TOTAL_RX_BD; i++) { 4326 if (sc->rx_mbuf_ptr[i] != NULL) { 4327 if (sc->rx_mbuf_map[i] != NULL) { 4328 bus_dmamap_sync(sc->bnx_dmatag, 4329 sc->rx_mbuf_map[i], 0, 4330 sc->rx_mbuf_map[i]->dm_mapsize, 4331 BUS_DMASYNC_POSTREAD); 4332 bus_dmamap_unload(sc->bnx_dmatag, 4333 sc->rx_mbuf_map[i]); 4334 } 4335 m_freem(sc->rx_mbuf_ptr[i]); 4336 sc->rx_mbuf_ptr[i] = NULL; 4337 DBRUNIF(1, sc->rx_mbuf_alloc--); 4338 } 4339 } 4340 4341 /* Clear each RX chain page. */ 4342 for (i = 0; i < RX_PAGES; i++) 4343 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4344 4345 sc->free_rx_bd = sc->max_rx_bd; 4346 4347 /* Check if we lost any mbufs in the process. */ 4348 DBRUNIF((sc->rx_mbuf_alloc), 4349 aprint_error_dev(sc->bnx_dev, 4350 "Memory leak! Lost %d mbufs from rx chain!\n", 4351 sc->rx_mbuf_alloc)); 4352 4353 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4354 } 4355 4356 /****************************************************************************/ 4357 /* Set media options. */ 4358 /* */ 4359 /* Returns: */ 4360 /* 0 for success, positive value for failure. */ 4361 /****************************************************************************/ 4362 int 4363 bnx_ifmedia_upd(struct ifnet *ifp) 4364 { 4365 struct bnx_softc *sc; 4366 struct mii_data *mii; 4367 int rc = 0; 4368 4369 sc = ifp->if_softc; 4370 4371 mii = &sc->bnx_mii; 4372 sc->bnx_link = 0; 4373 if (mii->mii_instance) { 4374 struct mii_softc *miisc; 4375 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4376 mii_phy_reset(miisc); 4377 } 4378 mii_mediachg(mii); 4379 4380 return rc; 4381 } 4382 4383 /****************************************************************************/ 4384 /* Reports current media status. */ 4385 /* */ 4386 /* Returns: */ 4387 /* Nothing. */ 4388 /****************************************************************************/ 4389 void 4390 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4391 { 4392 struct bnx_softc *sc; 4393 struct mii_data *mii; 4394 int s; 4395 4396 sc = ifp->if_softc; 4397 4398 s = splnet(); 4399 4400 mii = &sc->bnx_mii; 4401 4402 mii_pollstat(mii); 4403 ifmr->ifm_status = mii->mii_media_status; 4404 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4405 sc->bnx_flowflags; 4406 4407 splx(s); 4408 } 4409 4410 /****************************************************************************/ 4411 /* Handles PHY generated interrupt events. */ 4412 /* */ 4413 /* Returns: */ 4414 /* Nothing. */ 4415 /****************************************************************************/ 4416 void 4417 bnx_phy_intr(struct bnx_softc *sc) 4418 { 4419 uint32_t new_link_state, old_link_state; 4420 4421 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4422 BUS_DMASYNC_POSTREAD); 4423 new_link_state = sc->status_block->status_attn_bits & 4424 STATUS_ATTN_BITS_LINK_STATE; 4425 old_link_state = sc->status_block->status_attn_bits_ack & 4426 STATUS_ATTN_BITS_LINK_STATE; 4427 4428 /* Handle any changes if the link state has changed. */ 4429 if (new_link_state != old_link_state) { 4430 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4431 4432 sc->bnx_link = 0; 4433 callout_stop(&sc->bnx_timeout); 4434 bnx_tick(sc); 4435 4436 /* Update the status_attn_bits_ack field in the status block. */ 4437 if (new_link_state) { 4438 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4439 STATUS_ATTN_BITS_LINK_STATE); 4440 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4441 } else { 4442 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4443 STATUS_ATTN_BITS_LINK_STATE); 4444 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4445 } 4446 } 4447 4448 /* Acknowledge the link change interrupt. */ 4449 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4450 } 4451 4452 /****************************************************************************/ 4453 /* Handles received frame interrupt events. */ 4454 /* */ 4455 /* Returns: */ 4456 /* Nothing. */ 4457 /****************************************************************************/ 4458 void 4459 bnx_rx_intr(struct bnx_softc *sc) 4460 { 4461 struct status_block *sblk = sc->status_block; 4462 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4463 uint16_t hw_cons, sw_cons, sw_chain_cons; 4464 uint16_t sw_prod, sw_chain_prod; 4465 uint32_t sw_prod_bseq; 4466 struct l2_fhdr *l2fhdr; 4467 int i; 4468 4469 DBRUNIF(1, sc->rx_interrupts++); 4470 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4471 BUS_DMASYNC_POSTREAD); 4472 4473 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4474 for (i = 0; i < RX_PAGES; i++) 4475 bus_dmamap_sync(sc->bnx_dmatag, 4476 sc->rx_bd_chain_map[i], 0, 4477 sc->rx_bd_chain_map[i]->dm_mapsize, 4478 BUS_DMASYNC_POSTWRITE); 4479 4480 /* Get the hardware's view of the RX consumer index. */ 4481 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4482 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4483 hw_cons++; 4484 4485 /* Get working copies of the driver's view of the RX indices. */ 4486 sw_cons = sc->rx_cons; 4487 sw_prod = sc->rx_prod; 4488 sw_prod_bseq = sc->rx_prod_bseq; 4489 4490 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4491 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4492 __func__, sw_prod, sw_cons, sw_prod_bseq); 4493 4494 /* Prevent speculative reads from getting ahead of the status block. */ 4495 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4496 BUS_SPACE_BARRIER_READ); 4497 4498 /* Update some debug statistics counters */ 4499 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4500 sc->rx_low_watermark = sc->free_rx_bd); 4501 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4502 4503 /* 4504 * Scan through the receive chain as long 4505 * as there is work to do. 4506 */ 4507 while (sw_cons != hw_cons) { 4508 struct mbuf *m; 4509 struct rx_bd *rxbd __diagused; 4510 unsigned int len; 4511 uint32_t status; 4512 4513 /* Convert the producer/consumer indices to an actual 4514 * rx_bd index. 4515 */ 4516 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4517 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4518 4519 /* Get the used rx_bd. */ 4520 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4521 sc->free_rx_bd++; 4522 4523 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4524 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4525 4526 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4527 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4528 #ifdef DIAGNOSTIC 4529 /* Validate that this is the last rx_bd. */ 4530 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4531 printf("%s: Unexpected mbuf found in " 4532 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4533 sw_chain_cons); 4534 } 4535 #endif 4536 4537 /* DRC - ToDo: If the received packet is small, say 4538 * less than 128 bytes, allocate a new mbuf 4539 * here, copy the data to that mbuf, and 4540 * recycle the mapped jumbo frame. 4541 */ 4542 4543 /* Unmap the mbuf from DMA space. */ 4544 #ifdef DIAGNOSTIC 4545 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4546 printf("invalid map sw_cons 0x%x " 4547 "sw_prod 0x%x " 4548 "sw_chain_cons 0x%x " 4549 "sw_chain_prod 0x%x " 4550 "hw_cons 0x%x " 4551 "TOTAL_RX_BD_PER_PAGE 0x%x " 4552 "TOTAL_RX_BD 0x%x\n", 4553 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4554 hw_cons, 4555 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4556 } 4557 #endif 4558 bus_dmamap_sync(sc->bnx_dmatag, 4559 sc->rx_mbuf_map[sw_chain_cons], 0, 4560 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4561 BUS_DMASYNC_POSTREAD); 4562 bus_dmamap_unload(sc->bnx_dmatag, 4563 sc->rx_mbuf_map[sw_chain_cons]); 4564 4565 /* Remove the mbuf from the driver's chain. */ 4566 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4567 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4568 4569 /* 4570 * Frames received on the NetXteme II are prepended 4571 * with the l2_fhdr structure which provides status 4572 * information about the received frame (including 4573 * VLAN tags and checksum info) and are also 4574 * automatically adjusted to align the IP header 4575 * (i.e. two null bytes are inserted before the 4576 * Ethernet header). 4577 */ 4578 l2fhdr = mtod(m, struct l2_fhdr *); 4579 4580 len = l2fhdr->l2_fhdr_pkt_len; 4581 status = l2fhdr->l2_fhdr_status; 4582 4583 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4584 aprint_error("Simulating l2_fhdr status error.\n"); 4585 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4586 4587 /* Watch for unusual sized frames. */ 4588 DBRUNIF(((len < BNX_MIN_MTU) || 4589 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4590 aprint_error_dev(sc->bnx_dev, 4591 "Unusual frame size found. " 4592 "Min(%d), Actual(%d), Max(%d)\n", 4593 (int)BNX_MIN_MTU, len, 4594 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4595 4596 bnx_dump_mbuf(sc, m); 4597 bnx_breakpoint(sc)); 4598 4599 len -= ETHER_CRC_LEN; 4600 4601 /* Check the received frame for errors. */ 4602 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4603 L2_FHDR_ERRORS_PHY_DECODE | 4604 L2_FHDR_ERRORS_ALIGNMENT | 4605 L2_FHDR_ERRORS_TOO_SHORT | 4606 L2_FHDR_ERRORS_GIANT_FRAME)) || 4607 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4608 len > 4609 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4610 ifp->if_ierrors++; 4611 DBRUNIF(1, sc->l2fhdr_status_errors++); 4612 4613 /* Reuse the mbuf for a new frame. */ 4614 if (bnx_add_buf(sc, m, &sw_prod, 4615 &sw_chain_prod, &sw_prod_bseq)) { 4616 DBRUNIF(1, bnx_breakpoint(sc)); 4617 panic("%s: Can't reuse RX mbuf!\n", 4618 device_xname(sc->bnx_dev)); 4619 } 4620 continue; 4621 } 4622 4623 /* 4624 * Get a new mbuf for the rx_bd. If no new 4625 * mbufs are available then reuse the current mbuf, 4626 * log an ierror on the interface, and generate 4627 * an error in the system log. 4628 */ 4629 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4630 &sw_prod_bseq)) { 4631 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4632 "Failed to allocate " 4633 "new mbuf, incoming frame dropped!\n")); 4634 4635 ifp->if_ierrors++; 4636 4637 /* Try and reuse the exisitng mbuf. */ 4638 if (bnx_add_buf(sc, m, &sw_prod, 4639 &sw_chain_prod, &sw_prod_bseq)) { 4640 DBRUNIF(1, bnx_breakpoint(sc)); 4641 panic("%s: Double mbuf allocation " 4642 "failure!", 4643 device_xname(sc->bnx_dev)); 4644 } 4645 continue; 4646 } 4647 4648 /* Skip over the l2_fhdr when passing the data up 4649 * the stack. 4650 */ 4651 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4652 4653 /* Adjust the pckt length to match the received data. */ 4654 m->m_pkthdr.len = m->m_len = len; 4655 4656 /* Send the packet to the appropriate interface. */ 4657 m_set_rcvif(m, ifp); 4658 4659 DBRUN(BNX_VERBOSE_RECV, 4660 struct ether_header *eh; 4661 eh = mtod(m, struct ether_header *); 4662 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4663 __func__, ether_sprintf(eh->ether_dhost), 4664 ether_sprintf(eh->ether_shost), 4665 htons(eh->ether_type))); 4666 4667 /* Validate the checksum. */ 4668 4669 /* Check for an IP datagram. */ 4670 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4671 /* Check if the IP checksum is valid. */ 4672 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4673 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4674 #ifdef BNX_DEBUG 4675 else 4676 DBPRINT(sc, BNX_WARN_SEND, 4677 "%s(): Invalid IP checksum " 4678 "= 0x%04X!\n", 4679 __func__, 4680 l2fhdr->l2_fhdr_ip_xsum 4681 ); 4682 #endif 4683 } 4684 4685 /* Check for a valid TCP/UDP frame. */ 4686 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4687 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4688 /* Check for a good TCP/UDP checksum. */ 4689 if ((status & 4690 (L2_FHDR_ERRORS_TCP_XSUM | 4691 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4692 m->m_pkthdr.csum_flags |= 4693 M_CSUM_TCPv4 | 4694 M_CSUM_UDPv4; 4695 } else { 4696 DBPRINT(sc, BNX_WARN_SEND, 4697 "%s(): Invalid TCP/UDP " 4698 "checksum = 0x%04X!\n", 4699 __func__, 4700 l2fhdr->l2_fhdr_tcp_udp_xsum); 4701 } 4702 } 4703 4704 /* 4705 * If we received a packet with a vlan tag, 4706 * attach that information to the packet. 4707 */ 4708 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4709 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4710 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4711 } 4712 4713 /* Pass the mbuf off to the upper layers. */ 4714 4715 DBPRINT(sc, BNX_VERBOSE_RECV, 4716 "%s(): Passing received frame up.\n", __func__); 4717 if_percpuq_enqueue(ifp->if_percpuq, m); 4718 DBRUNIF(1, sc->rx_mbuf_alloc--); 4719 4720 } 4721 4722 sw_cons = NEXT_RX_BD(sw_cons); 4723 4724 /* Refresh hw_cons to see if there's new work */ 4725 if (sw_cons == hw_cons) { 4726 hw_cons = sc->hw_rx_cons = 4727 sblk->status_rx_quick_consumer_index0; 4728 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4729 USABLE_RX_BD_PER_PAGE) 4730 hw_cons++; 4731 } 4732 4733 /* Prevent speculative reads from getting ahead of 4734 * the status block. 4735 */ 4736 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4737 BUS_SPACE_BARRIER_READ); 4738 } 4739 4740 for (i = 0; i < RX_PAGES; i++) 4741 bus_dmamap_sync(sc->bnx_dmatag, 4742 sc->rx_bd_chain_map[i], 0, 4743 sc->rx_bd_chain_map[i]->dm_mapsize, 4744 BUS_DMASYNC_PREWRITE); 4745 4746 sc->rx_cons = sw_cons; 4747 sc->rx_prod = sw_prod; 4748 sc->rx_prod_bseq = sw_prod_bseq; 4749 4750 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4751 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4752 4753 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4754 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4755 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4756 } 4757 4758 /****************************************************************************/ 4759 /* Handles transmit completion interrupt events. */ 4760 /* */ 4761 /* Returns: */ 4762 /* Nothing. */ 4763 /****************************************************************************/ 4764 void 4765 bnx_tx_intr(struct bnx_softc *sc) 4766 { 4767 struct status_block *sblk = sc->status_block; 4768 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4769 struct bnx_pkt *pkt; 4770 bus_dmamap_t map; 4771 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4772 4773 DBRUNIF(1, sc->tx_interrupts++); 4774 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4775 BUS_DMASYNC_POSTREAD); 4776 4777 /* Get the hardware's view of the TX consumer index. */ 4778 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4779 4780 /* Skip to the next entry if this is a chain page pointer. */ 4781 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4782 hw_tx_cons++; 4783 4784 sw_tx_cons = sc->tx_cons; 4785 4786 /* Prevent speculative reads from getting ahead of the status block. */ 4787 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4788 BUS_SPACE_BARRIER_READ); 4789 4790 /* Cycle through any completed TX chain page entries. */ 4791 while (sw_tx_cons != hw_tx_cons) { 4792 #ifdef BNX_DEBUG 4793 struct tx_bd *txbd = NULL; 4794 #endif 4795 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4796 4797 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4798 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4799 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4800 4801 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4802 aprint_error_dev(sc->bnx_dev, 4803 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4804 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4805 4806 DBRUNIF(1, txbd = &sc->tx_bd_chain 4807 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4808 4809 DBRUNIF((txbd == NULL), 4810 aprint_error_dev(sc->bnx_dev, 4811 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4812 bnx_breakpoint(sc)); 4813 4814 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4815 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4816 4817 4818 mutex_enter(&sc->tx_pkt_mtx); 4819 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4820 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4821 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4822 mutex_exit(&sc->tx_pkt_mtx); 4823 /* 4824 * Free the associated mbuf. Remember 4825 * that only the last tx_bd of a packet 4826 * has an mbuf pointer and DMA map. 4827 */ 4828 map = pkt->pkt_dmamap; 4829 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4830 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4831 bus_dmamap_unload(sc->bnx_dmatag, map); 4832 4833 m_freem(pkt->pkt_mbuf); 4834 DBRUNIF(1, sc->tx_mbuf_alloc--); 4835 4836 ifp->if_opackets++; 4837 4838 mutex_enter(&sc->tx_pkt_mtx); 4839 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4840 } 4841 mutex_exit(&sc->tx_pkt_mtx); 4842 4843 sc->used_tx_bd--; 4844 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4845 __FILE__, __LINE__, sc->used_tx_bd); 4846 4847 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4848 4849 /* Refresh hw_cons to see if there's new work. */ 4850 hw_tx_cons = sc->hw_tx_cons = 4851 sblk->status_tx_quick_consumer_index0; 4852 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4853 USABLE_TX_BD_PER_PAGE) 4854 hw_tx_cons++; 4855 4856 /* Prevent speculative reads from getting ahead of 4857 * the status block. 4858 */ 4859 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4860 BUS_SPACE_BARRIER_READ); 4861 } 4862 4863 /* Clear the TX timeout timer. */ 4864 ifp->if_timer = 0; 4865 4866 /* Clear the tx hardware queue full flag. */ 4867 if (sc->used_tx_bd < sc->max_tx_bd) { 4868 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4869 aprint_debug_dev(sc->bnx_dev, 4870 "Open TX chain! %d/%d (used/total)\n", 4871 sc->used_tx_bd, sc->max_tx_bd)); 4872 ifp->if_flags &= ~IFF_OACTIVE; 4873 } 4874 4875 sc->tx_cons = sw_tx_cons; 4876 } 4877 4878 /****************************************************************************/ 4879 /* Disables interrupt generation. */ 4880 /* */ 4881 /* Returns: */ 4882 /* Nothing. */ 4883 /****************************************************************************/ 4884 void 4885 bnx_disable_intr(struct bnx_softc *sc) 4886 { 4887 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4888 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4889 } 4890 4891 /****************************************************************************/ 4892 /* Enables interrupt generation. */ 4893 /* */ 4894 /* Returns: */ 4895 /* Nothing. */ 4896 /****************************************************************************/ 4897 void 4898 bnx_enable_intr(struct bnx_softc *sc) 4899 { 4900 uint32_t val; 4901 4902 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4903 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4904 4905 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4906 sc->last_status_idx); 4907 4908 val = REG_RD(sc, BNX_HC_COMMAND); 4909 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4910 } 4911 4912 /****************************************************************************/ 4913 /* Handles controller initialization. */ 4914 /* */ 4915 /****************************************************************************/ 4916 int 4917 bnx_init(struct ifnet *ifp) 4918 { 4919 struct bnx_softc *sc = ifp->if_softc; 4920 uint32_t ether_mtu; 4921 int s, error = 0; 4922 4923 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4924 4925 s = splnet(); 4926 4927 bnx_stop(ifp, 0); 4928 4929 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 4930 aprint_error_dev(sc->bnx_dev, 4931 "Controller reset failed!\n"); 4932 goto bnx_init_exit; 4933 } 4934 4935 if ((error = bnx_chipinit(sc)) != 0) { 4936 aprint_error_dev(sc->bnx_dev, 4937 "Controller initialization failed!\n"); 4938 goto bnx_init_exit; 4939 } 4940 4941 if ((error = bnx_blockinit(sc)) != 0) { 4942 aprint_error_dev(sc->bnx_dev, 4943 "Block initialization failed!\n"); 4944 goto bnx_init_exit; 4945 } 4946 4947 /* Calculate and program the Ethernet MRU size. */ 4948 if (ifp->if_mtu <= ETHERMTU) { 4949 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 4950 sc->mbuf_alloc_size = MCLBYTES; 4951 } else { 4952 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 4953 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 4954 } 4955 4956 4957 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 4958 4959 /* 4960 * Program the MRU and enable Jumbo frame 4961 * support. 4962 */ 4963 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 4964 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4965 4966 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4967 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4968 4969 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4970 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 4971 sc->mbuf_alloc_size, sc->max_frame_size); 4972 4973 /* Program appropriate promiscuous/multicast filtering. */ 4974 bnx_iff(sc); 4975 4976 /* Init RX buffer descriptor chain. */ 4977 bnx_init_rx_chain(sc); 4978 4979 /* Init TX buffer descriptor chain. */ 4980 bnx_init_tx_chain(sc); 4981 4982 /* Enable host interrupts. */ 4983 bnx_enable_intr(sc); 4984 4985 bnx_ifmedia_upd(ifp); 4986 4987 SET(ifp->if_flags, IFF_RUNNING); 4988 CLR(ifp->if_flags, IFF_OACTIVE); 4989 4990 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 4991 4992 bnx_init_exit: 4993 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4994 4995 splx(s); 4996 4997 return error; 4998 } 4999 5000 void 5001 bnx_mgmt_init(struct bnx_softc *sc) 5002 { 5003 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5004 uint32_t val; 5005 5006 /* Check if the driver is still running and bail out if it is. */ 5007 if (ifp->if_flags & IFF_RUNNING) 5008 goto bnx_mgmt_init_exit; 5009 5010 /* Initialize the on-boards CPUs */ 5011 bnx_init_cpus(sc); 5012 5013 val = (BCM_PAGE_BITS - 8) << 24; 5014 REG_WR(sc, BNX_RV2P_CONFIG, val); 5015 5016 /* Enable all critical blocks in the MAC. */ 5017 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5018 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5019 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5020 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5021 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5022 DELAY(20); 5023 5024 bnx_ifmedia_upd(ifp); 5025 5026 bnx_mgmt_init_exit: 5027 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5028 } 5029 5030 /****************************************************************************/ 5031 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5032 /* memory visible to the controller. */ 5033 /* */ 5034 /* Returns: */ 5035 /* 0 for success, positive value for failure. */ 5036 /****************************************************************************/ 5037 int 5038 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5039 { 5040 struct bnx_pkt *pkt; 5041 bus_dmamap_t map; 5042 struct tx_bd *txbd = NULL; 5043 uint16_t vlan_tag = 0, flags = 0; 5044 uint16_t chain_prod, prod; 5045 #ifdef BNX_DEBUG 5046 uint16_t debug_prod; 5047 #endif 5048 uint32_t addr, prod_bseq; 5049 int i, error; 5050 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 5051 bool remap = true; 5052 5053 mutex_enter(&sc->tx_pkt_mtx); 5054 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5055 if (pkt == NULL) { 5056 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5057 mutex_exit(&sc->tx_pkt_mtx); 5058 return ENETDOWN; 5059 } 5060 5061 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5062 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5063 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 5064 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5065 } 5066 5067 mutex_exit(&sc->tx_pkt_mtx); 5068 return ENOMEM; 5069 } 5070 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5071 mutex_exit(&sc->tx_pkt_mtx); 5072 5073 /* Transfer any checksum offload flags to the bd. */ 5074 if (m->m_pkthdr.csum_flags) { 5075 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5076 flags |= TX_BD_FLAGS_IP_CKSUM; 5077 if (m->m_pkthdr.csum_flags & 5078 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5079 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5080 } 5081 5082 /* Transfer any VLAN tags to the bd. */ 5083 if (vlan_has_tag(m)) { 5084 flags |= TX_BD_FLAGS_VLAN_TAG; 5085 vlan_tag = vlan_get_tag(m); 5086 } 5087 5088 /* Map the mbuf into DMAable memory. */ 5089 prod = sc->tx_prod; 5090 chain_prod = TX_CHAIN_IDX(prod); 5091 map = pkt->pkt_dmamap; 5092 5093 /* Map the mbuf into our DMA address space. */ 5094 retry: 5095 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5096 if (__predict_false(error)) { 5097 if (error == EFBIG) { 5098 if (remap == true) { 5099 struct mbuf *newm; 5100 5101 remap = false; 5102 newm = m_defrag(m, M_NOWAIT); 5103 if (newm != NULL) { 5104 m = newm; 5105 goto retry; 5106 } 5107 } 5108 } 5109 sc->tx_dma_map_failures++; 5110 goto maperr; 5111 } 5112 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5113 BUS_DMASYNC_PREWRITE); 5114 /* Make sure there's room in the chain */ 5115 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5116 goto nospace; 5117 5118 /* prod points to an empty tx_bd at this point. */ 5119 prod_bseq = sc->tx_prod_bseq; 5120 #ifdef BNX_DEBUG 5121 debug_prod = chain_prod; 5122 #endif 5123 DBPRINT(sc, BNX_INFO_SEND, 5124 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5125 "prod_bseq = 0x%08X\n", 5126 __func__, prod, chain_prod, prod_bseq); 5127 5128 /* 5129 * Cycle through each mbuf segment that makes up 5130 * the outgoing frame, gathering the mapping info 5131 * for that segment and creating a tx_bd for the 5132 * mbuf. 5133 */ 5134 for (i = 0; i < map->dm_nsegs ; i++) { 5135 chain_prod = TX_CHAIN_IDX(prod); 5136 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5137 5138 addr = (uint32_t)map->dm_segs[i].ds_addr; 5139 txbd->tx_bd_haddr_lo = addr; 5140 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5141 txbd->tx_bd_haddr_hi = addr; 5142 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5143 txbd->tx_bd_vlan_tag = vlan_tag; 5144 txbd->tx_bd_flags = flags; 5145 prod_bseq += map->dm_segs[i].ds_len; 5146 if (i == 0) 5147 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5148 prod = NEXT_TX_BD(prod); 5149 } 5150 5151 /* Set the END flag on the last TX buffer descriptor. */ 5152 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5153 5154 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5155 5156 DBPRINT(sc, BNX_INFO_SEND, 5157 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5158 "prod_bseq = 0x%08X\n", 5159 __func__, prod, chain_prod, prod_bseq); 5160 5161 pkt->pkt_mbuf = m; 5162 pkt->pkt_end_desc = chain_prod; 5163 5164 mutex_enter(&sc->tx_pkt_mtx); 5165 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5166 mutex_exit(&sc->tx_pkt_mtx); 5167 5168 sc->used_tx_bd += map->dm_nsegs; 5169 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5170 __FILE__, __LINE__, sc->used_tx_bd); 5171 5172 /* Update some debug statistics counters */ 5173 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5174 sc->tx_hi_watermark = sc->used_tx_bd); 5175 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5176 DBRUNIF(1, sc->tx_mbuf_alloc++); 5177 5178 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5179 map->dm_nsegs)); 5180 5181 /* prod points to the next free tx_bd at this point. */ 5182 sc->tx_prod = prod; 5183 sc->tx_prod_bseq = prod_bseq; 5184 5185 return 0; 5186 5187 5188 nospace: 5189 bus_dmamap_unload(sc->bnx_dmatag, map); 5190 maperr: 5191 mutex_enter(&sc->tx_pkt_mtx); 5192 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5193 mutex_exit(&sc->tx_pkt_mtx); 5194 5195 return ENOMEM; 5196 } 5197 5198 /****************************************************************************/ 5199 /* Main transmit routine. */ 5200 /* */ 5201 /* Returns: */ 5202 /* Nothing. */ 5203 /****************************************************************************/ 5204 void 5205 bnx_start(struct ifnet *ifp) 5206 { 5207 struct bnx_softc *sc = ifp->if_softc; 5208 struct mbuf *m_head = NULL; 5209 int count = 0; 5210 #ifdef BNX_DEBUG 5211 uint16_t tx_chain_prod; 5212 #endif 5213 5214 /* If there's no link or the transmit queue is empty then just exit. */ 5215 if (!sc->bnx_link 5216 ||(ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5217 DBPRINT(sc, BNX_INFO_SEND, 5218 "%s(): output active or device not running.\n", __func__); 5219 goto bnx_start_exit; 5220 } 5221 5222 /* prod points to the next free tx_bd. */ 5223 #ifdef BNX_DEBUG 5224 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5225 #endif 5226 5227 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5228 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5229 "used_tx %d max_tx %d\n", 5230 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5231 sc->used_tx_bd, sc->max_tx_bd); 5232 5233 /* 5234 * Keep adding entries while there is space in the ring. 5235 */ 5236 while (sc->used_tx_bd < sc->max_tx_bd) { 5237 /* Check for any frames to send. */ 5238 IFQ_POLL(&ifp->if_snd, m_head); 5239 if (m_head == NULL) 5240 break; 5241 5242 /* 5243 * Pack the data into the transmit ring. If we 5244 * don't have room, set the OACTIVE flag to wait 5245 * for the NIC to drain the chain. 5246 */ 5247 if (bnx_tx_encap(sc, m_head)) { 5248 ifp->if_flags |= IFF_OACTIVE; 5249 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5250 "business! Total tx_bd used = %d\n", 5251 sc->used_tx_bd); 5252 break; 5253 } 5254 5255 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5256 count++; 5257 5258 /* Send a copy of the frame to any BPF listeners. */ 5259 bpf_mtap(ifp, m_head, BPF_D_OUT); 5260 } 5261 5262 if (count == 0) { 5263 /* no packets were dequeued */ 5264 DBPRINT(sc, BNX_VERBOSE_SEND, 5265 "%s(): No packets were dequeued\n", __func__); 5266 goto bnx_start_exit; 5267 } 5268 5269 /* Update the driver's counters. */ 5270 #ifdef BNX_DEBUG 5271 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5272 #endif 5273 5274 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5275 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5276 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5277 5278 /* Start the transmit. */ 5279 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5280 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5281 5282 /* Set the tx timeout. */ 5283 ifp->if_timer = BNX_TX_TIMEOUT; 5284 5285 bnx_start_exit: 5286 return; 5287 } 5288 5289 /****************************************************************************/ 5290 /* Handles any IOCTL calls from the operating system. */ 5291 /* */ 5292 /* Returns: */ 5293 /* 0 for success, positive value for failure. */ 5294 /****************************************************************************/ 5295 int 5296 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5297 { 5298 struct bnx_softc *sc = ifp->if_softc; 5299 struct ifreq *ifr = (struct ifreq *) data; 5300 struct mii_data *mii = &sc->bnx_mii; 5301 int s, error = 0; 5302 5303 s = splnet(); 5304 5305 switch (command) { 5306 case SIOCSIFFLAGS: 5307 if ((error = ifioctl_common(ifp, command, data)) != 0) 5308 break; 5309 /* XXX set an ifflags callback and let ether_ioctl 5310 * handle all of this. 5311 */ 5312 if (ISSET(ifp->if_flags, IFF_UP)) { 5313 if (ifp->if_flags & IFF_RUNNING) 5314 error = ENETRESET; 5315 else 5316 bnx_init(ifp); 5317 } else if (ifp->if_flags & IFF_RUNNING) 5318 bnx_stop(ifp, 1); 5319 break; 5320 5321 case SIOCSIFMEDIA: 5322 /* Flow control requires full-duplex mode. */ 5323 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5324 (ifr->ifr_media & IFM_FDX) == 0) 5325 ifr->ifr_media &= ~IFM_ETH_FMASK; 5326 5327 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5328 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5329 /* We can do both TXPAUSE and RXPAUSE. */ 5330 ifr->ifr_media |= 5331 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5332 } 5333 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5334 } 5335 /* FALLTHROUGH */ 5336 case SIOCGIFMEDIA: 5337 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5338 sc->bnx_phy_flags); 5339 5340 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5341 break; 5342 5343 default: 5344 error = ether_ioctl(ifp, command, data); 5345 } 5346 5347 if (error == ENETRESET) { 5348 if (ifp->if_flags & IFF_RUNNING) 5349 bnx_iff(sc); 5350 error = 0; 5351 } 5352 5353 splx(s); 5354 return error; 5355 } 5356 5357 /****************************************************************************/ 5358 /* Transmit timeout handler. */ 5359 /* */ 5360 /* Returns: */ 5361 /* Nothing. */ 5362 /****************************************************************************/ 5363 void 5364 bnx_watchdog(struct ifnet *ifp) 5365 { 5366 struct bnx_softc *sc = ifp->if_softc; 5367 5368 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5369 bnx_dump_status_block(sc)); 5370 /* 5371 * If we are in this routine because of pause frames, then 5372 * don't reset the hardware. 5373 */ 5374 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5375 return; 5376 5377 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5378 5379 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5380 5381 bnx_init(ifp); 5382 5383 ifp->if_oerrors++; 5384 } 5385 5386 /* 5387 * Interrupt handler. 5388 */ 5389 /****************************************************************************/ 5390 /* Main interrupt entry point. Verifies that the controller generated the */ 5391 /* interrupt and then calls a separate routine for handle the various */ 5392 /* interrupt causes (PHY, TX, RX). */ 5393 /* */ 5394 /* Returns: */ 5395 /* 0 for success, positive value for failure. */ 5396 /****************************************************************************/ 5397 int 5398 bnx_intr(void *xsc) 5399 { 5400 struct bnx_softc *sc = xsc; 5401 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5402 uint32_t status_attn_bits; 5403 uint16_t status_idx; 5404 const struct status_block *sblk; 5405 int rv = 0; 5406 5407 if (!device_is_active(sc->bnx_dev) || 5408 (ifp->if_flags & IFF_RUNNING) == 0) 5409 return 0; 5410 5411 DBRUNIF(1, sc->interrupts_generated++); 5412 5413 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5414 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5415 5416 sblk = sc->status_block; 5417 /* 5418 * If the hardware status block index 5419 * matches the last value read by the 5420 * driver and we haven't asserted our 5421 * interrupt then there's nothing to do. 5422 */ 5423 status_idx = sblk->status_idx; 5424 if ((status_idx != sc->last_status_idx) || 5425 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5426 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5427 rv = 1; 5428 5429 /* Ack the interrupt */ 5430 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5431 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5432 5433 status_attn_bits = sblk->status_attn_bits; 5434 5435 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5436 aprint_debug("Simulating unexpected status attention bit set."); 5437 status_attn_bits = status_attn_bits | 5438 STATUS_ATTN_BITS_PARITY_ERROR); 5439 5440 /* Was it a link change interrupt? */ 5441 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5442 (sblk->status_attn_bits_ack & 5443 STATUS_ATTN_BITS_LINK_STATE)) 5444 bnx_phy_intr(sc); 5445 5446 /* If any other attention is asserted then the chip is toast. */ 5447 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5448 (sblk->status_attn_bits_ack & 5449 ~STATUS_ATTN_BITS_LINK_STATE))) { 5450 DBRUN(sc->unexpected_attentions++); 5451 5452 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5453 sblk->status_attn_bits); 5454 5455 DBRUNIF((bnx_debug_unexpected_attention == 0), 5456 bnx_breakpoint(sc)); 5457 5458 bnx_init(ifp); 5459 goto out; 5460 } 5461 5462 /* Check for any completed RX frames. */ 5463 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5464 bnx_rx_intr(sc); 5465 5466 /* Check for any completed TX frames. */ 5467 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5468 bnx_tx_intr(sc); 5469 5470 /* 5471 * Save the status block index value for use during the 5472 * next interrupt. 5473 */ 5474 sc->last_status_idx = status_idx; 5475 5476 /* Start moving packets again */ 5477 if (ifp->if_flags & IFF_RUNNING) 5478 if_schedule_deferred_start(ifp); 5479 } 5480 5481 out: 5482 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5483 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5484 5485 return rv; 5486 } 5487 5488 /****************************************************************************/ 5489 /* Programs the various packet receive modes (broadcast and multicast). */ 5490 /* */ 5491 /* Returns: */ 5492 /* Nothing. */ 5493 /****************************************************************************/ 5494 void 5495 bnx_iff(struct bnx_softc *sc) 5496 { 5497 struct ethercom *ec = &sc->bnx_ec; 5498 struct ifnet *ifp = &ec->ec_if; 5499 struct ether_multi *enm; 5500 struct ether_multistep step; 5501 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5502 uint32_t rx_mode, sort_mode; 5503 int h, i; 5504 5505 /* Initialize receive mode default settings. */ 5506 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5507 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5508 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5509 ifp->if_flags &= ~IFF_ALLMULTI; 5510 5511 /* 5512 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5513 * be enbled. 5514 */ 5515 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5516 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5517 5518 /* 5519 * Check for promiscuous, all multicast, or selected 5520 * multicast address filtering. 5521 */ 5522 if (ifp->if_flags & IFF_PROMISC) { 5523 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5524 5525 ifp->if_flags |= IFF_ALLMULTI; 5526 /* Enable promiscuous mode. */ 5527 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5528 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5529 } else if (ifp->if_flags & IFF_ALLMULTI) { 5530 allmulti: 5531 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5532 5533 ifp->if_flags |= IFF_ALLMULTI; 5534 /* Enable all multicast addresses. */ 5535 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5536 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5537 0xffffffff); 5538 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5539 } else { 5540 /* Accept one or more multicast(s). */ 5541 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5542 5543 ETHER_FIRST_MULTI(step, ec, enm); 5544 while (enm != NULL) { 5545 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5546 ETHER_ADDR_LEN)) { 5547 goto allmulti; 5548 } 5549 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5550 0xFF; 5551 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5552 ETHER_NEXT_MULTI(step, enm); 5553 } 5554 5555 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5556 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5557 hashes[i]); 5558 5559 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5560 } 5561 5562 /* Only make changes if the recive mode has actually changed. */ 5563 if (rx_mode != sc->rx_mode) { 5564 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5565 rx_mode); 5566 5567 sc->rx_mode = rx_mode; 5568 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5569 } 5570 5571 /* Disable and clear the exisitng sort before enabling a new sort. */ 5572 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5573 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5574 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5575 } 5576 5577 /****************************************************************************/ 5578 /* Called periodically to updates statistics from the controllers */ 5579 /* statistics block. */ 5580 /* */ 5581 /* Returns: */ 5582 /* Nothing. */ 5583 /****************************************************************************/ 5584 void 5585 bnx_stats_update(struct bnx_softc *sc) 5586 { 5587 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5588 struct statistics_block *stats; 5589 5590 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5591 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5592 BUS_DMASYNC_POSTREAD); 5593 5594 stats = (struct statistics_block *)sc->stats_block; 5595 5596 /* 5597 * Update the interface statistics from the 5598 * hardware statistics. 5599 */ 5600 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5601 5602 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5603 (u_long)stats->stat_EtherStatsOverrsizePkts + 5604 (u_long)stats->stat_IfInMBUFDiscards + 5605 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5606 (u_long)stats->stat_Dot3StatsFCSErrors; 5607 5608 ifp->if_oerrors = (u_long) 5609 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5610 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5611 (u_long)stats->stat_Dot3StatsLateCollisions; 5612 5613 /* 5614 * Certain controllers don't report 5615 * carrier sense errors correctly. 5616 * See errata E11_5708CA0_1165. 5617 */ 5618 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5619 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5620 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5621 5622 /* 5623 * Update the sysctl statistics from the 5624 * hardware statistics. 5625 */ 5626 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5627 (uint64_t) stats->stat_IfHCInOctets_lo; 5628 5629 sc->stat_IfHCInBadOctets = 5630 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5631 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5632 5633 sc->stat_IfHCOutOctets = 5634 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5635 (uint64_t) stats->stat_IfHCOutOctets_lo; 5636 5637 sc->stat_IfHCOutBadOctets = 5638 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5639 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5640 5641 sc->stat_IfHCInUcastPkts = 5642 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5643 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5644 5645 sc->stat_IfHCInMulticastPkts = 5646 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5647 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5648 5649 sc->stat_IfHCInBroadcastPkts = 5650 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5651 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5652 5653 sc->stat_IfHCOutUcastPkts = 5654 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5655 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5656 5657 sc->stat_IfHCOutMulticastPkts = 5658 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5659 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5660 5661 sc->stat_IfHCOutBroadcastPkts = 5662 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5663 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5664 5665 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5666 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5667 5668 sc->stat_Dot3StatsCarrierSenseErrors = 5669 stats->stat_Dot3StatsCarrierSenseErrors; 5670 5671 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5672 5673 sc->stat_Dot3StatsAlignmentErrors = 5674 stats->stat_Dot3StatsAlignmentErrors; 5675 5676 sc->stat_Dot3StatsSingleCollisionFrames = 5677 stats->stat_Dot3StatsSingleCollisionFrames; 5678 5679 sc->stat_Dot3StatsMultipleCollisionFrames = 5680 stats->stat_Dot3StatsMultipleCollisionFrames; 5681 5682 sc->stat_Dot3StatsDeferredTransmissions = 5683 stats->stat_Dot3StatsDeferredTransmissions; 5684 5685 sc->stat_Dot3StatsExcessiveCollisions = 5686 stats->stat_Dot3StatsExcessiveCollisions; 5687 5688 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5689 5690 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5691 5692 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5693 5694 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5695 5696 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5697 5698 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5699 5700 sc->stat_EtherStatsPktsRx64Octets = 5701 stats->stat_EtherStatsPktsRx64Octets; 5702 5703 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5704 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5705 5706 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5707 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5708 5709 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5710 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5711 5712 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5713 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5714 5715 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5716 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5717 5718 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5719 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5720 5721 sc->stat_EtherStatsPktsTx64Octets = 5722 stats->stat_EtherStatsPktsTx64Octets; 5723 5724 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5725 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5726 5727 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5728 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5729 5730 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5731 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5732 5733 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5734 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5735 5736 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5737 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5738 5739 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5740 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5741 5742 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5743 5744 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5745 5746 sc->stat_OutXonSent = stats->stat_OutXonSent; 5747 5748 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5749 5750 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5751 5752 sc->stat_MacControlFramesReceived = 5753 stats->stat_MacControlFramesReceived; 5754 5755 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5756 5757 sc->stat_IfInFramesL2FilterDiscards = 5758 stats->stat_IfInFramesL2FilterDiscards; 5759 5760 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5761 5762 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5763 5764 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5765 5766 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5767 5768 sc->stat_CatchupInRuleCheckerDiscards = 5769 stats->stat_CatchupInRuleCheckerDiscards; 5770 5771 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5772 5773 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5774 5775 sc->stat_CatchupInRuleCheckerP4Hit = 5776 stats->stat_CatchupInRuleCheckerP4Hit; 5777 5778 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5779 } 5780 5781 void 5782 bnx_tick(void *xsc) 5783 { 5784 struct bnx_softc *sc = xsc; 5785 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5786 struct mii_data *mii; 5787 uint32_t msg; 5788 uint16_t prod, chain_prod; 5789 uint32_t prod_bseq; 5790 int s = splnet(); 5791 5792 /* Tell the firmware that the driver is still running. */ 5793 #ifdef BNX_DEBUG 5794 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5795 #else 5796 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5797 #endif 5798 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5799 5800 /* Update the statistics from the hardware statistics block. */ 5801 bnx_stats_update(sc); 5802 5803 /* Schedule the next tick. */ 5804 if (!sc->bnx_detaching) 5805 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5806 5807 if (sc->bnx_link) 5808 goto bnx_tick_exit; 5809 5810 mii = &sc->bnx_mii; 5811 mii_tick(mii); 5812 5813 /* Check if the link has come up. */ 5814 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5815 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5816 sc->bnx_link++; 5817 /* Now that link is up, handle any outstanding TX traffic. */ 5818 if_schedule_deferred_start(ifp); 5819 } 5820 5821 bnx_tick_exit: 5822 /* try to get more RX buffers, just in case */ 5823 prod = sc->rx_prod; 5824 prod_bseq = sc->rx_prod_bseq; 5825 chain_prod = RX_CHAIN_IDX(prod); 5826 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5827 sc->rx_prod = prod; 5828 sc->rx_prod_bseq = prod_bseq; 5829 5830 splx(s); 5831 return; 5832 } 5833 5834 /****************************************************************************/ 5835 /* BNX Debug Routines */ 5836 /****************************************************************************/ 5837 #ifdef BNX_DEBUG 5838 5839 /****************************************************************************/ 5840 /* Prints out information about an mbuf. */ 5841 /* */ 5842 /* Returns: */ 5843 /* Nothing. */ 5844 /****************************************************************************/ 5845 void 5846 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5847 { 5848 struct mbuf *mp = m; 5849 5850 if (m == NULL) { 5851 /* Index out of range. */ 5852 aprint_error("mbuf ptr is null!\n"); 5853 return; 5854 } 5855 5856 while (mp) { 5857 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5858 mp, mp->m_len); 5859 5860 if (mp->m_flags & M_EXT) 5861 aprint_debug("M_EXT "); 5862 if (mp->m_flags & M_PKTHDR) 5863 aprint_debug("M_PKTHDR "); 5864 aprint_debug("\n"); 5865 5866 if (mp->m_flags & M_EXT) 5867 aprint_debug("- m_ext: vaddr = %p, " 5868 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5869 5870 mp = mp->m_next; 5871 } 5872 } 5873 5874 /****************************************************************************/ 5875 /* Prints out the mbufs in the TX mbuf chain. */ 5876 /* */ 5877 /* Returns: */ 5878 /* Nothing. */ 5879 /****************************************************************************/ 5880 void 5881 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5882 { 5883 #if 0 5884 struct mbuf *m; 5885 int i; 5886 5887 aprint_debug_dev(sc->bnx_dev, 5888 "----------------------------" 5889 " tx mbuf data " 5890 "----------------------------\n"); 5891 5892 for (i = 0; i < count; i++) { 5893 m = sc->tx_mbuf_ptr[chain_prod]; 5894 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5895 bnx_dump_mbuf(sc, m); 5896 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5897 } 5898 5899 aprint_debug_dev(sc->bnx_dev, 5900 "--------------------------------------------" 5901 "----------------------------\n"); 5902 #endif 5903 } 5904 5905 /* 5906 * This routine prints the RX mbuf chain. 5907 */ 5908 void 5909 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5910 { 5911 struct mbuf *m; 5912 int i; 5913 5914 aprint_debug_dev(sc->bnx_dev, 5915 "----------------------------" 5916 " rx mbuf data " 5917 "----------------------------\n"); 5918 5919 for (i = 0; i < count; i++) { 5920 m = sc->rx_mbuf_ptr[chain_prod]; 5921 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5922 bnx_dump_mbuf(sc, m); 5923 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5924 } 5925 5926 5927 aprint_debug_dev(sc->bnx_dev, 5928 "--------------------------------------------" 5929 "----------------------------\n"); 5930 } 5931 5932 void 5933 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 5934 { 5935 if (idx > MAX_TX_BD) 5936 /* Index out of range. */ 5937 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 5938 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 5939 /* TX Chain page pointer. */ 5940 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 5941 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 5942 txbd->tx_bd_haddr_lo); 5943 else 5944 /* Normal tx_bd entry. */ 5945 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5946 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 5947 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 5948 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 5949 txbd->tx_bd_flags); 5950 } 5951 5952 void 5953 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 5954 { 5955 if (idx > MAX_RX_BD) 5956 /* Index out of range. */ 5957 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 5958 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5959 /* TX Chain page pointer. */ 5960 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 5961 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 5962 rxbd->rx_bd_haddr_lo); 5963 else 5964 /* Normal tx_bd entry. */ 5965 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 5966 "0x%08X, flags = 0x%08X\n", idx, 5967 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 5968 rxbd->rx_bd_len, rxbd->rx_bd_flags); 5969 } 5970 5971 void 5972 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 5973 { 5974 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 5975 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 5976 "tcp_udp_xsum = 0x%04X\n", idx, 5977 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 5978 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 5979 l2fhdr->l2_fhdr_tcp_udp_xsum); 5980 } 5981 5982 /* 5983 * This routine prints the TX chain. 5984 */ 5985 void 5986 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 5987 { 5988 struct tx_bd *txbd; 5989 int i; 5990 5991 /* First some info about the tx_bd chain structure. */ 5992 aprint_debug_dev(sc->bnx_dev, 5993 "----------------------------" 5994 " tx_bd chain " 5995 "----------------------------\n"); 5996 5997 BNX_PRINTF(sc, 5998 "page size = 0x%08X, tx chain pages = 0x%08X\n", 5999 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6000 6001 BNX_PRINTF(sc, 6002 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6003 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6004 6005 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6006 6007 aprint_error_dev(sc->bnx_dev, "" 6008 "-----------------------------" 6009 " tx_bd data " 6010 "-----------------------------\n"); 6011 6012 /* Now print out the tx_bd's themselves. */ 6013 for (i = 0; i < count; i++) { 6014 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6015 bnx_dump_txbd(sc, tx_prod, txbd); 6016 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6017 } 6018 6019 aprint_debug_dev(sc->bnx_dev, 6020 "-----------------------------" 6021 "--------------" 6022 "-----------------------------\n"); 6023 } 6024 6025 /* 6026 * This routine prints the RX chain. 6027 */ 6028 void 6029 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6030 { 6031 struct rx_bd *rxbd; 6032 int i; 6033 6034 /* First some info about the tx_bd chain structure. */ 6035 aprint_debug_dev(sc->bnx_dev, 6036 "----------------------------" 6037 " rx_bd chain " 6038 "----------------------------\n"); 6039 6040 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6041 6042 BNX_PRINTF(sc, 6043 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6044 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6045 6046 BNX_PRINTF(sc, 6047 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6048 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6049 6050 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6051 6052 aprint_error_dev(sc->bnx_dev, 6053 "----------------------------" 6054 " rx_bd data " 6055 "----------------------------\n"); 6056 6057 /* Now print out the rx_bd's themselves. */ 6058 for (i = 0; i < count; i++) { 6059 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6060 bnx_dump_rxbd(sc, rx_prod, rxbd); 6061 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6062 } 6063 6064 aprint_debug_dev(sc->bnx_dev, 6065 "----------------------------" 6066 "--------------" 6067 "----------------------------\n"); 6068 } 6069 6070 /* 6071 * This routine prints the status block. 6072 */ 6073 void 6074 bnx_dump_status_block(struct bnx_softc *sc) 6075 { 6076 struct status_block *sblk; 6077 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6078 BUS_DMASYNC_POSTREAD); 6079 6080 sblk = sc->status_block; 6081 6082 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6083 "Status Block -----------------------------\n"); 6084 6085 BNX_PRINTF(sc, 6086 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6087 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6088 sblk->status_idx); 6089 6090 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6091 sblk->status_rx_quick_consumer_index0, 6092 sblk->status_tx_quick_consumer_index0); 6093 6094 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6095 6096 /* Theses indices are not used for normal L2 drivers. */ 6097 if (sblk->status_rx_quick_consumer_index1 || 6098 sblk->status_tx_quick_consumer_index1) 6099 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6100 sblk->status_rx_quick_consumer_index1, 6101 sblk->status_tx_quick_consumer_index1); 6102 6103 if (sblk->status_rx_quick_consumer_index2 || 6104 sblk->status_tx_quick_consumer_index2) 6105 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6106 sblk->status_rx_quick_consumer_index2, 6107 sblk->status_tx_quick_consumer_index2); 6108 6109 if (sblk->status_rx_quick_consumer_index3 || 6110 sblk->status_tx_quick_consumer_index3) 6111 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6112 sblk->status_rx_quick_consumer_index3, 6113 sblk->status_tx_quick_consumer_index3); 6114 6115 if (sblk->status_rx_quick_consumer_index4 || 6116 sblk->status_rx_quick_consumer_index5) 6117 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6118 sblk->status_rx_quick_consumer_index4, 6119 sblk->status_rx_quick_consumer_index5); 6120 6121 if (sblk->status_rx_quick_consumer_index6 || 6122 sblk->status_rx_quick_consumer_index7) 6123 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6124 sblk->status_rx_quick_consumer_index6, 6125 sblk->status_rx_quick_consumer_index7); 6126 6127 if (sblk->status_rx_quick_consumer_index8 || 6128 sblk->status_rx_quick_consumer_index9) 6129 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6130 sblk->status_rx_quick_consumer_index8, 6131 sblk->status_rx_quick_consumer_index9); 6132 6133 if (sblk->status_rx_quick_consumer_index10 || 6134 sblk->status_rx_quick_consumer_index11) 6135 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6136 sblk->status_rx_quick_consumer_index10, 6137 sblk->status_rx_quick_consumer_index11); 6138 6139 if (sblk->status_rx_quick_consumer_index12 || 6140 sblk->status_rx_quick_consumer_index13) 6141 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6142 sblk->status_rx_quick_consumer_index12, 6143 sblk->status_rx_quick_consumer_index13); 6144 6145 if (sblk->status_rx_quick_consumer_index14 || 6146 sblk->status_rx_quick_consumer_index15) 6147 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6148 sblk->status_rx_quick_consumer_index14, 6149 sblk->status_rx_quick_consumer_index15); 6150 6151 if (sblk->status_completion_producer_index || 6152 sblk->status_cmd_consumer_index) 6153 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6154 sblk->status_completion_producer_index, 6155 sblk->status_cmd_consumer_index); 6156 6157 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6158 "-----------------------------\n"); 6159 } 6160 6161 /* 6162 * This routine prints the statistics block. 6163 */ 6164 void 6165 bnx_dump_stats_block(struct bnx_softc *sc) 6166 { 6167 struct statistics_block *sblk; 6168 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6169 BUS_DMASYNC_POSTREAD); 6170 6171 sblk = sc->stats_block; 6172 6173 aprint_debug_dev(sc->bnx_dev, "" 6174 "-----------------------------" 6175 " Stats Block " 6176 "-----------------------------\n"); 6177 6178 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6179 "IfHcInBadOctets = 0x%08X:%08X\n", 6180 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6181 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6182 6183 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6184 "IfHcOutBadOctets = 0x%08X:%08X\n", 6185 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6186 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6187 6188 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6189 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6190 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6191 sblk->stat_IfHCInMulticastPkts_hi, 6192 sblk->stat_IfHCInMulticastPkts_lo); 6193 6194 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6195 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6196 sblk->stat_IfHCInBroadcastPkts_hi, 6197 sblk->stat_IfHCInBroadcastPkts_lo, 6198 sblk->stat_IfHCOutUcastPkts_hi, 6199 sblk->stat_IfHCOutUcastPkts_lo); 6200 6201 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6202 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6203 sblk->stat_IfHCOutMulticastPkts_hi, 6204 sblk->stat_IfHCOutMulticastPkts_lo, 6205 sblk->stat_IfHCOutBroadcastPkts_hi, 6206 sblk->stat_IfHCOutBroadcastPkts_lo); 6207 6208 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6209 BNX_PRINTF(sc, "0x%08X : " 6210 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6211 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6212 6213 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6214 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6215 sblk->stat_Dot3StatsCarrierSenseErrors); 6216 6217 if (sblk->stat_Dot3StatsFCSErrors) 6218 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6219 sblk->stat_Dot3StatsFCSErrors); 6220 6221 if (sblk->stat_Dot3StatsAlignmentErrors) 6222 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6223 sblk->stat_Dot3StatsAlignmentErrors); 6224 6225 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6226 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6227 sblk->stat_Dot3StatsSingleCollisionFrames); 6228 6229 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6230 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6231 sblk->stat_Dot3StatsMultipleCollisionFrames); 6232 6233 if (sblk->stat_Dot3StatsDeferredTransmissions) 6234 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6235 sblk->stat_Dot3StatsDeferredTransmissions); 6236 6237 if (sblk->stat_Dot3StatsExcessiveCollisions) 6238 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6239 sblk->stat_Dot3StatsExcessiveCollisions); 6240 6241 if (sblk->stat_Dot3StatsLateCollisions) 6242 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6243 sblk->stat_Dot3StatsLateCollisions); 6244 6245 if (sblk->stat_EtherStatsCollisions) 6246 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6247 sblk->stat_EtherStatsCollisions); 6248 6249 if (sblk->stat_EtherStatsFragments) 6250 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6251 sblk->stat_EtherStatsFragments); 6252 6253 if (sblk->stat_EtherStatsJabbers) 6254 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6255 sblk->stat_EtherStatsJabbers); 6256 6257 if (sblk->stat_EtherStatsUndersizePkts) 6258 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6259 sblk->stat_EtherStatsUndersizePkts); 6260 6261 if (sblk->stat_EtherStatsOverrsizePkts) 6262 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6263 sblk->stat_EtherStatsOverrsizePkts); 6264 6265 if (sblk->stat_EtherStatsPktsRx64Octets) 6266 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6267 sblk->stat_EtherStatsPktsRx64Octets); 6268 6269 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6270 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6271 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6272 6273 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6274 BNX_PRINTF(sc, "0x%08X : " 6275 "EtherStatsPktsRx128Octetsto255Octets\n", 6276 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6277 6278 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6279 BNX_PRINTF(sc, "0x%08X : " 6280 "EtherStatsPktsRx256Octetsto511Octets\n", 6281 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6282 6283 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6284 BNX_PRINTF(sc, "0x%08X : " 6285 "EtherStatsPktsRx512Octetsto1023Octets\n", 6286 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6287 6288 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6289 BNX_PRINTF(sc, "0x%08X : " 6290 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6291 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6292 6293 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6294 BNX_PRINTF(sc, "0x%08X : " 6295 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6296 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6297 6298 if (sblk->stat_EtherStatsPktsTx64Octets) 6299 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6300 sblk->stat_EtherStatsPktsTx64Octets); 6301 6302 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6303 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6304 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6305 6306 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6307 BNX_PRINTF(sc, "0x%08X : " 6308 "EtherStatsPktsTx128Octetsto255Octets\n", 6309 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6310 6311 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6312 BNX_PRINTF(sc, "0x%08X : " 6313 "EtherStatsPktsTx256Octetsto511Octets\n", 6314 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6315 6316 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6317 BNX_PRINTF(sc, "0x%08X : " 6318 "EtherStatsPktsTx512Octetsto1023Octets\n", 6319 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6320 6321 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6322 BNX_PRINTF(sc, "0x%08X : " 6323 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6324 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6325 6326 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6327 BNX_PRINTF(sc, "0x%08X : " 6328 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6329 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6330 6331 if (sblk->stat_XonPauseFramesReceived) 6332 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6333 sblk->stat_XonPauseFramesReceived); 6334 6335 if (sblk->stat_XoffPauseFramesReceived) 6336 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6337 sblk->stat_XoffPauseFramesReceived); 6338 6339 if (sblk->stat_OutXonSent) 6340 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6341 sblk->stat_OutXonSent); 6342 6343 if (sblk->stat_OutXoffSent) 6344 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6345 sblk->stat_OutXoffSent); 6346 6347 if (sblk->stat_FlowControlDone) 6348 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6349 sblk->stat_FlowControlDone); 6350 6351 if (sblk->stat_MacControlFramesReceived) 6352 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6353 sblk->stat_MacControlFramesReceived); 6354 6355 if (sblk->stat_XoffStateEntered) 6356 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6357 sblk->stat_XoffStateEntered); 6358 6359 if (sblk->stat_IfInFramesL2FilterDiscards) 6360 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6361 sblk->stat_IfInFramesL2FilterDiscards); 6362 6363 if (sblk->stat_IfInRuleCheckerDiscards) 6364 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6365 sblk->stat_IfInRuleCheckerDiscards); 6366 6367 if (sblk->stat_IfInFTQDiscards) 6368 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6369 sblk->stat_IfInFTQDiscards); 6370 6371 if (sblk->stat_IfInMBUFDiscards) 6372 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6373 sblk->stat_IfInMBUFDiscards); 6374 6375 if (sblk->stat_IfInRuleCheckerP4Hit) 6376 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6377 sblk->stat_IfInRuleCheckerP4Hit); 6378 6379 if (sblk->stat_CatchupInRuleCheckerDiscards) 6380 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6381 sblk->stat_CatchupInRuleCheckerDiscards); 6382 6383 if (sblk->stat_CatchupInFTQDiscards) 6384 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6385 sblk->stat_CatchupInFTQDiscards); 6386 6387 if (sblk->stat_CatchupInMBUFDiscards) 6388 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6389 sblk->stat_CatchupInMBUFDiscards); 6390 6391 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6392 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6393 sblk->stat_CatchupInRuleCheckerP4Hit); 6394 6395 aprint_debug_dev(sc->bnx_dev, 6396 "-----------------------------" 6397 "--------------" 6398 "-----------------------------\n"); 6399 } 6400 6401 void 6402 bnx_dump_driver_state(struct bnx_softc *sc) 6403 { 6404 aprint_debug_dev(sc->bnx_dev, 6405 "-----------------------------" 6406 " Driver State " 6407 "-----------------------------\n"); 6408 6409 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6410 "address\n", sc); 6411 6412 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6413 sc->status_block); 6414 6415 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6416 "address\n", sc->stats_block); 6417 6418 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6419 "address\n", sc->tx_bd_chain); 6420 6421 #if 0 6422 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6423 sc->rx_bd_chain); 6424 6425 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6426 sc->tx_mbuf_ptr); 6427 #endif 6428 6429 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6430 sc->rx_mbuf_ptr); 6431 6432 BNX_PRINTF(sc, 6433 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6434 sc->interrupts_generated); 6435 6436 BNX_PRINTF(sc, 6437 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6438 sc->rx_interrupts); 6439 6440 BNX_PRINTF(sc, 6441 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6442 sc->tx_interrupts); 6443 6444 BNX_PRINTF(sc, 6445 " 0x%08X - (sc->last_status_idx) status block index\n", 6446 sc->last_status_idx); 6447 6448 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6449 sc->tx_prod); 6450 6451 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6452 sc->tx_cons); 6453 6454 BNX_PRINTF(sc, 6455 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6456 sc->tx_prod_bseq); 6457 BNX_PRINTF(sc, 6458 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6459 sc->tx_mbuf_alloc); 6460 6461 BNX_PRINTF(sc, 6462 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6463 sc->used_tx_bd); 6464 6465 BNX_PRINTF(sc, 6466 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6467 sc->tx_hi_watermark, sc->max_tx_bd); 6468 6469 6470 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6471 sc->rx_prod); 6472 6473 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6474 sc->rx_cons); 6475 6476 BNX_PRINTF(sc, 6477 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6478 sc->rx_prod_bseq); 6479 6480 BNX_PRINTF(sc, 6481 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6482 sc->rx_mbuf_alloc); 6483 6484 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6485 sc->free_rx_bd); 6486 6487 BNX_PRINTF(sc, 6488 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6489 sc->rx_low_watermark, sc->max_rx_bd); 6490 6491 BNX_PRINTF(sc, 6492 " 0x%08X - (sc->mbuf_alloc_failed) " 6493 "mbuf alloc failures\n", 6494 sc->mbuf_alloc_failed); 6495 6496 BNX_PRINTF(sc, 6497 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6498 "simulated mbuf alloc failures\n", 6499 sc->mbuf_sim_alloc_failed); 6500 6501 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6502 "-----------------------------\n"); 6503 } 6504 6505 void 6506 bnx_dump_hw_state(struct bnx_softc *sc) 6507 { 6508 uint32_t val1; 6509 int i; 6510 6511 aprint_debug_dev(sc->bnx_dev, 6512 "----------------------------" 6513 " Hardware State " 6514 "----------------------------\n"); 6515 6516 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6517 6518 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6519 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6520 val1, BNX_MISC_ENABLE_STATUS_BITS); 6521 6522 val1 = REG_RD(sc, BNX_DMA_STATUS); 6523 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6524 6525 val1 = REG_RD(sc, BNX_CTX_STATUS); 6526 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6527 6528 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6529 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6530 BNX_EMAC_STATUS); 6531 6532 val1 = REG_RD(sc, BNX_RPM_STATUS); 6533 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6534 6535 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6536 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6537 BNX_TBDR_STATUS); 6538 6539 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6540 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6541 BNX_TDMA_STATUS); 6542 6543 val1 = REG_RD(sc, BNX_HC_STATUS); 6544 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6545 6546 aprint_debug_dev(sc->bnx_dev, 6547 "----------------------------" 6548 "----------------" 6549 "----------------------------\n"); 6550 6551 aprint_debug_dev(sc->bnx_dev, 6552 "----------------------------" 6553 " Register Dump " 6554 "----------------------------\n"); 6555 6556 for (i = 0x400; i < 0x8000; i += 0x10) 6557 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6558 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6559 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6560 6561 aprint_debug_dev(sc->bnx_dev, 6562 "----------------------------" 6563 "----------------" 6564 "----------------------------\n"); 6565 } 6566 6567 void 6568 bnx_breakpoint(struct bnx_softc *sc) 6569 { 6570 /* Unreachable code to shut the compiler up about unused functions. */ 6571 if (0) { 6572 bnx_dump_txbd(sc, 0, NULL); 6573 bnx_dump_rxbd(sc, 0, NULL); 6574 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6575 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6576 bnx_dump_l2fhdr(sc, 0, NULL); 6577 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6578 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6579 bnx_dump_status_block(sc); 6580 bnx_dump_stats_block(sc); 6581 bnx_dump_driver_state(sc); 6582 bnx_dump_hw_state(sc); 6583 } 6584 6585 bnx_dump_driver_state(sc); 6586 /* Print the important status block fields. */ 6587 bnx_dump_status_block(sc); 6588 6589 #if 0 6590 /* Call the debugger. */ 6591 breakpoint(); 6592 #endif 6593 6594 return; 6595 } 6596 #endif 6597
Indexes created Thu Sep 25 16:09:42 GMT 2025