if_bnx.c revision 1.78
1 /* $NetBSD: if_bnx.c,v 1.78 2019/04/05 07:15:26 msaitoh Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.78 2019/04/05 07:15:26 msaitoh Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 device_t dev = sc->bnx_dev; 466 int i = 0; 467 468 aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 469 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 470 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 471 ? "Serdes " : "", sc->bnx_chipid); 472 473 /* Bus info. */ 474 if (sc->bnx_flags & BNX_PCIE_FLAG) { 475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); 476 switch (sc->link_speed) { 477 case 1: aprint_normal("2.5GT/s\n"); break; 478 case 2: aprint_normal("5GT/s\n"); break; 479 default: aprint_normal("Unknown link speed\n"); 480 } 481 } else { 482 aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n", 483 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 484 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 485 sc->bus_speed_mhz); 486 } 487 488 /* Firmware version and device features. */ 489 aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (", 490 sc->bnx_bc_ver, RX_PAGES, TX_PAGES); 491 492 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) { 493 if (i > 0) aprint_normal("|"); 494 aprint_normal("2.5G"); i++; 495 } 496 497 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 498 if (i > 0) aprint_normal("|"); 499 aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver); 500 } else { 501 aprint_normal(")\n"); 502 } 503 504 aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 505 sc->bnx_rx_quick_cons_trip_int, 506 sc->bnx_rx_quick_cons_trip, 507 sc->bnx_rx_ticks_int, 508 sc->bnx_rx_ticks, 509 sc->bnx_tx_quick_cons_trip_int, 510 sc->bnx_tx_quick_cons_trip, 511 sc->bnx_tx_ticks_int, 512 sc->bnx_tx_ticks); 513 } 514 515 516 /****************************************************************************/ 517 /* PCI Capabilities Probe Function. */ 518 /* */ 519 /* Walks the PCI capabiites list for the device to find what features are */ 520 /* supported. */ 521 /* */ 522 /* Returns: */ 523 /* None. */ 524 /****************************************************************************/ 525 static void 526 bnx_probe_pci_caps(struct bnx_softc *sc) 527 { 528 struct pci_attach_args *pa = &(sc->bnx_pa); 529 pcireg_t reg; 530 531 /* Check if PCI-X capability is enabled. */ 532 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 533 NULL) != 0) { 534 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 535 } 536 537 /* Check if PCIe capability is enabled. */ 538 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 539 NULL) != 0) { 540 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 541 reg + PCIE_LCSR); 542 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 543 "0x%08X\n", link_status); 544 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 546 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 547 sc->bnx_flags |= BNX_PCIE_FLAG; 548 } 549 550 /* Check if MSI capability is enabled. */ 551 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 552 NULL) != 0) 553 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 554 555 /* Check if MSI-X capability is enabled. */ 556 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 557 NULL) != 0) 558 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 559 } 560 561 562 /****************************************************************************/ 563 /* Device attach function. */ 564 /* */ 565 /* Allocates device resources, performs secondary chip identification, */ 566 /* resets and initializes the hardware, and initializes driver instance */ 567 /* variables. */ 568 /* */ 569 /* Returns: */ 570 /* 0 on success, positive value on failure. */ 571 /****************************************************************************/ 572 void 573 bnx_attach(device_t parent, device_t self, void *aux) 574 { 575 const struct bnx_product *bp; 576 struct bnx_softc *sc = device_private(self); 577 prop_dictionary_t dict; 578 struct pci_attach_args *pa = aux; 579 pci_chipset_tag_t pc = pa->pa_pc; 580 pci_intr_handle_t ih; 581 const char *intrstr = NULL; 582 uint32_t command; 583 struct ifnet *ifp; 584 uint32_t val; 585 int mii_flags = MIIF_FORCEANEG; 586 pcireg_t memtype; 587 char intrbuf[PCI_INTRSTR_LEN]; 588 int i, j; 589 590 if (bnx_tx_pool == NULL) { 591 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 592 if (bnx_tx_pool != NULL) { 593 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 594 0, 0, 0, "bnxpkts", NULL, IPL_NET); 595 } else { 596 aprint_error(": can't alloc bnx_tx_pool\n"); 597 return; 598 } 599 } 600 601 bp = bnx_lookup(pa); 602 if (bp == NULL) 603 panic("unknown device"); 604 605 sc->bnx_dev = self; 606 607 aprint_naive("\n"); 608 aprint_normal(": %s\n", bp->bp_name); 609 610 sc->bnx_pa = *pa; 611 612 /* 613 * Map control/status registers. 614 */ 615 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 616 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 617 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 618 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 619 620 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 621 aprint_error_dev(sc->bnx_dev, 622 "failed to enable memory mapping!\n"); 623 return; 624 } 625 626 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 627 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 628 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 629 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 630 return; 631 } 632 633 if (pci_intr_map(pa, &ih)) { 634 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 635 goto bnx_attach_fail; 636 } 637 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 638 639 /* 640 * Configure byte swap and enable indirect register access. 641 * Rely on CPU to do target byte swapping on big endian systems. 642 * Access to registers outside of PCI configurtion space are not 643 * valid until this is done. 644 */ 645 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 646 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 647 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 648 649 /* Save ASIC revsion info. */ 650 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 651 652 /* 653 * Find the base address for shared memory access. 654 * Newer versions of bootcode use a signature and offset 655 * while older versions use a fixed address. 656 */ 657 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 658 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 659 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 660 (sc->bnx_pa.pa_function << 2)); 661 else 662 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 663 664 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 665 666 /* Set initial device and PHY flags */ 667 sc->bnx_flags = 0; 668 sc->bnx_phy_flags = 0; 669 670 /* Fetch the bootcode revision. */ 671 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 672 for (i = 0, j = 0; i < 3; i++) { 673 uint8_t num; 674 int k, skip0; 675 676 num = (uint8_t)(val >> (24 - (i * 8))); 677 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 678 if (num >= k || !skip0 || k == 1) { 679 sc->bnx_bc_ver[j++] = (num / k) + '0'; 680 skip0 = 0; 681 } 682 } 683 if (i != 2) 684 sc->bnx_bc_ver[j++] = '.'; 685 } 686 687 /* Check if any management firmware is enabled. */ 688 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 689 if (val & BNX_PORT_FEATURE_ASF_ENABLED) { 690 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 691 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 692 693 /* Allow time for firmware to enter the running state. */ 694 for (i = 0; i < 30; i++) { 695 val = REG_RD_IND(sc, sc->bnx_shmem_base + 696 BNX_BC_STATE_CONDITION); 697 if (val & BNX_CONDITION_MFW_RUN_MASK) 698 break; 699 DELAY(10000); 700 } 701 702 /* Check if management firmware is running. */ 703 val = REG_RD_IND(sc, sc->bnx_shmem_base + 704 BNX_BC_STATE_CONDITION); 705 val &= BNX_CONDITION_MFW_RUN_MASK; 706 if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) && 707 (val != BNX_CONDITION_MFW_RUN_NONE)) { 708 uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base + 709 BNX_MFW_VER_PTR); 710 711 /* Read the management firmware version string. */ 712 for (j = 0; j < 3; j++) { 713 val = bnx_reg_rd_ind(sc, addr + j * 4); 714 val = bswap32(val); 715 memcpy(&sc->bnx_mfw_ver[i], &val, 4); 716 i += 4; 717 } 718 } else { 719 /* May cause firmware synchronization timeouts. */ 720 BNX_PRINTF(sc, "%s(%d): Management firmware enabled " 721 "but not running!\n", __FILE__, __LINE__); 722 strcpy(sc->bnx_mfw_ver, "NOT RUNNING!"); 723 724 /* ToDo: Any action the driver should take? */ 725 } 726 } 727 728 bnx_probe_pci_caps(sc); 729 730 /* Get PCI bus information (speed and type). */ 731 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 732 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 733 uint32_t clkreg; 734 735 sc->bnx_flags |= BNX_PCIX_FLAG; 736 737 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 738 739 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 740 switch (clkreg) { 741 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 742 sc->bus_speed_mhz = 133; 743 break; 744 745 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 746 sc->bus_speed_mhz = 100; 747 break; 748 749 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 750 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 751 sc->bus_speed_mhz = 66; 752 break; 753 754 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 755 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 756 sc->bus_speed_mhz = 50; 757 break; 758 759 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 760 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 761 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 762 sc->bus_speed_mhz = 33; 763 break; 764 } 765 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 766 sc->bus_speed_mhz = 66; 767 else 768 sc->bus_speed_mhz = 33; 769 770 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 771 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 772 773 /* Reset the controller. */ 774 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 775 goto bnx_attach_fail; 776 777 /* Initialize the controller. */ 778 if (bnx_chipinit(sc)) { 779 aprint_error_dev(sc->bnx_dev, 780 "Controller initialization failed!\n"); 781 goto bnx_attach_fail; 782 } 783 784 /* Perform NVRAM test. */ 785 if (bnx_nvram_test(sc)) { 786 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 787 goto bnx_attach_fail; 788 } 789 790 /* Fetch the permanent Ethernet MAC address. */ 791 bnx_get_mac_addr(sc); 792 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 793 ether_sprintf(sc->eaddr)); 794 795 /* 796 * Trip points control how many BDs 797 * should be ready before generating an 798 * interrupt while ticks control how long 799 * a BD can sit in the chain before 800 * generating an interrupt. Set the default 801 * values for the RX and TX rings. 802 */ 803 804 #ifdef BNX_DEBUG 805 /* Force more frequent interrupts. */ 806 sc->bnx_tx_quick_cons_trip_int = 1; 807 sc->bnx_tx_quick_cons_trip = 1; 808 sc->bnx_tx_ticks_int = 0; 809 sc->bnx_tx_ticks = 0; 810 811 sc->bnx_rx_quick_cons_trip_int = 1; 812 sc->bnx_rx_quick_cons_trip = 1; 813 sc->bnx_rx_ticks_int = 0; 814 sc->bnx_rx_ticks = 0; 815 #else 816 sc->bnx_tx_quick_cons_trip_int = 20; 817 sc->bnx_tx_quick_cons_trip = 20; 818 sc->bnx_tx_ticks_int = 80; 819 sc->bnx_tx_ticks = 80; 820 821 sc->bnx_rx_quick_cons_trip_int = 6; 822 sc->bnx_rx_quick_cons_trip = 6; 823 sc->bnx_rx_ticks_int = 18; 824 sc->bnx_rx_ticks = 18; 825 #endif 826 827 /* Update statistics once every second. */ 828 sc->bnx_stats_ticks = 1000000 & 0xffff00; 829 830 /* Find the media type for the adapter. */ 831 bnx_get_media(sc); 832 833 /* 834 * Store config data needed by the PHY driver for 835 * backplane applications 836 */ 837 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 838 BNX_SHARED_HW_CFG_CONFIG); 839 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 840 BNX_PORT_HW_CFG_CONFIG); 841 842 /* Allocate DMA memory resources. */ 843 sc->bnx_dmatag = pa->pa_dmat; 844 if (bnx_dma_alloc(sc)) { 845 aprint_error_dev(sc->bnx_dev, 846 "DMA resource allocation failed!\n"); 847 goto bnx_attach_fail; 848 } 849 850 /* Initialize the ifnet interface. */ 851 ifp = &sc->bnx_ec.ec_if; 852 ifp->if_softc = sc; 853 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 854 ifp->if_ioctl = bnx_ioctl; 855 ifp->if_stop = bnx_stop; 856 ifp->if_start = bnx_start; 857 ifp->if_init = bnx_init; 858 ifp->if_watchdog = bnx_watchdog; 859 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 860 IFQ_SET_READY(&ifp->if_snd); 861 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 862 863 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 864 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 865 866 ifp->if_capabilities |= 867 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 868 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 869 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 870 871 /* create workqueue to handle packet allocations */ 872 if (workqueue_create(&sc->bnx_wq, device_xname(self), 873 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 874 aprint_error_dev(self, "failed to create workqueue\n"); 875 goto bnx_attach_fail; 876 } 877 878 sc->bnx_mii.mii_ifp = ifp; 879 sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; 880 sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; 881 sc->bnx_mii.mii_statchg = bnx_miibus_statchg; 882 883 /* Handle any special PHY initialization for SerDes PHYs. */ 884 bnx_init_media(sc); 885 886 sc->bnx_ec.ec_mii = &sc->bnx_mii; 887 ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, 888 bnx_ifmedia_sts); 889 890 /* set phyflags and chipid before mii_attach() */ 891 dict = device_properties(self); 892 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 893 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 894 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 895 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 896 897 /* Print some useful adapter info */ 898 bnx_print_adapter_info(sc); 899 900 mii_flags |= MIIF_DOPAUSE; 901 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 902 mii_flags |= MIIF_HAVEFIBER; 903 mii_attach(self, &sc->bnx_mii, 0xffffffff, 904 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 905 906 if (LIST_EMPTY(&sc->bnx_mii.mii_phys)) { 907 aprint_error_dev(self, "no PHY found!\n"); 908 ifmedia_add(&sc->bnx_mii.mii_media, 909 IFM_ETHER|IFM_MANUAL, 0, NULL); 910 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_MANUAL); 911 } else 912 ifmedia_set(&sc->bnx_mii.mii_media, IFM_ETHER | IFM_AUTO); 913 914 /* Attach to the Ethernet interface list. */ 915 if_attach(ifp); 916 if_deferred_start_init(ifp, NULL); 917 ether_ifattach(ifp,sc->eaddr); 918 919 callout_init(&sc->bnx_timeout, 0); 920 921 /* Hookup IRQ last. */ 922 sc->bnx_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bnx_intr, 923 sc, device_xname(self)); 924 if (sc->bnx_intrhand == NULL) { 925 aprint_error_dev(self, "couldn't establish interrupt"); 926 if (intrstr != NULL) 927 aprint_error(" at %s", intrstr); 928 aprint_error("\n"); 929 goto bnx_attach_fail; 930 } 931 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 932 933 if (pmf_device_register(self, NULL, NULL)) 934 pmf_class_network_register(self, ifp); 935 else 936 aprint_error_dev(self, "couldn't establish power handler\n"); 937 938 /* Print some important debugging info. */ 939 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 940 941 /* Get the firmware running so ASF still works. */ 942 bnx_mgmt_init(sc); 943 944 goto bnx_attach_exit; 945 946 bnx_attach_fail: 947 bnx_release_resources(sc); 948 949 bnx_attach_exit: 950 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 951 } 952 953 /****************************************************************************/ 954 /* Device detach function. */ 955 /* */ 956 /* Stops the controller, resets the controller, and releases resources. */ 957 /* */ 958 /* Returns: */ 959 /* 0 on success, positive value on failure. */ 960 /****************************************************************************/ 961 int 962 bnx_detach(device_t dev, int flags) 963 { 964 int s; 965 struct bnx_softc *sc; 966 struct ifnet *ifp; 967 968 sc = device_private(dev); 969 ifp = &sc->bnx_ec.ec_if; 970 971 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 972 973 /* Stop and reset the controller. */ 974 s = splnet(); 975 bnx_stop(ifp, 1); 976 splx(s); 977 978 pmf_device_deregister(dev); 979 callout_destroy(&sc->bnx_timeout); 980 ether_ifdetach(ifp); 981 workqueue_destroy(sc->bnx_wq); 982 983 /* Delete all remaining media. */ 984 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 985 986 if_detach(ifp); 987 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 988 989 /* Release all remaining resources. */ 990 bnx_release_resources(sc); 991 992 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 993 994 return 0; 995 } 996 997 /****************************************************************************/ 998 /* Indirect register read. */ 999 /* */ 1000 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1001 /* configuration space. Using this mechanism avoids issues with posted */ 1002 /* reads but is much slower than memory-mapped I/O. */ 1003 /* */ 1004 /* Returns: */ 1005 /* The value of the register. */ 1006 /****************************************************************************/ 1007 uint32_t 1008 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 1009 { 1010 struct pci_attach_args *pa = &(sc->bnx_pa); 1011 1012 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1013 offset); 1014 #ifdef BNX_DEBUG 1015 { 1016 uint32_t val; 1017 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 1018 BNX_PCICFG_REG_WINDOW); 1019 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 1020 "val = 0x%08X\n", __func__, offset, val); 1021 return val; 1022 } 1023 #else 1024 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 1025 #endif 1026 } 1027 1028 /****************************************************************************/ 1029 /* Indirect register write. */ 1030 /* */ 1031 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1032 /* configuration space. Using this mechanism avoids issues with posted */ 1033 /* writes but is muchh slower than memory-mapped I/O. */ 1034 /* */ 1035 /* Returns: */ 1036 /* Nothing. */ 1037 /****************************************************************************/ 1038 void 1039 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 1040 { 1041 struct pci_attach_args *pa = &(sc->bnx_pa); 1042 1043 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 1044 __func__, offset, val); 1045 1046 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1047 offset); 1048 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 1049 } 1050 1051 /****************************************************************************/ 1052 /* Context memory write. */ 1053 /* */ 1054 /* The NetXtreme II controller uses context memory to track connection */ 1055 /* information for L2 and higher network protocols. */ 1056 /* */ 1057 /* Returns: */ 1058 /* Nothing. */ 1059 /****************************************************************************/ 1060 void 1061 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 1062 uint32_t ctx_val) 1063 { 1064 uint32_t idx, offset = ctx_offset + cid_addr; 1065 uint32_t val, retry_cnt = 5; 1066 1067 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1068 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1069 REG_WR(sc, BNX_CTX_CTX_CTRL, 1070 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 1071 1072 for (idx = 0; idx < retry_cnt; idx++) { 1073 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1074 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1075 break; 1076 DELAY(5); 1077 } 1078 1079 #if 0 1080 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1081 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1082 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1083 __FILE__, __LINE__, cid_addr, ctx_offset); 1084 #endif 1085 1086 } else { 1087 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1088 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1089 } 1090 } 1091 1092 /****************************************************************************/ 1093 /* PHY register read. */ 1094 /* */ 1095 /* Implements register reads on the MII bus. */ 1096 /* */ 1097 /* Returns: */ 1098 /* The value of the register. */ 1099 /****************************************************************************/ 1100 int 1101 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1102 { 1103 struct bnx_softc *sc = device_private(dev); 1104 uint32_t data; 1105 int i, rv = 0; 1106 1107 /* 1108 * The BCM5709S PHY is an IEEE Clause 45 PHY 1109 * with special mappings to work with IEEE 1110 * Clause 22 register accesses. 1111 */ 1112 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1113 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1114 reg += 0x10; 1115 } 1116 1117 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1118 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1119 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1120 1121 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1122 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1123 1124 DELAY(40); 1125 } 1126 1127 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1128 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1129 BNX_EMAC_MDIO_COMM_START_BUSY; 1130 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1131 1132 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1133 DELAY(10); 1134 1135 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1136 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1137 DELAY(5); 1138 1139 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1140 data &= BNX_EMAC_MDIO_COMM_DATA; 1141 1142 break; 1143 } 1144 } 1145 1146 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1147 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1148 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1149 rv = ETIMEDOUT; 1150 } else { 1151 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1152 *val = data & 0xffff; 1153 1154 DBPRINT(sc, BNX_EXCESSIVE, 1155 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1156 phy, (uint16_t) reg & 0xffff, *val); 1157 } 1158 1159 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1160 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1161 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1162 1163 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1164 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1165 1166 DELAY(40); 1167 } 1168 1169 return rv; 1170 } 1171 1172 /****************************************************************************/ 1173 /* PHY register write. */ 1174 /* */ 1175 /* Implements register writes on the MII bus. */ 1176 /* */ 1177 /* Returns: */ 1178 /* The value of the register. */ 1179 /****************************************************************************/ 1180 int 1181 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1182 { 1183 struct bnx_softc *sc = device_private(dev); 1184 uint32_t val1; 1185 int i, rv = 0; 1186 1187 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1188 "val = 0x%04hX\n", __func__, 1189 phy, (uint16_t) reg & 0xffff, val); 1190 1191 /* 1192 * The BCM5709S PHY is an IEEE Clause 45 PHY 1193 * with special mappings to work with IEEE 1194 * Clause 22 register accesses. 1195 */ 1196 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1197 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1198 reg += 0x10; 1199 } 1200 1201 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1202 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1203 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1204 1205 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1206 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1207 1208 DELAY(40); 1209 } 1210 1211 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1212 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1213 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1214 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1215 1216 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1217 DELAY(10); 1218 1219 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1220 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1221 DELAY(5); 1222 break; 1223 } 1224 } 1225 1226 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1227 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1228 __LINE__); 1229 rv = ETIMEDOUT; 1230 } 1231 1232 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1233 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1234 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1235 1236 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1237 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1238 1239 DELAY(40); 1240 } 1241 1242 return rv; 1243 } 1244 1245 /****************************************************************************/ 1246 /* MII bus status change. */ 1247 /* */ 1248 /* Called by the MII bus driver when the PHY establishes link to set the */ 1249 /* MAC interface registers. */ 1250 /* */ 1251 /* Returns: */ 1252 /* Nothing. */ 1253 /****************************************************************************/ 1254 void 1255 bnx_miibus_statchg(struct ifnet *ifp) 1256 { 1257 struct bnx_softc *sc = ifp->if_softc; 1258 struct mii_data *mii = &sc->bnx_mii; 1259 uint32_t rx_mode = sc->rx_mode; 1260 int val; 1261 1262 val = REG_RD(sc, BNX_EMAC_MODE); 1263 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1264 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1265 BNX_EMAC_MODE_25G); 1266 1267 /* 1268 * Get flow control negotiation result. 1269 */ 1270 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1271 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1272 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1273 mii->mii_media_active &= ~IFM_ETH_FMASK; 1274 } 1275 1276 /* Set MII or GMII interface based on the speed 1277 * negotiated by the PHY. 1278 */ 1279 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1280 case IFM_10_T: 1281 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1282 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1283 val |= BNX_EMAC_MODE_PORT_MII_10; 1284 break; 1285 } 1286 /* FALLTHROUGH */ 1287 case IFM_100_TX: 1288 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1289 val |= BNX_EMAC_MODE_PORT_MII; 1290 break; 1291 case IFM_2500_SX: 1292 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1293 val |= BNX_EMAC_MODE_25G; 1294 /* FALLTHROUGH */ 1295 case IFM_1000_T: 1296 case IFM_1000_SX: 1297 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1298 val |= BNX_EMAC_MODE_PORT_GMII; 1299 break; 1300 default: 1301 val |= BNX_EMAC_MODE_PORT_GMII; 1302 break; 1303 } 1304 1305 /* Set half or full duplex based on the duplicity 1306 * negotiated by the PHY. 1307 */ 1308 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1309 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1310 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1311 } else 1312 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1313 1314 REG_WR(sc, BNX_EMAC_MODE, val); 1315 1316 /* 1317 * 802.3x flow control 1318 */ 1319 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1320 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1321 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1322 } else { 1323 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1324 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1325 } 1326 1327 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1328 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1329 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1330 } else { 1331 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1332 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1333 } 1334 1335 /* Only make changes if the recive mode has actually changed. */ 1336 if (rx_mode != sc->rx_mode) { 1337 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1338 rx_mode); 1339 1340 sc->rx_mode = rx_mode; 1341 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1342 1343 bnx_init_rx_context(sc); 1344 } 1345 } 1346 1347 /****************************************************************************/ 1348 /* Acquire NVRAM lock. */ 1349 /* */ 1350 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1351 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1352 /* for use by the driver. */ 1353 /* */ 1354 /* Returns: */ 1355 /* 0 on success, positive value on failure. */ 1356 /****************************************************************************/ 1357 int 1358 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1359 { 1360 uint32_t val; 1361 int j; 1362 1363 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1364 1365 /* Request access to the flash interface. */ 1366 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1367 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1368 val = REG_RD(sc, BNX_NVM_SW_ARB); 1369 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1370 break; 1371 1372 DELAY(5); 1373 } 1374 1375 if (j >= NVRAM_TIMEOUT_COUNT) { 1376 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1377 return EBUSY; 1378 } 1379 1380 return 0; 1381 } 1382 1383 /****************************************************************************/ 1384 /* Release NVRAM lock. */ 1385 /* */ 1386 /* When the caller is finished accessing NVRAM the lock must be released. */ 1387 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1388 /* for use by the driver. */ 1389 /* */ 1390 /* Returns: */ 1391 /* 0 on success, positive value on failure. */ 1392 /****************************************************************************/ 1393 int 1394 bnx_release_nvram_lock(struct bnx_softc *sc) 1395 { 1396 int j; 1397 uint32_t val; 1398 1399 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1400 1401 /* Relinquish nvram interface. */ 1402 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1403 1404 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1405 val = REG_RD(sc, BNX_NVM_SW_ARB); 1406 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1407 break; 1408 1409 DELAY(5); 1410 } 1411 1412 if (j >= NVRAM_TIMEOUT_COUNT) { 1413 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1414 return EBUSY; 1415 } 1416 1417 return 0; 1418 } 1419 1420 #ifdef BNX_NVRAM_WRITE_SUPPORT 1421 /****************************************************************************/ 1422 /* Enable NVRAM write access. */ 1423 /* */ 1424 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1425 /* */ 1426 /* Returns: */ 1427 /* 0 on success, positive value on failure. */ 1428 /****************************************************************************/ 1429 int 1430 bnx_enable_nvram_write(struct bnx_softc *sc) 1431 { 1432 uint32_t val; 1433 1434 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1435 1436 val = REG_RD(sc, BNX_MISC_CFG); 1437 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1438 1439 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1440 int j; 1441 1442 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1443 REG_WR(sc, BNX_NVM_COMMAND, 1444 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1445 1446 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1447 DELAY(5); 1448 1449 val = REG_RD(sc, BNX_NVM_COMMAND); 1450 if (val & BNX_NVM_COMMAND_DONE) 1451 break; 1452 } 1453 1454 if (j >= NVRAM_TIMEOUT_COUNT) { 1455 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1456 return EBUSY; 1457 } 1458 } 1459 1460 return 0; 1461 } 1462 1463 /****************************************************************************/ 1464 /* Disable NVRAM write access. */ 1465 /* */ 1466 /* When the caller is finished writing to NVRAM write access must be */ 1467 /* disabled. */ 1468 /* */ 1469 /* Returns: */ 1470 /* Nothing. */ 1471 /****************************************************************************/ 1472 void 1473 bnx_disable_nvram_write(struct bnx_softc *sc) 1474 { 1475 uint32_t val; 1476 1477 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1478 1479 val = REG_RD(sc, BNX_MISC_CFG); 1480 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1481 } 1482 #endif 1483 1484 /****************************************************************************/ 1485 /* Enable NVRAM access. */ 1486 /* */ 1487 /* Before accessing NVRAM for read or write operations the caller must */ 1488 /* enabled NVRAM access. */ 1489 /* */ 1490 /* Returns: */ 1491 /* Nothing. */ 1492 /****************************************************************************/ 1493 void 1494 bnx_enable_nvram_access(struct bnx_softc *sc) 1495 { 1496 uint32_t val; 1497 1498 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1499 1500 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1501 /* Enable both bits, even on read. */ 1502 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1503 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1504 } 1505 1506 /****************************************************************************/ 1507 /* Disable NVRAM access. */ 1508 /* */ 1509 /* When the caller is finished accessing NVRAM access must be disabled. */ 1510 /* */ 1511 /* Returns: */ 1512 /* Nothing. */ 1513 /****************************************************************************/ 1514 void 1515 bnx_disable_nvram_access(struct bnx_softc *sc) 1516 { 1517 uint32_t val; 1518 1519 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1520 1521 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1522 1523 /* Disable both bits, even after read. */ 1524 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1525 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1526 } 1527 1528 #ifdef BNX_NVRAM_WRITE_SUPPORT 1529 /****************************************************************************/ 1530 /* Erase NVRAM page before writing. */ 1531 /* */ 1532 /* Non-buffered flash parts require that a page be erased before it is */ 1533 /* written. */ 1534 /* */ 1535 /* Returns: */ 1536 /* 0 on success, positive value on failure. */ 1537 /****************************************************************************/ 1538 int 1539 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1540 { 1541 uint32_t cmd; 1542 int j; 1543 1544 /* Buffered flash doesn't require an erase. */ 1545 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1546 return 0; 1547 1548 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1549 1550 /* Build an erase command. */ 1551 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1552 BNX_NVM_COMMAND_DOIT; 1553 1554 /* 1555 * Clear the DONE bit separately, set the NVRAM address to erase, 1556 * and issue the erase command. 1557 */ 1558 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1559 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1560 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1561 1562 /* Wait for completion. */ 1563 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1564 uint32_t val; 1565 1566 DELAY(5); 1567 1568 val = REG_RD(sc, BNX_NVM_COMMAND); 1569 if (val & BNX_NVM_COMMAND_DONE) 1570 break; 1571 } 1572 1573 if (j >= NVRAM_TIMEOUT_COUNT) { 1574 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1575 return EBUSY; 1576 } 1577 1578 return 0; 1579 } 1580 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1581 1582 /****************************************************************************/ 1583 /* Read a dword (32 bits) from NVRAM. */ 1584 /* */ 1585 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1586 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1587 /* */ 1588 /* Returns: */ 1589 /* 0 on success and the 32 bit value read, positive value on failure. */ 1590 /****************************************************************************/ 1591 int 1592 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1593 uint8_t *ret_val, uint32_t cmd_flags) 1594 { 1595 uint32_t cmd; 1596 int i, rc = 0; 1597 1598 /* Build the command word. */ 1599 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1600 1601 /* Calculate the offset for buffered flash if translation is used. */ 1602 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1603 offset = ((offset / sc->bnx_flash_info->page_size) << 1604 sc->bnx_flash_info->page_bits) + 1605 (offset % sc->bnx_flash_info->page_size); 1606 } 1607 1608 /* 1609 * Clear the DONE bit separately, set the address to read, 1610 * and issue the read. 1611 */ 1612 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1613 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1614 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1615 1616 /* Wait for completion. */ 1617 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1618 uint32_t val; 1619 1620 DELAY(5); 1621 1622 val = REG_RD(sc, BNX_NVM_COMMAND); 1623 if (val & BNX_NVM_COMMAND_DONE) { 1624 val = REG_RD(sc, BNX_NVM_READ); 1625 1626 val = be32toh(val); 1627 memcpy(ret_val, &val, 4); 1628 break; 1629 } 1630 } 1631 1632 /* Check for errors. */ 1633 if (i >= NVRAM_TIMEOUT_COUNT) { 1634 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1635 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1636 rc = EBUSY; 1637 } 1638 1639 return rc; 1640 } 1641 1642 #ifdef BNX_NVRAM_WRITE_SUPPORT 1643 /****************************************************************************/ 1644 /* Write a dword (32 bits) to NVRAM. */ 1645 /* */ 1646 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1647 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1648 /* enabled NVRAM write access. */ 1649 /* */ 1650 /* Returns: */ 1651 /* 0 on success, positive value on failure. */ 1652 /****************************************************************************/ 1653 int 1654 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1655 uint32_t cmd_flags) 1656 { 1657 uint32_t cmd, val32; 1658 int j; 1659 1660 /* Build the command word. */ 1661 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1662 1663 /* Calculate the offset for buffered flash if translation is used. */ 1664 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1665 offset = ((offset / sc->bnx_flash_info->page_size) << 1666 sc->bnx_flash_info->page_bits) + 1667 (offset % sc->bnx_flash_info->page_size); 1668 } 1669 1670 /* 1671 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1672 * set the NVRAM address to write, and issue the write command 1673 */ 1674 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1675 memcpy(&val32, val, 4); 1676 val32 = htobe32(val32); 1677 REG_WR(sc, BNX_NVM_WRITE, val32); 1678 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1679 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1680 1681 /* Wait for completion. */ 1682 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1683 DELAY(5); 1684 1685 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1686 break; 1687 } 1688 if (j >= NVRAM_TIMEOUT_COUNT) { 1689 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1690 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1691 return EBUSY; 1692 } 1693 1694 return 0; 1695 } 1696 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1697 1698 /****************************************************************************/ 1699 /* Initialize NVRAM access. */ 1700 /* */ 1701 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1702 /* access that device. */ 1703 /* */ 1704 /* Returns: */ 1705 /* 0 on success, positive value on failure. */ 1706 /****************************************************************************/ 1707 int 1708 bnx_init_nvram(struct bnx_softc *sc) 1709 { 1710 uint32_t val; 1711 int j, entry_count, rc = 0; 1712 struct flash_spec *flash; 1713 1714 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1715 1716 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1717 sc->bnx_flash_info = &flash_5709; 1718 goto bnx_init_nvram_get_flash_size; 1719 } 1720 1721 /* Determine the selected interface. */ 1722 val = REG_RD(sc, BNX_NVM_CFG1); 1723 1724 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1725 1726 /* 1727 * Flash reconfiguration is required to support additional 1728 * NVRAM devices not directly supported in hardware. 1729 * Check if the flash interface was reconfigured 1730 * by the bootcode. 1731 */ 1732 1733 if (val & 0x40000000) { 1734 /* Flash interface reconfigured by bootcode. */ 1735 1736 DBPRINT(sc,BNX_INFO_LOAD, 1737 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1738 1739 for (j = 0, flash = &flash_table[0]; j < entry_count; 1740 j++, flash++) { 1741 if ((val & FLASH_BACKUP_STRAP_MASK) == 1742 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1743 sc->bnx_flash_info = flash; 1744 break; 1745 } 1746 } 1747 } else { 1748 /* Flash interface not yet reconfigured. */ 1749 uint32_t mask; 1750 1751 DBPRINT(sc,BNX_INFO_LOAD, 1752 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1753 1754 if (val & (1 << 23)) 1755 mask = FLASH_BACKUP_STRAP_MASK; 1756 else 1757 mask = FLASH_STRAP_MASK; 1758 1759 /* Look for the matching NVRAM device configuration data. */ 1760 for (j = 0, flash = &flash_table[0]; j < entry_count; 1761 j++, flash++) { 1762 /* Check if the dev matches any of the known devices. */ 1763 if ((val & mask) == (flash->strapping & mask)) { 1764 /* Found a device match. */ 1765 sc->bnx_flash_info = flash; 1766 1767 /* Request access to the flash interface. */ 1768 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1769 return rc; 1770 1771 /* Reconfigure the flash interface. */ 1772 bnx_enable_nvram_access(sc); 1773 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1774 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1775 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1776 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1777 bnx_disable_nvram_access(sc); 1778 bnx_release_nvram_lock(sc); 1779 1780 break; 1781 } 1782 } 1783 } 1784 1785 /* Check if a matching device was found. */ 1786 if (j == entry_count) { 1787 sc->bnx_flash_info = NULL; 1788 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1789 __FILE__, __LINE__); 1790 rc = ENODEV; 1791 } 1792 1793 bnx_init_nvram_get_flash_size: 1794 /* Write the flash config data to the shared memory interface. */ 1795 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1796 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1797 if (val) 1798 sc->bnx_flash_size = val; 1799 else 1800 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1801 1802 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1803 "0x%08X\n", sc->bnx_flash_info->total_size); 1804 1805 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1806 1807 return rc; 1808 } 1809 1810 /****************************************************************************/ 1811 /* Read an arbitrary range of data from NVRAM. */ 1812 /* */ 1813 /* Prepares the NVRAM interface for access and reads the requested data */ 1814 /* into the supplied buffer. */ 1815 /* */ 1816 /* Returns: */ 1817 /* 0 on success and the data read, positive value on failure. */ 1818 /****************************************************************************/ 1819 int 1820 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1821 int buf_size) 1822 { 1823 int rc = 0; 1824 uint32_t cmd_flags, offset32, len32, extra; 1825 1826 if (buf_size == 0) 1827 return 0; 1828 1829 /* Request access to the flash interface. */ 1830 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1831 return rc; 1832 1833 /* Enable access to flash interface */ 1834 bnx_enable_nvram_access(sc); 1835 1836 len32 = buf_size; 1837 offset32 = offset; 1838 extra = 0; 1839 1840 cmd_flags = 0; 1841 1842 if (offset32 & 3) { 1843 uint8_t buf[4]; 1844 uint32_t pre_len; 1845 1846 offset32 &= ~3; 1847 pre_len = 4 - (offset & 3); 1848 1849 if (pre_len >= len32) { 1850 pre_len = len32; 1851 cmd_flags = 1852 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1853 } else 1854 cmd_flags = BNX_NVM_COMMAND_FIRST; 1855 1856 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1857 1858 if (rc) 1859 return rc; 1860 1861 memcpy(ret_buf, buf + (offset & 3), pre_len); 1862 1863 offset32 += 4; 1864 ret_buf += pre_len; 1865 len32 -= pre_len; 1866 } 1867 1868 if (len32 & 3) { 1869 extra = 4 - (len32 & 3); 1870 len32 = (len32 + 4) & ~3; 1871 } 1872 1873 if (len32 == 4) { 1874 uint8_t buf[4]; 1875 1876 if (cmd_flags) 1877 cmd_flags = BNX_NVM_COMMAND_LAST; 1878 else 1879 cmd_flags = 1880 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1881 1882 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1883 1884 memcpy(ret_buf, buf, 4 - extra); 1885 } else if (len32 > 0) { 1886 uint8_t buf[4]; 1887 1888 /* Read the first word. */ 1889 if (cmd_flags) 1890 cmd_flags = 0; 1891 else 1892 cmd_flags = BNX_NVM_COMMAND_FIRST; 1893 1894 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1895 1896 /* Advance to the next dword. */ 1897 offset32 += 4; 1898 ret_buf += 4; 1899 len32 -= 4; 1900 1901 while (len32 > 4 && rc == 0) { 1902 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1903 1904 /* Advance to the next dword. */ 1905 offset32 += 4; 1906 ret_buf += 4; 1907 len32 -= 4; 1908 } 1909 1910 if (rc) 1911 return rc; 1912 1913 cmd_flags = BNX_NVM_COMMAND_LAST; 1914 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1915 1916 memcpy(ret_buf, buf, 4 - extra); 1917 } 1918 1919 /* Disable access to flash interface and release the lock. */ 1920 bnx_disable_nvram_access(sc); 1921 bnx_release_nvram_lock(sc); 1922 1923 return rc; 1924 } 1925 1926 #ifdef BNX_NVRAM_WRITE_SUPPORT 1927 /****************************************************************************/ 1928 /* Write an arbitrary range of data from NVRAM. */ 1929 /* */ 1930 /* Prepares the NVRAM interface for write access and writes the requested */ 1931 /* data from the supplied buffer. The caller is responsible for */ 1932 /* calculating any appropriate CRCs. */ 1933 /* */ 1934 /* Returns: */ 1935 /* 0 on success, positive value on failure. */ 1936 /****************************************************************************/ 1937 int 1938 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1939 int buf_size) 1940 { 1941 uint32_t written, offset32, len32; 1942 uint8_t *buf, start[4], end[4]; 1943 int rc = 0; 1944 int align_start, align_end; 1945 1946 buf = data_buf; 1947 offset32 = offset; 1948 len32 = buf_size; 1949 align_start = align_end = 0; 1950 1951 if ((align_start = (offset32 & 3))) { 1952 offset32 &= ~3; 1953 len32 += align_start; 1954 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1955 return rc; 1956 } 1957 1958 if (len32 & 3) { 1959 if ((len32 > 4) || !align_start) { 1960 align_end = 4 - (len32 & 3); 1961 len32 += align_end; 1962 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1963 end, 4))) 1964 return rc; 1965 } 1966 } 1967 1968 if (align_start || align_end) { 1969 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1970 if (buf == NULL) 1971 return ENOMEM; 1972 1973 if (align_start) 1974 memcpy(buf, start, 4); 1975 1976 if (align_end) 1977 memcpy(buf + len32 - 4, end, 4); 1978 1979 memcpy(buf + align_start, data_buf, buf_size); 1980 } 1981 1982 written = 0; 1983 while ((written < len32) && (rc == 0)) { 1984 uint32_t page_start, page_end, data_start, data_end; 1985 uint32_t addr, cmd_flags; 1986 int i; 1987 uint8_t flash_buffer[264]; 1988 1989 /* Find the page_start addr */ 1990 page_start = offset32 + written; 1991 page_start -= (page_start % sc->bnx_flash_info->page_size); 1992 /* Find the page_end addr */ 1993 page_end = page_start + sc->bnx_flash_info->page_size; 1994 /* Find the data_start addr */ 1995 data_start = (written == 0) ? offset32 : page_start; 1996 /* Find the data_end addr */ 1997 data_end = (page_end > offset32 + len32) ? 1998 (offset32 + len32) : page_end; 1999 2000 /* Request access to the flash interface. */ 2001 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 2002 goto nvram_write_end; 2003 2004 /* Enable access to flash interface */ 2005 bnx_enable_nvram_access(sc); 2006 2007 cmd_flags = BNX_NVM_COMMAND_FIRST; 2008 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2009 int j; 2010 2011 /* Read the whole page into the buffer 2012 * (non-buffer flash only) */ 2013 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 2014 if (j == (sc->bnx_flash_info->page_size - 4)) 2015 cmd_flags |= BNX_NVM_COMMAND_LAST; 2016 2017 rc = bnx_nvram_read_dword(sc, 2018 page_start + j, 2019 &flash_buffer[j], 2020 cmd_flags); 2021 2022 if (rc) 2023 goto nvram_write_end; 2024 2025 cmd_flags = 0; 2026 } 2027 } 2028 2029 /* Enable writes to flash interface (unlock write-protect) */ 2030 if ((rc = bnx_enable_nvram_write(sc)) != 0) 2031 goto nvram_write_end; 2032 2033 /* Erase the page */ 2034 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 2035 goto nvram_write_end; 2036 2037 /* Re-enable the write again for the actual write */ 2038 bnx_enable_nvram_write(sc); 2039 2040 /* Loop to write back the buffer data from page_start to 2041 * data_start */ 2042 i = 0; 2043 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2044 for (addr = page_start; addr < data_start; 2045 addr += 4, i += 4) { 2046 2047 rc = bnx_nvram_write_dword(sc, addr, 2048 &flash_buffer[i], cmd_flags); 2049 2050 if (rc != 0) 2051 goto nvram_write_end; 2052 2053 cmd_flags = 0; 2054 } 2055 } 2056 2057 /* Loop to write the new data from data_start to data_end */ 2058 for (addr = data_start; addr < data_end; addr += 4, i++) { 2059 if ((addr == page_end - 4) || 2060 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 2061 && (addr == data_end - 4))) { 2062 2063 cmd_flags |= BNX_NVM_COMMAND_LAST; 2064 } 2065 2066 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2067 2068 if (rc != 0) 2069 goto nvram_write_end; 2070 2071 cmd_flags = 0; 2072 buf += 4; 2073 } 2074 2075 /* Loop to write back the buffer data from data_end 2076 * to page_end */ 2077 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2078 for (addr = data_end; addr < page_end; 2079 addr += 4, i += 4) { 2080 2081 if (addr == page_end-4) 2082 cmd_flags = BNX_NVM_COMMAND_LAST; 2083 2084 rc = bnx_nvram_write_dword(sc, addr, 2085 &flash_buffer[i], cmd_flags); 2086 2087 if (rc != 0) 2088 goto nvram_write_end; 2089 2090 cmd_flags = 0; 2091 } 2092 } 2093 2094 /* Disable writes to flash interface (lock write-protect) */ 2095 bnx_disable_nvram_write(sc); 2096 2097 /* Disable access to flash interface */ 2098 bnx_disable_nvram_access(sc); 2099 bnx_release_nvram_lock(sc); 2100 2101 /* Increment written */ 2102 written += data_end - data_start; 2103 } 2104 2105 nvram_write_end: 2106 if (align_start || align_end) 2107 free(buf, M_DEVBUF); 2108 2109 return rc; 2110 } 2111 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2112 2113 /****************************************************************************/ 2114 /* Verifies that NVRAM is accessible and contains valid data. */ 2115 /* */ 2116 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2117 /* correct. */ 2118 /* */ 2119 /* Returns: */ 2120 /* 0 on success, positive value on failure. */ 2121 /****************************************************************************/ 2122 int 2123 bnx_nvram_test(struct bnx_softc *sc) 2124 { 2125 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2126 uint8_t *data = (uint8_t *) buf; 2127 int rc = 0; 2128 uint32_t magic, csum; 2129 2130 /* 2131 * Check that the device NVRAM is valid by reading 2132 * the magic value at offset 0. 2133 */ 2134 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2135 goto bnx_nvram_test_done; 2136 2137 magic = be32toh(buf[0]); 2138 if (magic != BNX_NVRAM_MAGIC) { 2139 rc = ENODEV; 2140 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2141 "Expected: 0x%08X, Found: 0x%08X\n", 2142 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2143 goto bnx_nvram_test_done; 2144 } 2145 2146 /* 2147 * Verify that the device NVRAM includes valid 2148 * configuration data. 2149 */ 2150 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2151 goto bnx_nvram_test_done; 2152 2153 csum = ether_crc32_le(data, 0x100); 2154 if (csum != BNX_CRC32_RESIDUAL) { 2155 rc = ENODEV; 2156 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2157 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2158 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2159 goto bnx_nvram_test_done; 2160 } 2161 2162 csum = ether_crc32_le(data + 0x100, 0x100); 2163 if (csum != BNX_CRC32_RESIDUAL) { 2164 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2165 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2166 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2167 rc = ENODEV; 2168 } 2169 2170 bnx_nvram_test_done: 2171 return rc; 2172 } 2173 2174 /****************************************************************************/ 2175 /* Identifies the current media type of the controller and sets the PHY */ 2176 /* address. */ 2177 /* */ 2178 /* Returns: */ 2179 /* Nothing. */ 2180 /****************************************************************************/ 2181 void 2182 bnx_get_media(struct bnx_softc *sc) 2183 { 2184 sc->bnx_phy_addr = 1; 2185 2186 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2187 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2188 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2189 uint32_t strap; 2190 2191 /* 2192 * The BCM5709S is software configurable 2193 * for Copper or SerDes operation. 2194 */ 2195 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2196 DBPRINT(sc, BNX_INFO_LOAD, 2197 "5709 bonded for copper.\n"); 2198 goto bnx_get_media_exit; 2199 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2200 DBPRINT(sc, BNX_INFO_LOAD, 2201 "5709 bonded for dual media.\n"); 2202 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2203 goto bnx_get_media_exit; 2204 } 2205 2206 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2207 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2208 else { 2209 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2210 >> 8; 2211 } 2212 2213 if (sc->bnx_pa.pa_function == 0) { 2214 switch (strap) { 2215 case 0x4: 2216 case 0x5: 2217 case 0x6: 2218 DBPRINT(sc, BNX_INFO_LOAD, 2219 "BCM5709 s/w configured for SerDes.\n"); 2220 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2221 break; 2222 default: 2223 DBPRINT(sc, BNX_INFO_LOAD, 2224 "BCM5709 s/w configured for Copper.\n"); 2225 } 2226 } else { 2227 switch (strap) { 2228 case 0x1: 2229 case 0x2: 2230 case 0x4: 2231 DBPRINT(sc, BNX_INFO_LOAD, 2232 "BCM5709 s/w configured for SerDes.\n"); 2233 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2234 break; 2235 default: 2236 DBPRINT(sc, BNX_INFO_LOAD, 2237 "BCM5709 s/w configured for Copper.\n"); 2238 } 2239 } 2240 2241 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2242 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2243 2244 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2245 uint32_t val; 2246 2247 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2248 2249 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2250 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2251 2252 /* 2253 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2254 * separate PHY for SerDes. 2255 */ 2256 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2257 sc->bnx_phy_addr = 2; 2258 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2259 BNX_SHARED_HW_CFG_CONFIG); 2260 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2261 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2262 DBPRINT(sc, BNX_INFO_LOAD, 2263 "Found 2.5Gb capable adapter\n"); 2264 } 2265 } 2266 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2267 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2268 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2269 2270 bnx_get_media_exit: 2271 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2272 "Using PHY address %d.\n", sc->bnx_phy_addr); 2273 } 2274 2275 /****************************************************************************/ 2276 /* Performs PHY initialization required before MII drivers access the */ 2277 /* device. */ 2278 /* */ 2279 /* Returns: */ 2280 /* Nothing. */ 2281 /****************************************************************************/ 2282 void 2283 bnx_init_media(struct bnx_softc *sc) 2284 { 2285 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2286 /* 2287 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2288 * IEEE Clause 22 method. Otherwise we have no way to attach 2289 * the PHY to the mii(4) layer. PHY specific configuration 2290 * is done by the mii(4) layer. 2291 */ 2292 2293 /* Select auto-negotiation MMD of the PHY. */ 2294 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2295 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2296 2297 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2298 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2299 2300 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2301 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2302 } 2303 } 2304 2305 /****************************************************************************/ 2306 /* Free any DMA memory owned by the driver. */ 2307 /* */ 2308 /* Scans through each data structre that requires DMA memory and frees */ 2309 /* the memory if allocated. */ 2310 /* */ 2311 /* Returns: */ 2312 /* Nothing. */ 2313 /****************************************************************************/ 2314 void 2315 bnx_dma_free(struct bnx_softc *sc) 2316 { 2317 int i; 2318 2319 DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2320 2321 /* Destroy the status block. */ 2322 if (sc->status_block != NULL && sc->status_map != NULL) { 2323 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2324 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2325 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2326 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2327 BNX_STATUS_BLK_SZ); 2328 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2329 sc->status_rseg); 2330 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2331 sc->status_block = NULL; 2332 sc->status_map = NULL; 2333 } 2334 2335 /* Destroy the statistics block. */ 2336 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2337 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2338 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2339 BNX_STATS_BLK_SZ); 2340 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2341 sc->stats_rseg); 2342 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2343 sc->stats_block = NULL; 2344 sc->stats_map = NULL; 2345 } 2346 2347 /* Free, unmap and destroy all context memory pages. */ 2348 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2349 for (i = 0; i < sc->ctx_pages; i++) { 2350 if (sc->ctx_block[i] != NULL) { 2351 bus_dmamap_unload(sc->bnx_dmatag, 2352 sc->ctx_map[i]); 2353 bus_dmamem_unmap(sc->bnx_dmatag, 2354 (void *)sc->ctx_block[i], 2355 BCM_PAGE_SIZE); 2356 bus_dmamem_free(sc->bnx_dmatag, 2357 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2358 bus_dmamap_destroy(sc->bnx_dmatag, 2359 sc->ctx_map[i]); 2360 sc->ctx_block[i] = NULL; 2361 } 2362 } 2363 } 2364 2365 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2366 for (i = 0; i < TX_PAGES; i++ ) { 2367 if (sc->tx_bd_chain[i] != NULL && 2368 sc->tx_bd_chain_map[i] != NULL) { 2369 bus_dmamap_unload(sc->bnx_dmatag, 2370 sc->tx_bd_chain_map[i]); 2371 bus_dmamem_unmap(sc->bnx_dmatag, 2372 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2373 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2374 sc->tx_bd_chain_rseg[i]); 2375 bus_dmamap_destroy(sc->bnx_dmatag, 2376 sc->tx_bd_chain_map[i]); 2377 sc->tx_bd_chain[i] = NULL; 2378 sc->tx_bd_chain_map[i] = NULL; 2379 } 2380 } 2381 2382 /* Destroy the TX dmamaps. */ 2383 /* This isn't necessary since we dont allocate them up front */ 2384 2385 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2386 for (i = 0; i < RX_PAGES; i++ ) { 2387 if (sc->rx_bd_chain[i] != NULL && 2388 sc->rx_bd_chain_map[i] != NULL) { 2389 bus_dmamap_unload(sc->bnx_dmatag, 2390 sc->rx_bd_chain_map[i]); 2391 bus_dmamem_unmap(sc->bnx_dmatag, 2392 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2393 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2394 sc->rx_bd_chain_rseg[i]); 2395 2396 bus_dmamap_destroy(sc->bnx_dmatag, 2397 sc->rx_bd_chain_map[i]); 2398 sc->rx_bd_chain[i] = NULL; 2399 sc->rx_bd_chain_map[i] = NULL; 2400 } 2401 } 2402 2403 /* Unload and destroy the RX mbuf maps. */ 2404 for (i = 0; i < TOTAL_RX_BD; i++) { 2405 if (sc->rx_mbuf_map[i] != NULL) { 2406 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2407 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2408 } 2409 } 2410 2411 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2412 } 2413 2414 /****************************************************************************/ 2415 /* Allocate any DMA memory needed by the driver. */ 2416 /* */ 2417 /* Allocates DMA memory needed for the various global structures needed by */ 2418 /* hardware. */ 2419 /* */ 2420 /* Returns: */ 2421 /* 0 for success, positive value for failure. */ 2422 /****************************************************************************/ 2423 int 2424 bnx_dma_alloc(struct bnx_softc *sc) 2425 { 2426 int i, rc = 0; 2427 2428 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2429 2430 /* 2431 * Allocate DMA memory for the status block, map the memory into DMA 2432 * space, and fetch the physical address of the block. 2433 */ 2434 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2435 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2436 aprint_error_dev(sc->bnx_dev, 2437 "Could not create status block DMA map!\n"); 2438 rc = ENOMEM; 2439 goto bnx_dma_alloc_exit; 2440 } 2441 2442 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2443 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2444 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2445 aprint_error_dev(sc->bnx_dev, 2446 "Could not allocate status block DMA memory!\n"); 2447 rc = ENOMEM; 2448 goto bnx_dma_alloc_exit; 2449 } 2450 2451 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2452 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2453 aprint_error_dev(sc->bnx_dev, 2454 "Could not map status block DMA memory!\n"); 2455 rc = ENOMEM; 2456 goto bnx_dma_alloc_exit; 2457 } 2458 2459 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2460 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2461 aprint_error_dev(sc->bnx_dev, 2462 "Could not load status block DMA memory!\n"); 2463 rc = ENOMEM; 2464 goto bnx_dma_alloc_exit; 2465 } 2466 2467 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2468 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2469 2470 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2471 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2472 2473 /* DRC - Fix for 64 bit addresses. */ 2474 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2475 (uint32_t) sc->status_block_paddr); 2476 2477 /* BCM5709 uses host memory as cache for context memory. */ 2478 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2479 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2480 if (sc->ctx_pages == 0) 2481 sc->ctx_pages = 1; 2482 if (sc->ctx_pages > 4) /* XXX */ 2483 sc->ctx_pages = 4; 2484 2485 DBRUNIF((sc->ctx_pages > 512), 2486 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2487 __FILE__, __LINE__, sc->ctx_pages)); 2488 2489 2490 for (i = 0; i < sc->ctx_pages; i++) { 2491 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2492 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2493 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2494 &sc->ctx_map[i]) != 0) { 2495 rc = ENOMEM; 2496 goto bnx_dma_alloc_exit; 2497 } 2498 2499 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2500 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2501 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2502 rc = ENOMEM; 2503 goto bnx_dma_alloc_exit; 2504 } 2505 2506 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2507 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2508 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2509 rc = ENOMEM; 2510 goto bnx_dma_alloc_exit; 2511 } 2512 2513 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2514 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2515 BUS_DMA_NOWAIT) != 0) { 2516 rc = ENOMEM; 2517 goto bnx_dma_alloc_exit; 2518 } 2519 2520 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2521 } 2522 } 2523 2524 /* 2525 * Allocate DMA memory for the statistics block, map the memory into 2526 * DMA space, and fetch the physical address of the block. 2527 */ 2528 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2529 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2530 aprint_error_dev(sc->bnx_dev, 2531 "Could not create stats block DMA map!\n"); 2532 rc = ENOMEM; 2533 goto bnx_dma_alloc_exit; 2534 } 2535 2536 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2537 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2538 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2539 aprint_error_dev(sc->bnx_dev, 2540 "Could not allocate stats block DMA memory!\n"); 2541 rc = ENOMEM; 2542 goto bnx_dma_alloc_exit; 2543 } 2544 2545 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2546 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2547 aprint_error_dev(sc->bnx_dev, 2548 "Could not map stats block DMA memory!\n"); 2549 rc = ENOMEM; 2550 goto bnx_dma_alloc_exit; 2551 } 2552 2553 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2554 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2555 aprint_error_dev(sc->bnx_dev, 2556 "Could not load status block DMA memory!\n"); 2557 rc = ENOMEM; 2558 goto bnx_dma_alloc_exit; 2559 } 2560 2561 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2562 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2563 2564 /* DRC - Fix for 64 bit address. */ 2565 DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", 2566 (uint32_t) sc->stats_block_paddr); 2567 2568 /* 2569 * Allocate DMA memory for the TX buffer descriptor chain, 2570 * and fetch the physical address of the block. 2571 */ 2572 for (i = 0; i < TX_PAGES; i++) { 2573 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2574 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2575 &sc->tx_bd_chain_map[i])) { 2576 aprint_error_dev(sc->bnx_dev, 2577 "Could not create Tx desc %d DMA map!\n", i); 2578 rc = ENOMEM; 2579 goto bnx_dma_alloc_exit; 2580 } 2581 2582 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2583 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2584 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2585 aprint_error_dev(sc->bnx_dev, 2586 "Could not allocate TX desc %d DMA memory!\n", 2587 i); 2588 rc = ENOMEM; 2589 goto bnx_dma_alloc_exit; 2590 } 2591 2592 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2593 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2594 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2595 aprint_error_dev(sc->bnx_dev, 2596 "Could not map TX desc %d DMA memory!\n", i); 2597 rc = ENOMEM; 2598 goto bnx_dma_alloc_exit; 2599 } 2600 2601 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2602 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2603 BUS_DMA_NOWAIT)) { 2604 aprint_error_dev(sc->bnx_dev, 2605 "Could not load TX desc %d DMA memory!\n", i); 2606 rc = ENOMEM; 2607 goto bnx_dma_alloc_exit; 2608 } 2609 2610 sc->tx_bd_chain_paddr[i] = 2611 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2612 2613 /* DRC - Fix for 64 bit systems. */ 2614 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2615 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2616 } 2617 2618 /* 2619 * Create lists to hold TX mbufs. 2620 */ 2621 TAILQ_INIT(&sc->tx_free_pkts); 2622 TAILQ_INIT(&sc->tx_used_pkts); 2623 sc->tx_pkt_count = 0; 2624 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2625 2626 /* 2627 * Allocate DMA memory for the Rx buffer descriptor chain, 2628 * and fetch the physical address of the block. 2629 */ 2630 for (i = 0; i < RX_PAGES; i++) { 2631 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2632 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2633 &sc->rx_bd_chain_map[i])) { 2634 aprint_error_dev(sc->bnx_dev, 2635 "Could not create Rx desc %d DMA map!\n", i); 2636 rc = ENOMEM; 2637 goto bnx_dma_alloc_exit; 2638 } 2639 2640 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2641 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2642 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2643 aprint_error_dev(sc->bnx_dev, 2644 "Could not allocate Rx desc %d DMA memory!\n", i); 2645 rc = ENOMEM; 2646 goto bnx_dma_alloc_exit; 2647 } 2648 2649 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2650 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2651 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2652 aprint_error_dev(sc->bnx_dev, 2653 "Could not map Rx desc %d DMA memory!\n", i); 2654 rc = ENOMEM; 2655 goto bnx_dma_alloc_exit; 2656 } 2657 2658 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2659 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2660 BUS_DMA_NOWAIT)) { 2661 aprint_error_dev(sc->bnx_dev, 2662 "Could not load Rx desc %d DMA memory!\n", i); 2663 rc = ENOMEM; 2664 goto bnx_dma_alloc_exit; 2665 } 2666 2667 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2668 sc->rx_bd_chain_paddr[i] = 2669 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2670 2671 /* DRC - Fix for 64 bit systems. */ 2672 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2673 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2674 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2675 0, BNX_RX_CHAIN_PAGE_SZ, 2676 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2677 } 2678 2679 /* 2680 * Create DMA maps for the Rx buffer mbufs. 2681 */ 2682 for (i = 0; i < TOTAL_RX_BD; i++) { 2683 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2684 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2685 &sc->rx_mbuf_map[i])) { 2686 aprint_error_dev(sc->bnx_dev, 2687 "Could not create Rx mbuf %d DMA map!\n", i); 2688 rc = ENOMEM; 2689 goto bnx_dma_alloc_exit; 2690 } 2691 } 2692 2693 bnx_dma_alloc_exit: 2694 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2695 2696 return rc; 2697 } 2698 2699 /****************************************************************************/ 2700 /* Release all resources used by the driver. */ 2701 /* */ 2702 /* Releases all resources acquired by the driver including interrupts, */ 2703 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2704 /* */ 2705 /* Returns: */ 2706 /* Nothing. */ 2707 /****************************************************************************/ 2708 void 2709 bnx_release_resources(struct bnx_softc *sc) 2710 { 2711 struct pci_attach_args *pa = &(sc->bnx_pa); 2712 2713 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2714 2715 bnx_dma_free(sc); 2716 2717 if (sc->bnx_intrhand != NULL) 2718 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2719 2720 if (sc->bnx_size) 2721 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2722 2723 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2724 } 2725 2726 /****************************************************************************/ 2727 /* Firmware synchronization. */ 2728 /* */ 2729 /* Before performing certain events such as a chip reset, synchronize with */ 2730 /* the firmware first. */ 2731 /* */ 2732 /* Returns: */ 2733 /* 0 for success, positive value for failure. */ 2734 /****************************************************************************/ 2735 int 2736 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2737 { 2738 int i, rc = 0; 2739 uint32_t val; 2740 2741 /* Don't waste any time if we've timed out before. */ 2742 if (sc->bnx_fw_timed_out) { 2743 rc = EBUSY; 2744 goto bnx_fw_sync_exit; 2745 } 2746 2747 /* Increment the message sequence number. */ 2748 sc->bnx_fw_wr_seq++; 2749 msg_data |= sc->bnx_fw_wr_seq; 2750 2751 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2752 msg_data); 2753 2754 /* Send the message to the bootcode driver mailbox. */ 2755 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2756 2757 /* Wait for the bootcode to acknowledge the message. */ 2758 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2759 /* Check for a response in the bootcode firmware mailbox. */ 2760 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2761 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2762 break; 2763 DELAY(1000); 2764 } 2765 2766 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2767 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2768 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2769 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2770 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2771 2772 msg_data &= ~BNX_DRV_MSG_CODE; 2773 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2774 2775 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2776 2777 sc->bnx_fw_timed_out = 1; 2778 rc = EBUSY; 2779 } 2780 2781 bnx_fw_sync_exit: 2782 return rc; 2783 } 2784 2785 /****************************************************************************/ 2786 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2787 /* */ 2788 /* Returns: */ 2789 /* Nothing. */ 2790 /****************************************************************************/ 2791 void 2792 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2793 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2794 { 2795 int i; 2796 uint32_t val; 2797 2798 /* Set the page size used by RV2P. */ 2799 if (rv2p_proc == RV2P_PROC2) { 2800 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2801 USABLE_RX_BD_PER_PAGE); 2802 } 2803 2804 for (i = 0; i < rv2p_code_len; i += 8) { 2805 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2806 rv2p_code++; 2807 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2808 rv2p_code++; 2809 2810 if (rv2p_proc == RV2P_PROC1) { 2811 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2812 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2813 } else { 2814 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2815 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2816 } 2817 } 2818 2819 /* Reset the processor, un-stall is done later. */ 2820 if (rv2p_proc == RV2P_PROC1) 2821 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2822 else 2823 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2824 } 2825 2826 /****************************************************************************/ 2827 /* Load RISC processor firmware. */ 2828 /* */ 2829 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2830 /* associated with a particular processor. */ 2831 /* */ 2832 /* Returns: */ 2833 /* Nothing. */ 2834 /****************************************************************************/ 2835 void 2836 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2837 struct fw_info *fw) 2838 { 2839 uint32_t offset; 2840 uint32_t val; 2841 2842 /* Halt the CPU. */ 2843 val = REG_RD_IND(sc, cpu_reg->mode); 2844 val |= cpu_reg->mode_value_halt; 2845 REG_WR_IND(sc, cpu_reg->mode, val); 2846 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2847 2848 /* Load the Text area. */ 2849 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2850 if (fw->text) { 2851 int j; 2852 2853 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2854 REG_WR_IND(sc, offset, fw->text[j]); 2855 } 2856 2857 /* Load the Data area. */ 2858 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2859 if (fw->data) { 2860 int j; 2861 2862 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2863 REG_WR_IND(sc, offset, fw->data[j]); 2864 } 2865 2866 /* Load the SBSS area. */ 2867 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2868 if (fw->sbss) { 2869 int j; 2870 2871 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2872 REG_WR_IND(sc, offset, fw->sbss[j]); 2873 } 2874 2875 /* Load the BSS area. */ 2876 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2877 if (fw->bss) { 2878 int j; 2879 2880 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2881 REG_WR_IND(sc, offset, fw->bss[j]); 2882 } 2883 2884 /* Load the Read-Only area. */ 2885 offset = cpu_reg->spad_base + 2886 (fw->rodata_addr - cpu_reg->mips_view_base); 2887 if (fw->rodata) { 2888 int j; 2889 2890 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2891 REG_WR_IND(sc, offset, fw->rodata[j]); 2892 } 2893 2894 /* Clear the pre-fetch instruction. */ 2895 REG_WR_IND(sc, cpu_reg->inst, 0); 2896 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2897 2898 /* Start the CPU. */ 2899 val = REG_RD_IND(sc, cpu_reg->mode); 2900 val &= ~cpu_reg->mode_value_halt; 2901 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2902 REG_WR_IND(sc, cpu_reg->mode, val); 2903 } 2904 2905 /****************************************************************************/ 2906 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2907 /* */ 2908 /* Loads the firmware for each CPU and starts the CPU. */ 2909 /* */ 2910 /* Returns: */ 2911 /* Nothing. */ 2912 /****************************************************************************/ 2913 void 2914 bnx_init_cpus(struct bnx_softc *sc) 2915 { 2916 struct cpu_reg cpu_reg; 2917 struct fw_info fw; 2918 2919 switch (BNX_CHIP_NUM(sc)) { 2920 case BNX_CHIP_NUM_5709: 2921 /* Initialize the RV2P processor. */ 2922 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2923 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2924 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2925 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2926 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2927 } else { 2928 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2929 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2930 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2931 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2932 } 2933 2934 /* Initialize the RX Processor. */ 2935 cpu_reg.mode = BNX_RXP_CPU_MODE; 2936 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2937 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2938 cpu_reg.state = BNX_RXP_CPU_STATE; 2939 cpu_reg.state_value_clear = 0xffffff; 2940 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2941 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2942 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2943 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2944 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2945 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2946 cpu_reg.mips_view_base = 0x8000000; 2947 2948 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2949 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2950 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2951 fw.start_addr = bnx_RXP_b09FwStartAddr; 2952 2953 fw.text_addr = bnx_RXP_b09FwTextAddr; 2954 fw.text_len = bnx_RXP_b09FwTextLen; 2955 fw.text_index = 0; 2956 fw.text = bnx_RXP_b09FwText; 2957 2958 fw.data_addr = bnx_RXP_b09FwDataAddr; 2959 fw.data_len = bnx_RXP_b09FwDataLen; 2960 fw.data_index = 0; 2961 fw.data = bnx_RXP_b09FwData; 2962 2963 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2964 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2965 fw.sbss_index = 0; 2966 fw.sbss = bnx_RXP_b09FwSbss; 2967 2968 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2969 fw.bss_len = bnx_RXP_b09FwBssLen; 2970 fw.bss_index = 0; 2971 fw.bss = bnx_RXP_b09FwBss; 2972 2973 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2974 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2975 fw.rodata_index = 0; 2976 fw.rodata = bnx_RXP_b09FwRodata; 2977 2978 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2979 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2980 2981 /* Initialize the TX Processor. */ 2982 cpu_reg.mode = BNX_TXP_CPU_MODE; 2983 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2984 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2985 cpu_reg.state = BNX_TXP_CPU_STATE; 2986 cpu_reg.state_value_clear = 0xffffff; 2987 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2988 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2989 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2990 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2991 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2992 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2993 cpu_reg.mips_view_base = 0x8000000; 2994 2995 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2996 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2997 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2998 fw.start_addr = bnx_TXP_b09FwStartAddr; 2999 3000 fw.text_addr = bnx_TXP_b09FwTextAddr; 3001 fw.text_len = bnx_TXP_b09FwTextLen; 3002 fw.text_index = 0; 3003 fw.text = bnx_TXP_b09FwText; 3004 3005 fw.data_addr = bnx_TXP_b09FwDataAddr; 3006 fw.data_len = bnx_TXP_b09FwDataLen; 3007 fw.data_index = 0; 3008 fw.data = bnx_TXP_b09FwData; 3009 3010 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 3011 fw.sbss_len = bnx_TXP_b09FwSbssLen; 3012 fw.sbss_index = 0; 3013 fw.sbss = bnx_TXP_b09FwSbss; 3014 3015 fw.bss_addr = bnx_TXP_b09FwBssAddr; 3016 fw.bss_len = bnx_TXP_b09FwBssLen; 3017 fw.bss_index = 0; 3018 fw.bss = bnx_TXP_b09FwBss; 3019 3020 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 3021 fw.rodata_len = bnx_TXP_b09FwRodataLen; 3022 fw.rodata_index = 0; 3023 fw.rodata = bnx_TXP_b09FwRodata; 3024 3025 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3026 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3027 3028 /* Initialize the TX Patch-up Processor. */ 3029 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3030 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3031 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3032 cpu_reg.state = BNX_TPAT_CPU_STATE; 3033 cpu_reg.state_value_clear = 0xffffff; 3034 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3035 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3036 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3037 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3038 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3039 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3040 cpu_reg.mips_view_base = 0x8000000; 3041 3042 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 3043 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 3044 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 3045 fw.start_addr = bnx_TPAT_b09FwStartAddr; 3046 3047 fw.text_addr = bnx_TPAT_b09FwTextAddr; 3048 fw.text_len = bnx_TPAT_b09FwTextLen; 3049 fw.text_index = 0; 3050 fw.text = bnx_TPAT_b09FwText; 3051 3052 fw.data_addr = bnx_TPAT_b09FwDataAddr; 3053 fw.data_len = bnx_TPAT_b09FwDataLen; 3054 fw.data_index = 0; 3055 fw.data = bnx_TPAT_b09FwData; 3056 3057 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 3058 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 3059 fw.sbss_index = 0; 3060 fw.sbss = bnx_TPAT_b09FwSbss; 3061 3062 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 3063 fw.bss_len = bnx_TPAT_b09FwBssLen; 3064 fw.bss_index = 0; 3065 fw.bss = bnx_TPAT_b09FwBss; 3066 3067 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3068 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3069 fw.rodata_index = 0; 3070 fw.rodata = bnx_TPAT_b09FwRodata; 3071 3072 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3073 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3074 3075 /* Initialize the Completion Processor. */ 3076 cpu_reg.mode = BNX_COM_CPU_MODE; 3077 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3078 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3079 cpu_reg.state = BNX_COM_CPU_STATE; 3080 cpu_reg.state_value_clear = 0xffffff; 3081 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3082 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3083 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3084 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3085 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3086 cpu_reg.spad_base = BNX_COM_SCRATCH; 3087 cpu_reg.mips_view_base = 0x8000000; 3088 3089 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3090 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3091 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3092 fw.start_addr = bnx_COM_b09FwStartAddr; 3093 3094 fw.text_addr = bnx_COM_b09FwTextAddr; 3095 fw.text_len = bnx_COM_b09FwTextLen; 3096 fw.text_index = 0; 3097 fw.text = bnx_COM_b09FwText; 3098 3099 fw.data_addr = bnx_COM_b09FwDataAddr; 3100 fw.data_len = bnx_COM_b09FwDataLen; 3101 fw.data_index = 0; 3102 fw.data = bnx_COM_b09FwData; 3103 3104 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3105 fw.sbss_len = bnx_COM_b09FwSbssLen; 3106 fw.sbss_index = 0; 3107 fw.sbss = bnx_COM_b09FwSbss; 3108 3109 fw.bss_addr = bnx_COM_b09FwBssAddr; 3110 fw.bss_len = bnx_COM_b09FwBssLen; 3111 fw.bss_index = 0; 3112 fw.bss = bnx_COM_b09FwBss; 3113 3114 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3115 fw.rodata_len = bnx_COM_b09FwRodataLen; 3116 fw.rodata_index = 0; 3117 fw.rodata = bnx_COM_b09FwRodata; 3118 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3119 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3120 break; 3121 default: 3122 /* Initialize the RV2P processor. */ 3123 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3124 RV2P_PROC1); 3125 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3126 RV2P_PROC2); 3127 3128 /* Initialize the RX Processor. */ 3129 cpu_reg.mode = BNX_RXP_CPU_MODE; 3130 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3131 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3132 cpu_reg.state = BNX_RXP_CPU_STATE; 3133 cpu_reg.state_value_clear = 0xffffff; 3134 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3135 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3136 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3137 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3138 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3139 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3140 cpu_reg.mips_view_base = 0x8000000; 3141 3142 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3143 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3144 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3145 fw.start_addr = bnx_RXP_b06FwStartAddr; 3146 3147 fw.text_addr = bnx_RXP_b06FwTextAddr; 3148 fw.text_len = bnx_RXP_b06FwTextLen; 3149 fw.text_index = 0; 3150 fw.text = bnx_RXP_b06FwText; 3151 3152 fw.data_addr = bnx_RXP_b06FwDataAddr; 3153 fw.data_len = bnx_RXP_b06FwDataLen; 3154 fw.data_index = 0; 3155 fw.data = bnx_RXP_b06FwData; 3156 3157 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3158 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3159 fw.sbss_index = 0; 3160 fw.sbss = bnx_RXP_b06FwSbss; 3161 3162 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3163 fw.bss_len = bnx_RXP_b06FwBssLen; 3164 fw.bss_index = 0; 3165 fw.bss = bnx_RXP_b06FwBss; 3166 3167 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3168 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3169 fw.rodata_index = 0; 3170 fw.rodata = bnx_RXP_b06FwRodata; 3171 3172 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3173 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3174 3175 /* Initialize the TX Processor. */ 3176 cpu_reg.mode = BNX_TXP_CPU_MODE; 3177 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3178 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3179 cpu_reg.state = BNX_TXP_CPU_STATE; 3180 cpu_reg.state_value_clear = 0xffffff; 3181 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3182 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3183 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3184 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3185 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3186 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3187 cpu_reg.mips_view_base = 0x8000000; 3188 3189 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3190 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3191 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3192 fw.start_addr = bnx_TXP_b06FwStartAddr; 3193 3194 fw.text_addr = bnx_TXP_b06FwTextAddr; 3195 fw.text_len = bnx_TXP_b06FwTextLen; 3196 fw.text_index = 0; 3197 fw.text = bnx_TXP_b06FwText; 3198 3199 fw.data_addr = bnx_TXP_b06FwDataAddr; 3200 fw.data_len = bnx_TXP_b06FwDataLen; 3201 fw.data_index = 0; 3202 fw.data = bnx_TXP_b06FwData; 3203 3204 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3205 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3206 fw.sbss_index = 0; 3207 fw.sbss = bnx_TXP_b06FwSbss; 3208 3209 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3210 fw.bss_len = bnx_TXP_b06FwBssLen; 3211 fw.bss_index = 0; 3212 fw.bss = bnx_TXP_b06FwBss; 3213 3214 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3215 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3216 fw.rodata_index = 0; 3217 fw.rodata = bnx_TXP_b06FwRodata; 3218 3219 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3220 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3221 3222 /* Initialize the TX Patch-up Processor. */ 3223 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3224 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3225 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3226 cpu_reg.state = BNX_TPAT_CPU_STATE; 3227 cpu_reg.state_value_clear = 0xffffff; 3228 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3229 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3230 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3231 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3232 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3233 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3234 cpu_reg.mips_view_base = 0x8000000; 3235 3236 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3237 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3238 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3239 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3240 3241 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3242 fw.text_len = bnx_TPAT_b06FwTextLen; 3243 fw.text_index = 0; 3244 fw.text = bnx_TPAT_b06FwText; 3245 3246 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3247 fw.data_len = bnx_TPAT_b06FwDataLen; 3248 fw.data_index = 0; 3249 fw.data = bnx_TPAT_b06FwData; 3250 3251 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3252 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3253 fw.sbss_index = 0; 3254 fw.sbss = bnx_TPAT_b06FwSbss; 3255 3256 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3257 fw.bss_len = bnx_TPAT_b06FwBssLen; 3258 fw.bss_index = 0; 3259 fw.bss = bnx_TPAT_b06FwBss; 3260 3261 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3262 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3263 fw.rodata_index = 0; 3264 fw.rodata = bnx_TPAT_b06FwRodata; 3265 3266 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3267 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3268 3269 /* Initialize the Completion Processor. */ 3270 cpu_reg.mode = BNX_COM_CPU_MODE; 3271 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3272 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3273 cpu_reg.state = BNX_COM_CPU_STATE; 3274 cpu_reg.state_value_clear = 0xffffff; 3275 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3276 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3277 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3278 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3279 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3280 cpu_reg.spad_base = BNX_COM_SCRATCH; 3281 cpu_reg.mips_view_base = 0x8000000; 3282 3283 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3284 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3285 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3286 fw.start_addr = bnx_COM_b06FwStartAddr; 3287 3288 fw.text_addr = bnx_COM_b06FwTextAddr; 3289 fw.text_len = bnx_COM_b06FwTextLen; 3290 fw.text_index = 0; 3291 fw.text = bnx_COM_b06FwText; 3292 3293 fw.data_addr = bnx_COM_b06FwDataAddr; 3294 fw.data_len = bnx_COM_b06FwDataLen; 3295 fw.data_index = 0; 3296 fw.data = bnx_COM_b06FwData; 3297 3298 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3299 fw.sbss_len = bnx_COM_b06FwSbssLen; 3300 fw.sbss_index = 0; 3301 fw.sbss = bnx_COM_b06FwSbss; 3302 3303 fw.bss_addr = bnx_COM_b06FwBssAddr; 3304 fw.bss_len = bnx_COM_b06FwBssLen; 3305 fw.bss_index = 0; 3306 fw.bss = bnx_COM_b06FwBss; 3307 3308 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3309 fw.rodata_len = bnx_COM_b06FwRodataLen; 3310 fw.rodata_index = 0; 3311 fw.rodata = bnx_COM_b06FwRodata; 3312 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3313 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3314 break; 3315 } 3316 } 3317 3318 /****************************************************************************/ 3319 /* Initialize context memory. */ 3320 /* */ 3321 /* Clears the memory associated with each Context ID (CID). */ 3322 /* */ 3323 /* Returns: */ 3324 /* Nothing. */ 3325 /****************************************************************************/ 3326 void 3327 bnx_init_context(struct bnx_softc *sc) 3328 { 3329 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3330 /* DRC: Replace this constant value with a #define. */ 3331 int i, retry_cnt = 10; 3332 uint32_t val; 3333 3334 /* 3335 * BCM5709 context memory may be cached 3336 * in host memory so prepare the host memory 3337 * for access. 3338 */ 3339 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3340 | (1 << 12); 3341 val |= (BCM_PAGE_BITS - 8) << 16; 3342 REG_WR(sc, BNX_CTX_COMMAND, val); 3343 3344 /* Wait for mem init command to complete. */ 3345 for (i = 0; i < retry_cnt; i++) { 3346 val = REG_RD(sc, BNX_CTX_COMMAND); 3347 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3348 break; 3349 DELAY(2); 3350 } 3351 3352 /* ToDo: Consider returning an error here. */ 3353 3354 for (i = 0; i < sc->ctx_pages; i++) { 3355 int j; 3356 3357 /* Set the physaddr of the context memory cache. */ 3358 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3359 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3360 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3361 val = (uint32_t) 3362 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3363 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3364 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3365 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3366 3367 /* Verify that the context memory write was successful. */ 3368 for (j = 0; j < retry_cnt; j++) { 3369 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3370 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3371 break; 3372 DELAY(5); 3373 } 3374 3375 /* ToDo: Consider returning an error here. */ 3376 } 3377 } else { 3378 uint32_t vcid_addr, offset; 3379 3380 /* 3381 * For the 5706/5708, context memory is local to the 3382 * controller, so initialize the controller context memory. 3383 */ 3384 3385 vcid_addr = GET_CID_ADDR(96); 3386 while (vcid_addr) { 3387 3388 vcid_addr -= BNX_PHY_CTX_SIZE; 3389 3390 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3391 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3392 3393 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3394 offset += 4) 3395 CTX_WR(sc, 0x00, offset, 0); 3396 3397 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3398 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3399 } 3400 } 3401 } 3402 3403 /****************************************************************************/ 3404 /* Fetch the permanent MAC address of the controller. */ 3405 /* */ 3406 /* Returns: */ 3407 /* Nothing. */ 3408 /****************************************************************************/ 3409 void 3410 bnx_get_mac_addr(struct bnx_softc *sc) 3411 { 3412 uint32_t mac_lo = 0, mac_hi = 0; 3413 3414 /* 3415 * The NetXtreme II bootcode populates various NIC 3416 * power-on and runtime configuration items in a 3417 * shared memory area. The factory configured MAC 3418 * address is available from both NVRAM and the 3419 * shared memory area so we'll read the value from 3420 * shared memory for speed. 3421 */ 3422 3423 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3424 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3425 3426 if ((mac_lo == 0) && (mac_hi == 0)) { 3427 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3428 __FILE__, __LINE__); 3429 } else { 3430 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3431 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3432 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3433 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3434 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3435 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3436 } 3437 3438 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3439 "%s\n", ether_sprintf(sc->eaddr)); 3440 } 3441 3442 /****************************************************************************/ 3443 /* Program the MAC address. */ 3444 /* */ 3445 /* Returns: */ 3446 /* Nothing. */ 3447 /****************************************************************************/ 3448 void 3449 bnx_set_mac_addr(struct bnx_softc *sc) 3450 { 3451 uint32_t val; 3452 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3453 3454 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3455 "%s\n", ether_sprintf(sc->eaddr)); 3456 3457 val = (mac_addr[0] << 8) | mac_addr[1]; 3458 3459 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3460 3461 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3462 (mac_addr[4] << 8) | mac_addr[5]; 3463 3464 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3465 } 3466 3467 /****************************************************************************/ 3468 /* Stop the controller. */ 3469 /* */ 3470 /* Returns: */ 3471 /* Nothing. */ 3472 /****************************************************************************/ 3473 void 3474 bnx_stop(struct ifnet *ifp, int disable) 3475 { 3476 struct bnx_softc *sc = ifp->if_softc; 3477 3478 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3479 3480 if (disable) { 3481 sc->bnx_detaching = 1; 3482 callout_halt(&sc->bnx_timeout, NULL); 3483 } else 3484 callout_stop(&sc->bnx_timeout); 3485 3486 mii_down(&sc->bnx_mii); 3487 3488 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3489 3490 /* Disable the transmit/receive blocks. */ 3491 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3492 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3493 DELAY(20); 3494 3495 bnx_disable_intr(sc); 3496 3497 /* Tell firmware that the driver is going away. */ 3498 if (disable) 3499 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3500 else 3501 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3502 3503 /* Free RX buffers. */ 3504 bnx_free_rx_chain(sc); 3505 3506 /* Free TX buffers. */ 3507 bnx_free_tx_chain(sc); 3508 3509 ifp->if_timer = 0; 3510 3511 sc->bnx_link = 0; 3512 3513 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3514 3515 bnx_mgmt_init(sc); 3516 } 3517 3518 int 3519 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3520 { 3521 struct pci_attach_args *pa = &(sc->bnx_pa); 3522 uint32_t val; 3523 int i, rc = 0; 3524 3525 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3526 3527 /* Wait for pending PCI transactions to complete. */ 3528 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3529 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3530 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3531 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3532 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3533 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3534 DELAY(5); 3535 3536 /* Disable DMA */ 3537 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3538 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3539 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3540 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3541 } 3542 3543 /* Assume bootcode is running. */ 3544 sc->bnx_fw_timed_out = 0; 3545 3546 /* Give the firmware a chance to prepare for the reset. */ 3547 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3548 if (rc) 3549 goto bnx_reset_exit; 3550 3551 /* Set a firmware reminder that this is a soft reset. */ 3552 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3553 BNX_DRV_RESET_SIGNATURE_MAGIC); 3554 3555 /* Dummy read to force the chip to complete all current transactions. */ 3556 val = REG_RD(sc, BNX_MISC_ID); 3557 3558 /* Chip reset. */ 3559 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3560 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3561 REG_RD(sc, BNX_MISC_COMMAND); 3562 DELAY(5); 3563 3564 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3565 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3566 3567 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3568 val); 3569 } else { 3570 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3571 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3572 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3573 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3574 3575 /* Allow up to 30us for reset to complete. */ 3576 for (i = 0; i < 10; i++) { 3577 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3578 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3579 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3580 break; 3581 } 3582 DELAY(10); 3583 } 3584 3585 /* Check that reset completed successfully. */ 3586 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3587 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3588 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3589 __FILE__, __LINE__); 3590 rc = EBUSY; 3591 goto bnx_reset_exit; 3592 } 3593 } 3594 3595 /* Make sure byte swapping is properly configured. */ 3596 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3597 if (val != 0x01020304) { 3598 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3599 __FILE__, __LINE__); 3600 rc = ENODEV; 3601 goto bnx_reset_exit; 3602 } 3603 3604 /* Just completed a reset, assume that firmware is running again. */ 3605 sc->bnx_fw_timed_out = 0; 3606 3607 /* Wait for the firmware to finish its initialization. */ 3608 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3609 if (rc) 3610 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3611 "initialization!\n", __FILE__, __LINE__); 3612 3613 bnx_reset_exit: 3614 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3615 3616 return rc; 3617 } 3618 3619 int 3620 bnx_chipinit(struct bnx_softc *sc) 3621 { 3622 struct pci_attach_args *pa = &(sc->bnx_pa); 3623 uint32_t val; 3624 int rc = 0; 3625 3626 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3627 3628 /* Make sure the interrupt is not active. */ 3629 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3630 3631 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3632 /* channels and PCI clock compensation delay. */ 3633 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3634 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3635 #if BYTE_ORDER == BIG_ENDIAN 3636 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3637 #endif 3638 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3639 DMA_READ_CHANS << 12 | 3640 DMA_WRITE_CHANS << 16; 3641 3642 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3643 3644 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3645 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3646 3647 /* 3648 * This setting resolves a problem observed on certain Intel PCI 3649 * chipsets that cannot handle multiple outstanding DMA operations. 3650 * See errata E9_5706A1_65. 3651 */ 3652 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3653 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3654 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3655 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3656 3657 REG_WR(sc, BNX_DMA_CONFIG, val); 3658 3659 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3660 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3661 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3662 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3663 val & ~0x20000); 3664 } 3665 3666 /* Enable the RX_V2P and Context state machines before access. */ 3667 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3668 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3669 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3670 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3671 3672 /* Initialize context mapping and zero out the quick contexts. */ 3673 bnx_init_context(sc); 3674 3675 /* Initialize the on-boards CPUs */ 3676 bnx_init_cpus(sc); 3677 3678 /* Enable management frames (NC-SI) to flow to the MCP. */ 3679 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3680 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) | 3681 BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3682 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3683 } 3684 3685 /* Prepare NVRAM for access. */ 3686 if (bnx_init_nvram(sc)) { 3687 rc = ENODEV; 3688 goto bnx_chipinit_exit; 3689 } 3690 3691 /* Set the kernel bypass block size */ 3692 val = REG_RD(sc, BNX_MQ_CONFIG); 3693 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3694 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3695 3696 /* Enable bins used on the 5709. */ 3697 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3698 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3699 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3700 val |= BNX_MQ_CONFIG_HALT_DIS; 3701 } 3702 3703 REG_WR(sc, BNX_MQ_CONFIG, val); 3704 3705 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3706 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3707 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3708 3709 val = (BCM_PAGE_BITS - 8) << 24; 3710 REG_WR(sc, BNX_RV2P_CONFIG, val); 3711 3712 /* Configure page size. */ 3713 val = REG_RD(sc, BNX_TBDR_CONFIG); 3714 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3715 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3716 REG_WR(sc, BNX_TBDR_CONFIG, val); 3717 3718 #if 0 3719 /* Set the perfect match control register to default. */ 3720 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3721 #endif 3722 3723 bnx_chipinit_exit: 3724 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3725 3726 return rc; 3727 } 3728 3729 /****************************************************************************/ 3730 /* Initialize the controller in preparation to send/receive traffic. */ 3731 /* */ 3732 /* Returns: */ 3733 /* 0 for success, positive value for failure. */ 3734 /****************************************************************************/ 3735 int 3736 bnx_blockinit(struct bnx_softc *sc) 3737 { 3738 uint32_t reg, val; 3739 int rc = 0; 3740 3741 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3742 3743 /* Load the hardware default MAC address. */ 3744 bnx_set_mac_addr(sc); 3745 3746 /* Set the Ethernet backoff seed value */ 3747 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3748 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3749 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3750 3751 sc->last_status_idx = 0; 3752 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3753 3754 /* Set up link change interrupt generation. */ 3755 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3756 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3757 3758 /* Program the physical address of the status block. */ 3759 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3760 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3761 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3762 3763 /* Program the physical address of the statistics block. */ 3764 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3765 (uint32_t)(sc->stats_block_paddr)); 3766 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3767 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3768 3769 /* Program various host coalescing parameters. */ 3770 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3771 << 16) | sc->bnx_tx_quick_cons_trip); 3772 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3773 << 16) | sc->bnx_rx_quick_cons_trip); 3774 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3775 sc->bnx_comp_prod_trip); 3776 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3777 sc->bnx_tx_ticks); 3778 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3779 sc->bnx_rx_ticks); 3780 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3781 sc->bnx_com_ticks); 3782 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3783 sc->bnx_cmd_ticks); 3784 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3785 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3786 REG_WR(sc, BNX_HC_CONFIG, 3787 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3788 BNX_HC_CONFIG_COLLECT_STATS)); 3789 3790 /* Clear the internal statistics counters. */ 3791 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3792 3793 /* Verify that bootcode is running. */ 3794 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3795 3796 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3797 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3798 __FILE__, __LINE__); reg = 0); 3799 3800 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3801 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3802 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3803 "Expected: 08%08X\n", __FILE__, __LINE__, 3804 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3805 BNX_DEV_INFO_SIGNATURE_MAGIC); 3806 rc = ENODEV; 3807 goto bnx_blockinit_exit; 3808 } 3809 3810 /* Enable DMA */ 3811 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3812 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3813 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3814 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3815 } 3816 3817 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3818 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3819 3820 /* Disable management frames (NC-SI) from flowing to the MCP. */ 3821 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3822 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) & 3823 ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3824 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3825 } 3826 3827 /* Enable all remaining blocks in the MAC. */ 3828 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3829 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3830 BNX_MISC_ENABLE_DEFAULT_XI); 3831 } else 3832 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3833 3834 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3835 DELAY(20); 3836 3837 bnx_blockinit_exit: 3838 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3839 3840 return rc; 3841 } 3842 3843 static int 3844 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3845 uint16_t *chain_prod, uint32_t *prod_bseq) 3846 { 3847 bus_dmamap_t map; 3848 struct rx_bd *rxbd; 3849 uint32_t addr; 3850 int i; 3851 #ifdef BNX_DEBUG 3852 uint16_t debug_chain_prod = *chain_prod; 3853 #endif 3854 uint16_t first_chain_prod; 3855 3856 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3857 3858 /* Map the mbuf cluster into device memory. */ 3859 map = sc->rx_mbuf_map[*chain_prod]; 3860 first_chain_prod = *chain_prod; 3861 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3862 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3863 __FILE__, __LINE__); 3864 3865 m_freem(m_new); 3866 3867 DBRUNIF(1, sc->rx_mbuf_alloc--); 3868 3869 return ENOBUFS; 3870 } 3871 /* Make sure there is room in the receive chain. */ 3872 if (map->dm_nsegs > sc->free_rx_bd) { 3873 bus_dmamap_unload(sc->bnx_dmatag, map); 3874 m_freem(m_new); 3875 return EFBIG; 3876 } 3877 #ifdef BNX_DEBUG 3878 /* Track the distribution of buffer segments. */ 3879 sc->rx_mbuf_segs[map->dm_nsegs]++; 3880 #endif 3881 3882 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3883 BUS_DMASYNC_PREREAD); 3884 3885 /* Update some debug statistics counters */ 3886 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3887 sc->rx_low_watermark = sc->free_rx_bd); 3888 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3889 3890 /* 3891 * Setup the rx_bd for the first segment 3892 */ 3893 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3894 3895 addr = (uint32_t)map->dm_segs[0].ds_addr; 3896 rxbd->rx_bd_haddr_lo = addr; 3897 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3898 rxbd->rx_bd_haddr_hi = addr; 3899 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3900 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3901 *prod_bseq += map->dm_segs[0].ds_len; 3902 bus_dmamap_sync(sc->bnx_dmatag, 3903 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3904 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3905 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3906 3907 for (i = 1; i < map->dm_nsegs; i++) { 3908 *prod = NEXT_RX_BD(*prod); 3909 *chain_prod = RX_CHAIN_IDX(*prod); 3910 3911 rxbd = 3912 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3913 3914 addr = (uint32_t)map->dm_segs[i].ds_addr; 3915 rxbd->rx_bd_haddr_lo = addr; 3916 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3917 rxbd->rx_bd_haddr_hi = addr; 3918 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3919 rxbd->rx_bd_flags = 0; 3920 *prod_bseq += map->dm_segs[i].ds_len; 3921 bus_dmamap_sync(sc->bnx_dmatag, 3922 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3923 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3924 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3925 } 3926 3927 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3928 bus_dmamap_sync(sc->bnx_dmatag, 3929 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3930 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3931 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3932 3933 /* 3934 * Save the mbuf, adjust the map pointer (swap map for first and 3935 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3936 * and update our counter. 3937 */ 3938 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3939 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3940 sc->rx_mbuf_map[*chain_prod] = map; 3941 sc->free_rx_bd -= map->dm_nsegs; 3942 3943 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3944 map->dm_nsegs)); 3945 *prod = NEXT_RX_BD(*prod); 3946 *chain_prod = RX_CHAIN_IDX(*prod); 3947 3948 return 0; 3949 } 3950 3951 /****************************************************************************/ 3952 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3953 /* */ 3954 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3955 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3956 /* necessary. */ 3957 /* */ 3958 /* Returns: */ 3959 /* 0 for success, positive value for failure. */ 3960 /****************************************************************************/ 3961 int 3962 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3963 uint16_t *chain_prod, uint32_t *prod_bseq) 3964 { 3965 struct mbuf *m_new = NULL; 3966 int rc = 0; 3967 uint16_t min_free_bd; 3968 3969 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3970 __func__); 3971 3972 /* Make sure the inputs are valid. */ 3973 DBRUNIF((*chain_prod > MAX_RX_BD), 3974 aprint_error_dev(sc->bnx_dev, 3975 "RX producer out of range: 0x%04X > 0x%04X\n", 3976 *chain_prod, (uint16_t)MAX_RX_BD)); 3977 3978 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3979 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3980 *prod_bseq); 3981 3982 /* try to get in as many mbufs as possible */ 3983 if (sc->mbuf_alloc_size == MCLBYTES) 3984 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3985 else 3986 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3987 while (sc->free_rx_bd >= min_free_bd) { 3988 /* Simulate an mbuf allocation failure. */ 3989 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3990 aprint_error_dev(sc->bnx_dev, 3991 "Simulating mbuf allocation failure.\n"); 3992 sc->mbuf_sim_alloc_failed++; 3993 rc = ENOBUFS; 3994 goto bnx_get_buf_exit); 3995 3996 /* This is a new mbuf allocation. */ 3997 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3998 if (m_new == NULL) { 3999 DBPRINT(sc, BNX_WARN, 4000 "%s(%d): RX mbuf header allocation failed!\n", 4001 __FILE__, __LINE__); 4002 4003 sc->mbuf_alloc_failed++; 4004 4005 rc = ENOBUFS; 4006 goto bnx_get_buf_exit; 4007 } 4008 4009 DBRUNIF(1, sc->rx_mbuf_alloc++); 4010 4011 /* Simulate an mbuf cluster allocation failure. */ 4012 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4013 m_freem(m_new); 4014 sc->rx_mbuf_alloc--; 4015 sc->mbuf_alloc_failed++; 4016 sc->mbuf_sim_alloc_failed++; 4017 rc = ENOBUFS; 4018 goto bnx_get_buf_exit); 4019 4020 if (sc->mbuf_alloc_size == MCLBYTES) 4021 MCLGET(m_new, M_DONTWAIT); 4022 else 4023 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 4024 M_DONTWAIT); 4025 if (!(m_new->m_flags & M_EXT)) { 4026 DBPRINT(sc, BNX_WARN, 4027 "%s(%d): RX mbuf chain allocation failed!\n", 4028 __FILE__, __LINE__); 4029 4030 m_freem(m_new); 4031 4032 DBRUNIF(1, sc->rx_mbuf_alloc--); 4033 sc->mbuf_alloc_failed++; 4034 4035 rc = ENOBUFS; 4036 goto bnx_get_buf_exit; 4037 } 4038 4039 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 4040 if (rc != 0) 4041 goto bnx_get_buf_exit; 4042 } 4043 4044 bnx_get_buf_exit: 4045 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 4046 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 4047 *chain_prod, *prod_bseq); 4048 4049 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 4050 __func__); 4051 4052 return rc; 4053 } 4054 4055 void 4056 bnx_alloc_pkts(struct work * unused, void * arg) 4057 { 4058 struct bnx_softc *sc = arg; 4059 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4060 struct bnx_pkt *pkt; 4061 int i, s; 4062 4063 for (i = 0; i < 4; i++) { /* magic! */ 4064 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 4065 if (pkt == NULL) 4066 break; 4067 4068 if (bus_dmamap_create(sc->bnx_dmatag, 4069 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4070 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4071 &pkt->pkt_dmamap) != 0) 4072 goto put; 4073 4074 if (!ISSET(ifp->if_flags, IFF_UP)) 4075 goto stopping; 4076 4077 mutex_enter(&sc->tx_pkt_mtx); 4078 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4079 sc->tx_pkt_count++; 4080 mutex_exit(&sc->tx_pkt_mtx); 4081 } 4082 4083 mutex_enter(&sc->tx_pkt_mtx); 4084 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4085 mutex_exit(&sc->tx_pkt_mtx); 4086 4087 /* fire-up TX now that allocations have been done */ 4088 s = splnet(); 4089 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4090 bnx_start(ifp); 4091 splx(s); 4092 4093 return; 4094 4095 stopping: 4096 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4097 put: 4098 pool_put(bnx_tx_pool, pkt); 4099 return; 4100 } 4101 4102 /****************************************************************************/ 4103 /* Initialize the TX context memory. */ 4104 /* */ 4105 /* Returns: */ 4106 /* Nothing */ 4107 /****************************************************************************/ 4108 void 4109 bnx_init_tx_context(struct bnx_softc *sc) 4110 { 4111 uint32_t val; 4112 4113 /* Initialize the context ID for an L2 TX chain. */ 4114 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4115 /* Set the CID type to support an L2 connection. */ 4116 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4117 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4118 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4119 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4120 4121 /* Point the hardware to the first page in the chain. */ 4122 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4123 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4124 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4125 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4126 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4127 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4128 } else { 4129 /* Set the CID type to support an L2 connection. */ 4130 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4131 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4132 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4133 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4134 4135 /* Point the hardware to the first page in the chain. */ 4136 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4137 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4138 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4139 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4140 } 4141 } 4142 4143 4144 /****************************************************************************/ 4145 /* Allocate memory and initialize the TX data structures. */ 4146 /* */ 4147 /* Returns: */ 4148 /* 0 for success, positive value for failure. */ 4149 /****************************************************************************/ 4150 int 4151 bnx_init_tx_chain(struct bnx_softc *sc) 4152 { 4153 struct tx_bd *txbd; 4154 uint32_t addr; 4155 int i, rc = 0; 4156 4157 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4158 4159 /* Force an allocation of some dmamaps for tx up front */ 4160 bnx_alloc_pkts(NULL, sc); 4161 4162 /* Set the initial TX producer/consumer indices. */ 4163 sc->tx_prod = 0; 4164 sc->tx_cons = 0; 4165 sc->tx_prod_bseq = 0; 4166 sc->used_tx_bd = 0; 4167 sc->max_tx_bd = USABLE_TX_BD; 4168 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4169 DBRUNIF(1, sc->tx_full_count = 0); 4170 4171 /* 4172 * The NetXtreme II supports a linked-list structure called 4173 * a Buffer Descriptor Chain (or BD chain). A BD chain 4174 * consists of a series of 1 or more chain pages, each of which 4175 * consists of a fixed number of BD entries. 4176 * The last BD entry on each page is a pointer to the next page 4177 * in the chain, and the last pointer in the BD chain 4178 * points back to the beginning of the chain. 4179 */ 4180 4181 /* Set the TX next pointer chain entries. */ 4182 for (i = 0; i < TX_PAGES; i++) { 4183 int j; 4184 4185 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4186 4187 /* Check if we've reached the last page. */ 4188 if (i == (TX_PAGES - 1)) 4189 j = 0; 4190 else 4191 j = i + 1; 4192 4193 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4194 txbd->tx_bd_haddr_lo = addr; 4195 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4196 txbd->tx_bd_haddr_hi = addr; 4197 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4198 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4199 } 4200 4201 /* 4202 * Initialize the context ID for an L2 TX chain. 4203 */ 4204 bnx_init_tx_context(sc); 4205 4206 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4207 4208 return rc; 4209 } 4210 4211 /****************************************************************************/ 4212 /* Free memory and clear the TX data structures. */ 4213 /* */ 4214 /* Returns: */ 4215 /* Nothing. */ 4216 /****************************************************************************/ 4217 void 4218 bnx_free_tx_chain(struct bnx_softc *sc) 4219 { 4220 struct bnx_pkt *pkt; 4221 int i; 4222 4223 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4224 4225 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4226 mutex_enter(&sc->tx_pkt_mtx); 4227 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4228 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4229 mutex_exit(&sc->tx_pkt_mtx); 4230 4231 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4232 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4233 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4234 4235 m_freem(pkt->pkt_mbuf); 4236 DBRUNIF(1, sc->tx_mbuf_alloc--); 4237 4238 mutex_enter(&sc->tx_pkt_mtx); 4239 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4240 } 4241 4242 /* Destroy all the dmamaps we allocated for TX */ 4243 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4244 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4245 sc->tx_pkt_count--; 4246 mutex_exit(&sc->tx_pkt_mtx); 4247 4248 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4249 pool_put(bnx_tx_pool, pkt); 4250 4251 mutex_enter(&sc->tx_pkt_mtx); 4252 } 4253 mutex_exit(&sc->tx_pkt_mtx); 4254 4255 4256 4257 /* Clear each TX chain page. */ 4258 for (i = 0; i < TX_PAGES; i++) { 4259 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4260 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4261 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4262 } 4263 4264 sc->used_tx_bd = 0; 4265 4266 /* Check if we lost any mbufs in the process. */ 4267 DBRUNIF((sc->tx_mbuf_alloc), 4268 aprint_error_dev(sc->bnx_dev, 4269 "Memory leak! Lost %d mbufs from tx chain!\n", 4270 sc->tx_mbuf_alloc)); 4271 4272 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4273 } 4274 4275 /****************************************************************************/ 4276 /* Initialize the RX context memory. */ 4277 /* */ 4278 /* Returns: */ 4279 /* Nothing */ 4280 /****************************************************************************/ 4281 void 4282 bnx_init_rx_context(struct bnx_softc *sc) 4283 { 4284 uint32_t val; 4285 4286 /* Initialize the context ID for an L2 RX chain. */ 4287 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4288 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4289 4290 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4291 val |= 0x000000ff; 4292 4293 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4294 4295 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4296 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4297 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4298 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4299 } 4300 4301 /* Point the hardware to the first page in the chain. */ 4302 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4303 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4304 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4305 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4306 } 4307 4308 /****************************************************************************/ 4309 /* Allocate memory and initialize the RX data structures. */ 4310 /* */ 4311 /* Returns: */ 4312 /* 0 for success, positive value for failure. */ 4313 /****************************************************************************/ 4314 int 4315 bnx_init_rx_chain(struct bnx_softc *sc) 4316 { 4317 struct rx_bd *rxbd; 4318 int i, rc = 0; 4319 uint16_t prod, chain_prod; 4320 uint32_t prod_bseq, addr; 4321 4322 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4323 4324 /* Initialize the RX producer and consumer indices. */ 4325 sc->rx_prod = 0; 4326 sc->rx_cons = 0; 4327 sc->rx_prod_bseq = 0; 4328 sc->free_rx_bd = USABLE_RX_BD; 4329 sc->max_rx_bd = USABLE_RX_BD; 4330 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4331 DBRUNIF(1, sc->rx_empty_count = 0); 4332 4333 /* Initialize the RX next pointer chain entries. */ 4334 for (i = 0; i < RX_PAGES; i++) { 4335 int j; 4336 4337 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4338 4339 /* Check if we've reached the last page. */ 4340 if (i == (RX_PAGES - 1)) 4341 j = 0; 4342 else 4343 j = i + 1; 4344 4345 /* Setup the chain page pointers. */ 4346 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4347 rxbd->rx_bd_haddr_hi = addr; 4348 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4349 rxbd->rx_bd_haddr_lo = addr; 4350 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4351 0, BNX_RX_CHAIN_PAGE_SZ, 4352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4353 } 4354 4355 /* Allocate mbuf clusters for the rx_bd chain. */ 4356 prod = prod_bseq = 0; 4357 chain_prod = RX_CHAIN_IDX(prod); 4358 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4359 BNX_PRINTF(sc, 4360 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4361 } 4362 4363 /* Save the RX chain producer index. */ 4364 sc->rx_prod = prod; 4365 sc->rx_prod_bseq = prod_bseq; 4366 4367 for (i = 0; i < RX_PAGES; i++) 4368 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4369 sc->rx_bd_chain_map[i]->dm_mapsize, 4370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4371 4372 /* Tell the chip about the waiting rx_bd's. */ 4373 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4374 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4375 4376 bnx_init_rx_context(sc); 4377 4378 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4379 4380 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4381 4382 return rc; 4383 } 4384 4385 /****************************************************************************/ 4386 /* Free memory and clear the RX data structures. */ 4387 /* */ 4388 /* Returns: */ 4389 /* Nothing. */ 4390 /****************************************************************************/ 4391 void 4392 bnx_free_rx_chain(struct bnx_softc *sc) 4393 { 4394 int i; 4395 4396 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4397 4398 /* Free any mbufs still in the RX mbuf chain. */ 4399 for (i = 0; i < TOTAL_RX_BD; i++) { 4400 if (sc->rx_mbuf_ptr[i] != NULL) { 4401 if (sc->rx_mbuf_map[i] != NULL) { 4402 bus_dmamap_sync(sc->bnx_dmatag, 4403 sc->rx_mbuf_map[i], 0, 4404 sc->rx_mbuf_map[i]->dm_mapsize, 4405 BUS_DMASYNC_POSTREAD); 4406 bus_dmamap_unload(sc->bnx_dmatag, 4407 sc->rx_mbuf_map[i]); 4408 } 4409 m_freem(sc->rx_mbuf_ptr[i]); 4410 sc->rx_mbuf_ptr[i] = NULL; 4411 DBRUNIF(1, sc->rx_mbuf_alloc--); 4412 } 4413 } 4414 4415 /* Clear each RX chain page. */ 4416 for (i = 0; i < RX_PAGES; i++) 4417 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4418 4419 sc->free_rx_bd = sc->max_rx_bd; 4420 4421 /* Check if we lost any mbufs in the process. */ 4422 DBRUNIF((sc->rx_mbuf_alloc), 4423 aprint_error_dev(sc->bnx_dev, 4424 "Memory leak! Lost %d mbufs from rx chain!\n", 4425 sc->rx_mbuf_alloc)); 4426 4427 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4428 } 4429 4430 /****************************************************************************/ 4431 /* Set media options. */ 4432 /* */ 4433 /* Returns: */ 4434 /* 0 for success, positive value for failure. */ 4435 /****************************************************************************/ 4436 int 4437 bnx_ifmedia_upd(struct ifnet *ifp) 4438 { 4439 struct bnx_softc *sc; 4440 struct mii_data *mii; 4441 int rc = 0; 4442 4443 sc = ifp->if_softc; 4444 4445 mii = &sc->bnx_mii; 4446 sc->bnx_link = 0; 4447 if (mii->mii_instance) { 4448 struct mii_softc *miisc; 4449 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4450 mii_phy_reset(miisc); 4451 } 4452 mii_mediachg(mii); 4453 4454 return rc; 4455 } 4456 4457 /****************************************************************************/ 4458 /* Reports current media status. */ 4459 /* */ 4460 /* Returns: */ 4461 /* Nothing. */ 4462 /****************************************************************************/ 4463 void 4464 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4465 { 4466 struct bnx_softc *sc; 4467 struct mii_data *mii; 4468 int s; 4469 4470 sc = ifp->if_softc; 4471 4472 s = splnet(); 4473 4474 mii = &sc->bnx_mii; 4475 4476 mii_pollstat(mii); 4477 ifmr->ifm_status = mii->mii_media_status; 4478 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4479 sc->bnx_flowflags; 4480 4481 splx(s); 4482 } 4483 4484 /****************************************************************************/ 4485 /* Handles PHY generated interrupt events. */ 4486 /* */ 4487 /* Returns: */ 4488 /* Nothing. */ 4489 /****************************************************************************/ 4490 void 4491 bnx_phy_intr(struct bnx_softc *sc) 4492 { 4493 uint32_t new_link_state, old_link_state; 4494 4495 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4496 BUS_DMASYNC_POSTREAD); 4497 new_link_state = sc->status_block->status_attn_bits & 4498 STATUS_ATTN_BITS_LINK_STATE; 4499 old_link_state = sc->status_block->status_attn_bits_ack & 4500 STATUS_ATTN_BITS_LINK_STATE; 4501 4502 /* Handle any changes if the link state has changed. */ 4503 if (new_link_state != old_link_state) { 4504 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4505 4506 sc->bnx_link = 0; 4507 callout_stop(&sc->bnx_timeout); 4508 bnx_tick(sc); 4509 4510 /* Update the status_attn_bits_ack field in the status block. */ 4511 if (new_link_state) { 4512 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4513 STATUS_ATTN_BITS_LINK_STATE); 4514 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4515 } else { 4516 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4517 STATUS_ATTN_BITS_LINK_STATE); 4518 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4519 } 4520 } 4521 4522 /* Acknowledge the link change interrupt. */ 4523 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4524 } 4525 4526 /****************************************************************************/ 4527 /* Handles received frame interrupt events. */ 4528 /* */ 4529 /* Returns: */ 4530 /* Nothing. */ 4531 /****************************************************************************/ 4532 void 4533 bnx_rx_intr(struct bnx_softc *sc) 4534 { 4535 struct status_block *sblk = sc->status_block; 4536 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4537 uint16_t hw_cons, sw_cons, sw_chain_cons; 4538 uint16_t sw_prod, sw_chain_prod; 4539 uint32_t sw_prod_bseq; 4540 struct l2_fhdr *l2fhdr; 4541 int i; 4542 4543 DBRUNIF(1, sc->rx_interrupts++); 4544 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4545 BUS_DMASYNC_POSTREAD); 4546 4547 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4548 for (i = 0; i < RX_PAGES; i++) 4549 bus_dmamap_sync(sc->bnx_dmatag, 4550 sc->rx_bd_chain_map[i], 0, 4551 sc->rx_bd_chain_map[i]->dm_mapsize, 4552 BUS_DMASYNC_POSTWRITE); 4553 4554 /* Get the hardware's view of the RX consumer index. */ 4555 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4556 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4557 hw_cons++; 4558 4559 /* Get working copies of the driver's view of the RX indices. */ 4560 sw_cons = sc->rx_cons; 4561 sw_prod = sc->rx_prod; 4562 sw_prod_bseq = sc->rx_prod_bseq; 4563 4564 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4565 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4566 __func__, sw_prod, sw_cons, sw_prod_bseq); 4567 4568 /* Prevent speculative reads from getting ahead of the status block. */ 4569 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4570 BUS_SPACE_BARRIER_READ); 4571 4572 /* Update some debug statistics counters */ 4573 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4574 sc->rx_low_watermark = sc->free_rx_bd); 4575 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4576 4577 /* 4578 * Scan through the receive chain as long 4579 * as there is work to do. 4580 */ 4581 while (sw_cons != hw_cons) { 4582 struct mbuf *m; 4583 struct rx_bd *rxbd __diagused; 4584 unsigned int len; 4585 uint32_t status; 4586 4587 /* Convert the producer/consumer indices to an actual 4588 * rx_bd index. 4589 */ 4590 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4591 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4592 4593 /* Get the used rx_bd. */ 4594 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4595 sc->free_rx_bd++; 4596 4597 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4598 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4599 4600 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4601 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4602 #ifdef DIAGNOSTIC 4603 /* Validate that this is the last rx_bd. */ 4604 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4605 printf("%s: Unexpected mbuf found in " 4606 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4607 sw_chain_cons); 4608 } 4609 #endif 4610 4611 /* DRC - ToDo: If the received packet is small, say 4612 * less than 128 bytes, allocate a new mbuf 4613 * here, copy the data to that mbuf, and 4614 * recycle the mapped jumbo frame. 4615 */ 4616 4617 /* Unmap the mbuf from DMA space. */ 4618 #ifdef DIAGNOSTIC 4619 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4620 printf("invalid map sw_cons 0x%x " 4621 "sw_prod 0x%x " 4622 "sw_chain_cons 0x%x " 4623 "sw_chain_prod 0x%x " 4624 "hw_cons 0x%x " 4625 "TOTAL_RX_BD_PER_PAGE 0x%x " 4626 "TOTAL_RX_BD 0x%x\n", 4627 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4628 hw_cons, 4629 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4630 } 4631 #endif 4632 bus_dmamap_sync(sc->bnx_dmatag, 4633 sc->rx_mbuf_map[sw_chain_cons], 0, 4634 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4635 BUS_DMASYNC_POSTREAD); 4636 bus_dmamap_unload(sc->bnx_dmatag, 4637 sc->rx_mbuf_map[sw_chain_cons]); 4638 4639 /* Remove the mbuf from the driver's chain. */ 4640 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4641 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4642 4643 /* 4644 * Frames received on the NetXteme II are prepended 4645 * with the l2_fhdr structure which provides status 4646 * information about the received frame (including 4647 * VLAN tags and checksum info) and are also 4648 * automatically adjusted to align the IP header 4649 * (i.e. two null bytes are inserted before the 4650 * Ethernet header). 4651 */ 4652 l2fhdr = mtod(m, struct l2_fhdr *); 4653 4654 len = l2fhdr->l2_fhdr_pkt_len; 4655 status = l2fhdr->l2_fhdr_status; 4656 4657 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4658 aprint_error("Simulating l2_fhdr status error.\n"); 4659 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4660 4661 /* Watch for unusual sized frames. */ 4662 DBRUNIF(((len < BNX_MIN_MTU) || 4663 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4664 aprint_error_dev(sc->bnx_dev, 4665 "Unusual frame size found. " 4666 "Min(%d), Actual(%d), Max(%d)\n", 4667 (int)BNX_MIN_MTU, len, 4668 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4669 4670 bnx_dump_mbuf(sc, m); 4671 bnx_breakpoint(sc)); 4672 4673 len -= ETHER_CRC_LEN; 4674 4675 /* Check the received frame for errors. */ 4676 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4677 L2_FHDR_ERRORS_PHY_DECODE | 4678 L2_FHDR_ERRORS_ALIGNMENT | 4679 L2_FHDR_ERRORS_TOO_SHORT | 4680 L2_FHDR_ERRORS_GIANT_FRAME)) || 4681 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4682 len > 4683 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4684 ifp->if_ierrors++; 4685 DBRUNIF(1, sc->l2fhdr_status_errors++); 4686 4687 /* Reuse the mbuf for a new frame. */ 4688 if (bnx_add_buf(sc, m, &sw_prod, 4689 &sw_chain_prod, &sw_prod_bseq)) { 4690 DBRUNIF(1, bnx_breakpoint(sc)); 4691 panic("%s: Can't reuse RX mbuf!\n", 4692 device_xname(sc->bnx_dev)); 4693 } 4694 continue; 4695 } 4696 4697 /* 4698 * Get a new mbuf for the rx_bd. If no new 4699 * mbufs are available then reuse the current mbuf, 4700 * log an ierror on the interface, and generate 4701 * an error in the system log. 4702 */ 4703 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4704 &sw_prod_bseq)) { 4705 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4706 "Failed to allocate " 4707 "new mbuf, incoming frame dropped!\n")); 4708 4709 ifp->if_ierrors++; 4710 4711 /* Try and reuse the exisitng mbuf. */ 4712 if (bnx_add_buf(sc, m, &sw_prod, 4713 &sw_chain_prod, &sw_prod_bseq)) { 4714 DBRUNIF(1, bnx_breakpoint(sc)); 4715 panic("%s: Double mbuf allocation " 4716 "failure!", 4717 device_xname(sc->bnx_dev)); 4718 } 4719 continue; 4720 } 4721 4722 /* Skip over the l2_fhdr when passing the data up 4723 * the stack. 4724 */ 4725 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4726 4727 /* Adjust the pckt length to match the received data. */ 4728 m->m_pkthdr.len = m->m_len = len; 4729 4730 /* Send the packet to the appropriate interface. */ 4731 m_set_rcvif(m, ifp); 4732 4733 DBRUN(BNX_VERBOSE_RECV, 4734 struct ether_header *eh; 4735 eh = mtod(m, struct ether_header *); 4736 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4737 __func__, ether_sprintf(eh->ether_dhost), 4738 ether_sprintf(eh->ether_shost), 4739 htons(eh->ether_type))); 4740 4741 /* Validate the checksum. */ 4742 4743 /* Check for an IP datagram. */ 4744 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4745 /* Check if the IP checksum is valid. */ 4746 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4747 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4748 #ifdef BNX_DEBUG 4749 else 4750 DBPRINT(sc, BNX_WARN_SEND, 4751 "%s(): Invalid IP checksum " 4752 "= 0x%04X!\n", 4753 __func__, 4754 l2fhdr->l2_fhdr_ip_xsum 4755 ); 4756 #endif 4757 } 4758 4759 /* Check for a valid TCP/UDP frame. */ 4760 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4761 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4762 /* Check for a good TCP/UDP checksum. */ 4763 if ((status & 4764 (L2_FHDR_ERRORS_TCP_XSUM | 4765 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4766 m->m_pkthdr.csum_flags |= 4767 M_CSUM_TCPv4 | 4768 M_CSUM_UDPv4; 4769 } else { 4770 DBPRINT(sc, BNX_WARN_SEND, 4771 "%s(): Invalid TCP/UDP " 4772 "checksum = 0x%04X!\n", 4773 __func__, 4774 l2fhdr->l2_fhdr_tcp_udp_xsum); 4775 } 4776 } 4777 4778 /* 4779 * If we received a packet with a vlan tag, 4780 * attach that information to the packet. 4781 */ 4782 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4783 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4784 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4785 } 4786 4787 /* Pass the mbuf off to the upper layers. */ 4788 4789 DBPRINT(sc, BNX_VERBOSE_RECV, 4790 "%s(): Passing received frame up.\n", __func__); 4791 if_percpuq_enqueue(ifp->if_percpuq, m); 4792 DBRUNIF(1, sc->rx_mbuf_alloc--); 4793 4794 } 4795 4796 sw_cons = NEXT_RX_BD(sw_cons); 4797 4798 /* Refresh hw_cons to see if there's new work */ 4799 if (sw_cons == hw_cons) { 4800 hw_cons = sc->hw_rx_cons = 4801 sblk->status_rx_quick_consumer_index0; 4802 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4803 USABLE_RX_BD_PER_PAGE) 4804 hw_cons++; 4805 } 4806 4807 /* Prevent speculative reads from getting ahead of 4808 * the status block. 4809 */ 4810 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4811 BUS_SPACE_BARRIER_READ); 4812 } 4813 4814 for (i = 0; i < RX_PAGES; i++) 4815 bus_dmamap_sync(sc->bnx_dmatag, 4816 sc->rx_bd_chain_map[i], 0, 4817 sc->rx_bd_chain_map[i]->dm_mapsize, 4818 BUS_DMASYNC_PREWRITE); 4819 4820 sc->rx_cons = sw_cons; 4821 sc->rx_prod = sw_prod; 4822 sc->rx_prod_bseq = sw_prod_bseq; 4823 4824 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4825 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4826 4827 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4828 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4829 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4830 } 4831 4832 /****************************************************************************/ 4833 /* Handles transmit completion interrupt events. */ 4834 /* */ 4835 /* Returns: */ 4836 /* Nothing. */ 4837 /****************************************************************************/ 4838 void 4839 bnx_tx_intr(struct bnx_softc *sc) 4840 { 4841 struct status_block *sblk = sc->status_block; 4842 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4843 struct bnx_pkt *pkt; 4844 bus_dmamap_t map; 4845 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4846 4847 DBRUNIF(1, sc->tx_interrupts++); 4848 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4849 BUS_DMASYNC_POSTREAD); 4850 4851 /* Get the hardware's view of the TX consumer index. */ 4852 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4853 4854 /* Skip to the next entry if this is a chain page pointer. */ 4855 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4856 hw_tx_cons++; 4857 4858 sw_tx_cons = sc->tx_cons; 4859 4860 /* Prevent speculative reads from getting ahead of the status block. */ 4861 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4862 BUS_SPACE_BARRIER_READ); 4863 4864 /* Cycle through any completed TX chain page entries. */ 4865 while (sw_tx_cons != hw_tx_cons) { 4866 #ifdef BNX_DEBUG 4867 struct tx_bd *txbd = NULL; 4868 #endif 4869 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4870 4871 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4872 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4873 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4874 4875 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4876 aprint_error_dev(sc->bnx_dev, 4877 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4878 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4879 4880 DBRUNIF(1, txbd = &sc->tx_bd_chain 4881 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4882 4883 DBRUNIF((txbd == NULL), 4884 aprint_error_dev(sc->bnx_dev, 4885 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4886 bnx_breakpoint(sc)); 4887 4888 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4889 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4890 4891 4892 mutex_enter(&sc->tx_pkt_mtx); 4893 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4894 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4895 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4896 mutex_exit(&sc->tx_pkt_mtx); 4897 /* 4898 * Free the associated mbuf. Remember 4899 * that only the last tx_bd of a packet 4900 * has an mbuf pointer and DMA map. 4901 */ 4902 map = pkt->pkt_dmamap; 4903 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4904 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4905 bus_dmamap_unload(sc->bnx_dmatag, map); 4906 4907 m_freem(pkt->pkt_mbuf); 4908 DBRUNIF(1, sc->tx_mbuf_alloc--); 4909 4910 ifp->if_opackets++; 4911 4912 mutex_enter(&sc->tx_pkt_mtx); 4913 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4914 } 4915 mutex_exit(&sc->tx_pkt_mtx); 4916 4917 sc->used_tx_bd--; 4918 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4919 __FILE__, __LINE__, sc->used_tx_bd); 4920 4921 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4922 4923 /* Refresh hw_cons to see if there's new work. */ 4924 hw_tx_cons = sc->hw_tx_cons = 4925 sblk->status_tx_quick_consumer_index0; 4926 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4927 USABLE_TX_BD_PER_PAGE) 4928 hw_tx_cons++; 4929 4930 /* Prevent speculative reads from getting ahead of 4931 * the status block. 4932 */ 4933 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4934 BUS_SPACE_BARRIER_READ); 4935 } 4936 4937 /* Clear the TX timeout timer. */ 4938 ifp->if_timer = 0; 4939 4940 /* Clear the tx hardware queue full flag. */ 4941 if (sc->used_tx_bd < sc->max_tx_bd) { 4942 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4943 aprint_debug_dev(sc->bnx_dev, 4944 "Open TX chain! %d/%d (used/total)\n", 4945 sc->used_tx_bd, sc->max_tx_bd)); 4946 ifp->if_flags &= ~IFF_OACTIVE; 4947 } 4948 4949 sc->tx_cons = sw_tx_cons; 4950 } 4951 4952 /****************************************************************************/ 4953 /* Disables interrupt generation. */ 4954 /* */ 4955 /* Returns: */ 4956 /* Nothing. */ 4957 /****************************************************************************/ 4958 void 4959 bnx_disable_intr(struct bnx_softc *sc) 4960 { 4961 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4962 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4963 } 4964 4965 /****************************************************************************/ 4966 /* Enables interrupt generation. */ 4967 /* */ 4968 /* Returns: */ 4969 /* Nothing. */ 4970 /****************************************************************************/ 4971 void 4972 bnx_enable_intr(struct bnx_softc *sc) 4973 { 4974 uint32_t val; 4975 4976 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4977 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4978 4979 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4980 sc->last_status_idx); 4981 4982 val = REG_RD(sc, BNX_HC_COMMAND); 4983 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4984 } 4985 4986 /****************************************************************************/ 4987 /* Handles controller initialization. */ 4988 /* */ 4989 /****************************************************************************/ 4990 int 4991 bnx_init(struct ifnet *ifp) 4992 { 4993 struct bnx_softc *sc = ifp->if_softc; 4994 uint32_t ether_mtu; 4995 int s, error = 0; 4996 4997 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4998 4999 s = splnet(); 5000 5001 bnx_stop(ifp, 0); 5002 5003 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 5004 aprint_error_dev(sc->bnx_dev, 5005 "Controller reset failed!\n"); 5006 goto bnx_init_exit; 5007 } 5008 5009 if ((error = bnx_chipinit(sc)) != 0) { 5010 aprint_error_dev(sc->bnx_dev, 5011 "Controller initialization failed!\n"); 5012 goto bnx_init_exit; 5013 } 5014 5015 if ((error = bnx_blockinit(sc)) != 0) { 5016 aprint_error_dev(sc->bnx_dev, 5017 "Block initialization failed!\n"); 5018 goto bnx_init_exit; 5019 } 5020 5021 /* Calculate and program the Ethernet MRU size. */ 5022 if (ifp->if_mtu <= ETHERMTU) { 5023 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 5024 sc->mbuf_alloc_size = MCLBYTES; 5025 } else { 5026 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 5027 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 5028 } 5029 5030 5031 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 5032 5033 /* 5034 * Program the MRU and enable Jumbo frame 5035 * support. 5036 */ 5037 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 5038 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 5039 5040 /* Calculate the RX Ethernet frame size for rx_bd's. */ 5041 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 5042 5043 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 5044 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 5045 sc->mbuf_alloc_size, sc->max_frame_size); 5046 5047 /* Program appropriate promiscuous/multicast filtering. */ 5048 bnx_iff(sc); 5049 5050 /* Init RX buffer descriptor chain. */ 5051 bnx_init_rx_chain(sc); 5052 5053 /* Init TX buffer descriptor chain. */ 5054 bnx_init_tx_chain(sc); 5055 5056 /* Enable host interrupts. */ 5057 bnx_enable_intr(sc); 5058 5059 bnx_ifmedia_upd(ifp); 5060 5061 SET(ifp->if_flags, IFF_RUNNING); 5062 CLR(ifp->if_flags, IFF_OACTIVE); 5063 5064 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5065 5066 bnx_init_exit: 5067 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5068 5069 splx(s); 5070 5071 return error; 5072 } 5073 5074 void 5075 bnx_mgmt_init(struct bnx_softc *sc) 5076 { 5077 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5078 uint32_t val; 5079 5080 /* Check if the driver is still running and bail out if it is. */ 5081 if (ifp->if_flags & IFF_RUNNING) 5082 goto bnx_mgmt_init_exit; 5083 5084 /* Initialize the on-boards CPUs */ 5085 bnx_init_cpus(sc); 5086 5087 val = (BCM_PAGE_BITS - 8) << 24; 5088 REG_WR(sc, BNX_RV2P_CONFIG, val); 5089 5090 /* Enable all critical blocks in the MAC. */ 5091 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5092 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5093 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5094 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5095 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5096 DELAY(20); 5097 5098 bnx_ifmedia_upd(ifp); 5099 5100 bnx_mgmt_init_exit: 5101 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5102 } 5103 5104 /****************************************************************************/ 5105 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5106 /* memory visible to the controller. */ 5107 /* */ 5108 /* Returns: */ 5109 /* 0 for success, positive value for failure. */ 5110 /****************************************************************************/ 5111 int 5112 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5113 { 5114 struct bnx_pkt *pkt; 5115 bus_dmamap_t map; 5116 struct tx_bd *txbd = NULL; 5117 uint16_t vlan_tag = 0, flags = 0; 5118 uint16_t chain_prod, prod; 5119 #ifdef BNX_DEBUG 5120 uint16_t debug_prod; 5121 #endif 5122 uint32_t addr, prod_bseq; 5123 int i, error; 5124 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 5125 bool remap = true; 5126 5127 mutex_enter(&sc->tx_pkt_mtx); 5128 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5129 if (pkt == NULL) { 5130 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5131 mutex_exit(&sc->tx_pkt_mtx); 5132 return ENETDOWN; 5133 } 5134 5135 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5136 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5137 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 5138 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5139 } 5140 5141 mutex_exit(&sc->tx_pkt_mtx); 5142 return ENOMEM; 5143 } 5144 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5145 mutex_exit(&sc->tx_pkt_mtx); 5146 5147 /* Transfer any checksum offload flags to the bd. */ 5148 if (m->m_pkthdr.csum_flags) { 5149 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5150 flags |= TX_BD_FLAGS_IP_CKSUM; 5151 if (m->m_pkthdr.csum_flags & 5152 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5153 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5154 } 5155 5156 /* Transfer any VLAN tags to the bd. */ 5157 if (vlan_has_tag(m)) { 5158 flags |= TX_BD_FLAGS_VLAN_TAG; 5159 vlan_tag = vlan_get_tag(m); 5160 } 5161 5162 /* Map the mbuf into DMAable memory. */ 5163 prod = sc->tx_prod; 5164 chain_prod = TX_CHAIN_IDX(prod); 5165 map = pkt->pkt_dmamap; 5166 5167 /* Map the mbuf into our DMA address space. */ 5168 retry: 5169 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5170 if (__predict_false(error)) { 5171 if (error == EFBIG) { 5172 if (remap == true) { 5173 struct mbuf *newm; 5174 5175 remap = false; 5176 newm = m_defrag(m, M_NOWAIT); 5177 if (newm != NULL) { 5178 m = newm; 5179 goto retry; 5180 } 5181 } 5182 } 5183 sc->tx_dma_map_failures++; 5184 goto maperr; 5185 } 5186 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5187 BUS_DMASYNC_PREWRITE); 5188 /* Make sure there's room in the chain */ 5189 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5190 goto nospace; 5191 5192 /* prod points to an empty tx_bd at this point. */ 5193 prod_bseq = sc->tx_prod_bseq; 5194 #ifdef BNX_DEBUG 5195 debug_prod = chain_prod; 5196 #endif 5197 DBPRINT(sc, BNX_INFO_SEND, 5198 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5199 "prod_bseq = 0x%08X\n", 5200 __func__, prod, chain_prod, prod_bseq); 5201 5202 /* 5203 * Cycle through each mbuf segment that makes up 5204 * the outgoing frame, gathering the mapping info 5205 * for that segment and creating a tx_bd for the 5206 * mbuf. 5207 */ 5208 for (i = 0; i < map->dm_nsegs ; i++) { 5209 chain_prod = TX_CHAIN_IDX(prod); 5210 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5211 5212 addr = (uint32_t)map->dm_segs[i].ds_addr; 5213 txbd->tx_bd_haddr_lo = addr; 5214 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5215 txbd->tx_bd_haddr_hi = addr; 5216 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5217 txbd->tx_bd_vlan_tag = vlan_tag; 5218 txbd->tx_bd_flags = flags; 5219 prod_bseq += map->dm_segs[i].ds_len; 5220 if (i == 0) 5221 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5222 prod = NEXT_TX_BD(prod); 5223 } 5224 5225 /* Set the END flag on the last TX buffer descriptor. */ 5226 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5227 5228 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5229 5230 DBPRINT(sc, BNX_INFO_SEND, 5231 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5232 "prod_bseq = 0x%08X\n", 5233 __func__, prod, chain_prod, prod_bseq); 5234 5235 pkt->pkt_mbuf = m; 5236 pkt->pkt_end_desc = chain_prod; 5237 5238 mutex_enter(&sc->tx_pkt_mtx); 5239 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5240 mutex_exit(&sc->tx_pkt_mtx); 5241 5242 sc->used_tx_bd += map->dm_nsegs; 5243 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5244 __FILE__, __LINE__, sc->used_tx_bd); 5245 5246 /* Update some debug statistics counters */ 5247 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5248 sc->tx_hi_watermark = sc->used_tx_bd); 5249 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5250 DBRUNIF(1, sc->tx_mbuf_alloc++); 5251 5252 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5253 map->dm_nsegs)); 5254 5255 /* prod points to the next free tx_bd at this point. */ 5256 sc->tx_prod = prod; 5257 sc->tx_prod_bseq = prod_bseq; 5258 5259 return 0; 5260 5261 5262 nospace: 5263 bus_dmamap_unload(sc->bnx_dmatag, map); 5264 maperr: 5265 mutex_enter(&sc->tx_pkt_mtx); 5266 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5267 mutex_exit(&sc->tx_pkt_mtx); 5268 5269 return ENOMEM; 5270 } 5271 5272 /****************************************************************************/ 5273 /* Main transmit routine. */ 5274 /* */ 5275 /* Returns: */ 5276 /* Nothing. */ 5277 /****************************************************************************/ 5278 void 5279 bnx_start(struct ifnet *ifp) 5280 { 5281 struct bnx_softc *sc = ifp->if_softc; 5282 struct mbuf *m_head = NULL; 5283 int count = 0; 5284 #ifdef BNX_DEBUG 5285 uint16_t tx_chain_prod; 5286 #endif 5287 5288 /* If there's no link or the transmit queue is empty then just exit. */ 5289 if (!sc->bnx_link 5290 ||(ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) { 5291 DBPRINT(sc, BNX_INFO_SEND, 5292 "%s(): output active or device not running.\n", __func__); 5293 goto bnx_start_exit; 5294 } 5295 5296 /* prod points to the next free tx_bd. */ 5297 #ifdef BNX_DEBUG 5298 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5299 #endif 5300 5301 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5302 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5303 "used_tx %d max_tx %d\n", 5304 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5305 sc->used_tx_bd, sc->max_tx_bd); 5306 5307 /* 5308 * Keep adding entries while there is space in the ring. 5309 */ 5310 while (sc->used_tx_bd < sc->max_tx_bd) { 5311 /* Check for any frames to send. */ 5312 IFQ_POLL(&ifp->if_snd, m_head); 5313 if (m_head == NULL) 5314 break; 5315 5316 /* 5317 * Pack the data into the transmit ring. If we 5318 * don't have room, set the OACTIVE flag to wait 5319 * for the NIC to drain the chain. 5320 */ 5321 if (bnx_tx_encap(sc, m_head)) { 5322 ifp->if_flags |= IFF_OACTIVE; 5323 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5324 "business! Total tx_bd used = %d\n", 5325 sc->used_tx_bd); 5326 break; 5327 } 5328 5329 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5330 count++; 5331 5332 /* Send a copy of the frame to any BPF listeners. */ 5333 bpf_mtap(ifp, m_head, BPF_D_OUT); 5334 } 5335 5336 if (count == 0) { 5337 /* no packets were dequeued */ 5338 DBPRINT(sc, BNX_VERBOSE_SEND, 5339 "%s(): No packets were dequeued\n", __func__); 5340 goto bnx_start_exit; 5341 } 5342 5343 /* Update the driver's counters. */ 5344 #ifdef BNX_DEBUG 5345 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5346 #endif 5347 5348 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5349 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5350 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5351 5352 /* Start the transmit. */ 5353 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5354 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5355 5356 /* Set the tx timeout. */ 5357 ifp->if_timer = BNX_TX_TIMEOUT; 5358 5359 bnx_start_exit: 5360 return; 5361 } 5362 5363 /****************************************************************************/ 5364 /* Handles any IOCTL calls from the operating system. */ 5365 /* */ 5366 /* Returns: */ 5367 /* 0 for success, positive value for failure. */ 5368 /****************************************************************************/ 5369 int 5370 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5371 { 5372 struct bnx_softc *sc = ifp->if_softc; 5373 struct ifreq *ifr = (struct ifreq *) data; 5374 struct mii_data *mii = &sc->bnx_mii; 5375 int s, error = 0; 5376 5377 s = splnet(); 5378 5379 switch (command) { 5380 case SIOCSIFFLAGS: 5381 if ((error = ifioctl_common(ifp, command, data)) != 0) 5382 break; 5383 /* XXX set an ifflags callback and let ether_ioctl 5384 * handle all of this. 5385 */ 5386 if (ISSET(ifp->if_flags, IFF_UP)) { 5387 if (ifp->if_flags & IFF_RUNNING) 5388 error = ENETRESET; 5389 else 5390 bnx_init(ifp); 5391 } else if (ifp->if_flags & IFF_RUNNING) 5392 bnx_stop(ifp, 1); 5393 break; 5394 5395 case SIOCSIFMEDIA: 5396 /* Flow control requires full-duplex mode. */ 5397 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5398 (ifr->ifr_media & IFM_FDX) == 0) 5399 ifr->ifr_media &= ~IFM_ETH_FMASK; 5400 5401 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5402 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5403 /* We can do both TXPAUSE and RXPAUSE. */ 5404 ifr->ifr_media |= 5405 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5406 } 5407 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5408 } 5409 /* FALLTHROUGH */ 5410 case SIOCGIFMEDIA: 5411 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5412 sc->bnx_phy_flags); 5413 5414 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5415 break; 5416 5417 default: 5418 error = ether_ioctl(ifp, command, data); 5419 } 5420 5421 if (error == ENETRESET) { 5422 if (ifp->if_flags & IFF_RUNNING) 5423 bnx_iff(sc); 5424 error = 0; 5425 } 5426 5427 splx(s); 5428 return error; 5429 } 5430 5431 /****************************************************************************/ 5432 /* Transmit timeout handler. */ 5433 /* */ 5434 /* Returns: */ 5435 /* Nothing. */ 5436 /****************************************************************************/ 5437 void 5438 bnx_watchdog(struct ifnet *ifp) 5439 { 5440 struct bnx_softc *sc = ifp->if_softc; 5441 5442 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5443 bnx_dump_status_block(sc)); 5444 /* 5445 * If we are in this routine because of pause frames, then 5446 * don't reset the hardware. 5447 */ 5448 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5449 return; 5450 5451 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5452 5453 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5454 5455 bnx_init(ifp); 5456 5457 ifp->if_oerrors++; 5458 } 5459 5460 /* 5461 * Interrupt handler. 5462 */ 5463 /****************************************************************************/ 5464 /* Main interrupt entry point. Verifies that the controller generated the */ 5465 /* interrupt and then calls a separate routine for handle the various */ 5466 /* interrupt causes (PHY, TX, RX). */ 5467 /* */ 5468 /* Returns: */ 5469 /* 0 for success, positive value for failure. */ 5470 /****************************************************************************/ 5471 int 5472 bnx_intr(void *xsc) 5473 { 5474 struct bnx_softc *sc = xsc; 5475 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5476 uint32_t status_attn_bits; 5477 uint16_t status_idx; 5478 const struct status_block *sblk; 5479 int rv = 0; 5480 5481 if (!device_is_active(sc->bnx_dev) || 5482 (ifp->if_flags & IFF_RUNNING) == 0) 5483 return 0; 5484 5485 DBRUNIF(1, sc->interrupts_generated++); 5486 5487 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5488 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5489 5490 sblk = sc->status_block; 5491 /* 5492 * If the hardware status block index 5493 * matches the last value read by the 5494 * driver and we haven't asserted our 5495 * interrupt then there's nothing to do. 5496 */ 5497 status_idx = sblk->status_idx; 5498 if ((status_idx != sc->last_status_idx) || 5499 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5500 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5501 rv = 1; 5502 5503 /* Ack the interrupt */ 5504 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5505 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5506 5507 status_attn_bits = sblk->status_attn_bits; 5508 5509 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5510 aprint_debug("Simulating unexpected status attention bit set."); 5511 status_attn_bits = status_attn_bits | 5512 STATUS_ATTN_BITS_PARITY_ERROR); 5513 5514 /* Was it a link change interrupt? */ 5515 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5516 (sblk->status_attn_bits_ack & 5517 STATUS_ATTN_BITS_LINK_STATE)) 5518 bnx_phy_intr(sc); 5519 5520 /* If any other attention is asserted then the chip is toast. */ 5521 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5522 (sblk->status_attn_bits_ack & 5523 ~STATUS_ATTN_BITS_LINK_STATE))) { 5524 DBRUN(sc->unexpected_attentions++); 5525 5526 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5527 sblk->status_attn_bits); 5528 5529 DBRUNIF((bnx_debug_unexpected_attention == 0), 5530 bnx_breakpoint(sc)); 5531 5532 bnx_init(ifp); 5533 goto out; 5534 } 5535 5536 /* Check for any completed RX frames. */ 5537 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5538 bnx_rx_intr(sc); 5539 5540 /* Check for any completed TX frames. */ 5541 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5542 bnx_tx_intr(sc); 5543 5544 /* 5545 * Save the status block index value for use during the 5546 * next interrupt. 5547 */ 5548 sc->last_status_idx = status_idx; 5549 5550 /* Start moving packets again */ 5551 if (ifp->if_flags & IFF_RUNNING) 5552 if_schedule_deferred_start(ifp); 5553 } 5554 5555 out: 5556 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5557 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5558 5559 return rv; 5560 } 5561 5562 /****************************************************************************/ 5563 /* Programs the various packet receive modes (broadcast and multicast). */ 5564 /* */ 5565 /* Returns: */ 5566 /* Nothing. */ 5567 /****************************************************************************/ 5568 void 5569 bnx_iff(struct bnx_softc *sc) 5570 { 5571 struct ethercom *ec = &sc->bnx_ec; 5572 struct ifnet *ifp = &ec->ec_if; 5573 struct ether_multi *enm; 5574 struct ether_multistep step; 5575 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5576 uint32_t rx_mode, sort_mode; 5577 int h, i; 5578 5579 /* Initialize receive mode default settings. */ 5580 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5581 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5582 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5583 ifp->if_flags &= ~IFF_ALLMULTI; 5584 5585 /* 5586 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5587 * be enbled. 5588 */ 5589 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5590 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5591 5592 /* 5593 * Check for promiscuous, all multicast, or selected 5594 * multicast address filtering. 5595 */ 5596 if (ifp->if_flags & IFF_PROMISC) { 5597 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5598 5599 ifp->if_flags |= IFF_ALLMULTI; 5600 /* Enable promiscuous mode. */ 5601 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5602 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5603 } else if (ifp->if_flags & IFF_ALLMULTI) { 5604 allmulti: 5605 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5606 5607 ifp->if_flags |= IFF_ALLMULTI; 5608 /* Enable all multicast addresses. */ 5609 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5610 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5611 0xffffffff); 5612 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5613 } else { 5614 /* Accept one or more multicast(s). */ 5615 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5616 5617 ETHER_FIRST_MULTI(step, ec, enm); 5618 while (enm != NULL) { 5619 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5620 ETHER_ADDR_LEN)) { 5621 goto allmulti; 5622 } 5623 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5624 0xFF; 5625 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5626 ETHER_NEXT_MULTI(step, enm); 5627 } 5628 5629 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5630 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5631 hashes[i]); 5632 5633 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5634 } 5635 5636 /* Only make changes if the recive mode has actually changed. */ 5637 if (rx_mode != sc->rx_mode) { 5638 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5639 rx_mode); 5640 5641 sc->rx_mode = rx_mode; 5642 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5643 } 5644 5645 /* Disable and clear the exisitng sort before enabling a new sort. */ 5646 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5647 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5648 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5649 } 5650 5651 /****************************************************************************/ 5652 /* Called periodically to updates statistics from the controllers */ 5653 /* statistics block. */ 5654 /* */ 5655 /* Returns: */ 5656 /* Nothing. */ 5657 /****************************************************************************/ 5658 void 5659 bnx_stats_update(struct bnx_softc *sc) 5660 { 5661 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5662 struct statistics_block *stats; 5663 5664 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5665 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5666 BUS_DMASYNC_POSTREAD); 5667 5668 stats = (struct statistics_block *)sc->stats_block; 5669 5670 /* 5671 * Update the interface statistics from the 5672 * hardware statistics. 5673 */ 5674 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5675 5676 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5677 (u_long)stats->stat_EtherStatsOverrsizePkts + 5678 (u_long)stats->stat_IfInMBUFDiscards + 5679 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5680 (u_long)stats->stat_Dot3StatsFCSErrors; 5681 5682 ifp->if_oerrors = (u_long) 5683 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5684 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5685 (u_long)stats->stat_Dot3StatsLateCollisions; 5686 5687 /* 5688 * Certain controllers don't report 5689 * carrier sense errors correctly. 5690 * See errata E11_5708CA0_1165. 5691 */ 5692 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5693 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5694 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5695 5696 /* 5697 * Update the sysctl statistics from the 5698 * hardware statistics. 5699 */ 5700 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5701 (uint64_t) stats->stat_IfHCInOctets_lo; 5702 5703 sc->stat_IfHCInBadOctets = 5704 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5705 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5706 5707 sc->stat_IfHCOutOctets = 5708 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5709 (uint64_t) stats->stat_IfHCOutOctets_lo; 5710 5711 sc->stat_IfHCOutBadOctets = 5712 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5713 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5714 5715 sc->stat_IfHCInUcastPkts = 5716 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5717 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5718 5719 sc->stat_IfHCInMulticastPkts = 5720 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5721 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5722 5723 sc->stat_IfHCInBroadcastPkts = 5724 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5725 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5726 5727 sc->stat_IfHCOutUcastPkts = 5728 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5729 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5730 5731 sc->stat_IfHCOutMulticastPkts = 5732 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5733 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5734 5735 sc->stat_IfHCOutBroadcastPkts = 5736 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5737 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5738 5739 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5740 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5741 5742 sc->stat_Dot3StatsCarrierSenseErrors = 5743 stats->stat_Dot3StatsCarrierSenseErrors; 5744 5745 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5746 5747 sc->stat_Dot3StatsAlignmentErrors = 5748 stats->stat_Dot3StatsAlignmentErrors; 5749 5750 sc->stat_Dot3StatsSingleCollisionFrames = 5751 stats->stat_Dot3StatsSingleCollisionFrames; 5752 5753 sc->stat_Dot3StatsMultipleCollisionFrames = 5754 stats->stat_Dot3StatsMultipleCollisionFrames; 5755 5756 sc->stat_Dot3StatsDeferredTransmissions = 5757 stats->stat_Dot3StatsDeferredTransmissions; 5758 5759 sc->stat_Dot3StatsExcessiveCollisions = 5760 stats->stat_Dot3StatsExcessiveCollisions; 5761 5762 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5763 5764 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5765 5766 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5767 5768 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5769 5770 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5771 5772 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5773 5774 sc->stat_EtherStatsPktsRx64Octets = 5775 stats->stat_EtherStatsPktsRx64Octets; 5776 5777 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5778 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5779 5780 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5781 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5782 5783 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5784 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5785 5786 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5787 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5788 5789 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5790 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5791 5792 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5793 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5794 5795 sc->stat_EtherStatsPktsTx64Octets = 5796 stats->stat_EtherStatsPktsTx64Octets; 5797 5798 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5799 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5800 5801 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5802 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5803 5804 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5805 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5806 5807 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5808 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5809 5810 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5811 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5812 5813 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5814 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5815 5816 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5817 5818 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5819 5820 sc->stat_OutXonSent = stats->stat_OutXonSent; 5821 5822 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5823 5824 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5825 5826 sc->stat_MacControlFramesReceived = 5827 stats->stat_MacControlFramesReceived; 5828 5829 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5830 5831 sc->stat_IfInFramesL2FilterDiscards = 5832 stats->stat_IfInFramesL2FilterDiscards; 5833 5834 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5835 5836 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5837 5838 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5839 5840 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5841 5842 sc->stat_CatchupInRuleCheckerDiscards = 5843 stats->stat_CatchupInRuleCheckerDiscards; 5844 5845 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5846 5847 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5848 5849 sc->stat_CatchupInRuleCheckerP4Hit = 5850 stats->stat_CatchupInRuleCheckerP4Hit; 5851 5852 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5853 } 5854 5855 void 5856 bnx_tick(void *xsc) 5857 { 5858 struct bnx_softc *sc = xsc; 5859 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5860 struct mii_data *mii; 5861 uint32_t msg; 5862 uint16_t prod, chain_prod; 5863 uint32_t prod_bseq; 5864 int s = splnet(); 5865 5866 /* Tell the firmware that the driver is still running. */ 5867 #ifdef BNX_DEBUG 5868 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5869 #else 5870 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5871 #endif 5872 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5873 5874 /* Update the statistics from the hardware statistics block. */ 5875 bnx_stats_update(sc); 5876 5877 /* Schedule the next tick. */ 5878 if (!sc->bnx_detaching) 5879 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5880 5881 if (sc->bnx_link) 5882 goto bnx_tick_exit; 5883 5884 mii = &sc->bnx_mii; 5885 mii_tick(mii); 5886 5887 /* Check if the link has come up. */ 5888 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5889 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5890 sc->bnx_link++; 5891 /* Now that link is up, handle any outstanding TX traffic. */ 5892 if_schedule_deferred_start(ifp); 5893 } 5894 5895 bnx_tick_exit: 5896 /* try to get more RX buffers, just in case */ 5897 prod = sc->rx_prod; 5898 prod_bseq = sc->rx_prod_bseq; 5899 chain_prod = RX_CHAIN_IDX(prod); 5900 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5901 sc->rx_prod = prod; 5902 sc->rx_prod_bseq = prod_bseq; 5903 5904 splx(s); 5905 return; 5906 } 5907 5908 /****************************************************************************/ 5909 /* BNX Debug Routines */ 5910 /****************************************************************************/ 5911 #ifdef BNX_DEBUG 5912 5913 /****************************************************************************/ 5914 /* Prints out information about an mbuf. */ 5915 /* */ 5916 /* Returns: */ 5917 /* Nothing. */ 5918 /****************************************************************************/ 5919 void 5920 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5921 { 5922 struct mbuf *mp = m; 5923 5924 if (m == NULL) { 5925 /* Index out of range. */ 5926 aprint_error("mbuf ptr is null!\n"); 5927 return; 5928 } 5929 5930 while (mp) { 5931 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5932 mp, mp->m_len); 5933 5934 if (mp->m_flags & M_EXT) 5935 aprint_debug("M_EXT "); 5936 if (mp->m_flags & M_PKTHDR) 5937 aprint_debug("M_PKTHDR "); 5938 aprint_debug("\n"); 5939 5940 if (mp->m_flags & M_EXT) 5941 aprint_debug("- m_ext: vaddr = %p, " 5942 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5943 5944 mp = mp->m_next; 5945 } 5946 } 5947 5948 /****************************************************************************/ 5949 /* Prints out the mbufs in the TX mbuf chain. */ 5950 /* */ 5951 /* Returns: */ 5952 /* Nothing. */ 5953 /****************************************************************************/ 5954 void 5955 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5956 { 5957 #if 0 5958 struct mbuf *m; 5959 int i; 5960 5961 aprint_debug_dev(sc->bnx_dev, 5962 "----------------------------" 5963 " tx mbuf data " 5964 "----------------------------\n"); 5965 5966 for (i = 0; i < count; i++) { 5967 m = sc->tx_mbuf_ptr[chain_prod]; 5968 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5969 bnx_dump_mbuf(sc, m); 5970 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5971 } 5972 5973 aprint_debug_dev(sc->bnx_dev, 5974 "--------------------------------------------" 5975 "----------------------------\n"); 5976 #endif 5977 } 5978 5979 /* 5980 * This routine prints the RX mbuf chain. 5981 */ 5982 void 5983 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5984 { 5985 struct mbuf *m; 5986 int i; 5987 5988 aprint_debug_dev(sc->bnx_dev, 5989 "----------------------------" 5990 " rx mbuf data " 5991 "----------------------------\n"); 5992 5993 for (i = 0; i < count; i++) { 5994 m = sc->rx_mbuf_ptr[chain_prod]; 5995 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 5996 bnx_dump_mbuf(sc, m); 5997 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 5998 } 5999 6000 6001 aprint_debug_dev(sc->bnx_dev, 6002 "--------------------------------------------" 6003 "----------------------------\n"); 6004 } 6005 6006 void 6007 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 6008 { 6009 if (idx > MAX_TX_BD) 6010 /* Index out of range. */ 6011 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6012 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6013 /* TX Chain page pointer. */ 6014 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 6015 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 6016 txbd->tx_bd_haddr_lo); 6017 else 6018 /* Normal tx_bd entry. */ 6019 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6020 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 6021 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6022 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6023 txbd->tx_bd_flags); 6024 } 6025 6026 void 6027 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 6028 { 6029 if (idx > MAX_RX_BD) 6030 /* Index out of range. */ 6031 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6032 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6033 /* TX Chain page pointer. */ 6034 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 6035 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 6036 rxbd->rx_bd_haddr_lo); 6037 else 6038 /* Normal tx_bd entry. */ 6039 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6040 "0x%08X, flags = 0x%08X\n", idx, 6041 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6042 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6043 } 6044 6045 void 6046 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6047 { 6048 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6049 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6050 "tcp_udp_xsum = 0x%04X\n", idx, 6051 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6052 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6053 l2fhdr->l2_fhdr_tcp_udp_xsum); 6054 } 6055 6056 /* 6057 * This routine prints the TX chain. 6058 */ 6059 void 6060 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 6061 { 6062 struct tx_bd *txbd; 6063 int i; 6064 6065 /* First some info about the tx_bd chain structure. */ 6066 aprint_debug_dev(sc->bnx_dev, 6067 "----------------------------" 6068 " tx_bd chain " 6069 "----------------------------\n"); 6070 6071 BNX_PRINTF(sc, 6072 "page size = 0x%08X, tx chain pages = 0x%08X\n", 6073 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6074 6075 BNX_PRINTF(sc, 6076 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6077 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6078 6079 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6080 6081 aprint_error_dev(sc->bnx_dev, "" 6082 "-----------------------------" 6083 " tx_bd data " 6084 "-----------------------------\n"); 6085 6086 /* Now print out the tx_bd's themselves. */ 6087 for (i = 0; i < count; i++) { 6088 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6089 bnx_dump_txbd(sc, tx_prod, txbd); 6090 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6091 } 6092 6093 aprint_debug_dev(sc->bnx_dev, 6094 "-----------------------------" 6095 "--------------" 6096 "-----------------------------\n"); 6097 } 6098 6099 /* 6100 * This routine prints the RX chain. 6101 */ 6102 void 6103 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6104 { 6105 struct rx_bd *rxbd; 6106 int i; 6107 6108 /* First some info about the tx_bd chain structure. */ 6109 aprint_debug_dev(sc->bnx_dev, 6110 "----------------------------" 6111 " rx_bd chain " 6112 "----------------------------\n"); 6113 6114 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6115 6116 BNX_PRINTF(sc, 6117 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6118 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6119 6120 BNX_PRINTF(sc, 6121 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6122 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6123 6124 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6125 6126 aprint_error_dev(sc->bnx_dev, 6127 "----------------------------" 6128 " rx_bd data " 6129 "----------------------------\n"); 6130 6131 /* Now print out the rx_bd's themselves. */ 6132 for (i = 0; i < count; i++) { 6133 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6134 bnx_dump_rxbd(sc, rx_prod, rxbd); 6135 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6136 } 6137 6138 aprint_debug_dev(sc->bnx_dev, 6139 "----------------------------" 6140 "--------------" 6141 "----------------------------\n"); 6142 } 6143 6144 /* 6145 * This routine prints the status block. 6146 */ 6147 void 6148 bnx_dump_status_block(struct bnx_softc *sc) 6149 { 6150 struct status_block *sblk; 6151 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6152 BUS_DMASYNC_POSTREAD); 6153 6154 sblk = sc->status_block; 6155 6156 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6157 "Status Block -----------------------------\n"); 6158 6159 BNX_PRINTF(sc, 6160 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6161 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6162 sblk->status_idx); 6163 6164 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6165 sblk->status_rx_quick_consumer_index0, 6166 sblk->status_tx_quick_consumer_index0); 6167 6168 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6169 6170 /* Theses indices are not used for normal L2 drivers. */ 6171 if (sblk->status_rx_quick_consumer_index1 || 6172 sblk->status_tx_quick_consumer_index1) 6173 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6174 sblk->status_rx_quick_consumer_index1, 6175 sblk->status_tx_quick_consumer_index1); 6176 6177 if (sblk->status_rx_quick_consumer_index2 || 6178 sblk->status_tx_quick_consumer_index2) 6179 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6180 sblk->status_rx_quick_consumer_index2, 6181 sblk->status_tx_quick_consumer_index2); 6182 6183 if (sblk->status_rx_quick_consumer_index3 || 6184 sblk->status_tx_quick_consumer_index3) 6185 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6186 sblk->status_rx_quick_consumer_index3, 6187 sblk->status_tx_quick_consumer_index3); 6188 6189 if (sblk->status_rx_quick_consumer_index4 || 6190 sblk->status_rx_quick_consumer_index5) 6191 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6192 sblk->status_rx_quick_consumer_index4, 6193 sblk->status_rx_quick_consumer_index5); 6194 6195 if (sblk->status_rx_quick_consumer_index6 || 6196 sblk->status_rx_quick_consumer_index7) 6197 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6198 sblk->status_rx_quick_consumer_index6, 6199 sblk->status_rx_quick_consumer_index7); 6200 6201 if (sblk->status_rx_quick_consumer_index8 || 6202 sblk->status_rx_quick_consumer_index9) 6203 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6204 sblk->status_rx_quick_consumer_index8, 6205 sblk->status_rx_quick_consumer_index9); 6206 6207 if (sblk->status_rx_quick_consumer_index10 || 6208 sblk->status_rx_quick_consumer_index11) 6209 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6210 sblk->status_rx_quick_consumer_index10, 6211 sblk->status_rx_quick_consumer_index11); 6212 6213 if (sblk->status_rx_quick_consumer_index12 || 6214 sblk->status_rx_quick_consumer_index13) 6215 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6216 sblk->status_rx_quick_consumer_index12, 6217 sblk->status_rx_quick_consumer_index13); 6218 6219 if (sblk->status_rx_quick_consumer_index14 || 6220 sblk->status_rx_quick_consumer_index15) 6221 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6222 sblk->status_rx_quick_consumer_index14, 6223 sblk->status_rx_quick_consumer_index15); 6224 6225 if (sblk->status_completion_producer_index || 6226 sblk->status_cmd_consumer_index) 6227 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6228 sblk->status_completion_producer_index, 6229 sblk->status_cmd_consumer_index); 6230 6231 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6232 "-----------------------------\n"); 6233 } 6234 6235 /* 6236 * This routine prints the statistics block. 6237 */ 6238 void 6239 bnx_dump_stats_block(struct bnx_softc *sc) 6240 { 6241 struct statistics_block *sblk; 6242 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6243 BUS_DMASYNC_POSTREAD); 6244 6245 sblk = sc->stats_block; 6246 6247 aprint_debug_dev(sc->bnx_dev, "" 6248 "-----------------------------" 6249 " Stats Block " 6250 "-----------------------------\n"); 6251 6252 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6253 "IfHcInBadOctets = 0x%08X:%08X\n", 6254 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6255 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6256 6257 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6258 "IfHcOutBadOctets = 0x%08X:%08X\n", 6259 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6260 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6261 6262 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6263 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6264 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6265 sblk->stat_IfHCInMulticastPkts_hi, 6266 sblk->stat_IfHCInMulticastPkts_lo); 6267 6268 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6269 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6270 sblk->stat_IfHCInBroadcastPkts_hi, 6271 sblk->stat_IfHCInBroadcastPkts_lo, 6272 sblk->stat_IfHCOutUcastPkts_hi, 6273 sblk->stat_IfHCOutUcastPkts_lo); 6274 6275 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6276 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6277 sblk->stat_IfHCOutMulticastPkts_hi, 6278 sblk->stat_IfHCOutMulticastPkts_lo, 6279 sblk->stat_IfHCOutBroadcastPkts_hi, 6280 sblk->stat_IfHCOutBroadcastPkts_lo); 6281 6282 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6283 BNX_PRINTF(sc, "0x%08X : " 6284 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6285 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6286 6287 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6288 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6289 sblk->stat_Dot3StatsCarrierSenseErrors); 6290 6291 if (sblk->stat_Dot3StatsFCSErrors) 6292 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6293 sblk->stat_Dot3StatsFCSErrors); 6294 6295 if (sblk->stat_Dot3StatsAlignmentErrors) 6296 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6297 sblk->stat_Dot3StatsAlignmentErrors); 6298 6299 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6300 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6301 sblk->stat_Dot3StatsSingleCollisionFrames); 6302 6303 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6304 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6305 sblk->stat_Dot3StatsMultipleCollisionFrames); 6306 6307 if (sblk->stat_Dot3StatsDeferredTransmissions) 6308 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6309 sblk->stat_Dot3StatsDeferredTransmissions); 6310 6311 if (sblk->stat_Dot3StatsExcessiveCollisions) 6312 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6313 sblk->stat_Dot3StatsExcessiveCollisions); 6314 6315 if (sblk->stat_Dot3StatsLateCollisions) 6316 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6317 sblk->stat_Dot3StatsLateCollisions); 6318 6319 if (sblk->stat_EtherStatsCollisions) 6320 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6321 sblk->stat_EtherStatsCollisions); 6322 6323 if (sblk->stat_EtherStatsFragments) 6324 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6325 sblk->stat_EtherStatsFragments); 6326 6327 if (sblk->stat_EtherStatsJabbers) 6328 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6329 sblk->stat_EtherStatsJabbers); 6330 6331 if (sblk->stat_EtherStatsUndersizePkts) 6332 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6333 sblk->stat_EtherStatsUndersizePkts); 6334 6335 if (sblk->stat_EtherStatsOverrsizePkts) 6336 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6337 sblk->stat_EtherStatsOverrsizePkts); 6338 6339 if (sblk->stat_EtherStatsPktsRx64Octets) 6340 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6341 sblk->stat_EtherStatsPktsRx64Octets); 6342 6343 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6344 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6345 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6346 6347 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6348 BNX_PRINTF(sc, "0x%08X : " 6349 "EtherStatsPktsRx128Octetsto255Octets\n", 6350 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6351 6352 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6353 BNX_PRINTF(sc, "0x%08X : " 6354 "EtherStatsPktsRx256Octetsto511Octets\n", 6355 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6356 6357 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6358 BNX_PRINTF(sc, "0x%08X : " 6359 "EtherStatsPktsRx512Octetsto1023Octets\n", 6360 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6361 6362 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6363 BNX_PRINTF(sc, "0x%08X : " 6364 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6365 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6366 6367 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6368 BNX_PRINTF(sc, "0x%08X : " 6369 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6370 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6371 6372 if (sblk->stat_EtherStatsPktsTx64Octets) 6373 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6374 sblk->stat_EtherStatsPktsTx64Octets); 6375 6376 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6377 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6378 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6379 6380 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6381 BNX_PRINTF(sc, "0x%08X : " 6382 "EtherStatsPktsTx128Octetsto255Octets\n", 6383 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6384 6385 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6386 BNX_PRINTF(sc, "0x%08X : " 6387 "EtherStatsPktsTx256Octetsto511Octets\n", 6388 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6389 6390 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6391 BNX_PRINTF(sc, "0x%08X : " 6392 "EtherStatsPktsTx512Octetsto1023Octets\n", 6393 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6394 6395 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6396 BNX_PRINTF(sc, "0x%08X : " 6397 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6398 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6399 6400 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6401 BNX_PRINTF(sc, "0x%08X : " 6402 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6403 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6404 6405 if (sblk->stat_XonPauseFramesReceived) 6406 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6407 sblk->stat_XonPauseFramesReceived); 6408 6409 if (sblk->stat_XoffPauseFramesReceived) 6410 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6411 sblk->stat_XoffPauseFramesReceived); 6412 6413 if (sblk->stat_OutXonSent) 6414 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6415 sblk->stat_OutXonSent); 6416 6417 if (sblk->stat_OutXoffSent) 6418 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6419 sblk->stat_OutXoffSent); 6420 6421 if (sblk->stat_FlowControlDone) 6422 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6423 sblk->stat_FlowControlDone); 6424 6425 if (sblk->stat_MacControlFramesReceived) 6426 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6427 sblk->stat_MacControlFramesReceived); 6428 6429 if (sblk->stat_XoffStateEntered) 6430 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6431 sblk->stat_XoffStateEntered); 6432 6433 if (sblk->stat_IfInFramesL2FilterDiscards) 6434 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6435 sblk->stat_IfInFramesL2FilterDiscards); 6436 6437 if (sblk->stat_IfInRuleCheckerDiscards) 6438 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6439 sblk->stat_IfInRuleCheckerDiscards); 6440 6441 if (sblk->stat_IfInFTQDiscards) 6442 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6443 sblk->stat_IfInFTQDiscards); 6444 6445 if (sblk->stat_IfInMBUFDiscards) 6446 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6447 sblk->stat_IfInMBUFDiscards); 6448 6449 if (sblk->stat_IfInRuleCheckerP4Hit) 6450 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6451 sblk->stat_IfInRuleCheckerP4Hit); 6452 6453 if (sblk->stat_CatchupInRuleCheckerDiscards) 6454 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6455 sblk->stat_CatchupInRuleCheckerDiscards); 6456 6457 if (sblk->stat_CatchupInFTQDiscards) 6458 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6459 sblk->stat_CatchupInFTQDiscards); 6460 6461 if (sblk->stat_CatchupInMBUFDiscards) 6462 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6463 sblk->stat_CatchupInMBUFDiscards); 6464 6465 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6466 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6467 sblk->stat_CatchupInRuleCheckerP4Hit); 6468 6469 aprint_debug_dev(sc->bnx_dev, 6470 "-----------------------------" 6471 "--------------" 6472 "-----------------------------\n"); 6473 } 6474 6475 void 6476 bnx_dump_driver_state(struct bnx_softc *sc) 6477 { 6478 aprint_debug_dev(sc->bnx_dev, 6479 "-----------------------------" 6480 " Driver State " 6481 "-----------------------------\n"); 6482 6483 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6484 "address\n", sc); 6485 6486 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6487 sc->status_block); 6488 6489 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6490 "address\n", sc->stats_block); 6491 6492 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6493 "address\n", sc->tx_bd_chain); 6494 6495 #if 0 6496 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6497 sc->rx_bd_chain); 6498 6499 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6500 sc->tx_mbuf_ptr); 6501 #endif 6502 6503 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6504 sc->rx_mbuf_ptr); 6505 6506 BNX_PRINTF(sc, 6507 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6508 sc->interrupts_generated); 6509 6510 BNX_PRINTF(sc, 6511 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6512 sc->rx_interrupts); 6513 6514 BNX_PRINTF(sc, 6515 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6516 sc->tx_interrupts); 6517 6518 BNX_PRINTF(sc, 6519 " 0x%08X - (sc->last_status_idx) status block index\n", 6520 sc->last_status_idx); 6521 6522 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6523 sc->tx_prod); 6524 6525 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6526 sc->tx_cons); 6527 6528 BNX_PRINTF(sc, 6529 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6530 sc->tx_prod_bseq); 6531 BNX_PRINTF(sc, 6532 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6533 sc->tx_mbuf_alloc); 6534 6535 BNX_PRINTF(sc, 6536 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6537 sc->used_tx_bd); 6538 6539 BNX_PRINTF(sc, 6540 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6541 sc->tx_hi_watermark, sc->max_tx_bd); 6542 6543 6544 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6545 sc->rx_prod); 6546 6547 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6548 sc->rx_cons); 6549 6550 BNX_PRINTF(sc, 6551 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6552 sc->rx_prod_bseq); 6553 6554 BNX_PRINTF(sc, 6555 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6556 sc->rx_mbuf_alloc); 6557 6558 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6559 sc->free_rx_bd); 6560 6561 BNX_PRINTF(sc, 6562 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6563 sc->rx_low_watermark, sc->max_rx_bd); 6564 6565 BNX_PRINTF(sc, 6566 " 0x%08X - (sc->mbuf_alloc_failed) " 6567 "mbuf alloc failures\n", 6568 sc->mbuf_alloc_failed); 6569 6570 BNX_PRINTF(sc, 6571 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6572 "simulated mbuf alloc failures\n", 6573 sc->mbuf_sim_alloc_failed); 6574 6575 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6576 "-----------------------------\n"); 6577 } 6578 6579 void 6580 bnx_dump_hw_state(struct bnx_softc *sc) 6581 { 6582 uint32_t val1; 6583 int i; 6584 6585 aprint_debug_dev(sc->bnx_dev, 6586 "----------------------------" 6587 " Hardware State " 6588 "----------------------------\n"); 6589 6590 BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); 6591 6592 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6593 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6594 val1, BNX_MISC_ENABLE_STATUS_BITS); 6595 6596 val1 = REG_RD(sc, BNX_DMA_STATUS); 6597 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6598 6599 val1 = REG_RD(sc, BNX_CTX_STATUS); 6600 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6601 6602 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6603 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6604 BNX_EMAC_STATUS); 6605 6606 val1 = REG_RD(sc, BNX_RPM_STATUS); 6607 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6608 6609 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6610 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6611 BNX_TBDR_STATUS); 6612 6613 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6614 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6615 BNX_TDMA_STATUS); 6616 6617 val1 = REG_RD(sc, BNX_HC_STATUS); 6618 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6619 6620 aprint_debug_dev(sc->bnx_dev, 6621 "----------------------------" 6622 "----------------" 6623 "----------------------------\n"); 6624 6625 aprint_debug_dev(sc->bnx_dev, 6626 "----------------------------" 6627 " Register Dump " 6628 "----------------------------\n"); 6629 6630 for (i = 0x400; i < 0x8000; i += 0x10) 6631 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6632 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6633 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6634 6635 aprint_debug_dev(sc->bnx_dev, 6636 "----------------------------" 6637 "----------------" 6638 "----------------------------\n"); 6639 } 6640 6641 void 6642 bnx_breakpoint(struct bnx_softc *sc) 6643 { 6644 /* Unreachable code to shut the compiler up about unused functions. */ 6645 if (0) { 6646 bnx_dump_txbd(sc, 0, NULL); 6647 bnx_dump_rxbd(sc, 0, NULL); 6648 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6649 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6650 bnx_dump_l2fhdr(sc, 0, NULL); 6651 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6652 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6653 bnx_dump_status_block(sc); 6654 bnx_dump_stats_block(sc); 6655 bnx_dump_driver_state(sc); 6656 bnx_dump_hw_state(sc); 6657 } 6658 6659 bnx_dump_driver_state(sc); 6660 /* Print the important status block fields. */ 6661 bnx_dump_status_block(sc); 6662 6663 #if 0 6664 /* Call the debugger. */ 6665 breakpoint(); 6666 #endif 6667 6668 return; 6669 } 6670 #endif 6671
Indexes created Tue Sep 23 14:10:03 GMT 2025