if_bnx.c revision 1.85
1 /* $NetBSD: if_bnx.c,v 1.85 2019/05/28 07:41:49 msaitoh Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.85 2019/05/28 07:41:49 msaitoh Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 device_t dev = sc->bnx_dev; 466 int i = 0; 467 468 aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 469 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 470 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 471 ? "Serdes " : "", sc->bnx_chipid); 472 473 /* Bus info. */ 474 if (sc->bnx_flags & BNX_PCIE_FLAG) { 475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); 476 switch (sc->link_speed) { 477 case 1: aprint_normal("2.5GT/s\n"); break; 478 case 2: aprint_normal("5GT/s\n"); break; 479 default: aprint_normal("Unknown link speed\n"); 480 } 481 } else { 482 aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n", 483 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 484 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 485 sc->bus_speed_mhz); 486 } 487 488 /* Firmware version and device features. */ 489 aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (", 490 sc->bnx_bc_ver, RX_PAGES, TX_PAGES); 491 492 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) { 493 if (i > 0) aprint_normal("|"); 494 aprint_normal("2.5G"); i++; 495 } 496 497 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 498 if (i > 0) aprint_normal("|"); 499 aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver); 500 } else { 501 aprint_normal(")\n"); 502 } 503 504 aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 505 sc->bnx_rx_quick_cons_trip_int, 506 sc->bnx_rx_quick_cons_trip, 507 sc->bnx_rx_ticks_int, 508 sc->bnx_rx_ticks, 509 sc->bnx_tx_quick_cons_trip_int, 510 sc->bnx_tx_quick_cons_trip, 511 sc->bnx_tx_ticks_int, 512 sc->bnx_tx_ticks); 513 } 514 515 516 /****************************************************************************/ 517 /* PCI Capabilities Probe Function. */ 518 /* */ 519 /* Walks the PCI capabiites list for the device to find what features are */ 520 /* supported. */ 521 /* */ 522 /* Returns: */ 523 /* None. */ 524 /****************************************************************************/ 525 static void 526 bnx_probe_pci_caps(struct bnx_softc *sc) 527 { 528 struct pci_attach_args *pa = &(sc->bnx_pa); 529 pcireg_t reg; 530 531 /* Check if PCI-X capability is enabled. */ 532 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 533 NULL) != 0) { 534 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 535 } 536 537 /* Check if PCIe capability is enabled. */ 538 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 539 NULL) != 0) { 540 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 541 reg + PCIE_LCSR); 542 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 543 "0x%08X\n", link_status); 544 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 546 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 547 sc->bnx_flags |= BNX_PCIE_FLAG; 548 } 549 550 /* Check if MSI capability is enabled. */ 551 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 552 NULL) != 0) 553 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 554 555 /* Check if MSI-X capability is enabled. */ 556 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 557 NULL) != 0) 558 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 559 } 560 561 562 /****************************************************************************/ 563 /* Device attach function. */ 564 /* */ 565 /* Allocates device resources, performs secondary chip identification, */ 566 /* resets and initializes the hardware, and initializes driver instance */ 567 /* variables. */ 568 /* */ 569 /* Returns: */ 570 /* 0 on success, positive value on failure. */ 571 /****************************************************************************/ 572 void 573 bnx_attach(device_t parent, device_t self, void *aux) 574 { 575 const struct bnx_product *bp; 576 struct bnx_softc *sc = device_private(self); 577 prop_dictionary_t dict; 578 struct pci_attach_args *pa = aux; 579 pci_chipset_tag_t pc = pa->pa_pc; 580 pci_intr_handle_t ih; 581 const char *intrstr = NULL; 582 uint32_t command; 583 struct ifnet *ifp; 584 struct mii_data * const mii = &sc->bnx_mii; 585 uint32_t val; 586 int mii_flags = MIIF_FORCEANEG; 587 pcireg_t memtype; 588 char intrbuf[PCI_INTRSTR_LEN]; 589 int i, j; 590 591 if (bnx_tx_pool == NULL) { 592 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT); 593 if (bnx_tx_pool != NULL) { 594 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 595 0, 0, 0, "bnxpkts", NULL, IPL_NET); 596 } else { 597 aprint_error(": can't alloc bnx_tx_pool\n"); 598 return; 599 } 600 } 601 602 bp = bnx_lookup(pa); 603 if (bp == NULL) 604 panic("unknown device"); 605 606 sc->bnx_dev = self; 607 608 aprint_naive("\n"); 609 aprint_normal(": %s\n", bp->bp_name); 610 611 sc->bnx_pa = *pa; 612 613 /* 614 * Map control/status registers. 615 */ 616 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 617 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 618 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 619 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 620 621 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 622 aprint_error_dev(sc->bnx_dev, 623 "failed to enable memory mapping!\n"); 624 return; 625 } 626 627 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 628 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 629 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 630 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 631 return; 632 } 633 634 if (pci_intr_map(pa, &ih)) { 635 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 636 goto bnx_attach_fail; 637 } 638 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 639 640 /* 641 * Configure byte swap and enable indirect register access. 642 * Rely on CPU to do target byte swapping on big endian systems. 643 * Access to registers outside of PCI configurtion space are not 644 * valid until this is done. 645 */ 646 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 647 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 648 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 649 650 /* Save ASIC revsion info. */ 651 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 652 653 /* 654 * Find the base address for shared memory access. 655 * Newer versions of bootcode use a signature and offset 656 * while older versions use a fixed address. 657 */ 658 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 659 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 660 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 661 (sc->bnx_pa.pa_function << 2)); 662 else 663 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 664 665 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 666 667 /* Set initial device and PHY flags */ 668 sc->bnx_flags = 0; 669 sc->bnx_phy_flags = 0; 670 671 /* Fetch the bootcode revision. */ 672 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 673 for (i = 0, j = 0; i < 3; i++) { 674 uint8_t num; 675 int k, skip0; 676 677 num = (uint8_t)(val >> (24 - (i * 8))); 678 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 679 if (num >= k || !skip0 || k == 1) { 680 sc->bnx_bc_ver[j++] = (num / k) + '0'; 681 skip0 = 0; 682 } 683 } 684 if (i != 2) 685 sc->bnx_bc_ver[j++] = '.'; 686 } 687 688 /* Check if any management firmware is enabled. */ 689 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 690 if (val & BNX_PORT_FEATURE_ASF_ENABLED) { 691 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 692 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 693 694 /* Allow time for firmware to enter the running state. */ 695 for (i = 0; i < 30; i++) { 696 val = REG_RD_IND(sc, sc->bnx_shmem_base + 697 BNX_BC_STATE_CONDITION); 698 if (val & BNX_CONDITION_MFW_RUN_MASK) 699 break; 700 DELAY(10000); 701 } 702 703 /* Check if management firmware is running. */ 704 val = REG_RD_IND(sc, sc->bnx_shmem_base + 705 BNX_BC_STATE_CONDITION); 706 val &= BNX_CONDITION_MFW_RUN_MASK; 707 if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) && 708 (val != BNX_CONDITION_MFW_RUN_NONE)) { 709 uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base + 710 BNX_MFW_VER_PTR); 711 712 /* Read the management firmware version string. */ 713 for (j = 0; j < 3; j++) { 714 val = bnx_reg_rd_ind(sc, addr + j * 4); 715 val = bswap32(val); 716 memcpy(&sc->bnx_mfw_ver[i], &val, 4); 717 i += 4; 718 } 719 } else { 720 /* May cause firmware synchronization timeouts. */ 721 BNX_PRINTF(sc, "%s(%d): Management firmware enabled " 722 "but not running!\n", __FILE__, __LINE__); 723 strcpy(sc->bnx_mfw_ver, "NOT RUNNING!"); 724 725 /* ToDo: Any action the driver should take? */ 726 } 727 } 728 729 bnx_probe_pci_caps(sc); 730 731 /* Get PCI bus information (speed and type). */ 732 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 733 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 734 uint32_t clkreg; 735 736 sc->bnx_flags |= BNX_PCIX_FLAG; 737 738 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 739 740 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 741 switch (clkreg) { 742 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 743 sc->bus_speed_mhz = 133; 744 break; 745 746 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 747 sc->bus_speed_mhz = 100; 748 break; 749 750 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 751 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 752 sc->bus_speed_mhz = 66; 753 break; 754 755 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 756 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 757 sc->bus_speed_mhz = 50; 758 break; 759 760 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 761 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 762 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 763 sc->bus_speed_mhz = 33; 764 break; 765 } 766 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 767 sc->bus_speed_mhz = 66; 768 else 769 sc->bus_speed_mhz = 33; 770 771 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 772 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 773 774 /* Reset the controller. */ 775 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 776 goto bnx_attach_fail; 777 778 /* Initialize the controller. */ 779 if (bnx_chipinit(sc)) { 780 aprint_error_dev(sc->bnx_dev, 781 "Controller initialization failed!\n"); 782 goto bnx_attach_fail; 783 } 784 785 /* Perform NVRAM test. */ 786 if (bnx_nvram_test(sc)) { 787 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 788 goto bnx_attach_fail; 789 } 790 791 /* Fetch the permanent Ethernet MAC address. */ 792 bnx_get_mac_addr(sc); 793 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 794 ether_sprintf(sc->eaddr)); 795 796 /* 797 * Trip points control how many BDs 798 * should be ready before generating an 799 * interrupt while ticks control how long 800 * a BD can sit in the chain before 801 * generating an interrupt. Set the default 802 * values for the RX and TX rings. 803 */ 804 805 #ifdef BNX_DEBUG 806 /* Force more frequent interrupts. */ 807 sc->bnx_tx_quick_cons_trip_int = 1; 808 sc->bnx_tx_quick_cons_trip = 1; 809 sc->bnx_tx_ticks_int = 0; 810 sc->bnx_tx_ticks = 0; 811 812 sc->bnx_rx_quick_cons_trip_int = 1; 813 sc->bnx_rx_quick_cons_trip = 1; 814 sc->bnx_rx_ticks_int = 0; 815 sc->bnx_rx_ticks = 0; 816 #else 817 sc->bnx_tx_quick_cons_trip_int = 20; 818 sc->bnx_tx_quick_cons_trip = 20; 819 sc->bnx_tx_ticks_int = 80; 820 sc->bnx_tx_ticks = 80; 821 822 sc->bnx_rx_quick_cons_trip_int = 6; 823 sc->bnx_rx_quick_cons_trip = 6; 824 sc->bnx_rx_ticks_int = 18; 825 sc->bnx_rx_ticks = 18; 826 #endif 827 828 /* Update statistics once every second. */ 829 sc->bnx_stats_ticks = 1000000 & 0xffff00; 830 831 /* Find the media type for the adapter. */ 832 bnx_get_media(sc); 833 834 /* 835 * Store config data needed by the PHY driver for 836 * backplane applications 837 */ 838 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 839 BNX_SHARED_HW_CFG_CONFIG); 840 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 841 BNX_PORT_HW_CFG_CONFIG); 842 843 /* Allocate DMA memory resources. */ 844 sc->bnx_dmatag = pa->pa_dmat; 845 if (bnx_dma_alloc(sc)) { 846 aprint_error_dev(sc->bnx_dev, 847 "DMA resource allocation failed!\n"); 848 goto bnx_attach_fail; 849 } 850 851 /* Initialize the ifnet interface. */ 852 ifp = &sc->bnx_ec.ec_if; 853 ifp->if_softc = sc; 854 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 855 ifp->if_ioctl = bnx_ioctl; 856 ifp->if_stop = bnx_stop; 857 ifp->if_start = bnx_start; 858 ifp->if_init = bnx_init; 859 ifp->if_watchdog = bnx_watchdog; 860 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 861 IFQ_SET_READY(&ifp->if_snd); 862 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 863 864 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 865 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 866 867 ifp->if_capabilities |= 868 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 869 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 870 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 871 872 /* create workqueue to handle packet allocations */ 873 if (workqueue_create(&sc->bnx_wq, device_xname(self), 874 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 875 aprint_error_dev(self, "failed to create workqueue\n"); 876 goto bnx_attach_fail; 877 } 878 879 mii->mii_ifp = ifp; 880 mii->mii_readreg = bnx_miibus_read_reg; 881 mii->mii_writereg = bnx_miibus_write_reg; 882 mii->mii_statchg = bnx_miibus_statchg; 883 884 /* Handle any special PHY initialization for SerDes PHYs. */ 885 bnx_init_media(sc); 886 887 sc->bnx_ec.ec_mii = mii; 888 ifmedia_init(&mii->mii_media, 0, bnx_ifmedia_upd, bnx_ifmedia_sts); 889 890 /* set phyflags and chipid before mii_attach() */ 891 dict = device_properties(self); 892 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 893 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 894 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 895 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 896 897 /* Print some useful adapter info */ 898 bnx_print_adapter_info(sc); 899 900 mii_flags |= MIIF_DOPAUSE; 901 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 902 mii_flags |= MIIF_HAVEFIBER; 903 mii_attach(self, mii, 0xffffffff, 904 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 905 906 if (LIST_EMPTY(&mii->mii_phys)) { 907 aprint_error_dev(self, "no PHY found!\n"); 908 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 909 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 910 } else 911 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 912 913 /* Attach to the Ethernet interface list. */ 914 if_attach(ifp); 915 if_deferred_start_init(ifp, NULL); 916 ether_ifattach(ifp, sc->eaddr); 917 918 callout_init(&sc->bnx_timeout, 0); 919 920 /* Hookup IRQ last. */ 921 sc->bnx_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bnx_intr, 922 sc, device_xname(self)); 923 if (sc->bnx_intrhand == NULL) { 924 aprint_error_dev(self, "couldn't establish interrupt"); 925 if (intrstr != NULL) 926 aprint_error(" at %s", intrstr); 927 aprint_error("\n"); 928 goto bnx_attach_fail; 929 } 930 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 931 932 if (pmf_device_register(self, NULL, NULL)) 933 pmf_class_network_register(self, ifp); 934 else 935 aprint_error_dev(self, "couldn't establish power handler\n"); 936 937 /* Print some important debugging info. */ 938 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 939 940 /* Get the firmware running so ASF still works. */ 941 bnx_mgmt_init(sc); 942 943 goto bnx_attach_exit; 944 945 bnx_attach_fail: 946 bnx_release_resources(sc); 947 948 bnx_attach_exit: 949 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 950 } 951 952 /****************************************************************************/ 953 /* Device detach function. */ 954 /* */ 955 /* Stops the controller, resets the controller, and releases resources. */ 956 /* */ 957 /* Returns: */ 958 /* 0 on success, positive value on failure. */ 959 /****************************************************************************/ 960 int 961 bnx_detach(device_t dev, int flags) 962 { 963 int s; 964 struct bnx_softc *sc; 965 struct ifnet *ifp; 966 967 sc = device_private(dev); 968 ifp = &sc->bnx_ec.ec_if; 969 970 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 971 972 /* Stop and reset the controller. */ 973 s = splnet(); 974 bnx_stop(ifp, 1); 975 splx(s); 976 977 pmf_device_deregister(dev); 978 callout_destroy(&sc->bnx_timeout); 979 ether_ifdetach(ifp); 980 workqueue_destroy(sc->bnx_wq); 981 982 /* Delete all remaining media. */ 983 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 984 985 if_detach(ifp); 986 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 987 988 /* Release all remaining resources. */ 989 bnx_release_resources(sc); 990 991 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 992 993 return 0; 994 } 995 996 /****************************************************************************/ 997 /* Indirect register read. */ 998 /* */ 999 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1000 /* configuration space. Using this mechanism avoids issues with posted */ 1001 /* reads but is much slower than memory-mapped I/O. */ 1002 /* */ 1003 /* Returns: */ 1004 /* The value of the register. */ 1005 /****************************************************************************/ 1006 uint32_t 1007 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 1008 { 1009 struct pci_attach_args *pa = &(sc->bnx_pa); 1010 1011 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1012 offset); 1013 #ifdef BNX_DEBUG 1014 { 1015 uint32_t val; 1016 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 1017 BNX_PCICFG_REG_WINDOW); 1018 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 1019 "val = 0x%08X\n", __func__, offset, val); 1020 return val; 1021 } 1022 #else 1023 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 1024 #endif 1025 } 1026 1027 /****************************************************************************/ 1028 /* Indirect register write. */ 1029 /* */ 1030 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1031 /* configuration space. Using this mechanism avoids issues with posted */ 1032 /* writes but is muchh slower than memory-mapped I/O. */ 1033 /* */ 1034 /* Returns: */ 1035 /* Nothing. */ 1036 /****************************************************************************/ 1037 void 1038 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 1039 { 1040 struct pci_attach_args *pa = &(sc->bnx_pa); 1041 1042 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 1043 __func__, offset, val); 1044 1045 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1046 offset); 1047 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 1048 } 1049 1050 /****************************************************************************/ 1051 /* Context memory write. */ 1052 /* */ 1053 /* The NetXtreme II controller uses context memory to track connection */ 1054 /* information for L2 and higher network protocols. */ 1055 /* */ 1056 /* Returns: */ 1057 /* Nothing. */ 1058 /****************************************************************************/ 1059 void 1060 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 1061 uint32_t ctx_val) 1062 { 1063 uint32_t idx, offset = ctx_offset + cid_addr; 1064 uint32_t val, retry_cnt = 5; 1065 1066 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1067 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1068 REG_WR(sc, BNX_CTX_CTX_CTRL, 1069 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 1070 1071 for (idx = 0; idx < retry_cnt; idx++) { 1072 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1073 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1074 break; 1075 DELAY(5); 1076 } 1077 1078 #if 0 1079 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1080 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1081 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1082 __FILE__, __LINE__, cid_addr, ctx_offset); 1083 #endif 1084 1085 } else { 1086 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1087 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1088 } 1089 } 1090 1091 /****************************************************************************/ 1092 /* PHY register read. */ 1093 /* */ 1094 /* Implements register reads on the MII bus. */ 1095 /* */ 1096 /* Returns: */ 1097 /* The value of the register. */ 1098 /****************************************************************************/ 1099 int 1100 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1101 { 1102 struct bnx_softc *sc = device_private(dev); 1103 uint32_t data; 1104 int i, rv = 0; 1105 1106 /* 1107 * The BCM5709S PHY is an IEEE Clause 45 PHY 1108 * with special mappings to work with IEEE 1109 * Clause 22 register accesses. 1110 */ 1111 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1112 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1113 reg += 0x10; 1114 } 1115 1116 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1117 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1118 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1119 1120 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1121 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1122 1123 DELAY(40); 1124 } 1125 1126 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1127 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1128 BNX_EMAC_MDIO_COMM_START_BUSY; 1129 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1130 1131 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1132 DELAY(10); 1133 1134 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1135 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1136 DELAY(5); 1137 1138 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1139 data &= BNX_EMAC_MDIO_COMM_DATA; 1140 1141 break; 1142 } 1143 } 1144 1145 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1146 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1147 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1148 rv = ETIMEDOUT; 1149 } else { 1150 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1151 *val = data & 0xffff; 1152 1153 DBPRINT(sc, BNX_EXCESSIVE, 1154 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1155 phy, (uint16_t) reg & 0xffff, *val); 1156 } 1157 1158 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1159 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1160 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1161 1162 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1163 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1164 1165 DELAY(40); 1166 } 1167 1168 return rv; 1169 } 1170 1171 /****************************************************************************/ 1172 /* PHY register write. */ 1173 /* */ 1174 /* Implements register writes on the MII bus. */ 1175 /* */ 1176 /* Returns: */ 1177 /* The value of the register. */ 1178 /****************************************************************************/ 1179 int 1180 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1181 { 1182 struct bnx_softc *sc = device_private(dev); 1183 uint32_t val1; 1184 int i, rv = 0; 1185 1186 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1187 "val = 0x%04hX\n", __func__, 1188 phy, (uint16_t) reg & 0xffff, val); 1189 1190 /* 1191 * The BCM5709S PHY is an IEEE Clause 45 PHY 1192 * with special mappings to work with IEEE 1193 * Clause 22 register accesses. 1194 */ 1195 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1196 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1197 reg += 0x10; 1198 } 1199 1200 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1201 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1202 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1203 1204 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1205 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1206 1207 DELAY(40); 1208 } 1209 1210 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1211 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1212 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1213 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1214 1215 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1216 DELAY(10); 1217 1218 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1219 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1220 DELAY(5); 1221 break; 1222 } 1223 } 1224 1225 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1226 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1227 __LINE__); 1228 rv = ETIMEDOUT; 1229 } 1230 1231 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1232 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1233 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1234 1235 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1236 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1237 1238 DELAY(40); 1239 } 1240 1241 return rv; 1242 } 1243 1244 /****************************************************************************/ 1245 /* MII bus status change. */ 1246 /* */ 1247 /* Called by the MII bus driver when the PHY establishes link to set the */ 1248 /* MAC interface registers. */ 1249 /* */ 1250 /* Returns: */ 1251 /* Nothing. */ 1252 /****************************************************************************/ 1253 void 1254 bnx_miibus_statchg(struct ifnet *ifp) 1255 { 1256 struct bnx_softc *sc = ifp->if_softc; 1257 struct mii_data *mii = &sc->bnx_mii; 1258 uint32_t rx_mode = sc->rx_mode; 1259 int val; 1260 1261 val = REG_RD(sc, BNX_EMAC_MODE); 1262 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1263 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1264 BNX_EMAC_MODE_25G); 1265 1266 /* 1267 * Get flow control negotiation result. 1268 */ 1269 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1270 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1271 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1272 mii->mii_media_active &= ~IFM_ETH_FMASK; 1273 } 1274 1275 /* Set MII or GMII interface based on the speed 1276 * negotiated by the PHY. 1277 */ 1278 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1279 case IFM_10_T: 1280 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1281 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1282 val |= BNX_EMAC_MODE_PORT_MII_10; 1283 break; 1284 } 1285 /* FALLTHROUGH */ 1286 case IFM_100_TX: 1287 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1288 val |= BNX_EMAC_MODE_PORT_MII; 1289 break; 1290 case IFM_2500_SX: 1291 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1292 val |= BNX_EMAC_MODE_25G; 1293 /* FALLTHROUGH */ 1294 case IFM_1000_T: 1295 case IFM_1000_SX: 1296 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1297 val |= BNX_EMAC_MODE_PORT_GMII; 1298 break; 1299 default: 1300 val |= BNX_EMAC_MODE_PORT_GMII; 1301 break; 1302 } 1303 1304 /* Set half or full duplex based on the duplicity 1305 * negotiated by the PHY. 1306 */ 1307 if ((mii->mii_media_active & IFM_HDX) != 0) { 1308 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1309 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1310 } else 1311 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1312 1313 REG_WR(sc, BNX_EMAC_MODE, val); 1314 1315 /* 1316 * 802.3x flow control 1317 */ 1318 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1319 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1320 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1321 } else { 1322 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1323 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1324 } 1325 1326 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1327 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1328 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1329 } else { 1330 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1331 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1332 } 1333 1334 /* Only make changes if the recive mode has actually changed. */ 1335 if (rx_mode != sc->rx_mode) { 1336 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1337 rx_mode); 1338 1339 sc->rx_mode = rx_mode; 1340 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1341 1342 bnx_init_rx_context(sc); 1343 } 1344 } 1345 1346 /****************************************************************************/ 1347 /* Acquire NVRAM lock. */ 1348 /* */ 1349 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1350 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1351 /* for use by the driver. */ 1352 /* */ 1353 /* Returns: */ 1354 /* 0 on success, positive value on failure. */ 1355 /****************************************************************************/ 1356 int 1357 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1358 { 1359 uint32_t val; 1360 int j; 1361 1362 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1363 1364 /* Request access to the flash interface. */ 1365 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1366 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1367 val = REG_RD(sc, BNX_NVM_SW_ARB); 1368 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1369 break; 1370 1371 DELAY(5); 1372 } 1373 1374 if (j >= NVRAM_TIMEOUT_COUNT) { 1375 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1376 return EBUSY; 1377 } 1378 1379 return 0; 1380 } 1381 1382 /****************************************************************************/ 1383 /* Release NVRAM lock. */ 1384 /* */ 1385 /* When the caller is finished accessing NVRAM the lock must be released. */ 1386 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1387 /* for use by the driver. */ 1388 /* */ 1389 /* Returns: */ 1390 /* 0 on success, positive value on failure. */ 1391 /****************************************************************************/ 1392 int 1393 bnx_release_nvram_lock(struct bnx_softc *sc) 1394 { 1395 int j; 1396 uint32_t val; 1397 1398 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1399 1400 /* Relinquish nvram interface. */ 1401 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1402 1403 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1404 val = REG_RD(sc, BNX_NVM_SW_ARB); 1405 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1406 break; 1407 1408 DELAY(5); 1409 } 1410 1411 if (j >= NVRAM_TIMEOUT_COUNT) { 1412 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1413 return EBUSY; 1414 } 1415 1416 return 0; 1417 } 1418 1419 #ifdef BNX_NVRAM_WRITE_SUPPORT 1420 /****************************************************************************/ 1421 /* Enable NVRAM write access. */ 1422 /* */ 1423 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1424 /* */ 1425 /* Returns: */ 1426 /* 0 on success, positive value on failure. */ 1427 /****************************************************************************/ 1428 int 1429 bnx_enable_nvram_write(struct bnx_softc *sc) 1430 { 1431 uint32_t val; 1432 1433 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1434 1435 val = REG_RD(sc, BNX_MISC_CFG); 1436 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1437 1438 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1439 int j; 1440 1441 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1442 REG_WR(sc, BNX_NVM_COMMAND, 1443 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1444 1445 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1446 DELAY(5); 1447 1448 val = REG_RD(sc, BNX_NVM_COMMAND); 1449 if (val & BNX_NVM_COMMAND_DONE) 1450 break; 1451 } 1452 1453 if (j >= NVRAM_TIMEOUT_COUNT) { 1454 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1455 return EBUSY; 1456 } 1457 } 1458 1459 return 0; 1460 } 1461 1462 /****************************************************************************/ 1463 /* Disable NVRAM write access. */ 1464 /* */ 1465 /* When the caller is finished writing to NVRAM write access must be */ 1466 /* disabled. */ 1467 /* */ 1468 /* Returns: */ 1469 /* Nothing. */ 1470 /****************************************************************************/ 1471 void 1472 bnx_disable_nvram_write(struct bnx_softc *sc) 1473 { 1474 uint32_t val; 1475 1476 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1477 1478 val = REG_RD(sc, BNX_MISC_CFG); 1479 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1480 } 1481 #endif 1482 1483 /****************************************************************************/ 1484 /* Enable NVRAM access. */ 1485 /* */ 1486 /* Before accessing NVRAM for read or write operations the caller must */ 1487 /* enabled NVRAM access. */ 1488 /* */ 1489 /* Returns: */ 1490 /* Nothing. */ 1491 /****************************************************************************/ 1492 void 1493 bnx_enable_nvram_access(struct bnx_softc *sc) 1494 { 1495 uint32_t val; 1496 1497 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1498 1499 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1500 /* Enable both bits, even on read. */ 1501 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1502 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1503 } 1504 1505 /****************************************************************************/ 1506 /* Disable NVRAM access. */ 1507 /* */ 1508 /* When the caller is finished accessing NVRAM access must be disabled. */ 1509 /* */ 1510 /* Returns: */ 1511 /* Nothing. */ 1512 /****************************************************************************/ 1513 void 1514 bnx_disable_nvram_access(struct bnx_softc *sc) 1515 { 1516 uint32_t val; 1517 1518 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1519 1520 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1521 1522 /* Disable both bits, even after read. */ 1523 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1524 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1525 } 1526 1527 #ifdef BNX_NVRAM_WRITE_SUPPORT 1528 /****************************************************************************/ 1529 /* Erase NVRAM page before writing. */ 1530 /* */ 1531 /* Non-buffered flash parts require that a page be erased before it is */ 1532 /* written. */ 1533 /* */ 1534 /* Returns: */ 1535 /* 0 on success, positive value on failure. */ 1536 /****************************************************************************/ 1537 int 1538 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1539 { 1540 uint32_t cmd; 1541 int j; 1542 1543 /* Buffered flash doesn't require an erase. */ 1544 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1545 return 0; 1546 1547 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1548 1549 /* Build an erase command. */ 1550 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1551 BNX_NVM_COMMAND_DOIT; 1552 1553 /* 1554 * Clear the DONE bit separately, set the NVRAM address to erase, 1555 * and issue the erase command. 1556 */ 1557 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1558 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1559 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1560 1561 /* Wait for completion. */ 1562 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1563 uint32_t val; 1564 1565 DELAY(5); 1566 1567 val = REG_RD(sc, BNX_NVM_COMMAND); 1568 if (val & BNX_NVM_COMMAND_DONE) 1569 break; 1570 } 1571 1572 if (j >= NVRAM_TIMEOUT_COUNT) { 1573 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1574 return EBUSY; 1575 } 1576 1577 return 0; 1578 } 1579 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1580 1581 /****************************************************************************/ 1582 /* Read a dword (32 bits) from NVRAM. */ 1583 /* */ 1584 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1585 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1586 /* */ 1587 /* Returns: */ 1588 /* 0 on success and the 32 bit value read, positive value on failure. */ 1589 /****************************************************************************/ 1590 int 1591 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1592 uint8_t *ret_val, uint32_t cmd_flags) 1593 { 1594 uint32_t cmd; 1595 int i, rc = 0; 1596 1597 /* Build the command word. */ 1598 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1599 1600 /* Calculate the offset for buffered flash if translation is used. */ 1601 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1602 offset = ((offset / sc->bnx_flash_info->page_size) << 1603 sc->bnx_flash_info->page_bits) + 1604 (offset % sc->bnx_flash_info->page_size); 1605 } 1606 1607 /* 1608 * Clear the DONE bit separately, set the address to read, 1609 * and issue the read. 1610 */ 1611 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1612 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1613 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1614 1615 /* Wait for completion. */ 1616 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1617 uint32_t val; 1618 1619 DELAY(5); 1620 1621 val = REG_RD(sc, BNX_NVM_COMMAND); 1622 if (val & BNX_NVM_COMMAND_DONE) { 1623 val = REG_RD(sc, BNX_NVM_READ); 1624 1625 val = be32toh(val); 1626 memcpy(ret_val, &val, 4); 1627 break; 1628 } 1629 } 1630 1631 /* Check for errors. */ 1632 if (i >= NVRAM_TIMEOUT_COUNT) { 1633 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1634 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1635 rc = EBUSY; 1636 } 1637 1638 return rc; 1639 } 1640 1641 #ifdef BNX_NVRAM_WRITE_SUPPORT 1642 /****************************************************************************/ 1643 /* Write a dword (32 bits) to NVRAM. */ 1644 /* */ 1645 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1646 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1647 /* enabled NVRAM write access. */ 1648 /* */ 1649 /* Returns: */ 1650 /* 0 on success, positive value on failure. */ 1651 /****************************************************************************/ 1652 int 1653 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1654 uint32_t cmd_flags) 1655 { 1656 uint32_t cmd, val32; 1657 int j; 1658 1659 /* Build the command word. */ 1660 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1661 1662 /* Calculate the offset for buffered flash if translation is used. */ 1663 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1664 offset = ((offset / sc->bnx_flash_info->page_size) << 1665 sc->bnx_flash_info->page_bits) + 1666 (offset % sc->bnx_flash_info->page_size); 1667 } 1668 1669 /* 1670 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1671 * set the NVRAM address to write, and issue the write command 1672 */ 1673 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1674 memcpy(&val32, val, 4); 1675 val32 = htobe32(val32); 1676 REG_WR(sc, BNX_NVM_WRITE, val32); 1677 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1678 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1679 1680 /* Wait for completion. */ 1681 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1682 DELAY(5); 1683 1684 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1685 break; 1686 } 1687 if (j >= NVRAM_TIMEOUT_COUNT) { 1688 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1689 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1690 return EBUSY; 1691 } 1692 1693 return 0; 1694 } 1695 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1696 1697 /****************************************************************************/ 1698 /* Initialize NVRAM access. */ 1699 /* */ 1700 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1701 /* access that device. */ 1702 /* */ 1703 /* Returns: */ 1704 /* 0 on success, positive value on failure. */ 1705 /****************************************************************************/ 1706 int 1707 bnx_init_nvram(struct bnx_softc *sc) 1708 { 1709 uint32_t val; 1710 int j, entry_count, rc = 0; 1711 struct flash_spec *flash; 1712 1713 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1714 1715 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1716 sc->bnx_flash_info = &flash_5709; 1717 goto bnx_init_nvram_get_flash_size; 1718 } 1719 1720 /* Determine the selected interface. */ 1721 val = REG_RD(sc, BNX_NVM_CFG1); 1722 1723 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1724 1725 /* 1726 * Flash reconfiguration is required to support additional 1727 * NVRAM devices not directly supported in hardware. 1728 * Check if the flash interface was reconfigured 1729 * by the bootcode. 1730 */ 1731 1732 if (val & 0x40000000) { 1733 /* Flash interface reconfigured by bootcode. */ 1734 1735 DBPRINT(sc, BNX_INFO_LOAD, 1736 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1737 1738 for (j = 0, flash = &flash_table[0]; j < entry_count; 1739 j++, flash++) { 1740 if ((val & FLASH_BACKUP_STRAP_MASK) == 1741 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1742 sc->bnx_flash_info = flash; 1743 break; 1744 } 1745 } 1746 } else { 1747 /* Flash interface not yet reconfigured. */ 1748 uint32_t mask; 1749 1750 DBPRINT(sc, BNX_INFO_LOAD, 1751 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1752 1753 if (val & (1 << 23)) 1754 mask = FLASH_BACKUP_STRAP_MASK; 1755 else 1756 mask = FLASH_STRAP_MASK; 1757 1758 /* Look for the matching NVRAM device configuration data. */ 1759 for (j = 0, flash = &flash_table[0]; j < entry_count; 1760 j++, flash++) { 1761 /* Check if the dev matches any of the known devices. */ 1762 if ((val & mask) == (flash->strapping & mask)) { 1763 /* Found a device match. */ 1764 sc->bnx_flash_info = flash; 1765 1766 /* Request access to the flash interface. */ 1767 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1768 return rc; 1769 1770 /* Reconfigure the flash interface. */ 1771 bnx_enable_nvram_access(sc); 1772 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1773 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1774 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1775 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1776 bnx_disable_nvram_access(sc); 1777 bnx_release_nvram_lock(sc); 1778 1779 break; 1780 } 1781 } 1782 } 1783 1784 /* Check if a matching device was found. */ 1785 if (j == entry_count) { 1786 sc->bnx_flash_info = NULL; 1787 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1788 __FILE__, __LINE__); 1789 rc = ENODEV; 1790 } 1791 1792 bnx_init_nvram_get_flash_size: 1793 /* Write the flash config data to the shared memory interface. */ 1794 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1795 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1796 if (val) 1797 sc->bnx_flash_size = val; 1798 else 1799 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1800 1801 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1802 "0x%08X\n", sc->bnx_flash_info->total_size); 1803 1804 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1805 1806 return rc; 1807 } 1808 1809 /****************************************************************************/ 1810 /* Read an arbitrary range of data from NVRAM. */ 1811 /* */ 1812 /* Prepares the NVRAM interface for access and reads the requested data */ 1813 /* into the supplied buffer. */ 1814 /* */ 1815 /* Returns: */ 1816 /* 0 on success and the data read, positive value on failure. */ 1817 /****************************************************************************/ 1818 int 1819 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1820 int buf_size) 1821 { 1822 int rc = 0; 1823 uint32_t cmd_flags, offset32, len32, extra; 1824 1825 if (buf_size == 0) 1826 return 0; 1827 1828 /* Request access to the flash interface. */ 1829 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1830 return rc; 1831 1832 /* Enable access to flash interface */ 1833 bnx_enable_nvram_access(sc); 1834 1835 len32 = buf_size; 1836 offset32 = offset; 1837 extra = 0; 1838 1839 cmd_flags = 0; 1840 1841 if (offset32 & 3) { 1842 uint8_t buf[4]; 1843 uint32_t pre_len; 1844 1845 offset32 &= ~3; 1846 pre_len = 4 - (offset & 3); 1847 1848 if (pre_len >= len32) { 1849 pre_len = len32; 1850 cmd_flags = 1851 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1852 } else 1853 cmd_flags = BNX_NVM_COMMAND_FIRST; 1854 1855 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1856 1857 if (rc) 1858 return rc; 1859 1860 memcpy(ret_buf, buf + (offset & 3), pre_len); 1861 1862 offset32 += 4; 1863 ret_buf += pre_len; 1864 len32 -= pre_len; 1865 } 1866 1867 if (len32 & 3) { 1868 extra = 4 - (len32 & 3); 1869 len32 = (len32 + 4) & ~3; 1870 } 1871 1872 if (len32 == 4) { 1873 uint8_t buf[4]; 1874 1875 if (cmd_flags) 1876 cmd_flags = BNX_NVM_COMMAND_LAST; 1877 else 1878 cmd_flags = 1879 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1880 1881 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1882 1883 memcpy(ret_buf, buf, 4 - extra); 1884 } else if (len32 > 0) { 1885 uint8_t buf[4]; 1886 1887 /* Read the first word. */ 1888 if (cmd_flags) 1889 cmd_flags = 0; 1890 else 1891 cmd_flags = BNX_NVM_COMMAND_FIRST; 1892 1893 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1894 1895 /* Advance to the next dword. */ 1896 offset32 += 4; 1897 ret_buf += 4; 1898 len32 -= 4; 1899 1900 while (len32 > 4 && rc == 0) { 1901 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1902 1903 /* Advance to the next dword. */ 1904 offset32 += 4; 1905 ret_buf += 4; 1906 len32 -= 4; 1907 } 1908 1909 if (rc) 1910 return rc; 1911 1912 cmd_flags = BNX_NVM_COMMAND_LAST; 1913 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1914 1915 memcpy(ret_buf, buf, 4 - extra); 1916 } 1917 1918 /* Disable access to flash interface and release the lock. */ 1919 bnx_disable_nvram_access(sc); 1920 bnx_release_nvram_lock(sc); 1921 1922 return rc; 1923 } 1924 1925 #ifdef BNX_NVRAM_WRITE_SUPPORT 1926 /****************************************************************************/ 1927 /* Write an arbitrary range of data from NVRAM. */ 1928 /* */ 1929 /* Prepares the NVRAM interface for write access and writes the requested */ 1930 /* data from the supplied buffer. The caller is responsible for */ 1931 /* calculating any appropriate CRCs. */ 1932 /* */ 1933 /* Returns: */ 1934 /* 0 on success, positive value on failure. */ 1935 /****************************************************************************/ 1936 int 1937 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1938 int buf_size) 1939 { 1940 uint32_t written, offset32, len32; 1941 uint8_t *buf, start[4], end[4]; 1942 int rc = 0; 1943 int align_start, align_end; 1944 1945 buf = data_buf; 1946 offset32 = offset; 1947 len32 = buf_size; 1948 align_start = align_end = 0; 1949 1950 if ((align_start = (offset32 & 3))) { 1951 offset32 &= ~3; 1952 len32 += align_start; 1953 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1954 return rc; 1955 } 1956 1957 if (len32 & 3) { 1958 if ((len32 > 4) || !align_start) { 1959 align_end = 4 - (len32 & 3); 1960 len32 += align_end; 1961 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1962 end, 4))) 1963 return rc; 1964 } 1965 } 1966 1967 if (align_start || align_end) { 1968 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1969 if (buf == NULL) 1970 return ENOMEM; 1971 1972 if (align_start) 1973 memcpy(buf, start, 4); 1974 1975 if (align_end) 1976 memcpy(buf + len32 - 4, end, 4); 1977 1978 memcpy(buf + align_start, data_buf, buf_size); 1979 } 1980 1981 written = 0; 1982 while ((written < len32) && (rc == 0)) { 1983 uint32_t page_start, page_end, data_start, data_end; 1984 uint32_t addr, cmd_flags; 1985 int i; 1986 uint8_t flash_buffer[264]; 1987 1988 /* Find the page_start addr */ 1989 page_start = offset32 + written; 1990 page_start -= (page_start % sc->bnx_flash_info->page_size); 1991 /* Find the page_end addr */ 1992 page_end = page_start + sc->bnx_flash_info->page_size; 1993 /* Find the data_start addr */ 1994 data_start = (written == 0) ? offset32 : page_start; 1995 /* Find the data_end addr */ 1996 data_end = (page_end > offset32 + len32) ? 1997 (offset32 + len32) : page_end; 1998 1999 /* Request access to the flash interface. */ 2000 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 2001 goto nvram_write_end; 2002 2003 /* Enable access to flash interface */ 2004 bnx_enable_nvram_access(sc); 2005 2006 cmd_flags = BNX_NVM_COMMAND_FIRST; 2007 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2008 int j; 2009 2010 /* Read the whole page into the buffer 2011 * (non-buffer flash only) */ 2012 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 2013 if (j == (sc->bnx_flash_info->page_size - 4)) 2014 cmd_flags |= BNX_NVM_COMMAND_LAST; 2015 2016 rc = bnx_nvram_read_dword(sc, 2017 page_start + j, 2018 &flash_buffer[j], 2019 cmd_flags); 2020 2021 if (rc) 2022 goto nvram_write_end; 2023 2024 cmd_flags = 0; 2025 } 2026 } 2027 2028 /* Enable writes to flash interface (unlock write-protect) */ 2029 if ((rc = bnx_enable_nvram_write(sc)) != 0) 2030 goto nvram_write_end; 2031 2032 /* Erase the page */ 2033 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 2034 goto nvram_write_end; 2035 2036 /* Re-enable the write again for the actual write */ 2037 bnx_enable_nvram_write(sc); 2038 2039 /* Loop to write back the buffer data from page_start to 2040 * data_start */ 2041 i = 0; 2042 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2043 for (addr = page_start; addr < data_start; 2044 addr += 4, i += 4) { 2045 2046 rc = bnx_nvram_write_dword(sc, addr, 2047 &flash_buffer[i], cmd_flags); 2048 2049 if (rc != 0) 2050 goto nvram_write_end; 2051 2052 cmd_flags = 0; 2053 } 2054 } 2055 2056 /* Loop to write the new data from data_start to data_end */ 2057 for (addr = data_start; addr < data_end; addr += 4, i++) { 2058 if ((addr == page_end - 4) || 2059 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 2060 && (addr == data_end - 4))) { 2061 2062 cmd_flags |= BNX_NVM_COMMAND_LAST; 2063 } 2064 2065 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2066 2067 if (rc != 0) 2068 goto nvram_write_end; 2069 2070 cmd_flags = 0; 2071 buf += 4; 2072 } 2073 2074 /* Loop to write back the buffer data from data_end 2075 * to page_end */ 2076 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2077 for (addr = data_end; addr < page_end; 2078 addr += 4, i += 4) { 2079 2080 if (addr == page_end-4) 2081 cmd_flags = BNX_NVM_COMMAND_LAST; 2082 2083 rc = bnx_nvram_write_dword(sc, addr, 2084 &flash_buffer[i], cmd_flags); 2085 2086 if (rc != 0) 2087 goto nvram_write_end; 2088 2089 cmd_flags = 0; 2090 } 2091 } 2092 2093 /* Disable writes to flash interface (lock write-protect) */ 2094 bnx_disable_nvram_write(sc); 2095 2096 /* Disable access to flash interface */ 2097 bnx_disable_nvram_access(sc); 2098 bnx_release_nvram_lock(sc); 2099 2100 /* Increment written */ 2101 written += data_end - data_start; 2102 } 2103 2104 nvram_write_end: 2105 if (align_start || align_end) 2106 free(buf, M_DEVBUF); 2107 2108 return rc; 2109 } 2110 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2111 2112 /****************************************************************************/ 2113 /* Verifies that NVRAM is accessible and contains valid data. */ 2114 /* */ 2115 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2116 /* correct. */ 2117 /* */ 2118 /* Returns: */ 2119 /* 0 on success, positive value on failure. */ 2120 /****************************************************************************/ 2121 int 2122 bnx_nvram_test(struct bnx_softc *sc) 2123 { 2124 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2125 uint8_t *data = (uint8_t *) buf; 2126 int rc = 0; 2127 uint32_t magic, csum; 2128 2129 /* 2130 * Check that the device NVRAM is valid by reading 2131 * the magic value at offset 0. 2132 */ 2133 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2134 goto bnx_nvram_test_done; 2135 2136 magic = be32toh(buf[0]); 2137 if (magic != BNX_NVRAM_MAGIC) { 2138 rc = ENODEV; 2139 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2140 "Expected: 0x%08X, Found: 0x%08X\n", 2141 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2142 goto bnx_nvram_test_done; 2143 } 2144 2145 /* 2146 * Verify that the device NVRAM includes valid 2147 * configuration data. 2148 */ 2149 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2150 goto bnx_nvram_test_done; 2151 2152 csum = ether_crc32_le(data, 0x100); 2153 if (csum != BNX_CRC32_RESIDUAL) { 2154 rc = ENODEV; 2155 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2156 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2157 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2158 goto bnx_nvram_test_done; 2159 } 2160 2161 csum = ether_crc32_le(data + 0x100, 0x100); 2162 if (csum != BNX_CRC32_RESIDUAL) { 2163 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2164 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2165 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2166 rc = ENODEV; 2167 } 2168 2169 bnx_nvram_test_done: 2170 return rc; 2171 } 2172 2173 /****************************************************************************/ 2174 /* Identifies the current media type of the controller and sets the PHY */ 2175 /* address. */ 2176 /* */ 2177 /* Returns: */ 2178 /* Nothing. */ 2179 /****************************************************************************/ 2180 void 2181 bnx_get_media(struct bnx_softc *sc) 2182 { 2183 sc->bnx_phy_addr = 1; 2184 2185 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2186 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2187 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2188 uint32_t strap; 2189 2190 /* 2191 * The BCM5709S is software configurable 2192 * for Copper or SerDes operation. 2193 */ 2194 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2195 DBPRINT(sc, BNX_INFO_LOAD, 2196 "5709 bonded for copper.\n"); 2197 goto bnx_get_media_exit; 2198 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2199 DBPRINT(sc, BNX_INFO_LOAD, 2200 "5709 bonded for dual media.\n"); 2201 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2202 goto bnx_get_media_exit; 2203 } 2204 2205 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2206 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2207 else { 2208 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2209 >> 8; 2210 } 2211 2212 if (sc->bnx_pa.pa_function == 0) { 2213 switch (strap) { 2214 case 0x4: 2215 case 0x5: 2216 case 0x6: 2217 DBPRINT(sc, BNX_INFO_LOAD, 2218 "BCM5709 s/w configured for SerDes.\n"); 2219 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2220 break; 2221 default: 2222 DBPRINT(sc, BNX_INFO_LOAD, 2223 "BCM5709 s/w configured for Copper.\n"); 2224 } 2225 } else { 2226 switch (strap) { 2227 case 0x1: 2228 case 0x2: 2229 case 0x4: 2230 DBPRINT(sc, BNX_INFO_LOAD, 2231 "BCM5709 s/w configured for SerDes.\n"); 2232 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2233 break; 2234 default: 2235 DBPRINT(sc, BNX_INFO_LOAD, 2236 "BCM5709 s/w configured for Copper.\n"); 2237 } 2238 } 2239 2240 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2241 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2242 2243 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2244 uint32_t val; 2245 2246 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2247 2248 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2249 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2250 2251 /* 2252 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2253 * separate PHY for SerDes. 2254 */ 2255 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2256 sc->bnx_phy_addr = 2; 2257 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2258 BNX_SHARED_HW_CFG_CONFIG); 2259 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2260 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2261 DBPRINT(sc, BNX_INFO_LOAD, 2262 "Found 2.5Gb capable adapter\n"); 2263 } 2264 } 2265 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2266 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2267 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2268 2269 bnx_get_media_exit: 2270 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2271 "Using PHY address %d.\n", sc->bnx_phy_addr); 2272 } 2273 2274 /****************************************************************************/ 2275 /* Performs PHY initialization required before MII drivers access the */ 2276 /* device. */ 2277 /* */ 2278 /* Returns: */ 2279 /* Nothing. */ 2280 /****************************************************************************/ 2281 void 2282 bnx_init_media(struct bnx_softc *sc) 2283 { 2284 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2285 /* 2286 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2287 * IEEE Clause 22 method. Otherwise we have no way to attach 2288 * the PHY to the mii(4) layer. PHY specific configuration 2289 * is done by the mii(4) layer. 2290 */ 2291 2292 /* Select auto-negotiation MMD of the PHY. */ 2293 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2294 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2295 2296 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2297 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2298 2299 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2300 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2301 } 2302 } 2303 2304 /****************************************************************************/ 2305 /* Free any DMA memory owned by the driver. */ 2306 /* */ 2307 /* Scans through each data structre that requires DMA memory and frees */ 2308 /* the memory if allocated. */ 2309 /* */ 2310 /* Returns: */ 2311 /* Nothing. */ 2312 /****************************************************************************/ 2313 void 2314 bnx_dma_free(struct bnx_softc *sc) 2315 { 2316 int i; 2317 2318 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2319 2320 /* Destroy the status block. */ 2321 if (sc->status_block != NULL && sc->status_map != NULL) { 2322 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2323 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2324 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2325 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2326 BNX_STATUS_BLK_SZ); 2327 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2328 sc->status_rseg); 2329 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2330 sc->status_block = NULL; 2331 sc->status_map = NULL; 2332 } 2333 2334 /* Destroy the statistics block. */ 2335 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2336 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2337 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2338 BNX_STATS_BLK_SZ); 2339 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2340 sc->stats_rseg); 2341 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2342 sc->stats_block = NULL; 2343 sc->stats_map = NULL; 2344 } 2345 2346 /* Free, unmap and destroy all context memory pages. */ 2347 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2348 for (i = 0; i < sc->ctx_pages; i++) { 2349 if (sc->ctx_block[i] != NULL) { 2350 bus_dmamap_unload(sc->bnx_dmatag, 2351 sc->ctx_map[i]); 2352 bus_dmamem_unmap(sc->bnx_dmatag, 2353 (void *)sc->ctx_block[i], 2354 BCM_PAGE_SIZE); 2355 bus_dmamem_free(sc->bnx_dmatag, 2356 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2357 bus_dmamap_destroy(sc->bnx_dmatag, 2358 sc->ctx_map[i]); 2359 sc->ctx_block[i] = NULL; 2360 } 2361 } 2362 } 2363 2364 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2365 for (i = 0; i < TX_PAGES; i++ ) { 2366 if (sc->tx_bd_chain[i] != NULL && 2367 sc->tx_bd_chain_map[i] != NULL) { 2368 bus_dmamap_unload(sc->bnx_dmatag, 2369 sc->tx_bd_chain_map[i]); 2370 bus_dmamem_unmap(sc->bnx_dmatag, 2371 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2372 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2373 sc->tx_bd_chain_rseg[i]); 2374 bus_dmamap_destroy(sc->bnx_dmatag, 2375 sc->tx_bd_chain_map[i]); 2376 sc->tx_bd_chain[i] = NULL; 2377 sc->tx_bd_chain_map[i] = NULL; 2378 } 2379 } 2380 2381 /* Destroy the TX dmamaps. */ 2382 /* This isn't necessary since we dont allocate them up front */ 2383 2384 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2385 for (i = 0; i < RX_PAGES; i++ ) { 2386 if (sc->rx_bd_chain[i] != NULL && 2387 sc->rx_bd_chain_map[i] != NULL) { 2388 bus_dmamap_unload(sc->bnx_dmatag, 2389 sc->rx_bd_chain_map[i]); 2390 bus_dmamem_unmap(sc->bnx_dmatag, 2391 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2392 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2393 sc->rx_bd_chain_rseg[i]); 2394 2395 bus_dmamap_destroy(sc->bnx_dmatag, 2396 sc->rx_bd_chain_map[i]); 2397 sc->rx_bd_chain[i] = NULL; 2398 sc->rx_bd_chain_map[i] = NULL; 2399 } 2400 } 2401 2402 /* Unload and destroy the RX mbuf maps. */ 2403 for (i = 0; i < TOTAL_RX_BD; i++) { 2404 if (sc->rx_mbuf_map[i] != NULL) { 2405 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2406 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2407 } 2408 } 2409 2410 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2411 } 2412 2413 /****************************************************************************/ 2414 /* Allocate any DMA memory needed by the driver. */ 2415 /* */ 2416 /* Allocates DMA memory needed for the various global structures needed by */ 2417 /* hardware. */ 2418 /* */ 2419 /* Returns: */ 2420 /* 0 for success, positive value for failure. */ 2421 /****************************************************************************/ 2422 int 2423 bnx_dma_alloc(struct bnx_softc *sc) 2424 { 2425 int i, rc = 0; 2426 2427 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2428 2429 /* 2430 * Allocate DMA memory for the status block, map the memory into DMA 2431 * space, and fetch the physical address of the block. 2432 */ 2433 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2434 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2435 aprint_error_dev(sc->bnx_dev, 2436 "Could not create status block DMA map!\n"); 2437 rc = ENOMEM; 2438 goto bnx_dma_alloc_exit; 2439 } 2440 2441 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2442 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2443 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2444 aprint_error_dev(sc->bnx_dev, 2445 "Could not allocate status block DMA memory!\n"); 2446 rc = ENOMEM; 2447 goto bnx_dma_alloc_exit; 2448 } 2449 2450 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2451 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2452 aprint_error_dev(sc->bnx_dev, 2453 "Could not map status block DMA memory!\n"); 2454 rc = ENOMEM; 2455 goto bnx_dma_alloc_exit; 2456 } 2457 2458 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2459 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2460 aprint_error_dev(sc->bnx_dev, 2461 "Could not load status block DMA memory!\n"); 2462 rc = ENOMEM; 2463 goto bnx_dma_alloc_exit; 2464 } 2465 2466 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2467 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2468 2469 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2470 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2471 2472 /* DRC - Fix for 64 bit addresses. */ 2473 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2474 (uint32_t) sc->status_block_paddr); 2475 2476 /* BCM5709 uses host memory as cache for context memory. */ 2477 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2478 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2479 if (sc->ctx_pages == 0) 2480 sc->ctx_pages = 1; 2481 if (sc->ctx_pages > 4) /* XXX */ 2482 sc->ctx_pages = 4; 2483 2484 DBRUNIF((sc->ctx_pages > 512), 2485 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2486 __FILE__, __LINE__, sc->ctx_pages)); 2487 2488 2489 for (i = 0; i < sc->ctx_pages; i++) { 2490 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2491 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2492 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2493 &sc->ctx_map[i]) != 0) { 2494 rc = ENOMEM; 2495 goto bnx_dma_alloc_exit; 2496 } 2497 2498 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2499 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2500 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2501 rc = ENOMEM; 2502 goto bnx_dma_alloc_exit; 2503 } 2504 2505 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2506 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2507 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2508 rc = ENOMEM; 2509 goto bnx_dma_alloc_exit; 2510 } 2511 2512 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2513 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2514 BUS_DMA_NOWAIT) != 0) { 2515 rc = ENOMEM; 2516 goto bnx_dma_alloc_exit; 2517 } 2518 2519 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2520 } 2521 } 2522 2523 /* 2524 * Allocate DMA memory for the statistics block, map the memory into 2525 * DMA space, and fetch the physical address of the block. 2526 */ 2527 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2528 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2529 aprint_error_dev(sc->bnx_dev, 2530 "Could not create stats block DMA map!\n"); 2531 rc = ENOMEM; 2532 goto bnx_dma_alloc_exit; 2533 } 2534 2535 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2536 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2537 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2538 aprint_error_dev(sc->bnx_dev, 2539 "Could not allocate stats block DMA memory!\n"); 2540 rc = ENOMEM; 2541 goto bnx_dma_alloc_exit; 2542 } 2543 2544 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2545 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2546 aprint_error_dev(sc->bnx_dev, 2547 "Could not map stats block DMA memory!\n"); 2548 rc = ENOMEM; 2549 goto bnx_dma_alloc_exit; 2550 } 2551 2552 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2553 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2554 aprint_error_dev(sc->bnx_dev, 2555 "Could not load status block DMA memory!\n"); 2556 rc = ENOMEM; 2557 goto bnx_dma_alloc_exit; 2558 } 2559 2560 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2561 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2562 2563 /* DRC - Fix for 64 bit address. */ 2564 DBPRINT(sc, BNX_INFO, "stats_block_paddr = 0x%08X\n", 2565 (uint32_t) sc->stats_block_paddr); 2566 2567 /* 2568 * Allocate DMA memory for the TX buffer descriptor chain, 2569 * and fetch the physical address of the block. 2570 */ 2571 for (i = 0; i < TX_PAGES; i++) { 2572 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2573 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2574 &sc->tx_bd_chain_map[i])) { 2575 aprint_error_dev(sc->bnx_dev, 2576 "Could not create Tx desc %d DMA map!\n", i); 2577 rc = ENOMEM; 2578 goto bnx_dma_alloc_exit; 2579 } 2580 2581 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2582 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2583 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2584 aprint_error_dev(sc->bnx_dev, 2585 "Could not allocate TX desc %d DMA memory!\n", 2586 i); 2587 rc = ENOMEM; 2588 goto bnx_dma_alloc_exit; 2589 } 2590 2591 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2592 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2593 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2594 aprint_error_dev(sc->bnx_dev, 2595 "Could not map TX desc %d DMA memory!\n", i); 2596 rc = ENOMEM; 2597 goto bnx_dma_alloc_exit; 2598 } 2599 2600 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2601 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2602 BUS_DMA_NOWAIT)) { 2603 aprint_error_dev(sc->bnx_dev, 2604 "Could not load TX desc %d DMA memory!\n", i); 2605 rc = ENOMEM; 2606 goto bnx_dma_alloc_exit; 2607 } 2608 2609 sc->tx_bd_chain_paddr[i] = 2610 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2611 2612 /* DRC - Fix for 64 bit systems. */ 2613 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2614 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2615 } 2616 2617 /* 2618 * Create lists to hold TX mbufs. 2619 */ 2620 TAILQ_INIT(&sc->tx_free_pkts); 2621 TAILQ_INIT(&sc->tx_used_pkts); 2622 sc->tx_pkt_count = 0; 2623 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2624 2625 /* 2626 * Allocate DMA memory for the Rx buffer descriptor chain, 2627 * and fetch the physical address of the block. 2628 */ 2629 for (i = 0; i < RX_PAGES; i++) { 2630 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2631 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2632 &sc->rx_bd_chain_map[i])) { 2633 aprint_error_dev(sc->bnx_dev, 2634 "Could not create Rx desc %d DMA map!\n", i); 2635 rc = ENOMEM; 2636 goto bnx_dma_alloc_exit; 2637 } 2638 2639 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2640 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2641 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2642 aprint_error_dev(sc->bnx_dev, 2643 "Could not allocate Rx desc %d DMA memory!\n", i); 2644 rc = ENOMEM; 2645 goto bnx_dma_alloc_exit; 2646 } 2647 2648 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2649 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2650 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2651 aprint_error_dev(sc->bnx_dev, 2652 "Could not map Rx desc %d DMA memory!\n", i); 2653 rc = ENOMEM; 2654 goto bnx_dma_alloc_exit; 2655 } 2656 2657 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2658 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2659 BUS_DMA_NOWAIT)) { 2660 aprint_error_dev(sc->bnx_dev, 2661 "Could not load Rx desc %d DMA memory!\n", i); 2662 rc = ENOMEM; 2663 goto bnx_dma_alloc_exit; 2664 } 2665 2666 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2667 sc->rx_bd_chain_paddr[i] = 2668 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2669 2670 /* DRC - Fix for 64 bit systems. */ 2671 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2672 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2673 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2674 0, BNX_RX_CHAIN_PAGE_SZ, 2675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2676 } 2677 2678 /* 2679 * Create DMA maps for the Rx buffer mbufs. 2680 */ 2681 for (i = 0; i < TOTAL_RX_BD; i++) { 2682 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2683 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2684 &sc->rx_mbuf_map[i])) { 2685 aprint_error_dev(sc->bnx_dev, 2686 "Could not create Rx mbuf %d DMA map!\n", i); 2687 rc = ENOMEM; 2688 goto bnx_dma_alloc_exit; 2689 } 2690 } 2691 2692 bnx_dma_alloc_exit: 2693 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2694 2695 return rc; 2696 } 2697 2698 /****************************************************************************/ 2699 /* Release all resources used by the driver. */ 2700 /* */ 2701 /* Releases all resources acquired by the driver including interrupts, */ 2702 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2703 /* */ 2704 /* Returns: */ 2705 /* Nothing. */ 2706 /****************************************************************************/ 2707 void 2708 bnx_release_resources(struct bnx_softc *sc) 2709 { 2710 struct pci_attach_args *pa = &(sc->bnx_pa); 2711 2712 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2713 2714 bnx_dma_free(sc); 2715 2716 if (sc->bnx_intrhand != NULL) 2717 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2718 2719 if (sc->bnx_size) 2720 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2721 2722 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2723 } 2724 2725 /****************************************************************************/ 2726 /* Firmware synchronization. */ 2727 /* */ 2728 /* Before performing certain events such as a chip reset, synchronize with */ 2729 /* the firmware first. */ 2730 /* */ 2731 /* Returns: */ 2732 /* 0 for success, positive value for failure. */ 2733 /****************************************************************************/ 2734 int 2735 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2736 { 2737 int i, rc = 0; 2738 uint32_t val; 2739 2740 /* Don't waste any time if we've timed out before. */ 2741 if (sc->bnx_fw_timed_out) { 2742 rc = EBUSY; 2743 goto bnx_fw_sync_exit; 2744 } 2745 2746 /* Increment the message sequence number. */ 2747 sc->bnx_fw_wr_seq++; 2748 msg_data |= sc->bnx_fw_wr_seq; 2749 2750 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2751 msg_data); 2752 2753 /* Send the message to the bootcode driver mailbox. */ 2754 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2755 2756 /* Wait for the bootcode to acknowledge the message. */ 2757 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2758 /* Check for a response in the bootcode firmware mailbox. */ 2759 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2760 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2761 break; 2762 DELAY(1000); 2763 } 2764 2765 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2766 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2767 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2768 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2769 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2770 2771 msg_data &= ~BNX_DRV_MSG_CODE; 2772 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2773 2774 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2775 2776 sc->bnx_fw_timed_out = 1; 2777 rc = EBUSY; 2778 } 2779 2780 bnx_fw_sync_exit: 2781 return rc; 2782 } 2783 2784 /****************************************************************************/ 2785 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2786 /* */ 2787 /* Returns: */ 2788 /* Nothing. */ 2789 /****************************************************************************/ 2790 void 2791 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2792 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2793 { 2794 int i; 2795 uint32_t val; 2796 2797 /* Set the page size used by RV2P. */ 2798 if (rv2p_proc == RV2P_PROC2) { 2799 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2800 USABLE_RX_BD_PER_PAGE); 2801 } 2802 2803 for (i = 0; i < rv2p_code_len; i += 8) { 2804 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2805 rv2p_code++; 2806 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2807 rv2p_code++; 2808 2809 if (rv2p_proc == RV2P_PROC1) { 2810 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2811 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2812 } else { 2813 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2814 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2815 } 2816 } 2817 2818 /* Reset the processor, un-stall is done later. */ 2819 if (rv2p_proc == RV2P_PROC1) 2820 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2821 else 2822 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2823 } 2824 2825 /****************************************************************************/ 2826 /* Load RISC processor firmware. */ 2827 /* */ 2828 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2829 /* associated with a particular processor. */ 2830 /* */ 2831 /* Returns: */ 2832 /* Nothing. */ 2833 /****************************************************************************/ 2834 void 2835 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2836 struct fw_info *fw) 2837 { 2838 uint32_t offset; 2839 uint32_t val; 2840 2841 /* Halt the CPU. */ 2842 val = REG_RD_IND(sc, cpu_reg->mode); 2843 val |= cpu_reg->mode_value_halt; 2844 REG_WR_IND(sc, cpu_reg->mode, val); 2845 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2846 2847 /* Load the Text area. */ 2848 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2849 if (fw->text) { 2850 int j; 2851 2852 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2853 REG_WR_IND(sc, offset, fw->text[j]); 2854 } 2855 2856 /* Load the Data area. */ 2857 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2858 if (fw->data) { 2859 int j; 2860 2861 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2862 REG_WR_IND(sc, offset, fw->data[j]); 2863 } 2864 2865 /* Load the SBSS area. */ 2866 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2867 if (fw->sbss) { 2868 int j; 2869 2870 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2871 REG_WR_IND(sc, offset, fw->sbss[j]); 2872 } 2873 2874 /* Load the BSS area. */ 2875 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2876 if (fw->bss) { 2877 int j; 2878 2879 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2880 REG_WR_IND(sc, offset, fw->bss[j]); 2881 } 2882 2883 /* Load the Read-Only area. */ 2884 offset = cpu_reg->spad_base + 2885 (fw->rodata_addr - cpu_reg->mips_view_base); 2886 if (fw->rodata) { 2887 int j; 2888 2889 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2890 REG_WR_IND(sc, offset, fw->rodata[j]); 2891 } 2892 2893 /* Clear the pre-fetch instruction. */ 2894 REG_WR_IND(sc, cpu_reg->inst, 0); 2895 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2896 2897 /* Start the CPU. */ 2898 val = REG_RD_IND(sc, cpu_reg->mode); 2899 val &= ~cpu_reg->mode_value_halt; 2900 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2901 REG_WR_IND(sc, cpu_reg->mode, val); 2902 } 2903 2904 /****************************************************************************/ 2905 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2906 /* */ 2907 /* Loads the firmware for each CPU and starts the CPU. */ 2908 /* */ 2909 /* Returns: */ 2910 /* Nothing. */ 2911 /****************************************************************************/ 2912 void 2913 bnx_init_cpus(struct bnx_softc *sc) 2914 { 2915 struct cpu_reg cpu_reg; 2916 struct fw_info fw; 2917 2918 switch (BNX_CHIP_NUM(sc)) { 2919 case BNX_CHIP_NUM_5709: 2920 /* Initialize the RV2P processor. */ 2921 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2922 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2923 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2924 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2925 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2926 } else { 2927 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2928 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2929 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2930 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2931 } 2932 2933 /* Initialize the RX Processor. */ 2934 cpu_reg.mode = BNX_RXP_CPU_MODE; 2935 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2936 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2937 cpu_reg.state = BNX_RXP_CPU_STATE; 2938 cpu_reg.state_value_clear = 0xffffff; 2939 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2940 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2941 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2942 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2943 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2944 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2945 cpu_reg.mips_view_base = 0x8000000; 2946 2947 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2948 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2949 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2950 fw.start_addr = bnx_RXP_b09FwStartAddr; 2951 2952 fw.text_addr = bnx_RXP_b09FwTextAddr; 2953 fw.text_len = bnx_RXP_b09FwTextLen; 2954 fw.text_index = 0; 2955 fw.text = bnx_RXP_b09FwText; 2956 2957 fw.data_addr = bnx_RXP_b09FwDataAddr; 2958 fw.data_len = bnx_RXP_b09FwDataLen; 2959 fw.data_index = 0; 2960 fw.data = bnx_RXP_b09FwData; 2961 2962 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2963 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2964 fw.sbss_index = 0; 2965 fw.sbss = bnx_RXP_b09FwSbss; 2966 2967 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2968 fw.bss_len = bnx_RXP_b09FwBssLen; 2969 fw.bss_index = 0; 2970 fw.bss = bnx_RXP_b09FwBss; 2971 2972 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2973 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2974 fw.rodata_index = 0; 2975 fw.rodata = bnx_RXP_b09FwRodata; 2976 2977 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2978 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2979 2980 /* Initialize the TX Processor. */ 2981 cpu_reg.mode = BNX_TXP_CPU_MODE; 2982 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2983 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2984 cpu_reg.state = BNX_TXP_CPU_STATE; 2985 cpu_reg.state_value_clear = 0xffffff; 2986 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2987 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2988 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2989 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2990 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2991 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2992 cpu_reg.mips_view_base = 0x8000000; 2993 2994 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2995 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2996 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2997 fw.start_addr = bnx_TXP_b09FwStartAddr; 2998 2999 fw.text_addr = bnx_TXP_b09FwTextAddr; 3000 fw.text_len = bnx_TXP_b09FwTextLen; 3001 fw.text_index = 0; 3002 fw.text = bnx_TXP_b09FwText; 3003 3004 fw.data_addr = bnx_TXP_b09FwDataAddr; 3005 fw.data_len = bnx_TXP_b09FwDataLen; 3006 fw.data_index = 0; 3007 fw.data = bnx_TXP_b09FwData; 3008 3009 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 3010 fw.sbss_len = bnx_TXP_b09FwSbssLen; 3011 fw.sbss_index = 0; 3012 fw.sbss = bnx_TXP_b09FwSbss; 3013 3014 fw.bss_addr = bnx_TXP_b09FwBssAddr; 3015 fw.bss_len = bnx_TXP_b09FwBssLen; 3016 fw.bss_index = 0; 3017 fw.bss = bnx_TXP_b09FwBss; 3018 3019 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 3020 fw.rodata_len = bnx_TXP_b09FwRodataLen; 3021 fw.rodata_index = 0; 3022 fw.rodata = bnx_TXP_b09FwRodata; 3023 3024 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3025 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3026 3027 /* Initialize the TX Patch-up Processor. */ 3028 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3029 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3030 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3031 cpu_reg.state = BNX_TPAT_CPU_STATE; 3032 cpu_reg.state_value_clear = 0xffffff; 3033 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3034 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3035 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3036 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3037 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3038 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3039 cpu_reg.mips_view_base = 0x8000000; 3040 3041 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 3042 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 3043 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 3044 fw.start_addr = bnx_TPAT_b09FwStartAddr; 3045 3046 fw.text_addr = bnx_TPAT_b09FwTextAddr; 3047 fw.text_len = bnx_TPAT_b09FwTextLen; 3048 fw.text_index = 0; 3049 fw.text = bnx_TPAT_b09FwText; 3050 3051 fw.data_addr = bnx_TPAT_b09FwDataAddr; 3052 fw.data_len = bnx_TPAT_b09FwDataLen; 3053 fw.data_index = 0; 3054 fw.data = bnx_TPAT_b09FwData; 3055 3056 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 3057 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 3058 fw.sbss_index = 0; 3059 fw.sbss = bnx_TPAT_b09FwSbss; 3060 3061 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 3062 fw.bss_len = bnx_TPAT_b09FwBssLen; 3063 fw.bss_index = 0; 3064 fw.bss = bnx_TPAT_b09FwBss; 3065 3066 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3067 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3068 fw.rodata_index = 0; 3069 fw.rodata = bnx_TPAT_b09FwRodata; 3070 3071 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3072 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3073 3074 /* Initialize the Completion Processor. */ 3075 cpu_reg.mode = BNX_COM_CPU_MODE; 3076 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3077 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3078 cpu_reg.state = BNX_COM_CPU_STATE; 3079 cpu_reg.state_value_clear = 0xffffff; 3080 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3081 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3082 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3083 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3084 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3085 cpu_reg.spad_base = BNX_COM_SCRATCH; 3086 cpu_reg.mips_view_base = 0x8000000; 3087 3088 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3089 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3090 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3091 fw.start_addr = bnx_COM_b09FwStartAddr; 3092 3093 fw.text_addr = bnx_COM_b09FwTextAddr; 3094 fw.text_len = bnx_COM_b09FwTextLen; 3095 fw.text_index = 0; 3096 fw.text = bnx_COM_b09FwText; 3097 3098 fw.data_addr = bnx_COM_b09FwDataAddr; 3099 fw.data_len = bnx_COM_b09FwDataLen; 3100 fw.data_index = 0; 3101 fw.data = bnx_COM_b09FwData; 3102 3103 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3104 fw.sbss_len = bnx_COM_b09FwSbssLen; 3105 fw.sbss_index = 0; 3106 fw.sbss = bnx_COM_b09FwSbss; 3107 3108 fw.bss_addr = bnx_COM_b09FwBssAddr; 3109 fw.bss_len = bnx_COM_b09FwBssLen; 3110 fw.bss_index = 0; 3111 fw.bss = bnx_COM_b09FwBss; 3112 3113 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3114 fw.rodata_len = bnx_COM_b09FwRodataLen; 3115 fw.rodata_index = 0; 3116 fw.rodata = bnx_COM_b09FwRodata; 3117 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3118 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3119 break; 3120 default: 3121 /* Initialize the RV2P processor. */ 3122 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3123 RV2P_PROC1); 3124 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3125 RV2P_PROC2); 3126 3127 /* Initialize the RX Processor. */ 3128 cpu_reg.mode = BNX_RXP_CPU_MODE; 3129 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3130 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3131 cpu_reg.state = BNX_RXP_CPU_STATE; 3132 cpu_reg.state_value_clear = 0xffffff; 3133 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3134 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3135 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3136 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3137 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3138 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3139 cpu_reg.mips_view_base = 0x8000000; 3140 3141 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3142 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3143 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3144 fw.start_addr = bnx_RXP_b06FwStartAddr; 3145 3146 fw.text_addr = bnx_RXP_b06FwTextAddr; 3147 fw.text_len = bnx_RXP_b06FwTextLen; 3148 fw.text_index = 0; 3149 fw.text = bnx_RXP_b06FwText; 3150 3151 fw.data_addr = bnx_RXP_b06FwDataAddr; 3152 fw.data_len = bnx_RXP_b06FwDataLen; 3153 fw.data_index = 0; 3154 fw.data = bnx_RXP_b06FwData; 3155 3156 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3157 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3158 fw.sbss_index = 0; 3159 fw.sbss = bnx_RXP_b06FwSbss; 3160 3161 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3162 fw.bss_len = bnx_RXP_b06FwBssLen; 3163 fw.bss_index = 0; 3164 fw.bss = bnx_RXP_b06FwBss; 3165 3166 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3167 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3168 fw.rodata_index = 0; 3169 fw.rodata = bnx_RXP_b06FwRodata; 3170 3171 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3172 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3173 3174 /* Initialize the TX Processor. */ 3175 cpu_reg.mode = BNX_TXP_CPU_MODE; 3176 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3177 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3178 cpu_reg.state = BNX_TXP_CPU_STATE; 3179 cpu_reg.state_value_clear = 0xffffff; 3180 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3181 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3182 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3183 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3184 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3185 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3186 cpu_reg.mips_view_base = 0x8000000; 3187 3188 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3189 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3190 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3191 fw.start_addr = bnx_TXP_b06FwStartAddr; 3192 3193 fw.text_addr = bnx_TXP_b06FwTextAddr; 3194 fw.text_len = bnx_TXP_b06FwTextLen; 3195 fw.text_index = 0; 3196 fw.text = bnx_TXP_b06FwText; 3197 3198 fw.data_addr = bnx_TXP_b06FwDataAddr; 3199 fw.data_len = bnx_TXP_b06FwDataLen; 3200 fw.data_index = 0; 3201 fw.data = bnx_TXP_b06FwData; 3202 3203 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3204 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3205 fw.sbss_index = 0; 3206 fw.sbss = bnx_TXP_b06FwSbss; 3207 3208 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3209 fw.bss_len = bnx_TXP_b06FwBssLen; 3210 fw.bss_index = 0; 3211 fw.bss = bnx_TXP_b06FwBss; 3212 3213 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3214 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3215 fw.rodata_index = 0; 3216 fw.rodata = bnx_TXP_b06FwRodata; 3217 3218 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3219 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3220 3221 /* Initialize the TX Patch-up Processor. */ 3222 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3223 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3224 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3225 cpu_reg.state = BNX_TPAT_CPU_STATE; 3226 cpu_reg.state_value_clear = 0xffffff; 3227 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3228 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3229 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3230 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3231 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3232 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3233 cpu_reg.mips_view_base = 0x8000000; 3234 3235 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3236 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3237 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3238 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3239 3240 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3241 fw.text_len = bnx_TPAT_b06FwTextLen; 3242 fw.text_index = 0; 3243 fw.text = bnx_TPAT_b06FwText; 3244 3245 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3246 fw.data_len = bnx_TPAT_b06FwDataLen; 3247 fw.data_index = 0; 3248 fw.data = bnx_TPAT_b06FwData; 3249 3250 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3251 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3252 fw.sbss_index = 0; 3253 fw.sbss = bnx_TPAT_b06FwSbss; 3254 3255 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3256 fw.bss_len = bnx_TPAT_b06FwBssLen; 3257 fw.bss_index = 0; 3258 fw.bss = bnx_TPAT_b06FwBss; 3259 3260 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3261 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3262 fw.rodata_index = 0; 3263 fw.rodata = bnx_TPAT_b06FwRodata; 3264 3265 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3266 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3267 3268 /* Initialize the Completion Processor. */ 3269 cpu_reg.mode = BNX_COM_CPU_MODE; 3270 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3271 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3272 cpu_reg.state = BNX_COM_CPU_STATE; 3273 cpu_reg.state_value_clear = 0xffffff; 3274 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3275 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3276 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3277 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3278 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3279 cpu_reg.spad_base = BNX_COM_SCRATCH; 3280 cpu_reg.mips_view_base = 0x8000000; 3281 3282 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3283 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3284 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3285 fw.start_addr = bnx_COM_b06FwStartAddr; 3286 3287 fw.text_addr = bnx_COM_b06FwTextAddr; 3288 fw.text_len = bnx_COM_b06FwTextLen; 3289 fw.text_index = 0; 3290 fw.text = bnx_COM_b06FwText; 3291 3292 fw.data_addr = bnx_COM_b06FwDataAddr; 3293 fw.data_len = bnx_COM_b06FwDataLen; 3294 fw.data_index = 0; 3295 fw.data = bnx_COM_b06FwData; 3296 3297 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3298 fw.sbss_len = bnx_COM_b06FwSbssLen; 3299 fw.sbss_index = 0; 3300 fw.sbss = bnx_COM_b06FwSbss; 3301 3302 fw.bss_addr = bnx_COM_b06FwBssAddr; 3303 fw.bss_len = bnx_COM_b06FwBssLen; 3304 fw.bss_index = 0; 3305 fw.bss = bnx_COM_b06FwBss; 3306 3307 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3308 fw.rodata_len = bnx_COM_b06FwRodataLen; 3309 fw.rodata_index = 0; 3310 fw.rodata = bnx_COM_b06FwRodata; 3311 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3312 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3313 break; 3314 } 3315 } 3316 3317 /****************************************************************************/ 3318 /* Initialize context memory. */ 3319 /* */ 3320 /* Clears the memory associated with each Context ID (CID). */ 3321 /* */ 3322 /* Returns: */ 3323 /* Nothing. */ 3324 /****************************************************************************/ 3325 void 3326 bnx_init_context(struct bnx_softc *sc) 3327 { 3328 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3329 /* DRC: Replace this constant value with a #define. */ 3330 int i, retry_cnt = 10; 3331 uint32_t val; 3332 3333 /* 3334 * BCM5709 context memory may be cached 3335 * in host memory so prepare the host memory 3336 * for access. 3337 */ 3338 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3339 | (1 << 12); 3340 val |= (BCM_PAGE_BITS - 8) << 16; 3341 REG_WR(sc, BNX_CTX_COMMAND, val); 3342 3343 /* Wait for mem init command to complete. */ 3344 for (i = 0; i < retry_cnt; i++) { 3345 val = REG_RD(sc, BNX_CTX_COMMAND); 3346 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3347 break; 3348 DELAY(2); 3349 } 3350 3351 /* ToDo: Consider returning an error here. */ 3352 3353 for (i = 0; i < sc->ctx_pages; i++) { 3354 int j; 3355 3356 /* Set the physaddr of the context memory cache. */ 3357 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3358 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3359 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3360 val = (uint32_t) 3361 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3362 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3363 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3364 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3365 3366 /* Verify that the context memory write was successful. */ 3367 for (j = 0; j < retry_cnt; j++) { 3368 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3369 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3370 break; 3371 DELAY(5); 3372 } 3373 3374 /* ToDo: Consider returning an error here. */ 3375 } 3376 } else { 3377 uint32_t vcid_addr, offset; 3378 3379 /* 3380 * For the 5706/5708, context memory is local to the 3381 * controller, so initialize the controller context memory. 3382 */ 3383 3384 vcid_addr = GET_CID_ADDR(96); 3385 while (vcid_addr) { 3386 3387 vcid_addr -= BNX_PHY_CTX_SIZE; 3388 3389 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3390 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3391 3392 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3393 offset += 4) 3394 CTX_WR(sc, 0x00, offset, 0); 3395 3396 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3397 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3398 } 3399 } 3400 } 3401 3402 /****************************************************************************/ 3403 /* Fetch the permanent MAC address of the controller. */ 3404 /* */ 3405 /* Returns: */ 3406 /* Nothing. */ 3407 /****************************************************************************/ 3408 void 3409 bnx_get_mac_addr(struct bnx_softc *sc) 3410 { 3411 uint32_t mac_lo = 0, mac_hi = 0; 3412 3413 /* 3414 * The NetXtreme II bootcode populates various NIC 3415 * power-on and runtime configuration items in a 3416 * shared memory area. The factory configured MAC 3417 * address is available from both NVRAM and the 3418 * shared memory area so we'll read the value from 3419 * shared memory for speed. 3420 */ 3421 3422 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3423 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3424 3425 if ((mac_lo == 0) && (mac_hi == 0)) { 3426 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3427 __FILE__, __LINE__); 3428 } else { 3429 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3430 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3431 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3432 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3433 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3434 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3435 } 3436 3437 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3438 "%s\n", ether_sprintf(sc->eaddr)); 3439 } 3440 3441 /****************************************************************************/ 3442 /* Program the MAC address. */ 3443 /* */ 3444 /* Returns: */ 3445 /* Nothing. */ 3446 /****************************************************************************/ 3447 void 3448 bnx_set_mac_addr(struct bnx_softc *sc) 3449 { 3450 uint32_t val; 3451 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3452 3453 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3454 "%s\n", ether_sprintf(sc->eaddr)); 3455 3456 val = (mac_addr[0] << 8) | mac_addr[1]; 3457 3458 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3459 3460 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3461 (mac_addr[4] << 8) | mac_addr[5]; 3462 3463 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3464 } 3465 3466 /****************************************************************************/ 3467 /* Stop the controller. */ 3468 /* */ 3469 /* Returns: */ 3470 /* Nothing. */ 3471 /****************************************************************************/ 3472 void 3473 bnx_stop(struct ifnet *ifp, int disable) 3474 { 3475 struct bnx_softc *sc = ifp->if_softc; 3476 3477 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3478 3479 if (disable) { 3480 sc->bnx_detaching = 1; 3481 callout_halt(&sc->bnx_timeout, NULL); 3482 } else 3483 callout_stop(&sc->bnx_timeout); 3484 3485 mii_down(&sc->bnx_mii); 3486 3487 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3488 3489 /* Disable the transmit/receive blocks. */ 3490 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3491 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3492 DELAY(20); 3493 3494 bnx_disable_intr(sc); 3495 3496 /* Tell firmware that the driver is going away. */ 3497 if (disable) 3498 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3499 else 3500 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3501 3502 /* Free RX buffers. */ 3503 bnx_free_rx_chain(sc); 3504 3505 /* Free TX buffers. */ 3506 bnx_free_tx_chain(sc); 3507 3508 ifp->if_timer = 0; 3509 3510 sc->bnx_link = 0; 3511 3512 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3513 3514 bnx_mgmt_init(sc); 3515 } 3516 3517 int 3518 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3519 { 3520 struct pci_attach_args *pa = &(sc->bnx_pa); 3521 uint32_t val; 3522 int i, rc = 0; 3523 3524 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3525 3526 /* Wait for pending PCI transactions to complete. */ 3527 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 3528 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) { 3529 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3530 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3531 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3532 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3533 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3534 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3535 DELAY(5); 3536 } else { 3537 /* Disable DMA */ 3538 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3539 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3540 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3541 REG_RD(sc, BNX_MISC_NEW_CORE_CTL); /* barrier */ 3542 3543 for (i = 0; i < 100; i++) { 3544 delay(1 * 1000); 3545 val = REG_RD(sc, BNX_PCICFG_DEVICE_CONTROL); 3546 if ((val & PCIE_DCSR_TRANSACTION_PND) == 0) 3547 break; 3548 } 3549 } 3550 3551 /* Assume bootcode is running. */ 3552 sc->bnx_fw_timed_out = 0; 3553 3554 /* Give the firmware a chance to prepare for the reset. */ 3555 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3556 if (rc) 3557 goto bnx_reset_exit; 3558 3559 /* Set a firmware reminder that this is a soft reset. */ 3560 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3561 BNX_DRV_RESET_SIGNATURE_MAGIC); 3562 3563 /* Dummy read to force the chip to complete all current transactions. */ 3564 val = REG_RD(sc, BNX_MISC_ID); 3565 3566 /* Chip reset. */ 3567 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3568 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3569 REG_RD(sc, BNX_MISC_COMMAND); 3570 DELAY(5); 3571 3572 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3573 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3574 3575 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3576 val); 3577 } else { 3578 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3579 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3580 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3581 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3582 3583 /* Allow up to 30us for reset to complete. */ 3584 for (i = 0; i < 10; i++) { 3585 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3586 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3587 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3588 break; 3589 } 3590 DELAY(10); 3591 } 3592 3593 /* Check that reset completed successfully. */ 3594 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3595 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3596 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3597 __FILE__, __LINE__); 3598 rc = EBUSY; 3599 goto bnx_reset_exit; 3600 } 3601 } 3602 3603 /* Make sure byte swapping is properly configured. */ 3604 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3605 if (val != 0x01020304) { 3606 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3607 __FILE__, __LINE__); 3608 rc = ENODEV; 3609 goto bnx_reset_exit; 3610 } 3611 3612 /* Just completed a reset, assume that firmware is running again. */ 3613 sc->bnx_fw_timed_out = 0; 3614 3615 /* Wait for the firmware to finish its initialization. */ 3616 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3617 if (rc) 3618 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3619 "initialization!\n", __FILE__, __LINE__); 3620 3621 bnx_reset_exit: 3622 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3623 3624 return rc; 3625 } 3626 3627 int 3628 bnx_chipinit(struct bnx_softc *sc) 3629 { 3630 struct pci_attach_args *pa = &(sc->bnx_pa); 3631 uint32_t val; 3632 int rc = 0; 3633 3634 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3635 3636 /* Make sure the interrupt is not active. */ 3637 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3638 3639 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3640 /* channels and PCI clock compensation delay. */ 3641 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3642 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3643 #if BYTE_ORDER == BIG_ENDIAN 3644 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3645 #endif 3646 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3647 DMA_READ_CHANS << 12 | 3648 DMA_WRITE_CHANS << 16; 3649 3650 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3651 3652 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3653 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3654 3655 /* 3656 * This setting resolves a problem observed on certain Intel PCI 3657 * chipsets that cannot handle multiple outstanding DMA operations. 3658 * See errata E9_5706A1_65. 3659 */ 3660 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3661 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3662 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3663 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3664 3665 REG_WR(sc, BNX_DMA_CONFIG, val); 3666 3667 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3668 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3669 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3670 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3671 val & ~0x20000); 3672 } 3673 3674 /* Enable the RX_V2P and Context state machines before access. */ 3675 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3676 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3677 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3678 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3679 3680 /* Initialize context mapping and zero out the quick contexts. */ 3681 bnx_init_context(sc); 3682 3683 /* Initialize the on-boards CPUs */ 3684 bnx_init_cpus(sc); 3685 3686 /* Enable management frames (NC-SI) to flow to the MCP. */ 3687 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3688 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) | 3689 BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3690 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3691 } 3692 3693 /* Prepare NVRAM for access. */ 3694 if (bnx_init_nvram(sc)) { 3695 rc = ENODEV; 3696 goto bnx_chipinit_exit; 3697 } 3698 3699 /* Set the kernel bypass block size */ 3700 val = REG_RD(sc, BNX_MQ_CONFIG); 3701 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3702 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3703 3704 /* Enable bins used on the 5709. */ 3705 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3706 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3707 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3708 val |= BNX_MQ_CONFIG_HALT_DIS; 3709 } 3710 3711 REG_WR(sc, BNX_MQ_CONFIG, val); 3712 3713 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3714 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3715 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3716 3717 val = (BCM_PAGE_BITS - 8) << 24; 3718 REG_WR(sc, BNX_RV2P_CONFIG, val); 3719 3720 /* Configure page size. */ 3721 val = REG_RD(sc, BNX_TBDR_CONFIG); 3722 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3723 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3724 REG_WR(sc, BNX_TBDR_CONFIG, val); 3725 3726 #if 0 3727 /* Set the perfect match control register to default. */ 3728 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3729 #endif 3730 3731 bnx_chipinit_exit: 3732 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3733 3734 return rc; 3735 } 3736 3737 /****************************************************************************/ 3738 /* Initialize the controller in preparation to send/receive traffic. */ 3739 /* */ 3740 /* Returns: */ 3741 /* 0 for success, positive value for failure. */ 3742 /****************************************************************************/ 3743 int 3744 bnx_blockinit(struct bnx_softc *sc) 3745 { 3746 uint32_t reg, val; 3747 int rc = 0; 3748 3749 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3750 3751 /* Load the hardware default MAC address. */ 3752 bnx_set_mac_addr(sc); 3753 3754 /* Set the Ethernet backoff seed value */ 3755 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3756 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3757 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3758 3759 sc->last_status_idx = 0; 3760 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3761 3762 /* Set up link change interrupt generation. */ 3763 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3764 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3765 3766 /* Program the physical address of the status block. */ 3767 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3768 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3769 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3770 3771 /* Program the physical address of the statistics block. */ 3772 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3773 (uint32_t)(sc->stats_block_paddr)); 3774 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3775 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3776 3777 /* Program various host coalescing parameters. */ 3778 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3779 << 16) | sc->bnx_tx_quick_cons_trip); 3780 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3781 << 16) | sc->bnx_rx_quick_cons_trip); 3782 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3783 sc->bnx_comp_prod_trip); 3784 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3785 sc->bnx_tx_ticks); 3786 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3787 sc->bnx_rx_ticks); 3788 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3789 sc->bnx_com_ticks); 3790 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3791 sc->bnx_cmd_ticks); 3792 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3793 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3794 REG_WR(sc, BNX_HC_CONFIG, 3795 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3796 BNX_HC_CONFIG_COLLECT_STATS)); 3797 3798 /* Clear the internal statistics counters. */ 3799 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3800 3801 /* Verify that bootcode is running. */ 3802 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3803 3804 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3805 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3806 __FILE__, __LINE__); reg = 0); 3807 3808 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3809 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3810 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3811 "Expected: 08%08X\n", __FILE__, __LINE__, 3812 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3813 BNX_DEV_INFO_SIGNATURE_MAGIC); 3814 rc = ENODEV; 3815 goto bnx_blockinit_exit; 3816 } 3817 3818 /* Enable DMA */ 3819 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3820 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3821 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3822 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3823 } 3824 3825 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3826 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3827 3828 /* Disable management frames (NC-SI) from flowing to the MCP. */ 3829 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3830 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) & 3831 ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3832 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3833 } 3834 3835 /* Enable all remaining blocks in the MAC. */ 3836 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3837 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3838 BNX_MISC_ENABLE_DEFAULT_XI); 3839 } else 3840 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3841 3842 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3843 DELAY(20); 3844 3845 bnx_blockinit_exit: 3846 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3847 3848 return rc; 3849 } 3850 3851 static int 3852 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3853 uint16_t *chain_prod, uint32_t *prod_bseq) 3854 { 3855 bus_dmamap_t map; 3856 struct rx_bd *rxbd; 3857 uint32_t addr; 3858 int i; 3859 #ifdef BNX_DEBUG 3860 uint16_t debug_chain_prod = *chain_prod; 3861 #endif 3862 uint16_t first_chain_prod; 3863 3864 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3865 3866 /* Map the mbuf cluster into device memory. */ 3867 map = sc->rx_mbuf_map[*chain_prod]; 3868 first_chain_prod = *chain_prod; 3869 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3870 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3871 __FILE__, __LINE__); 3872 3873 m_freem(m_new); 3874 3875 DBRUNIF(1, sc->rx_mbuf_alloc--); 3876 3877 return ENOBUFS; 3878 } 3879 /* Make sure there is room in the receive chain. */ 3880 if (map->dm_nsegs > sc->free_rx_bd) { 3881 bus_dmamap_unload(sc->bnx_dmatag, map); 3882 m_freem(m_new); 3883 return EFBIG; 3884 } 3885 #ifdef BNX_DEBUG 3886 /* Track the distribution of buffer segments. */ 3887 sc->rx_mbuf_segs[map->dm_nsegs]++; 3888 #endif 3889 3890 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3891 BUS_DMASYNC_PREREAD); 3892 3893 /* Update some debug statistics counters */ 3894 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3895 sc->rx_low_watermark = sc->free_rx_bd); 3896 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3897 3898 /* 3899 * Setup the rx_bd for the first segment 3900 */ 3901 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3902 3903 addr = (uint32_t)map->dm_segs[0].ds_addr; 3904 rxbd->rx_bd_haddr_lo = addr; 3905 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3906 rxbd->rx_bd_haddr_hi = addr; 3907 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3908 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3909 *prod_bseq += map->dm_segs[0].ds_len; 3910 bus_dmamap_sync(sc->bnx_dmatag, 3911 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3912 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3913 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3914 3915 for (i = 1; i < map->dm_nsegs; i++) { 3916 *prod = NEXT_RX_BD(*prod); 3917 *chain_prod = RX_CHAIN_IDX(*prod); 3918 3919 rxbd = 3920 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3921 3922 addr = (uint32_t)map->dm_segs[i].ds_addr; 3923 rxbd->rx_bd_haddr_lo = addr; 3924 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3925 rxbd->rx_bd_haddr_hi = addr; 3926 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3927 rxbd->rx_bd_flags = 0; 3928 *prod_bseq += map->dm_segs[i].ds_len; 3929 bus_dmamap_sync(sc->bnx_dmatag, 3930 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3931 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3932 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3933 } 3934 3935 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3936 bus_dmamap_sync(sc->bnx_dmatag, 3937 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3938 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3939 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3940 3941 /* 3942 * Save the mbuf, adjust the map pointer (swap map for first and 3943 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3944 * and update our counter. 3945 */ 3946 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3947 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3948 sc->rx_mbuf_map[*chain_prod] = map; 3949 sc->free_rx_bd -= map->dm_nsegs; 3950 3951 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3952 map->dm_nsegs)); 3953 *prod = NEXT_RX_BD(*prod); 3954 *chain_prod = RX_CHAIN_IDX(*prod); 3955 3956 return 0; 3957 } 3958 3959 /****************************************************************************/ 3960 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3961 /* */ 3962 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3963 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3964 /* necessary. */ 3965 /* */ 3966 /* Returns: */ 3967 /* 0 for success, positive value for failure. */ 3968 /****************************************************************************/ 3969 int 3970 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3971 uint16_t *chain_prod, uint32_t *prod_bseq) 3972 { 3973 struct mbuf *m_new = NULL; 3974 int rc = 0; 3975 uint16_t min_free_bd; 3976 3977 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3978 __func__); 3979 3980 /* Make sure the inputs are valid. */ 3981 DBRUNIF((*chain_prod > MAX_RX_BD), 3982 aprint_error_dev(sc->bnx_dev, 3983 "RX producer out of range: 0x%04X > 0x%04X\n", 3984 *chain_prod, (uint16_t)MAX_RX_BD)); 3985 3986 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3987 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3988 *prod_bseq); 3989 3990 /* try to get in as many mbufs as possible */ 3991 if (sc->mbuf_alloc_size == MCLBYTES) 3992 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3993 else 3994 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3995 while (sc->free_rx_bd >= min_free_bd) { 3996 /* Simulate an mbuf allocation failure. */ 3997 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3998 aprint_error_dev(sc->bnx_dev, 3999 "Simulating mbuf allocation failure.\n"); 4000 sc->mbuf_sim_alloc_failed++; 4001 rc = ENOBUFS; 4002 goto bnx_get_buf_exit); 4003 4004 /* This is a new mbuf allocation. */ 4005 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4006 if (m_new == NULL) { 4007 DBPRINT(sc, BNX_WARN, 4008 "%s(%d): RX mbuf header allocation failed!\n", 4009 __FILE__, __LINE__); 4010 4011 sc->mbuf_alloc_failed++; 4012 4013 rc = ENOBUFS; 4014 goto bnx_get_buf_exit; 4015 } 4016 4017 DBRUNIF(1, sc->rx_mbuf_alloc++); 4018 4019 /* Simulate an mbuf cluster allocation failure. */ 4020 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4021 m_freem(m_new); 4022 sc->rx_mbuf_alloc--; 4023 sc->mbuf_alloc_failed++; 4024 sc->mbuf_sim_alloc_failed++; 4025 rc = ENOBUFS; 4026 goto bnx_get_buf_exit); 4027 4028 if (sc->mbuf_alloc_size == MCLBYTES) 4029 MCLGET(m_new, M_DONTWAIT); 4030 else 4031 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 4032 M_DONTWAIT); 4033 if (!(m_new->m_flags & M_EXT)) { 4034 DBPRINT(sc, BNX_WARN, 4035 "%s(%d): RX mbuf chain allocation failed!\n", 4036 __FILE__, __LINE__); 4037 4038 m_freem(m_new); 4039 4040 DBRUNIF(1, sc->rx_mbuf_alloc--); 4041 sc->mbuf_alloc_failed++; 4042 4043 rc = ENOBUFS; 4044 goto bnx_get_buf_exit; 4045 } 4046 4047 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 4048 if (rc != 0) 4049 goto bnx_get_buf_exit; 4050 } 4051 4052 bnx_get_buf_exit: 4053 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 4054 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 4055 *chain_prod, *prod_bseq); 4056 4057 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 4058 __func__); 4059 4060 return rc; 4061 } 4062 4063 void 4064 bnx_alloc_pkts(struct work * unused, void * arg) 4065 { 4066 struct bnx_softc *sc = arg; 4067 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4068 struct bnx_pkt *pkt; 4069 int i, s; 4070 4071 for (i = 0; i < 4; i++) { /* magic! */ 4072 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 4073 if (pkt == NULL) 4074 break; 4075 4076 if (bus_dmamap_create(sc->bnx_dmatag, 4077 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4078 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4079 &pkt->pkt_dmamap) != 0) 4080 goto put; 4081 4082 if (!ISSET(ifp->if_flags, IFF_UP)) 4083 goto stopping; 4084 4085 mutex_enter(&sc->tx_pkt_mtx); 4086 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4087 sc->tx_pkt_count++; 4088 mutex_exit(&sc->tx_pkt_mtx); 4089 } 4090 4091 mutex_enter(&sc->tx_pkt_mtx); 4092 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4093 mutex_exit(&sc->tx_pkt_mtx); 4094 4095 /* fire-up TX now that allocations have been done */ 4096 s = splnet(); 4097 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4098 bnx_start(ifp); 4099 splx(s); 4100 4101 return; 4102 4103 stopping: 4104 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4105 put: 4106 pool_put(bnx_tx_pool, pkt); 4107 return; 4108 } 4109 4110 /****************************************************************************/ 4111 /* Initialize the TX context memory. */ 4112 /* */ 4113 /* Returns: */ 4114 /* Nothing */ 4115 /****************************************************************************/ 4116 void 4117 bnx_init_tx_context(struct bnx_softc *sc) 4118 { 4119 uint32_t val; 4120 4121 /* Initialize the context ID for an L2 TX chain. */ 4122 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4123 /* Set the CID type to support an L2 connection. */ 4124 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4125 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4126 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4127 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4128 4129 /* Point the hardware to the first page in the chain. */ 4130 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4131 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4132 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4133 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4134 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4135 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4136 } else { 4137 /* Set the CID type to support an L2 connection. */ 4138 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4139 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4140 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4141 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4142 4143 /* Point the hardware to the first page in the chain. */ 4144 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4145 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4146 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4147 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4148 } 4149 } 4150 4151 4152 /****************************************************************************/ 4153 /* Allocate memory and initialize the TX data structures. */ 4154 /* */ 4155 /* Returns: */ 4156 /* 0 for success, positive value for failure. */ 4157 /****************************************************************************/ 4158 int 4159 bnx_init_tx_chain(struct bnx_softc *sc) 4160 { 4161 struct tx_bd *txbd; 4162 uint32_t addr; 4163 int i, rc = 0; 4164 4165 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4166 4167 /* Force an allocation of some dmamaps for tx up front */ 4168 bnx_alloc_pkts(NULL, sc); 4169 4170 /* Set the initial TX producer/consumer indices. */ 4171 sc->tx_prod = 0; 4172 sc->tx_cons = 0; 4173 sc->tx_prod_bseq = 0; 4174 sc->used_tx_bd = 0; 4175 sc->max_tx_bd = USABLE_TX_BD; 4176 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4177 DBRUNIF(1, sc->tx_full_count = 0); 4178 4179 /* 4180 * The NetXtreme II supports a linked-list structure called 4181 * a Buffer Descriptor Chain (or BD chain). A BD chain 4182 * consists of a series of 1 or more chain pages, each of which 4183 * consists of a fixed number of BD entries. 4184 * The last BD entry on each page is a pointer to the next page 4185 * in the chain, and the last pointer in the BD chain 4186 * points back to the beginning of the chain. 4187 */ 4188 4189 /* Set the TX next pointer chain entries. */ 4190 for (i = 0; i < TX_PAGES; i++) { 4191 int j; 4192 4193 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4194 4195 /* Check if we've reached the last page. */ 4196 if (i == (TX_PAGES - 1)) 4197 j = 0; 4198 else 4199 j = i + 1; 4200 4201 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4202 txbd->tx_bd_haddr_lo = addr; 4203 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4204 txbd->tx_bd_haddr_hi = addr; 4205 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4206 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4207 } 4208 4209 /* 4210 * Initialize the context ID for an L2 TX chain. 4211 */ 4212 bnx_init_tx_context(sc); 4213 4214 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4215 4216 return rc; 4217 } 4218 4219 /****************************************************************************/ 4220 /* Free memory and clear the TX data structures. */ 4221 /* */ 4222 /* Returns: */ 4223 /* Nothing. */ 4224 /****************************************************************************/ 4225 void 4226 bnx_free_tx_chain(struct bnx_softc *sc) 4227 { 4228 struct bnx_pkt *pkt; 4229 int i; 4230 4231 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4232 4233 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4234 mutex_enter(&sc->tx_pkt_mtx); 4235 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4236 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4237 mutex_exit(&sc->tx_pkt_mtx); 4238 4239 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4240 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4241 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4242 4243 m_freem(pkt->pkt_mbuf); 4244 DBRUNIF(1, sc->tx_mbuf_alloc--); 4245 4246 mutex_enter(&sc->tx_pkt_mtx); 4247 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4248 } 4249 4250 /* Destroy all the dmamaps we allocated for TX */ 4251 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4252 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4253 sc->tx_pkt_count--; 4254 mutex_exit(&sc->tx_pkt_mtx); 4255 4256 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4257 pool_put(bnx_tx_pool, pkt); 4258 4259 mutex_enter(&sc->tx_pkt_mtx); 4260 } 4261 mutex_exit(&sc->tx_pkt_mtx); 4262 4263 4264 4265 /* Clear each TX chain page. */ 4266 for (i = 0; i < TX_PAGES; i++) { 4267 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4268 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4269 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4270 } 4271 4272 sc->used_tx_bd = 0; 4273 4274 /* Check if we lost any mbufs in the process. */ 4275 DBRUNIF((sc->tx_mbuf_alloc), 4276 aprint_error_dev(sc->bnx_dev, 4277 "Memory leak! Lost %d mbufs from tx chain!\n", 4278 sc->tx_mbuf_alloc)); 4279 4280 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4281 } 4282 4283 /****************************************************************************/ 4284 /* Initialize the RX context memory. */ 4285 /* */ 4286 /* Returns: */ 4287 /* Nothing */ 4288 /****************************************************************************/ 4289 void 4290 bnx_init_rx_context(struct bnx_softc *sc) 4291 { 4292 uint32_t val; 4293 4294 /* Initialize the context ID for an L2 RX chain. */ 4295 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4296 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4297 4298 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4299 val |= 0x000000ff; 4300 4301 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4302 4303 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4304 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4305 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4306 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4307 } 4308 4309 /* Point the hardware to the first page in the chain. */ 4310 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4311 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4312 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4313 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4314 } 4315 4316 /****************************************************************************/ 4317 /* Allocate memory and initialize the RX data structures. */ 4318 /* */ 4319 /* Returns: */ 4320 /* 0 for success, positive value for failure. */ 4321 /****************************************************************************/ 4322 int 4323 bnx_init_rx_chain(struct bnx_softc *sc) 4324 { 4325 struct rx_bd *rxbd; 4326 int i, rc = 0; 4327 uint16_t prod, chain_prod; 4328 uint32_t prod_bseq, addr; 4329 4330 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4331 4332 /* Initialize the RX producer and consumer indices. */ 4333 sc->rx_prod = 0; 4334 sc->rx_cons = 0; 4335 sc->rx_prod_bseq = 0; 4336 sc->free_rx_bd = USABLE_RX_BD; 4337 sc->max_rx_bd = USABLE_RX_BD; 4338 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4339 DBRUNIF(1, sc->rx_empty_count = 0); 4340 4341 /* Initialize the RX next pointer chain entries. */ 4342 for (i = 0; i < RX_PAGES; i++) { 4343 int j; 4344 4345 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4346 4347 /* Check if we've reached the last page. */ 4348 if (i == (RX_PAGES - 1)) 4349 j = 0; 4350 else 4351 j = i + 1; 4352 4353 /* Setup the chain page pointers. */ 4354 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4355 rxbd->rx_bd_haddr_hi = addr; 4356 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4357 rxbd->rx_bd_haddr_lo = addr; 4358 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4359 0, BNX_RX_CHAIN_PAGE_SZ, 4360 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4361 } 4362 4363 /* Allocate mbuf clusters for the rx_bd chain. */ 4364 prod = prod_bseq = 0; 4365 chain_prod = RX_CHAIN_IDX(prod); 4366 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4367 BNX_PRINTF(sc, 4368 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4369 } 4370 4371 /* Save the RX chain producer index. */ 4372 sc->rx_prod = prod; 4373 sc->rx_prod_bseq = prod_bseq; 4374 4375 for (i = 0; i < RX_PAGES; i++) 4376 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4377 sc->rx_bd_chain_map[i]->dm_mapsize, 4378 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4379 4380 /* Tell the chip about the waiting rx_bd's. */ 4381 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4382 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4383 4384 bnx_init_rx_context(sc); 4385 4386 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4387 4388 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4389 4390 return rc; 4391 } 4392 4393 /****************************************************************************/ 4394 /* Free memory and clear the RX data structures. */ 4395 /* */ 4396 /* Returns: */ 4397 /* Nothing. */ 4398 /****************************************************************************/ 4399 void 4400 bnx_free_rx_chain(struct bnx_softc *sc) 4401 { 4402 int i; 4403 4404 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4405 4406 /* Free any mbufs still in the RX mbuf chain. */ 4407 for (i = 0; i < TOTAL_RX_BD; i++) { 4408 if (sc->rx_mbuf_ptr[i] != NULL) { 4409 if (sc->rx_mbuf_map[i] != NULL) { 4410 bus_dmamap_sync(sc->bnx_dmatag, 4411 sc->rx_mbuf_map[i], 0, 4412 sc->rx_mbuf_map[i]->dm_mapsize, 4413 BUS_DMASYNC_POSTREAD); 4414 bus_dmamap_unload(sc->bnx_dmatag, 4415 sc->rx_mbuf_map[i]); 4416 } 4417 m_freem(sc->rx_mbuf_ptr[i]); 4418 sc->rx_mbuf_ptr[i] = NULL; 4419 DBRUNIF(1, sc->rx_mbuf_alloc--); 4420 } 4421 } 4422 4423 /* Clear each RX chain page. */ 4424 for (i = 0; i < RX_PAGES; i++) 4425 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4426 4427 sc->free_rx_bd = sc->max_rx_bd; 4428 4429 /* Check if we lost any mbufs in the process. */ 4430 DBRUNIF((sc->rx_mbuf_alloc), 4431 aprint_error_dev(sc->bnx_dev, 4432 "Memory leak! Lost %d mbufs from rx chain!\n", 4433 sc->rx_mbuf_alloc)); 4434 4435 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4436 } 4437 4438 /****************************************************************************/ 4439 /* Set media options. */ 4440 /* */ 4441 /* Returns: */ 4442 /* 0 for success, positive value for failure. */ 4443 /****************************************************************************/ 4444 int 4445 bnx_ifmedia_upd(struct ifnet *ifp) 4446 { 4447 struct bnx_softc *sc; 4448 struct mii_data *mii; 4449 int rc = 0; 4450 4451 sc = ifp->if_softc; 4452 4453 mii = &sc->bnx_mii; 4454 sc->bnx_link = 0; 4455 if (mii->mii_instance) { 4456 struct mii_softc *miisc; 4457 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4458 mii_phy_reset(miisc); 4459 } 4460 mii_mediachg(mii); 4461 4462 return rc; 4463 } 4464 4465 /****************************************************************************/ 4466 /* Reports current media status. */ 4467 /* */ 4468 /* Returns: */ 4469 /* Nothing. */ 4470 /****************************************************************************/ 4471 void 4472 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4473 { 4474 struct bnx_softc *sc; 4475 struct mii_data *mii; 4476 int s; 4477 4478 sc = ifp->if_softc; 4479 4480 s = splnet(); 4481 4482 mii = &sc->bnx_mii; 4483 4484 mii_pollstat(mii); 4485 ifmr->ifm_status = mii->mii_media_status; 4486 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4487 sc->bnx_flowflags; 4488 4489 splx(s); 4490 } 4491 4492 /****************************************************************************/ 4493 /* Handles PHY generated interrupt events. */ 4494 /* */ 4495 /* Returns: */ 4496 /* Nothing. */ 4497 /****************************************************************************/ 4498 void 4499 bnx_phy_intr(struct bnx_softc *sc) 4500 { 4501 uint32_t new_link_state, old_link_state; 4502 4503 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4504 BUS_DMASYNC_POSTREAD); 4505 new_link_state = sc->status_block->status_attn_bits & 4506 STATUS_ATTN_BITS_LINK_STATE; 4507 old_link_state = sc->status_block->status_attn_bits_ack & 4508 STATUS_ATTN_BITS_LINK_STATE; 4509 4510 /* Handle any changes if the link state has changed. */ 4511 if (new_link_state != old_link_state) { 4512 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4513 4514 sc->bnx_link = 0; 4515 callout_stop(&sc->bnx_timeout); 4516 bnx_tick(sc); 4517 4518 /* Update the status_attn_bits_ack field in the status block. */ 4519 if (new_link_state) { 4520 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4521 STATUS_ATTN_BITS_LINK_STATE); 4522 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4523 } else { 4524 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4525 STATUS_ATTN_BITS_LINK_STATE); 4526 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4527 } 4528 } 4529 4530 /* Acknowledge the link change interrupt. */ 4531 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4532 } 4533 4534 /****************************************************************************/ 4535 /* Handles received frame interrupt events. */ 4536 /* */ 4537 /* Returns: */ 4538 /* Nothing. */ 4539 /****************************************************************************/ 4540 void 4541 bnx_rx_intr(struct bnx_softc *sc) 4542 { 4543 struct status_block *sblk = sc->status_block; 4544 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4545 uint16_t hw_cons, sw_cons, sw_chain_cons; 4546 uint16_t sw_prod, sw_chain_prod; 4547 uint32_t sw_prod_bseq; 4548 struct l2_fhdr *l2fhdr; 4549 int i; 4550 4551 DBRUNIF(1, sc->rx_interrupts++); 4552 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4553 BUS_DMASYNC_POSTREAD); 4554 4555 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4556 for (i = 0; i < RX_PAGES; i++) 4557 bus_dmamap_sync(sc->bnx_dmatag, 4558 sc->rx_bd_chain_map[i], 0, 4559 sc->rx_bd_chain_map[i]->dm_mapsize, 4560 BUS_DMASYNC_POSTWRITE); 4561 4562 /* Get the hardware's view of the RX consumer index. */ 4563 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4564 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4565 hw_cons++; 4566 4567 /* Get working copies of the driver's view of the RX indices. */ 4568 sw_cons = sc->rx_cons; 4569 sw_prod = sc->rx_prod; 4570 sw_prod_bseq = sc->rx_prod_bseq; 4571 4572 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4573 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4574 __func__, sw_prod, sw_cons, sw_prod_bseq); 4575 4576 /* Prevent speculative reads from getting ahead of the status block. */ 4577 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4578 BUS_SPACE_BARRIER_READ); 4579 4580 /* Update some debug statistics counters */ 4581 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4582 sc->rx_low_watermark = sc->free_rx_bd); 4583 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4584 4585 /* 4586 * Scan through the receive chain as long 4587 * as there is work to do. 4588 */ 4589 while (sw_cons != hw_cons) { 4590 struct mbuf *m; 4591 struct rx_bd *rxbd __diagused; 4592 unsigned int len; 4593 uint32_t status; 4594 4595 /* Convert the producer/consumer indices to an actual 4596 * rx_bd index. 4597 */ 4598 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4599 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4600 4601 /* Get the used rx_bd. */ 4602 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4603 sc->free_rx_bd++; 4604 4605 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4606 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4607 4608 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4609 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4610 #ifdef DIAGNOSTIC 4611 /* Validate that this is the last rx_bd. */ 4612 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4613 printf("%s: Unexpected mbuf found in " 4614 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4615 sw_chain_cons); 4616 } 4617 #endif 4618 4619 /* DRC - ToDo: If the received packet is small, say 4620 * less than 128 bytes, allocate a new mbuf 4621 * here, copy the data to that mbuf, and 4622 * recycle the mapped jumbo frame. 4623 */ 4624 4625 /* Unmap the mbuf from DMA space. */ 4626 #ifdef DIAGNOSTIC 4627 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4628 printf("invalid map sw_cons 0x%x " 4629 "sw_prod 0x%x " 4630 "sw_chain_cons 0x%x " 4631 "sw_chain_prod 0x%x " 4632 "hw_cons 0x%x " 4633 "TOTAL_RX_BD_PER_PAGE 0x%x " 4634 "TOTAL_RX_BD 0x%x\n", 4635 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4636 hw_cons, 4637 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4638 } 4639 #endif 4640 bus_dmamap_sync(sc->bnx_dmatag, 4641 sc->rx_mbuf_map[sw_chain_cons], 0, 4642 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4643 BUS_DMASYNC_POSTREAD); 4644 bus_dmamap_unload(sc->bnx_dmatag, 4645 sc->rx_mbuf_map[sw_chain_cons]); 4646 4647 /* Remove the mbuf from the driver's chain. */ 4648 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4649 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4650 4651 /* 4652 * Frames received on the NetXteme II are prepended 4653 * with the l2_fhdr structure which provides status 4654 * information about the received frame (including 4655 * VLAN tags and checksum info) and are also 4656 * automatically adjusted to align the IP header 4657 * (i.e. two null bytes are inserted before the 4658 * Ethernet header). 4659 */ 4660 l2fhdr = mtod(m, struct l2_fhdr *); 4661 4662 len = l2fhdr->l2_fhdr_pkt_len; 4663 status = l2fhdr->l2_fhdr_status; 4664 4665 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4666 aprint_error("Simulating l2_fhdr status error.\n"); 4667 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4668 4669 /* Watch for unusual sized frames. */ 4670 DBRUNIF(((len < BNX_MIN_MTU) || 4671 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4672 aprint_error_dev(sc->bnx_dev, 4673 "Unusual frame size found. " 4674 "Min(%d), Actual(%d), Max(%d)\n", 4675 (int)BNX_MIN_MTU, len, 4676 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4677 4678 bnx_dump_mbuf(sc, m); 4679 bnx_breakpoint(sc)); 4680 4681 len -= ETHER_CRC_LEN; 4682 4683 /* Check the received frame for errors. */ 4684 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4685 L2_FHDR_ERRORS_PHY_DECODE | 4686 L2_FHDR_ERRORS_ALIGNMENT | 4687 L2_FHDR_ERRORS_TOO_SHORT | 4688 L2_FHDR_ERRORS_GIANT_FRAME)) || 4689 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4690 len > 4691 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4692 ifp->if_ierrors++; 4693 DBRUNIF(1, sc->l2fhdr_status_errors++); 4694 4695 /* Reuse the mbuf for a new frame. */ 4696 if (bnx_add_buf(sc, m, &sw_prod, 4697 &sw_chain_prod, &sw_prod_bseq)) { 4698 DBRUNIF(1, bnx_breakpoint(sc)); 4699 panic("%s: Can't reuse RX mbuf!\n", 4700 device_xname(sc->bnx_dev)); 4701 } 4702 continue; 4703 } 4704 4705 /* 4706 * Get a new mbuf for the rx_bd. If no new 4707 * mbufs are available then reuse the current mbuf, 4708 * log an ierror on the interface, and generate 4709 * an error in the system log. 4710 */ 4711 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4712 &sw_prod_bseq)) { 4713 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4714 "Failed to allocate " 4715 "new mbuf, incoming frame dropped!\n")); 4716 4717 ifp->if_ierrors++; 4718 4719 /* Try and reuse the exisitng mbuf. */ 4720 if (bnx_add_buf(sc, m, &sw_prod, 4721 &sw_chain_prod, &sw_prod_bseq)) { 4722 DBRUNIF(1, bnx_breakpoint(sc)); 4723 panic("%s: Double mbuf allocation " 4724 "failure!", 4725 device_xname(sc->bnx_dev)); 4726 } 4727 continue; 4728 } 4729 4730 /* Skip over the l2_fhdr when passing the data up 4731 * the stack. 4732 */ 4733 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4734 4735 /* Adjust the pckt length to match the received data. */ 4736 m->m_pkthdr.len = m->m_len = len; 4737 4738 /* Send the packet to the appropriate interface. */ 4739 m_set_rcvif(m, ifp); 4740 4741 DBRUN(BNX_VERBOSE_RECV, 4742 struct ether_header *eh; 4743 eh = mtod(m, struct ether_header *); 4744 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4745 __func__, ether_sprintf(eh->ether_dhost), 4746 ether_sprintf(eh->ether_shost), 4747 htons(eh->ether_type))); 4748 4749 /* Validate the checksum. */ 4750 4751 /* Check for an IP datagram. */ 4752 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4753 /* Check if the IP checksum is valid. */ 4754 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4755 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4756 #ifdef BNX_DEBUG 4757 else 4758 DBPRINT(sc, BNX_WARN_SEND, 4759 "%s(): Invalid IP checksum " 4760 "= 0x%04X!\n", 4761 __func__, 4762 l2fhdr->l2_fhdr_ip_xsum 4763 ); 4764 #endif 4765 } 4766 4767 /* Check for a valid TCP/UDP frame. */ 4768 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4769 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4770 /* Check for a good TCP/UDP checksum. */ 4771 if ((status & 4772 (L2_FHDR_ERRORS_TCP_XSUM | 4773 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4774 m->m_pkthdr.csum_flags |= 4775 M_CSUM_TCPv4 | 4776 M_CSUM_UDPv4; 4777 } else { 4778 DBPRINT(sc, BNX_WARN_SEND, 4779 "%s(): Invalid TCP/UDP " 4780 "checksum = 0x%04X!\n", 4781 __func__, 4782 l2fhdr->l2_fhdr_tcp_udp_xsum); 4783 } 4784 } 4785 4786 /* 4787 * If we received a packet with a vlan tag, 4788 * attach that information to the packet. 4789 */ 4790 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4791 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4792 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4793 } 4794 4795 /* Pass the mbuf off to the upper layers. */ 4796 4797 DBPRINT(sc, BNX_VERBOSE_RECV, 4798 "%s(): Passing received frame up.\n", __func__); 4799 if_percpuq_enqueue(ifp->if_percpuq, m); 4800 DBRUNIF(1, sc->rx_mbuf_alloc--); 4801 4802 } 4803 4804 sw_cons = NEXT_RX_BD(sw_cons); 4805 4806 /* Refresh hw_cons to see if there's new work */ 4807 if (sw_cons == hw_cons) { 4808 hw_cons = sc->hw_rx_cons = 4809 sblk->status_rx_quick_consumer_index0; 4810 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4811 USABLE_RX_BD_PER_PAGE) 4812 hw_cons++; 4813 } 4814 4815 /* Prevent speculative reads from getting ahead of 4816 * the status block. 4817 */ 4818 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4819 BUS_SPACE_BARRIER_READ); 4820 } 4821 4822 for (i = 0; i < RX_PAGES; i++) 4823 bus_dmamap_sync(sc->bnx_dmatag, 4824 sc->rx_bd_chain_map[i], 0, 4825 sc->rx_bd_chain_map[i]->dm_mapsize, 4826 BUS_DMASYNC_PREWRITE); 4827 4828 sc->rx_cons = sw_cons; 4829 sc->rx_prod = sw_prod; 4830 sc->rx_prod_bseq = sw_prod_bseq; 4831 4832 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4833 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4834 4835 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4836 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4837 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4838 } 4839 4840 /****************************************************************************/ 4841 /* Handles transmit completion interrupt events. */ 4842 /* */ 4843 /* Returns: */ 4844 /* Nothing. */ 4845 /****************************************************************************/ 4846 void 4847 bnx_tx_intr(struct bnx_softc *sc) 4848 { 4849 struct status_block *sblk = sc->status_block; 4850 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4851 struct bnx_pkt *pkt; 4852 bus_dmamap_t map; 4853 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4854 4855 DBRUNIF(1, sc->tx_interrupts++); 4856 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4857 BUS_DMASYNC_POSTREAD); 4858 4859 /* Get the hardware's view of the TX consumer index. */ 4860 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4861 4862 /* Skip to the next entry if this is a chain page pointer. */ 4863 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4864 hw_tx_cons++; 4865 4866 sw_tx_cons = sc->tx_cons; 4867 4868 /* Prevent speculative reads from getting ahead of the status block. */ 4869 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4870 BUS_SPACE_BARRIER_READ); 4871 4872 /* Cycle through any completed TX chain page entries. */ 4873 while (sw_tx_cons != hw_tx_cons) { 4874 #ifdef BNX_DEBUG 4875 struct tx_bd *txbd = NULL; 4876 #endif 4877 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4878 4879 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4880 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4881 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4882 4883 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4884 aprint_error_dev(sc->bnx_dev, 4885 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4886 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4887 4888 DBRUNIF(1, txbd = &sc->tx_bd_chain 4889 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4890 4891 DBRUNIF((txbd == NULL), 4892 aprint_error_dev(sc->bnx_dev, 4893 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4894 bnx_breakpoint(sc)); 4895 4896 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4897 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4898 4899 4900 mutex_enter(&sc->tx_pkt_mtx); 4901 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4902 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4903 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4904 mutex_exit(&sc->tx_pkt_mtx); 4905 /* 4906 * Free the associated mbuf. Remember 4907 * that only the last tx_bd of a packet 4908 * has an mbuf pointer and DMA map. 4909 */ 4910 map = pkt->pkt_dmamap; 4911 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4912 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4913 bus_dmamap_unload(sc->bnx_dmatag, map); 4914 4915 m_freem(pkt->pkt_mbuf); 4916 DBRUNIF(1, sc->tx_mbuf_alloc--); 4917 4918 ifp->if_opackets++; 4919 4920 mutex_enter(&sc->tx_pkt_mtx); 4921 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4922 } 4923 mutex_exit(&sc->tx_pkt_mtx); 4924 4925 sc->used_tx_bd--; 4926 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4927 __FILE__, __LINE__, sc->used_tx_bd); 4928 4929 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4930 4931 /* Refresh hw_cons to see if there's new work. */ 4932 hw_tx_cons = sc->hw_tx_cons = 4933 sblk->status_tx_quick_consumer_index0; 4934 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4935 USABLE_TX_BD_PER_PAGE) 4936 hw_tx_cons++; 4937 4938 /* Prevent speculative reads from getting ahead of 4939 * the status block. 4940 */ 4941 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4942 BUS_SPACE_BARRIER_READ); 4943 } 4944 4945 /* Clear the TX timeout timer. */ 4946 ifp->if_timer = 0; 4947 4948 /* Clear the tx hardware queue full flag. */ 4949 if (sc->used_tx_bd < sc->max_tx_bd) { 4950 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4951 aprint_debug_dev(sc->bnx_dev, 4952 "Open TX chain! %d/%d (used/total)\n", 4953 sc->used_tx_bd, sc->max_tx_bd)); 4954 ifp->if_flags &= ~IFF_OACTIVE; 4955 } 4956 4957 sc->tx_cons = sw_tx_cons; 4958 } 4959 4960 /****************************************************************************/ 4961 /* Disables interrupt generation. */ 4962 /* */ 4963 /* Returns: */ 4964 /* Nothing. */ 4965 /****************************************************************************/ 4966 void 4967 bnx_disable_intr(struct bnx_softc *sc) 4968 { 4969 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4970 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4971 } 4972 4973 /****************************************************************************/ 4974 /* Enables interrupt generation. */ 4975 /* */ 4976 /* Returns: */ 4977 /* Nothing. */ 4978 /****************************************************************************/ 4979 void 4980 bnx_enable_intr(struct bnx_softc *sc) 4981 { 4982 uint32_t val; 4983 4984 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4985 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4986 4987 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4988 sc->last_status_idx); 4989 4990 val = REG_RD(sc, BNX_HC_COMMAND); 4991 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4992 } 4993 4994 /****************************************************************************/ 4995 /* Handles controller initialization. */ 4996 /* */ 4997 /****************************************************************************/ 4998 int 4999 bnx_init(struct ifnet *ifp) 5000 { 5001 struct bnx_softc *sc = ifp->if_softc; 5002 uint32_t ether_mtu; 5003 int s, error = 0; 5004 5005 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 5006 5007 s = splnet(); 5008 5009 bnx_stop(ifp, 0); 5010 5011 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 5012 aprint_error_dev(sc->bnx_dev, 5013 "Controller reset failed!\n"); 5014 goto bnx_init_exit; 5015 } 5016 5017 if ((error = bnx_chipinit(sc)) != 0) { 5018 aprint_error_dev(sc->bnx_dev, 5019 "Controller initialization failed!\n"); 5020 goto bnx_init_exit; 5021 } 5022 5023 if ((error = bnx_blockinit(sc)) != 0) { 5024 aprint_error_dev(sc->bnx_dev, 5025 "Block initialization failed!\n"); 5026 goto bnx_init_exit; 5027 } 5028 5029 /* Calculate and program the Ethernet MRU size. */ 5030 if (ifp->if_mtu <= ETHERMTU) { 5031 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 5032 sc->mbuf_alloc_size = MCLBYTES; 5033 } else { 5034 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 5035 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 5036 } 5037 5038 5039 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 5040 5041 /* 5042 * Program the MRU and enable Jumbo frame 5043 * support. 5044 */ 5045 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 5046 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 5047 5048 /* Calculate the RX Ethernet frame size for rx_bd's. */ 5049 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 5050 5051 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 5052 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 5053 sc->mbuf_alloc_size, sc->max_frame_size); 5054 5055 /* Program appropriate promiscuous/multicast filtering. */ 5056 bnx_iff(sc); 5057 5058 /* Init RX buffer descriptor chain. */ 5059 bnx_init_rx_chain(sc); 5060 5061 /* Init TX buffer descriptor chain. */ 5062 bnx_init_tx_chain(sc); 5063 5064 /* Enable host interrupts. */ 5065 bnx_enable_intr(sc); 5066 5067 bnx_ifmedia_upd(ifp); 5068 5069 SET(ifp->if_flags, IFF_RUNNING); 5070 CLR(ifp->if_flags, IFF_OACTIVE); 5071 5072 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5073 5074 bnx_init_exit: 5075 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5076 5077 splx(s); 5078 5079 return error; 5080 } 5081 5082 void 5083 bnx_mgmt_init(struct bnx_softc *sc) 5084 { 5085 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5086 uint32_t val; 5087 5088 /* Check if the driver is still running and bail out if it is. */ 5089 if (ifp->if_flags & IFF_RUNNING) 5090 goto bnx_mgmt_init_exit; 5091 5092 /* Initialize the on-boards CPUs */ 5093 bnx_init_cpus(sc); 5094 5095 val = (BCM_PAGE_BITS - 8) << 24; 5096 REG_WR(sc, BNX_RV2P_CONFIG, val); 5097 5098 /* Enable all critical blocks in the MAC. */ 5099 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5100 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5101 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5102 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5103 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5104 DELAY(20); 5105 5106 bnx_ifmedia_upd(ifp); 5107 5108 bnx_mgmt_init_exit: 5109 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5110 } 5111 5112 /****************************************************************************/ 5113 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5114 /* memory visible to the controller. */ 5115 /* */ 5116 /* Returns: */ 5117 /* 0 for success, positive value for failure. */ 5118 /****************************************************************************/ 5119 int 5120 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5121 { 5122 struct bnx_pkt *pkt; 5123 bus_dmamap_t map; 5124 struct tx_bd *txbd = NULL; 5125 uint16_t vlan_tag = 0, flags = 0; 5126 uint16_t chain_prod, prod; 5127 #ifdef BNX_DEBUG 5128 uint16_t debug_prod; 5129 #endif 5130 uint32_t addr, prod_bseq; 5131 int i, error; 5132 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 5133 bool remap = true; 5134 5135 mutex_enter(&sc->tx_pkt_mtx); 5136 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5137 if (pkt == NULL) { 5138 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5139 mutex_exit(&sc->tx_pkt_mtx); 5140 return ENETDOWN; 5141 } 5142 5143 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5144 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5145 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 5146 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5147 } 5148 5149 mutex_exit(&sc->tx_pkt_mtx); 5150 return ENOMEM; 5151 } 5152 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5153 mutex_exit(&sc->tx_pkt_mtx); 5154 5155 /* Transfer any checksum offload flags to the bd. */ 5156 if (m->m_pkthdr.csum_flags) { 5157 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5158 flags |= TX_BD_FLAGS_IP_CKSUM; 5159 if (m->m_pkthdr.csum_flags & 5160 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5161 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5162 } 5163 5164 /* Transfer any VLAN tags to the bd. */ 5165 if (vlan_has_tag(m)) { 5166 flags |= TX_BD_FLAGS_VLAN_TAG; 5167 vlan_tag = vlan_get_tag(m); 5168 } 5169 5170 /* Map the mbuf into DMAable memory. */ 5171 prod = sc->tx_prod; 5172 chain_prod = TX_CHAIN_IDX(prod); 5173 map = pkt->pkt_dmamap; 5174 5175 /* Map the mbuf into our DMA address space. */ 5176 retry: 5177 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5178 if (__predict_false(error)) { 5179 if (error == EFBIG) { 5180 if (remap == true) { 5181 struct mbuf *newm; 5182 5183 remap = false; 5184 newm = m_defrag(m, M_NOWAIT); 5185 if (newm != NULL) { 5186 m = newm; 5187 goto retry; 5188 } 5189 } 5190 } 5191 sc->tx_dma_map_failures++; 5192 goto maperr; 5193 } 5194 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5195 BUS_DMASYNC_PREWRITE); 5196 /* Make sure there's room in the chain */ 5197 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5198 goto nospace; 5199 5200 /* prod points to an empty tx_bd at this point. */ 5201 prod_bseq = sc->tx_prod_bseq; 5202 #ifdef BNX_DEBUG 5203 debug_prod = chain_prod; 5204 #endif 5205 DBPRINT(sc, BNX_INFO_SEND, 5206 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5207 "prod_bseq = 0x%08X\n", 5208 __func__, prod, chain_prod, prod_bseq); 5209 5210 /* 5211 * Cycle through each mbuf segment that makes up 5212 * the outgoing frame, gathering the mapping info 5213 * for that segment and creating a tx_bd for the 5214 * mbuf. 5215 */ 5216 for (i = 0; i < map->dm_nsegs ; i++) { 5217 chain_prod = TX_CHAIN_IDX(prod); 5218 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5219 5220 addr = (uint32_t)map->dm_segs[i].ds_addr; 5221 txbd->tx_bd_haddr_lo = addr; 5222 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5223 txbd->tx_bd_haddr_hi = addr; 5224 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5225 txbd->tx_bd_vlan_tag = vlan_tag; 5226 txbd->tx_bd_flags = flags; 5227 prod_bseq += map->dm_segs[i].ds_len; 5228 if (i == 0) 5229 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5230 prod = NEXT_TX_BD(prod); 5231 } 5232 5233 /* Set the END flag on the last TX buffer descriptor. */ 5234 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5235 5236 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5237 5238 DBPRINT(sc, BNX_INFO_SEND, 5239 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5240 "prod_bseq = 0x%08X\n", 5241 __func__, prod, chain_prod, prod_bseq); 5242 5243 pkt->pkt_mbuf = m; 5244 pkt->pkt_end_desc = chain_prod; 5245 5246 mutex_enter(&sc->tx_pkt_mtx); 5247 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5248 mutex_exit(&sc->tx_pkt_mtx); 5249 5250 sc->used_tx_bd += map->dm_nsegs; 5251 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5252 __FILE__, __LINE__, sc->used_tx_bd); 5253 5254 /* Update some debug statistics counters */ 5255 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5256 sc->tx_hi_watermark = sc->used_tx_bd); 5257 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5258 DBRUNIF(1, sc->tx_mbuf_alloc++); 5259 5260 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5261 map->dm_nsegs)); 5262 5263 /* prod points to the next free tx_bd at this point. */ 5264 sc->tx_prod = prod; 5265 sc->tx_prod_bseq = prod_bseq; 5266 5267 return 0; 5268 5269 5270 nospace: 5271 bus_dmamap_unload(sc->bnx_dmatag, map); 5272 maperr: 5273 mutex_enter(&sc->tx_pkt_mtx); 5274 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5275 mutex_exit(&sc->tx_pkt_mtx); 5276 5277 return ENOMEM; 5278 } 5279 5280 /****************************************************************************/ 5281 /* Main transmit routine. */ 5282 /* */ 5283 /* Returns: */ 5284 /* Nothing. */ 5285 /****************************************************************************/ 5286 void 5287 bnx_start(struct ifnet *ifp) 5288 { 5289 struct bnx_softc *sc = ifp->if_softc; 5290 struct mbuf *m_head = NULL; 5291 int count = 0; 5292 #ifdef BNX_DEBUG 5293 uint16_t tx_chain_prod; 5294 #endif 5295 5296 /* If there's no link or the transmit queue is empty then just exit. */ 5297 if (!sc->bnx_link 5298 ||(ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) { 5299 DBPRINT(sc, BNX_INFO_SEND, 5300 "%s(): output active or device not running.\n", __func__); 5301 goto bnx_start_exit; 5302 } 5303 5304 /* prod points to the next free tx_bd. */ 5305 #ifdef BNX_DEBUG 5306 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5307 #endif 5308 5309 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5310 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5311 "used_tx %d max_tx %d\n", 5312 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5313 sc->used_tx_bd, sc->max_tx_bd); 5314 5315 /* 5316 * Keep adding entries while there is space in the ring. 5317 */ 5318 while (sc->used_tx_bd < sc->max_tx_bd) { 5319 /* Check for any frames to send. */ 5320 IFQ_POLL(&ifp->if_snd, m_head); 5321 if (m_head == NULL) 5322 break; 5323 5324 /* 5325 * Pack the data into the transmit ring. If we 5326 * don't have room, set the OACTIVE flag to wait 5327 * for the NIC to drain the chain. 5328 */ 5329 if (bnx_tx_encap(sc, m_head)) { 5330 ifp->if_flags |= IFF_OACTIVE; 5331 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5332 "business! Total tx_bd used = %d\n", 5333 sc->used_tx_bd); 5334 break; 5335 } 5336 5337 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5338 count++; 5339 5340 /* Send a copy of the frame to any BPF listeners. */ 5341 bpf_mtap(ifp, m_head, BPF_D_OUT); 5342 } 5343 5344 if (count == 0) { 5345 /* no packets were dequeued */ 5346 DBPRINT(sc, BNX_VERBOSE_SEND, 5347 "%s(): No packets were dequeued\n", __func__); 5348 goto bnx_start_exit; 5349 } 5350 5351 /* Update the driver's counters. */ 5352 #ifdef BNX_DEBUG 5353 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5354 #endif 5355 5356 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5357 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5358 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5359 5360 /* Start the transmit. */ 5361 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5362 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5363 5364 /* Set the tx timeout. */ 5365 ifp->if_timer = BNX_TX_TIMEOUT; 5366 5367 bnx_start_exit: 5368 return; 5369 } 5370 5371 /****************************************************************************/ 5372 /* Handles any IOCTL calls from the operating system. */ 5373 /* */ 5374 /* Returns: */ 5375 /* 0 for success, positive value for failure. */ 5376 /****************************************************************************/ 5377 int 5378 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5379 { 5380 struct bnx_softc *sc = ifp->if_softc; 5381 struct ifreq *ifr = (struct ifreq *) data; 5382 struct mii_data *mii = &sc->bnx_mii; 5383 int s, error = 0; 5384 5385 s = splnet(); 5386 5387 switch (command) { 5388 case SIOCSIFFLAGS: 5389 if ((error = ifioctl_common(ifp, command, data)) != 0) 5390 break; 5391 /* XXX set an ifflags callback and let ether_ioctl 5392 * handle all of this. 5393 */ 5394 if (ISSET(ifp->if_flags, IFF_UP)) { 5395 if (ifp->if_flags & IFF_RUNNING) 5396 error = ENETRESET; 5397 else 5398 bnx_init(ifp); 5399 } else if (ifp->if_flags & IFF_RUNNING) 5400 bnx_stop(ifp, 1); 5401 break; 5402 5403 case SIOCSIFMEDIA: 5404 /* Flow control requires full-duplex mode. */ 5405 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5406 (ifr->ifr_media & IFM_FDX) == 0) 5407 ifr->ifr_media &= ~IFM_ETH_FMASK; 5408 5409 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5410 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5411 /* We can do both TXPAUSE and RXPAUSE. */ 5412 ifr->ifr_media |= 5413 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5414 } 5415 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5416 } 5417 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5418 sc->bnx_phy_flags); 5419 5420 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5421 break; 5422 5423 default: 5424 error = ether_ioctl(ifp, command, data); 5425 } 5426 5427 if (error == ENETRESET) { 5428 if (ifp->if_flags & IFF_RUNNING) 5429 bnx_iff(sc); 5430 error = 0; 5431 } 5432 5433 splx(s); 5434 return error; 5435 } 5436 5437 /****************************************************************************/ 5438 /* Transmit timeout handler. */ 5439 /* */ 5440 /* Returns: */ 5441 /* Nothing. */ 5442 /****************************************************************************/ 5443 void 5444 bnx_watchdog(struct ifnet *ifp) 5445 { 5446 struct bnx_softc *sc = ifp->if_softc; 5447 5448 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5449 bnx_dump_status_block(sc)); 5450 /* 5451 * If we are in this routine because of pause frames, then 5452 * don't reset the hardware. 5453 */ 5454 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5455 return; 5456 5457 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5458 5459 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5460 5461 bnx_init(ifp); 5462 5463 ifp->if_oerrors++; 5464 } 5465 5466 /* 5467 * Interrupt handler. 5468 */ 5469 /****************************************************************************/ 5470 /* Main interrupt entry point. Verifies that the controller generated the */ 5471 /* interrupt and then calls a separate routine for handle the various */ 5472 /* interrupt causes (PHY, TX, RX). */ 5473 /* */ 5474 /* Returns: */ 5475 /* 0 for success, positive value for failure. */ 5476 /****************************************************************************/ 5477 int 5478 bnx_intr(void *xsc) 5479 { 5480 struct bnx_softc *sc = xsc; 5481 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5482 uint32_t status_attn_bits; 5483 uint16_t status_idx; 5484 const struct status_block *sblk; 5485 int rv = 0; 5486 5487 if (!device_is_active(sc->bnx_dev) || 5488 (ifp->if_flags & IFF_RUNNING) == 0) 5489 return 0; 5490 5491 DBRUNIF(1, sc->interrupts_generated++); 5492 5493 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5494 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5495 5496 sblk = sc->status_block; 5497 /* 5498 * If the hardware status block index 5499 * matches the last value read by the 5500 * driver and we haven't asserted our 5501 * interrupt then there's nothing to do. 5502 */ 5503 status_idx = sblk->status_idx; 5504 if ((status_idx != sc->last_status_idx) || 5505 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5506 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5507 rv = 1; 5508 5509 /* Ack the interrupt */ 5510 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5511 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5512 5513 status_attn_bits = sblk->status_attn_bits; 5514 5515 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5516 aprint_debug("Simulating unexpected status attention bit set."); 5517 status_attn_bits = status_attn_bits | 5518 STATUS_ATTN_BITS_PARITY_ERROR); 5519 5520 /* Was it a link change interrupt? */ 5521 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5522 (sblk->status_attn_bits_ack & 5523 STATUS_ATTN_BITS_LINK_STATE)) 5524 bnx_phy_intr(sc); 5525 5526 /* If any other attention is asserted then the chip is toast. */ 5527 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5528 (sblk->status_attn_bits_ack & 5529 ~STATUS_ATTN_BITS_LINK_STATE))) { 5530 DBRUN(sc->unexpected_attentions++); 5531 5532 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5533 sblk->status_attn_bits); 5534 5535 DBRUNIF((bnx_debug_unexpected_attention == 0), 5536 bnx_breakpoint(sc)); 5537 5538 bnx_init(ifp); 5539 goto out; 5540 } 5541 5542 /* Check for any completed RX frames. */ 5543 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5544 bnx_rx_intr(sc); 5545 5546 /* Check for any completed TX frames. */ 5547 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5548 bnx_tx_intr(sc); 5549 5550 /* 5551 * Save the status block index value for use during the 5552 * next interrupt. 5553 */ 5554 sc->last_status_idx = status_idx; 5555 5556 /* Start moving packets again */ 5557 if (ifp->if_flags & IFF_RUNNING) 5558 if_schedule_deferred_start(ifp); 5559 } 5560 5561 out: 5562 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5563 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5564 5565 return rv; 5566 } 5567 5568 /****************************************************************************/ 5569 /* Programs the various packet receive modes (broadcast and multicast). */ 5570 /* */ 5571 /* Returns: */ 5572 /* Nothing. */ 5573 /****************************************************************************/ 5574 void 5575 bnx_iff(struct bnx_softc *sc) 5576 { 5577 struct ethercom *ec = &sc->bnx_ec; 5578 struct ifnet *ifp = &ec->ec_if; 5579 struct ether_multi *enm; 5580 struct ether_multistep step; 5581 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5582 uint32_t rx_mode, sort_mode; 5583 int h, i; 5584 5585 /* Initialize receive mode default settings. */ 5586 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5587 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5588 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5589 ifp->if_flags &= ~IFF_ALLMULTI; 5590 5591 /* 5592 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5593 * be enbled. 5594 */ 5595 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5596 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5597 5598 /* 5599 * Check for promiscuous, all multicast, or selected 5600 * multicast address filtering. 5601 */ 5602 if (ifp->if_flags & IFF_PROMISC) { 5603 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5604 5605 ifp->if_flags |= IFF_ALLMULTI; 5606 /* Enable promiscuous mode. */ 5607 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5608 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5609 } else if (ifp->if_flags & IFF_ALLMULTI) { 5610 allmulti: 5611 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5612 5613 ifp->if_flags |= IFF_ALLMULTI; 5614 /* Enable all multicast addresses. */ 5615 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5616 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5617 0xffffffff); 5618 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5619 } else { 5620 /* Accept one or more multicast(s). */ 5621 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5622 5623 ETHER_LOCK(ec); 5624 ETHER_FIRST_MULTI(step, ec, enm); 5625 while (enm != NULL) { 5626 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5627 ETHER_ADDR_LEN)) { 5628 ETHER_UNLOCK(ec); 5629 goto allmulti; 5630 } 5631 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5632 0xFF; 5633 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5634 ETHER_NEXT_MULTI(step, enm); 5635 } 5636 ETHER_UNLOCK(ec); 5637 5638 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5639 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5640 hashes[i]); 5641 5642 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5643 } 5644 5645 /* Only make changes if the recive mode has actually changed. */ 5646 if (rx_mode != sc->rx_mode) { 5647 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5648 rx_mode); 5649 5650 sc->rx_mode = rx_mode; 5651 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5652 } 5653 5654 /* Disable and clear the exisitng sort before enabling a new sort. */ 5655 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5656 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5657 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5658 } 5659 5660 /****************************************************************************/ 5661 /* Called periodically to updates statistics from the controllers */ 5662 /* statistics block. */ 5663 /* */ 5664 /* Returns: */ 5665 /* Nothing. */ 5666 /****************************************************************************/ 5667 void 5668 bnx_stats_update(struct bnx_softc *sc) 5669 { 5670 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5671 struct statistics_block *stats; 5672 5673 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5674 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5675 BUS_DMASYNC_POSTREAD); 5676 5677 stats = (struct statistics_block *)sc->stats_block; 5678 5679 /* 5680 * Update the interface statistics from the 5681 * hardware statistics. 5682 */ 5683 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5684 5685 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5686 (u_long)stats->stat_EtherStatsOverrsizePkts + 5687 (u_long)stats->stat_IfInMBUFDiscards + 5688 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5689 (u_long)stats->stat_Dot3StatsFCSErrors; 5690 5691 ifp->if_oerrors = (u_long) 5692 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5693 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5694 (u_long)stats->stat_Dot3StatsLateCollisions; 5695 5696 /* 5697 * Certain controllers don't report 5698 * carrier sense errors correctly. 5699 * See errata E11_5708CA0_1165. 5700 */ 5701 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5702 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5703 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5704 5705 /* 5706 * Update the sysctl statistics from the 5707 * hardware statistics. 5708 */ 5709 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5710 (uint64_t) stats->stat_IfHCInOctets_lo; 5711 5712 sc->stat_IfHCInBadOctets = 5713 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5714 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5715 5716 sc->stat_IfHCOutOctets = 5717 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5718 (uint64_t) stats->stat_IfHCOutOctets_lo; 5719 5720 sc->stat_IfHCOutBadOctets = 5721 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5722 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5723 5724 sc->stat_IfHCInUcastPkts = 5725 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5726 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5727 5728 sc->stat_IfHCInMulticastPkts = 5729 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5730 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5731 5732 sc->stat_IfHCInBroadcastPkts = 5733 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5734 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5735 5736 sc->stat_IfHCOutUcastPkts = 5737 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5738 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5739 5740 sc->stat_IfHCOutMulticastPkts = 5741 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5742 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5743 5744 sc->stat_IfHCOutBroadcastPkts = 5745 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5746 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5747 5748 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5749 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5750 5751 sc->stat_Dot3StatsCarrierSenseErrors = 5752 stats->stat_Dot3StatsCarrierSenseErrors; 5753 5754 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5755 5756 sc->stat_Dot3StatsAlignmentErrors = 5757 stats->stat_Dot3StatsAlignmentErrors; 5758 5759 sc->stat_Dot3StatsSingleCollisionFrames = 5760 stats->stat_Dot3StatsSingleCollisionFrames; 5761 5762 sc->stat_Dot3StatsMultipleCollisionFrames = 5763 stats->stat_Dot3StatsMultipleCollisionFrames; 5764 5765 sc->stat_Dot3StatsDeferredTransmissions = 5766 stats->stat_Dot3StatsDeferredTransmissions; 5767 5768 sc->stat_Dot3StatsExcessiveCollisions = 5769 stats->stat_Dot3StatsExcessiveCollisions; 5770 5771 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5772 5773 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5774 5775 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5776 5777 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5778 5779 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5780 5781 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5782 5783 sc->stat_EtherStatsPktsRx64Octets = 5784 stats->stat_EtherStatsPktsRx64Octets; 5785 5786 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5787 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5788 5789 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5790 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5791 5792 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5793 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5794 5795 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5796 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5797 5798 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5799 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5800 5801 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5802 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5803 5804 sc->stat_EtherStatsPktsTx64Octets = 5805 stats->stat_EtherStatsPktsTx64Octets; 5806 5807 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5808 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5809 5810 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5811 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5812 5813 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5814 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5815 5816 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5817 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5818 5819 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5820 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5821 5822 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5823 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5824 5825 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5826 5827 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5828 5829 sc->stat_OutXonSent = stats->stat_OutXonSent; 5830 5831 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5832 5833 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5834 5835 sc->stat_MacControlFramesReceived = 5836 stats->stat_MacControlFramesReceived; 5837 5838 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5839 5840 sc->stat_IfInFramesL2FilterDiscards = 5841 stats->stat_IfInFramesL2FilterDiscards; 5842 5843 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5844 5845 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5846 5847 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5848 5849 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5850 5851 sc->stat_CatchupInRuleCheckerDiscards = 5852 stats->stat_CatchupInRuleCheckerDiscards; 5853 5854 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5855 5856 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5857 5858 sc->stat_CatchupInRuleCheckerP4Hit = 5859 stats->stat_CatchupInRuleCheckerP4Hit; 5860 5861 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5862 } 5863 5864 void 5865 bnx_tick(void *xsc) 5866 { 5867 struct bnx_softc *sc = xsc; 5868 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5869 struct mii_data *mii; 5870 uint32_t msg; 5871 uint16_t prod, chain_prod; 5872 uint32_t prod_bseq; 5873 int s = splnet(); 5874 5875 /* Tell the firmware that the driver is still running. */ 5876 #ifdef BNX_DEBUG 5877 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5878 #else 5879 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5880 #endif 5881 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5882 5883 /* Update the statistics from the hardware statistics block. */ 5884 bnx_stats_update(sc); 5885 5886 /* Schedule the next tick. */ 5887 if (!sc->bnx_detaching) 5888 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5889 5890 if (sc->bnx_link) 5891 goto bnx_tick_exit; 5892 5893 mii = &sc->bnx_mii; 5894 mii_tick(mii); 5895 5896 /* Check if the link has come up. */ 5897 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5898 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5899 sc->bnx_link++; 5900 /* Now that link is up, handle any outstanding TX traffic. */ 5901 if_schedule_deferred_start(ifp); 5902 } 5903 5904 bnx_tick_exit: 5905 /* try to get more RX buffers, just in case */ 5906 prod = sc->rx_prod; 5907 prod_bseq = sc->rx_prod_bseq; 5908 chain_prod = RX_CHAIN_IDX(prod); 5909 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5910 sc->rx_prod = prod; 5911 sc->rx_prod_bseq = prod_bseq; 5912 5913 splx(s); 5914 return; 5915 } 5916 5917 /****************************************************************************/ 5918 /* BNX Debug Routines */ 5919 /****************************************************************************/ 5920 #ifdef BNX_DEBUG 5921 5922 /****************************************************************************/ 5923 /* Prints out information about an mbuf. */ 5924 /* */ 5925 /* Returns: */ 5926 /* Nothing. */ 5927 /****************************************************************************/ 5928 void 5929 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5930 { 5931 struct mbuf *mp = m; 5932 5933 if (m == NULL) { 5934 /* Index out of range. */ 5935 aprint_error("mbuf ptr is null!\n"); 5936 return; 5937 } 5938 5939 while (mp) { 5940 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5941 mp, mp->m_len); 5942 5943 if (mp->m_flags & M_EXT) 5944 aprint_debug("M_EXT "); 5945 if (mp->m_flags & M_PKTHDR) 5946 aprint_debug("M_PKTHDR "); 5947 aprint_debug("\n"); 5948 5949 if (mp->m_flags & M_EXT) 5950 aprint_debug("- m_ext: vaddr = %p, " 5951 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5952 5953 mp = mp->m_next; 5954 } 5955 } 5956 5957 /****************************************************************************/ 5958 /* Prints out the mbufs in the TX mbuf chain. */ 5959 /* */ 5960 /* Returns: */ 5961 /* Nothing. */ 5962 /****************************************************************************/ 5963 void 5964 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5965 { 5966 #if 0 5967 struct mbuf *m; 5968 int i; 5969 5970 aprint_debug_dev(sc->bnx_dev, 5971 "----------------------------" 5972 " tx mbuf data " 5973 "----------------------------\n"); 5974 5975 for (i = 0; i < count; i++) { 5976 m = sc->tx_mbuf_ptr[chain_prod]; 5977 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5978 bnx_dump_mbuf(sc, m); 5979 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5980 } 5981 5982 aprint_debug_dev(sc->bnx_dev, 5983 "--------------------------------------------" 5984 "----------------------------\n"); 5985 #endif 5986 } 5987 5988 /* 5989 * This routine prints the RX mbuf chain. 5990 */ 5991 void 5992 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5993 { 5994 struct mbuf *m; 5995 int i; 5996 5997 aprint_debug_dev(sc->bnx_dev, 5998 "----------------------------" 5999 " rx mbuf data " 6000 "----------------------------\n"); 6001 6002 for (i = 0; i < count; i++) { 6003 m = sc->rx_mbuf_ptr[chain_prod]; 6004 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6005 bnx_dump_mbuf(sc, m); 6006 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6007 } 6008 6009 6010 aprint_debug_dev(sc->bnx_dev, 6011 "--------------------------------------------" 6012 "----------------------------\n"); 6013 } 6014 6015 void 6016 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 6017 { 6018 if (idx > MAX_TX_BD) 6019 /* Index out of range. */ 6020 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6021 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6022 /* TX Chain page pointer. */ 6023 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 6024 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 6025 txbd->tx_bd_haddr_lo); 6026 else 6027 /* Normal tx_bd entry. */ 6028 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6029 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 6030 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6031 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6032 txbd->tx_bd_flags); 6033 } 6034 6035 void 6036 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 6037 { 6038 if (idx > MAX_RX_BD) 6039 /* Index out of range. */ 6040 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6041 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6042 /* TX Chain page pointer. */ 6043 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 6044 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 6045 rxbd->rx_bd_haddr_lo); 6046 else 6047 /* Normal tx_bd entry. */ 6048 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6049 "0x%08X, flags = 0x%08X\n", idx, 6050 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6051 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6052 } 6053 6054 void 6055 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6056 { 6057 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6058 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6059 "tcp_udp_xsum = 0x%04X\n", idx, 6060 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6061 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6062 l2fhdr->l2_fhdr_tcp_udp_xsum); 6063 } 6064 6065 /* 6066 * This routine prints the TX chain. 6067 */ 6068 void 6069 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 6070 { 6071 struct tx_bd *txbd; 6072 int i; 6073 6074 /* First some info about the tx_bd chain structure. */ 6075 aprint_debug_dev(sc->bnx_dev, 6076 "----------------------------" 6077 " tx_bd chain " 6078 "----------------------------\n"); 6079 6080 BNX_PRINTF(sc, 6081 "page size = 0x%08X, tx chain pages = 0x%08X\n", 6082 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6083 6084 BNX_PRINTF(sc, 6085 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6086 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6087 6088 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6089 6090 aprint_error_dev(sc->bnx_dev, "" 6091 "-----------------------------" 6092 " tx_bd data " 6093 "-----------------------------\n"); 6094 6095 /* Now print out the tx_bd's themselves. */ 6096 for (i = 0; i < count; i++) { 6097 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6098 bnx_dump_txbd(sc, tx_prod, txbd); 6099 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6100 } 6101 6102 aprint_debug_dev(sc->bnx_dev, 6103 "-----------------------------" 6104 "--------------" 6105 "-----------------------------\n"); 6106 } 6107 6108 /* 6109 * This routine prints the RX chain. 6110 */ 6111 void 6112 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6113 { 6114 struct rx_bd *rxbd; 6115 int i; 6116 6117 /* First some info about the tx_bd chain structure. */ 6118 aprint_debug_dev(sc->bnx_dev, 6119 "----------------------------" 6120 " rx_bd chain " 6121 "----------------------------\n"); 6122 6123 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6124 6125 BNX_PRINTF(sc, 6126 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6127 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6128 6129 BNX_PRINTF(sc, 6130 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6131 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6132 6133 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6134 6135 aprint_error_dev(sc->bnx_dev, 6136 "----------------------------" 6137 " rx_bd data " 6138 "----------------------------\n"); 6139 6140 /* Now print out the rx_bd's themselves. */ 6141 for (i = 0; i < count; i++) { 6142 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6143 bnx_dump_rxbd(sc, rx_prod, rxbd); 6144 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6145 } 6146 6147 aprint_debug_dev(sc->bnx_dev, 6148 "----------------------------" 6149 "--------------" 6150 "----------------------------\n"); 6151 } 6152 6153 /* 6154 * This routine prints the status block. 6155 */ 6156 void 6157 bnx_dump_status_block(struct bnx_softc *sc) 6158 { 6159 struct status_block *sblk; 6160 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6161 BUS_DMASYNC_POSTREAD); 6162 6163 sblk = sc->status_block; 6164 6165 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6166 "Status Block -----------------------------\n"); 6167 6168 BNX_PRINTF(sc, 6169 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6170 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6171 sblk->status_idx); 6172 6173 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6174 sblk->status_rx_quick_consumer_index0, 6175 sblk->status_tx_quick_consumer_index0); 6176 6177 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6178 6179 /* Theses indices are not used for normal L2 drivers. */ 6180 if (sblk->status_rx_quick_consumer_index1 || 6181 sblk->status_tx_quick_consumer_index1) 6182 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6183 sblk->status_rx_quick_consumer_index1, 6184 sblk->status_tx_quick_consumer_index1); 6185 6186 if (sblk->status_rx_quick_consumer_index2 || 6187 sblk->status_tx_quick_consumer_index2) 6188 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6189 sblk->status_rx_quick_consumer_index2, 6190 sblk->status_tx_quick_consumer_index2); 6191 6192 if (sblk->status_rx_quick_consumer_index3 || 6193 sblk->status_tx_quick_consumer_index3) 6194 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6195 sblk->status_rx_quick_consumer_index3, 6196 sblk->status_tx_quick_consumer_index3); 6197 6198 if (sblk->status_rx_quick_consumer_index4 || 6199 sblk->status_rx_quick_consumer_index5) 6200 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6201 sblk->status_rx_quick_consumer_index4, 6202 sblk->status_rx_quick_consumer_index5); 6203 6204 if (sblk->status_rx_quick_consumer_index6 || 6205 sblk->status_rx_quick_consumer_index7) 6206 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6207 sblk->status_rx_quick_consumer_index6, 6208 sblk->status_rx_quick_consumer_index7); 6209 6210 if (sblk->status_rx_quick_consumer_index8 || 6211 sblk->status_rx_quick_consumer_index9) 6212 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6213 sblk->status_rx_quick_consumer_index8, 6214 sblk->status_rx_quick_consumer_index9); 6215 6216 if (sblk->status_rx_quick_consumer_index10 || 6217 sblk->status_rx_quick_consumer_index11) 6218 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6219 sblk->status_rx_quick_consumer_index10, 6220 sblk->status_rx_quick_consumer_index11); 6221 6222 if (sblk->status_rx_quick_consumer_index12 || 6223 sblk->status_rx_quick_consumer_index13) 6224 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6225 sblk->status_rx_quick_consumer_index12, 6226 sblk->status_rx_quick_consumer_index13); 6227 6228 if (sblk->status_rx_quick_consumer_index14 || 6229 sblk->status_rx_quick_consumer_index15) 6230 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6231 sblk->status_rx_quick_consumer_index14, 6232 sblk->status_rx_quick_consumer_index15); 6233 6234 if (sblk->status_completion_producer_index || 6235 sblk->status_cmd_consumer_index) 6236 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6237 sblk->status_completion_producer_index, 6238 sblk->status_cmd_consumer_index); 6239 6240 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6241 "-----------------------------\n"); 6242 } 6243 6244 /* 6245 * This routine prints the statistics block. 6246 */ 6247 void 6248 bnx_dump_stats_block(struct bnx_softc *sc) 6249 { 6250 struct statistics_block *sblk; 6251 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6252 BUS_DMASYNC_POSTREAD); 6253 6254 sblk = sc->stats_block; 6255 6256 aprint_debug_dev(sc->bnx_dev, "" 6257 "-----------------------------" 6258 " Stats Block " 6259 "-----------------------------\n"); 6260 6261 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6262 "IfHcInBadOctets = 0x%08X:%08X\n", 6263 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6264 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6265 6266 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6267 "IfHcOutBadOctets = 0x%08X:%08X\n", 6268 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6269 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6270 6271 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6272 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6273 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6274 sblk->stat_IfHCInMulticastPkts_hi, 6275 sblk->stat_IfHCInMulticastPkts_lo); 6276 6277 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6278 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6279 sblk->stat_IfHCInBroadcastPkts_hi, 6280 sblk->stat_IfHCInBroadcastPkts_lo, 6281 sblk->stat_IfHCOutUcastPkts_hi, 6282 sblk->stat_IfHCOutUcastPkts_lo); 6283 6284 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6285 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6286 sblk->stat_IfHCOutMulticastPkts_hi, 6287 sblk->stat_IfHCOutMulticastPkts_lo, 6288 sblk->stat_IfHCOutBroadcastPkts_hi, 6289 sblk->stat_IfHCOutBroadcastPkts_lo); 6290 6291 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6292 BNX_PRINTF(sc, "0x%08X : " 6293 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6294 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6295 6296 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6297 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6298 sblk->stat_Dot3StatsCarrierSenseErrors); 6299 6300 if (sblk->stat_Dot3StatsFCSErrors) 6301 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6302 sblk->stat_Dot3StatsFCSErrors); 6303 6304 if (sblk->stat_Dot3StatsAlignmentErrors) 6305 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6306 sblk->stat_Dot3StatsAlignmentErrors); 6307 6308 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6309 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6310 sblk->stat_Dot3StatsSingleCollisionFrames); 6311 6312 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6313 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6314 sblk->stat_Dot3StatsMultipleCollisionFrames); 6315 6316 if (sblk->stat_Dot3StatsDeferredTransmissions) 6317 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6318 sblk->stat_Dot3StatsDeferredTransmissions); 6319 6320 if (sblk->stat_Dot3StatsExcessiveCollisions) 6321 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6322 sblk->stat_Dot3StatsExcessiveCollisions); 6323 6324 if (sblk->stat_Dot3StatsLateCollisions) 6325 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6326 sblk->stat_Dot3StatsLateCollisions); 6327 6328 if (sblk->stat_EtherStatsCollisions) 6329 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6330 sblk->stat_EtherStatsCollisions); 6331 6332 if (sblk->stat_EtherStatsFragments) 6333 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6334 sblk->stat_EtherStatsFragments); 6335 6336 if (sblk->stat_EtherStatsJabbers) 6337 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6338 sblk->stat_EtherStatsJabbers); 6339 6340 if (sblk->stat_EtherStatsUndersizePkts) 6341 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6342 sblk->stat_EtherStatsUndersizePkts); 6343 6344 if (sblk->stat_EtherStatsOverrsizePkts) 6345 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6346 sblk->stat_EtherStatsOverrsizePkts); 6347 6348 if (sblk->stat_EtherStatsPktsRx64Octets) 6349 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6350 sblk->stat_EtherStatsPktsRx64Octets); 6351 6352 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6353 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6354 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6355 6356 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6357 BNX_PRINTF(sc, "0x%08X : " 6358 "EtherStatsPktsRx128Octetsto255Octets\n", 6359 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6360 6361 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6362 BNX_PRINTF(sc, "0x%08X : " 6363 "EtherStatsPktsRx256Octetsto511Octets\n", 6364 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6365 6366 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6367 BNX_PRINTF(sc, "0x%08X : " 6368 "EtherStatsPktsRx512Octetsto1023Octets\n", 6369 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6370 6371 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6372 BNX_PRINTF(sc, "0x%08X : " 6373 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6374 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6375 6376 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6377 BNX_PRINTF(sc, "0x%08X : " 6378 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6379 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6380 6381 if (sblk->stat_EtherStatsPktsTx64Octets) 6382 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6383 sblk->stat_EtherStatsPktsTx64Octets); 6384 6385 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6386 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6387 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6388 6389 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6390 BNX_PRINTF(sc, "0x%08X : " 6391 "EtherStatsPktsTx128Octetsto255Octets\n", 6392 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6393 6394 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6395 BNX_PRINTF(sc, "0x%08X : " 6396 "EtherStatsPktsTx256Octetsto511Octets\n", 6397 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6398 6399 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6400 BNX_PRINTF(sc, "0x%08X : " 6401 "EtherStatsPktsTx512Octetsto1023Octets\n", 6402 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6403 6404 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6405 BNX_PRINTF(sc, "0x%08X : " 6406 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6407 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6408 6409 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6410 BNX_PRINTF(sc, "0x%08X : " 6411 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6412 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6413 6414 if (sblk->stat_XonPauseFramesReceived) 6415 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6416 sblk->stat_XonPauseFramesReceived); 6417 6418 if (sblk->stat_XoffPauseFramesReceived) 6419 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6420 sblk->stat_XoffPauseFramesReceived); 6421 6422 if (sblk->stat_OutXonSent) 6423 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6424 sblk->stat_OutXonSent); 6425 6426 if (sblk->stat_OutXoffSent) 6427 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6428 sblk->stat_OutXoffSent); 6429 6430 if (sblk->stat_FlowControlDone) 6431 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6432 sblk->stat_FlowControlDone); 6433 6434 if (sblk->stat_MacControlFramesReceived) 6435 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6436 sblk->stat_MacControlFramesReceived); 6437 6438 if (sblk->stat_XoffStateEntered) 6439 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6440 sblk->stat_XoffStateEntered); 6441 6442 if (sblk->stat_IfInFramesL2FilterDiscards) 6443 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6444 sblk->stat_IfInFramesL2FilterDiscards); 6445 6446 if (sblk->stat_IfInRuleCheckerDiscards) 6447 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6448 sblk->stat_IfInRuleCheckerDiscards); 6449 6450 if (sblk->stat_IfInFTQDiscards) 6451 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6452 sblk->stat_IfInFTQDiscards); 6453 6454 if (sblk->stat_IfInMBUFDiscards) 6455 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6456 sblk->stat_IfInMBUFDiscards); 6457 6458 if (sblk->stat_IfInRuleCheckerP4Hit) 6459 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6460 sblk->stat_IfInRuleCheckerP4Hit); 6461 6462 if (sblk->stat_CatchupInRuleCheckerDiscards) 6463 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6464 sblk->stat_CatchupInRuleCheckerDiscards); 6465 6466 if (sblk->stat_CatchupInFTQDiscards) 6467 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6468 sblk->stat_CatchupInFTQDiscards); 6469 6470 if (sblk->stat_CatchupInMBUFDiscards) 6471 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6472 sblk->stat_CatchupInMBUFDiscards); 6473 6474 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6475 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6476 sblk->stat_CatchupInRuleCheckerP4Hit); 6477 6478 aprint_debug_dev(sc->bnx_dev, 6479 "-----------------------------" 6480 "--------------" 6481 "-----------------------------\n"); 6482 } 6483 6484 void 6485 bnx_dump_driver_state(struct bnx_softc *sc) 6486 { 6487 aprint_debug_dev(sc->bnx_dev, 6488 "-----------------------------" 6489 " Driver State " 6490 "-----------------------------\n"); 6491 6492 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6493 "address\n", sc); 6494 6495 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6496 sc->status_block); 6497 6498 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6499 "address\n", sc->stats_block); 6500 6501 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6502 "address\n", sc->tx_bd_chain); 6503 6504 #if 0 6505 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6506 sc->rx_bd_chain); 6507 6508 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6509 sc->tx_mbuf_ptr); 6510 #endif 6511 6512 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6513 sc->rx_mbuf_ptr); 6514 6515 BNX_PRINTF(sc, 6516 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6517 sc->interrupts_generated); 6518 6519 BNX_PRINTF(sc, 6520 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6521 sc->rx_interrupts); 6522 6523 BNX_PRINTF(sc, 6524 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6525 sc->tx_interrupts); 6526 6527 BNX_PRINTF(sc, 6528 " 0x%08X - (sc->last_status_idx) status block index\n", 6529 sc->last_status_idx); 6530 6531 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6532 sc->tx_prod); 6533 6534 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6535 sc->tx_cons); 6536 6537 BNX_PRINTF(sc, 6538 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6539 sc->tx_prod_bseq); 6540 BNX_PRINTF(sc, 6541 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6542 sc->tx_mbuf_alloc); 6543 6544 BNX_PRINTF(sc, 6545 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6546 sc->used_tx_bd); 6547 6548 BNX_PRINTF(sc, 6549 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6550 sc->tx_hi_watermark, sc->max_tx_bd); 6551 6552 6553 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6554 sc->rx_prod); 6555 6556 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6557 sc->rx_cons); 6558 6559 BNX_PRINTF(sc, 6560 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6561 sc->rx_prod_bseq); 6562 6563 BNX_PRINTF(sc, 6564 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6565 sc->rx_mbuf_alloc); 6566 6567 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6568 sc->free_rx_bd); 6569 6570 BNX_PRINTF(sc, 6571 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6572 sc->rx_low_watermark, sc->max_rx_bd); 6573 6574 BNX_PRINTF(sc, 6575 " 0x%08X - (sc->mbuf_alloc_failed) " 6576 "mbuf alloc failures\n", 6577 sc->mbuf_alloc_failed); 6578 6579 BNX_PRINTF(sc, 6580 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6581 "simulated mbuf alloc failures\n", 6582 sc->mbuf_sim_alloc_failed); 6583 6584 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6585 "-----------------------------\n"); 6586 } 6587 6588 void 6589 bnx_dump_hw_state(struct bnx_softc *sc) 6590 { 6591 uint32_t val1; 6592 int i; 6593 6594 aprint_debug_dev(sc->bnx_dev, 6595 "----------------------------" 6596 " Hardware State " 6597 "----------------------------\n"); 6598 6599 val1 = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 6600 BNX_PRINTF(sc, "0x%08X : bootcode version\n", val1); 6601 6602 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6603 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6604 val1, BNX_MISC_ENABLE_STATUS_BITS); 6605 6606 val1 = REG_RD(sc, BNX_DMA_STATUS); 6607 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6608 6609 val1 = REG_RD(sc, BNX_CTX_STATUS); 6610 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6611 6612 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6613 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6614 BNX_EMAC_STATUS); 6615 6616 val1 = REG_RD(sc, BNX_RPM_STATUS); 6617 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6618 6619 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6620 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6621 BNX_TBDR_STATUS); 6622 6623 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6624 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6625 BNX_TDMA_STATUS); 6626 6627 val1 = REG_RD(sc, BNX_HC_STATUS); 6628 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6629 6630 aprint_debug_dev(sc->bnx_dev, 6631 "----------------------------" 6632 "----------------" 6633 "----------------------------\n"); 6634 6635 aprint_debug_dev(sc->bnx_dev, 6636 "----------------------------" 6637 " Register Dump " 6638 "----------------------------\n"); 6639 6640 for (i = 0x400; i < 0x8000; i += 0x10) 6641 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6642 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6643 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6644 6645 aprint_debug_dev(sc->bnx_dev, 6646 "----------------------------" 6647 "----------------" 6648 "----------------------------\n"); 6649 } 6650 6651 void 6652 bnx_breakpoint(struct bnx_softc *sc) 6653 { 6654 /* Unreachable code to shut the compiler up about unused functions. */ 6655 if (0) { 6656 bnx_dump_txbd(sc, 0, NULL); 6657 bnx_dump_rxbd(sc, 0, NULL); 6658 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6659 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6660 bnx_dump_l2fhdr(sc, 0, NULL); 6661 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6662 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6663 bnx_dump_status_block(sc); 6664 bnx_dump_stats_block(sc); 6665 bnx_dump_driver_state(sc); 6666 bnx_dump_hw_state(sc); 6667 } 6668 6669 bnx_dump_driver_state(sc); 6670 /* Print the important status block fields. */ 6671 bnx_dump_status_block(sc); 6672 6673 #if 0 6674 /* Call the debugger. */ 6675 breakpoint(); 6676 #endif 6677 6678 return; 6679 } 6680 #endif 6681
Indexes created Tue Sep 23 07:09:52 GMT 2025