if_bnx.c revision 1.88
1 /* $NetBSD: if_bnx.c,v 1.88 2019/11/10 21:16:36 chs Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.88 2019/11/10 21:16:36 chs Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 device_t dev = sc->bnx_dev; 466 int i = 0; 467 468 aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 469 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 470 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 471 ? "Serdes " : "", sc->bnx_chipid); 472 473 /* Bus info. */ 474 if (sc->bnx_flags & BNX_PCIE_FLAG) { 475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); 476 switch (sc->link_speed) { 477 case 1: aprint_normal("2.5GT/s\n"); break; 478 case 2: aprint_normal("5GT/s\n"); break; 479 default: aprint_normal("Unknown link speed\n"); 480 } 481 } else { 482 aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n", 483 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 484 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 485 sc->bus_speed_mhz); 486 } 487 488 /* Firmware version and device features. */ 489 aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (", 490 sc->bnx_bc_ver, RX_PAGES, TX_PAGES); 491 492 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) { 493 if (i > 0) aprint_normal("|"); 494 aprint_normal("2.5G"); i++; 495 } 496 497 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 498 if (i > 0) aprint_normal("|"); 499 aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver); 500 } else { 501 aprint_normal(")\n"); 502 } 503 504 aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 505 sc->bnx_rx_quick_cons_trip_int, 506 sc->bnx_rx_quick_cons_trip, 507 sc->bnx_rx_ticks_int, 508 sc->bnx_rx_ticks, 509 sc->bnx_tx_quick_cons_trip_int, 510 sc->bnx_tx_quick_cons_trip, 511 sc->bnx_tx_ticks_int, 512 sc->bnx_tx_ticks); 513 } 514 515 516 /****************************************************************************/ 517 /* PCI Capabilities Probe Function. */ 518 /* */ 519 /* Walks the PCI capabiites list for the device to find what features are */ 520 /* supported. */ 521 /* */ 522 /* Returns: */ 523 /* None. */ 524 /****************************************************************************/ 525 static void 526 bnx_probe_pci_caps(struct bnx_softc *sc) 527 { 528 struct pci_attach_args *pa = &(sc->bnx_pa); 529 pcireg_t reg; 530 531 /* Check if PCI-X capability is enabled. */ 532 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 533 NULL) != 0) { 534 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 535 } 536 537 /* Check if PCIe capability is enabled. */ 538 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 539 NULL) != 0) { 540 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 541 reg + PCIE_LCSR); 542 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 543 "0x%08X\n", link_status); 544 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 546 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 547 sc->bnx_flags |= BNX_PCIE_FLAG; 548 } 549 550 /* Check if MSI capability is enabled. */ 551 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 552 NULL) != 0) 553 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 554 555 /* Check if MSI-X capability is enabled. */ 556 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 557 NULL) != 0) 558 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 559 } 560 561 562 /****************************************************************************/ 563 /* Device attach function. */ 564 /* */ 565 /* Allocates device resources, performs secondary chip identification, */ 566 /* resets and initializes the hardware, and initializes driver instance */ 567 /* variables. */ 568 /* */ 569 /* Returns: */ 570 /* 0 on success, positive value on failure. */ 571 /****************************************************************************/ 572 void 573 bnx_attach(device_t parent, device_t self, void *aux) 574 { 575 const struct bnx_product *bp; 576 struct bnx_softc *sc = device_private(self); 577 prop_dictionary_t dict; 578 struct pci_attach_args *pa = aux; 579 pci_chipset_tag_t pc = pa->pa_pc; 580 pci_intr_handle_t ih; 581 const char *intrstr = NULL; 582 uint32_t command; 583 struct ifnet *ifp; 584 struct mii_data * const mii = &sc->bnx_mii; 585 uint32_t val; 586 int mii_flags = MIIF_FORCEANEG; 587 pcireg_t memtype; 588 char intrbuf[PCI_INTRSTR_LEN]; 589 int i, j; 590 591 if (bnx_tx_pool == NULL) { 592 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_WAITOK); 593 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 594 0, 0, 0, "bnxpkts", NULL, IPL_NET); 595 } 596 597 bp = bnx_lookup(pa); 598 if (bp == NULL) 599 panic("unknown device"); 600 601 sc->bnx_dev = self; 602 603 aprint_naive("\n"); 604 aprint_normal(": %s\n", bp->bp_name); 605 606 sc->bnx_pa = *pa; 607 608 /* 609 * Map control/status registers. 610 */ 611 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 612 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 613 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 614 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 615 616 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 617 aprint_error_dev(sc->bnx_dev, 618 "failed to enable memory mapping!\n"); 619 return; 620 } 621 622 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 623 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 624 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 625 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 626 return; 627 } 628 629 if (pci_intr_map(pa, &ih)) { 630 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 631 goto bnx_attach_fail; 632 } 633 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 634 635 /* 636 * Configure byte swap and enable indirect register access. 637 * Rely on CPU to do target byte swapping on big endian systems. 638 * Access to registers outside of PCI configurtion space are not 639 * valid until this is done. 640 */ 641 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 642 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 643 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 644 645 /* Save ASIC revsion info. */ 646 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 647 648 /* 649 * Find the base address for shared memory access. 650 * Newer versions of bootcode use a signature and offset 651 * while older versions use a fixed address. 652 */ 653 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 654 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 655 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 656 (sc->bnx_pa.pa_function << 2)); 657 else 658 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 659 660 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 661 662 /* Set initial device and PHY flags */ 663 sc->bnx_flags = 0; 664 sc->bnx_phy_flags = 0; 665 666 /* Fetch the bootcode revision. */ 667 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 668 for (i = 0, j = 0; i < 3; i++) { 669 uint8_t num; 670 int k, skip0; 671 672 num = (uint8_t)(val >> (24 - (i * 8))); 673 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 674 if (num >= k || !skip0 || k == 1) { 675 sc->bnx_bc_ver[j++] = (num / k) + '0'; 676 skip0 = 0; 677 } 678 } 679 if (i != 2) 680 sc->bnx_bc_ver[j++] = '.'; 681 } 682 683 /* Check if any management firmware is enabled. */ 684 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 685 if (val & BNX_PORT_FEATURE_ASF_ENABLED) { 686 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 687 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 688 689 /* Allow time for firmware to enter the running state. */ 690 for (i = 0; i < 30; i++) { 691 val = REG_RD_IND(sc, sc->bnx_shmem_base + 692 BNX_BC_STATE_CONDITION); 693 if (val & BNX_CONDITION_MFW_RUN_MASK) 694 break; 695 DELAY(10000); 696 } 697 698 /* Check if management firmware is running. */ 699 val = REG_RD_IND(sc, sc->bnx_shmem_base + 700 BNX_BC_STATE_CONDITION); 701 val &= BNX_CONDITION_MFW_RUN_MASK; 702 if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) && 703 (val != BNX_CONDITION_MFW_RUN_NONE)) { 704 uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base + 705 BNX_MFW_VER_PTR); 706 707 /* Read the management firmware version string. */ 708 for (j = 0; j < 3; j++) { 709 val = bnx_reg_rd_ind(sc, addr + j * 4); 710 val = bswap32(val); 711 memcpy(&sc->bnx_mfw_ver[i], &val, 4); 712 i += 4; 713 } 714 } else { 715 /* May cause firmware synchronization timeouts. */ 716 BNX_PRINTF(sc, "%s(%d): Management firmware enabled " 717 "but not running!\n", __FILE__, __LINE__); 718 strcpy(sc->bnx_mfw_ver, "NOT RUNNING!"); 719 720 /* ToDo: Any action the driver should take? */ 721 } 722 } 723 724 bnx_probe_pci_caps(sc); 725 726 /* Get PCI bus information (speed and type). */ 727 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 728 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 729 uint32_t clkreg; 730 731 sc->bnx_flags |= BNX_PCIX_FLAG; 732 733 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 734 735 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 736 switch (clkreg) { 737 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 738 sc->bus_speed_mhz = 133; 739 break; 740 741 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 742 sc->bus_speed_mhz = 100; 743 break; 744 745 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 746 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 747 sc->bus_speed_mhz = 66; 748 break; 749 750 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 751 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 752 sc->bus_speed_mhz = 50; 753 break; 754 755 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 756 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 757 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 758 sc->bus_speed_mhz = 33; 759 break; 760 } 761 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 762 sc->bus_speed_mhz = 66; 763 else 764 sc->bus_speed_mhz = 33; 765 766 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 767 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 768 769 /* Reset the controller. */ 770 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 771 goto bnx_attach_fail; 772 773 /* Initialize the controller. */ 774 if (bnx_chipinit(sc)) { 775 aprint_error_dev(sc->bnx_dev, 776 "Controller initialization failed!\n"); 777 goto bnx_attach_fail; 778 } 779 780 /* Perform NVRAM test. */ 781 if (bnx_nvram_test(sc)) { 782 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 783 goto bnx_attach_fail; 784 } 785 786 /* Fetch the permanent Ethernet MAC address. */ 787 bnx_get_mac_addr(sc); 788 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 789 ether_sprintf(sc->eaddr)); 790 791 /* 792 * Trip points control how many BDs 793 * should be ready before generating an 794 * interrupt while ticks control how long 795 * a BD can sit in the chain before 796 * generating an interrupt. Set the default 797 * values for the RX and TX rings. 798 */ 799 800 #ifdef BNX_DEBUG 801 /* Force more frequent interrupts. */ 802 sc->bnx_tx_quick_cons_trip_int = 1; 803 sc->bnx_tx_quick_cons_trip = 1; 804 sc->bnx_tx_ticks_int = 0; 805 sc->bnx_tx_ticks = 0; 806 807 sc->bnx_rx_quick_cons_trip_int = 1; 808 sc->bnx_rx_quick_cons_trip = 1; 809 sc->bnx_rx_ticks_int = 0; 810 sc->bnx_rx_ticks = 0; 811 #else 812 sc->bnx_tx_quick_cons_trip_int = 20; 813 sc->bnx_tx_quick_cons_trip = 20; 814 sc->bnx_tx_ticks_int = 80; 815 sc->bnx_tx_ticks = 80; 816 817 sc->bnx_rx_quick_cons_trip_int = 6; 818 sc->bnx_rx_quick_cons_trip = 6; 819 sc->bnx_rx_ticks_int = 18; 820 sc->bnx_rx_ticks = 18; 821 #endif 822 823 /* Update statistics once every second. */ 824 sc->bnx_stats_ticks = 1000000 & 0xffff00; 825 826 /* Find the media type for the adapter. */ 827 bnx_get_media(sc); 828 829 /* 830 * Store config data needed by the PHY driver for 831 * backplane applications 832 */ 833 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 834 BNX_SHARED_HW_CFG_CONFIG); 835 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 836 BNX_PORT_HW_CFG_CONFIG); 837 838 /* Allocate DMA memory resources. */ 839 sc->bnx_dmatag = pa->pa_dmat; 840 if (bnx_dma_alloc(sc)) { 841 aprint_error_dev(sc->bnx_dev, 842 "DMA resource allocation failed!\n"); 843 goto bnx_attach_fail; 844 } 845 846 /* Initialize the ifnet interface. */ 847 ifp = &sc->bnx_ec.ec_if; 848 ifp->if_softc = sc; 849 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 850 ifp->if_ioctl = bnx_ioctl; 851 ifp->if_stop = bnx_stop; 852 ifp->if_start = bnx_start; 853 ifp->if_init = bnx_init; 854 ifp->if_watchdog = bnx_watchdog; 855 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 856 IFQ_SET_READY(&ifp->if_snd); 857 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 858 859 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 860 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 861 sc->bnx_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 862 863 ifp->if_capabilities |= 864 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 865 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 866 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 867 868 /* create workqueue to handle packet allocations */ 869 if (workqueue_create(&sc->bnx_wq, device_xname(self), 870 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 871 aprint_error_dev(self, "failed to create workqueue\n"); 872 goto bnx_attach_fail; 873 } 874 875 mii->mii_ifp = ifp; 876 mii->mii_readreg = bnx_miibus_read_reg; 877 mii->mii_writereg = bnx_miibus_write_reg; 878 mii->mii_statchg = bnx_miibus_statchg; 879 880 /* Handle any special PHY initialization for SerDes PHYs. */ 881 bnx_init_media(sc); 882 883 sc->bnx_ec.ec_mii = mii; 884 ifmedia_init(&mii->mii_media, 0, bnx_ifmedia_upd, bnx_ifmedia_sts); 885 886 /* set phyflags and chipid before mii_attach() */ 887 dict = device_properties(self); 888 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 889 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 890 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 891 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 892 893 /* Print some useful adapter info */ 894 bnx_print_adapter_info(sc); 895 896 mii_flags |= MIIF_DOPAUSE; 897 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 898 mii_flags |= MIIF_HAVEFIBER; 899 mii_attach(self, mii, 0xffffffff, 900 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 901 902 if (LIST_EMPTY(&mii->mii_phys)) { 903 aprint_error_dev(self, "no PHY found!\n"); 904 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 905 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 906 } else 907 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 908 909 /* Attach to the Ethernet interface list. */ 910 if_attach(ifp); 911 if_deferred_start_init(ifp, NULL); 912 ether_ifattach(ifp, sc->eaddr); 913 914 callout_init(&sc->bnx_timeout, 0); 915 916 /* Hookup IRQ last. */ 917 sc->bnx_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, bnx_intr, 918 sc, device_xname(self)); 919 if (sc->bnx_intrhand == NULL) { 920 aprint_error_dev(self, "couldn't establish interrupt"); 921 if (intrstr != NULL) 922 aprint_error(" at %s", intrstr); 923 aprint_error("\n"); 924 goto bnx_attach_fail; 925 } 926 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 927 928 if (pmf_device_register(self, NULL, NULL)) 929 pmf_class_network_register(self, ifp); 930 else 931 aprint_error_dev(self, "couldn't establish power handler\n"); 932 933 /* Print some important debugging info. */ 934 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 935 936 /* Get the firmware running so ASF still works. */ 937 bnx_mgmt_init(sc); 938 939 goto bnx_attach_exit; 940 941 bnx_attach_fail: 942 bnx_release_resources(sc); 943 944 bnx_attach_exit: 945 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 946 } 947 948 /****************************************************************************/ 949 /* Device detach function. */ 950 /* */ 951 /* Stops the controller, resets the controller, and releases resources. */ 952 /* */ 953 /* Returns: */ 954 /* 0 on success, positive value on failure. */ 955 /****************************************************************************/ 956 int 957 bnx_detach(device_t dev, int flags) 958 { 959 int s; 960 struct bnx_softc *sc; 961 struct ifnet *ifp; 962 963 sc = device_private(dev); 964 ifp = &sc->bnx_ec.ec_if; 965 966 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 967 968 /* Stop and reset the controller. */ 969 s = splnet(); 970 bnx_stop(ifp, 1); 971 splx(s); 972 973 pmf_device_deregister(dev); 974 callout_destroy(&sc->bnx_timeout); 975 ether_ifdetach(ifp); 976 workqueue_destroy(sc->bnx_wq); 977 978 /* Delete all remaining media. */ 979 ifmedia_delete_instance(&sc->bnx_mii.mii_media, IFM_INST_ANY); 980 981 if_detach(ifp); 982 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 983 984 /* Release all remaining resources. */ 985 bnx_release_resources(sc); 986 987 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 988 989 return 0; 990 } 991 992 /****************************************************************************/ 993 /* Indirect register read. */ 994 /* */ 995 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 996 /* configuration space. Using this mechanism avoids issues with posted */ 997 /* reads but is much slower than memory-mapped I/O. */ 998 /* */ 999 /* Returns: */ 1000 /* The value of the register. */ 1001 /****************************************************************************/ 1002 uint32_t 1003 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 1004 { 1005 struct pci_attach_args *pa = &(sc->bnx_pa); 1006 1007 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1008 offset); 1009 #ifdef BNX_DEBUG 1010 { 1011 uint32_t val; 1012 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 1013 BNX_PCICFG_REG_WINDOW); 1014 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 1015 "val = 0x%08X\n", __func__, offset, val); 1016 return val; 1017 } 1018 #else 1019 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 1020 #endif 1021 } 1022 1023 /****************************************************************************/ 1024 /* Indirect register write. */ 1025 /* */ 1026 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1027 /* configuration space. Using this mechanism avoids issues with posted */ 1028 /* writes but is muchh slower than memory-mapped I/O. */ 1029 /* */ 1030 /* Returns: */ 1031 /* Nothing. */ 1032 /****************************************************************************/ 1033 void 1034 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 1035 { 1036 struct pci_attach_args *pa = &(sc->bnx_pa); 1037 1038 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 1039 __func__, offset, val); 1040 1041 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1042 offset); 1043 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 1044 } 1045 1046 /****************************************************************************/ 1047 /* Context memory write. */ 1048 /* */ 1049 /* The NetXtreme II controller uses context memory to track connection */ 1050 /* information for L2 and higher network protocols. */ 1051 /* */ 1052 /* Returns: */ 1053 /* Nothing. */ 1054 /****************************************************************************/ 1055 void 1056 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 1057 uint32_t ctx_val) 1058 { 1059 uint32_t idx, offset = ctx_offset + cid_addr; 1060 uint32_t val, retry_cnt = 5; 1061 1062 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1063 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1064 REG_WR(sc, BNX_CTX_CTX_CTRL, 1065 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 1066 1067 for (idx = 0; idx < retry_cnt; idx++) { 1068 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1069 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1070 break; 1071 DELAY(5); 1072 } 1073 1074 #if 0 1075 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1076 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1077 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1078 __FILE__, __LINE__, cid_addr, ctx_offset); 1079 #endif 1080 1081 } else { 1082 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1083 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1084 } 1085 } 1086 1087 /****************************************************************************/ 1088 /* PHY register read. */ 1089 /* */ 1090 /* Implements register reads on the MII bus. */ 1091 /* */ 1092 /* Returns: */ 1093 /* The value of the register. */ 1094 /****************************************************************************/ 1095 int 1096 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1097 { 1098 struct bnx_softc *sc = device_private(dev); 1099 uint32_t data; 1100 int i, rv = 0; 1101 1102 /* 1103 * The BCM5709S PHY is an IEEE Clause 45 PHY 1104 * with special mappings to work with IEEE 1105 * Clause 22 register accesses. 1106 */ 1107 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1108 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1109 reg += 0x10; 1110 } 1111 1112 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1113 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1114 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1115 1116 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1117 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1118 1119 DELAY(40); 1120 } 1121 1122 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1123 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1124 BNX_EMAC_MDIO_COMM_START_BUSY; 1125 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1126 1127 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1128 DELAY(10); 1129 1130 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1131 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1132 DELAY(5); 1133 1134 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1135 data &= BNX_EMAC_MDIO_COMM_DATA; 1136 1137 break; 1138 } 1139 } 1140 1141 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1142 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1143 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1144 rv = ETIMEDOUT; 1145 } else { 1146 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1147 *val = data & 0xffff; 1148 1149 DBPRINT(sc, BNX_EXCESSIVE, 1150 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1151 phy, (uint16_t) reg & 0xffff, *val); 1152 } 1153 1154 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1155 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1156 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1157 1158 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1159 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1160 1161 DELAY(40); 1162 } 1163 1164 return rv; 1165 } 1166 1167 /****************************************************************************/ 1168 /* PHY register write. */ 1169 /* */ 1170 /* Implements register writes on the MII bus. */ 1171 /* */ 1172 /* Returns: */ 1173 /* The value of the register. */ 1174 /****************************************************************************/ 1175 int 1176 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1177 { 1178 struct bnx_softc *sc = device_private(dev); 1179 uint32_t val1; 1180 int i, rv = 0; 1181 1182 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1183 "val = 0x%04hX\n", __func__, 1184 phy, (uint16_t) reg & 0xffff, val); 1185 1186 /* 1187 * The BCM5709S PHY is an IEEE Clause 45 PHY 1188 * with special mappings to work with IEEE 1189 * Clause 22 register accesses. 1190 */ 1191 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1192 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1193 reg += 0x10; 1194 } 1195 1196 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1197 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1198 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1199 1200 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1201 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1202 1203 DELAY(40); 1204 } 1205 1206 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1207 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1208 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1209 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1210 1211 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1212 DELAY(10); 1213 1214 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1215 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1216 DELAY(5); 1217 break; 1218 } 1219 } 1220 1221 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1222 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1223 __LINE__); 1224 rv = ETIMEDOUT; 1225 } 1226 1227 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1228 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1229 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1230 1231 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1232 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1233 1234 DELAY(40); 1235 } 1236 1237 return rv; 1238 } 1239 1240 /****************************************************************************/ 1241 /* MII bus status change. */ 1242 /* */ 1243 /* Called by the MII bus driver when the PHY establishes link to set the */ 1244 /* MAC interface registers. */ 1245 /* */ 1246 /* Returns: */ 1247 /* Nothing. */ 1248 /****************************************************************************/ 1249 void 1250 bnx_miibus_statchg(struct ifnet *ifp) 1251 { 1252 struct bnx_softc *sc = ifp->if_softc; 1253 struct mii_data *mii = &sc->bnx_mii; 1254 uint32_t rx_mode = sc->rx_mode; 1255 int val; 1256 1257 val = REG_RD(sc, BNX_EMAC_MODE); 1258 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1259 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1260 BNX_EMAC_MODE_25G); 1261 1262 /* 1263 * Get flow control negotiation result. 1264 */ 1265 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1266 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1267 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1268 mii->mii_media_active &= ~IFM_ETH_FMASK; 1269 } 1270 1271 /* Set MII or GMII interface based on the speed 1272 * negotiated by the PHY. 1273 */ 1274 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1275 case IFM_10_T: 1276 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1277 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1278 val |= BNX_EMAC_MODE_PORT_MII_10; 1279 break; 1280 } 1281 /* FALLTHROUGH */ 1282 case IFM_100_TX: 1283 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1284 val |= BNX_EMAC_MODE_PORT_MII; 1285 break; 1286 case IFM_2500_SX: 1287 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1288 val |= BNX_EMAC_MODE_25G; 1289 /* FALLTHROUGH */ 1290 case IFM_1000_T: 1291 case IFM_1000_SX: 1292 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1293 val |= BNX_EMAC_MODE_PORT_GMII; 1294 break; 1295 default: 1296 val |= BNX_EMAC_MODE_PORT_GMII; 1297 break; 1298 } 1299 1300 /* Set half or full duplex based on the duplicity 1301 * negotiated by the PHY. 1302 */ 1303 if ((mii->mii_media_active & IFM_HDX) != 0) { 1304 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1305 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1306 } else 1307 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1308 1309 REG_WR(sc, BNX_EMAC_MODE, val); 1310 1311 /* 1312 * 802.3x flow control 1313 */ 1314 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1315 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1316 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1317 } else { 1318 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1319 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1320 } 1321 1322 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1323 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1324 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1325 } else { 1326 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1327 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1328 } 1329 1330 /* Only make changes if the recive mode has actually changed. */ 1331 if (rx_mode != sc->rx_mode) { 1332 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1333 rx_mode); 1334 1335 sc->rx_mode = rx_mode; 1336 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1337 1338 bnx_init_rx_context(sc); 1339 } 1340 } 1341 1342 /****************************************************************************/ 1343 /* Acquire NVRAM lock. */ 1344 /* */ 1345 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1346 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1347 /* for use by the driver. */ 1348 /* */ 1349 /* Returns: */ 1350 /* 0 on success, positive value on failure. */ 1351 /****************************************************************************/ 1352 int 1353 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1354 { 1355 uint32_t val; 1356 int j; 1357 1358 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1359 1360 /* Request access to the flash interface. */ 1361 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1362 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1363 val = REG_RD(sc, BNX_NVM_SW_ARB); 1364 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1365 break; 1366 1367 DELAY(5); 1368 } 1369 1370 if (j >= NVRAM_TIMEOUT_COUNT) { 1371 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1372 return EBUSY; 1373 } 1374 1375 return 0; 1376 } 1377 1378 /****************************************************************************/ 1379 /* Release NVRAM lock. */ 1380 /* */ 1381 /* When the caller is finished accessing NVRAM the lock must be released. */ 1382 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1383 /* for use by the driver. */ 1384 /* */ 1385 /* Returns: */ 1386 /* 0 on success, positive value on failure. */ 1387 /****************************************************************************/ 1388 int 1389 bnx_release_nvram_lock(struct bnx_softc *sc) 1390 { 1391 int j; 1392 uint32_t val; 1393 1394 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1395 1396 /* Relinquish nvram interface. */ 1397 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1398 1399 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1400 val = REG_RD(sc, BNX_NVM_SW_ARB); 1401 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1402 break; 1403 1404 DELAY(5); 1405 } 1406 1407 if (j >= NVRAM_TIMEOUT_COUNT) { 1408 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1409 return EBUSY; 1410 } 1411 1412 return 0; 1413 } 1414 1415 #ifdef BNX_NVRAM_WRITE_SUPPORT 1416 /****************************************************************************/ 1417 /* Enable NVRAM write access. */ 1418 /* */ 1419 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1420 /* */ 1421 /* Returns: */ 1422 /* 0 on success, positive value on failure. */ 1423 /****************************************************************************/ 1424 int 1425 bnx_enable_nvram_write(struct bnx_softc *sc) 1426 { 1427 uint32_t val; 1428 1429 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1430 1431 val = REG_RD(sc, BNX_MISC_CFG); 1432 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1433 1434 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1435 int j; 1436 1437 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1438 REG_WR(sc, BNX_NVM_COMMAND, 1439 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1440 1441 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1442 DELAY(5); 1443 1444 val = REG_RD(sc, BNX_NVM_COMMAND); 1445 if (val & BNX_NVM_COMMAND_DONE) 1446 break; 1447 } 1448 1449 if (j >= NVRAM_TIMEOUT_COUNT) { 1450 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1451 return EBUSY; 1452 } 1453 } 1454 1455 return 0; 1456 } 1457 1458 /****************************************************************************/ 1459 /* Disable NVRAM write access. */ 1460 /* */ 1461 /* When the caller is finished writing to NVRAM write access must be */ 1462 /* disabled. */ 1463 /* */ 1464 /* Returns: */ 1465 /* Nothing. */ 1466 /****************************************************************************/ 1467 void 1468 bnx_disable_nvram_write(struct bnx_softc *sc) 1469 { 1470 uint32_t val; 1471 1472 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1473 1474 val = REG_RD(sc, BNX_MISC_CFG); 1475 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1476 } 1477 #endif 1478 1479 /****************************************************************************/ 1480 /* Enable NVRAM access. */ 1481 /* */ 1482 /* Before accessing NVRAM for read or write operations the caller must */ 1483 /* enabled NVRAM access. */ 1484 /* */ 1485 /* Returns: */ 1486 /* Nothing. */ 1487 /****************************************************************************/ 1488 void 1489 bnx_enable_nvram_access(struct bnx_softc *sc) 1490 { 1491 uint32_t val; 1492 1493 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1494 1495 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1496 /* Enable both bits, even on read. */ 1497 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1498 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1499 } 1500 1501 /****************************************************************************/ 1502 /* Disable NVRAM access. */ 1503 /* */ 1504 /* When the caller is finished accessing NVRAM access must be disabled. */ 1505 /* */ 1506 /* Returns: */ 1507 /* Nothing. */ 1508 /****************************************************************************/ 1509 void 1510 bnx_disable_nvram_access(struct bnx_softc *sc) 1511 { 1512 uint32_t val; 1513 1514 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1515 1516 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1517 1518 /* Disable both bits, even after read. */ 1519 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1520 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1521 } 1522 1523 #ifdef BNX_NVRAM_WRITE_SUPPORT 1524 /****************************************************************************/ 1525 /* Erase NVRAM page before writing. */ 1526 /* */ 1527 /* Non-buffered flash parts require that a page be erased before it is */ 1528 /* written. */ 1529 /* */ 1530 /* Returns: */ 1531 /* 0 on success, positive value on failure. */ 1532 /****************************************************************************/ 1533 int 1534 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1535 { 1536 uint32_t cmd; 1537 int j; 1538 1539 /* Buffered flash doesn't require an erase. */ 1540 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1541 return 0; 1542 1543 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1544 1545 /* Build an erase command. */ 1546 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1547 BNX_NVM_COMMAND_DOIT; 1548 1549 /* 1550 * Clear the DONE bit separately, set the NVRAM address to erase, 1551 * and issue the erase command. 1552 */ 1553 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1554 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1555 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1556 1557 /* Wait for completion. */ 1558 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1559 uint32_t val; 1560 1561 DELAY(5); 1562 1563 val = REG_RD(sc, BNX_NVM_COMMAND); 1564 if (val & BNX_NVM_COMMAND_DONE) 1565 break; 1566 } 1567 1568 if (j >= NVRAM_TIMEOUT_COUNT) { 1569 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1570 return EBUSY; 1571 } 1572 1573 return 0; 1574 } 1575 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1576 1577 /****************************************************************************/ 1578 /* Read a dword (32 bits) from NVRAM. */ 1579 /* */ 1580 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1581 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1582 /* */ 1583 /* Returns: */ 1584 /* 0 on success and the 32 bit value read, positive value on failure. */ 1585 /****************************************************************************/ 1586 int 1587 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1588 uint8_t *ret_val, uint32_t cmd_flags) 1589 { 1590 uint32_t cmd; 1591 int i, rc = 0; 1592 1593 /* Build the command word. */ 1594 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1595 1596 /* Calculate the offset for buffered flash if translation is used. */ 1597 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1598 offset = ((offset / sc->bnx_flash_info->page_size) << 1599 sc->bnx_flash_info->page_bits) + 1600 (offset % sc->bnx_flash_info->page_size); 1601 } 1602 1603 /* 1604 * Clear the DONE bit separately, set the address to read, 1605 * and issue the read. 1606 */ 1607 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1608 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1609 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1610 1611 /* Wait for completion. */ 1612 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1613 uint32_t val; 1614 1615 DELAY(5); 1616 1617 val = REG_RD(sc, BNX_NVM_COMMAND); 1618 if (val & BNX_NVM_COMMAND_DONE) { 1619 val = REG_RD(sc, BNX_NVM_READ); 1620 1621 val = be32toh(val); 1622 memcpy(ret_val, &val, 4); 1623 break; 1624 } 1625 } 1626 1627 /* Check for errors. */ 1628 if (i >= NVRAM_TIMEOUT_COUNT) { 1629 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1630 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1631 rc = EBUSY; 1632 } 1633 1634 return rc; 1635 } 1636 1637 #ifdef BNX_NVRAM_WRITE_SUPPORT 1638 /****************************************************************************/ 1639 /* Write a dword (32 bits) to NVRAM. */ 1640 /* */ 1641 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1642 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1643 /* enabled NVRAM write access. */ 1644 /* */ 1645 /* Returns: */ 1646 /* 0 on success, positive value on failure. */ 1647 /****************************************************************************/ 1648 int 1649 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1650 uint32_t cmd_flags) 1651 { 1652 uint32_t cmd, val32; 1653 int j; 1654 1655 /* Build the command word. */ 1656 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1657 1658 /* Calculate the offset for buffered flash if translation is used. */ 1659 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1660 offset = ((offset / sc->bnx_flash_info->page_size) << 1661 sc->bnx_flash_info->page_bits) + 1662 (offset % sc->bnx_flash_info->page_size); 1663 } 1664 1665 /* 1666 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1667 * set the NVRAM address to write, and issue the write command 1668 */ 1669 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1670 memcpy(&val32, val, 4); 1671 val32 = htobe32(val32); 1672 REG_WR(sc, BNX_NVM_WRITE, val32); 1673 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1674 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1675 1676 /* Wait for completion. */ 1677 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1678 DELAY(5); 1679 1680 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1681 break; 1682 } 1683 if (j >= NVRAM_TIMEOUT_COUNT) { 1684 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1685 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1686 return EBUSY; 1687 } 1688 1689 return 0; 1690 } 1691 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1692 1693 /****************************************************************************/ 1694 /* Initialize NVRAM access. */ 1695 /* */ 1696 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1697 /* access that device. */ 1698 /* */ 1699 /* Returns: */ 1700 /* 0 on success, positive value on failure. */ 1701 /****************************************************************************/ 1702 int 1703 bnx_init_nvram(struct bnx_softc *sc) 1704 { 1705 uint32_t val; 1706 int j, entry_count, rc = 0; 1707 struct flash_spec *flash; 1708 1709 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1710 1711 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1712 sc->bnx_flash_info = &flash_5709; 1713 goto bnx_init_nvram_get_flash_size; 1714 } 1715 1716 /* Determine the selected interface. */ 1717 val = REG_RD(sc, BNX_NVM_CFG1); 1718 1719 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1720 1721 /* 1722 * Flash reconfiguration is required to support additional 1723 * NVRAM devices not directly supported in hardware. 1724 * Check if the flash interface was reconfigured 1725 * by the bootcode. 1726 */ 1727 1728 if (val & 0x40000000) { 1729 /* Flash interface reconfigured by bootcode. */ 1730 1731 DBPRINT(sc, BNX_INFO_LOAD, 1732 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1733 1734 for (j = 0, flash = &flash_table[0]; j < entry_count; 1735 j++, flash++) { 1736 if ((val & FLASH_BACKUP_STRAP_MASK) == 1737 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1738 sc->bnx_flash_info = flash; 1739 break; 1740 } 1741 } 1742 } else { 1743 /* Flash interface not yet reconfigured. */ 1744 uint32_t mask; 1745 1746 DBPRINT(sc, BNX_INFO_LOAD, 1747 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1748 1749 if (val & (1 << 23)) 1750 mask = FLASH_BACKUP_STRAP_MASK; 1751 else 1752 mask = FLASH_STRAP_MASK; 1753 1754 /* Look for the matching NVRAM device configuration data. */ 1755 for (j = 0, flash = &flash_table[0]; j < entry_count; 1756 j++, flash++) { 1757 /* Check if the dev matches any of the known devices. */ 1758 if ((val & mask) == (flash->strapping & mask)) { 1759 /* Found a device match. */ 1760 sc->bnx_flash_info = flash; 1761 1762 /* Request access to the flash interface. */ 1763 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1764 return rc; 1765 1766 /* Reconfigure the flash interface. */ 1767 bnx_enable_nvram_access(sc); 1768 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1769 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1770 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1771 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1772 bnx_disable_nvram_access(sc); 1773 bnx_release_nvram_lock(sc); 1774 1775 break; 1776 } 1777 } 1778 } 1779 1780 /* Check if a matching device was found. */ 1781 if (j == entry_count) { 1782 sc->bnx_flash_info = NULL; 1783 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1784 __FILE__, __LINE__); 1785 rc = ENODEV; 1786 } 1787 1788 bnx_init_nvram_get_flash_size: 1789 /* Write the flash config data to the shared memory interface. */ 1790 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1791 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1792 if (val) 1793 sc->bnx_flash_size = val; 1794 else 1795 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1796 1797 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1798 "0x%08X\n", sc->bnx_flash_info->total_size); 1799 1800 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1801 1802 return rc; 1803 } 1804 1805 /****************************************************************************/ 1806 /* Read an arbitrary range of data from NVRAM. */ 1807 /* */ 1808 /* Prepares the NVRAM interface for access and reads the requested data */ 1809 /* into the supplied buffer. */ 1810 /* */ 1811 /* Returns: */ 1812 /* 0 on success and the data read, positive value on failure. */ 1813 /****************************************************************************/ 1814 int 1815 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1816 int buf_size) 1817 { 1818 int rc = 0; 1819 uint32_t cmd_flags, offset32, len32, extra; 1820 1821 if (buf_size == 0) 1822 return 0; 1823 1824 /* Request access to the flash interface. */ 1825 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1826 return rc; 1827 1828 /* Enable access to flash interface */ 1829 bnx_enable_nvram_access(sc); 1830 1831 len32 = buf_size; 1832 offset32 = offset; 1833 extra = 0; 1834 1835 cmd_flags = 0; 1836 1837 if (offset32 & 3) { 1838 uint8_t buf[4]; 1839 uint32_t pre_len; 1840 1841 offset32 &= ~3; 1842 pre_len = 4 - (offset & 3); 1843 1844 if (pre_len >= len32) { 1845 pre_len = len32; 1846 cmd_flags = 1847 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1848 } else 1849 cmd_flags = BNX_NVM_COMMAND_FIRST; 1850 1851 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1852 1853 if (rc) 1854 return rc; 1855 1856 memcpy(ret_buf, buf + (offset & 3), pre_len); 1857 1858 offset32 += 4; 1859 ret_buf += pre_len; 1860 len32 -= pre_len; 1861 } 1862 1863 if (len32 & 3) { 1864 extra = 4 - (len32 & 3); 1865 len32 = (len32 + 4) & ~3; 1866 } 1867 1868 if (len32 == 4) { 1869 uint8_t buf[4]; 1870 1871 if (cmd_flags) 1872 cmd_flags = BNX_NVM_COMMAND_LAST; 1873 else 1874 cmd_flags = 1875 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1876 1877 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1878 1879 memcpy(ret_buf, buf, 4 - extra); 1880 } else if (len32 > 0) { 1881 uint8_t buf[4]; 1882 1883 /* Read the first word. */ 1884 if (cmd_flags) 1885 cmd_flags = 0; 1886 else 1887 cmd_flags = BNX_NVM_COMMAND_FIRST; 1888 1889 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1890 1891 /* Advance to the next dword. */ 1892 offset32 += 4; 1893 ret_buf += 4; 1894 len32 -= 4; 1895 1896 while (len32 > 4 && rc == 0) { 1897 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1898 1899 /* Advance to the next dword. */ 1900 offset32 += 4; 1901 ret_buf += 4; 1902 len32 -= 4; 1903 } 1904 1905 if (rc) 1906 return rc; 1907 1908 cmd_flags = BNX_NVM_COMMAND_LAST; 1909 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1910 1911 memcpy(ret_buf, buf, 4 - extra); 1912 } 1913 1914 /* Disable access to flash interface and release the lock. */ 1915 bnx_disable_nvram_access(sc); 1916 bnx_release_nvram_lock(sc); 1917 1918 return rc; 1919 } 1920 1921 #ifdef BNX_NVRAM_WRITE_SUPPORT 1922 /****************************************************************************/ 1923 /* Write an arbitrary range of data from NVRAM. */ 1924 /* */ 1925 /* Prepares the NVRAM interface for write access and writes the requested */ 1926 /* data from the supplied buffer. The caller is responsible for */ 1927 /* calculating any appropriate CRCs. */ 1928 /* */ 1929 /* Returns: */ 1930 /* 0 on success, positive value on failure. */ 1931 /****************************************************************************/ 1932 int 1933 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1934 int buf_size) 1935 { 1936 uint32_t written, offset32, len32; 1937 uint8_t *buf, start[4], end[4]; 1938 int rc = 0; 1939 int align_start, align_end; 1940 1941 buf = data_buf; 1942 offset32 = offset; 1943 len32 = buf_size; 1944 align_start = align_end = 0; 1945 1946 if ((align_start = (offset32 & 3))) { 1947 offset32 &= ~3; 1948 len32 += align_start; 1949 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1950 return rc; 1951 } 1952 1953 if (len32 & 3) { 1954 if ((len32 > 4) || !align_start) { 1955 align_end = 4 - (len32 & 3); 1956 len32 += align_end; 1957 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1958 end, 4))) 1959 return rc; 1960 } 1961 } 1962 1963 if (align_start || align_end) { 1964 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1965 if (buf == NULL) 1966 return ENOMEM; 1967 1968 if (align_start) 1969 memcpy(buf, start, 4); 1970 1971 if (align_end) 1972 memcpy(buf + len32 - 4, end, 4); 1973 1974 memcpy(buf + align_start, data_buf, buf_size); 1975 } 1976 1977 written = 0; 1978 while ((written < len32) && (rc == 0)) { 1979 uint32_t page_start, page_end, data_start, data_end; 1980 uint32_t addr, cmd_flags; 1981 int i; 1982 uint8_t flash_buffer[264]; 1983 1984 /* Find the page_start addr */ 1985 page_start = offset32 + written; 1986 page_start -= (page_start % sc->bnx_flash_info->page_size); 1987 /* Find the page_end addr */ 1988 page_end = page_start + sc->bnx_flash_info->page_size; 1989 /* Find the data_start addr */ 1990 data_start = (written == 0) ? offset32 : page_start; 1991 /* Find the data_end addr */ 1992 data_end = (page_end > offset32 + len32) ? 1993 (offset32 + len32) : page_end; 1994 1995 /* Request access to the flash interface. */ 1996 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1997 goto nvram_write_end; 1998 1999 /* Enable access to flash interface */ 2000 bnx_enable_nvram_access(sc); 2001 2002 cmd_flags = BNX_NVM_COMMAND_FIRST; 2003 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2004 int j; 2005 2006 /* Read the whole page into the buffer 2007 * (non-buffer flash only) */ 2008 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 2009 if (j == (sc->bnx_flash_info->page_size - 4)) 2010 cmd_flags |= BNX_NVM_COMMAND_LAST; 2011 2012 rc = bnx_nvram_read_dword(sc, 2013 page_start + j, 2014 &flash_buffer[j], 2015 cmd_flags); 2016 2017 if (rc) 2018 goto nvram_write_end; 2019 2020 cmd_flags = 0; 2021 } 2022 } 2023 2024 /* Enable writes to flash interface (unlock write-protect) */ 2025 if ((rc = bnx_enable_nvram_write(sc)) != 0) 2026 goto nvram_write_end; 2027 2028 /* Erase the page */ 2029 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 2030 goto nvram_write_end; 2031 2032 /* Re-enable the write again for the actual write */ 2033 bnx_enable_nvram_write(sc); 2034 2035 /* Loop to write back the buffer data from page_start to 2036 * data_start */ 2037 i = 0; 2038 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2039 for (addr = page_start; addr < data_start; 2040 addr += 4, i += 4) { 2041 2042 rc = bnx_nvram_write_dword(sc, addr, 2043 &flash_buffer[i], cmd_flags); 2044 2045 if (rc != 0) 2046 goto nvram_write_end; 2047 2048 cmd_flags = 0; 2049 } 2050 } 2051 2052 /* Loop to write the new data from data_start to data_end */ 2053 for (addr = data_start; addr < data_end; addr += 4, i++) { 2054 if ((addr == page_end - 4) || 2055 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 2056 && (addr == data_end - 4))) { 2057 2058 cmd_flags |= BNX_NVM_COMMAND_LAST; 2059 } 2060 2061 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2062 2063 if (rc != 0) 2064 goto nvram_write_end; 2065 2066 cmd_flags = 0; 2067 buf += 4; 2068 } 2069 2070 /* Loop to write back the buffer data from data_end 2071 * to page_end */ 2072 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2073 for (addr = data_end; addr < page_end; 2074 addr += 4, i += 4) { 2075 2076 if (addr == page_end-4) 2077 cmd_flags = BNX_NVM_COMMAND_LAST; 2078 2079 rc = bnx_nvram_write_dword(sc, addr, 2080 &flash_buffer[i], cmd_flags); 2081 2082 if (rc != 0) 2083 goto nvram_write_end; 2084 2085 cmd_flags = 0; 2086 } 2087 } 2088 2089 /* Disable writes to flash interface (lock write-protect) */ 2090 bnx_disable_nvram_write(sc); 2091 2092 /* Disable access to flash interface */ 2093 bnx_disable_nvram_access(sc); 2094 bnx_release_nvram_lock(sc); 2095 2096 /* Increment written */ 2097 written += data_end - data_start; 2098 } 2099 2100 nvram_write_end: 2101 if (align_start || align_end) 2102 free(buf, M_DEVBUF); 2103 2104 return rc; 2105 } 2106 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2107 2108 /****************************************************************************/ 2109 /* Verifies that NVRAM is accessible and contains valid data. */ 2110 /* */ 2111 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2112 /* correct. */ 2113 /* */ 2114 /* Returns: */ 2115 /* 0 on success, positive value on failure. */ 2116 /****************************************************************************/ 2117 int 2118 bnx_nvram_test(struct bnx_softc *sc) 2119 { 2120 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2121 uint8_t *data = (uint8_t *) buf; 2122 int rc = 0; 2123 uint32_t magic, csum; 2124 2125 /* 2126 * Check that the device NVRAM is valid by reading 2127 * the magic value at offset 0. 2128 */ 2129 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2130 goto bnx_nvram_test_done; 2131 2132 magic = be32toh(buf[0]); 2133 if (magic != BNX_NVRAM_MAGIC) { 2134 rc = ENODEV; 2135 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2136 "Expected: 0x%08X, Found: 0x%08X\n", 2137 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2138 goto bnx_nvram_test_done; 2139 } 2140 2141 /* 2142 * Verify that the device NVRAM includes valid 2143 * configuration data. 2144 */ 2145 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2146 goto bnx_nvram_test_done; 2147 2148 csum = ether_crc32_le(data, 0x100); 2149 if (csum != BNX_CRC32_RESIDUAL) { 2150 rc = ENODEV; 2151 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2152 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2153 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2154 goto bnx_nvram_test_done; 2155 } 2156 2157 csum = ether_crc32_le(data + 0x100, 0x100); 2158 if (csum != BNX_CRC32_RESIDUAL) { 2159 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2160 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2161 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2162 rc = ENODEV; 2163 } 2164 2165 bnx_nvram_test_done: 2166 return rc; 2167 } 2168 2169 /****************************************************************************/ 2170 /* Identifies the current media type of the controller and sets the PHY */ 2171 /* address. */ 2172 /* */ 2173 /* Returns: */ 2174 /* Nothing. */ 2175 /****************************************************************************/ 2176 void 2177 bnx_get_media(struct bnx_softc *sc) 2178 { 2179 sc->bnx_phy_addr = 1; 2180 2181 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2182 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2183 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2184 uint32_t strap; 2185 2186 /* 2187 * The BCM5709S is software configurable 2188 * for Copper or SerDes operation. 2189 */ 2190 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2191 DBPRINT(sc, BNX_INFO_LOAD, 2192 "5709 bonded for copper.\n"); 2193 goto bnx_get_media_exit; 2194 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2195 DBPRINT(sc, BNX_INFO_LOAD, 2196 "5709 bonded for dual media.\n"); 2197 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2198 goto bnx_get_media_exit; 2199 } 2200 2201 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2202 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2203 else { 2204 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2205 >> 8; 2206 } 2207 2208 if (sc->bnx_pa.pa_function == 0) { 2209 switch (strap) { 2210 case 0x4: 2211 case 0x5: 2212 case 0x6: 2213 DBPRINT(sc, BNX_INFO_LOAD, 2214 "BCM5709 s/w configured for SerDes.\n"); 2215 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2216 break; 2217 default: 2218 DBPRINT(sc, BNX_INFO_LOAD, 2219 "BCM5709 s/w configured for Copper.\n"); 2220 } 2221 } else { 2222 switch (strap) { 2223 case 0x1: 2224 case 0x2: 2225 case 0x4: 2226 DBPRINT(sc, BNX_INFO_LOAD, 2227 "BCM5709 s/w configured for SerDes.\n"); 2228 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2229 break; 2230 default: 2231 DBPRINT(sc, BNX_INFO_LOAD, 2232 "BCM5709 s/w configured for Copper.\n"); 2233 } 2234 } 2235 2236 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2237 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2238 2239 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2240 uint32_t val; 2241 2242 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2243 2244 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2245 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2246 2247 /* 2248 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2249 * separate PHY for SerDes. 2250 */ 2251 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2252 sc->bnx_phy_addr = 2; 2253 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2254 BNX_SHARED_HW_CFG_CONFIG); 2255 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2256 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2257 DBPRINT(sc, BNX_INFO_LOAD, 2258 "Found 2.5Gb capable adapter\n"); 2259 } 2260 } 2261 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2262 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2263 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2264 2265 bnx_get_media_exit: 2266 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2267 "Using PHY address %d.\n", sc->bnx_phy_addr); 2268 } 2269 2270 /****************************************************************************/ 2271 /* Performs PHY initialization required before MII drivers access the */ 2272 /* device. */ 2273 /* */ 2274 /* Returns: */ 2275 /* Nothing. */ 2276 /****************************************************************************/ 2277 void 2278 bnx_init_media(struct bnx_softc *sc) 2279 { 2280 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2281 /* 2282 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2283 * IEEE Clause 22 method. Otherwise we have no way to attach 2284 * the PHY to the mii(4) layer. PHY specific configuration 2285 * is done by the mii(4) layer. 2286 */ 2287 2288 /* Select auto-negotiation MMD of the PHY. */ 2289 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2290 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2291 2292 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2293 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2294 2295 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2296 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2297 } 2298 } 2299 2300 /****************************************************************************/ 2301 /* Free any DMA memory owned by the driver. */ 2302 /* */ 2303 /* Scans through each data structre that requires DMA memory and frees */ 2304 /* the memory if allocated. */ 2305 /* */ 2306 /* Returns: */ 2307 /* Nothing. */ 2308 /****************************************************************************/ 2309 void 2310 bnx_dma_free(struct bnx_softc *sc) 2311 { 2312 int i; 2313 2314 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2315 2316 /* Destroy the status block. */ 2317 if (sc->status_block != NULL && sc->status_map != NULL) { 2318 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2319 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2320 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2321 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2322 BNX_STATUS_BLK_SZ); 2323 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2324 sc->status_rseg); 2325 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2326 sc->status_block = NULL; 2327 sc->status_map = NULL; 2328 } 2329 2330 /* Destroy the statistics block. */ 2331 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2332 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2333 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2334 BNX_STATS_BLK_SZ); 2335 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2336 sc->stats_rseg); 2337 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2338 sc->stats_block = NULL; 2339 sc->stats_map = NULL; 2340 } 2341 2342 /* Free, unmap and destroy all context memory pages. */ 2343 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2344 for (i = 0; i < sc->ctx_pages; i++) { 2345 if (sc->ctx_block[i] != NULL) { 2346 bus_dmamap_unload(sc->bnx_dmatag, 2347 sc->ctx_map[i]); 2348 bus_dmamem_unmap(sc->bnx_dmatag, 2349 (void *)sc->ctx_block[i], 2350 BCM_PAGE_SIZE); 2351 bus_dmamem_free(sc->bnx_dmatag, 2352 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2353 bus_dmamap_destroy(sc->bnx_dmatag, 2354 sc->ctx_map[i]); 2355 sc->ctx_block[i] = NULL; 2356 } 2357 } 2358 } 2359 2360 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2361 for (i = 0; i < TX_PAGES; i++ ) { 2362 if (sc->tx_bd_chain[i] != NULL && 2363 sc->tx_bd_chain_map[i] != NULL) { 2364 bus_dmamap_unload(sc->bnx_dmatag, 2365 sc->tx_bd_chain_map[i]); 2366 bus_dmamem_unmap(sc->bnx_dmatag, 2367 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2368 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2369 sc->tx_bd_chain_rseg[i]); 2370 bus_dmamap_destroy(sc->bnx_dmatag, 2371 sc->tx_bd_chain_map[i]); 2372 sc->tx_bd_chain[i] = NULL; 2373 sc->tx_bd_chain_map[i] = NULL; 2374 } 2375 } 2376 2377 /* Destroy the TX dmamaps. */ 2378 /* This isn't necessary since we dont allocate them up front */ 2379 2380 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2381 for (i = 0; i < RX_PAGES; i++ ) { 2382 if (sc->rx_bd_chain[i] != NULL && 2383 sc->rx_bd_chain_map[i] != NULL) { 2384 bus_dmamap_unload(sc->bnx_dmatag, 2385 sc->rx_bd_chain_map[i]); 2386 bus_dmamem_unmap(sc->bnx_dmatag, 2387 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2388 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2389 sc->rx_bd_chain_rseg[i]); 2390 2391 bus_dmamap_destroy(sc->bnx_dmatag, 2392 sc->rx_bd_chain_map[i]); 2393 sc->rx_bd_chain[i] = NULL; 2394 sc->rx_bd_chain_map[i] = NULL; 2395 } 2396 } 2397 2398 /* Unload and destroy the RX mbuf maps. */ 2399 for (i = 0; i < TOTAL_RX_BD; i++) { 2400 if (sc->rx_mbuf_map[i] != NULL) { 2401 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2402 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2403 } 2404 } 2405 2406 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2407 } 2408 2409 /****************************************************************************/ 2410 /* Allocate any DMA memory needed by the driver. */ 2411 /* */ 2412 /* Allocates DMA memory needed for the various global structures needed by */ 2413 /* hardware. */ 2414 /* */ 2415 /* Returns: */ 2416 /* 0 for success, positive value for failure. */ 2417 /****************************************************************************/ 2418 int 2419 bnx_dma_alloc(struct bnx_softc *sc) 2420 { 2421 int i, rc = 0; 2422 2423 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2424 2425 /* 2426 * Allocate DMA memory for the status block, map the memory into DMA 2427 * space, and fetch the physical address of the block. 2428 */ 2429 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2430 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2431 aprint_error_dev(sc->bnx_dev, 2432 "Could not create status block DMA map!\n"); 2433 rc = ENOMEM; 2434 goto bnx_dma_alloc_exit; 2435 } 2436 2437 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2438 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2439 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2440 aprint_error_dev(sc->bnx_dev, 2441 "Could not allocate status block DMA memory!\n"); 2442 rc = ENOMEM; 2443 goto bnx_dma_alloc_exit; 2444 } 2445 2446 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2447 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2448 aprint_error_dev(sc->bnx_dev, 2449 "Could not map status block DMA memory!\n"); 2450 rc = ENOMEM; 2451 goto bnx_dma_alloc_exit; 2452 } 2453 2454 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2455 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2456 aprint_error_dev(sc->bnx_dev, 2457 "Could not load status block DMA memory!\n"); 2458 rc = ENOMEM; 2459 goto bnx_dma_alloc_exit; 2460 } 2461 2462 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2463 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2464 2465 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2466 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2467 2468 /* DRC - Fix for 64 bit addresses. */ 2469 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2470 (uint32_t) sc->status_block_paddr); 2471 2472 /* BCM5709 uses host memory as cache for context memory. */ 2473 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2474 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2475 if (sc->ctx_pages == 0) 2476 sc->ctx_pages = 1; 2477 if (sc->ctx_pages > 4) /* XXX */ 2478 sc->ctx_pages = 4; 2479 2480 DBRUNIF((sc->ctx_pages > 512), 2481 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2482 __FILE__, __LINE__, sc->ctx_pages)); 2483 2484 2485 for (i = 0; i < sc->ctx_pages; i++) { 2486 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2487 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2488 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2489 &sc->ctx_map[i]) != 0) { 2490 rc = ENOMEM; 2491 goto bnx_dma_alloc_exit; 2492 } 2493 2494 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2495 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2496 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2497 rc = ENOMEM; 2498 goto bnx_dma_alloc_exit; 2499 } 2500 2501 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2502 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2503 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2504 rc = ENOMEM; 2505 goto bnx_dma_alloc_exit; 2506 } 2507 2508 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2509 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2510 BUS_DMA_NOWAIT) != 0) { 2511 rc = ENOMEM; 2512 goto bnx_dma_alloc_exit; 2513 } 2514 2515 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2516 } 2517 } 2518 2519 /* 2520 * Allocate DMA memory for the statistics block, map the memory into 2521 * DMA space, and fetch the physical address of the block. 2522 */ 2523 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2524 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2525 aprint_error_dev(sc->bnx_dev, 2526 "Could not create stats block DMA map!\n"); 2527 rc = ENOMEM; 2528 goto bnx_dma_alloc_exit; 2529 } 2530 2531 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2532 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2533 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2534 aprint_error_dev(sc->bnx_dev, 2535 "Could not allocate stats block DMA memory!\n"); 2536 rc = ENOMEM; 2537 goto bnx_dma_alloc_exit; 2538 } 2539 2540 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2541 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2542 aprint_error_dev(sc->bnx_dev, 2543 "Could not map stats block DMA memory!\n"); 2544 rc = ENOMEM; 2545 goto bnx_dma_alloc_exit; 2546 } 2547 2548 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2549 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2550 aprint_error_dev(sc->bnx_dev, 2551 "Could not load status block DMA memory!\n"); 2552 rc = ENOMEM; 2553 goto bnx_dma_alloc_exit; 2554 } 2555 2556 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2557 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2558 2559 /* DRC - Fix for 64 bit address. */ 2560 DBPRINT(sc, BNX_INFO, "stats_block_paddr = 0x%08X\n", 2561 (uint32_t) sc->stats_block_paddr); 2562 2563 /* 2564 * Allocate DMA memory for the TX buffer descriptor chain, 2565 * and fetch the physical address of the block. 2566 */ 2567 for (i = 0; i < TX_PAGES; i++) { 2568 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2569 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2570 &sc->tx_bd_chain_map[i])) { 2571 aprint_error_dev(sc->bnx_dev, 2572 "Could not create Tx desc %d DMA map!\n", i); 2573 rc = ENOMEM; 2574 goto bnx_dma_alloc_exit; 2575 } 2576 2577 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2578 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2579 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2580 aprint_error_dev(sc->bnx_dev, 2581 "Could not allocate TX desc %d DMA memory!\n", 2582 i); 2583 rc = ENOMEM; 2584 goto bnx_dma_alloc_exit; 2585 } 2586 2587 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2588 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2589 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2590 aprint_error_dev(sc->bnx_dev, 2591 "Could not map TX desc %d DMA memory!\n", i); 2592 rc = ENOMEM; 2593 goto bnx_dma_alloc_exit; 2594 } 2595 2596 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2597 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2598 BUS_DMA_NOWAIT)) { 2599 aprint_error_dev(sc->bnx_dev, 2600 "Could not load TX desc %d DMA memory!\n", i); 2601 rc = ENOMEM; 2602 goto bnx_dma_alloc_exit; 2603 } 2604 2605 sc->tx_bd_chain_paddr[i] = 2606 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2607 2608 /* DRC - Fix for 64 bit systems. */ 2609 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2610 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2611 } 2612 2613 /* 2614 * Create lists to hold TX mbufs. 2615 */ 2616 TAILQ_INIT(&sc->tx_free_pkts); 2617 TAILQ_INIT(&sc->tx_used_pkts); 2618 sc->tx_pkt_count = 0; 2619 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2620 2621 /* 2622 * Allocate DMA memory for the Rx buffer descriptor chain, 2623 * and fetch the physical address of the block. 2624 */ 2625 for (i = 0; i < RX_PAGES; i++) { 2626 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2627 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2628 &sc->rx_bd_chain_map[i])) { 2629 aprint_error_dev(sc->bnx_dev, 2630 "Could not create Rx desc %d DMA map!\n", i); 2631 rc = ENOMEM; 2632 goto bnx_dma_alloc_exit; 2633 } 2634 2635 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2636 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2637 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2638 aprint_error_dev(sc->bnx_dev, 2639 "Could not allocate Rx desc %d DMA memory!\n", i); 2640 rc = ENOMEM; 2641 goto bnx_dma_alloc_exit; 2642 } 2643 2644 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2645 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2646 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2647 aprint_error_dev(sc->bnx_dev, 2648 "Could not map Rx desc %d DMA memory!\n", i); 2649 rc = ENOMEM; 2650 goto bnx_dma_alloc_exit; 2651 } 2652 2653 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2654 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2655 BUS_DMA_NOWAIT)) { 2656 aprint_error_dev(sc->bnx_dev, 2657 "Could not load Rx desc %d DMA memory!\n", i); 2658 rc = ENOMEM; 2659 goto bnx_dma_alloc_exit; 2660 } 2661 2662 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2663 sc->rx_bd_chain_paddr[i] = 2664 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2665 2666 /* DRC - Fix for 64 bit systems. */ 2667 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2668 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2669 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2670 0, BNX_RX_CHAIN_PAGE_SZ, 2671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2672 } 2673 2674 /* 2675 * Create DMA maps for the Rx buffer mbufs. 2676 */ 2677 for (i = 0; i < TOTAL_RX_BD; i++) { 2678 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2679 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2680 &sc->rx_mbuf_map[i])) { 2681 aprint_error_dev(sc->bnx_dev, 2682 "Could not create Rx mbuf %d DMA map!\n", i); 2683 rc = ENOMEM; 2684 goto bnx_dma_alloc_exit; 2685 } 2686 } 2687 2688 bnx_dma_alloc_exit: 2689 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2690 2691 return rc; 2692 } 2693 2694 /****************************************************************************/ 2695 /* Release all resources used by the driver. */ 2696 /* */ 2697 /* Releases all resources acquired by the driver including interrupts, */ 2698 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2699 /* */ 2700 /* Returns: */ 2701 /* Nothing. */ 2702 /****************************************************************************/ 2703 void 2704 bnx_release_resources(struct bnx_softc *sc) 2705 { 2706 struct pci_attach_args *pa = &(sc->bnx_pa); 2707 2708 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2709 2710 bnx_dma_free(sc); 2711 2712 if (sc->bnx_intrhand != NULL) 2713 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2714 2715 if (sc->bnx_size) 2716 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2717 2718 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2719 } 2720 2721 /****************************************************************************/ 2722 /* Firmware synchronization. */ 2723 /* */ 2724 /* Before performing certain events such as a chip reset, synchronize with */ 2725 /* the firmware first. */ 2726 /* */ 2727 /* Returns: */ 2728 /* 0 for success, positive value for failure. */ 2729 /****************************************************************************/ 2730 int 2731 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2732 { 2733 int i, rc = 0; 2734 uint32_t val; 2735 2736 /* Don't waste any time if we've timed out before. */ 2737 if (sc->bnx_fw_timed_out) { 2738 rc = EBUSY; 2739 goto bnx_fw_sync_exit; 2740 } 2741 2742 /* Increment the message sequence number. */ 2743 sc->bnx_fw_wr_seq++; 2744 msg_data |= sc->bnx_fw_wr_seq; 2745 2746 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2747 msg_data); 2748 2749 /* Send the message to the bootcode driver mailbox. */ 2750 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2751 2752 /* Wait for the bootcode to acknowledge the message. */ 2753 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2754 /* Check for a response in the bootcode firmware mailbox. */ 2755 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2756 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2757 break; 2758 DELAY(1000); 2759 } 2760 2761 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2762 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2763 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2764 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2765 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2766 2767 msg_data &= ~BNX_DRV_MSG_CODE; 2768 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2769 2770 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2771 2772 sc->bnx_fw_timed_out = 1; 2773 rc = EBUSY; 2774 } 2775 2776 bnx_fw_sync_exit: 2777 return rc; 2778 } 2779 2780 /****************************************************************************/ 2781 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2782 /* */ 2783 /* Returns: */ 2784 /* Nothing. */ 2785 /****************************************************************************/ 2786 void 2787 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2788 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2789 { 2790 int i; 2791 uint32_t val; 2792 2793 /* Set the page size used by RV2P. */ 2794 if (rv2p_proc == RV2P_PROC2) { 2795 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2796 USABLE_RX_BD_PER_PAGE); 2797 } 2798 2799 for (i = 0; i < rv2p_code_len; i += 8) { 2800 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2801 rv2p_code++; 2802 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2803 rv2p_code++; 2804 2805 if (rv2p_proc == RV2P_PROC1) { 2806 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2807 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2808 } else { 2809 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2810 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2811 } 2812 } 2813 2814 /* Reset the processor, un-stall is done later. */ 2815 if (rv2p_proc == RV2P_PROC1) 2816 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2817 else 2818 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2819 } 2820 2821 /****************************************************************************/ 2822 /* Load RISC processor firmware. */ 2823 /* */ 2824 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2825 /* associated with a particular processor. */ 2826 /* */ 2827 /* Returns: */ 2828 /* Nothing. */ 2829 /****************************************************************************/ 2830 void 2831 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2832 struct fw_info *fw) 2833 { 2834 uint32_t offset; 2835 uint32_t val; 2836 2837 /* Halt the CPU. */ 2838 val = REG_RD_IND(sc, cpu_reg->mode); 2839 val |= cpu_reg->mode_value_halt; 2840 REG_WR_IND(sc, cpu_reg->mode, val); 2841 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2842 2843 /* Load the Text area. */ 2844 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2845 if (fw->text) { 2846 int j; 2847 2848 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2849 REG_WR_IND(sc, offset, fw->text[j]); 2850 } 2851 2852 /* Load the Data area. */ 2853 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2854 if (fw->data) { 2855 int j; 2856 2857 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2858 REG_WR_IND(sc, offset, fw->data[j]); 2859 } 2860 2861 /* Load the SBSS area. */ 2862 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2863 if (fw->sbss) { 2864 int j; 2865 2866 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2867 REG_WR_IND(sc, offset, fw->sbss[j]); 2868 } 2869 2870 /* Load the BSS area. */ 2871 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2872 if (fw->bss) { 2873 int j; 2874 2875 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2876 REG_WR_IND(sc, offset, fw->bss[j]); 2877 } 2878 2879 /* Load the Read-Only area. */ 2880 offset = cpu_reg->spad_base + 2881 (fw->rodata_addr - cpu_reg->mips_view_base); 2882 if (fw->rodata) { 2883 int j; 2884 2885 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2886 REG_WR_IND(sc, offset, fw->rodata[j]); 2887 } 2888 2889 /* Clear the pre-fetch instruction. */ 2890 REG_WR_IND(sc, cpu_reg->inst, 0); 2891 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2892 2893 /* Start the CPU. */ 2894 val = REG_RD_IND(sc, cpu_reg->mode); 2895 val &= ~cpu_reg->mode_value_halt; 2896 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2897 REG_WR_IND(sc, cpu_reg->mode, val); 2898 } 2899 2900 /****************************************************************************/ 2901 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2902 /* */ 2903 /* Loads the firmware for each CPU and starts the CPU. */ 2904 /* */ 2905 /* Returns: */ 2906 /* Nothing. */ 2907 /****************************************************************************/ 2908 void 2909 bnx_init_cpus(struct bnx_softc *sc) 2910 { 2911 struct cpu_reg cpu_reg; 2912 struct fw_info fw; 2913 2914 switch (BNX_CHIP_NUM(sc)) { 2915 case BNX_CHIP_NUM_5709: 2916 /* Initialize the RV2P processor. */ 2917 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2918 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2919 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2920 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2921 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2922 } else { 2923 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2924 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2925 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2926 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2927 } 2928 2929 /* Initialize the RX Processor. */ 2930 cpu_reg.mode = BNX_RXP_CPU_MODE; 2931 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2932 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2933 cpu_reg.state = BNX_RXP_CPU_STATE; 2934 cpu_reg.state_value_clear = 0xffffff; 2935 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2936 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2937 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2938 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2939 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2940 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2941 cpu_reg.mips_view_base = 0x8000000; 2942 2943 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2944 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2945 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2946 fw.start_addr = bnx_RXP_b09FwStartAddr; 2947 2948 fw.text_addr = bnx_RXP_b09FwTextAddr; 2949 fw.text_len = bnx_RXP_b09FwTextLen; 2950 fw.text_index = 0; 2951 fw.text = bnx_RXP_b09FwText; 2952 2953 fw.data_addr = bnx_RXP_b09FwDataAddr; 2954 fw.data_len = bnx_RXP_b09FwDataLen; 2955 fw.data_index = 0; 2956 fw.data = bnx_RXP_b09FwData; 2957 2958 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2959 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2960 fw.sbss_index = 0; 2961 fw.sbss = bnx_RXP_b09FwSbss; 2962 2963 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2964 fw.bss_len = bnx_RXP_b09FwBssLen; 2965 fw.bss_index = 0; 2966 fw.bss = bnx_RXP_b09FwBss; 2967 2968 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2969 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2970 fw.rodata_index = 0; 2971 fw.rodata = bnx_RXP_b09FwRodata; 2972 2973 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2974 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2975 2976 /* Initialize the TX Processor. */ 2977 cpu_reg.mode = BNX_TXP_CPU_MODE; 2978 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2979 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2980 cpu_reg.state = BNX_TXP_CPU_STATE; 2981 cpu_reg.state_value_clear = 0xffffff; 2982 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2983 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2984 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2985 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2986 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2987 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2988 cpu_reg.mips_view_base = 0x8000000; 2989 2990 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2991 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2992 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2993 fw.start_addr = bnx_TXP_b09FwStartAddr; 2994 2995 fw.text_addr = bnx_TXP_b09FwTextAddr; 2996 fw.text_len = bnx_TXP_b09FwTextLen; 2997 fw.text_index = 0; 2998 fw.text = bnx_TXP_b09FwText; 2999 3000 fw.data_addr = bnx_TXP_b09FwDataAddr; 3001 fw.data_len = bnx_TXP_b09FwDataLen; 3002 fw.data_index = 0; 3003 fw.data = bnx_TXP_b09FwData; 3004 3005 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 3006 fw.sbss_len = bnx_TXP_b09FwSbssLen; 3007 fw.sbss_index = 0; 3008 fw.sbss = bnx_TXP_b09FwSbss; 3009 3010 fw.bss_addr = bnx_TXP_b09FwBssAddr; 3011 fw.bss_len = bnx_TXP_b09FwBssLen; 3012 fw.bss_index = 0; 3013 fw.bss = bnx_TXP_b09FwBss; 3014 3015 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 3016 fw.rodata_len = bnx_TXP_b09FwRodataLen; 3017 fw.rodata_index = 0; 3018 fw.rodata = bnx_TXP_b09FwRodata; 3019 3020 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3021 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3022 3023 /* Initialize the TX Patch-up Processor. */ 3024 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3025 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3026 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3027 cpu_reg.state = BNX_TPAT_CPU_STATE; 3028 cpu_reg.state_value_clear = 0xffffff; 3029 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3030 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3031 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3032 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3033 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3034 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3035 cpu_reg.mips_view_base = 0x8000000; 3036 3037 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 3038 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 3039 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 3040 fw.start_addr = bnx_TPAT_b09FwStartAddr; 3041 3042 fw.text_addr = bnx_TPAT_b09FwTextAddr; 3043 fw.text_len = bnx_TPAT_b09FwTextLen; 3044 fw.text_index = 0; 3045 fw.text = bnx_TPAT_b09FwText; 3046 3047 fw.data_addr = bnx_TPAT_b09FwDataAddr; 3048 fw.data_len = bnx_TPAT_b09FwDataLen; 3049 fw.data_index = 0; 3050 fw.data = bnx_TPAT_b09FwData; 3051 3052 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 3053 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 3054 fw.sbss_index = 0; 3055 fw.sbss = bnx_TPAT_b09FwSbss; 3056 3057 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 3058 fw.bss_len = bnx_TPAT_b09FwBssLen; 3059 fw.bss_index = 0; 3060 fw.bss = bnx_TPAT_b09FwBss; 3061 3062 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3063 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3064 fw.rodata_index = 0; 3065 fw.rodata = bnx_TPAT_b09FwRodata; 3066 3067 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3068 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3069 3070 /* Initialize the Completion Processor. */ 3071 cpu_reg.mode = BNX_COM_CPU_MODE; 3072 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3073 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3074 cpu_reg.state = BNX_COM_CPU_STATE; 3075 cpu_reg.state_value_clear = 0xffffff; 3076 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3077 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3078 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3079 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3080 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3081 cpu_reg.spad_base = BNX_COM_SCRATCH; 3082 cpu_reg.mips_view_base = 0x8000000; 3083 3084 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3085 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3086 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3087 fw.start_addr = bnx_COM_b09FwStartAddr; 3088 3089 fw.text_addr = bnx_COM_b09FwTextAddr; 3090 fw.text_len = bnx_COM_b09FwTextLen; 3091 fw.text_index = 0; 3092 fw.text = bnx_COM_b09FwText; 3093 3094 fw.data_addr = bnx_COM_b09FwDataAddr; 3095 fw.data_len = bnx_COM_b09FwDataLen; 3096 fw.data_index = 0; 3097 fw.data = bnx_COM_b09FwData; 3098 3099 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3100 fw.sbss_len = bnx_COM_b09FwSbssLen; 3101 fw.sbss_index = 0; 3102 fw.sbss = bnx_COM_b09FwSbss; 3103 3104 fw.bss_addr = bnx_COM_b09FwBssAddr; 3105 fw.bss_len = bnx_COM_b09FwBssLen; 3106 fw.bss_index = 0; 3107 fw.bss = bnx_COM_b09FwBss; 3108 3109 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3110 fw.rodata_len = bnx_COM_b09FwRodataLen; 3111 fw.rodata_index = 0; 3112 fw.rodata = bnx_COM_b09FwRodata; 3113 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3114 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3115 break; 3116 default: 3117 /* Initialize the RV2P processor. */ 3118 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3119 RV2P_PROC1); 3120 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3121 RV2P_PROC2); 3122 3123 /* Initialize the RX Processor. */ 3124 cpu_reg.mode = BNX_RXP_CPU_MODE; 3125 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3126 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3127 cpu_reg.state = BNX_RXP_CPU_STATE; 3128 cpu_reg.state_value_clear = 0xffffff; 3129 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3130 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3131 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3132 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3133 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3134 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3135 cpu_reg.mips_view_base = 0x8000000; 3136 3137 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3138 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3139 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3140 fw.start_addr = bnx_RXP_b06FwStartAddr; 3141 3142 fw.text_addr = bnx_RXP_b06FwTextAddr; 3143 fw.text_len = bnx_RXP_b06FwTextLen; 3144 fw.text_index = 0; 3145 fw.text = bnx_RXP_b06FwText; 3146 3147 fw.data_addr = bnx_RXP_b06FwDataAddr; 3148 fw.data_len = bnx_RXP_b06FwDataLen; 3149 fw.data_index = 0; 3150 fw.data = bnx_RXP_b06FwData; 3151 3152 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3153 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3154 fw.sbss_index = 0; 3155 fw.sbss = bnx_RXP_b06FwSbss; 3156 3157 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3158 fw.bss_len = bnx_RXP_b06FwBssLen; 3159 fw.bss_index = 0; 3160 fw.bss = bnx_RXP_b06FwBss; 3161 3162 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3163 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3164 fw.rodata_index = 0; 3165 fw.rodata = bnx_RXP_b06FwRodata; 3166 3167 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3168 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3169 3170 /* Initialize the TX Processor. */ 3171 cpu_reg.mode = BNX_TXP_CPU_MODE; 3172 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3173 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3174 cpu_reg.state = BNX_TXP_CPU_STATE; 3175 cpu_reg.state_value_clear = 0xffffff; 3176 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3177 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3178 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3179 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3180 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3181 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3182 cpu_reg.mips_view_base = 0x8000000; 3183 3184 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3185 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3186 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3187 fw.start_addr = bnx_TXP_b06FwStartAddr; 3188 3189 fw.text_addr = bnx_TXP_b06FwTextAddr; 3190 fw.text_len = bnx_TXP_b06FwTextLen; 3191 fw.text_index = 0; 3192 fw.text = bnx_TXP_b06FwText; 3193 3194 fw.data_addr = bnx_TXP_b06FwDataAddr; 3195 fw.data_len = bnx_TXP_b06FwDataLen; 3196 fw.data_index = 0; 3197 fw.data = bnx_TXP_b06FwData; 3198 3199 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3200 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3201 fw.sbss_index = 0; 3202 fw.sbss = bnx_TXP_b06FwSbss; 3203 3204 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3205 fw.bss_len = bnx_TXP_b06FwBssLen; 3206 fw.bss_index = 0; 3207 fw.bss = bnx_TXP_b06FwBss; 3208 3209 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3210 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3211 fw.rodata_index = 0; 3212 fw.rodata = bnx_TXP_b06FwRodata; 3213 3214 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3215 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3216 3217 /* Initialize the TX Patch-up Processor. */ 3218 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3219 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3220 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3221 cpu_reg.state = BNX_TPAT_CPU_STATE; 3222 cpu_reg.state_value_clear = 0xffffff; 3223 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3224 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3225 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3226 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3227 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3228 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3229 cpu_reg.mips_view_base = 0x8000000; 3230 3231 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3232 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3233 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3234 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3235 3236 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3237 fw.text_len = bnx_TPAT_b06FwTextLen; 3238 fw.text_index = 0; 3239 fw.text = bnx_TPAT_b06FwText; 3240 3241 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3242 fw.data_len = bnx_TPAT_b06FwDataLen; 3243 fw.data_index = 0; 3244 fw.data = bnx_TPAT_b06FwData; 3245 3246 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3247 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3248 fw.sbss_index = 0; 3249 fw.sbss = bnx_TPAT_b06FwSbss; 3250 3251 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3252 fw.bss_len = bnx_TPAT_b06FwBssLen; 3253 fw.bss_index = 0; 3254 fw.bss = bnx_TPAT_b06FwBss; 3255 3256 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3257 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3258 fw.rodata_index = 0; 3259 fw.rodata = bnx_TPAT_b06FwRodata; 3260 3261 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3262 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3263 3264 /* Initialize the Completion Processor. */ 3265 cpu_reg.mode = BNX_COM_CPU_MODE; 3266 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3267 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3268 cpu_reg.state = BNX_COM_CPU_STATE; 3269 cpu_reg.state_value_clear = 0xffffff; 3270 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3271 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3272 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3273 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3274 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3275 cpu_reg.spad_base = BNX_COM_SCRATCH; 3276 cpu_reg.mips_view_base = 0x8000000; 3277 3278 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3279 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3280 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3281 fw.start_addr = bnx_COM_b06FwStartAddr; 3282 3283 fw.text_addr = bnx_COM_b06FwTextAddr; 3284 fw.text_len = bnx_COM_b06FwTextLen; 3285 fw.text_index = 0; 3286 fw.text = bnx_COM_b06FwText; 3287 3288 fw.data_addr = bnx_COM_b06FwDataAddr; 3289 fw.data_len = bnx_COM_b06FwDataLen; 3290 fw.data_index = 0; 3291 fw.data = bnx_COM_b06FwData; 3292 3293 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3294 fw.sbss_len = bnx_COM_b06FwSbssLen; 3295 fw.sbss_index = 0; 3296 fw.sbss = bnx_COM_b06FwSbss; 3297 3298 fw.bss_addr = bnx_COM_b06FwBssAddr; 3299 fw.bss_len = bnx_COM_b06FwBssLen; 3300 fw.bss_index = 0; 3301 fw.bss = bnx_COM_b06FwBss; 3302 3303 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3304 fw.rodata_len = bnx_COM_b06FwRodataLen; 3305 fw.rodata_index = 0; 3306 fw.rodata = bnx_COM_b06FwRodata; 3307 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3308 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3309 break; 3310 } 3311 } 3312 3313 /****************************************************************************/ 3314 /* Initialize context memory. */ 3315 /* */ 3316 /* Clears the memory associated with each Context ID (CID). */ 3317 /* */ 3318 /* Returns: */ 3319 /* Nothing. */ 3320 /****************************************************************************/ 3321 void 3322 bnx_init_context(struct bnx_softc *sc) 3323 { 3324 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3325 /* DRC: Replace this constant value with a #define. */ 3326 int i, retry_cnt = 10; 3327 uint32_t val; 3328 3329 /* 3330 * BCM5709 context memory may be cached 3331 * in host memory so prepare the host memory 3332 * for access. 3333 */ 3334 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3335 | (1 << 12); 3336 val |= (BCM_PAGE_BITS - 8) << 16; 3337 REG_WR(sc, BNX_CTX_COMMAND, val); 3338 3339 /* Wait for mem init command to complete. */ 3340 for (i = 0; i < retry_cnt; i++) { 3341 val = REG_RD(sc, BNX_CTX_COMMAND); 3342 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3343 break; 3344 DELAY(2); 3345 } 3346 3347 /* ToDo: Consider returning an error here. */ 3348 3349 for (i = 0; i < sc->ctx_pages; i++) { 3350 int j; 3351 3352 /* Set the physaddr of the context memory cache. */ 3353 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3354 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3355 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3356 val = (uint32_t) 3357 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3358 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3359 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3360 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3361 3362 /* Verify that the context memory write was successful. */ 3363 for (j = 0; j < retry_cnt; j++) { 3364 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3365 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3366 break; 3367 DELAY(5); 3368 } 3369 3370 /* ToDo: Consider returning an error here. */ 3371 } 3372 } else { 3373 uint32_t vcid_addr, offset; 3374 3375 /* 3376 * For the 5706/5708, context memory is local to the 3377 * controller, so initialize the controller context memory. 3378 */ 3379 3380 vcid_addr = GET_CID_ADDR(96); 3381 while (vcid_addr) { 3382 3383 vcid_addr -= BNX_PHY_CTX_SIZE; 3384 3385 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3386 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3387 3388 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3389 offset += 4) 3390 CTX_WR(sc, 0x00, offset, 0); 3391 3392 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3393 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3394 } 3395 } 3396 } 3397 3398 /****************************************************************************/ 3399 /* Fetch the permanent MAC address of the controller. */ 3400 /* */ 3401 /* Returns: */ 3402 /* Nothing. */ 3403 /****************************************************************************/ 3404 void 3405 bnx_get_mac_addr(struct bnx_softc *sc) 3406 { 3407 uint32_t mac_lo = 0, mac_hi = 0; 3408 3409 /* 3410 * The NetXtreme II bootcode populates various NIC 3411 * power-on and runtime configuration items in a 3412 * shared memory area. The factory configured MAC 3413 * address is available from both NVRAM and the 3414 * shared memory area so we'll read the value from 3415 * shared memory for speed. 3416 */ 3417 3418 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3419 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3420 3421 if ((mac_lo == 0) && (mac_hi == 0)) { 3422 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3423 __FILE__, __LINE__); 3424 } else { 3425 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3426 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3427 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3428 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3429 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3430 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3431 } 3432 3433 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3434 "%s\n", ether_sprintf(sc->eaddr)); 3435 } 3436 3437 /****************************************************************************/ 3438 /* Program the MAC address. */ 3439 /* */ 3440 /* Returns: */ 3441 /* Nothing. */ 3442 /****************************************************************************/ 3443 void 3444 bnx_set_mac_addr(struct bnx_softc *sc) 3445 { 3446 uint32_t val; 3447 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3448 3449 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3450 "%s\n", ether_sprintf(sc->eaddr)); 3451 3452 val = (mac_addr[0] << 8) | mac_addr[1]; 3453 3454 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3455 3456 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3457 (mac_addr[4] << 8) | mac_addr[5]; 3458 3459 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3460 } 3461 3462 /****************************************************************************/ 3463 /* Stop the controller. */ 3464 /* */ 3465 /* Returns: */ 3466 /* Nothing. */ 3467 /****************************************************************************/ 3468 void 3469 bnx_stop(struct ifnet *ifp, int disable) 3470 { 3471 struct bnx_softc *sc = ifp->if_softc; 3472 3473 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3474 3475 if (disable) { 3476 sc->bnx_detaching = 1; 3477 callout_halt(&sc->bnx_timeout, NULL); 3478 } else 3479 callout_stop(&sc->bnx_timeout); 3480 3481 mii_down(&sc->bnx_mii); 3482 3483 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3484 3485 /* Disable the transmit/receive blocks. */ 3486 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3487 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3488 DELAY(20); 3489 3490 bnx_disable_intr(sc); 3491 3492 /* Tell firmware that the driver is going away. */ 3493 if (disable) 3494 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3495 else 3496 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3497 3498 /* Free RX buffers. */ 3499 bnx_free_rx_chain(sc); 3500 3501 /* Free TX buffers. */ 3502 bnx_free_tx_chain(sc); 3503 3504 ifp->if_timer = 0; 3505 3506 sc->bnx_link = 0; 3507 3508 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3509 3510 bnx_mgmt_init(sc); 3511 } 3512 3513 int 3514 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3515 { 3516 struct pci_attach_args *pa = &(sc->bnx_pa); 3517 uint32_t val; 3518 int i, rc = 0; 3519 3520 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3521 3522 /* Wait for pending PCI transactions to complete. */ 3523 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 3524 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) { 3525 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3526 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3527 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3528 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3529 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3530 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3531 DELAY(5); 3532 } else { 3533 /* Disable DMA */ 3534 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3535 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3536 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3537 REG_RD(sc, BNX_MISC_NEW_CORE_CTL); /* barrier */ 3538 3539 for (i = 0; i < 100; i++) { 3540 delay(1 * 1000); 3541 val = REG_RD(sc, BNX_PCICFG_DEVICE_CONTROL); 3542 if ((val & PCIE_DCSR_TRANSACTION_PND) == 0) 3543 break; 3544 } 3545 } 3546 3547 /* Assume bootcode is running. */ 3548 sc->bnx_fw_timed_out = 0; 3549 3550 /* Give the firmware a chance to prepare for the reset. */ 3551 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3552 if (rc) 3553 goto bnx_reset_exit; 3554 3555 /* Set a firmware reminder that this is a soft reset. */ 3556 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3557 BNX_DRV_RESET_SIGNATURE_MAGIC); 3558 3559 /* Dummy read to force the chip to complete all current transactions. */ 3560 val = REG_RD(sc, BNX_MISC_ID); 3561 3562 /* Chip reset. */ 3563 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3564 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3565 REG_RD(sc, BNX_MISC_COMMAND); 3566 DELAY(5); 3567 3568 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3569 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3570 3571 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3572 val); 3573 } else { 3574 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3575 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3576 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3577 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3578 3579 /* Allow up to 30us for reset to complete. */ 3580 for (i = 0; i < 10; i++) { 3581 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3582 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3583 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3584 break; 3585 } 3586 DELAY(10); 3587 } 3588 3589 /* Check that reset completed successfully. */ 3590 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3591 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3592 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3593 __FILE__, __LINE__); 3594 rc = EBUSY; 3595 goto bnx_reset_exit; 3596 } 3597 } 3598 3599 /* Make sure byte swapping is properly configured. */ 3600 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3601 if (val != 0x01020304) { 3602 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3603 __FILE__, __LINE__); 3604 rc = ENODEV; 3605 goto bnx_reset_exit; 3606 } 3607 3608 /* Just completed a reset, assume that firmware is running again. */ 3609 sc->bnx_fw_timed_out = 0; 3610 3611 /* Wait for the firmware to finish its initialization. */ 3612 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3613 if (rc) 3614 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3615 "initialization!\n", __FILE__, __LINE__); 3616 3617 bnx_reset_exit: 3618 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3619 3620 return rc; 3621 } 3622 3623 int 3624 bnx_chipinit(struct bnx_softc *sc) 3625 { 3626 struct pci_attach_args *pa = &(sc->bnx_pa); 3627 uint32_t val; 3628 int rc = 0; 3629 3630 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3631 3632 /* Make sure the interrupt is not active. */ 3633 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3634 3635 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3636 /* channels and PCI clock compensation delay. */ 3637 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3638 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3639 #if BYTE_ORDER == BIG_ENDIAN 3640 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3641 #endif 3642 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3643 DMA_READ_CHANS << 12 | 3644 DMA_WRITE_CHANS << 16; 3645 3646 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3647 3648 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3649 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3650 3651 /* 3652 * This setting resolves a problem observed on certain Intel PCI 3653 * chipsets that cannot handle multiple outstanding DMA operations. 3654 * See errata E9_5706A1_65. 3655 */ 3656 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3657 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3658 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3659 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3660 3661 REG_WR(sc, BNX_DMA_CONFIG, val); 3662 3663 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3664 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3665 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3666 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3667 val & ~0x20000); 3668 } 3669 3670 /* Enable the RX_V2P and Context state machines before access. */ 3671 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3672 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3673 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3674 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3675 3676 /* Initialize context mapping and zero out the quick contexts. */ 3677 bnx_init_context(sc); 3678 3679 /* Initialize the on-boards CPUs */ 3680 bnx_init_cpus(sc); 3681 3682 /* Enable management frames (NC-SI) to flow to the MCP. */ 3683 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3684 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) | 3685 BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3686 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3687 } 3688 3689 /* Prepare NVRAM for access. */ 3690 if (bnx_init_nvram(sc)) { 3691 rc = ENODEV; 3692 goto bnx_chipinit_exit; 3693 } 3694 3695 /* Set the kernel bypass block size */ 3696 val = REG_RD(sc, BNX_MQ_CONFIG); 3697 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3698 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3699 3700 /* Enable bins used on the 5709. */ 3701 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3702 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3703 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3704 val |= BNX_MQ_CONFIG_HALT_DIS; 3705 } 3706 3707 REG_WR(sc, BNX_MQ_CONFIG, val); 3708 3709 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3710 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3711 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3712 3713 val = (BCM_PAGE_BITS - 8) << 24; 3714 REG_WR(sc, BNX_RV2P_CONFIG, val); 3715 3716 /* Configure page size. */ 3717 val = REG_RD(sc, BNX_TBDR_CONFIG); 3718 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3719 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3720 REG_WR(sc, BNX_TBDR_CONFIG, val); 3721 3722 #if 0 3723 /* Set the perfect match control register to default. */ 3724 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3725 #endif 3726 3727 bnx_chipinit_exit: 3728 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3729 3730 return rc; 3731 } 3732 3733 /****************************************************************************/ 3734 /* Initialize the controller in preparation to send/receive traffic. */ 3735 /* */ 3736 /* Returns: */ 3737 /* 0 for success, positive value for failure. */ 3738 /****************************************************************************/ 3739 int 3740 bnx_blockinit(struct bnx_softc *sc) 3741 { 3742 uint32_t reg, val; 3743 int rc = 0; 3744 3745 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3746 3747 /* Load the hardware default MAC address. */ 3748 bnx_set_mac_addr(sc); 3749 3750 /* Set the Ethernet backoff seed value */ 3751 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3752 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3753 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3754 3755 sc->last_status_idx = 0; 3756 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3757 3758 /* Set up link change interrupt generation. */ 3759 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3760 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3761 3762 /* Program the physical address of the status block. */ 3763 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3764 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3765 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3766 3767 /* Program the physical address of the statistics block. */ 3768 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3769 (uint32_t)(sc->stats_block_paddr)); 3770 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3771 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3772 3773 /* Program various host coalescing parameters. */ 3774 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3775 << 16) | sc->bnx_tx_quick_cons_trip); 3776 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3777 << 16) | sc->bnx_rx_quick_cons_trip); 3778 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3779 sc->bnx_comp_prod_trip); 3780 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3781 sc->bnx_tx_ticks); 3782 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3783 sc->bnx_rx_ticks); 3784 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3785 sc->bnx_com_ticks); 3786 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3787 sc->bnx_cmd_ticks); 3788 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3789 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3790 REG_WR(sc, BNX_HC_CONFIG, 3791 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3792 BNX_HC_CONFIG_COLLECT_STATS)); 3793 3794 /* Clear the internal statistics counters. */ 3795 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3796 3797 /* Verify that bootcode is running. */ 3798 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3799 3800 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3801 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3802 __FILE__, __LINE__); reg = 0); 3803 3804 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3805 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3806 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3807 "Expected: 08%08X\n", __FILE__, __LINE__, 3808 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3809 BNX_DEV_INFO_SIGNATURE_MAGIC); 3810 rc = ENODEV; 3811 goto bnx_blockinit_exit; 3812 } 3813 3814 /* Enable DMA */ 3815 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3816 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3817 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3818 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3819 } 3820 3821 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3822 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3823 3824 /* Disable management frames (NC-SI) from flowing to the MCP. */ 3825 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3826 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) & 3827 ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3828 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3829 } 3830 3831 /* Enable all remaining blocks in the MAC. */ 3832 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3833 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3834 BNX_MISC_ENABLE_DEFAULT_XI); 3835 } else 3836 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3837 3838 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3839 DELAY(20); 3840 3841 bnx_blockinit_exit: 3842 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3843 3844 return rc; 3845 } 3846 3847 static int 3848 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3849 uint16_t *chain_prod, uint32_t *prod_bseq) 3850 { 3851 bus_dmamap_t map; 3852 struct rx_bd *rxbd; 3853 uint32_t addr; 3854 int i; 3855 #ifdef BNX_DEBUG 3856 uint16_t debug_chain_prod = *chain_prod; 3857 #endif 3858 uint16_t first_chain_prod; 3859 3860 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3861 3862 /* Map the mbuf cluster into device memory. */ 3863 map = sc->rx_mbuf_map[*chain_prod]; 3864 first_chain_prod = *chain_prod; 3865 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3866 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3867 __FILE__, __LINE__); 3868 3869 m_freem(m_new); 3870 3871 DBRUNIF(1, sc->rx_mbuf_alloc--); 3872 3873 return ENOBUFS; 3874 } 3875 /* Make sure there is room in the receive chain. */ 3876 if (map->dm_nsegs > sc->free_rx_bd) { 3877 bus_dmamap_unload(sc->bnx_dmatag, map); 3878 m_freem(m_new); 3879 return EFBIG; 3880 } 3881 #ifdef BNX_DEBUG 3882 /* Track the distribution of buffer segments. */ 3883 sc->rx_mbuf_segs[map->dm_nsegs]++; 3884 #endif 3885 3886 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3887 BUS_DMASYNC_PREREAD); 3888 3889 /* Update some debug statistics counters */ 3890 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3891 sc->rx_low_watermark = sc->free_rx_bd); 3892 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3893 3894 /* 3895 * Setup the rx_bd for the first segment 3896 */ 3897 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3898 3899 addr = (uint32_t)map->dm_segs[0].ds_addr; 3900 rxbd->rx_bd_haddr_lo = addr; 3901 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3902 rxbd->rx_bd_haddr_hi = addr; 3903 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3904 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3905 *prod_bseq += map->dm_segs[0].ds_len; 3906 bus_dmamap_sync(sc->bnx_dmatag, 3907 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3908 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3909 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3910 3911 for (i = 1; i < map->dm_nsegs; i++) { 3912 *prod = NEXT_RX_BD(*prod); 3913 *chain_prod = RX_CHAIN_IDX(*prod); 3914 3915 rxbd = 3916 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3917 3918 addr = (uint32_t)map->dm_segs[i].ds_addr; 3919 rxbd->rx_bd_haddr_lo = addr; 3920 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3921 rxbd->rx_bd_haddr_hi = addr; 3922 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3923 rxbd->rx_bd_flags = 0; 3924 *prod_bseq += map->dm_segs[i].ds_len; 3925 bus_dmamap_sync(sc->bnx_dmatag, 3926 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3927 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3928 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3929 } 3930 3931 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3932 bus_dmamap_sync(sc->bnx_dmatag, 3933 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3934 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3935 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3936 3937 /* 3938 * Save the mbuf, adjust the map pointer (swap map for first and 3939 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3940 * and update our counter. 3941 */ 3942 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3943 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3944 sc->rx_mbuf_map[*chain_prod] = map; 3945 sc->free_rx_bd -= map->dm_nsegs; 3946 3947 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3948 map->dm_nsegs)); 3949 *prod = NEXT_RX_BD(*prod); 3950 *chain_prod = RX_CHAIN_IDX(*prod); 3951 3952 return 0; 3953 } 3954 3955 /****************************************************************************/ 3956 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3957 /* */ 3958 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3959 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3960 /* necessary. */ 3961 /* */ 3962 /* Returns: */ 3963 /* 0 for success, positive value for failure. */ 3964 /****************************************************************************/ 3965 int 3966 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3967 uint16_t *chain_prod, uint32_t *prod_bseq) 3968 { 3969 struct mbuf *m_new = NULL; 3970 int rc = 0; 3971 uint16_t min_free_bd; 3972 3973 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3974 __func__); 3975 3976 /* Make sure the inputs are valid. */ 3977 DBRUNIF((*chain_prod > MAX_RX_BD), 3978 aprint_error_dev(sc->bnx_dev, 3979 "RX producer out of range: 0x%04X > 0x%04X\n", 3980 *chain_prod, (uint16_t)MAX_RX_BD)); 3981 3982 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3983 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3984 *prod_bseq); 3985 3986 /* try to get in as many mbufs as possible */ 3987 if (sc->mbuf_alloc_size == MCLBYTES) 3988 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3989 else 3990 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3991 while (sc->free_rx_bd >= min_free_bd) { 3992 /* Simulate an mbuf allocation failure. */ 3993 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3994 aprint_error_dev(sc->bnx_dev, 3995 "Simulating mbuf allocation failure.\n"); 3996 sc->mbuf_sim_alloc_failed++; 3997 rc = ENOBUFS; 3998 goto bnx_get_buf_exit); 3999 4000 /* This is a new mbuf allocation. */ 4001 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4002 if (m_new == NULL) { 4003 DBPRINT(sc, BNX_WARN, 4004 "%s(%d): RX mbuf header allocation failed!\n", 4005 __FILE__, __LINE__); 4006 4007 sc->mbuf_alloc_failed++; 4008 4009 rc = ENOBUFS; 4010 goto bnx_get_buf_exit; 4011 } 4012 4013 DBRUNIF(1, sc->rx_mbuf_alloc++); 4014 4015 /* Simulate an mbuf cluster allocation failure. */ 4016 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4017 m_freem(m_new); 4018 sc->rx_mbuf_alloc--; 4019 sc->mbuf_alloc_failed++; 4020 sc->mbuf_sim_alloc_failed++; 4021 rc = ENOBUFS; 4022 goto bnx_get_buf_exit); 4023 4024 if (sc->mbuf_alloc_size == MCLBYTES) 4025 MCLGET(m_new, M_DONTWAIT); 4026 else 4027 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 4028 M_DONTWAIT); 4029 if (!(m_new->m_flags & M_EXT)) { 4030 DBPRINT(sc, BNX_WARN, 4031 "%s(%d): RX mbuf chain allocation failed!\n", 4032 __FILE__, __LINE__); 4033 4034 m_freem(m_new); 4035 4036 DBRUNIF(1, sc->rx_mbuf_alloc--); 4037 sc->mbuf_alloc_failed++; 4038 4039 rc = ENOBUFS; 4040 goto bnx_get_buf_exit; 4041 } 4042 4043 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 4044 if (rc != 0) 4045 goto bnx_get_buf_exit; 4046 } 4047 4048 bnx_get_buf_exit: 4049 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 4050 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 4051 *chain_prod, *prod_bseq); 4052 4053 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 4054 __func__); 4055 4056 return rc; 4057 } 4058 4059 void 4060 bnx_alloc_pkts(struct work * unused, void * arg) 4061 { 4062 struct bnx_softc *sc = arg; 4063 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4064 struct bnx_pkt *pkt; 4065 int i, s; 4066 4067 for (i = 0; i < 4; i++) { /* magic! */ 4068 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 4069 if (pkt == NULL) 4070 break; 4071 4072 if (bus_dmamap_create(sc->bnx_dmatag, 4073 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4074 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4075 &pkt->pkt_dmamap) != 0) 4076 goto put; 4077 4078 if (!ISSET(ifp->if_flags, IFF_UP)) 4079 goto stopping; 4080 4081 mutex_enter(&sc->tx_pkt_mtx); 4082 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4083 sc->tx_pkt_count++; 4084 mutex_exit(&sc->tx_pkt_mtx); 4085 } 4086 4087 mutex_enter(&sc->tx_pkt_mtx); 4088 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4089 mutex_exit(&sc->tx_pkt_mtx); 4090 4091 /* fire-up TX now that allocations have been done */ 4092 s = splnet(); 4093 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4094 bnx_start(ifp); 4095 splx(s); 4096 4097 return; 4098 4099 stopping: 4100 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4101 put: 4102 pool_put(bnx_tx_pool, pkt); 4103 return; 4104 } 4105 4106 /****************************************************************************/ 4107 /* Initialize the TX context memory. */ 4108 /* */ 4109 /* Returns: */ 4110 /* Nothing */ 4111 /****************************************************************************/ 4112 void 4113 bnx_init_tx_context(struct bnx_softc *sc) 4114 { 4115 uint32_t val; 4116 4117 /* Initialize the context ID for an L2 TX chain. */ 4118 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4119 /* Set the CID type to support an L2 connection. */ 4120 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4121 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4122 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4123 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4124 4125 /* Point the hardware to the first page in the chain. */ 4126 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4127 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4128 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4129 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4130 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4131 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4132 } else { 4133 /* Set the CID type to support an L2 connection. */ 4134 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4135 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4136 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4137 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4138 4139 /* Point the hardware to the first page in the chain. */ 4140 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4141 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4142 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4143 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4144 } 4145 } 4146 4147 4148 /****************************************************************************/ 4149 /* Allocate memory and initialize the TX data structures. */ 4150 /* */ 4151 /* Returns: */ 4152 /* 0 for success, positive value for failure. */ 4153 /****************************************************************************/ 4154 int 4155 bnx_init_tx_chain(struct bnx_softc *sc) 4156 { 4157 struct tx_bd *txbd; 4158 uint32_t addr; 4159 int i, rc = 0; 4160 4161 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4162 4163 /* Force an allocation of some dmamaps for tx up front */ 4164 bnx_alloc_pkts(NULL, sc); 4165 4166 /* Set the initial TX producer/consumer indices. */ 4167 sc->tx_prod = 0; 4168 sc->tx_cons = 0; 4169 sc->tx_prod_bseq = 0; 4170 sc->used_tx_bd = 0; 4171 sc->max_tx_bd = USABLE_TX_BD; 4172 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4173 DBRUNIF(1, sc->tx_full_count = 0); 4174 4175 /* 4176 * The NetXtreme II supports a linked-list structure called 4177 * a Buffer Descriptor Chain (or BD chain). A BD chain 4178 * consists of a series of 1 or more chain pages, each of which 4179 * consists of a fixed number of BD entries. 4180 * The last BD entry on each page is a pointer to the next page 4181 * in the chain, and the last pointer in the BD chain 4182 * points back to the beginning of the chain. 4183 */ 4184 4185 /* Set the TX next pointer chain entries. */ 4186 for (i = 0; i < TX_PAGES; i++) { 4187 int j; 4188 4189 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4190 4191 /* Check if we've reached the last page. */ 4192 if (i == (TX_PAGES - 1)) 4193 j = 0; 4194 else 4195 j = i + 1; 4196 4197 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4198 txbd->tx_bd_haddr_lo = addr; 4199 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4200 txbd->tx_bd_haddr_hi = addr; 4201 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4202 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4203 } 4204 4205 /* 4206 * Initialize the context ID for an L2 TX chain. 4207 */ 4208 bnx_init_tx_context(sc); 4209 4210 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4211 4212 return rc; 4213 } 4214 4215 /****************************************************************************/ 4216 /* Free memory and clear the TX data structures. */ 4217 /* */ 4218 /* Returns: */ 4219 /* Nothing. */ 4220 /****************************************************************************/ 4221 void 4222 bnx_free_tx_chain(struct bnx_softc *sc) 4223 { 4224 struct bnx_pkt *pkt; 4225 int i; 4226 4227 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4228 4229 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4230 mutex_enter(&sc->tx_pkt_mtx); 4231 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4232 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4233 mutex_exit(&sc->tx_pkt_mtx); 4234 4235 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4236 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4237 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4238 4239 m_freem(pkt->pkt_mbuf); 4240 DBRUNIF(1, sc->tx_mbuf_alloc--); 4241 4242 mutex_enter(&sc->tx_pkt_mtx); 4243 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4244 } 4245 4246 /* Destroy all the dmamaps we allocated for TX */ 4247 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4248 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4249 sc->tx_pkt_count--; 4250 mutex_exit(&sc->tx_pkt_mtx); 4251 4252 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4253 pool_put(bnx_tx_pool, pkt); 4254 4255 mutex_enter(&sc->tx_pkt_mtx); 4256 } 4257 mutex_exit(&sc->tx_pkt_mtx); 4258 4259 4260 4261 /* Clear each TX chain page. */ 4262 for (i = 0; i < TX_PAGES; i++) { 4263 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4264 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4265 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4266 } 4267 4268 sc->used_tx_bd = 0; 4269 4270 /* Check if we lost any mbufs in the process. */ 4271 DBRUNIF((sc->tx_mbuf_alloc), 4272 aprint_error_dev(sc->bnx_dev, 4273 "Memory leak! Lost %d mbufs from tx chain!\n", 4274 sc->tx_mbuf_alloc)); 4275 4276 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4277 } 4278 4279 /****************************************************************************/ 4280 /* Initialize the RX context memory. */ 4281 /* */ 4282 /* Returns: */ 4283 /* Nothing */ 4284 /****************************************************************************/ 4285 void 4286 bnx_init_rx_context(struct bnx_softc *sc) 4287 { 4288 uint32_t val; 4289 4290 /* Initialize the context ID for an L2 RX chain. */ 4291 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4292 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4293 4294 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4295 val |= 0x000000ff; 4296 4297 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4298 4299 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4300 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4301 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4302 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4303 } 4304 4305 /* Point the hardware to the first page in the chain. */ 4306 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4307 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4308 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4309 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4310 } 4311 4312 /****************************************************************************/ 4313 /* Allocate memory and initialize the RX data structures. */ 4314 /* */ 4315 /* Returns: */ 4316 /* 0 for success, positive value for failure. */ 4317 /****************************************************************************/ 4318 int 4319 bnx_init_rx_chain(struct bnx_softc *sc) 4320 { 4321 struct rx_bd *rxbd; 4322 int i, rc = 0; 4323 uint16_t prod, chain_prod; 4324 uint32_t prod_bseq, addr; 4325 4326 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4327 4328 /* Initialize the RX producer and consumer indices. */ 4329 sc->rx_prod = 0; 4330 sc->rx_cons = 0; 4331 sc->rx_prod_bseq = 0; 4332 sc->free_rx_bd = USABLE_RX_BD; 4333 sc->max_rx_bd = USABLE_RX_BD; 4334 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4335 DBRUNIF(1, sc->rx_empty_count = 0); 4336 4337 /* Initialize the RX next pointer chain entries. */ 4338 for (i = 0; i < RX_PAGES; i++) { 4339 int j; 4340 4341 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4342 4343 /* Check if we've reached the last page. */ 4344 if (i == (RX_PAGES - 1)) 4345 j = 0; 4346 else 4347 j = i + 1; 4348 4349 /* Setup the chain page pointers. */ 4350 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4351 rxbd->rx_bd_haddr_hi = addr; 4352 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4353 rxbd->rx_bd_haddr_lo = addr; 4354 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4355 0, BNX_RX_CHAIN_PAGE_SZ, 4356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4357 } 4358 4359 /* Allocate mbuf clusters for the rx_bd chain. */ 4360 prod = prod_bseq = 0; 4361 chain_prod = RX_CHAIN_IDX(prod); 4362 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4363 BNX_PRINTF(sc, 4364 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4365 } 4366 4367 /* Save the RX chain producer index. */ 4368 sc->rx_prod = prod; 4369 sc->rx_prod_bseq = prod_bseq; 4370 4371 for (i = 0; i < RX_PAGES; i++) 4372 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4373 sc->rx_bd_chain_map[i]->dm_mapsize, 4374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4375 4376 /* Tell the chip about the waiting rx_bd's. */ 4377 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4378 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4379 4380 bnx_init_rx_context(sc); 4381 4382 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4383 4384 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4385 4386 return rc; 4387 } 4388 4389 /****************************************************************************/ 4390 /* Free memory and clear the RX data structures. */ 4391 /* */ 4392 /* Returns: */ 4393 /* Nothing. */ 4394 /****************************************************************************/ 4395 void 4396 bnx_free_rx_chain(struct bnx_softc *sc) 4397 { 4398 int i; 4399 4400 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4401 4402 /* Free any mbufs still in the RX mbuf chain. */ 4403 for (i = 0; i < TOTAL_RX_BD; i++) { 4404 if (sc->rx_mbuf_ptr[i] != NULL) { 4405 if (sc->rx_mbuf_map[i] != NULL) { 4406 bus_dmamap_sync(sc->bnx_dmatag, 4407 sc->rx_mbuf_map[i], 0, 4408 sc->rx_mbuf_map[i]->dm_mapsize, 4409 BUS_DMASYNC_POSTREAD); 4410 bus_dmamap_unload(sc->bnx_dmatag, 4411 sc->rx_mbuf_map[i]); 4412 } 4413 m_freem(sc->rx_mbuf_ptr[i]); 4414 sc->rx_mbuf_ptr[i] = NULL; 4415 DBRUNIF(1, sc->rx_mbuf_alloc--); 4416 } 4417 } 4418 4419 /* Clear each RX chain page. */ 4420 for (i = 0; i < RX_PAGES; i++) 4421 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4422 4423 sc->free_rx_bd = sc->max_rx_bd; 4424 4425 /* Check if we lost any mbufs in the process. */ 4426 DBRUNIF((sc->rx_mbuf_alloc), 4427 aprint_error_dev(sc->bnx_dev, 4428 "Memory leak! Lost %d mbufs from rx chain!\n", 4429 sc->rx_mbuf_alloc)); 4430 4431 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4432 } 4433 4434 /****************************************************************************/ 4435 /* Set media options. */ 4436 /* */ 4437 /* Returns: */ 4438 /* 0 for success, positive value for failure. */ 4439 /****************************************************************************/ 4440 int 4441 bnx_ifmedia_upd(struct ifnet *ifp) 4442 { 4443 struct bnx_softc *sc; 4444 struct mii_data *mii; 4445 int rc = 0; 4446 4447 sc = ifp->if_softc; 4448 4449 mii = &sc->bnx_mii; 4450 sc->bnx_link = 0; 4451 if (mii->mii_instance) { 4452 struct mii_softc *miisc; 4453 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4454 mii_phy_reset(miisc); 4455 } 4456 mii_mediachg(mii); 4457 4458 return rc; 4459 } 4460 4461 /****************************************************************************/ 4462 /* Reports current media status. */ 4463 /* */ 4464 /* Returns: */ 4465 /* Nothing. */ 4466 /****************************************************************************/ 4467 void 4468 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4469 { 4470 struct bnx_softc *sc; 4471 struct mii_data *mii; 4472 int s; 4473 4474 sc = ifp->if_softc; 4475 4476 s = splnet(); 4477 4478 mii = &sc->bnx_mii; 4479 4480 mii_pollstat(mii); 4481 ifmr->ifm_status = mii->mii_media_status; 4482 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4483 sc->bnx_flowflags; 4484 4485 splx(s); 4486 } 4487 4488 /****************************************************************************/ 4489 /* Handles PHY generated interrupt events. */ 4490 /* */ 4491 /* Returns: */ 4492 /* Nothing. */ 4493 /****************************************************************************/ 4494 void 4495 bnx_phy_intr(struct bnx_softc *sc) 4496 { 4497 uint32_t new_link_state, old_link_state; 4498 4499 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4500 BUS_DMASYNC_POSTREAD); 4501 new_link_state = sc->status_block->status_attn_bits & 4502 STATUS_ATTN_BITS_LINK_STATE; 4503 old_link_state = sc->status_block->status_attn_bits_ack & 4504 STATUS_ATTN_BITS_LINK_STATE; 4505 4506 /* Handle any changes if the link state has changed. */ 4507 if (new_link_state != old_link_state) { 4508 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4509 4510 sc->bnx_link = 0; 4511 callout_stop(&sc->bnx_timeout); 4512 bnx_tick(sc); 4513 4514 /* Update the status_attn_bits_ack field in the status block. */ 4515 if (new_link_state) { 4516 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4517 STATUS_ATTN_BITS_LINK_STATE); 4518 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4519 } else { 4520 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4521 STATUS_ATTN_BITS_LINK_STATE); 4522 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4523 } 4524 } 4525 4526 /* Acknowledge the link change interrupt. */ 4527 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4528 } 4529 4530 /****************************************************************************/ 4531 /* Handles received frame interrupt events. */ 4532 /* */ 4533 /* Returns: */ 4534 /* Nothing. */ 4535 /****************************************************************************/ 4536 void 4537 bnx_rx_intr(struct bnx_softc *sc) 4538 { 4539 struct status_block *sblk = sc->status_block; 4540 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4541 uint16_t hw_cons, sw_cons, sw_chain_cons; 4542 uint16_t sw_prod, sw_chain_prod; 4543 uint32_t sw_prod_bseq; 4544 struct l2_fhdr *l2fhdr; 4545 int i; 4546 4547 DBRUNIF(1, sc->rx_interrupts++); 4548 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4549 BUS_DMASYNC_POSTREAD); 4550 4551 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4552 for (i = 0; i < RX_PAGES; i++) 4553 bus_dmamap_sync(sc->bnx_dmatag, 4554 sc->rx_bd_chain_map[i], 0, 4555 sc->rx_bd_chain_map[i]->dm_mapsize, 4556 BUS_DMASYNC_POSTWRITE); 4557 4558 /* Get the hardware's view of the RX consumer index. */ 4559 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4560 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4561 hw_cons++; 4562 4563 /* Get working copies of the driver's view of the RX indices. */ 4564 sw_cons = sc->rx_cons; 4565 sw_prod = sc->rx_prod; 4566 sw_prod_bseq = sc->rx_prod_bseq; 4567 4568 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4569 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4570 __func__, sw_prod, sw_cons, sw_prod_bseq); 4571 4572 /* Prevent speculative reads from getting ahead of the status block. */ 4573 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4574 BUS_SPACE_BARRIER_READ); 4575 4576 /* Update some debug statistics counters */ 4577 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4578 sc->rx_low_watermark = sc->free_rx_bd); 4579 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4580 4581 /* 4582 * Scan through the receive chain as long 4583 * as there is work to do. 4584 */ 4585 while (sw_cons != hw_cons) { 4586 struct mbuf *m; 4587 struct rx_bd *rxbd __diagused; 4588 unsigned int len; 4589 uint32_t status; 4590 4591 /* Convert the producer/consumer indices to an actual 4592 * rx_bd index. 4593 */ 4594 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4595 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4596 4597 /* Get the used rx_bd. */ 4598 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4599 sc->free_rx_bd++; 4600 4601 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4602 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4603 4604 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4605 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4606 #ifdef DIAGNOSTIC 4607 /* Validate that this is the last rx_bd. */ 4608 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4609 printf("%s: Unexpected mbuf found in " 4610 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4611 sw_chain_cons); 4612 } 4613 #endif 4614 4615 /* DRC - ToDo: If the received packet is small, say 4616 * less than 128 bytes, allocate a new mbuf 4617 * here, copy the data to that mbuf, and 4618 * recycle the mapped jumbo frame. 4619 */ 4620 4621 /* Unmap the mbuf from DMA space. */ 4622 #ifdef DIAGNOSTIC 4623 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4624 printf("invalid map sw_cons 0x%x " 4625 "sw_prod 0x%x " 4626 "sw_chain_cons 0x%x " 4627 "sw_chain_prod 0x%x " 4628 "hw_cons 0x%x " 4629 "TOTAL_RX_BD_PER_PAGE 0x%x " 4630 "TOTAL_RX_BD 0x%x\n", 4631 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4632 hw_cons, 4633 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4634 } 4635 #endif 4636 bus_dmamap_sync(sc->bnx_dmatag, 4637 sc->rx_mbuf_map[sw_chain_cons], 0, 4638 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4639 BUS_DMASYNC_POSTREAD); 4640 bus_dmamap_unload(sc->bnx_dmatag, 4641 sc->rx_mbuf_map[sw_chain_cons]); 4642 4643 /* Remove the mbuf from the driver's chain. */ 4644 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4645 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4646 4647 /* 4648 * Frames received on the NetXteme II are prepended 4649 * with the l2_fhdr structure which provides status 4650 * information about the received frame (including 4651 * VLAN tags and checksum info) and are also 4652 * automatically adjusted to align the IP header 4653 * (i.e. two null bytes are inserted before the 4654 * Ethernet header). 4655 */ 4656 l2fhdr = mtod(m, struct l2_fhdr *); 4657 4658 len = l2fhdr->l2_fhdr_pkt_len; 4659 status = l2fhdr->l2_fhdr_status; 4660 4661 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4662 aprint_error("Simulating l2_fhdr status error.\n"); 4663 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4664 4665 /* Watch for unusual sized frames. */ 4666 DBRUNIF(((len < BNX_MIN_MTU) || 4667 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4668 aprint_error_dev(sc->bnx_dev, 4669 "Unusual frame size found. " 4670 "Min(%d), Actual(%d), Max(%d)\n", 4671 (int)BNX_MIN_MTU, len, 4672 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4673 4674 bnx_dump_mbuf(sc, m); 4675 bnx_breakpoint(sc)); 4676 4677 len -= ETHER_CRC_LEN; 4678 4679 /* Check the received frame for errors. */ 4680 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4681 L2_FHDR_ERRORS_PHY_DECODE | 4682 L2_FHDR_ERRORS_ALIGNMENT | 4683 L2_FHDR_ERRORS_TOO_SHORT | 4684 L2_FHDR_ERRORS_GIANT_FRAME)) || 4685 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4686 len > 4687 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4688 ifp->if_ierrors++; 4689 DBRUNIF(1, sc->l2fhdr_status_errors++); 4690 4691 /* Reuse the mbuf for a new frame. */ 4692 if (bnx_add_buf(sc, m, &sw_prod, 4693 &sw_chain_prod, &sw_prod_bseq)) { 4694 DBRUNIF(1, bnx_breakpoint(sc)); 4695 panic("%s: Can't reuse RX mbuf!\n", 4696 device_xname(sc->bnx_dev)); 4697 } 4698 continue; 4699 } 4700 4701 /* 4702 * Get a new mbuf for the rx_bd. If no new 4703 * mbufs are available then reuse the current mbuf, 4704 * log an ierror on the interface, and generate 4705 * an error in the system log. 4706 */ 4707 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4708 &sw_prod_bseq)) { 4709 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4710 "Failed to allocate " 4711 "new mbuf, incoming frame dropped!\n")); 4712 4713 ifp->if_ierrors++; 4714 4715 /* Try and reuse the exisitng mbuf. */ 4716 if (bnx_add_buf(sc, m, &sw_prod, 4717 &sw_chain_prod, &sw_prod_bseq)) { 4718 DBRUNIF(1, bnx_breakpoint(sc)); 4719 panic("%s: Double mbuf allocation " 4720 "failure!", 4721 device_xname(sc->bnx_dev)); 4722 } 4723 continue; 4724 } 4725 4726 /* Skip over the l2_fhdr when passing the data up 4727 * the stack. 4728 */ 4729 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4730 4731 /* Adjust the pckt length to match the received data. */ 4732 m->m_pkthdr.len = m->m_len = len; 4733 4734 /* Send the packet to the appropriate interface. */ 4735 m_set_rcvif(m, ifp); 4736 4737 DBRUN(BNX_VERBOSE_RECV, 4738 struct ether_header *eh; 4739 eh = mtod(m, struct ether_header *); 4740 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4741 __func__, ether_sprintf(eh->ether_dhost), 4742 ether_sprintf(eh->ether_shost), 4743 htons(eh->ether_type))); 4744 4745 /* Validate the checksum. */ 4746 4747 /* Check for an IP datagram. */ 4748 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4749 /* Check if the IP checksum is valid. */ 4750 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4751 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4752 #ifdef BNX_DEBUG 4753 else 4754 DBPRINT(sc, BNX_WARN_SEND, 4755 "%s(): Invalid IP checksum " 4756 "= 0x%04X!\n", 4757 __func__, 4758 l2fhdr->l2_fhdr_ip_xsum 4759 ); 4760 #endif 4761 } 4762 4763 /* Check for a valid TCP/UDP frame. */ 4764 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4765 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4766 /* Check for a good TCP/UDP checksum. */ 4767 if ((status & 4768 (L2_FHDR_ERRORS_TCP_XSUM | 4769 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4770 m->m_pkthdr.csum_flags |= 4771 M_CSUM_TCPv4 | 4772 M_CSUM_UDPv4; 4773 } else { 4774 DBPRINT(sc, BNX_WARN_SEND, 4775 "%s(): Invalid TCP/UDP " 4776 "checksum = 0x%04X!\n", 4777 __func__, 4778 l2fhdr->l2_fhdr_tcp_udp_xsum); 4779 } 4780 } 4781 4782 /* 4783 * If we received a packet with a vlan tag, 4784 * attach that information to the packet. 4785 */ 4786 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4787 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4788 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4789 } 4790 4791 /* Pass the mbuf off to the upper layers. */ 4792 4793 DBPRINT(sc, BNX_VERBOSE_RECV, 4794 "%s(): Passing received frame up.\n", __func__); 4795 if_percpuq_enqueue(ifp->if_percpuq, m); 4796 DBRUNIF(1, sc->rx_mbuf_alloc--); 4797 4798 } 4799 4800 sw_cons = NEXT_RX_BD(sw_cons); 4801 4802 /* Refresh hw_cons to see if there's new work */ 4803 if (sw_cons == hw_cons) { 4804 hw_cons = sc->hw_rx_cons = 4805 sblk->status_rx_quick_consumer_index0; 4806 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4807 USABLE_RX_BD_PER_PAGE) 4808 hw_cons++; 4809 } 4810 4811 /* Prevent speculative reads from getting ahead of 4812 * the status block. 4813 */ 4814 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4815 BUS_SPACE_BARRIER_READ); 4816 } 4817 4818 for (i = 0; i < RX_PAGES; i++) 4819 bus_dmamap_sync(sc->bnx_dmatag, 4820 sc->rx_bd_chain_map[i], 0, 4821 sc->rx_bd_chain_map[i]->dm_mapsize, 4822 BUS_DMASYNC_PREWRITE); 4823 4824 sc->rx_cons = sw_cons; 4825 sc->rx_prod = sw_prod; 4826 sc->rx_prod_bseq = sw_prod_bseq; 4827 4828 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4829 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4830 4831 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4832 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4833 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4834 } 4835 4836 /****************************************************************************/ 4837 /* Handles transmit completion interrupt events. */ 4838 /* */ 4839 /* Returns: */ 4840 /* Nothing. */ 4841 /****************************************************************************/ 4842 void 4843 bnx_tx_intr(struct bnx_softc *sc) 4844 { 4845 struct status_block *sblk = sc->status_block; 4846 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4847 struct bnx_pkt *pkt; 4848 bus_dmamap_t map; 4849 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4850 4851 DBRUNIF(1, sc->tx_interrupts++); 4852 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4853 BUS_DMASYNC_POSTREAD); 4854 4855 /* Get the hardware's view of the TX consumer index. */ 4856 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4857 4858 /* Skip to the next entry if this is a chain page pointer. */ 4859 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4860 hw_tx_cons++; 4861 4862 sw_tx_cons = sc->tx_cons; 4863 4864 /* Prevent speculative reads from getting ahead of the status block. */ 4865 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4866 BUS_SPACE_BARRIER_READ); 4867 4868 /* Cycle through any completed TX chain page entries. */ 4869 while (sw_tx_cons != hw_tx_cons) { 4870 #ifdef BNX_DEBUG 4871 struct tx_bd *txbd = NULL; 4872 #endif 4873 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4874 4875 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4876 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4877 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4878 4879 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4880 aprint_error_dev(sc->bnx_dev, 4881 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4882 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4883 4884 DBRUNIF(1, txbd = &sc->tx_bd_chain 4885 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4886 4887 DBRUNIF((txbd == NULL), 4888 aprint_error_dev(sc->bnx_dev, 4889 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4890 bnx_breakpoint(sc)); 4891 4892 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4893 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4894 4895 4896 mutex_enter(&sc->tx_pkt_mtx); 4897 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4898 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4899 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4900 mutex_exit(&sc->tx_pkt_mtx); 4901 /* 4902 * Free the associated mbuf. Remember 4903 * that only the last tx_bd of a packet 4904 * has an mbuf pointer and DMA map. 4905 */ 4906 map = pkt->pkt_dmamap; 4907 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4908 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4909 bus_dmamap_unload(sc->bnx_dmatag, map); 4910 4911 m_freem(pkt->pkt_mbuf); 4912 DBRUNIF(1, sc->tx_mbuf_alloc--); 4913 4914 ifp->if_opackets++; 4915 4916 mutex_enter(&sc->tx_pkt_mtx); 4917 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4918 } 4919 mutex_exit(&sc->tx_pkt_mtx); 4920 4921 sc->used_tx_bd--; 4922 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4923 __FILE__, __LINE__, sc->used_tx_bd); 4924 4925 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4926 4927 /* Refresh hw_cons to see if there's new work. */ 4928 hw_tx_cons = sc->hw_tx_cons = 4929 sblk->status_tx_quick_consumer_index0; 4930 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4931 USABLE_TX_BD_PER_PAGE) 4932 hw_tx_cons++; 4933 4934 /* Prevent speculative reads from getting ahead of 4935 * the status block. 4936 */ 4937 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4938 BUS_SPACE_BARRIER_READ); 4939 } 4940 4941 /* Clear the TX timeout timer. */ 4942 ifp->if_timer = 0; 4943 4944 /* Clear the tx hardware queue full flag. */ 4945 if (sc->used_tx_bd < sc->max_tx_bd) { 4946 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4947 aprint_debug_dev(sc->bnx_dev, 4948 "Open TX chain! %d/%d (used/total)\n", 4949 sc->used_tx_bd, sc->max_tx_bd)); 4950 ifp->if_flags &= ~IFF_OACTIVE; 4951 } 4952 4953 sc->tx_cons = sw_tx_cons; 4954 } 4955 4956 /****************************************************************************/ 4957 /* Disables interrupt generation. */ 4958 /* */ 4959 /* Returns: */ 4960 /* Nothing. */ 4961 /****************************************************************************/ 4962 void 4963 bnx_disable_intr(struct bnx_softc *sc) 4964 { 4965 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4966 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4967 } 4968 4969 /****************************************************************************/ 4970 /* Enables interrupt generation. */ 4971 /* */ 4972 /* Returns: */ 4973 /* Nothing. */ 4974 /****************************************************************************/ 4975 void 4976 bnx_enable_intr(struct bnx_softc *sc) 4977 { 4978 uint32_t val; 4979 4980 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4981 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4982 4983 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4984 sc->last_status_idx); 4985 4986 val = REG_RD(sc, BNX_HC_COMMAND); 4987 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4988 } 4989 4990 /****************************************************************************/ 4991 /* Handles controller initialization. */ 4992 /* */ 4993 /****************************************************************************/ 4994 int 4995 bnx_init(struct ifnet *ifp) 4996 { 4997 struct bnx_softc *sc = ifp->if_softc; 4998 uint32_t ether_mtu; 4999 int s, error = 0; 5000 5001 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 5002 5003 s = splnet(); 5004 5005 bnx_stop(ifp, 0); 5006 5007 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 5008 aprint_error_dev(sc->bnx_dev, 5009 "Controller reset failed!\n"); 5010 goto bnx_init_exit; 5011 } 5012 5013 if ((error = bnx_chipinit(sc)) != 0) { 5014 aprint_error_dev(sc->bnx_dev, 5015 "Controller initialization failed!\n"); 5016 goto bnx_init_exit; 5017 } 5018 5019 if ((error = bnx_blockinit(sc)) != 0) { 5020 aprint_error_dev(sc->bnx_dev, 5021 "Block initialization failed!\n"); 5022 goto bnx_init_exit; 5023 } 5024 5025 /* Calculate and program the Ethernet MRU size. */ 5026 if (ifp->if_mtu <= ETHERMTU) { 5027 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 5028 sc->mbuf_alloc_size = MCLBYTES; 5029 } else { 5030 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 5031 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 5032 } 5033 5034 5035 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 5036 5037 /* 5038 * Program the MRU and enable Jumbo frame 5039 * support. 5040 */ 5041 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 5042 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 5043 5044 /* Calculate the RX Ethernet frame size for rx_bd's. */ 5045 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 5046 5047 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 5048 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 5049 sc->mbuf_alloc_size, sc->max_frame_size); 5050 5051 /* Program appropriate promiscuous/multicast filtering. */ 5052 bnx_iff(sc); 5053 5054 /* Init RX buffer descriptor chain. */ 5055 bnx_init_rx_chain(sc); 5056 5057 /* Init TX buffer descriptor chain. */ 5058 bnx_init_tx_chain(sc); 5059 5060 /* Enable host interrupts. */ 5061 bnx_enable_intr(sc); 5062 5063 bnx_ifmedia_upd(ifp); 5064 5065 SET(ifp->if_flags, IFF_RUNNING); 5066 CLR(ifp->if_flags, IFF_OACTIVE); 5067 5068 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5069 5070 bnx_init_exit: 5071 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5072 5073 splx(s); 5074 5075 return error; 5076 } 5077 5078 void 5079 bnx_mgmt_init(struct bnx_softc *sc) 5080 { 5081 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5082 uint32_t val; 5083 5084 /* Check if the driver is still running and bail out if it is. */ 5085 if (ifp->if_flags & IFF_RUNNING) 5086 goto bnx_mgmt_init_exit; 5087 5088 /* Initialize the on-boards CPUs */ 5089 bnx_init_cpus(sc); 5090 5091 val = (BCM_PAGE_BITS - 8) << 24; 5092 REG_WR(sc, BNX_RV2P_CONFIG, val); 5093 5094 /* Enable all critical blocks in the MAC. */ 5095 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5096 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5097 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5098 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5099 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5100 DELAY(20); 5101 5102 bnx_ifmedia_upd(ifp); 5103 5104 bnx_mgmt_init_exit: 5105 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5106 } 5107 5108 /****************************************************************************/ 5109 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5110 /* memory visible to the controller. */ 5111 /* */ 5112 /* Returns: */ 5113 /* 0 for success, positive value for failure. */ 5114 /****************************************************************************/ 5115 int 5116 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5117 { 5118 struct bnx_pkt *pkt; 5119 bus_dmamap_t map; 5120 struct tx_bd *txbd = NULL; 5121 uint16_t vlan_tag = 0, flags = 0; 5122 uint16_t chain_prod, prod; 5123 #ifdef BNX_DEBUG 5124 uint16_t debug_prod; 5125 #endif 5126 uint32_t addr, prod_bseq; 5127 int i, error; 5128 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 5129 bool remap = true; 5130 5131 mutex_enter(&sc->tx_pkt_mtx); 5132 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5133 if (pkt == NULL) { 5134 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5135 mutex_exit(&sc->tx_pkt_mtx); 5136 return ENETDOWN; 5137 } 5138 5139 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5140 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5141 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 5142 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5143 } 5144 5145 mutex_exit(&sc->tx_pkt_mtx); 5146 return ENOMEM; 5147 } 5148 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5149 mutex_exit(&sc->tx_pkt_mtx); 5150 5151 /* Transfer any checksum offload flags to the bd. */ 5152 if (m->m_pkthdr.csum_flags) { 5153 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5154 flags |= TX_BD_FLAGS_IP_CKSUM; 5155 if (m->m_pkthdr.csum_flags & 5156 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5157 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5158 } 5159 5160 /* Transfer any VLAN tags to the bd. */ 5161 if (vlan_has_tag(m)) { 5162 flags |= TX_BD_FLAGS_VLAN_TAG; 5163 vlan_tag = vlan_get_tag(m); 5164 } 5165 5166 /* Map the mbuf into DMAable memory. */ 5167 prod = sc->tx_prod; 5168 chain_prod = TX_CHAIN_IDX(prod); 5169 map = pkt->pkt_dmamap; 5170 5171 /* Map the mbuf into our DMA address space. */ 5172 retry: 5173 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5174 if (__predict_false(error)) { 5175 if (error == EFBIG) { 5176 if (remap == true) { 5177 struct mbuf *newm; 5178 5179 remap = false; 5180 newm = m_defrag(m, M_NOWAIT); 5181 if (newm != NULL) { 5182 m = newm; 5183 goto retry; 5184 } 5185 } 5186 } 5187 sc->tx_dma_map_failures++; 5188 goto maperr; 5189 } 5190 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5191 BUS_DMASYNC_PREWRITE); 5192 /* Make sure there's room in the chain */ 5193 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5194 goto nospace; 5195 5196 /* prod points to an empty tx_bd at this point. */ 5197 prod_bseq = sc->tx_prod_bseq; 5198 #ifdef BNX_DEBUG 5199 debug_prod = chain_prod; 5200 #endif 5201 DBPRINT(sc, BNX_INFO_SEND, 5202 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5203 "prod_bseq = 0x%08X\n", 5204 __func__, prod, chain_prod, prod_bseq); 5205 5206 /* 5207 * Cycle through each mbuf segment that makes up 5208 * the outgoing frame, gathering the mapping info 5209 * for that segment and creating a tx_bd for the 5210 * mbuf. 5211 */ 5212 for (i = 0; i < map->dm_nsegs ; i++) { 5213 chain_prod = TX_CHAIN_IDX(prod); 5214 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5215 5216 addr = (uint32_t)map->dm_segs[i].ds_addr; 5217 txbd->tx_bd_haddr_lo = addr; 5218 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5219 txbd->tx_bd_haddr_hi = addr; 5220 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5221 txbd->tx_bd_vlan_tag = vlan_tag; 5222 txbd->tx_bd_flags = flags; 5223 prod_bseq += map->dm_segs[i].ds_len; 5224 if (i == 0) 5225 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5226 prod = NEXT_TX_BD(prod); 5227 } 5228 5229 /* Set the END flag on the last TX buffer descriptor. */ 5230 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5231 5232 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5233 5234 DBPRINT(sc, BNX_INFO_SEND, 5235 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5236 "prod_bseq = 0x%08X\n", 5237 __func__, prod, chain_prod, prod_bseq); 5238 5239 pkt->pkt_mbuf = m; 5240 pkt->pkt_end_desc = chain_prod; 5241 5242 mutex_enter(&sc->tx_pkt_mtx); 5243 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5244 mutex_exit(&sc->tx_pkt_mtx); 5245 5246 sc->used_tx_bd += map->dm_nsegs; 5247 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5248 __FILE__, __LINE__, sc->used_tx_bd); 5249 5250 /* Update some debug statistics counters */ 5251 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5252 sc->tx_hi_watermark = sc->used_tx_bd); 5253 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5254 DBRUNIF(1, sc->tx_mbuf_alloc++); 5255 5256 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5257 map->dm_nsegs)); 5258 5259 /* prod points to the next free tx_bd at this point. */ 5260 sc->tx_prod = prod; 5261 sc->tx_prod_bseq = prod_bseq; 5262 5263 return 0; 5264 5265 5266 nospace: 5267 bus_dmamap_unload(sc->bnx_dmatag, map); 5268 maperr: 5269 mutex_enter(&sc->tx_pkt_mtx); 5270 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5271 mutex_exit(&sc->tx_pkt_mtx); 5272 5273 return ENOMEM; 5274 } 5275 5276 /****************************************************************************/ 5277 /* Main transmit routine. */ 5278 /* */ 5279 /* Returns: */ 5280 /* Nothing. */ 5281 /****************************************************************************/ 5282 void 5283 bnx_start(struct ifnet *ifp) 5284 { 5285 struct bnx_softc *sc = ifp->if_softc; 5286 struct mbuf *m_head = NULL; 5287 int count = 0; 5288 #ifdef BNX_DEBUG 5289 uint16_t tx_chain_prod; 5290 #endif 5291 5292 /* If there's no link or the transmit queue is empty then just exit. */ 5293 if (!sc->bnx_link 5294 ||(ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) { 5295 DBPRINT(sc, BNX_INFO_SEND, 5296 "%s(): output active or device not running.\n", __func__); 5297 goto bnx_start_exit; 5298 } 5299 5300 /* prod points to the next free tx_bd. */ 5301 #ifdef BNX_DEBUG 5302 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5303 #endif 5304 5305 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5306 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5307 "used_tx %d max_tx %d\n", 5308 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5309 sc->used_tx_bd, sc->max_tx_bd); 5310 5311 /* 5312 * Keep adding entries while there is space in the ring. 5313 */ 5314 while (sc->used_tx_bd < sc->max_tx_bd) { 5315 /* Check for any frames to send. */ 5316 IFQ_POLL(&ifp->if_snd, m_head); 5317 if (m_head == NULL) 5318 break; 5319 5320 /* 5321 * Pack the data into the transmit ring. If we 5322 * don't have room, set the OACTIVE flag to wait 5323 * for the NIC to drain the chain. 5324 */ 5325 if (bnx_tx_encap(sc, m_head)) { 5326 ifp->if_flags |= IFF_OACTIVE; 5327 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5328 "business! Total tx_bd used = %d\n", 5329 sc->used_tx_bd); 5330 break; 5331 } 5332 5333 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5334 count++; 5335 5336 /* Send a copy of the frame to any BPF listeners. */ 5337 bpf_mtap(ifp, m_head, BPF_D_OUT); 5338 } 5339 5340 if (count == 0) { 5341 /* no packets were dequeued */ 5342 DBPRINT(sc, BNX_VERBOSE_SEND, 5343 "%s(): No packets were dequeued\n", __func__); 5344 goto bnx_start_exit; 5345 } 5346 5347 /* Update the driver's counters. */ 5348 #ifdef BNX_DEBUG 5349 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5350 #endif 5351 5352 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5353 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5354 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5355 5356 /* Start the transmit. */ 5357 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5358 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5359 5360 /* Set the tx timeout. */ 5361 ifp->if_timer = BNX_TX_TIMEOUT; 5362 5363 bnx_start_exit: 5364 return; 5365 } 5366 5367 /****************************************************************************/ 5368 /* Handles any IOCTL calls from the operating system. */ 5369 /* */ 5370 /* Returns: */ 5371 /* 0 for success, positive value for failure. */ 5372 /****************************************************************************/ 5373 int 5374 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5375 { 5376 struct bnx_softc *sc = ifp->if_softc; 5377 struct ifreq *ifr = (struct ifreq *) data; 5378 struct mii_data *mii = &sc->bnx_mii; 5379 int s, error = 0; 5380 5381 s = splnet(); 5382 5383 switch (command) { 5384 case SIOCSIFFLAGS: 5385 if ((error = ifioctl_common(ifp, command, data)) != 0) 5386 break; 5387 /* XXX set an ifflags callback and let ether_ioctl 5388 * handle all of this. 5389 */ 5390 if (ISSET(ifp->if_flags, IFF_UP)) { 5391 if (ifp->if_flags & IFF_RUNNING) 5392 error = ENETRESET; 5393 else 5394 bnx_init(ifp); 5395 } else if (ifp->if_flags & IFF_RUNNING) 5396 bnx_stop(ifp, 1); 5397 break; 5398 5399 case SIOCSIFMEDIA: 5400 /* Flow control requires full-duplex mode. */ 5401 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5402 (ifr->ifr_media & IFM_FDX) == 0) 5403 ifr->ifr_media &= ~IFM_ETH_FMASK; 5404 5405 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5406 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5407 /* We can do both TXPAUSE and RXPAUSE. */ 5408 ifr->ifr_media |= 5409 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5410 } 5411 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5412 } 5413 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5414 sc->bnx_phy_flags); 5415 5416 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5417 break; 5418 5419 default: 5420 error = ether_ioctl(ifp, command, data); 5421 } 5422 5423 if (error == ENETRESET) { 5424 if (ifp->if_flags & IFF_RUNNING) 5425 bnx_iff(sc); 5426 error = 0; 5427 } 5428 5429 splx(s); 5430 return error; 5431 } 5432 5433 /****************************************************************************/ 5434 /* Transmit timeout handler. */ 5435 /* */ 5436 /* Returns: */ 5437 /* Nothing. */ 5438 /****************************************************************************/ 5439 void 5440 bnx_watchdog(struct ifnet *ifp) 5441 { 5442 struct bnx_softc *sc = ifp->if_softc; 5443 5444 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5445 bnx_dump_status_block(sc)); 5446 /* 5447 * If we are in this routine because of pause frames, then 5448 * don't reset the hardware. 5449 */ 5450 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5451 return; 5452 5453 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5454 5455 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5456 5457 bnx_init(ifp); 5458 5459 ifp->if_oerrors++; 5460 } 5461 5462 /* 5463 * Interrupt handler. 5464 */ 5465 /****************************************************************************/ 5466 /* Main interrupt entry point. Verifies that the controller generated the */ 5467 /* interrupt and then calls a separate routine for handle the various */ 5468 /* interrupt causes (PHY, TX, RX). */ 5469 /* */ 5470 /* Returns: */ 5471 /* 0 for success, positive value for failure. */ 5472 /****************************************************************************/ 5473 int 5474 bnx_intr(void *xsc) 5475 { 5476 struct bnx_softc *sc = xsc; 5477 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5478 uint32_t status_attn_bits; 5479 uint16_t status_idx; 5480 const struct status_block *sblk; 5481 int rv = 0; 5482 5483 if (!device_is_active(sc->bnx_dev) || 5484 (ifp->if_flags & IFF_RUNNING) == 0) 5485 return 0; 5486 5487 DBRUNIF(1, sc->interrupts_generated++); 5488 5489 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5490 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5491 5492 sblk = sc->status_block; 5493 /* 5494 * If the hardware status block index 5495 * matches the last value read by the 5496 * driver and we haven't asserted our 5497 * interrupt then there's nothing to do. 5498 */ 5499 status_idx = sblk->status_idx; 5500 if ((status_idx != sc->last_status_idx) || 5501 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5502 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5503 rv = 1; 5504 5505 /* Ack the interrupt */ 5506 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5507 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5508 5509 status_attn_bits = sblk->status_attn_bits; 5510 5511 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5512 aprint_debug("Simulating unexpected status attention bit set."); 5513 status_attn_bits = status_attn_bits | 5514 STATUS_ATTN_BITS_PARITY_ERROR); 5515 5516 /* Was it a link change interrupt? */ 5517 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5518 (sblk->status_attn_bits_ack & 5519 STATUS_ATTN_BITS_LINK_STATE)) 5520 bnx_phy_intr(sc); 5521 5522 /* If any other attention is asserted then the chip is toast. */ 5523 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5524 (sblk->status_attn_bits_ack & 5525 ~STATUS_ATTN_BITS_LINK_STATE))) { 5526 DBRUN(sc->unexpected_attentions++); 5527 5528 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5529 sblk->status_attn_bits); 5530 5531 DBRUNIF((bnx_debug_unexpected_attention == 0), 5532 bnx_breakpoint(sc)); 5533 5534 bnx_init(ifp); 5535 goto out; 5536 } 5537 5538 /* Check for any completed RX frames. */ 5539 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5540 bnx_rx_intr(sc); 5541 5542 /* Check for any completed TX frames. */ 5543 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5544 bnx_tx_intr(sc); 5545 5546 /* 5547 * Save the status block index value for use during the 5548 * next interrupt. 5549 */ 5550 sc->last_status_idx = status_idx; 5551 5552 /* Start moving packets again */ 5553 if (ifp->if_flags & IFF_RUNNING) 5554 if_schedule_deferred_start(ifp); 5555 } 5556 5557 out: 5558 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5559 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5560 5561 return rv; 5562 } 5563 5564 /****************************************************************************/ 5565 /* Programs the various packet receive modes (broadcast and multicast). */ 5566 /* */ 5567 /* Returns: */ 5568 /* Nothing. */ 5569 /****************************************************************************/ 5570 void 5571 bnx_iff(struct bnx_softc *sc) 5572 { 5573 struct ethercom *ec = &sc->bnx_ec; 5574 struct ifnet *ifp = &ec->ec_if; 5575 struct ether_multi *enm; 5576 struct ether_multistep step; 5577 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5578 uint32_t rx_mode, sort_mode; 5579 int h, i; 5580 5581 /* Initialize receive mode default settings. */ 5582 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5583 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5584 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5585 ifp->if_flags &= ~IFF_ALLMULTI; 5586 5587 /* 5588 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5589 * be enbled. 5590 */ 5591 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5592 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5593 5594 /* 5595 * Check for promiscuous, all multicast, or selected 5596 * multicast address filtering. 5597 */ 5598 if (ifp->if_flags & IFF_PROMISC) { 5599 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5600 5601 ifp->if_flags |= IFF_ALLMULTI; 5602 /* Enable promiscuous mode. */ 5603 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5604 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5605 } else if (ifp->if_flags & IFF_ALLMULTI) { 5606 allmulti: 5607 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5608 5609 ifp->if_flags |= IFF_ALLMULTI; 5610 /* Enable all multicast addresses. */ 5611 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5612 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5613 0xffffffff); 5614 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5615 } else { 5616 /* Accept one or more multicast(s). */ 5617 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5618 5619 ETHER_LOCK(ec); 5620 ETHER_FIRST_MULTI(step, ec, enm); 5621 while (enm != NULL) { 5622 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5623 ETHER_ADDR_LEN)) { 5624 ETHER_UNLOCK(ec); 5625 goto allmulti; 5626 } 5627 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5628 0xFF; 5629 hashes[(h & 0xE0) >> 5] |= __BIT(h & 0x1F); 5630 ETHER_NEXT_MULTI(step, enm); 5631 } 5632 ETHER_UNLOCK(ec); 5633 5634 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5635 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5636 hashes[i]); 5637 5638 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5639 } 5640 5641 /* Only make changes if the recive mode has actually changed. */ 5642 if (rx_mode != sc->rx_mode) { 5643 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5644 rx_mode); 5645 5646 sc->rx_mode = rx_mode; 5647 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5648 } 5649 5650 /* Disable and clear the exisitng sort before enabling a new sort. */ 5651 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5652 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5653 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5654 } 5655 5656 /****************************************************************************/ 5657 /* Called periodically to updates statistics from the controllers */ 5658 /* statistics block. */ 5659 /* */ 5660 /* Returns: */ 5661 /* Nothing. */ 5662 /****************************************************************************/ 5663 void 5664 bnx_stats_update(struct bnx_softc *sc) 5665 { 5666 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5667 struct statistics_block *stats; 5668 5669 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5670 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5671 BUS_DMASYNC_POSTREAD); 5672 5673 stats = (struct statistics_block *)sc->stats_block; 5674 5675 /* 5676 * Update the interface statistics from the 5677 * hardware statistics. 5678 */ 5679 ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; 5680 5681 ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + 5682 (u_long)stats->stat_EtherStatsOverrsizePkts + 5683 (u_long)stats->stat_IfInMBUFDiscards + 5684 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5685 (u_long)stats->stat_Dot3StatsFCSErrors; 5686 5687 ifp->if_oerrors = (u_long) 5688 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5689 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5690 (u_long)stats->stat_Dot3StatsLateCollisions; 5691 5692 /* 5693 * Certain controllers don't report 5694 * carrier sense errors correctly. 5695 * See errata E11_5708CA0_1165. 5696 */ 5697 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5698 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) 5699 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5700 5701 /* 5702 * Update the sysctl statistics from the 5703 * hardware statistics. 5704 */ 5705 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5706 (uint64_t) stats->stat_IfHCInOctets_lo; 5707 5708 sc->stat_IfHCInBadOctets = 5709 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5710 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5711 5712 sc->stat_IfHCOutOctets = 5713 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5714 (uint64_t) stats->stat_IfHCOutOctets_lo; 5715 5716 sc->stat_IfHCOutBadOctets = 5717 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5718 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5719 5720 sc->stat_IfHCInUcastPkts = 5721 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5722 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5723 5724 sc->stat_IfHCInMulticastPkts = 5725 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5726 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5727 5728 sc->stat_IfHCInBroadcastPkts = 5729 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5730 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5731 5732 sc->stat_IfHCOutUcastPkts = 5733 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5734 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5735 5736 sc->stat_IfHCOutMulticastPkts = 5737 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5738 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5739 5740 sc->stat_IfHCOutBroadcastPkts = 5741 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5742 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5743 5744 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5745 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5746 5747 sc->stat_Dot3StatsCarrierSenseErrors = 5748 stats->stat_Dot3StatsCarrierSenseErrors; 5749 5750 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5751 5752 sc->stat_Dot3StatsAlignmentErrors = 5753 stats->stat_Dot3StatsAlignmentErrors; 5754 5755 sc->stat_Dot3StatsSingleCollisionFrames = 5756 stats->stat_Dot3StatsSingleCollisionFrames; 5757 5758 sc->stat_Dot3StatsMultipleCollisionFrames = 5759 stats->stat_Dot3StatsMultipleCollisionFrames; 5760 5761 sc->stat_Dot3StatsDeferredTransmissions = 5762 stats->stat_Dot3StatsDeferredTransmissions; 5763 5764 sc->stat_Dot3StatsExcessiveCollisions = 5765 stats->stat_Dot3StatsExcessiveCollisions; 5766 5767 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5768 5769 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5770 5771 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5772 5773 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5774 5775 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5776 5777 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5778 5779 sc->stat_EtherStatsPktsRx64Octets = 5780 stats->stat_EtherStatsPktsRx64Octets; 5781 5782 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5783 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5784 5785 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5786 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5787 5788 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5789 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5790 5791 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5792 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5793 5794 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5795 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5796 5797 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5798 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5799 5800 sc->stat_EtherStatsPktsTx64Octets = 5801 stats->stat_EtherStatsPktsTx64Octets; 5802 5803 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5804 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5805 5806 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5807 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5808 5809 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5810 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5811 5812 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5813 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5814 5815 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5816 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5817 5818 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5819 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5820 5821 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5822 5823 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5824 5825 sc->stat_OutXonSent = stats->stat_OutXonSent; 5826 5827 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5828 5829 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5830 5831 sc->stat_MacControlFramesReceived = 5832 stats->stat_MacControlFramesReceived; 5833 5834 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5835 5836 sc->stat_IfInFramesL2FilterDiscards = 5837 stats->stat_IfInFramesL2FilterDiscards; 5838 5839 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5840 5841 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5842 5843 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5844 5845 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5846 5847 sc->stat_CatchupInRuleCheckerDiscards = 5848 stats->stat_CatchupInRuleCheckerDiscards; 5849 5850 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5851 5852 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5853 5854 sc->stat_CatchupInRuleCheckerP4Hit = 5855 stats->stat_CatchupInRuleCheckerP4Hit; 5856 5857 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5858 } 5859 5860 void 5861 bnx_tick(void *xsc) 5862 { 5863 struct bnx_softc *sc = xsc; 5864 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5865 struct mii_data *mii; 5866 uint32_t msg; 5867 uint16_t prod, chain_prod; 5868 uint32_t prod_bseq; 5869 int s = splnet(); 5870 5871 /* Tell the firmware that the driver is still running. */ 5872 #ifdef BNX_DEBUG 5873 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5874 #else 5875 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5876 #endif 5877 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5878 5879 /* Update the statistics from the hardware statistics block. */ 5880 bnx_stats_update(sc); 5881 5882 /* Schedule the next tick. */ 5883 if (!sc->bnx_detaching) 5884 callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); 5885 5886 if (sc->bnx_link) 5887 goto bnx_tick_exit; 5888 5889 mii = &sc->bnx_mii; 5890 mii_tick(mii); 5891 5892 /* Check if the link has come up. */ 5893 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5894 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5895 sc->bnx_link++; 5896 /* Now that link is up, handle any outstanding TX traffic. */ 5897 if_schedule_deferred_start(ifp); 5898 } 5899 5900 bnx_tick_exit: 5901 /* try to get more RX buffers, just in case */ 5902 prod = sc->rx_prod; 5903 prod_bseq = sc->rx_prod_bseq; 5904 chain_prod = RX_CHAIN_IDX(prod); 5905 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5906 sc->rx_prod = prod; 5907 sc->rx_prod_bseq = prod_bseq; 5908 5909 splx(s); 5910 return; 5911 } 5912 5913 /****************************************************************************/ 5914 /* BNX Debug Routines */ 5915 /****************************************************************************/ 5916 #ifdef BNX_DEBUG 5917 5918 /****************************************************************************/ 5919 /* Prints out information about an mbuf. */ 5920 /* */ 5921 /* Returns: */ 5922 /* Nothing. */ 5923 /****************************************************************************/ 5924 void 5925 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5926 { 5927 struct mbuf *mp = m; 5928 5929 if (m == NULL) { 5930 /* Index out of range. */ 5931 aprint_error("mbuf ptr is null!\n"); 5932 return; 5933 } 5934 5935 while (mp) { 5936 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5937 mp, mp->m_len); 5938 5939 if (mp->m_flags & M_EXT) 5940 aprint_debug("M_EXT "); 5941 if (mp->m_flags & M_PKTHDR) 5942 aprint_debug("M_PKTHDR "); 5943 aprint_debug("\n"); 5944 5945 if (mp->m_flags & M_EXT) 5946 aprint_debug("- m_ext: vaddr = %p, " 5947 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5948 5949 mp = mp->m_next; 5950 } 5951 } 5952 5953 /****************************************************************************/ 5954 /* Prints out the mbufs in the TX mbuf chain. */ 5955 /* */ 5956 /* Returns: */ 5957 /* Nothing. */ 5958 /****************************************************************************/ 5959 void 5960 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5961 { 5962 #if 0 5963 struct mbuf *m; 5964 int i; 5965 5966 aprint_debug_dev(sc->bnx_dev, 5967 "----------------------------" 5968 " tx mbuf data " 5969 "----------------------------\n"); 5970 5971 for (i = 0; i < count; i++) { 5972 m = sc->tx_mbuf_ptr[chain_prod]; 5973 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5974 bnx_dump_mbuf(sc, m); 5975 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5976 } 5977 5978 aprint_debug_dev(sc->bnx_dev, 5979 "--------------------------------------------" 5980 "----------------------------\n"); 5981 #endif 5982 } 5983 5984 /* 5985 * This routine prints the RX mbuf chain. 5986 */ 5987 void 5988 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5989 { 5990 struct mbuf *m; 5991 int i; 5992 5993 aprint_debug_dev(sc->bnx_dev, 5994 "----------------------------" 5995 " rx mbuf data " 5996 "----------------------------\n"); 5997 5998 for (i = 0; i < count; i++) { 5999 m = sc->rx_mbuf_ptr[chain_prod]; 6000 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6001 bnx_dump_mbuf(sc, m); 6002 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6003 } 6004 6005 6006 aprint_debug_dev(sc->bnx_dev, 6007 "--------------------------------------------" 6008 "----------------------------\n"); 6009 } 6010 6011 void 6012 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 6013 { 6014 if (idx > MAX_TX_BD) 6015 /* Index out of range. */ 6016 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6017 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6018 /* TX Chain page pointer. */ 6019 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 6020 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 6021 txbd->tx_bd_haddr_lo); 6022 else 6023 /* Normal tx_bd entry. */ 6024 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6025 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 6026 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6027 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6028 txbd->tx_bd_flags); 6029 } 6030 6031 void 6032 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 6033 { 6034 if (idx > MAX_RX_BD) 6035 /* Index out of range. */ 6036 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6037 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6038 /* TX Chain page pointer. */ 6039 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 6040 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 6041 rxbd->rx_bd_haddr_lo); 6042 else 6043 /* Normal tx_bd entry. */ 6044 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6045 "0x%08X, flags = 0x%08X\n", idx, 6046 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6047 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6048 } 6049 6050 void 6051 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6052 { 6053 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6054 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6055 "tcp_udp_xsum = 0x%04X\n", idx, 6056 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6057 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6058 l2fhdr->l2_fhdr_tcp_udp_xsum); 6059 } 6060 6061 /* 6062 * This routine prints the TX chain. 6063 */ 6064 void 6065 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 6066 { 6067 struct tx_bd *txbd; 6068 int i; 6069 6070 /* First some info about the tx_bd chain structure. */ 6071 aprint_debug_dev(sc->bnx_dev, 6072 "----------------------------" 6073 " tx_bd chain " 6074 "----------------------------\n"); 6075 6076 BNX_PRINTF(sc, 6077 "page size = 0x%08X, tx chain pages = 0x%08X\n", 6078 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6079 6080 BNX_PRINTF(sc, 6081 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6082 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6083 6084 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6085 6086 aprint_error_dev(sc->bnx_dev, "" 6087 "-----------------------------" 6088 " tx_bd data " 6089 "-----------------------------\n"); 6090 6091 /* Now print out the tx_bd's themselves. */ 6092 for (i = 0; i < count; i++) { 6093 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6094 bnx_dump_txbd(sc, tx_prod, txbd); 6095 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6096 } 6097 6098 aprint_debug_dev(sc->bnx_dev, 6099 "-----------------------------" 6100 "--------------" 6101 "-----------------------------\n"); 6102 } 6103 6104 /* 6105 * This routine prints the RX chain. 6106 */ 6107 void 6108 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6109 { 6110 struct rx_bd *rxbd; 6111 int i; 6112 6113 /* First some info about the tx_bd chain structure. */ 6114 aprint_debug_dev(sc->bnx_dev, 6115 "----------------------------" 6116 " rx_bd chain " 6117 "----------------------------\n"); 6118 6119 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6120 6121 BNX_PRINTF(sc, 6122 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6123 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6124 6125 BNX_PRINTF(sc, 6126 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6127 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6128 6129 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6130 6131 aprint_error_dev(sc->bnx_dev, 6132 "----------------------------" 6133 " rx_bd data " 6134 "----------------------------\n"); 6135 6136 /* Now print out the rx_bd's themselves. */ 6137 for (i = 0; i < count; i++) { 6138 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6139 bnx_dump_rxbd(sc, rx_prod, rxbd); 6140 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6141 } 6142 6143 aprint_debug_dev(sc->bnx_dev, 6144 "----------------------------" 6145 "--------------" 6146 "----------------------------\n"); 6147 } 6148 6149 /* 6150 * This routine prints the status block. 6151 */ 6152 void 6153 bnx_dump_status_block(struct bnx_softc *sc) 6154 { 6155 struct status_block *sblk; 6156 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6157 BUS_DMASYNC_POSTREAD); 6158 6159 sblk = sc->status_block; 6160 6161 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6162 "Status Block -----------------------------\n"); 6163 6164 BNX_PRINTF(sc, 6165 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6166 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6167 sblk->status_idx); 6168 6169 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6170 sblk->status_rx_quick_consumer_index0, 6171 sblk->status_tx_quick_consumer_index0); 6172 6173 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6174 6175 /* Theses indices are not used for normal L2 drivers. */ 6176 if (sblk->status_rx_quick_consumer_index1 || 6177 sblk->status_tx_quick_consumer_index1) 6178 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6179 sblk->status_rx_quick_consumer_index1, 6180 sblk->status_tx_quick_consumer_index1); 6181 6182 if (sblk->status_rx_quick_consumer_index2 || 6183 sblk->status_tx_quick_consumer_index2) 6184 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6185 sblk->status_rx_quick_consumer_index2, 6186 sblk->status_tx_quick_consumer_index2); 6187 6188 if (sblk->status_rx_quick_consumer_index3 || 6189 sblk->status_tx_quick_consumer_index3) 6190 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6191 sblk->status_rx_quick_consumer_index3, 6192 sblk->status_tx_quick_consumer_index3); 6193 6194 if (sblk->status_rx_quick_consumer_index4 || 6195 sblk->status_rx_quick_consumer_index5) 6196 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6197 sblk->status_rx_quick_consumer_index4, 6198 sblk->status_rx_quick_consumer_index5); 6199 6200 if (sblk->status_rx_quick_consumer_index6 || 6201 sblk->status_rx_quick_consumer_index7) 6202 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6203 sblk->status_rx_quick_consumer_index6, 6204 sblk->status_rx_quick_consumer_index7); 6205 6206 if (sblk->status_rx_quick_consumer_index8 || 6207 sblk->status_rx_quick_consumer_index9) 6208 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6209 sblk->status_rx_quick_consumer_index8, 6210 sblk->status_rx_quick_consumer_index9); 6211 6212 if (sblk->status_rx_quick_consumer_index10 || 6213 sblk->status_rx_quick_consumer_index11) 6214 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6215 sblk->status_rx_quick_consumer_index10, 6216 sblk->status_rx_quick_consumer_index11); 6217 6218 if (sblk->status_rx_quick_consumer_index12 || 6219 sblk->status_rx_quick_consumer_index13) 6220 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6221 sblk->status_rx_quick_consumer_index12, 6222 sblk->status_rx_quick_consumer_index13); 6223 6224 if (sblk->status_rx_quick_consumer_index14 || 6225 sblk->status_rx_quick_consumer_index15) 6226 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6227 sblk->status_rx_quick_consumer_index14, 6228 sblk->status_rx_quick_consumer_index15); 6229 6230 if (sblk->status_completion_producer_index || 6231 sblk->status_cmd_consumer_index) 6232 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6233 sblk->status_completion_producer_index, 6234 sblk->status_cmd_consumer_index); 6235 6236 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6237 "-----------------------------\n"); 6238 } 6239 6240 /* 6241 * This routine prints the statistics block. 6242 */ 6243 void 6244 bnx_dump_stats_block(struct bnx_softc *sc) 6245 { 6246 struct statistics_block *sblk; 6247 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6248 BUS_DMASYNC_POSTREAD); 6249 6250 sblk = sc->stats_block; 6251 6252 aprint_debug_dev(sc->bnx_dev, "" 6253 "-----------------------------" 6254 " Stats Block " 6255 "-----------------------------\n"); 6256 6257 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6258 "IfHcInBadOctets = 0x%08X:%08X\n", 6259 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6260 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6261 6262 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6263 "IfHcOutBadOctets = 0x%08X:%08X\n", 6264 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6265 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6266 6267 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6268 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6269 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6270 sblk->stat_IfHCInMulticastPkts_hi, 6271 sblk->stat_IfHCInMulticastPkts_lo); 6272 6273 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6274 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6275 sblk->stat_IfHCInBroadcastPkts_hi, 6276 sblk->stat_IfHCInBroadcastPkts_lo, 6277 sblk->stat_IfHCOutUcastPkts_hi, 6278 sblk->stat_IfHCOutUcastPkts_lo); 6279 6280 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6281 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6282 sblk->stat_IfHCOutMulticastPkts_hi, 6283 sblk->stat_IfHCOutMulticastPkts_lo, 6284 sblk->stat_IfHCOutBroadcastPkts_hi, 6285 sblk->stat_IfHCOutBroadcastPkts_lo); 6286 6287 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6288 BNX_PRINTF(sc, "0x%08X : " 6289 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6290 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6291 6292 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6293 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6294 sblk->stat_Dot3StatsCarrierSenseErrors); 6295 6296 if (sblk->stat_Dot3StatsFCSErrors) 6297 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6298 sblk->stat_Dot3StatsFCSErrors); 6299 6300 if (sblk->stat_Dot3StatsAlignmentErrors) 6301 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6302 sblk->stat_Dot3StatsAlignmentErrors); 6303 6304 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6305 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6306 sblk->stat_Dot3StatsSingleCollisionFrames); 6307 6308 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6309 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6310 sblk->stat_Dot3StatsMultipleCollisionFrames); 6311 6312 if (sblk->stat_Dot3StatsDeferredTransmissions) 6313 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6314 sblk->stat_Dot3StatsDeferredTransmissions); 6315 6316 if (sblk->stat_Dot3StatsExcessiveCollisions) 6317 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6318 sblk->stat_Dot3StatsExcessiveCollisions); 6319 6320 if (sblk->stat_Dot3StatsLateCollisions) 6321 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6322 sblk->stat_Dot3StatsLateCollisions); 6323 6324 if (sblk->stat_EtherStatsCollisions) 6325 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6326 sblk->stat_EtherStatsCollisions); 6327 6328 if (sblk->stat_EtherStatsFragments) 6329 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6330 sblk->stat_EtherStatsFragments); 6331 6332 if (sblk->stat_EtherStatsJabbers) 6333 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6334 sblk->stat_EtherStatsJabbers); 6335 6336 if (sblk->stat_EtherStatsUndersizePkts) 6337 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6338 sblk->stat_EtherStatsUndersizePkts); 6339 6340 if (sblk->stat_EtherStatsOverrsizePkts) 6341 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6342 sblk->stat_EtherStatsOverrsizePkts); 6343 6344 if (sblk->stat_EtherStatsPktsRx64Octets) 6345 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6346 sblk->stat_EtherStatsPktsRx64Octets); 6347 6348 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6349 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6350 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6351 6352 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6353 BNX_PRINTF(sc, "0x%08X : " 6354 "EtherStatsPktsRx128Octetsto255Octets\n", 6355 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6356 6357 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6358 BNX_PRINTF(sc, "0x%08X : " 6359 "EtherStatsPktsRx256Octetsto511Octets\n", 6360 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6361 6362 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6363 BNX_PRINTF(sc, "0x%08X : " 6364 "EtherStatsPktsRx512Octetsto1023Octets\n", 6365 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6366 6367 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6368 BNX_PRINTF(sc, "0x%08X : " 6369 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6370 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6371 6372 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6373 BNX_PRINTF(sc, "0x%08X : " 6374 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6375 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6376 6377 if (sblk->stat_EtherStatsPktsTx64Octets) 6378 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6379 sblk->stat_EtherStatsPktsTx64Octets); 6380 6381 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6382 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6383 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6384 6385 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6386 BNX_PRINTF(sc, "0x%08X : " 6387 "EtherStatsPktsTx128Octetsto255Octets\n", 6388 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6389 6390 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6391 BNX_PRINTF(sc, "0x%08X : " 6392 "EtherStatsPktsTx256Octetsto511Octets\n", 6393 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6394 6395 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6396 BNX_PRINTF(sc, "0x%08X : " 6397 "EtherStatsPktsTx512Octetsto1023Octets\n", 6398 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6399 6400 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6401 BNX_PRINTF(sc, "0x%08X : " 6402 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6403 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6404 6405 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6406 BNX_PRINTF(sc, "0x%08X : " 6407 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6408 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6409 6410 if (sblk->stat_XonPauseFramesReceived) 6411 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6412 sblk->stat_XonPauseFramesReceived); 6413 6414 if (sblk->stat_XoffPauseFramesReceived) 6415 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6416 sblk->stat_XoffPauseFramesReceived); 6417 6418 if (sblk->stat_OutXonSent) 6419 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6420 sblk->stat_OutXonSent); 6421 6422 if (sblk->stat_OutXoffSent) 6423 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6424 sblk->stat_OutXoffSent); 6425 6426 if (sblk->stat_FlowControlDone) 6427 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6428 sblk->stat_FlowControlDone); 6429 6430 if (sblk->stat_MacControlFramesReceived) 6431 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6432 sblk->stat_MacControlFramesReceived); 6433 6434 if (sblk->stat_XoffStateEntered) 6435 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6436 sblk->stat_XoffStateEntered); 6437 6438 if (sblk->stat_IfInFramesL2FilterDiscards) 6439 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6440 sblk->stat_IfInFramesL2FilterDiscards); 6441 6442 if (sblk->stat_IfInRuleCheckerDiscards) 6443 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6444 sblk->stat_IfInRuleCheckerDiscards); 6445 6446 if (sblk->stat_IfInFTQDiscards) 6447 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6448 sblk->stat_IfInFTQDiscards); 6449 6450 if (sblk->stat_IfInMBUFDiscards) 6451 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6452 sblk->stat_IfInMBUFDiscards); 6453 6454 if (sblk->stat_IfInRuleCheckerP4Hit) 6455 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6456 sblk->stat_IfInRuleCheckerP4Hit); 6457 6458 if (sblk->stat_CatchupInRuleCheckerDiscards) 6459 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6460 sblk->stat_CatchupInRuleCheckerDiscards); 6461 6462 if (sblk->stat_CatchupInFTQDiscards) 6463 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6464 sblk->stat_CatchupInFTQDiscards); 6465 6466 if (sblk->stat_CatchupInMBUFDiscards) 6467 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6468 sblk->stat_CatchupInMBUFDiscards); 6469 6470 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6471 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6472 sblk->stat_CatchupInRuleCheckerP4Hit); 6473 6474 aprint_debug_dev(sc->bnx_dev, 6475 "-----------------------------" 6476 "--------------" 6477 "-----------------------------\n"); 6478 } 6479 6480 void 6481 bnx_dump_driver_state(struct bnx_softc *sc) 6482 { 6483 aprint_debug_dev(sc->bnx_dev, 6484 "-----------------------------" 6485 " Driver State " 6486 "-----------------------------\n"); 6487 6488 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6489 "address\n", sc); 6490 6491 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6492 sc->status_block); 6493 6494 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6495 "address\n", sc->stats_block); 6496 6497 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6498 "address\n", sc->tx_bd_chain); 6499 6500 #if 0 6501 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6502 sc->rx_bd_chain); 6503 6504 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6505 sc->tx_mbuf_ptr); 6506 #endif 6507 6508 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6509 sc->rx_mbuf_ptr); 6510 6511 BNX_PRINTF(sc, 6512 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6513 sc->interrupts_generated); 6514 6515 BNX_PRINTF(sc, 6516 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6517 sc->rx_interrupts); 6518 6519 BNX_PRINTF(sc, 6520 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6521 sc->tx_interrupts); 6522 6523 BNX_PRINTF(sc, 6524 " 0x%08X - (sc->last_status_idx) status block index\n", 6525 sc->last_status_idx); 6526 6527 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6528 sc->tx_prod); 6529 6530 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6531 sc->tx_cons); 6532 6533 BNX_PRINTF(sc, 6534 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6535 sc->tx_prod_bseq); 6536 BNX_PRINTF(sc, 6537 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6538 sc->tx_mbuf_alloc); 6539 6540 BNX_PRINTF(sc, 6541 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6542 sc->used_tx_bd); 6543 6544 BNX_PRINTF(sc, 6545 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6546 sc->tx_hi_watermark, sc->max_tx_bd); 6547 6548 6549 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6550 sc->rx_prod); 6551 6552 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6553 sc->rx_cons); 6554 6555 BNX_PRINTF(sc, 6556 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6557 sc->rx_prod_bseq); 6558 6559 BNX_PRINTF(sc, 6560 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6561 sc->rx_mbuf_alloc); 6562 6563 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6564 sc->free_rx_bd); 6565 6566 BNX_PRINTF(sc, 6567 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6568 sc->rx_low_watermark, sc->max_rx_bd); 6569 6570 BNX_PRINTF(sc, 6571 " 0x%08X - (sc->mbuf_alloc_failed) " 6572 "mbuf alloc failures\n", 6573 sc->mbuf_alloc_failed); 6574 6575 BNX_PRINTF(sc, 6576 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6577 "simulated mbuf alloc failures\n", 6578 sc->mbuf_sim_alloc_failed); 6579 6580 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6581 "-----------------------------\n"); 6582 } 6583 6584 void 6585 bnx_dump_hw_state(struct bnx_softc *sc) 6586 { 6587 uint32_t val1; 6588 int i; 6589 6590 aprint_debug_dev(sc->bnx_dev, 6591 "----------------------------" 6592 " Hardware State " 6593 "----------------------------\n"); 6594 6595 val1 = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 6596 BNX_PRINTF(sc, "0x%08X : bootcode version\n", val1); 6597 6598 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6599 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6600 val1, BNX_MISC_ENABLE_STATUS_BITS); 6601 6602 val1 = REG_RD(sc, BNX_DMA_STATUS); 6603 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6604 6605 val1 = REG_RD(sc, BNX_CTX_STATUS); 6606 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6607 6608 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6609 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6610 BNX_EMAC_STATUS); 6611 6612 val1 = REG_RD(sc, BNX_RPM_STATUS); 6613 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6614 6615 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6616 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6617 BNX_TBDR_STATUS); 6618 6619 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6620 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6621 BNX_TDMA_STATUS); 6622 6623 val1 = REG_RD(sc, BNX_HC_STATUS); 6624 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6625 6626 aprint_debug_dev(sc->bnx_dev, 6627 "----------------------------" 6628 "----------------" 6629 "----------------------------\n"); 6630 6631 aprint_debug_dev(sc->bnx_dev, 6632 "----------------------------" 6633 " Register Dump " 6634 "----------------------------\n"); 6635 6636 for (i = 0x400; i < 0x8000; i += 0x10) 6637 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6638 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6639 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6640 6641 aprint_debug_dev(sc->bnx_dev, 6642 "----------------------------" 6643 "----------------" 6644 "----------------------------\n"); 6645 } 6646 6647 void 6648 bnx_breakpoint(struct bnx_softc *sc) 6649 { 6650 /* Unreachable code to shut the compiler up about unused functions. */ 6651 if (0) { 6652 bnx_dump_txbd(sc, 0, NULL); 6653 bnx_dump_rxbd(sc, 0, NULL); 6654 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6655 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6656 bnx_dump_l2fhdr(sc, 0, NULL); 6657 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6658 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6659 bnx_dump_status_block(sc); 6660 bnx_dump_stats_block(sc); 6661 bnx_dump_driver_state(sc); 6662 bnx_dump_hw_state(sc); 6663 } 6664 6665 bnx_dump_driver_state(sc); 6666 /* Print the important status block fields. */ 6667 bnx_dump_status_block(sc); 6668 6669 #if 0 6670 /* Call the debugger. */ 6671 breakpoint(); 6672 #endif 6673 6674 return; 6675 } 6676 #endif 6677
Indexes created Wed Sep 24 14:09:57 GMT 2025