if_bnx.c revision 1.96
1 /* $NetBSD: if_bnx.c,v 1.96 2020/07/12 19:05:32 jdolecek Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.96 2020/07/12 19:05:32 jdolecek Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 device_t dev = sc->bnx_dev; 466 int i = 0; 467 468 aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 469 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 470 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 471 ? "Serdes " : "", sc->bnx_chipid); 472 473 /* Bus info. */ 474 if (sc->bnx_flags & BNX_PCIE_FLAG) { 475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); 476 switch (sc->link_speed) { 477 case 1: aprint_normal("2.5GT/s\n"); break; 478 case 2: aprint_normal("5GT/s\n"); break; 479 default: aprint_normal("Unknown link speed\n"); 480 } 481 } else { 482 aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n", 483 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 484 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 485 sc->bus_speed_mhz); 486 } 487 488 /* Firmware version and device features. */ 489 aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (", 490 sc->bnx_bc_ver, RX_PAGES, TX_PAGES); 491 492 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) { 493 if (i > 0) aprint_normal("|"); 494 aprint_normal("2.5G"); i++; 495 } 496 497 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 498 if (i > 0) aprint_normal("|"); 499 aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver); 500 } else { 501 aprint_normal(")\n"); 502 } 503 504 aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 505 sc->bnx_rx_quick_cons_trip_int, 506 sc->bnx_rx_quick_cons_trip, 507 sc->bnx_rx_ticks_int, 508 sc->bnx_rx_ticks, 509 sc->bnx_tx_quick_cons_trip_int, 510 sc->bnx_tx_quick_cons_trip, 511 sc->bnx_tx_ticks_int, 512 sc->bnx_tx_ticks); 513 } 514 515 516 /****************************************************************************/ 517 /* PCI Capabilities Probe Function. */ 518 /* */ 519 /* Walks the PCI capabiites list for the device to find what features are */ 520 /* supported. */ 521 /* */ 522 /* Returns: */ 523 /* None. */ 524 /****************************************************************************/ 525 static void 526 bnx_probe_pci_caps(struct bnx_softc *sc) 527 { 528 struct pci_attach_args *pa = &(sc->bnx_pa); 529 pcireg_t reg; 530 531 /* Check if PCI-X capability is enabled. */ 532 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 533 NULL) != 0) { 534 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 535 } 536 537 /* Check if PCIe capability is enabled. */ 538 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 539 NULL) != 0) { 540 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 541 reg + PCIE_LCSR); 542 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 543 "0x%08X\n", link_status); 544 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 546 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 547 sc->bnx_flags |= BNX_PCIE_FLAG; 548 } 549 550 /* Check if MSI capability is enabled. */ 551 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 552 NULL) != 0) 553 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 554 555 /* Check if MSI-X capability is enabled. */ 556 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 557 NULL) != 0) 558 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 559 } 560 561 562 /****************************************************************************/ 563 /* Device attach function. */ 564 /* */ 565 /* Allocates device resources, performs secondary chip identification, */ 566 /* resets and initializes the hardware, and initializes driver instance */ 567 /* variables. */ 568 /* */ 569 /* Returns: */ 570 /* 0 on success, positive value on failure. */ 571 /****************************************************************************/ 572 void 573 bnx_attach(device_t parent, device_t self, void *aux) 574 { 575 const struct bnx_product *bp; 576 struct bnx_softc *sc = device_private(self); 577 prop_dictionary_t dict; 578 struct pci_attach_args *pa = aux; 579 pci_chipset_tag_t pc = pa->pa_pc; 580 const char *intrstr = NULL; 581 uint32_t command; 582 struct ifnet *ifp; 583 struct mii_data * const mii = &sc->bnx_mii; 584 uint32_t val; 585 int mii_flags = MIIF_FORCEANEG; 586 pcireg_t memtype; 587 char intrbuf[PCI_INTRSTR_LEN]; 588 int i, j; 589 590 if (bnx_tx_pool == NULL) { 591 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_WAITOK); 592 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 593 0, 0, 0, "bnxpkts", NULL, IPL_NET); 594 } 595 596 bp = bnx_lookup(pa); 597 if (bp == NULL) 598 panic("unknown device"); 599 600 sc->bnx_dev = self; 601 602 aprint_naive("\n"); 603 aprint_normal(": %s\n", bp->bp_name); 604 605 sc->bnx_pa = *pa; 606 607 /* 608 * Map control/status registers. 609 */ 610 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 611 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 612 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 613 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 614 615 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 616 aprint_error_dev(sc->bnx_dev, 617 "failed to enable memory mapping!\n"); 618 return; 619 } 620 621 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 622 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 623 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 624 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 625 return; 626 } 627 628 if (pci_intr_alloc(pa, &sc->bnx_ih, NULL, 0)) { 629 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 630 goto bnx_attach_fail; 631 } 632 intrstr = pci_intr_string(pc, sc->bnx_ih[0], intrbuf, sizeof(intrbuf)); 633 634 /* 635 * Configure byte swap and enable indirect register access. 636 * Rely on CPU to do target byte swapping on big endian systems. 637 * Access to registers outside of PCI configurtion space are not 638 * valid until this is done. 639 */ 640 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 641 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 642 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 643 644 /* Save ASIC revision info. */ 645 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 646 647 /* 648 * Find the base address for shared memory access. 649 * Newer versions of bootcode use a signature and offset 650 * while older versions use a fixed address. 651 */ 652 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 653 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 654 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 655 (sc->bnx_pa.pa_function << 2)); 656 else 657 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 658 659 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 660 661 /* Set initial device and PHY flags */ 662 sc->bnx_flags = 0; 663 sc->bnx_phy_flags = 0; 664 665 /* Fetch the bootcode revision. */ 666 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 667 for (i = 0, j = 0; i < 3; i++) { 668 uint8_t num; 669 int k, skip0; 670 671 num = (uint8_t)(val >> (24 - (i * 8))); 672 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 673 if (num >= k || !skip0 || k == 1) { 674 sc->bnx_bc_ver[j++] = (num / k) + '0'; 675 skip0 = 0; 676 } 677 } 678 if (i != 2) 679 sc->bnx_bc_ver[j++] = '.'; 680 } 681 682 /* Check if any management firmware is enabled. */ 683 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 684 if (val & BNX_PORT_FEATURE_ASF_ENABLED) { 685 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 686 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 687 688 /* Allow time for firmware to enter the running state. */ 689 for (i = 0; i < 30; i++) { 690 val = REG_RD_IND(sc, sc->bnx_shmem_base + 691 BNX_BC_STATE_CONDITION); 692 if (val & BNX_CONDITION_MFW_RUN_MASK) 693 break; 694 DELAY(10000); 695 } 696 697 /* Check if management firmware is running. */ 698 val = REG_RD_IND(sc, sc->bnx_shmem_base + 699 BNX_BC_STATE_CONDITION); 700 val &= BNX_CONDITION_MFW_RUN_MASK; 701 if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) && 702 (val != BNX_CONDITION_MFW_RUN_NONE)) { 703 uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base + 704 BNX_MFW_VER_PTR); 705 706 /* Read the management firmware version string. */ 707 for (j = 0; j < 3; j++) { 708 val = bnx_reg_rd_ind(sc, addr + j * 4); 709 val = bswap32(val); 710 memcpy(&sc->bnx_mfw_ver[i], &val, 4); 711 i += 4; 712 } 713 } else { 714 /* May cause firmware synchronization timeouts. */ 715 BNX_PRINTF(sc, "%s(%d): Management firmware enabled " 716 "but not running!\n", __FILE__, __LINE__); 717 strcpy(sc->bnx_mfw_ver, "NOT RUNNING!"); 718 719 /* ToDo: Any action the driver should take? */ 720 } 721 } 722 723 bnx_probe_pci_caps(sc); 724 725 /* Get PCI bus information (speed and type). */ 726 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 727 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 728 uint32_t clkreg; 729 730 sc->bnx_flags |= BNX_PCIX_FLAG; 731 732 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 733 734 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 735 switch (clkreg) { 736 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 737 sc->bus_speed_mhz = 133; 738 break; 739 740 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 741 sc->bus_speed_mhz = 100; 742 break; 743 744 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 745 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 746 sc->bus_speed_mhz = 66; 747 break; 748 749 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 750 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 751 sc->bus_speed_mhz = 50; 752 break; 753 754 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 755 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 756 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 757 sc->bus_speed_mhz = 33; 758 break; 759 } 760 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 761 sc->bus_speed_mhz = 66; 762 else 763 sc->bus_speed_mhz = 33; 764 765 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 766 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 767 768 /* Reset the controller. */ 769 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 770 goto bnx_attach_fail; 771 772 /* Initialize the controller. */ 773 if (bnx_chipinit(sc)) { 774 aprint_error_dev(sc->bnx_dev, 775 "Controller initialization failed!\n"); 776 goto bnx_attach_fail; 777 } 778 779 /* Perform NVRAM test. */ 780 if (bnx_nvram_test(sc)) { 781 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 782 goto bnx_attach_fail; 783 } 784 785 /* Fetch the permanent Ethernet MAC address. */ 786 bnx_get_mac_addr(sc); 787 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 788 ether_sprintf(sc->eaddr)); 789 790 /* 791 * Trip points control how many BDs 792 * should be ready before generating an 793 * interrupt while ticks control how long 794 * a BD can sit in the chain before 795 * generating an interrupt. Set the default 796 * values for the RX and TX rings. 797 */ 798 799 #ifdef BNX_DEBUG 800 /* Force more frequent interrupts. */ 801 sc->bnx_tx_quick_cons_trip_int = 1; 802 sc->bnx_tx_quick_cons_trip = 1; 803 sc->bnx_tx_ticks_int = 0; 804 sc->bnx_tx_ticks = 0; 805 806 sc->bnx_rx_quick_cons_trip_int = 1; 807 sc->bnx_rx_quick_cons_trip = 1; 808 sc->bnx_rx_ticks_int = 0; 809 sc->bnx_rx_ticks = 0; 810 #else 811 sc->bnx_tx_quick_cons_trip_int = 20; 812 sc->bnx_tx_quick_cons_trip = 20; 813 sc->bnx_tx_ticks_int = 80; 814 sc->bnx_tx_ticks = 80; 815 816 sc->bnx_rx_quick_cons_trip_int = 6; 817 sc->bnx_rx_quick_cons_trip = 6; 818 sc->bnx_rx_ticks_int = 18; 819 sc->bnx_rx_ticks = 18; 820 #endif 821 822 /* Update statistics once every second. */ 823 sc->bnx_stats_ticks = 1000000 & 0xffff00; 824 825 /* Find the media type for the adapter. */ 826 bnx_get_media(sc); 827 828 /* 829 * Store config data needed by the PHY driver for 830 * backplane applications 831 */ 832 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 833 BNX_SHARED_HW_CFG_CONFIG); 834 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 835 BNX_PORT_HW_CFG_CONFIG); 836 837 /* Allocate DMA memory resources. */ 838 sc->bnx_dmatag = pa->pa_dmat; 839 if (bnx_dma_alloc(sc)) { 840 aprint_error_dev(sc->bnx_dev, 841 "DMA resource allocation failed!\n"); 842 goto bnx_attach_fail; 843 } 844 845 /* Initialize the ifnet interface. */ 846 ifp = &sc->bnx_ec.ec_if; 847 ifp->if_softc = sc; 848 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 849 ifp->if_ioctl = bnx_ioctl; 850 ifp->if_stop = bnx_stop; 851 ifp->if_start = bnx_start; 852 ifp->if_init = bnx_init; 853 ifp->if_watchdog = bnx_watchdog; 854 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 855 IFQ_SET_READY(&ifp->if_snd); 856 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 857 858 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 859 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 860 sc->bnx_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 861 862 ifp->if_capabilities |= 863 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 864 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 865 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 866 867 /* create workqueue to handle packet allocations */ 868 if (workqueue_create(&sc->bnx_wq, device_xname(self), 869 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 870 aprint_error_dev(self, "failed to create workqueue\n"); 871 goto bnx_attach_fail; 872 } 873 874 mii->mii_ifp = ifp; 875 mii->mii_readreg = bnx_miibus_read_reg; 876 mii->mii_writereg = bnx_miibus_write_reg; 877 mii->mii_statchg = bnx_miibus_statchg; 878 879 /* Handle any special PHY initialization for SerDes PHYs. */ 880 bnx_init_media(sc); 881 882 sc->bnx_ec.ec_mii = mii; 883 ifmedia_init(&mii->mii_media, 0, bnx_ifmedia_upd, bnx_ifmedia_sts); 884 885 /* set phyflags and chipid before mii_attach() */ 886 dict = device_properties(self); 887 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 888 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 889 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 890 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 891 892 /* Print some useful adapter info */ 893 bnx_print_adapter_info(sc); 894 895 mii_flags |= MIIF_DOPAUSE; 896 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 897 mii_flags |= MIIF_HAVEFIBER; 898 mii_attach(self, mii, 0xffffffff, 899 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 900 901 if (LIST_EMPTY(&mii->mii_phys)) { 902 aprint_error_dev(self, "no PHY found!\n"); 903 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 904 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 905 } else 906 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 907 908 /* Attach to the Ethernet interface list. */ 909 if_attach(ifp); 910 if_deferred_start_init(ifp, NULL); 911 ether_ifattach(ifp, sc->eaddr); 912 913 callout_init(&sc->bnx_timeout, 0); 914 callout_setfunc(&sc->bnx_timeout, bnx_tick, sc); 915 916 /* Hookup IRQ last. */ 917 sc->bnx_intrhand = pci_intr_establish_xname(pc, sc->bnx_ih[0], IPL_NET, 918 bnx_intr, sc, device_xname(self)); 919 if (sc->bnx_intrhand == NULL) { 920 aprint_error_dev(self, "couldn't establish interrupt"); 921 if (intrstr != NULL) 922 aprint_error(" at %s", intrstr); 923 aprint_error("\n"); 924 goto bnx_attach_fail; 925 } 926 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 927 928 if (pmf_device_register(self, NULL, NULL)) 929 pmf_class_network_register(self, ifp); 930 else 931 aprint_error_dev(self, "couldn't establish power handler\n"); 932 933 /* Print some important debugging info. */ 934 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 935 936 /* Get the firmware running so ASF still works. */ 937 bnx_mgmt_init(sc); 938 939 goto bnx_attach_exit; 940 941 bnx_attach_fail: 942 bnx_release_resources(sc); 943 944 bnx_attach_exit: 945 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 946 } 947 948 /****************************************************************************/ 949 /* Device detach function. */ 950 /* */ 951 /* Stops the controller, resets the controller, and releases resources. */ 952 /* */ 953 /* Returns: */ 954 /* 0 on success, positive value on failure. */ 955 /****************************************************************************/ 956 int 957 bnx_detach(device_t dev, int flags) 958 { 959 int s; 960 struct bnx_softc *sc; 961 struct ifnet *ifp; 962 963 sc = device_private(dev); 964 ifp = &sc->bnx_ec.ec_if; 965 966 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 967 968 /* Stop and reset the controller. */ 969 s = splnet(); 970 bnx_stop(ifp, 1); 971 splx(s); 972 973 pmf_device_deregister(dev); 974 callout_destroy(&sc->bnx_timeout); 975 ether_ifdetach(ifp); 976 workqueue_destroy(sc->bnx_wq); 977 978 if_detach(ifp); 979 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 980 981 /* Delete all remaining media. */ 982 ifmedia_fini(&sc->bnx_mii.mii_media); 983 984 /* Release all remaining resources. */ 985 bnx_release_resources(sc); 986 987 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 988 989 return 0; 990 } 991 992 /****************************************************************************/ 993 /* Indirect register read. */ 994 /* */ 995 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 996 /* configuration space. Using this mechanism avoids issues with posted */ 997 /* reads but is much slower than memory-mapped I/O. */ 998 /* */ 999 /* Returns: */ 1000 /* The value of the register. */ 1001 /****************************************************************************/ 1002 uint32_t 1003 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 1004 { 1005 struct pci_attach_args *pa = &(sc->bnx_pa); 1006 1007 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1008 offset); 1009 #ifdef BNX_DEBUG 1010 { 1011 uint32_t val; 1012 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 1013 BNX_PCICFG_REG_WINDOW); 1014 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 1015 "val = 0x%08X\n", __func__, offset, val); 1016 return val; 1017 } 1018 #else 1019 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 1020 #endif 1021 } 1022 1023 /****************************************************************************/ 1024 /* Indirect register write. */ 1025 /* */ 1026 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1027 /* configuration space. Using this mechanism avoids issues with posted */ 1028 /* writes but is muchh slower than memory-mapped I/O. */ 1029 /* */ 1030 /* Returns: */ 1031 /* Nothing. */ 1032 /****************************************************************************/ 1033 void 1034 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 1035 { 1036 struct pci_attach_args *pa = &(sc->bnx_pa); 1037 1038 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 1039 __func__, offset, val); 1040 1041 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1042 offset); 1043 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 1044 } 1045 1046 /****************************************************************************/ 1047 /* Context memory write. */ 1048 /* */ 1049 /* The NetXtreme II controller uses context memory to track connection */ 1050 /* information for L2 and higher network protocols. */ 1051 /* */ 1052 /* Returns: */ 1053 /* Nothing. */ 1054 /****************************************************************************/ 1055 void 1056 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 1057 uint32_t ctx_val) 1058 { 1059 uint32_t idx, offset = ctx_offset + cid_addr; 1060 uint32_t val, retry_cnt = 5; 1061 1062 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1063 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1064 REG_WR(sc, BNX_CTX_CTX_CTRL, 1065 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 1066 1067 for (idx = 0; idx < retry_cnt; idx++) { 1068 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1069 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1070 break; 1071 DELAY(5); 1072 } 1073 1074 #if 0 1075 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1076 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1077 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1078 __FILE__, __LINE__, cid_addr, ctx_offset); 1079 #endif 1080 1081 } else { 1082 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1083 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1084 } 1085 } 1086 1087 /****************************************************************************/ 1088 /* PHY register read. */ 1089 /* */ 1090 /* Implements register reads on the MII bus. */ 1091 /* */ 1092 /* Returns: */ 1093 /* The value of the register. */ 1094 /****************************************************************************/ 1095 int 1096 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1097 { 1098 struct bnx_softc *sc = device_private(dev); 1099 uint32_t data; 1100 int i, rv = 0; 1101 1102 /* 1103 * The BCM5709S PHY is an IEEE Clause 45 PHY 1104 * with special mappings to work with IEEE 1105 * Clause 22 register accesses. 1106 */ 1107 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1108 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1109 reg += 0x10; 1110 } 1111 1112 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1113 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1114 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1115 1116 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1117 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1118 1119 DELAY(40); 1120 } 1121 1122 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1123 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1124 BNX_EMAC_MDIO_COMM_START_BUSY; 1125 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1126 1127 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1128 DELAY(10); 1129 1130 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1131 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1132 DELAY(5); 1133 1134 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1135 data &= BNX_EMAC_MDIO_COMM_DATA; 1136 1137 break; 1138 } 1139 } 1140 1141 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1142 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1143 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1144 rv = ETIMEDOUT; 1145 } else { 1146 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1147 *val = data & 0xffff; 1148 1149 DBPRINT(sc, BNX_EXCESSIVE, 1150 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1151 phy, (uint16_t) reg & 0xffff, *val); 1152 } 1153 1154 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1155 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1156 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1157 1158 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1159 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1160 1161 DELAY(40); 1162 } 1163 1164 return rv; 1165 } 1166 1167 /****************************************************************************/ 1168 /* PHY register write. */ 1169 /* */ 1170 /* Implements register writes on the MII bus. */ 1171 /* */ 1172 /* Returns: */ 1173 /* The value of the register. */ 1174 /****************************************************************************/ 1175 int 1176 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1177 { 1178 struct bnx_softc *sc = device_private(dev); 1179 uint32_t val1; 1180 int i, rv = 0; 1181 1182 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1183 "val = 0x%04hX\n", __func__, 1184 phy, (uint16_t) reg & 0xffff, val); 1185 1186 /* 1187 * The BCM5709S PHY is an IEEE Clause 45 PHY 1188 * with special mappings to work with IEEE 1189 * Clause 22 register accesses. 1190 */ 1191 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1192 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1193 reg += 0x10; 1194 } 1195 1196 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1197 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1198 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1199 1200 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1201 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1202 1203 DELAY(40); 1204 } 1205 1206 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1207 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1208 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1209 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1210 1211 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1212 DELAY(10); 1213 1214 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1215 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1216 DELAY(5); 1217 break; 1218 } 1219 } 1220 1221 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1222 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1223 __LINE__); 1224 rv = ETIMEDOUT; 1225 } 1226 1227 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1228 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1229 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1230 1231 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1232 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1233 1234 DELAY(40); 1235 } 1236 1237 return rv; 1238 } 1239 1240 /****************************************************************************/ 1241 /* MII bus status change. */ 1242 /* */ 1243 /* Called by the MII bus driver when the PHY establishes link to set the */ 1244 /* MAC interface registers. */ 1245 /* */ 1246 /* Returns: */ 1247 /* Nothing. */ 1248 /****************************************************************************/ 1249 void 1250 bnx_miibus_statchg(struct ifnet *ifp) 1251 { 1252 struct bnx_softc *sc = ifp->if_softc; 1253 struct mii_data *mii = &sc->bnx_mii; 1254 uint32_t rx_mode = sc->rx_mode; 1255 int val; 1256 1257 val = REG_RD(sc, BNX_EMAC_MODE); 1258 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1259 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1260 BNX_EMAC_MODE_25G); 1261 1262 /* 1263 * Get flow control negotiation result. 1264 */ 1265 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1266 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1267 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1268 mii->mii_media_active &= ~IFM_ETH_FMASK; 1269 } 1270 1271 /* Set MII or GMII interface based on the speed 1272 * negotiated by the PHY. 1273 */ 1274 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1275 case IFM_10_T: 1276 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1277 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1278 val |= BNX_EMAC_MODE_PORT_MII_10; 1279 break; 1280 } 1281 /* FALLTHROUGH */ 1282 case IFM_100_TX: 1283 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1284 val |= BNX_EMAC_MODE_PORT_MII; 1285 break; 1286 case IFM_2500_SX: 1287 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1288 val |= BNX_EMAC_MODE_25G; 1289 /* FALLTHROUGH */ 1290 case IFM_1000_T: 1291 case IFM_1000_SX: 1292 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1293 val |= BNX_EMAC_MODE_PORT_GMII; 1294 break; 1295 default: 1296 val |= BNX_EMAC_MODE_PORT_GMII; 1297 break; 1298 } 1299 1300 /* Set half or full duplex based on the duplicity 1301 * negotiated by the PHY. 1302 */ 1303 if ((mii->mii_media_active & IFM_HDX) != 0) { 1304 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1305 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1306 } else 1307 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1308 1309 REG_WR(sc, BNX_EMAC_MODE, val); 1310 1311 /* 1312 * 802.3x flow control 1313 */ 1314 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1315 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1316 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1317 } else { 1318 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1319 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1320 } 1321 1322 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1323 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1324 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1325 } else { 1326 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1327 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1328 } 1329 1330 /* Only make changes if the receive mode has actually changed. */ 1331 if (rx_mode != sc->rx_mode) { 1332 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1333 rx_mode); 1334 1335 sc->rx_mode = rx_mode; 1336 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1337 1338 bnx_init_rx_context(sc); 1339 } 1340 } 1341 1342 /****************************************************************************/ 1343 /* Acquire NVRAM lock. */ 1344 /* */ 1345 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1346 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1347 /* for use by the driver. */ 1348 /* */ 1349 /* Returns: */ 1350 /* 0 on success, positive value on failure. */ 1351 /****************************************************************************/ 1352 int 1353 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1354 { 1355 uint32_t val; 1356 int j; 1357 1358 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1359 1360 /* Request access to the flash interface. */ 1361 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1362 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1363 val = REG_RD(sc, BNX_NVM_SW_ARB); 1364 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1365 break; 1366 1367 DELAY(5); 1368 } 1369 1370 if (j >= NVRAM_TIMEOUT_COUNT) { 1371 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1372 return EBUSY; 1373 } 1374 1375 return 0; 1376 } 1377 1378 /****************************************************************************/ 1379 /* Release NVRAM lock. */ 1380 /* */ 1381 /* When the caller is finished accessing NVRAM the lock must be released. */ 1382 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1383 /* for use by the driver. */ 1384 /* */ 1385 /* Returns: */ 1386 /* 0 on success, positive value on failure. */ 1387 /****************************************************************************/ 1388 int 1389 bnx_release_nvram_lock(struct bnx_softc *sc) 1390 { 1391 int j; 1392 uint32_t val; 1393 1394 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1395 1396 /* Relinquish nvram interface. */ 1397 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1398 1399 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1400 val = REG_RD(sc, BNX_NVM_SW_ARB); 1401 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1402 break; 1403 1404 DELAY(5); 1405 } 1406 1407 if (j >= NVRAM_TIMEOUT_COUNT) { 1408 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1409 return EBUSY; 1410 } 1411 1412 return 0; 1413 } 1414 1415 #ifdef BNX_NVRAM_WRITE_SUPPORT 1416 /****************************************************************************/ 1417 /* Enable NVRAM write access. */ 1418 /* */ 1419 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1420 /* */ 1421 /* Returns: */ 1422 /* 0 on success, positive value on failure. */ 1423 /****************************************************************************/ 1424 int 1425 bnx_enable_nvram_write(struct bnx_softc *sc) 1426 { 1427 uint32_t val; 1428 1429 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1430 1431 val = REG_RD(sc, BNX_MISC_CFG); 1432 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1433 1434 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1435 int j; 1436 1437 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1438 REG_WR(sc, BNX_NVM_COMMAND, 1439 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1440 1441 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1442 DELAY(5); 1443 1444 val = REG_RD(sc, BNX_NVM_COMMAND); 1445 if (val & BNX_NVM_COMMAND_DONE) 1446 break; 1447 } 1448 1449 if (j >= NVRAM_TIMEOUT_COUNT) { 1450 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1451 return EBUSY; 1452 } 1453 } 1454 1455 return 0; 1456 } 1457 1458 /****************************************************************************/ 1459 /* Disable NVRAM write access. */ 1460 /* */ 1461 /* When the caller is finished writing to NVRAM write access must be */ 1462 /* disabled. */ 1463 /* */ 1464 /* Returns: */ 1465 /* Nothing. */ 1466 /****************************************************************************/ 1467 void 1468 bnx_disable_nvram_write(struct bnx_softc *sc) 1469 { 1470 uint32_t val; 1471 1472 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1473 1474 val = REG_RD(sc, BNX_MISC_CFG); 1475 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1476 } 1477 #endif 1478 1479 /****************************************************************************/ 1480 /* Enable NVRAM access. */ 1481 /* */ 1482 /* Before accessing NVRAM for read or write operations the caller must */ 1483 /* enabled NVRAM access. */ 1484 /* */ 1485 /* Returns: */ 1486 /* Nothing. */ 1487 /****************************************************************************/ 1488 void 1489 bnx_enable_nvram_access(struct bnx_softc *sc) 1490 { 1491 uint32_t val; 1492 1493 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1494 1495 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1496 /* Enable both bits, even on read. */ 1497 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1498 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1499 } 1500 1501 /****************************************************************************/ 1502 /* Disable NVRAM access. */ 1503 /* */ 1504 /* When the caller is finished accessing NVRAM access must be disabled. */ 1505 /* */ 1506 /* Returns: */ 1507 /* Nothing. */ 1508 /****************************************************************************/ 1509 void 1510 bnx_disable_nvram_access(struct bnx_softc *sc) 1511 { 1512 uint32_t val; 1513 1514 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1515 1516 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1517 1518 /* Disable both bits, even after read. */ 1519 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1520 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1521 } 1522 1523 #ifdef BNX_NVRAM_WRITE_SUPPORT 1524 /****************************************************************************/ 1525 /* Erase NVRAM page before writing. */ 1526 /* */ 1527 /* Non-buffered flash parts require that a page be erased before it is */ 1528 /* written. */ 1529 /* */ 1530 /* Returns: */ 1531 /* 0 on success, positive value on failure. */ 1532 /****************************************************************************/ 1533 int 1534 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1535 { 1536 uint32_t cmd; 1537 int j; 1538 1539 /* Buffered flash doesn't require an erase. */ 1540 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1541 return 0; 1542 1543 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1544 1545 /* Build an erase command. */ 1546 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1547 BNX_NVM_COMMAND_DOIT; 1548 1549 /* 1550 * Clear the DONE bit separately, set the NVRAM address to erase, 1551 * and issue the erase command. 1552 */ 1553 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1554 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1555 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1556 1557 /* Wait for completion. */ 1558 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1559 uint32_t val; 1560 1561 DELAY(5); 1562 1563 val = REG_RD(sc, BNX_NVM_COMMAND); 1564 if (val & BNX_NVM_COMMAND_DONE) 1565 break; 1566 } 1567 1568 if (j >= NVRAM_TIMEOUT_COUNT) { 1569 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1570 return EBUSY; 1571 } 1572 1573 return 0; 1574 } 1575 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1576 1577 /****************************************************************************/ 1578 /* Read a dword (32 bits) from NVRAM. */ 1579 /* */ 1580 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1581 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1582 /* */ 1583 /* Returns: */ 1584 /* 0 on success and the 32 bit value read, positive value on failure. */ 1585 /****************************************************************************/ 1586 int 1587 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1588 uint8_t *ret_val, uint32_t cmd_flags) 1589 { 1590 uint32_t cmd; 1591 int i, rc = 0; 1592 1593 /* Build the command word. */ 1594 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1595 1596 /* Calculate the offset for buffered flash if translation is used. */ 1597 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1598 offset = ((offset / sc->bnx_flash_info->page_size) << 1599 sc->bnx_flash_info->page_bits) + 1600 (offset % sc->bnx_flash_info->page_size); 1601 } 1602 1603 /* 1604 * Clear the DONE bit separately, set the address to read, 1605 * and issue the read. 1606 */ 1607 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1608 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1609 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1610 1611 /* Wait for completion. */ 1612 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1613 uint32_t val; 1614 1615 DELAY(5); 1616 1617 val = REG_RD(sc, BNX_NVM_COMMAND); 1618 if (val & BNX_NVM_COMMAND_DONE) { 1619 val = REG_RD(sc, BNX_NVM_READ); 1620 1621 val = be32toh(val); 1622 memcpy(ret_val, &val, 4); 1623 break; 1624 } 1625 } 1626 1627 /* Check for errors. */ 1628 if (i >= NVRAM_TIMEOUT_COUNT) { 1629 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1630 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1631 rc = EBUSY; 1632 } 1633 1634 return rc; 1635 } 1636 1637 #ifdef BNX_NVRAM_WRITE_SUPPORT 1638 /****************************************************************************/ 1639 /* Write a dword (32 bits) to NVRAM. */ 1640 /* */ 1641 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1642 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1643 /* enabled NVRAM write access. */ 1644 /* */ 1645 /* Returns: */ 1646 /* 0 on success, positive value on failure. */ 1647 /****************************************************************************/ 1648 int 1649 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1650 uint32_t cmd_flags) 1651 { 1652 uint32_t cmd, val32; 1653 int j; 1654 1655 /* Build the command word. */ 1656 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1657 1658 /* Calculate the offset for buffered flash if translation is used. */ 1659 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1660 offset = ((offset / sc->bnx_flash_info->page_size) << 1661 sc->bnx_flash_info->page_bits) + 1662 (offset % sc->bnx_flash_info->page_size); 1663 } 1664 1665 /* 1666 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1667 * set the NVRAM address to write, and issue the write command 1668 */ 1669 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1670 memcpy(&val32, val, 4); 1671 val32 = htobe32(val32); 1672 REG_WR(sc, BNX_NVM_WRITE, val32); 1673 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1674 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1675 1676 /* Wait for completion. */ 1677 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1678 DELAY(5); 1679 1680 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1681 break; 1682 } 1683 if (j >= NVRAM_TIMEOUT_COUNT) { 1684 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1685 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1686 return EBUSY; 1687 } 1688 1689 return 0; 1690 } 1691 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1692 1693 /****************************************************************************/ 1694 /* Initialize NVRAM access. */ 1695 /* */ 1696 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1697 /* access that device. */ 1698 /* */ 1699 /* Returns: */ 1700 /* 0 on success, positive value on failure. */ 1701 /****************************************************************************/ 1702 int 1703 bnx_init_nvram(struct bnx_softc *sc) 1704 { 1705 uint32_t val; 1706 int j, entry_count, rc = 0; 1707 struct flash_spec *flash; 1708 1709 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1710 1711 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1712 sc->bnx_flash_info = &flash_5709; 1713 goto bnx_init_nvram_get_flash_size; 1714 } 1715 1716 /* Determine the selected interface. */ 1717 val = REG_RD(sc, BNX_NVM_CFG1); 1718 1719 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1720 1721 /* 1722 * Flash reconfiguration is required to support additional 1723 * NVRAM devices not directly supported in hardware. 1724 * Check if the flash interface was reconfigured 1725 * by the bootcode. 1726 */ 1727 1728 if (val & 0x40000000) { 1729 /* Flash interface reconfigured by bootcode. */ 1730 1731 DBPRINT(sc, BNX_INFO_LOAD, 1732 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1733 1734 for (j = 0, flash = &flash_table[0]; j < entry_count; 1735 j++, flash++) { 1736 if ((val & FLASH_BACKUP_STRAP_MASK) == 1737 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1738 sc->bnx_flash_info = flash; 1739 break; 1740 } 1741 } 1742 } else { 1743 /* Flash interface not yet reconfigured. */ 1744 uint32_t mask; 1745 1746 DBPRINT(sc, BNX_INFO_LOAD, 1747 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1748 1749 if (val & (1 << 23)) 1750 mask = FLASH_BACKUP_STRAP_MASK; 1751 else 1752 mask = FLASH_STRAP_MASK; 1753 1754 /* Look for the matching NVRAM device configuration data. */ 1755 for (j = 0, flash = &flash_table[0]; j < entry_count; 1756 j++, flash++) { 1757 /* Check if the dev matches any of the known devices. */ 1758 if ((val & mask) == (flash->strapping & mask)) { 1759 /* Found a device match. */ 1760 sc->bnx_flash_info = flash; 1761 1762 /* Request access to the flash interface. */ 1763 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1764 return rc; 1765 1766 /* Reconfigure the flash interface. */ 1767 bnx_enable_nvram_access(sc); 1768 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1769 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1770 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1771 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1772 bnx_disable_nvram_access(sc); 1773 bnx_release_nvram_lock(sc); 1774 1775 break; 1776 } 1777 } 1778 } 1779 1780 /* Check if a matching device was found. */ 1781 if (j == entry_count) { 1782 sc->bnx_flash_info = NULL; 1783 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1784 __FILE__, __LINE__); 1785 rc = ENODEV; 1786 } 1787 1788 bnx_init_nvram_get_flash_size: 1789 /* Write the flash config data to the shared memory interface. */ 1790 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1791 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1792 if (val) 1793 sc->bnx_flash_size = val; 1794 else 1795 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1796 1797 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1798 "0x%08X\n", sc->bnx_flash_info->total_size); 1799 1800 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1801 1802 return rc; 1803 } 1804 1805 /****************************************************************************/ 1806 /* Read an arbitrary range of data from NVRAM. */ 1807 /* */ 1808 /* Prepares the NVRAM interface for access and reads the requested data */ 1809 /* into the supplied buffer. */ 1810 /* */ 1811 /* Returns: */ 1812 /* 0 on success and the data read, positive value on failure. */ 1813 /****************************************************************************/ 1814 int 1815 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1816 int buf_size) 1817 { 1818 int rc = 0; 1819 uint32_t cmd_flags, offset32, len32, extra; 1820 1821 if (buf_size == 0) 1822 return 0; 1823 1824 /* Request access to the flash interface. */ 1825 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1826 return rc; 1827 1828 /* Enable access to flash interface */ 1829 bnx_enable_nvram_access(sc); 1830 1831 len32 = buf_size; 1832 offset32 = offset; 1833 extra = 0; 1834 1835 cmd_flags = 0; 1836 1837 if (offset32 & 3) { 1838 uint8_t buf[4]; 1839 uint32_t pre_len; 1840 1841 offset32 &= ~3; 1842 pre_len = 4 - (offset & 3); 1843 1844 if (pre_len >= len32) { 1845 pre_len = len32; 1846 cmd_flags = 1847 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1848 } else 1849 cmd_flags = BNX_NVM_COMMAND_FIRST; 1850 1851 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1852 1853 if (rc) 1854 return rc; 1855 1856 memcpy(ret_buf, buf + (offset & 3), pre_len); 1857 1858 offset32 += 4; 1859 ret_buf += pre_len; 1860 len32 -= pre_len; 1861 } 1862 1863 if (len32 & 3) { 1864 extra = 4 - (len32 & 3); 1865 len32 = (len32 + 4) & ~3; 1866 } 1867 1868 if (len32 == 4) { 1869 uint8_t buf[4]; 1870 1871 if (cmd_flags) 1872 cmd_flags = BNX_NVM_COMMAND_LAST; 1873 else 1874 cmd_flags = 1875 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1876 1877 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1878 1879 memcpy(ret_buf, buf, 4 - extra); 1880 } else if (len32 > 0) { 1881 uint8_t buf[4]; 1882 1883 /* Read the first word. */ 1884 if (cmd_flags) 1885 cmd_flags = 0; 1886 else 1887 cmd_flags = BNX_NVM_COMMAND_FIRST; 1888 1889 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1890 1891 /* Advance to the next dword. */ 1892 offset32 += 4; 1893 ret_buf += 4; 1894 len32 -= 4; 1895 1896 while (len32 > 4 && rc == 0) { 1897 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1898 1899 /* Advance to the next dword. */ 1900 offset32 += 4; 1901 ret_buf += 4; 1902 len32 -= 4; 1903 } 1904 1905 if (rc) 1906 return rc; 1907 1908 cmd_flags = BNX_NVM_COMMAND_LAST; 1909 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1910 1911 memcpy(ret_buf, buf, 4 - extra); 1912 } 1913 1914 /* Disable access to flash interface and release the lock. */ 1915 bnx_disable_nvram_access(sc); 1916 bnx_release_nvram_lock(sc); 1917 1918 return rc; 1919 } 1920 1921 #ifdef BNX_NVRAM_WRITE_SUPPORT 1922 /****************************************************************************/ 1923 /* Write an arbitrary range of data from NVRAM. */ 1924 /* */ 1925 /* Prepares the NVRAM interface for write access and writes the requested */ 1926 /* data from the supplied buffer. The caller is responsible for */ 1927 /* calculating any appropriate CRCs. */ 1928 /* */ 1929 /* Returns: */ 1930 /* 0 on success, positive value on failure. */ 1931 /****************************************************************************/ 1932 int 1933 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1934 int buf_size) 1935 { 1936 uint32_t written, offset32, len32; 1937 uint8_t *buf, start[4], end[4]; 1938 int rc = 0; 1939 int align_start, align_end; 1940 1941 buf = data_buf; 1942 offset32 = offset; 1943 len32 = buf_size; 1944 align_start = align_end = 0; 1945 1946 if ((align_start = (offset32 & 3))) { 1947 offset32 &= ~3; 1948 len32 += align_start; 1949 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1950 return rc; 1951 } 1952 1953 if (len32 & 3) { 1954 if ((len32 > 4) || !align_start) { 1955 align_end = 4 - (len32 & 3); 1956 len32 += align_end; 1957 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1958 end, 4))) 1959 return rc; 1960 } 1961 } 1962 1963 if (align_start || align_end) { 1964 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1965 if (buf == NULL) 1966 return ENOMEM; 1967 1968 if (align_start) 1969 memcpy(buf, start, 4); 1970 1971 if (align_end) 1972 memcpy(buf + len32 - 4, end, 4); 1973 1974 memcpy(buf + align_start, data_buf, buf_size); 1975 } 1976 1977 written = 0; 1978 while ((written < len32) && (rc == 0)) { 1979 uint32_t page_start, page_end, data_start, data_end; 1980 uint32_t addr, cmd_flags; 1981 int i; 1982 uint8_t flash_buffer[264]; 1983 1984 /* Find the page_start addr */ 1985 page_start = offset32 + written; 1986 page_start -= (page_start % sc->bnx_flash_info->page_size); 1987 /* Find the page_end addr */ 1988 page_end = page_start + sc->bnx_flash_info->page_size; 1989 /* Find the data_start addr */ 1990 data_start = (written == 0) ? offset32 : page_start; 1991 /* Find the data_end addr */ 1992 data_end = (page_end > offset32 + len32) ? 1993 (offset32 + len32) : page_end; 1994 1995 /* Request access to the flash interface. */ 1996 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1997 goto nvram_write_end; 1998 1999 /* Enable access to flash interface */ 2000 bnx_enable_nvram_access(sc); 2001 2002 cmd_flags = BNX_NVM_COMMAND_FIRST; 2003 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2004 int j; 2005 2006 /* Read the whole page into the buffer 2007 * (non-buffer flash only) */ 2008 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 2009 if (j == (sc->bnx_flash_info->page_size - 4)) 2010 cmd_flags |= BNX_NVM_COMMAND_LAST; 2011 2012 rc = bnx_nvram_read_dword(sc, 2013 page_start + j, 2014 &flash_buffer[j], 2015 cmd_flags); 2016 2017 if (rc) 2018 goto nvram_write_end; 2019 2020 cmd_flags = 0; 2021 } 2022 } 2023 2024 /* Enable writes to flash interface (unlock write-protect) */ 2025 if ((rc = bnx_enable_nvram_write(sc)) != 0) 2026 goto nvram_write_end; 2027 2028 /* Erase the page */ 2029 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 2030 goto nvram_write_end; 2031 2032 /* Re-enable the write again for the actual write */ 2033 bnx_enable_nvram_write(sc); 2034 2035 /* Loop to write back the buffer data from page_start to 2036 * data_start */ 2037 i = 0; 2038 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2039 for (addr = page_start; addr < data_start; 2040 addr += 4, i += 4) { 2041 2042 rc = bnx_nvram_write_dword(sc, addr, 2043 &flash_buffer[i], cmd_flags); 2044 2045 if (rc != 0) 2046 goto nvram_write_end; 2047 2048 cmd_flags = 0; 2049 } 2050 } 2051 2052 /* Loop to write the new data from data_start to data_end */ 2053 for (addr = data_start; addr < data_end; addr += 4, i++) { 2054 if ((addr == page_end - 4) || 2055 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 2056 && (addr == data_end - 4))) { 2057 2058 cmd_flags |= BNX_NVM_COMMAND_LAST; 2059 } 2060 2061 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2062 2063 if (rc != 0) 2064 goto nvram_write_end; 2065 2066 cmd_flags = 0; 2067 buf += 4; 2068 } 2069 2070 /* Loop to write back the buffer data from data_end 2071 * to page_end */ 2072 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2073 for (addr = data_end; addr < page_end; 2074 addr += 4, i += 4) { 2075 2076 if (addr == page_end-4) 2077 cmd_flags = BNX_NVM_COMMAND_LAST; 2078 2079 rc = bnx_nvram_write_dword(sc, addr, 2080 &flash_buffer[i], cmd_flags); 2081 2082 if (rc != 0) 2083 goto nvram_write_end; 2084 2085 cmd_flags = 0; 2086 } 2087 } 2088 2089 /* Disable writes to flash interface (lock write-protect) */ 2090 bnx_disable_nvram_write(sc); 2091 2092 /* Disable access to flash interface */ 2093 bnx_disable_nvram_access(sc); 2094 bnx_release_nvram_lock(sc); 2095 2096 /* Increment written */ 2097 written += data_end - data_start; 2098 } 2099 2100 nvram_write_end: 2101 if (align_start || align_end) 2102 free(buf, M_DEVBUF); 2103 2104 return rc; 2105 } 2106 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2107 2108 /****************************************************************************/ 2109 /* Verifies that NVRAM is accessible and contains valid data. */ 2110 /* */ 2111 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2112 /* correct. */ 2113 /* */ 2114 /* Returns: */ 2115 /* 0 on success, positive value on failure. */ 2116 /****************************************************************************/ 2117 int 2118 bnx_nvram_test(struct bnx_softc *sc) 2119 { 2120 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2121 uint8_t *data = (uint8_t *) buf; 2122 int rc = 0; 2123 uint32_t magic, csum; 2124 2125 /* 2126 * Check that the device NVRAM is valid by reading 2127 * the magic value at offset 0. 2128 */ 2129 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2130 goto bnx_nvram_test_done; 2131 2132 magic = be32toh(buf[0]); 2133 if (magic != BNX_NVRAM_MAGIC) { 2134 rc = ENODEV; 2135 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2136 "Expected: 0x%08X, Found: 0x%08X\n", 2137 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2138 goto bnx_nvram_test_done; 2139 } 2140 2141 /* 2142 * Verify that the device NVRAM includes valid 2143 * configuration data. 2144 */ 2145 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2146 goto bnx_nvram_test_done; 2147 2148 csum = ether_crc32_le(data, 0x100); 2149 if (csum != BNX_CRC32_RESIDUAL) { 2150 rc = ENODEV; 2151 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2152 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2153 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2154 goto bnx_nvram_test_done; 2155 } 2156 2157 csum = ether_crc32_le(data + 0x100, 0x100); 2158 if (csum != BNX_CRC32_RESIDUAL) { 2159 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2160 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2161 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2162 rc = ENODEV; 2163 } 2164 2165 bnx_nvram_test_done: 2166 return rc; 2167 } 2168 2169 /****************************************************************************/ 2170 /* Identifies the current media type of the controller and sets the PHY */ 2171 /* address. */ 2172 /* */ 2173 /* Returns: */ 2174 /* Nothing. */ 2175 /****************************************************************************/ 2176 void 2177 bnx_get_media(struct bnx_softc *sc) 2178 { 2179 sc->bnx_phy_addr = 1; 2180 2181 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2182 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2183 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2184 uint32_t strap; 2185 2186 /* 2187 * The BCM5709S is software configurable 2188 * for Copper or SerDes operation. 2189 */ 2190 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2191 DBPRINT(sc, BNX_INFO_LOAD, 2192 "5709 bonded for copper.\n"); 2193 goto bnx_get_media_exit; 2194 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2195 DBPRINT(sc, BNX_INFO_LOAD, 2196 "5709 bonded for dual media.\n"); 2197 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2198 goto bnx_get_media_exit; 2199 } 2200 2201 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2202 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2203 else { 2204 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2205 >> 8; 2206 } 2207 2208 if (sc->bnx_pa.pa_function == 0) { 2209 switch (strap) { 2210 case 0x4: 2211 case 0x5: 2212 case 0x6: 2213 DBPRINT(sc, BNX_INFO_LOAD, 2214 "BCM5709 s/w configured for SerDes.\n"); 2215 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2216 break; 2217 default: 2218 DBPRINT(sc, BNX_INFO_LOAD, 2219 "BCM5709 s/w configured for Copper.\n"); 2220 } 2221 } else { 2222 switch (strap) { 2223 case 0x1: 2224 case 0x2: 2225 case 0x4: 2226 DBPRINT(sc, BNX_INFO_LOAD, 2227 "BCM5709 s/w configured for SerDes.\n"); 2228 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2229 break; 2230 default: 2231 DBPRINT(sc, BNX_INFO_LOAD, 2232 "BCM5709 s/w configured for Copper.\n"); 2233 } 2234 } 2235 2236 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2237 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2238 2239 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2240 uint32_t val; 2241 2242 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2243 2244 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2245 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2246 2247 /* 2248 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2249 * separate PHY for SerDes. 2250 */ 2251 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2252 sc->bnx_phy_addr = 2; 2253 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2254 BNX_SHARED_HW_CFG_CONFIG); 2255 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2256 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2257 DBPRINT(sc, BNX_INFO_LOAD, 2258 "Found 2.5Gb capable adapter\n"); 2259 } 2260 } 2261 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2262 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2263 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2264 2265 bnx_get_media_exit: 2266 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2267 "Using PHY address %d.\n", sc->bnx_phy_addr); 2268 } 2269 2270 /****************************************************************************/ 2271 /* Performs PHY initialization required before MII drivers access the */ 2272 /* device. */ 2273 /* */ 2274 /* Returns: */ 2275 /* Nothing. */ 2276 /****************************************************************************/ 2277 void 2278 bnx_init_media(struct bnx_softc *sc) 2279 { 2280 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2281 /* 2282 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2283 * IEEE Clause 22 method. Otherwise we have no way to attach 2284 * the PHY to the mii(4) layer. PHY specific configuration 2285 * is done by the mii(4) layer. 2286 */ 2287 2288 /* Select auto-negotiation MMD of the PHY. */ 2289 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2290 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2291 2292 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2293 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2294 2295 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2296 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2297 } 2298 } 2299 2300 /****************************************************************************/ 2301 /* Free any DMA memory owned by the driver. */ 2302 /* */ 2303 /* Scans through each data structre that requires DMA memory and frees */ 2304 /* the memory if allocated. */ 2305 /* */ 2306 /* Returns: */ 2307 /* Nothing. */ 2308 /****************************************************************************/ 2309 void 2310 bnx_dma_free(struct bnx_softc *sc) 2311 { 2312 int i; 2313 2314 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2315 2316 /* Destroy the status block. */ 2317 if (sc->status_block != NULL && sc->status_map != NULL) { 2318 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2319 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2320 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2321 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2322 BNX_STATUS_BLK_SZ); 2323 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2324 sc->status_rseg); 2325 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2326 sc->status_block = NULL; 2327 sc->status_map = NULL; 2328 } 2329 2330 /* Destroy the statistics block. */ 2331 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2332 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2333 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2334 BNX_STATS_BLK_SZ); 2335 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2336 sc->stats_rseg); 2337 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2338 sc->stats_block = NULL; 2339 sc->stats_map = NULL; 2340 } 2341 2342 /* Free, unmap and destroy all context memory pages. */ 2343 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2344 for (i = 0; i < sc->ctx_pages; i++) { 2345 if (sc->ctx_block[i] != NULL) { 2346 bus_dmamap_unload(sc->bnx_dmatag, 2347 sc->ctx_map[i]); 2348 bus_dmamem_unmap(sc->bnx_dmatag, 2349 (void *)sc->ctx_block[i], 2350 BCM_PAGE_SIZE); 2351 bus_dmamem_free(sc->bnx_dmatag, 2352 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2353 bus_dmamap_destroy(sc->bnx_dmatag, 2354 sc->ctx_map[i]); 2355 sc->ctx_block[i] = NULL; 2356 } 2357 } 2358 } 2359 2360 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2361 for (i = 0; i < TX_PAGES; i++ ) { 2362 if (sc->tx_bd_chain[i] != NULL && 2363 sc->tx_bd_chain_map[i] != NULL) { 2364 bus_dmamap_unload(sc->bnx_dmatag, 2365 sc->tx_bd_chain_map[i]); 2366 bus_dmamem_unmap(sc->bnx_dmatag, 2367 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2368 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2369 sc->tx_bd_chain_rseg[i]); 2370 bus_dmamap_destroy(sc->bnx_dmatag, 2371 sc->tx_bd_chain_map[i]); 2372 sc->tx_bd_chain[i] = NULL; 2373 sc->tx_bd_chain_map[i] = NULL; 2374 } 2375 } 2376 2377 /* Destroy the TX dmamaps. */ 2378 /* This isn't necessary since we dont allocate them up front */ 2379 2380 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2381 for (i = 0; i < RX_PAGES; i++ ) { 2382 if (sc->rx_bd_chain[i] != NULL && 2383 sc->rx_bd_chain_map[i] != NULL) { 2384 bus_dmamap_unload(sc->bnx_dmatag, 2385 sc->rx_bd_chain_map[i]); 2386 bus_dmamem_unmap(sc->bnx_dmatag, 2387 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2388 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2389 sc->rx_bd_chain_rseg[i]); 2390 2391 bus_dmamap_destroy(sc->bnx_dmatag, 2392 sc->rx_bd_chain_map[i]); 2393 sc->rx_bd_chain[i] = NULL; 2394 sc->rx_bd_chain_map[i] = NULL; 2395 } 2396 } 2397 2398 /* Unload and destroy the RX mbuf maps. */ 2399 for (i = 0; i < TOTAL_RX_BD; i++) { 2400 if (sc->rx_mbuf_map[i] != NULL) { 2401 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2402 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2403 } 2404 } 2405 2406 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2407 } 2408 2409 /****************************************************************************/ 2410 /* Allocate any DMA memory needed by the driver. */ 2411 /* */ 2412 /* Allocates DMA memory needed for the various global structures needed by */ 2413 /* hardware. */ 2414 /* */ 2415 /* Returns: */ 2416 /* 0 for success, positive value for failure. */ 2417 /****************************************************************************/ 2418 int 2419 bnx_dma_alloc(struct bnx_softc *sc) 2420 { 2421 int i, rc = 0; 2422 2423 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2424 2425 /* 2426 * Allocate DMA memory for the status block, map the memory into DMA 2427 * space, and fetch the physical address of the block. 2428 */ 2429 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2430 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2431 aprint_error_dev(sc->bnx_dev, 2432 "Could not create status block DMA map!\n"); 2433 rc = ENOMEM; 2434 goto bnx_dma_alloc_exit; 2435 } 2436 2437 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2438 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2439 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2440 aprint_error_dev(sc->bnx_dev, 2441 "Could not allocate status block DMA memory!\n"); 2442 rc = ENOMEM; 2443 goto bnx_dma_alloc_exit; 2444 } 2445 2446 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2447 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2448 aprint_error_dev(sc->bnx_dev, 2449 "Could not map status block DMA memory!\n"); 2450 rc = ENOMEM; 2451 goto bnx_dma_alloc_exit; 2452 } 2453 2454 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2455 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2456 aprint_error_dev(sc->bnx_dev, 2457 "Could not load status block DMA memory!\n"); 2458 rc = ENOMEM; 2459 goto bnx_dma_alloc_exit; 2460 } 2461 2462 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2463 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2464 2465 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2466 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2467 2468 /* DRC - Fix for 64 bit addresses. */ 2469 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2470 (uint32_t) sc->status_block_paddr); 2471 2472 /* BCM5709 uses host memory as cache for context memory. */ 2473 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2474 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2475 if (sc->ctx_pages == 0) 2476 sc->ctx_pages = 1; 2477 if (sc->ctx_pages > 4) /* XXX */ 2478 sc->ctx_pages = 4; 2479 2480 DBRUNIF((sc->ctx_pages > 512), 2481 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2482 __FILE__, __LINE__, sc->ctx_pages)); 2483 2484 2485 for (i = 0; i < sc->ctx_pages; i++) { 2486 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2487 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2488 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2489 &sc->ctx_map[i]) != 0) { 2490 rc = ENOMEM; 2491 goto bnx_dma_alloc_exit; 2492 } 2493 2494 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2495 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2496 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2497 rc = ENOMEM; 2498 goto bnx_dma_alloc_exit; 2499 } 2500 2501 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2502 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2503 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2504 rc = ENOMEM; 2505 goto bnx_dma_alloc_exit; 2506 } 2507 2508 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2509 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2510 BUS_DMA_NOWAIT) != 0) { 2511 rc = ENOMEM; 2512 goto bnx_dma_alloc_exit; 2513 } 2514 2515 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2516 } 2517 } 2518 2519 /* 2520 * Allocate DMA memory for the statistics block, map the memory into 2521 * DMA space, and fetch the physical address of the block. 2522 */ 2523 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2524 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2525 aprint_error_dev(sc->bnx_dev, 2526 "Could not create stats block DMA map!\n"); 2527 rc = ENOMEM; 2528 goto bnx_dma_alloc_exit; 2529 } 2530 2531 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2532 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2533 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2534 aprint_error_dev(sc->bnx_dev, 2535 "Could not allocate stats block DMA memory!\n"); 2536 rc = ENOMEM; 2537 goto bnx_dma_alloc_exit; 2538 } 2539 2540 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2541 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2542 aprint_error_dev(sc->bnx_dev, 2543 "Could not map stats block DMA memory!\n"); 2544 rc = ENOMEM; 2545 goto bnx_dma_alloc_exit; 2546 } 2547 2548 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2549 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2550 aprint_error_dev(sc->bnx_dev, 2551 "Could not load status block DMA memory!\n"); 2552 rc = ENOMEM; 2553 goto bnx_dma_alloc_exit; 2554 } 2555 2556 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2557 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2558 2559 /* DRC - Fix for 64 bit address. */ 2560 DBPRINT(sc, BNX_INFO, "stats_block_paddr = 0x%08X\n", 2561 (uint32_t) sc->stats_block_paddr); 2562 2563 /* 2564 * Allocate DMA memory for the TX buffer descriptor chain, 2565 * and fetch the physical address of the block. 2566 */ 2567 for (i = 0; i < TX_PAGES; i++) { 2568 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2569 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2570 &sc->tx_bd_chain_map[i])) { 2571 aprint_error_dev(sc->bnx_dev, 2572 "Could not create Tx desc %d DMA map!\n", i); 2573 rc = ENOMEM; 2574 goto bnx_dma_alloc_exit; 2575 } 2576 2577 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2578 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2579 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2580 aprint_error_dev(sc->bnx_dev, 2581 "Could not allocate TX desc %d DMA memory!\n", 2582 i); 2583 rc = ENOMEM; 2584 goto bnx_dma_alloc_exit; 2585 } 2586 2587 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2588 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2589 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2590 aprint_error_dev(sc->bnx_dev, 2591 "Could not map TX desc %d DMA memory!\n", i); 2592 rc = ENOMEM; 2593 goto bnx_dma_alloc_exit; 2594 } 2595 2596 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2597 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2598 BUS_DMA_NOWAIT)) { 2599 aprint_error_dev(sc->bnx_dev, 2600 "Could not load TX desc %d DMA memory!\n", i); 2601 rc = ENOMEM; 2602 goto bnx_dma_alloc_exit; 2603 } 2604 2605 sc->tx_bd_chain_paddr[i] = 2606 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2607 2608 /* DRC - Fix for 64 bit systems. */ 2609 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2610 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2611 } 2612 2613 /* 2614 * Create lists to hold TX mbufs. 2615 */ 2616 TAILQ_INIT(&sc->tx_free_pkts); 2617 TAILQ_INIT(&sc->tx_used_pkts); 2618 sc->tx_pkt_count = 0; 2619 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2620 2621 /* 2622 * Allocate DMA memory for the Rx buffer descriptor chain, 2623 * and fetch the physical address of the block. 2624 */ 2625 for (i = 0; i < RX_PAGES; i++) { 2626 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2627 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2628 &sc->rx_bd_chain_map[i])) { 2629 aprint_error_dev(sc->bnx_dev, 2630 "Could not create Rx desc %d DMA map!\n", i); 2631 rc = ENOMEM; 2632 goto bnx_dma_alloc_exit; 2633 } 2634 2635 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2636 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2637 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2638 aprint_error_dev(sc->bnx_dev, 2639 "Could not allocate Rx desc %d DMA memory!\n", i); 2640 rc = ENOMEM; 2641 goto bnx_dma_alloc_exit; 2642 } 2643 2644 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2645 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2646 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2647 aprint_error_dev(sc->bnx_dev, 2648 "Could not map Rx desc %d DMA memory!\n", i); 2649 rc = ENOMEM; 2650 goto bnx_dma_alloc_exit; 2651 } 2652 2653 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2654 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2655 BUS_DMA_NOWAIT)) { 2656 aprint_error_dev(sc->bnx_dev, 2657 "Could not load Rx desc %d DMA memory!\n", i); 2658 rc = ENOMEM; 2659 goto bnx_dma_alloc_exit; 2660 } 2661 2662 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2663 sc->rx_bd_chain_paddr[i] = 2664 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2665 2666 /* DRC - Fix for 64 bit systems. */ 2667 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2668 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2669 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2670 0, BNX_RX_CHAIN_PAGE_SZ, 2671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2672 } 2673 2674 /* 2675 * Create DMA maps for the Rx buffer mbufs. 2676 */ 2677 for (i = 0; i < TOTAL_RX_BD; i++) { 2678 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2679 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2680 &sc->rx_mbuf_map[i])) { 2681 aprint_error_dev(sc->bnx_dev, 2682 "Could not create Rx mbuf %d DMA map!\n", i); 2683 rc = ENOMEM; 2684 goto bnx_dma_alloc_exit; 2685 } 2686 } 2687 2688 bnx_dma_alloc_exit: 2689 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2690 2691 return rc; 2692 } 2693 2694 /****************************************************************************/ 2695 /* Release all resources used by the driver. */ 2696 /* */ 2697 /* Releases all resources acquired by the driver including interrupts, */ 2698 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2699 /* */ 2700 /* Returns: */ 2701 /* Nothing. */ 2702 /****************************************************************************/ 2703 void 2704 bnx_release_resources(struct bnx_softc *sc) 2705 { 2706 struct pci_attach_args *pa = &(sc->bnx_pa); 2707 2708 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2709 2710 bnx_dma_free(sc); 2711 2712 if (sc->bnx_intrhand != NULL) 2713 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2714 2715 if (sc->bnx_ih != NULL) 2716 pci_intr_release(pa->pa_pc, sc->bnx_ih, 1); 2717 2718 if (sc->bnx_size) 2719 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2720 2721 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2722 } 2723 2724 /****************************************************************************/ 2725 /* Firmware synchronization. */ 2726 /* */ 2727 /* Before performing certain events such as a chip reset, synchronize with */ 2728 /* the firmware first. */ 2729 /* */ 2730 /* Returns: */ 2731 /* 0 for success, positive value for failure. */ 2732 /****************************************************************************/ 2733 int 2734 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2735 { 2736 int i, rc = 0; 2737 uint32_t val; 2738 2739 /* Don't waste any time if we've timed out before. */ 2740 if (sc->bnx_fw_timed_out) { 2741 rc = EBUSY; 2742 goto bnx_fw_sync_exit; 2743 } 2744 2745 /* Increment the message sequence number. */ 2746 sc->bnx_fw_wr_seq++; 2747 msg_data |= sc->bnx_fw_wr_seq; 2748 2749 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2750 msg_data); 2751 2752 /* Send the message to the bootcode driver mailbox. */ 2753 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2754 2755 /* Wait for the bootcode to acknowledge the message. */ 2756 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2757 /* Check for a response in the bootcode firmware mailbox. */ 2758 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2759 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2760 break; 2761 DELAY(1000); 2762 } 2763 2764 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2765 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2766 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2767 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2768 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2769 2770 msg_data &= ~BNX_DRV_MSG_CODE; 2771 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2772 2773 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2774 2775 sc->bnx_fw_timed_out = 1; 2776 rc = EBUSY; 2777 } 2778 2779 bnx_fw_sync_exit: 2780 return rc; 2781 } 2782 2783 /****************************************************************************/ 2784 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2785 /* */ 2786 /* Returns: */ 2787 /* Nothing. */ 2788 /****************************************************************************/ 2789 void 2790 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2791 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2792 { 2793 int i; 2794 uint32_t val; 2795 2796 /* Set the page size used by RV2P. */ 2797 if (rv2p_proc == RV2P_PROC2) { 2798 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2799 USABLE_RX_BD_PER_PAGE); 2800 } 2801 2802 for (i = 0; i < rv2p_code_len; i += 8) { 2803 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2804 rv2p_code++; 2805 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2806 rv2p_code++; 2807 2808 if (rv2p_proc == RV2P_PROC1) { 2809 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2810 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2811 } else { 2812 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2813 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2814 } 2815 } 2816 2817 /* Reset the processor, un-stall is done later. */ 2818 if (rv2p_proc == RV2P_PROC1) 2819 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2820 else 2821 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2822 } 2823 2824 /****************************************************************************/ 2825 /* Load RISC processor firmware. */ 2826 /* */ 2827 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2828 /* associated with a particular processor. */ 2829 /* */ 2830 /* Returns: */ 2831 /* Nothing. */ 2832 /****************************************************************************/ 2833 void 2834 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2835 struct fw_info *fw) 2836 { 2837 uint32_t offset; 2838 uint32_t val; 2839 2840 /* Halt the CPU. */ 2841 val = REG_RD_IND(sc, cpu_reg->mode); 2842 val |= cpu_reg->mode_value_halt; 2843 REG_WR_IND(sc, cpu_reg->mode, val); 2844 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2845 2846 /* Load the Text area. */ 2847 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2848 if (fw->text) { 2849 int j; 2850 2851 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2852 REG_WR_IND(sc, offset, fw->text[j]); 2853 } 2854 2855 /* Load the Data area. */ 2856 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2857 if (fw->data) { 2858 int j; 2859 2860 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2861 REG_WR_IND(sc, offset, fw->data[j]); 2862 } 2863 2864 /* Load the SBSS area. */ 2865 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2866 if (fw->sbss) { 2867 int j; 2868 2869 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2870 REG_WR_IND(sc, offset, fw->sbss[j]); 2871 } 2872 2873 /* Load the BSS area. */ 2874 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2875 if (fw->bss) { 2876 int j; 2877 2878 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2879 REG_WR_IND(sc, offset, fw->bss[j]); 2880 } 2881 2882 /* Load the Read-Only area. */ 2883 offset = cpu_reg->spad_base + 2884 (fw->rodata_addr - cpu_reg->mips_view_base); 2885 if (fw->rodata) { 2886 int j; 2887 2888 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2889 REG_WR_IND(sc, offset, fw->rodata[j]); 2890 } 2891 2892 /* Clear the pre-fetch instruction. */ 2893 REG_WR_IND(sc, cpu_reg->inst, 0); 2894 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2895 2896 /* Start the CPU. */ 2897 val = REG_RD_IND(sc, cpu_reg->mode); 2898 val &= ~cpu_reg->mode_value_halt; 2899 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2900 REG_WR_IND(sc, cpu_reg->mode, val); 2901 } 2902 2903 /****************************************************************************/ 2904 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2905 /* */ 2906 /* Loads the firmware for each CPU and starts the CPU. */ 2907 /* */ 2908 /* Returns: */ 2909 /* Nothing. */ 2910 /****************************************************************************/ 2911 void 2912 bnx_init_cpus(struct bnx_softc *sc) 2913 { 2914 struct cpu_reg cpu_reg; 2915 struct fw_info fw; 2916 2917 switch (BNX_CHIP_NUM(sc)) { 2918 case BNX_CHIP_NUM_5709: 2919 /* Initialize the RV2P processor. */ 2920 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2921 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2922 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2923 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2924 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2925 } else { 2926 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2927 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2928 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2929 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2930 } 2931 2932 /* Initialize the RX Processor. */ 2933 cpu_reg.mode = BNX_RXP_CPU_MODE; 2934 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2935 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2936 cpu_reg.state = BNX_RXP_CPU_STATE; 2937 cpu_reg.state_value_clear = 0xffffff; 2938 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2939 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2940 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2941 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2942 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2943 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2944 cpu_reg.mips_view_base = 0x8000000; 2945 2946 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2947 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2948 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2949 fw.start_addr = bnx_RXP_b09FwStartAddr; 2950 2951 fw.text_addr = bnx_RXP_b09FwTextAddr; 2952 fw.text_len = bnx_RXP_b09FwTextLen; 2953 fw.text_index = 0; 2954 fw.text = bnx_RXP_b09FwText; 2955 2956 fw.data_addr = bnx_RXP_b09FwDataAddr; 2957 fw.data_len = bnx_RXP_b09FwDataLen; 2958 fw.data_index = 0; 2959 fw.data = bnx_RXP_b09FwData; 2960 2961 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2962 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2963 fw.sbss_index = 0; 2964 fw.sbss = bnx_RXP_b09FwSbss; 2965 2966 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2967 fw.bss_len = bnx_RXP_b09FwBssLen; 2968 fw.bss_index = 0; 2969 fw.bss = bnx_RXP_b09FwBss; 2970 2971 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2972 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2973 fw.rodata_index = 0; 2974 fw.rodata = bnx_RXP_b09FwRodata; 2975 2976 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2977 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2978 2979 /* Initialize the TX Processor. */ 2980 cpu_reg.mode = BNX_TXP_CPU_MODE; 2981 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2982 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2983 cpu_reg.state = BNX_TXP_CPU_STATE; 2984 cpu_reg.state_value_clear = 0xffffff; 2985 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2986 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2987 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2988 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2989 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2990 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2991 cpu_reg.mips_view_base = 0x8000000; 2992 2993 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 2994 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 2995 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 2996 fw.start_addr = bnx_TXP_b09FwStartAddr; 2997 2998 fw.text_addr = bnx_TXP_b09FwTextAddr; 2999 fw.text_len = bnx_TXP_b09FwTextLen; 3000 fw.text_index = 0; 3001 fw.text = bnx_TXP_b09FwText; 3002 3003 fw.data_addr = bnx_TXP_b09FwDataAddr; 3004 fw.data_len = bnx_TXP_b09FwDataLen; 3005 fw.data_index = 0; 3006 fw.data = bnx_TXP_b09FwData; 3007 3008 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 3009 fw.sbss_len = bnx_TXP_b09FwSbssLen; 3010 fw.sbss_index = 0; 3011 fw.sbss = bnx_TXP_b09FwSbss; 3012 3013 fw.bss_addr = bnx_TXP_b09FwBssAddr; 3014 fw.bss_len = bnx_TXP_b09FwBssLen; 3015 fw.bss_index = 0; 3016 fw.bss = bnx_TXP_b09FwBss; 3017 3018 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 3019 fw.rodata_len = bnx_TXP_b09FwRodataLen; 3020 fw.rodata_index = 0; 3021 fw.rodata = bnx_TXP_b09FwRodata; 3022 3023 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3024 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3025 3026 /* Initialize the TX Patch-up Processor. */ 3027 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3028 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3029 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3030 cpu_reg.state = BNX_TPAT_CPU_STATE; 3031 cpu_reg.state_value_clear = 0xffffff; 3032 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3033 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3034 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3035 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3036 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3037 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3038 cpu_reg.mips_view_base = 0x8000000; 3039 3040 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 3041 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 3042 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 3043 fw.start_addr = bnx_TPAT_b09FwStartAddr; 3044 3045 fw.text_addr = bnx_TPAT_b09FwTextAddr; 3046 fw.text_len = bnx_TPAT_b09FwTextLen; 3047 fw.text_index = 0; 3048 fw.text = bnx_TPAT_b09FwText; 3049 3050 fw.data_addr = bnx_TPAT_b09FwDataAddr; 3051 fw.data_len = bnx_TPAT_b09FwDataLen; 3052 fw.data_index = 0; 3053 fw.data = bnx_TPAT_b09FwData; 3054 3055 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 3056 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 3057 fw.sbss_index = 0; 3058 fw.sbss = bnx_TPAT_b09FwSbss; 3059 3060 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 3061 fw.bss_len = bnx_TPAT_b09FwBssLen; 3062 fw.bss_index = 0; 3063 fw.bss = bnx_TPAT_b09FwBss; 3064 3065 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3066 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3067 fw.rodata_index = 0; 3068 fw.rodata = bnx_TPAT_b09FwRodata; 3069 3070 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3071 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3072 3073 /* Initialize the Completion Processor. */ 3074 cpu_reg.mode = BNX_COM_CPU_MODE; 3075 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3076 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3077 cpu_reg.state = BNX_COM_CPU_STATE; 3078 cpu_reg.state_value_clear = 0xffffff; 3079 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3080 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3081 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3082 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3083 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3084 cpu_reg.spad_base = BNX_COM_SCRATCH; 3085 cpu_reg.mips_view_base = 0x8000000; 3086 3087 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3088 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3089 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3090 fw.start_addr = bnx_COM_b09FwStartAddr; 3091 3092 fw.text_addr = bnx_COM_b09FwTextAddr; 3093 fw.text_len = bnx_COM_b09FwTextLen; 3094 fw.text_index = 0; 3095 fw.text = bnx_COM_b09FwText; 3096 3097 fw.data_addr = bnx_COM_b09FwDataAddr; 3098 fw.data_len = bnx_COM_b09FwDataLen; 3099 fw.data_index = 0; 3100 fw.data = bnx_COM_b09FwData; 3101 3102 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3103 fw.sbss_len = bnx_COM_b09FwSbssLen; 3104 fw.sbss_index = 0; 3105 fw.sbss = bnx_COM_b09FwSbss; 3106 3107 fw.bss_addr = bnx_COM_b09FwBssAddr; 3108 fw.bss_len = bnx_COM_b09FwBssLen; 3109 fw.bss_index = 0; 3110 fw.bss = bnx_COM_b09FwBss; 3111 3112 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3113 fw.rodata_len = bnx_COM_b09FwRodataLen; 3114 fw.rodata_index = 0; 3115 fw.rodata = bnx_COM_b09FwRodata; 3116 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3117 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3118 break; 3119 default: 3120 /* Initialize the RV2P processor. */ 3121 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3122 RV2P_PROC1); 3123 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3124 RV2P_PROC2); 3125 3126 /* Initialize the RX Processor. */ 3127 cpu_reg.mode = BNX_RXP_CPU_MODE; 3128 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3129 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3130 cpu_reg.state = BNX_RXP_CPU_STATE; 3131 cpu_reg.state_value_clear = 0xffffff; 3132 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3133 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3134 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3135 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3136 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3137 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3138 cpu_reg.mips_view_base = 0x8000000; 3139 3140 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3141 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3142 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3143 fw.start_addr = bnx_RXP_b06FwStartAddr; 3144 3145 fw.text_addr = bnx_RXP_b06FwTextAddr; 3146 fw.text_len = bnx_RXP_b06FwTextLen; 3147 fw.text_index = 0; 3148 fw.text = bnx_RXP_b06FwText; 3149 3150 fw.data_addr = bnx_RXP_b06FwDataAddr; 3151 fw.data_len = bnx_RXP_b06FwDataLen; 3152 fw.data_index = 0; 3153 fw.data = bnx_RXP_b06FwData; 3154 3155 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3156 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3157 fw.sbss_index = 0; 3158 fw.sbss = bnx_RXP_b06FwSbss; 3159 3160 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3161 fw.bss_len = bnx_RXP_b06FwBssLen; 3162 fw.bss_index = 0; 3163 fw.bss = bnx_RXP_b06FwBss; 3164 3165 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3166 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3167 fw.rodata_index = 0; 3168 fw.rodata = bnx_RXP_b06FwRodata; 3169 3170 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3171 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3172 3173 /* Initialize the TX Processor. */ 3174 cpu_reg.mode = BNX_TXP_CPU_MODE; 3175 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3176 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3177 cpu_reg.state = BNX_TXP_CPU_STATE; 3178 cpu_reg.state_value_clear = 0xffffff; 3179 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3180 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3181 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3182 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3183 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3184 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3185 cpu_reg.mips_view_base = 0x8000000; 3186 3187 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3188 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3189 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3190 fw.start_addr = bnx_TXP_b06FwStartAddr; 3191 3192 fw.text_addr = bnx_TXP_b06FwTextAddr; 3193 fw.text_len = bnx_TXP_b06FwTextLen; 3194 fw.text_index = 0; 3195 fw.text = bnx_TXP_b06FwText; 3196 3197 fw.data_addr = bnx_TXP_b06FwDataAddr; 3198 fw.data_len = bnx_TXP_b06FwDataLen; 3199 fw.data_index = 0; 3200 fw.data = bnx_TXP_b06FwData; 3201 3202 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3203 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3204 fw.sbss_index = 0; 3205 fw.sbss = bnx_TXP_b06FwSbss; 3206 3207 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3208 fw.bss_len = bnx_TXP_b06FwBssLen; 3209 fw.bss_index = 0; 3210 fw.bss = bnx_TXP_b06FwBss; 3211 3212 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3213 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3214 fw.rodata_index = 0; 3215 fw.rodata = bnx_TXP_b06FwRodata; 3216 3217 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3218 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3219 3220 /* Initialize the TX Patch-up Processor. */ 3221 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3222 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3223 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3224 cpu_reg.state = BNX_TPAT_CPU_STATE; 3225 cpu_reg.state_value_clear = 0xffffff; 3226 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3227 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3228 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3229 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3230 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3231 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3232 cpu_reg.mips_view_base = 0x8000000; 3233 3234 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3235 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3236 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3237 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3238 3239 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3240 fw.text_len = bnx_TPAT_b06FwTextLen; 3241 fw.text_index = 0; 3242 fw.text = bnx_TPAT_b06FwText; 3243 3244 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3245 fw.data_len = bnx_TPAT_b06FwDataLen; 3246 fw.data_index = 0; 3247 fw.data = bnx_TPAT_b06FwData; 3248 3249 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3250 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3251 fw.sbss_index = 0; 3252 fw.sbss = bnx_TPAT_b06FwSbss; 3253 3254 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3255 fw.bss_len = bnx_TPAT_b06FwBssLen; 3256 fw.bss_index = 0; 3257 fw.bss = bnx_TPAT_b06FwBss; 3258 3259 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3260 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3261 fw.rodata_index = 0; 3262 fw.rodata = bnx_TPAT_b06FwRodata; 3263 3264 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3265 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3266 3267 /* Initialize the Completion Processor. */ 3268 cpu_reg.mode = BNX_COM_CPU_MODE; 3269 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3270 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3271 cpu_reg.state = BNX_COM_CPU_STATE; 3272 cpu_reg.state_value_clear = 0xffffff; 3273 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3274 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3275 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3276 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3277 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3278 cpu_reg.spad_base = BNX_COM_SCRATCH; 3279 cpu_reg.mips_view_base = 0x8000000; 3280 3281 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3282 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3283 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3284 fw.start_addr = bnx_COM_b06FwStartAddr; 3285 3286 fw.text_addr = bnx_COM_b06FwTextAddr; 3287 fw.text_len = bnx_COM_b06FwTextLen; 3288 fw.text_index = 0; 3289 fw.text = bnx_COM_b06FwText; 3290 3291 fw.data_addr = bnx_COM_b06FwDataAddr; 3292 fw.data_len = bnx_COM_b06FwDataLen; 3293 fw.data_index = 0; 3294 fw.data = bnx_COM_b06FwData; 3295 3296 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3297 fw.sbss_len = bnx_COM_b06FwSbssLen; 3298 fw.sbss_index = 0; 3299 fw.sbss = bnx_COM_b06FwSbss; 3300 3301 fw.bss_addr = bnx_COM_b06FwBssAddr; 3302 fw.bss_len = bnx_COM_b06FwBssLen; 3303 fw.bss_index = 0; 3304 fw.bss = bnx_COM_b06FwBss; 3305 3306 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3307 fw.rodata_len = bnx_COM_b06FwRodataLen; 3308 fw.rodata_index = 0; 3309 fw.rodata = bnx_COM_b06FwRodata; 3310 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3311 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3312 break; 3313 } 3314 } 3315 3316 /****************************************************************************/ 3317 /* Initialize context memory. */ 3318 /* */ 3319 /* Clears the memory associated with each Context ID (CID). */ 3320 /* */ 3321 /* Returns: */ 3322 /* Nothing. */ 3323 /****************************************************************************/ 3324 void 3325 bnx_init_context(struct bnx_softc *sc) 3326 { 3327 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3328 /* DRC: Replace this constant value with a #define. */ 3329 int i, retry_cnt = 10; 3330 uint32_t val; 3331 3332 /* 3333 * BCM5709 context memory may be cached 3334 * in host memory so prepare the host memory 3335 * for access. 3336 */ 3337 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3338 | (1 << 12); 3339 val |= (BCM_PAGE_BITS - 8) << 16; 3340 REG_WR(sc, BNX_CTX_COMMAND, val); 3341 3342 /* Wait for mem init command to complete. */ 3343 for (i = 0; i < retry_cnt; i++) { 3344 val = REG_RD(sc, BNX_CTX_COMMAND); 3345 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3346 break; 3347 DELAY(2); 3348 } 3349 3350 /* ToDo: Consider returning an error here. */ 3351 3352 for (i = 0; i < sc->ctx_pages; i++) { 3353 int j; 3354 3355 /* Set the physaddr of the context memory cache. */ 3356 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3357 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3358 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3359 val = (uint32_t) 3360 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3361 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3362 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3363 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3364 3365 /* Verify that the context memory write was successful. */ 3366 for (j = 0; j < retry_cnt; j++) { 3367 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3368 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3369 break; 3370 DELAY(5); 3371 } 3372 3373 /* ToDo: Consider returning an error here. */ 3374 } 3375 } else { 3376 uint32_t vcid_addr, offset; 3377 3378 /* 3379 * For the 5706/5708, context memory is local to the 3380 * controller, so initialize the controller context memory. 3381 */ 3382 3383 vcid_addr = GET_CID_ADDR(96); 3384 while (vcid_addr) { 3385 3386 vcid_addr -= BNX_PHY_CTX_SIZE; 3387 3388 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3389 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3390 3391 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3392 offset += 4) 3393 CTX_WR(sc, 0x00, offset, 0); 3394 3395 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3396 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3397 } 3398 } 3399 } 3400 3401 /****************************************************************************/ 3402 /* Fetch the permanent MAC address of the controller. */ 3403 /* */ 3404 /* Returns: */ 3405 /* Nothing. */ 3406 /****************************************************************************/ 3407 void 3408 bnx_get_mac_addr(struct bnx_softc *sc) 3409 { 3410 uint32_t mac_lo = 0, mac_hi = 0; 3411 3412 /* 3413 * The NetXtreme II bootcode populates various NIC 3414 * power-on and runtime configuration items in a 3415 * shared memory area. The factory configured MAC 3416 * address is available from both NVRAM and the 3417 * shared memory area so we'll read the value from 3418 * shared memory for speed. 3419 */ 3420 3421 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3422 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3423 3424 if ((mac_lo == 0) && (mac_hi == 0)) { 3425 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3426 __FILE__, __LINE__); 3427 } else { 3428 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3429 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3430 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3431 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3432 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3433 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3434 } 3435 3436 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3437 "%s\n", ether_sprintf(sc->eaddr)); 3438 } 3439 3440 /****************************************************************************/ 3441 /* Program the MAC address. */ 3442 /* */ 3443 /* Returns: */ 3444 /* Nothing. */ 3445 /****************************************************************************/ 3446 void 3447 bnx_set_mac_addr(struct bnx_softc *sc) 3448 { 3449 uint32_t val; 3450 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3451 3452 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3453 "%s\n", ether_sprintf(sc->eaddr)); 3454 3455 val = (mac_addr[0] << 8) | mac_addr[1]; 3456 3457 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3458 3459 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3460 (mac_addr[4] << 8) | mac_addr[5]; 3461 3462 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3463 } 3464 3465 /****************************************************************************/ 3466 /* Stop the controller. */ 3467 /* */ 3468 /* Returns: */ 3469 /* Nothing. */ 3470 /****************************************************************************/ 3471 void 3472 bnx_stop(struct ifnet *ifp, int disable) 3473 { 3474 struct bnx_softc *sc = ifp->if_softc; 3475 3476 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3477 3478 if (disable) { 3479 sc->bnx_detaching = 1; 3480 callout_halt(&sc->bnx_timeout, NULL); 3481 } else 3482 callout_stop(&sc->bnx_timeout); 3483 3484 mii_down(&sc->bnx_mii); 3485 3486 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3487 3488 /* Disable the transmit/receive blocks. */ 3489 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3490 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3491 DELAY(20); 3492 3493 bnx_disable_intr(sc); 3494 3495 /* Tell firmware that the driver is going away. */ 3496 if (disable) 3497 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3498 else 3499 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3500 3501 /* Free RX buffers. */ 3502 bnx_free_rx_chain(sc); 3503 3504 /* Free TX buffers. */ 3505 bnx_free_tx_chain(sc); 3506 3507 ifp->if_timer = 0; 3508 3509 sc->bnx_link = 0; 3510 3511 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3512 3513 bnx_mgmt_init(sc); 3514 } 3515 3516 int 3517 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3518 { 3519 struct pci_attach_args *pa = &(sc->bnx_pa); 3520 uint32_t val; 3521 int i, rc = 0; 3522 3523 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3524 3525 /* Wait for pending PCI transactions to complete. */ 3526 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 3527 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) { 3528 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3529 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3530 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3531 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3532 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3533 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3534 DELAY(5); 3535 } else { 3536 /* Disable DMA */ 3537 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3538 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3539 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3540 REG_RD(sc, BNX_MISC_NEW_CORE_CTL); /* barrier */ 3541 3542 for (i = 0; i < 100; i++) { 3543 delay(1 * 1000); 3544 val = REG_RD(sc, BNX_PCICFG_DEVICE_CONTROL); 3545 if ((val & PCIE_DCSR_TRANSACTION_PND) == 0) 3546 break; 3547 } 3548 } 3549 3550 /* Assume bootcode is running. */ 3551 sc->bnx_fw_timed_out = 0; 3552 3553 /* Give the firmware a chance to prepare for the reset. */ 3554 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3555 if (rc) 3556 goto bnx_reset_exit; 3557 3558 /* Set a firmware reminder that this is a soft reset. */ 3559 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3560 BNX_DRV_RESET_SIGNATURE_MAGIC); 3561 3562 /* Dummy read to force the chip to complete all current transactions. */ 3563 val = REG_RD(sc, BNX_MISC_ID); 3564 3565 /* Chip reset. */ 3566 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3567 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3568 REG_RD(sc, BNX_MISC_COMMAND); 3569 DELAY(5); 3570 3571 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3572 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3573 3574 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3575 val); 3576 } else { 3577 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3578 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3579 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3580 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3581 3582 /* Allow up to 30us for reset to complete. */ 3583 for (i = 0; i < 10; i++) { 3584 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3585 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3586 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3587 break; 3588 } 3589 DELAY(10); 3590 } 3591 3592 /* Check that reset completed successfully. */ 3593 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3594 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3595 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3596 __FILE__, __LINE__); 3597 rc = EBUSY; 3598 goto bnx_reset_exit; 3599 } 3600 } 3601 3602 /* Make sure byte swapping is properly configured. */ 3603 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3604 if (val != 0x01020304) { 3605 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3606 __FILE__, __LINE__); 3607 rc = ENODEV; 3608 goto bnx_reset_exit; 3609 } 3610 3611 /* Just completed a reset, assume that firmware is running again. */ 3612 sc->bnx_fw_timed_out = 0; 3613 3614 /* Wait for the firmware to finish its initialization. */ 3615 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3616 if (rc) 3617 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3618 "initialization!\n", __FILE__, __LINE__); 3619 3620 bnx_reset_exit: 3621 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3622 3623 return rc; 3624 } 3625 3626 int 3627 bnx_chipinit(struct bnx_softc *sc) 3628 { 3629 struct pci_attach_args *pa = &(sc->bnx_pa); 3630 uint32_t val; 3631 int rc = 0; 3632 3633 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3634 3635 /* Make sure the interrupt is not active. */ 3636 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3637 3638 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3639 /* channels and PCI clock compensation delay. */ 3640 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3641 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3642 #if BYTE_ORDER == BIG_ENDIAN 3643 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3644 #endif 3645 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3646 DMA_READ_CHANS << 12 | 3647 DMA_WRITE_CHANS << 16; 3648 3649 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3650 3651 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3652 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3653 3654 /* 3655 * This setting resolves a problem observed on certain Intel PCI 3656 * chipsets that cannot handle multiple outstanding DMA operations. 3657 * See errata E9_5706A1_65. 3658 */ 3659 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3660 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3661 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3662 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3663 3664 REG_WR(sc, BNX_DMA_CONFIG, val); 3665 3666 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3667 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3668 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3669 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3670 val & ~0x20000); 3671 } 3672 3673 /* Enable the RX_V2P and Context state machines before access. */ 3674 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3675 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3676 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3677 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3678 3679 /* Initialize context mapping and zero out the quick contexts. */ 3680 bnx_init_context(sc); 3681 3682 /* Initialize the on-boards CPUs */ 3683 bnx_init_cpus(sc); 3684 3685 /* Enable management frames (NC-SI) to flow to the MCP. */ 3686 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3687 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) | 3688 BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3689 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3690 } 3691 3692 /* Prepare NVRAM for access. */ 3693 if (bnx_init_nvram(sc)) { 3694 rc = ENODEV; 3695 goto bnx_chipinit_exit; 3696 } 3697 3698 /* Set the kernel bypass block size */ 3699 val = REG_RD(sc, BNX_MQ_CONFIG); 3700 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3701 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3702 3703 /* Enable bins used on the 5709. */ 3704 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3705 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3706 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3707 val |= BNX_MQ_CONFIG_HALT_DIS; 3708 } 3709 3710 REG_WR(sc, BNX_MQ_CONFIG, val); 3711 3712 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3713 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3714 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3715 3716 val = (BCM_PAGE_BITS - 8) << 24; 3717 REG_WR(sc, BNX_RV2P_CONFIG, val); 3718 3719 /* Configure page size. */ 3720 val = REG_RD(sc, BNX_TBDR_CONFIG); 3721 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3722 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3723 REG_WR(sc, BNX_TBDR_CONFIG, val); 3724 3725 #if 0 3726 /* Set the perfect match control register to default. */ 3727 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3728 #endif 3729 3730 bnx_chipinit_exit: 3731 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3732 3733 return rc; 3734 } 3735 3736 /****************************************************************************/ 3737 /* Initialize the controller in preparation to send/receive traffic. */ 3738 /* */ 3739 /* Returns: */ 3740 /* 0 for success, positive value for failure. */ 3741 /****************************************************************************/ 3742 int 3743 bnx_blockinit(struct bnx_softc *sc) 3744 { 3745 uint32_t reg, val; 3746 int rc = 0; 3747 3748 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3749 3750 /* Load the hardware default MAC address. */ 3751 bnx_set_mac_addr(sc); 3752 3753 /* Set the Ethernet backoff seed value */ 3754 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3755 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3756 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3757 3758 sc->last_status_idx = 0; 3759 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3760 3761 /* Set up link change interrupt generation. */ 3762 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3763 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3764 3765 /* Program the physical address of the status block. */ 3766 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3767 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3768 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3769 3770 /* Program the physical address of the statistics block. */ 3771 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3772 (uint32_t)(sc->stats_block_paddr)); 3773 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3774 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3775 3776 /* Program various host coalescing parameters. */ 3777 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3778 << 16) | sc->bnx_tx_quick_cons_trip); 3779 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3780 << 16) | sc->bnx_rx_quick_cons_trip); 3781 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3782 sc->bnx_comp_prod_trip); 3783 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3784 sc->bnx_tx_ticks); 3785 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3786 sc->bnx_rx_ticks); 3787 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3788 sc->bnx_com_ticks); 3789 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3790 sc->bnx_cmd_ticks); 3791 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3792 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3793 REG_WR(sc, BNX_HC_CONFIG, 3794 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3795 BNX_HC_CONFIG_COLLECT_STATS)); 3796 3797 /* Clear the internal statistics counters. */ 3798 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3799 3800 /* Verify that bootcode is running. */ 3801 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3802 3803 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3804 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3805 __FILE__, __LINE__); reg = 0); 3806 3807 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3808 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3809 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3810 "Expected: 08%08X\n", __FILE__, __LINE__, 3811 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3812 BNX_DEV_INFO_SIGNATURE_MAGIC); 3813 rc = ENODEV; 3814 goto bnx_blockinit_exit; 3815 } 3816 3817 /* Enable DMA */ 3818 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3819 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3820 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3821 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3822 } 3823 3824 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3825 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3826 3827 /* Disable management frames (NC-SI) from flowing to the MCP. */ 3828 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3829 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) & 3830 ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3831 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3832 } 3833 3834 /* Enable all remaining blocks in the MAC. */ 3835 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3836 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3837 BNX_MISC_ENABLE_DEFAULT_XI); 3838 } else 3839 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3840 3841 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3842 DELAY(20); 3843 3844 bnx_blockinit_exit: 3845 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3846 3847 return rc; 3848 } 3849 3850 static int 3851 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3852 uint16_t *chain_prod, uint32_t *prod_bseq) 3853 { 3854 bus_dmamap_t map; 3855 struct rx_bd *rxbd; 3856 uint32_t addr; 3857 int i; 3858 #ifdef BNX_DEBUG 3859 uint16_t debug_chain_prod = *chain_prod; 3860 #endif 3861 uint16_t first_chain_prod; 3862 3863 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3864 3865 /* Map the mbuf cluster into device memory. */ 3866 map = sc->rx_mbuf_map[*chain_prod]; 3867 first_chain_prod = *chain_prod; 3868 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3869 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3870 __FILE__, __LINE__); 3871 3872 m_freem(m_new); 3873 3874 DBRUNIF(1, sc->rx_mbuf_alloc--); 3875 3876 return ENOBUFS; 3877 } 3878 /* Make sure there is room in the receive chain. */ 3879 if (map->dm_nsegs > sc->free_rx_bd) { 3880 bus_dmamap_unload(sc->bnx_dmatag, map); 3881 m_freem(m_new); 3882 return EFBIG; 3883 } 3884 #ifdef BNX_DEBUG 3885 /* Track the distribution of buffer segments. */ 3886 sc->rx_mbuf_segs[map->dm_nsegs]++; 3887 #endif 3888 3889 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3890 BUS_DMASYNC_PREREAD); 3891 3892 /* Update some debug statistics counters */ 3893 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3894 sc->rx_low_watermark = sc->free_rx_bd); 3895 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3896 3897 /* 3898 * Setup the rx_bd for the first segment 3899 */ 3900 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3901 3902 addr = (uint32_t)map->dm_segs[0].ds_addr; 3903 rxbd->rx_bd_haddr_lo = addr; 3904 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3905 rxbd->rx_bd_haddr_hi = addr; 3906 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3907 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3908 *prod_bseq += map->dm_segs[0].ds_len; 3909 bus_dmamap_sync(sc->bnx_dmatag, 3910 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3911 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3912 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3913 3914 for (i = 1; i < map->dm_nsegs; i++) { 3915 *prod = NEXT_RX_BD(*prod); 3916 *chain_prod = RX_CHAIN_IDX(*prod); 3917 3918 rxbd = 3919 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3920 3921 addr = (uint32_t)map->dm_segs[i].ds_addr; 3922 rxbd->rx_bd_haddr_lo = addr; 3923 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3924 rxbd->rx_bd_haddr_hi = addr; 3925 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3926 rxbd->rx_bd_flags = 0; 3927 *prod_bseq += map->dm_segs[i].ds_len; 3928 bus_dmamap_sync(sc->bnx_dmatag, 3929 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3930 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3931 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3932 } 3933 3934 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3935 bus_dmamap_sync(sc->bnx_dmatag, 3936 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3937 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3938 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3939 3940 /* 3941 * Save the mbuf, adjust the map pointer (swap map for first and 3942 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3943 * and update our counter. 3944 */ 3945 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3946 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3947 sc->rx_mbuf_map[*chain_prod] = map; 3948 sc->free_rx_bd -= map->dm_nsegs; 3949 3950 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3951 map->dm_nsegs)); 3952 *prod = NEXT_RX_BD(*prod); 3953 *chain_prod = RX_CHAIN_IDX(*prod); 3954 3955 return 0; 3956 } 3957 3958 /****************************************************************************/ 3959 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3960 /* */ 3961 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3962 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3963 /* necessary. */ 3964 /* */ 3965 /* Returns: */ 3966 /* 0 for success, positive value for failure. */ 3967 /****************************************************************************/ 3968 int 3969 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3970 uint16_t *chain_prod, uint32_t *prod_bseq) 3971 { 3972 struct mbuf *m_new = NULL; 3973 int rc = 0; 3974 uint16_t min_free_bd; 3975 3976 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3977 __func__); 3978 3979 /* Make sure the inputs are valid. */ 3980 DBRUNIF((*chain_prod > MAX_RX_BD), 3981 aprint_error_dev(sc->bnx_dev, 3982 "RX producer out of range: 0x%04X > 0x%04X\n", 3983 *chain_prod, (uint16_t)MAX_RX_BD)); 3984 3985 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3986 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3987 *prod_bseq); 3988 3989 /* try to get in as many mbufs as possible */ 3990 if (sc->mbuf_alloc_size == MCLBYTES) 3991 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3992 else 3993 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 3994 while (sc->free_rx_bd >= min_free_bd) { 3995 /* Simulate an mbuf allocation failure. */ 3996 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 3997 aprint_error_dev(sc->bnx_dev, 3998 "Simulating mbuf allocation failure.\n"); 3999 sc->mbuf_sim_alloc_failed++; 4000 rc = ENOBUFS; 4001 goto bnx_get_buf_exit); 4002 4003 /* This is a new mbuf allocation. */ 4004 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4005 if (m_new == NULL) { 4006 DBPRINT(sc, BNX_WARN, 4007 "%s(%d): RX mbuf header allocation failed!\n", 4008 __FILE__, __LINE__); 4009 4010 sc->mbuf_alloc_failed++; 4011 4012 rc = ENOBUFS; 4013 goto bnx_get_buf_exit; 4014 } 4015 4016 DBRUNIF(1, sc->rx_mbuf_alloc++); 4017 4018 /* Simulate an mbuf cluster allocation failure. */ 4019 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4020 m_freem(m_new); 4021 sc->rx_mbuf_alloc--; 4022 sc->mbuf_alloc_failed++; 4023 sc->mbuf_sim_alloc_failed++; 4024 rc = ENOBUFS; 4025 goto bnx_get_buf_exit); 4026 4027 if (sc->mbuf_alloc_size == MCLBYTES) 4028 MCLGET(m_new, M_DONTWAIT); 4029 else 4030 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 4031 M_DONTWAIT); 4032 if (!(m_new->m_flags & M_EXT)) { 4033 DBPRINT(sc, BNX_WARN, 4034 "%s(%d): RX mbuf chain allocation failed!\n", 4035 __FILE__, __LINE__); 4036 4037 m_freem(m_new); 4038 4039 DBRUNIF(1, sc->rx_mbuf_alloc--); 4040 sc->mbuf_alloc_failed++; 4041 4042 rc = ENOBUFS; 4043 goto bnx_get_buf_exit; 4044 } 4045 4046 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 4047 if (rc != 0) 4048 goto bnx_get_buf_exit; 4049 } 4050 4051 bnx_get_buf_exit: 4052 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 4053 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 4054 *chain_prod, *prod_bseq); 4055 4056 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 4057 __func__); 4058 4059 return rc; 4060 } 4061 4062 void 4063 bnx_alloc_pkts(struct work * unused, void * arg) 4064 { 4065 struct bnx_softc *sc = arg; 4066 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4067 struct bnx_pkt *pkt; 4068 int i, s; 4069 4070 for (i = 0; i < 4; i++) { /* magic! */ 4071 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 4072 if (pkt == NULL) 4073 break; 4074 4075 if (bus_dmamap_create(sc->bnx_dmatag, 4076 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4077 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4078 &pkt->pkt_dmamap) != 0) 4079 goto put; 4080 4081 if (!ISSET(ifp->if_flags, IFF_UP)) 4082 goto stopping; 4083 4084 mutex_enter(&sc->tx_pkt_mtx); 4085 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4086 sc->tx_pkt_count++; 4087 mutex_exit(&sc->tx_pkt_mtx); 4088 } 4089 4090 mutex_enter(&sc->tx_pkt_mtx); 4091 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4092 mutex_exit(&sc->tx_pkt_mtx); 4093 4094 /* fire-up TX now that allocations have been done */ 4095 s = splnet(); 4096 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4097 bnx_start(ifp); 4098 splx(s); 4099 4100 return; 4101 4102 stopping: 4103 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4104 put: 4105 pool_put(bnx_tx_pool, pkt); 4106 return; 4107 } 4108 4109 /****************************************************************************/ 4110 /* Initialize the TX context memory. */ 4111 /* */ 4112 /* Returns: */ 4113 /* Nothing */ 4114 /****************************************************************************/ 4115 void 4116 bnx_init_tx_context(struct bnx_softc *sc) 4117 { 4118 uint32_t val; 4119 4120 /* Initialize the context ID for an L2 TX chain. */ 4121 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4122 /* Set the CID type to support an L2 connection. */ 4123 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4124 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4125 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4126 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4127 4128 /* Point the hardware to the first page in the chain. */ 4129 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4130 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4131 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4132 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4133 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4134 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4135 } else { 4136 /* Set the CID type to support an L2 connection. */ 4137 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4138 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4139 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4140 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4141 4142 /* Point the hardware to the first page in the chain. */ 4143 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4144 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4145 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4146 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4147 } 4148 } 4149 4150 4151 /****************************************************************************/ 4152 /* Allocate memory and initialize the TX data structures. */ 4153 /* */ 4154 /* Returns: */ 4155 /* 0 for success, positive value for failure. */ 4156 /****************************************************************************/ 4157 int 4158 bnx_init_tx_chain(struct bnx_softc *sc) 4159 { 4160 struct tx_bd *txbd; 4161 uint32_t addr; 4162 int i, rc = 0; 4163 4164 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4165 4166 /* Force an allocation of some dmamaps for tx up front */ 4167 bnx_alloc_pkts(NULL, sc); 4168 4169 /* Set the initial TX producer/consumer indices. */ 4170 sc->tx_prod = 0; 4171 sc->tx_cons = 0; 4172 sc->tx_prod_bseq = 0; 4173 sc->used_tx_bd = 0; 4174 sc->max_tx_bd = USABLE_TX_BD; 4175 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4176 DBRUNIF(1, sc->tx_full_count = 0); 4177 4178 /* 4179 * The NetXtreme II supports a linked-list structure called 4180 * a Buffer Descriptor Chain (or BD chain). A BD chain 4181 * consists of a series of 1 or more chain pages, each of which 4182 * consists of a fixed number of BD entries. 4183 * The last BD entry on each page is a pointer to the next page 4184 * in the chain, and the last pointer in the BD chain 4185 * points back to the beginning of the chain. 4186 */ 4187 4188 /* Set the TX next pointer chain entries. */ 4189 for (i = 0; i < TX_PAGES; i++) { 4190 int j; 4191 4192 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4193 4194 /* Check if we've reached the last page. */ 4195 if (i == (TX_PAGES - 1)) 4196 j = 0; 4197 else 4198 j = i + 1; 4199 4200 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4201 txbd->tx_bd_haddr_lo = addr; 4202 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4203 txbd->tx_bd_haddr_hi = addr; 4204 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4205 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4206 } 4207 4208 /* 4209 * Initialize the context ID for an L2 TX chain. 4210 */ 4211 bnx_init_tx_context(sc); 4212 4213 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4214 4215 return rc; 4216 } 4217 4218 /****************************************************************************/ 4219 /* Free memory and clear the TX data structures. */ 4220 /* */ 4221 /* Returns: */ 4222 /* Nothing. */ 4223 /****************************************************************************/ 4224 void 4225 bnx_free_tx_chain(struct bnx_softc *sc) 4226 { 4227 struct bnx_pkt *pkt; 4228 int i; 4229 4230 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4231 4232 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4233 mutex_enter(&sc->tx_pkt_mtx); 4234 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4235 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4236 mutex_exit(&sc->tx_pkt_mtx); 4237 4238 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4239 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4240 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4241 4242 m_freem(pkt->pkt_mbuf); 4243 DBRUNIF(1, sc->tx_mbuf_alloc--); 4244 4245 mutex_enter(&sc->tx_pkt_mtx); 4246 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4247 } 4248 4249 /* Destroy all the dmamaps we allocated for TX */ 4250 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 4251 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 4252 sc->tx_pkt_count--; 4253 mutex_exit(&sc->tx_pkt_mtx); 4254 4255 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4256 pool_put(bnx_tx_pool, pkt); 4257 4258 mutex_enter(&sc->tx_pkt_mtx); 4259 } 4260 mutex_exit(&sc->tx_pkt_mtx); 4261 4262 4263 4264 /* Clear each TX chain page. */ 4265 for (i = 0; i < TX_PAGES; i++) { 4266 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4267 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4268 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4269 } 4270 4271 sc->used_tx_bd = 0; 4272 4273 /* Check if we lost any mbufs in the process. */ 4274 DBRUNIF((sc->tx_mbuf_alloc), 4275 aprint_error_dev(sc->bnx_dev, 4276 "Memory leak! Lost %d mbufs from tx chain!\n", 4277 sc->tx_mbuf_alloc)); 4278 4279 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4280 } 4281 4282 /****************************************************************************/ 4283 /* Initialize the RX context memory. */ 4284 /* */ 4285 /* Returns: */ 4286 /* Nothing */ 4287 /****************************************************************************/ 4288 void 4289 bnx_init_rx_context(struct bnx_softc *sc) 4290 { 4291 uint32_t val; 4292 4293 /* Initialize the context ID for an L2 RX chain. */ 4294 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4295 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4296 4297 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4298 val |= 0x000000ff; 4299 4300 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4301 4302 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4303 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4304 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4305 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4306 } 4307 4308 /* Point the hardware to the first page in the chain. */ 4309 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4310 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4311 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4312 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4313 } 4314 4315 /****************************************************************************/ 4316 /* Allocate memory and initialize the RX data structures. */ 4317 /* */ 4318 /* Returns: */ 4319 /* 0 for success, positive value for failure. */ 4320 /****************************************************************************/ 4321 int 4322 bnx_init_rx_chain(struct bnx_softc *sc) 4323 { 4324 struct rx_bd *rxbd; 4325 int i, rc = 0; 4326 uint16_t prod, chain_prod; 4327 uint32_t prod_bseq, addr; 4328 4329 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4330 4331 /* Initialize the RX producer and consumer indices. */ 4332 sc->rx_prod = 0; 4333 sc->rx_cons = 0; 4334 sc->rx_prod_bseq = 0; 4335 sc->free_rx_bd = USABLE_RX_BD; 4336 sc->max_rx_bd = USABLE_RX_BD; 4337 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4338 DBRUNIF(1, sc->rx_empty_count = 0); 4339 4340 /* Initialize the RX next pointer chain entries. */ 4341 for (i = 0; i < RX_PAGES; i++) { 4342 int j; 4343 4344 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4345 4346 /* Check if we've reached the last page. */ 4347 if (i == (RX_PAGES - 1)) 4348 j = 0; 4349 else 4350 j = i + 1; 4351 4352 /* Setup the chain page pointers. */ 4353 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4354 rxbd->rx_bd_haddr_hi = addr; 4355 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4356 rxbd->rx_bd_haddr_lo = addr; 4357 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4358 0, BNX_RX_CHAIN_PAGE_SZ, 4359 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4360 } 4361 4362 /* Allocate mbuf clusters for the rx_bd chain. */ 4363 prod = prod_bseq = 0; 4364 chain_prod = RX_CHAIN_IDX(prod); 4365 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4366 BNX_PRINTF(sc, 4367 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4368 } 4369 4370 /* Save the RX chain producer index. */ 4371 sc->rx_prod = prod; 4372 sc->rx_prod_bseq = prod_bseq; 4373 4374 for (i = 0; i < RX_PAGES; i++) 4375 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4376 sc->rx_bd_chain_map[i]->dm_mapsize, 4377 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4378 4379 /* Tell the chip about the waiting rx_bd's. */ 4380 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4381 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4382 4383 bnx_init_rx_context(sc); 4384 4385 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4386 4387 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4388 4389 return rc; 4390 } 4391 4392 /****************************************************************************/ 4393 /* Free memory and clear the RX data structures. */ 4394 /* */ 4395 /* Returns: */ 4396 /* Nothing. */ 4397 /****************************************************************************/ 4398 void 4399 bnx_free_rx_chain(struct bnx_softc *sc) 4400 { 4401 int i; 4402 4403 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4404 4405 /* Free any mbufs still in the RX mbuf chain. */ 4406 for (i = 0; i < TOTAL_RX_BD; i++) { 4407 if (sc->rx_mbuf_ptr[i] != NULL) { 4408 if (sc->rx_mbuf_map[i] != NULL) { 4409 bus_dmamap_sync(sc->bnx_dmatag, 4410 sc->rx_mbuf_map[i], 0, 4411 sc->rx_mbuf_map[i]->dm_mapsize, 4412 BUS_DMASYNC_POSTREAD); 4413 bus_dmamap_unload(sc->bnx_dmatag, 4414 sc->rx_mbuf_map[i]); 4415 } 4416 m_freem(sc->rx_mbuf_ptr[i]); 4417 sc->rx_mbuf_ptr[i] = NULL; 4418 DBRUNIF(1, sc->rx_mbuf_alloc--); 4419 } 4420 } 4421 4422 /* Clear each RX chain page. */ 4423 for (i = 0; i < RX_PAGES; i++) 4424 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4425 4426 sc->free_rx_bd = sc->max_rx_bd; 4427 4428 /* Check if we lost any mbufs in the process. */ 4429 DBRUNIF((sc->rx_mbuf_alloc), 4430 aprint_error_dev(sc->bnx_dev, 4431 "Memory leak! Lost %d mbufs from rx chain!\n", 4432 sc->rx_mbuf_alloc)); 4433 4434 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4435 } 4436 4437 /****************************************************************************/ 4438 /* Set media options. */ 4439 /* */ 4440 /* Returns: */ 4441 /* 0 for success, positive value for failure. */ 4442 /****************************************************************************/ 4443 int 4444 bnx_ifmedia_upd(struct ifnet *ifp) 4445 { 4446 struct bnx_softc *sc; 4447 struct mii_data *mii; 4448 int rc = 0; 4449 4450 sc = ifp->if_softc; 4451 4452 mii = &sc->bnx_mii; 4453 sc->bnx_link = 0; 4454 if (mii->mii_instance) { 4455 struct mii_softc *miisc; 4456 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4457 mii_phy_reset(miisc); 4458 } 4459 mii_mediachg(mii); 4460 4461 return rc; 4462 } 4463 4464 /****************************************************************************/ 4465 /* Reports current media status. */ 4466 /* */ 4467 /* Returns: */ 4468 /* Nothing. */ 4469 /****************************************************************************/ 4470 void 4471 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4472 { 4473 struct bnx_softc *sc; 4474 struct mii_data *mii; 4475 int s; 4476 4477 sc = ifp->if_softc; 4478 4479 s = splnet(); 4480 4481 mii = &sc->bnx_mii; 4482 4483 mii_pollstat(mii); 4484 ifmr->ifm_status = mii->mii_media_status; 4485 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4486 sc->bnx_flowflags; 4487 4488 splx(s); 4489 } 4490 4491 /****************************************************************************/ 4492 /* Handles PHY generated interrupt events. */ 4493 /* */ 4494 /* Returns: */ 4495 /* Nothing. */ 4496 /****************************************************************************/ 4497 void 4498 bnx_phy_intr(struct bnx_softc *sc) 4499 { 4500 uint32_t new_link_state, old_link_state; 4501 4502 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4503 BUS_DMASYNC_POSTREAD); 4504 new_link_state = sc->status_block->status_attn_bits & 4505 STATUS_ATTN_BITS_LINK_STATE; 4506 old_link_state = sc->status_block->status_attn_bits_ack & 4507 STATUS_ATTN_BITS_LINK_STATE; 4508 4509 /* Handle any changes if the link state has changed. */ 4510 if (new_link_state != old_link_state) { 4511 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4512 4513 sc->bnx_link = 0; 4514 callout_stop(&sc->bnx_timeout); 4515 bnx_tick(sc); 4516 4517 /* Update the status_attn_bits_ack field in the status block. */ 4518 if (new_link_state) { 4519 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4520 STATUS_ATTN_BITS_LINK_STATE); 4521 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4522 } else { 4523 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4524 STATUS_ATTN_BITS_LINK_STATE); 4525 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4526 } 4527 } 4528 4529 /* Acknowledge the link change interrupt. */ 4530 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4531 } 4532 4533 /****************************************************************************/ 4534 /* Handles received frame interrupt events. */ 4535 /* */ 4536 /* Returns: */ 4537 /* Nothing. */ 4538 /****************************************************************************/ 4539 void 4540 bnx_rx_intr(struct bnx_softc *sc) 4541 { 4542 struct status_block *sblk = sc->status_block; 4543 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4544 uint16_t hw_cons, sw_cons, sw_chain_cons; 4545 uint16_t sw_prod, sw_chain_prod; 4546 uint32_t sw_prod_bseq; 4547 struct l2_fhdr *l2fhdr; 4548 int i; 4549 4550 DBRUNIF(1, sc->rx_interrupts++); 4551 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4552 BUS_DMASYNC_POSTREAD); 4553 4554 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4555 for (i = 0; i < RX_PAGES; i++) 4556 bus_dmamap_sync(sc->bnx_dmatag, 4557 sc->rx_bd_chain_map[i], 0, 4558 sc->rx_bd_chain_map[i]->dm_mapsize, 4559 BUS_DMASYNC_POSTWRITE); 4560 4561 /* Get the hardware's view of the RX consumer index. */ 4562 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4563 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4564 hw_cons++; 4565 4566 /* Get working copies of the driver's view of the RX indices. */ 4567 sw_cons = sc->rx_cons; 4568 sw_prod = sc->rx_prod; 4569 sw_prod_bseq = sc->rx_prod_bseq; 4570 4571 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4572 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4573 __func__, sw_prod, sw_cons, sw_prod_bseq); 4574 4575 /* Prevent speculative reads from getting ahead of the status block. */ 4576 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4577 BUS_SPACE_BARRIER_READ); 4578 4579 /* Update some debug statistics counters */ 4580 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4581 sc->rx_low_watermark = sc->free_rx_bd); 4582 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4583 4584 /* 4585 * Scan through the receive chain as long 4586 * as there is work to do. 4587 */ 4588 while (sw_cons != hw_cons) { 4589 struct mbuf *m; 4590 struct rx_bd *rxbd __diagused; 4591 unsigned int len; 4592 uint32_t status; 4593 4594 /* Convert the producer/consumer indices to an actual 4595 * rx_bd index. 4596 */ 4597 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4598 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4599 4600 /* Get the used rx_bd. */ 4601 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4602 sc->free_rx_bd++; 4603 4604 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4605 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4606 4607 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4608 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4609 #ifdef DIAGNOSTIC 4610 /* Validate that this is the last rx_bd. */ 4611 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4612 printf("%s: Unexpected mbuf found in " 4613 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4614 sw_chain_cons); 4615 } 4616 #endif 4617 4618 /* DRC - ToDo: If the received packet is small, say 4619 * less than 128 bytes, allocate a new mbuf 4620 * here, copy the data to that mbuf, and 4621 * recycle the mapped jumbo frame. 4622 */ 4623 4624 /* Unmap the mbuf from DMA space. */ 4625 #ifdef DIAGNOSTIC 4626 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4627 printf("invalid map sw_cons 0x%x " 4628 "sw_prod 0x%x " 4629 "sw_chain_cons 0x%x " 4630 "sw_chain_prod 0x%x " 4631 "hw_cons 0x%x " 4632 "TOTAL_RX_BD_PER_PAGE 0x%x " 4633 "TOTAL_RX_BD 0x%x\n", 4634 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4635 hw_cons, 4636 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4637 } 4638 #endif 4639 bus_dmamap_sync(sc->bnx_dmatag, 4640 sc->rx_mbuf_map[sw_chain_cons], 0, 4641 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4642 BUS_DMASYNC_POSTREAD); 4643 bus_dmamap_unload(sc->bnx_dmatag, 4644 sc->rx_mbuf_map[sw_chain_cons]); 4645 4646 /* Remove the mbuf from the driver's chain. */ 4647 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4648 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4649 4650 /* 4651 * Frames received on the NetXteme II are prepended 4652 * with the l2_fhdr structure which provides status 4653 * information about the received frame (including 4654 * VLAN tags and checksum info) and are also 4655 * automatically adjusted to align the IP header 4656 * (i.e. two null bytes are inserted before the 4657 * Ethernet header). 4658 */ 4659 l2fhdr = mtod(m, struct l2_fhdr *); 4660 4661 len = l2fhdr->l2_fhdr_pkt_len; 4662 status = l2fhdr->l2_fhdr_status; 4663 4664 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4665 aprint_error("Simulating l2_fhdr status error.\n"); 4666 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4667 4668 /* Watch for unusual sized frames. */ 4669 DBRUNIF(((len < BNX_MIN_MTU) || 4670 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4671 aprint_error_dev(sc->bnx_dev, 4672 "Unusual frame size found. " 4673 "Min(%d), Actual(%d), Max(%d)\n", 4674 (int)BNX_MIN_MTU, len, 4675 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4676 4677 bnx_dump_mbuf(sc, m); 4678 bnx_breakpoint(sc)); 4679 4680 len -= ETHER_CRC_LEN; 4681 4682 /* Check the received frame for errors. */ 4683 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4684 L2_FHDR_ERRORS_PHY_DECODE | 4685 L2_FHDR_ERRORS_ALIGNMENT | 4686 L2_FHDR_ERRORS_TOO_SHORT | 4687 L2_FHDR_ERRORS_GIANT_FRAME)) || 4688 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4689 len > 4690 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4691 if_statinc(ifp, if_ierrors); 4692 DBRUNIF(1, sc->l2fhdr_status_errors++); 4693 4694 /* Reuse the mbuf for a new frame. */ 4695 if (bnx_add_buf(sc, m, &sw_prod, 4696 &sw_chain_prod, &sw_prod_bseq)) { 4697 DBRUNIF(1, bnx_breakpoint(sc)); 4698 panic("%s: Can't reuse RX mbuf!\n", 4699 device_xname(sc->bnx_dev)); 4700 } 4701 continue; 4702 } 4703 4704 /* 4705 * Get a new mbuf for the rx_bd. If no new 4706 * mbufs are available then reuse the current mbuf, 4707 * log an ierror on the interface, and generate 4708 * an error in the system log. 4709 */ 4710 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4711 &sw_prod_bseq)) { 4712 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4713 "Failed to allocate " 4714 "new mbuf, incoming frame dropped!\n")); 4715 4716 if_statinc(ifp, if_ierrors); 4717 4718 /* Try and reuse the exisitng mbuf. */ 4719 if (bnx_add_buf(sc, m, &sw_prod, 4720 &sw_chain_prod, &sw_prod_bseq)) { 4721 DBRUNIF(1, bnx_breakpoint(sc)); 4722 panic("%s: Double mbuf allocation " 4723 "failure!", 4724 device_xname(sc->bnx_dev)); 4725 } 4726 continue; 4727 } 4728 4729 /* Skip over the l2_fhdr when passing the data up 4730 * the stack. 4731 */ 4732 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4733 4734 /* Adjust the pckt length to match the received data. */ 4735 m->m_pkthdr.len = m->m_len = len; 4736 4737 /* Send the packet to the appropriate interface. */ 4738 m_set_rcvif(m, ifp); 4739 4740 DBRUN(BNX_VERBOSE_RECV, 4741 struct ether_header *eh; 4742 eh = mtod(m, struct ether_header *); 4743 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4744 __func__, ether_sprintf(eh->ether_dhost), 4745 ether_sprintf(eh->ether_shost), 4746 htons(eh->ether_type))); 4747 4748 /* Validate the checksum. */ 4749 4750 /* Check for an IP datagram. */ 4751 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4752 /* Check if the IP checksum is valid. */ 4753 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4754 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4755 #ifdef BNX_DEBUG 4756 else 4757 DBPRINT(sc, BNX_WARN_SEND, 4758 "%s(): Invalid IP checksum " 4759 "= 0x%04X!\n", 4760 __func__, 4761 l2fhdr->l2_fhdr_ip_xsum 4762 ); 4763 #endif 4764 } 4765 4766 /* Check for a valid TCP/UDP frame. */ 4767 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4768 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4769 /* Check for a good TCP/UDP checksum. */ 4770 if ((status & 4771 (L2_FHDR_ERRORS_TCP_XSUM | 4772 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4773 m->m_pkthdr.csum_flags |= 4774 M_CSUM_TCPv4 | 4775 M_CSUM_UDPv4; 4776 } else { 4777 DBPRINT(sc, BNX_WARN_SEND, 4778 "%s(): Invalid TCP/UDP " 4779 "checksum = 0x%04X!\n", 4780 __func__, 4781 l2fhdr->l2_fhdr_tcp_udp_xsum); 4782 } 4783 } 4784 4785 /* 4786 * If we received a packet with a vlan tag, 4787 * attach that information to the packet. 4788 */ 4789 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4790 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4791 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4792 } 4793 4794 /* Pass the mbuf off to the upper layers. */ 4795 4796 DBPRINT(sc, BNX_VERBOSE_RECV, 4797 "%s(): Passing received frame up.\n", __func__); 4798 if_percpuq_enqueue(ifp->if_percpuq, m); 4799 DBRUNIF(1, sc->rx_mbuf_alloc--); 4800 4801 } 4802 4803 sw_cons = NEXT_RX_BD(sw_cons); 4804 4805 /* Refresh hw_cons to see if there's new work */ 4806 if (sw_cons == hw_cons) { 4807 hw_cons = sc->hw_rx_cons = 4808 sblk->status_rx_quick_consumer_index0; 4809 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4810 USABLE_RX_BD_PER_PAGE) 4811 hw_cons++; 4812 } 4813 4814 /* Prevent speculative reads from getting ahead of 4815 * the status block. 4816 */ 4817 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4818 BUS_SPACE_BARRIER_READ); 4819 } 4820 4821 for (i = 0; i < RX_PAGES; i++) 4822 bus_dmamap_sync(sc->bnx_dmatag, 4823 sc->rx_bd_chain_map[i], 0, 4824 sc->rx_bd_chain_map[i]->dm_mapsize, 4825 BUS_DMASYNC_PREWRITE); 4826 4827 sc->rx_cons = sw_cons; 4828 sc->rx_prod = sw_prod; 4829 sc->rx_prod_bseq = sw_prod_bseq; 4830 4831 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4832 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4833 4834 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4835 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4836 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4837 } 4838 4839 /****************************************************************************/ 4840 /* Handles transmit completion interrupt events. */ 4841 /* */ 4842 /* Returns: */ 4843 /* Nothing. */ 4844 /****************************************************************************/ 4845 void 4846 bnx_tx_intr(struct bnx_softc *sc) 4847 { 4848 struct status_block *sblk = sc->status_block; 4849 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4850 struct bnx_pkt *pkt; 4851 bus_dmamap_t map; 4852 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4853 4854 DBRUNIF(1, sc->tx_interrupts++); 4855 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4856 BUS_DMASYNC_POSTREAD); 4857 4858 /* Get the hardware's view of the TX consumer index. */ 4859 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4860 4861 /* Skip to the next entry if this is a chain page pointer. */ 4862 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4863 hw_tx_cons++; 4864 4865 sw_tx_cons = sc->tx_cons; 4866 4867 /* Prevent speculative reads from getting ahead of the status block. */ 4868 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4869 BUS_SPACE_BARRIER_READ); 4870 4871 /* Cycle through any completed TX chain page entries. */ 4872 while (sw_tx_cons != hw_tx_cons) { 4873 #ifdef BNX_DEBUG 4874 struct tx_bd *txbd = NULL; 4875 #endif 4876 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4877 4878 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4879 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4880 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4881 4882 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4883 aprint_error_dev(sc->bnx_dev, 4884 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4885 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4886 4887 DBRUNIF(1, txbd = &sc->tx_bd_chain 4888 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4889 4890 DBRUNIF((txbd == NULL), 4891 aprint_error_dev(sc->bnx_dev, 4892 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4893 bnx_breakpoint(sc)); 4894 4895 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4896 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4897 4898 4899 mutex_enter(&sc->tx_pkt_mtx); 4900 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4901 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4902 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4903 mutex_exit(&sc->tx_pkt_mtx); 4904 /* 4905 * Free the associated mbuf. Remember 4906 * that only the last tx_bd of a packet 4907 * has an mbuf pointer and DMA map. 4908 */ 4909 map = pkt->pkt_dmamap; 4910 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4911 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4912 bus_dmamap_unload(sc->bnx_dmatag, map); 4913 4914 m_freem(pkt->pkt_mbuf); 4915 DBRUNIF(1, sc->tx_mbuf_alloc--); 4916 4917 if_statinc(ifp, if_opackets); 4918 4919 mutex_enter(&sc->tx_pkt_mtx); 4920 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4921 } 4922 mutex_exit(&sc->tx_pkt_mtx); 4923 4924 sc->used_tx_bd--; 4925 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4926 __FILE__, __LINE__, sc->used_tx_bd); 4927 4928 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4929 4930 /* Refresh hw_cons to see if there's new work. */ 4931 hw_tx_cons = sc->hw_tx_cons = 4932 sblk->status_tx_quick_consumer_index0; 4933 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4934 USABLE_TX_BD_PER_PAGE) 4935 hw_tx_cons++; 4936 4937 /* Prevent speculative reads from getting ahead of 4938 * the status block. 4939 */ 4940 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4941 BUS_SPACE_BARRIER_READ); 4942 } 4943 4944 /* Clear the TX timeout timer. */ 4945 ifp->if_timer = 0; 4946 4947 /* Clear the tx hardware queue full flag. */ 4948 if (sc->used_tx_bd < sc->max_tx_bd) { 4949 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4950 aprint_debug_dev(sc->bnx_dev, 4951 "Open TX chain! %d/%d (used/total)\n", 4952 sc->used_tx_bd, sc->max_tx_bd)); 4953 ifp->if_flags &= ~IFF_OACTIVE; 4954 } 4955 4956 sc->tx_cons = sw_tx_cons; 4957 } 4958 4959 /****************************************************************************/ 4960 /* Disables interrupt generation. */ 4961 /* */ 4962 /* Returns: */ 4963 /* Nothing. */ 4964 /****************************************************************************/ 4965 void 4966 bnx_disable_intr(struct bnx_softc *sc) 4967 { 4968 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4969 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4970 } 4971 4972 /****************************************************************************/ 4973 /* Enables interrupt generation. */ 4974 /* */ 4975 /* Returns: */ 4976 /* Nothing. */ 4977 /****************************************************************************/ 4978 void 4979 bnx_enable_intr(struct bnx_softc *sc) 4980 { 4981 uint32_t val; 4982 4983 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4984 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4985 4986 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4987 sc->last_status_idx); 4988 4989 val = REG_RD(sc, BNX_HC_COMMAND); 4990 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4991 } 4992 4993 /****************************************************************************/ 4994 /* Handles controller initialization. */ 4995 /* */ 4996 /****************************************************************************/ 4997 int 4998 bnx_init(struct ifnet *ifp) 4999 { 5000 struct bnx_softc *sc = ifp->if_softc; 5001 uint32_t ether_mtu; 5002 int s, error = 0; 5003 5004 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 5005 5006 s = splnet(); 5007 5008 bnx_stop(ifp, 0); 5009 5010 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 5011 aprint_error_dev(sc->bnx_dev, 5012 "Controller reset failed!\n"); 5013 goto bnx_init_exit; 5014 } 5015 5016 if ((error = bnx_chipinit(sc)) != 0) { 5017 aprint_error_dev(sc->bnx_dev, 5018 "Controller initialization failed!\n"); 5019 goto bnx_init_exit; 5020 } 5021 5022 if ((error = bnx_blockinit(sc)) != 0) { 5023 aprint_error_dev(sc->bnx_dev, 5024 "Block initialization failed!\n"); 5025 goto bnx_init_exit; 5026 } 5027 5028 /* Calculate and program the Ethernet MRU size. */ 5029 if (ifp->if_mtu <= ETHERMTU) { 5030 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 5031 sc->mbuf_alloc_size = MCLBYTES; 5032 } else { 5033 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 5034 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 5035 } 5036 5037 5038 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 5039 5040 /* 5041 * Program the MRU and enable Jumbo frame 5042 * support. 5043 */ 5044 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 5045 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 5046 5047 /* Calculate the RX Ethernet frame size for rx_bd's. */ 5048 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 5049 5050 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 5051 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 5052 sc->mbuf_alloc_size, sc->max_frame_size); 5053 5054 /* Program appropriate promiscuous/multicast filtering. */ 5055 bnx_iff(sc); 5056 5057 /* Init RX buffer descriptor chain. */ 5058 bnx_init_rx_chain(sc); 5059 5060 /* Init TX buffer descriptor chain. */ 5061 bnx_init_tx_chain(sc); 5062 5063 /* Enable host interrupts. */ 5064 bnx_enable_intr(sc); 5065 5066 mii_ifmedia_change(&sc->bnx_mii); 5067 5068 SET(ifp->if_flags, IFF_RUNNING); 5069 CLR(ifp->if_flags, IFF_OACTIVE); 5070 5071 callout_schedule(&sc->bnx_timeout, hz); 5072 5073 bnx_init_exit: 5074 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5075 5076 splx(s); 5077 5078 return error; 5079 } 5080 5081 void 5082 bnx_mgmt_init(struct bnx_softc *sc) 5083 { 5084 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5085 uint32_t val; 5086 5087 /* Check if the driver is still running and bail out if it is. */ 5088 if (ifp->if_flags & IFF_RUNNING) 5089 goto bnx_mgmt_init_exit; 5090 5091 /* Initialize the on-boards CPUs */ 5092 bnx_init_cpus(sc); 5093 5094 val = (BCM_PAGE_BITS - 8) << 24; 5095 REG_WR(sc, BNX_RV2P_CONFIG, val); 5096 5097 /* Enable all critical blocks in the MAC. */ 5098 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5099 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5100 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5101 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5102 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5103 DELAY(20); 5104 5105 mii_ifmedia_change(&sc->bnx_mii); 5106 5107 bnx_mgmt_init_exit: 5108 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5109 } 5110 5111 /****************************************************************************/ 5112 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5113 /* memory visible to the controller. */ 5114 /* */ 5115 /* Returns: */ 5116 /* 0 for success, positive value for failure. */ 5117 /****************************************************************************/ 5118 int 5119 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5120 { 5121 struct bnx_pkt *pkt; 5122 bus_dmamap_t map; 5123 struct tx_bd *txbd = NULL; 5124 uint16_t vlan_tag = 0, flags = 0; 5125 uint16_t chain_prod, prod; 5126 #ifdef BNX_DEBUG 5127 uint16_t debug_prod; 5128 #endif 5129 uint32_t addr, prod_bseq; 5130 int i, error; 5131 static struct work bnx_wk; /* Dummy work. Statically allocated. */ 5132 bool remap = true; 5133 5134 mutex_enter(&sc->tx_pkt_mtx); 5135 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5136 if (pkt == NULL) { 5137 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5138 mutex_exit(&sc->tx_pkt_mtx); 5139 return ENETDOWN; 5140 } 5141 5142 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5143 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5144 workqueue_enqueue(sc->bnx_wq, &bnx_wk, NULL); 5145 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5146 } 5147 5148 mutex_exit(&sc->tx_pkt_mtx); 5149 return ENOMEM; 5150 } 5151 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5152 mutex_exit(&sc->tx_pkt_mtx); 5153 5154 /* Transfer any checksum offload flags to the bd. */ 5155 if (m->m_pkthdr.csum_flags) { 5156 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5157 flags |= TX_BD_FLAGS_IP_CKSUM; 5158 if (m->m_pkthdr.csum_flags & 5159 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5160 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5161 } 5162 5163 /* Transfer any VLAN tags to the bd. */ 5164 if (vlan_has_tag(m)) { 5165 flags |= TX_BD_FLAGS_VLAN_TAG; 5166 vlan_tag = vlan_get_tag(m); 5167 } 5168 5169 /* Map the mbuf into DMAable memory. */ 5170 prod = sc->tx_prod; 5171 chain_prod = TX_CHAIN_IDX(prod); 5172 map = pkt->pkt_dmamap; 5173 5174 /* Map the mbuf into our DMA address space. */ 5175 retry: 5176 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5177 if (__predict_false(error)) { 5178 if (error == EFBIG) { 5179 if (remap == true) { 5180 struct mbuf *newm; 5181 5182 remap = false; 5183 newm = m_defrag(m, M_NOWAIT); 5184 if (newm != NULL) { 5185 m = newm; 5186 goto retry; 5187 } 5188 } 5189 } 5190 sc->tx_dma_map_failures++; 5191 goto maperr; 5192 } 5193 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5194 BUS_DMASYNC_PREWRITE); 5195 /* Make sure there's room in the chain */ 5196 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5197 goto nospace; 5198 5199 /* prod points to an empty tx_bd at this point. */ 5200 prod_bseq = sc->tx_prod_bseq; 5201 #ifdef BNX_DEBUG 5202 debug_prod = chain_prod; 5203 #endif 5204 DBPRINT(sc, BNX_INFO_SEND, 5205 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5206 "prod_bseq = 0x%08X\n", 5207 __func__, prod, chain_prod, prod_bseq); 5208 5209 /* 5210 * Cycle through each mbuf segment that makes up 5211 * the outgoing frame, gathering the mapping info 5212 * for that segment and creating a tx_bd for the 5213 * mbuf. 5214 */ 5215 for (i = 0; i < map->dm_nsegs ; i++) { 5216 chain_prod = TX_CHAIN_IDX(prod); 5217 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5218 5219 addr = (uint32_t)map->dm_segs[i].ds_addr; 5220 txbd->tx_bd_haddr_lo = addr; 5221 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5222 txbd->tx_bd_haddr_hi = addr; 5223 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5224 txbd->tx_bd_vlan_tag = vlan_tag; 5225 txbd->tx_bd_flags = flags; 5226 prod_bseq += map->dm_segs[i].ds_len; 5227 if (i == 0) 5228 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5229 prod = NEXT_TX_BD(prod); 5230 } 5231 5232 /* Set the END flag on the last TX buffer descriptor. */ 5233 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5234 5235 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5236 5237 DBPRINT(sc, BNX_INFO_SEND, 5238 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5239 "prod_bseq = 0x%08X\n", 5240 __func__, prod, chain_prod, prod_bseq); 5241 5242 pkt->pkt_mbuf = m; 5243 pkt->pkt_end_desc = chain_prod; 5244 5245 mutex_enter(&sc->tx_pkt_mtx); 5246 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5247 mutex_exit(&sc->tx_pkt_mtx); 5248 5249 sc->used_tx_bd += map->dm_nsegs; 5250 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5251 __FILE__, __LINE__, sc->used_tx_bd); 5252 5253 /* Update some debug statistics counters */ 5254 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5255 sc->tx_hi_watermark = sc->used_tx_bd); 5256 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5257 DBRUNIF(1, sc->tx_mbuf_alloc++); 5258 5259 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5260 map->dm_nsegs)); 5261 5262 /* prod points to the next free tx_bd at this point. */ 5263 sc->tx_prod = prod; 5264 sc->tx_prod_bseq = prod_bseq; 5265 5266 return 0; 5267 5268 5269 nospace: 5270 bus_dmamap_unload(sc->bnx_dmatag, map); 5271 maperr: 5272 mutex_enter(&sc->tx_pkt_mtx); 5273 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5274 mutex_exit(&sc->tx_pkt_mtx); 5275 5276 return ENOMEM; 5277 } 5278 5279 /****************************************************************************/ 5280 /* Main transmit routine. */ 5281 /* */ 5282 /* Returns: */ 5283 /* Nothing. */ 5284 /****************************************************************************/ 5285 void 5286 bnx_start(struct ifnet *ifp) 5287 { 5288 struct bnx_softc *sc = ifp->if_softc; 5289 struct mbuf *m_head = NULL; 5290 int count = 0; 5291 #ifdef BNX_DEBUG 5292 uint16_t tx_chain_prod; 5293 #endif 5294 5295 /* If there's no link or the transmit queue is empty then just exit. */ 5296 if (!sc->bnx_link 5297 ||(ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) { 5298 DBPRINT(sc, BNX_INFO_SEND, 5299 "%s(): output active or device not running.\n", __func__); 5300 goto bnx_start_exit; 5301 } 5302 5303 /* prod points to the next free tx_bd. */ 5304 #ifdef BNX_DEBUG 5305 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5306 #endif 5307 5308 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5309 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5310 "used_tx %d max_tx %d\n", 5311 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5312 sc->used_tx_bd, sc->max_tx_bd); 5313 5314 /* 5315 * Keep adding entries while there is space in the ring. 5316 */ 5317 while (sc->used_tx_bd < sc->max_tx_bd) { 5318 /* Check for any frames to send. */ 5319 IFQ_POLL(&ifp->if_snd, m_head); 5320 if (m_head == NULL) 5321 break; 5322 5323 /* 5324 * Pack the data into the transmit ring. If we 5325 * don't have room, set the OACTIVE flag to wait 5326 * for the NIC to drain the chain. 5327 */ 5328 if (bnx_tx_encap(sc, m_head)) { 5329 ifp->if_flags |= IFF_OACTIVE; 5330 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5331 "business! Total tx_bd used = %d\n", 5332 sc->used_tx_bd); 5333 break; 5334 } 5335 5336 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5337 count++; 5338 5339 /* Send a copy of the frame to any BPF listeners. */ 5340 bpf_mtap(ifp, m_head, BPF_D_OUT); 5341 } 5342 5343 if (count == 0) { 5344 /* no packets were dequeued */ 5345 DBPRINT(sc, BNX_VERBOSE_SEND, 5346 "%s(): No packets were dequeued\n", __func__); 5347 goto bnx_start_exit; 5348 } 5349 5350 /* Update the driver's counters. */ 5351 #ifdef BNX_DEBUG 5352 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5353 #endif 5354 5355 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5356 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5357 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5358 5359 /* Start the transmit. */ 5360 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5361 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5362 5363 /* Set the tx timeout. */ 5364 ifp->if_timer = BNX_TX_TIMEOUT; 5365 5366 bnx_start_exit: 5367 return; 5368 } 5369 5370 /****************************************************************************/ 5371 /* Handles any IOCTL calls from the operating system. */ 5372 /* */ 5373 /* Returns: */ 5374 /* 0 for success, positive value for failure. */ 5375 /****************************************************************************/ 5376 int 5377 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5378 { 5379 struct bnx_softc *sc = ifp->if_softc; 5380 struct ifreq *ifr = (struct ifreq *) data; 5381 struct mii_data *mii = &sc->bnx_mii; 5382 int s, error = 0; 5383 5384 s = splnet(); 5385 5386 switch (command) { 5387 case SIOCSIFFLAGS: 5388 if ((error = ifioctl_common(ifp, command, data)) != 0) 5389 break; 5390 /* XXX set an ifflags callback and let ether_ioctl 5391 * handle all of this. 5392 */ 5393 if (ISSET(ifp->if_flags, IFF_UP)) { 5394 if (ifp->if_flags & IFF_RUNNING) 5395 error = ENETRESET; 5396 else 5397 bnx_init(ifp); 5398 } else if (ifp->if_flags & IFF_RUNNING) 5399 bnx_stop(ifp, 1); 5400 break; 5401 5402 case SIOCSIFMEDIA: 5403 /* Flow control requires full-duplex mode. */ 5404 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5405 (ifr->ifr_media & IFM_FDX) == 0) 5406 ifr->ifr_media &= ~IFM_ETH_FMASK; 5407 5408 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5409 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5410 /* We can do both TXPAUSE and RXPAUSE. */ 5411 ifr->ifr_media |= 5412 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5413 } 5414 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5415 } 5416 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5417 sc->bnx_phy_flags); 5418 5419 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5420 break; 5421 5422 default: 5423 error = ether_ioctl(ifp, command, data); 5424 } 5425 5426 if (error == ENETRESET) { 5427 if (ifp->if_flags & IFF_RUNNING) 5428 bnx_iff(sc); 5429 error = 0; 5430 } 5431 5432 splx(s); 5433 return error; 5434 } 5435 5436 /****************************************************************************/ 5437 /* Transmit timeout handler. */ 5438 /* */ 5439 /* Returns: */ 5440 /* Nothing. */ 5441 /****************************************************************************/ 5442 void 5443 bnx_watchdog(struct ifnet *ifp) 5444 { 5445 struct bnx_softc *sc = ifp->if_softc; 5446 5447 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5448 bnx_dump_status_block(sc)); 5449 /* 5450 * If we are in this routine because of pause frames, then 5451 * don't reset the hardware. 5452 */ 5453 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5454 return; 5455 5456 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5457 5458 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5459 5460 bnx_init(ifp); 5461 5462 if_statinc(ifp, if_oerrors); 5463 } 5464 5465 /* 5466 * Interrupt handler. 5467 */ 5468 /****************************************************************************/ 5469 /* Main interrupt entry point. Verifies that the controller generated the */ 5470 /* interrupt and then calls a separate routine for handle the various */ 5471 /* interrupt causes (PHY, TX, RX). */ 5472 /* */ 5473 /* Returns: */ 5474 /* 0 for success, positive value for failure. */ 5475 /****************************************************************************/ 5476 int 5477 bnx_intr(void *xsc) 5478 { 5479 struct bnx_softc *sc = xsc; 5480 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5481 uint32_t status_attn_bits; 5482 uint16_t status_idx; 5483 const struct status_block *sblk; 5484 int rv = 0; 5485 5486 if (!device_is_active(sc->bnx_dev) || 5487 (ifp->if_flags & IFF_RUNNING) == 0) 5488 return 0; 5489 5490 DBRUNIF(1, sc->interrupts_generated++); 5491 5492 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5493 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5494 5495 sblk = sc->status_block; 5496 /* 5497 * If the hardware status block index 5498 * matches the last value read by the 5499 * driver and we haven't asserted our 5500 * interrupt then there's nothing to do. 5501 */ 5502 status_idx = sblk->status_idx; 5503 if ((status_idx != sc->last_status_idx) || 5504 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5505 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5506 rv = 1; 5507 5508 /* Ack the interrupt */ 5509 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5510 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5511 5512 status_attn_bits = sblk->status_attn_bits; 5513 5514 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5515 aprint_debug("Simulating unexpected status attention bit set."); 5516 status_attn_bits = status_attn_bits | 5517 STATUS_ATTN_BITS_PARITY_ERROR); 5518 5519 /* Was it a link change interrupt? */ 5520 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5521 (sblk->status_attn_bits_ack & 5522 STATUS_ATTN_BITS_LINK_STATE)) 5523 bnx_phy_intr(sc); 5524 5525 /* If any other attention is asserted then the chip is toast. */ 5526 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5527 (sblk->status_attn_bits_ack & 5528 ~STATUS_ATTN_BITS_LINK_STATE))) { 5529 DBRUN(sc->unexpected_attentions++); 5530 5531 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5532 sblk->status_attn_bits); 5533 5534 DBRUNIF((bnx_debug_unexpected_attention == 0), 5535 bnx_breakpoint(sc)); 5536 5537 bnx_init(ifp); 5538 goto out; 5539 } 5540 5541 /* Check for any completed RX frames. */ 5542 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5543 bnx_rx_intr(sc); 5544 5545 /* Check for any completed TX frames. */ 5546 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5547 bnx_tx_intr(sc); 5548 5549 /* 5550 * Save the status block index value for use during the 5551 * next interrupt. 5552 */ 5553 sc->last_status_idx = status_idx; 5554 5555 /* Start moving packets again */ 5556 if (ifp->if_flags & IFF_RUNNING) 5557 if_schedule_deferred_start(ifp); 5558 } 5559 5560 out: 5561 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5562 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5563 5564 return rv; 5565 } 5566 5567 /****************************************************************************/ 5568 /* Programs the various packet receive modes (broadcast and multicast). */ 5569 /* */ 5570 /* Returns: */ 5571 /* Nothing. */ 5572 /****************************************************************************/ 5573 void 5574 bnx_iff(struct bnx_softc *sc) 5575 { 5576 struct ethercom *ec = &sc->bnx_ec; 5577 struct ifnet *ifp = &ec->ec_if; 5578 struct ether_multi *enm; 5579 struct ether_multistep step; 5580 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5581 uint32_t rx_mode, sort_mode; 5582 int h, i; 5583 5584 /* Initialize receive mode default settings. */ 5585 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5586 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5587 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5588 ifp->if_flags &= ~IFF_ALLMULTI; 5589 5590 /* 5591 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5592 * be enbled. 5593 */ 5594 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5595 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5596 5597 /* 5598 * Check for promiscuous, all multicast, or selected 5599 * multicast address filtering. 5600 */ 5601 if (ifp->if_flags & IFF_PROMISC) { 5602 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5603 5604 ifp->if_flags |= IFF_ALLMULTI; 5605 /* Enable promiscuous mode. */ 5606 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5607 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5608 } else if (ifp->if_flags & IFF_ALLMULTI) { 5609 allmulti: 5610 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5611 5612 ifp->if_flags |= IFF_ALLMULTI; 5613 /* Enable all multicast addresses. */ 5614 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5615 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5616 0xffffffff); 5617 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5618 } else { 5619 /* Accept one or more multicast(s). */ 5620 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5621 5622 ETHER_LOCK(ec); 5623 ETHER_FIRST_MULTI(step, ec, enm); 5624 while (enm != NULL) { 5625 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5626 ETHER_ADDR_LEN)) { 5627 ETHER_UNLOCK(ec); 5628 goto allmulti; 5629 } 5630 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5631 0xFF; 5632 hashes[(h & 0xE0) >> 5] |= __BIT(h & 0x1F); 5633 ETHER_NEXT_MULTI(step, enm); 5634 } 5635 ETHER_UNLOCK(ec); 5636 5637 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5638 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5639 hashes[i]); 5640 5641 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5642 } 5643 5644 /* Only make changes if the receive mode has actually changed. */ 5645 if (rx_mode != sc->rx_mode) { 5646 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5647 rx_mode); 5648 5649 sc->rx_mode = rx_mode; 5650 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5651 } 5652 5653 /* Disable and clear the exisitng sort before enabling a new sort. */ 5654 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5655 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5656 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5657 } 5658 5659 /****************************************************************************/ 5660 /* Called periodically to updates statistics from the controllers */ 5661 /* statistics block. */ 5662 /* */ 5663 /* Returns: */ 5664 /* Nothing. */ 5665 /****************************************************************************/ 5666 void 5667 bnx_stats_update(struct bnx_softc *sc) 5668 { 5669 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5670 struct statistics_block *stats; 5671 5672 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5673 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5674 BUS_DMASYNC_POSTREAD); 5675 5676 stats = (struct statistics_block *)sc->stats_block; 5677 5678 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 5679 uint64_t value; 5680 5681 /* 5682 * Update the interface statistics from the 5683 * hardware statistics. 5684 */ 5685 value = (u_long)stats->stat_EtherStatsCollisions; 5686 if_statadd_ref(nsr, if_collisions, value - sc->if_stat_collisions); 5687 sc->if_stat_collisions = value; 5688 5689 value = (u_long)stats->stat_EtherStatsUndersizePkts + 5690 (u_long)stats->stat_EtherStatsOverrsizePkts + 5691 (u_long)stats->stat_IfInMBUFDiscards + 5692 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5693 (u_long)stats->stat_Dot3StatsFCSErrors; 5694 if_statadd_ref(nsr, if_ierrors, value - sc->if_stat_ierrors); 5695 sc->if_stat_ierrors = value; 5696 5697 value = (u_long) 5698 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5699 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5700 (u_long)stats->stat_Dot3StatsLateCollisions; 5701 if_statadd_ref(nsr, if_oerrors, value - sc->if_stat_oerrors); 5702 sc->if_stat_oerrors = value; 5703 5704 /* 5705 * Certain controllers don't report 5706 * carrier sense errors correctly. 5707 * See errata E11_5708CA0_1165. 5708 */ 5709 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5710 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) { 5711 if_statadd_ref(nsr, if_oerrors, 5712 (u_long) stats->stat_Dot3StatsCarrierSenseErrors); 5713 } 5714 5715 IF_STAT_PUTREF(ifp); 5716 5717 /* 5718 * Update the sysctl statistics from the 5719 * hardware statistics. 5720 */ 5721 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5722 (uint64_t) stats->stat_IfHCInOctets_lo; 5723 5724 sc->stat_IfHCInBadOctets = 5725 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5726 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5727 5728 sc->stat_IfHCOutOctets = 5729 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5730 (uint64_t) stats->stat_IfHCOutOctets_lo; 5731 5732 sc->stat_IfHCOutBadOctets = 5733 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5734 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5735 5736 sc->stat_IfHCInUcastPkts = 5737 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5738 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5739 5740 sc->stat_IfHCInMulticastPkts = 5741 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5742 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5743 5744 sc->stat_IfHCInBroadcastPkts = 5745 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5746 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5747 5748 sc->stat_IfHCOutUcastPkts = 5749 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5750 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5751 5752 sc->stat_IfHCOutMulticastPkts = 5753 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5754 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5755 5756 sc->stat_IfHCOutBroadcastPkts = 5757 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5758 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5759 5760 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5761 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5762 5763 sc->stat_Dot3StatsCarrierSenseErrors = 5764 stats->stat_Dot3StatsCarrierSenseErrors; 5765 5766 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5767 5768 sc->stat_Dot3StatsAlignmentErrors = 5769 stats->stat_Dot3StatsAlignmentErrors; 5770 5771 sc->stat_Dot3StatsSingleCollisionFrames = 5772 stats->stat_Dot3StatsSingleCollisionFrames; 5773 5774 sc->stat_Dot3StatsMultipleCollisionFrames = 5775 stats->stat_Dot3StatsMultipleCollisionFrames; 5776 5777 sc->stat_Dot3StatsDeferredTransmissions = 5778 stats->stat_Dot3StatsDeferredTransmissions; 5779 5780 sc->stat_Dot3StatsExcessiveCollisions = 5781 stats->stat_Dot3StatsExcessiveCollisions; 5782 5783 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5784 5785 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5786 5787 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5788 5789 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5790 5791 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5792 5793 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5794 5795 sc->stat_EtherStatsPktsRx64Octets = 5796 stats->stat_EtherStatsPktsRx64Octets; 5797 5798 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5799 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5800 5801 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5802 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5803 5804 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5805 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5806 5807 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5808 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5809 5810 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5811 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5812 5813 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5814 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5815 5816 sc->stat_EtherStatsPktsTx64Octets = 5817 stats->stat_EtherStatsPktsTx64Octets; 5818 5819 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5820 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5821 5822 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5823 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5824 5825 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5826 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5827 5828 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5829 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5830 5831 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5832 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5833 5834 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5835 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5836 5837 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5838 5839 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5840 5841 sc->stat_OutXonSent = stats->stat_OutXonSent; 5842 5843 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5844 5845 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5846 5847 sc->stat_MacControlFramesReceived = 5848 stats->stat_MacControlFramesReceived; 5849 5850 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5851 5852 sc->stat_IfInFramesL2FilterDiscards = 5853 stats->stat_IfInFramesL2FilterDiscards; 5854 5855 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5856 5857 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5858 5859 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5860 5861 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5862 5863 sc->stat_CatchupInRuleCheckerDiscards = 5864 stats->stat_CatchupInRuleCheckerDiscards; 5865 5866 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5867 5868 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5869 5870 sc->stat_CatchupInRuleCheckerP4Hit = 5871 stats->stat_CatchupInRuleCheckerP4Hit; 5872 5873 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5874 } 5875 5876 void 5877 bnx_tick(void *xsc) 5878 { 5879 struct bnx_softc *sc = xsc; 5880 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5881 struct mii_data *mii; 5882 uint32_t msg; 5883 uint16_t prod, chain_prod; 5884 uint32_t prod_bseq; 5885 int s = splnet(); 5886 5887 /* Tell the firmware that the driver is still running. */ 5888 #ifdef BNX_DEBUG 5889 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5890 #else 5891 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5892 #endif 5893 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5894 5895 /* Update the statistics from the hardware statistics block. */ 5896 bnx_stats_update(sc); 5897 5898 /* Schedule the next tick. */ 5899 if (!sc->bnx_detaching) 5900 callout_schedule(&sc->bnx_timeout, hz); 5901 5902 if (sc->bnx_link) 5903 goto bnx_tick_exit; 5904 5905 mii = &sc->bnx_mii; 5906 mii_tick(mii); 5907 5908 /* Check if the link has come up. */ 5909 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5910 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5911 sc->bnx_link++; 5912 /* Now that link is up, handle any outstanding TX traffic. */ 5913 if_schedule_deferred_start(ifp); 5914 } 5915 5916 bnx_tick_exit: 5917 /* try to get more RX buffers, just in case */ 5918 prod = sc->rx_prod; 5919 prod_bseq = sc->rx_prod_bseq; 5920 chain_prod = RX_CHAIN_IDX(prod); 5921 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5922 sc->rx_prod = prod; 5923 sc->rx_prod_bseq = prod_bseq; 5924 5925 splx(s); 5926 return; 5927 } 5928 5929 /****************************************************************************/ 5930 /* BNX Debug Routines */ 5931 /****************************************************************************/ 5932 #ifdef BNX_DEBUG 5933 5934 /****************************************************************************/ 5935 /* Prints out information about an mbuf. */ 5936 /* */ 5937 /* Returns: */ 5938 /* Nothing. */ 5939 /****************************************************************************/ 5940 void 5941 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5942 { 5943 struct mbuf *mp = m; 5944 5945 if (m == NULL) { 5946 /* Index out of range. */ 5947 aprint_error("mbuf ptr is null!\n"); 5948 return; 5949 } 5950 5951 while (mp) { 5952 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5953 mp, mp->m_len); 5954 5955 if (mp->m_flags & M_EXT) 5956 aprint_debug("M_EXT "); 5957 if (mp->m_flags & M_PKTHDR) 5958 aprint_debug("M_PKTHDR "); 5959 aprint_debug("\n"); 5960 5961 if (mp->m_flags & M_EXT) 5962 aprint_debug("- m_ext: vaddr = %p, " 5963 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5964 5965 mp = mp->m_next; 5966 } 5967 } 5968 5969 /****************************************************************************/ 5970 /* Prints out the mbufs in the TX mbuf chain. */ 5971 /* */ 5972 /* Returns: */ 5973 /* Nothing. */ 5974 /****************************************************************************/ 5975 void 5976 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5977 { 5978 #if 0 5979 struct mbuf *m; 5980 int i; 5981 5982 aprint_debug_dev(sc->bnx_dev, 5983 "----------------------------" 5984 " tx mbuf data " 5985 "----------------------------\n"); 5986 5987 for (i = 0; i < count; i++) { 5988 m = sc->tx_mbuf_ptr[chain_prod]; 5989 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5990 bnx_dump_mbuf(sc, m); 5991 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5992 } 5993 5994 aprint_debug_dev(sc->bnx_dev, 5995 "--------------------------------------------" 5996 "----------------------------\n"); 5997 #endif 5998 } 5999 6000 /* 6001 * This routine prints the RX mbuf chain. 6002 */ 6003 void 6004 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 6005 { 6006 struct mbuf *m; 6007 int i; 6008 6009 aprint_debug_dev(sc->bnx_dev, 6010 "----------------------------" 6011 " rx mbuf data " 6012 "----------------------------\n"); 6013 6014 for (i = 0; i < count; i++) { 6015 m = sc->rx_mbuf_ptr[chain_prod]; 6016 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6017 bnx_dump_mbuf(sc, m); 6018 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6019 } 6020 6021 6022 aprint_debug_dev(sc->bnx_dev, 6023 "--------------------------------------------" 6024 "----------------------------\n"); 6025 } 6026 6027 void 6028 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 6029 { 6030 if (idx > MAX_TX_BD) 6031 /* Index out of range. */ 6032 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6033 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6034 /* TX Chain page pointer. */ 6035 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 6036 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 6037 txbd->tx_bd_haddr_lo); 6038 else 6039 /* Normal tx_bd entry. */ 6040 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6041 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 6042 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6043 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6044 txbd->tx_bd_flags); 6045 } 6046 6047 void 6048 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 6049 { 6050 if (idx > MAX_RX_BD) 6051 /* Index out of range. */ 6052 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6053 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6054 /* TX Chain page pointer. */ 6055 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 6056 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 6057 rxbd->rx_bd_haddr_lo); 6058 else 6059 /* Normal tx_bd entry. */ 6060 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6061 "0x%08X, flags = 0x%08X\n", idx, 6062 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6063 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6064 } 6065 6066 void 6067 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6068 { 6069 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6070 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6071 "tcp_udp_xsum = 0x%04X\n", idx, 6072 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6073 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6074 l2fhdr->l2_fhdr_tcp_udp_xsum); 6075 } 6076 6077 /* 6078 * This routine prints the TX chain. 6079 */ 6080 void 6081 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 6082 { 6083 struct tx_bd *txbd; 6084 int i; 6085 6086 /* First some info about the tx_bd chain structure. */ 6087 aprint_debug_dev(sc->bnx_dev, 6088 "----------------------------" 6089 " tx_bd chain " 6090 "----------------------------\n"); 6091 6092 BNX_PRINTF(sc, 6093 "page size = 0x%08X, tx chain pages = 0x%08X\n", 6094 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6095 6096 BNX_PRINTF(sc, 6097 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6098 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6099 6100 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6101 6102 aprint_error_dev(sc->bnx_dev, "" 6103 "-----------------------------" 6104 " tx_bd data " 6105 "-----------------------------\n"); 6106 6107 /* Now print out the tx_bd's themselves. */ 6108 for (i = 0; i < count; i++) { 6109 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6110 bnx_dump_txbd(sc, tx_prod, txbd); 6111 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6112 } 6113 6114 aprint_debug_dev(sc->bnx_dev, 6115 "-----------------------------" 6116 "--------------" 6117 "-----------------------------\n"); 6118 } 6119 6120 /* 6121 * This routine prints the RX chain. 6122 */ 6123 void 6124 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6125 { 6126 struct rx_bd *rxbd; 6127 int i; 6128 6129 /* First some info about the tx_bd chain structure. */ 6130 aprint_debug_dev(sc->bnx_dev, 6131 "----------------------------" 6132 " rx_bd chain " 6133 "----------------------------\n"); 6134 6135 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6136 6137 BNX_PRINTF(sc, 6138 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6139 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6140 6141 BNX_PRINTF(sc, 6142 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6143 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6144 6145 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6146 6147 aprint_error_dev(sc->bnx_dev, 6148 "----------------------------" 6149 " rx_bd data " 6150 "----------------------------\n"); 6151 6152 /* Now print out the rx_bd's themselves. */ 6153 for (i = 0; i < count; i++) { 6154 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6155 bnx_dump_rxbd(sc, rx_prod, rxbd); 6156 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6157 } 6158 6159 aprint_debug_dev(sc->bnx_dev, 6160 "----------------------------" 6161 "--------------" 6162 "----------------------------\n"); 6163 } 6164 6165 /* 6166 * This routine prints the status block. 6167 */ 6168 void 6169 bnx_dump_status_block(struct bnx_softc *sc) 6170 { 6171 struct status_block *sblk; 6172 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6173 BUS_DMASYNC_POSTREAD); 6174 6175 sblk = sc->status_block; 6176 6177 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6178 "Status Block -----------------------------\n"); 6179 6180 BNX_PRINTF(sc, 6181 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6182 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6183 sblk->status_idx); 6184 6185 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6186 sblk->status_rx_quick_consumer_index0, 6187 sblk->status_tx_quick_consumer_index0); 6188 6189 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6190 6191 /* Theses indices are not used for normal L2 drivers. */ 6192 if (sblk->status_rx_quick_consumer_index1 || 6193 sblk->status_tx_quick_consumer_index1) 6194 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6195 sblk->status_rx_quick_consumer_index1, 6196 sblk->status_tx_quick_consumer_index1); 6197 6198 if (sblk->status_rx_quick_consumer_index2 || 6199 sblk->status_tx_quick_consumer_index2) 6200 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6201 sblk->status_rx_quick_consumer_index2, 6202 sblk->status_tx_quick_consumer_index2); 6203 6204 if (sblk->status_rx_quick_consumer_index3 || 6205 sblk->status_tx_quick_consumer_index3) 6206 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6207 sblk->status_rx_quick_consumer_index3, 6208 sblk->status_tx_quick_consumer_index3); 6209 6210 if (sblk->status_rx_quick_consumer_index4 || 6211 sblk->status_rx_quick_consumer_index5) 6212 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6213 sblk->status_rx_quick_consumer_index4, 6214 sblk->status_rx_quick_consumer_index5); 6215 6216 if (sblk->status_rx_quick_consumer_index6 || 6217 sblk->status_rx_quick_consumer_index7) 6218 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6219 sblk->status_rx_quick_consumer_index6, 6220 sblk->status_rx_quick_consumer_index7); 6221 6222 if (sblk->status_rx_quick_consumer_index8 || 6223 sblk->status_rx_quick_consumer_index9) 6224 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6225 sblk->status_rx_quick_consumer_index8, 6226 sblk->status_rx_quick_consumer_index9); 6227 6228 if (sblk->status_rx_quick_consumer_index10 || 6229 sblk->status_rx_quick_consumer_index11) 6230 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6231 sblk->status_rx_quick_consumer_index10, 6232 sblk->status_rx_quick_consumer_index11); 6233 6234 if (sblk->status_rx_quick_consumer_index12 || 6235 sblk->status_rx_quick_consumer_index13) 6236 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6237 sblk->status_rx_quick_consumer_index12, 6238 sblk->status_rx_quick_consumer_index13); 6239 6240 if (sblk->status_rx_quick_consumer_index14 || 6241 sblk->status_rx_quick_consumer_index15) 6242 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6243 sblk->status_rx_quick_consumer_index14, 6244 sblk->status_rx_quick_consumer_index15); 6245 6246 if (sblk->status_completion_producer_index || 6247 sblk->status_cmd_consumer_index) 6248 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6249 sblk->status_completion_producer_index, 6250 sblk->status_cmd_consumer_index); 6251 6252 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6253 "-----------------------------\n"); 6254 } 6255 6256 /* 6257 * This routine prints the statistics block. 6258 */ 6259 void 6260 bnx_dump_stats_block(struct bnx_softc *sc) 6261 { 6262 struct statistics_block *sblk; 6263 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6264 BUS_DMASYNC_POSTREAD); 6265 6266 sblk = sc->stats_block; 6267 6268 aprint_debug_dev(sc->bnx_dev, "" 6269 "-----------------------------" 6270 " Stats Block " 6271 "-----------------------------\n"); 6272 6273 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6274 "IfHcInBadOctets = 0x%08X:%08X\n", 6275 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6276 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6277 6278 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6279 "IfHcOutBadOctets = 0x%08X:%08X\n", 6280 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6281 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6282 6283 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6284 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6285 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6286 sblk->stat_IfHCInMulticastPkts_hi, 6287 sblk->stat_IfHCInMulticastPkts_lo); 6288 6289 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6290 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6291 sblk->stat_IfHCInBroadcastPkts_hi, 6292 sblk->stat_IfHCInBroadcastPkts_lo, 6293 sblk->stat_IfHCOutUcastPkts_hi, 6294 sblk->stat_IfHCOutUcastPkts_lo); 6295 6296 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6297 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6298 sblk->stat_IfHCOutMulticastPkts_hi, 6299 sblk->stat_IfHCOutMulticastPkts_lo, 6300 sblk->stat_IfHCOutBroadcastPkts_hi, 6301 sblk->stat_IfHCOutBroadcastPkts_lo); 6302 6303 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6304 BNX_PRINTF(sc, "0x%08X : " 6305 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6306 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6307 6308 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6309 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6310 sblk->stat_Dot3StatsCarrierSenseErrors); 6311 6312 if (sblk->stat_Dot3StatsFCSErrors) 6313 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6314 sblk->stat_Dot3StatsFCSErrors); 6315 6316 if (sblk->stat_Dot3StatsAlignmentErrors) 6317 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6318 sblk->stat_Dot3StatsAlignmentErrors); 6319 6320 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6321 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6322 sblk->stat_Dot3StatsSingleCollisionFrames); 6323 6324 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6325 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6326 sblk->stat_Dot3StatsMultipleCollisionFrames); 6327 6328 if (sblk->stat_Dot3StatsDeferredTransmissions) 6329 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6330 sblk->stat_Dot3StatsDeferredTransmissions); 6331 6332 if (sblk->stat_Dot3StatsExcessiveCollisions) 6333 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6334 sblk->stat_Dot3StatsExcessiveCollisions); 6335 6336 if (sblk->stat_Dot3StatsLateCollisions) 6337 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6338 sblk->stat_Dot3StatsLateCollisions); 6339 6340 if (sblk->stat_EtherStatsCollisions) 6341 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6342 sblk->stat_EtherStatsCollisions); 6343 6344 if (sblk->stat_EtherStatsFragments) 6345 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6346 sblk->stat_EtherStatsFragments); 6347 6348 if (sblk->stat_EtherStatsJabbers) 6349 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6350 sblk->stat_EtherStatsJabbers); 6351 6352 if (sblk->stat_EtherStatsUndersizePkts) 6353 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6354 sblk->stat_EtherStatsUndersizePkts); 6355 6356 if (sblk->stat_EtherStatsOverrsizePkts) 6357 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6358 sblk->stat_EtherStatsOverrsizePkts); 6359 6360 if (sblk->stat_EtherStatsPktsRx64Octets) 6361 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6362 sblk->stat_EtherStatsPktsRx64Octets); 6363 6364 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6365 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6366 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6367 6368 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6369 BNX_PRINTF(sc, "0x%08X : " 6370 "EtherStatsPktsRx128Octetsto255Octets\n", 6371 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6372 6373 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6374 BNX_PRINTF(sc, "0x%08X : " 6375 "EtherStatsPktsRx256Octetsto511Octets\n", 6376 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6377 6378 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6379 BNX_PRINTF(sc, "0x%08X : " 6380 "EtherStatsPktsRx512Octetsto1023Octets\n", 6381 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6382 6383 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6384 BNX_PRINTF(sc, "0x%08X : " 6385 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6386 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6387 6388 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6389 BNX_PRINTF(sc, "0x%08X : " 6390 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6391 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6392 6393 if (sblk->stat_EtherStatsPktsTx64Octets) 6394 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6395 sblk->stat_EtherStatsPktsTx64Octets); 6396 6397 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6398 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6399 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6400 6401 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6402 BNX_PRINTF(sc, "0x%08X : " 6403 "EtherStatsPktsTx128Octetsto255Octets\n", 6404 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6405 6406 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6407 BNX_PRINTF(sc, "0x%08X : " 6408 "EtherStatsPktsTx256Octetsto511Octets\n", 6409 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6410 6411 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6412 BNX_PRINTF(sc, "0x%08X : " 6413 "EtherStatsPktsTx512Octetsto1023Octets\n", 6414 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6415 6416 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6417 BNX_PRINTF(sc, "0x%08X : " 6418 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6419 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6420 6421 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6422 BNX_PRINTF(sc, "0x%08X : " 6423 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6424 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6425 6426 if (sblk->stat_XonPauseFramesReceived) 6427 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6428 sblk->stat_XonPauseFramesReceived); 6429 6430 if (sblk->stat_XoffPauseFramesReceived) 6431 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6432 sblk->stat_XoffPauseFramesReceived); 6433 6434 if (sblk->stat_OutXonSent) 6435 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6436 sblk->stat_OutXonSent); 6437 6438 if (sblk->stat_OutXoffSent) 6439 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6440 sblk->stat_OutXoffSent); 6441 6442 if (sblk->stat_FlowControlDone) 6443 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6444 sblk->stat_FlowControlDone); 6445 6446 if (sblk->stat_MacControlFramesReceived) 6447 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6448 sblk->stat_MacControlFramesReceived); 6449 6450 if (sblk->stat_XoffStateEntered) 6451 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6452 sblk->stat_XoffStateEntered); 6453 6454 if (sblk->stat_IfInFramesL2FilterDiscards) 6455 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6456 sblk->stat_IfInFramesL2FilterDiscards); 6457 6458 if (sblk->stat_IfInRuleCheckerDiscards) 6459 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6460 sblk->stat_IfInRuleCheckerDiscards); 6461 6462 if (sblk->stat_IfInFTQDiscards) 6463 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6464 sblk->stat_IfInFTQDiscards); 6465 6466 if (sblk->stat_IfInMBUFDiscards) 6467 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6468 sblk->stat_IfInMBUFDiscards); 6469 6470 if (sblk->stat_IfInRuleCheckerP4Hit) 6471 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6472 sblk->stat_IfInRuleCheckerP4Hit); 6473 6474 if (sblk->stat_CatchupInRuleCheckerDiscards) 6475 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6476 sblk->stat_CatchupInRuleCheckerDiscards); 6477 6478 if (sblk->stat_CatchupInFTQDiscards) 6479 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6480 sblk->stat_CatchupInFTQDiscards); 6481 6482 if (sblk->stat_CatchupInMBUFDiscards) 6483 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6484 sblk->stat_CatchupInMBUFDiscards); 6485 6486 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6487 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6488 sblk->stat_CatchupInRuleCheckerP4Hit); 6489 6490 aprint_debug_dev(sc->bnx_dev, 6491 "-----------------------------" 6492 "--------------" 6493 "-----------------------------\n"); 6494 } 6495 6496 void 6497 bnx_dump_driver_state(struct bnx_softc *sc) 6498 { 6499 aprint_debug_dev(sc->bnx_dev, 6500 "-----------------------------" 6501 " Driver State " 6502 "-----------------------------\n"); 6503 6504 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6505 "address\n", sc); 6506 6507 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6508 sc->status_block); 6509 6510 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6511 "address\n", sc->stats_block); 6512 6513 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6514 "address\n", sc->tx_bd_chain); 6515 6516 #if 0 6517 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6518 sc->rx_bd_chain); 6519 6520 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6521 sc->tx_mbuf_ptr); 6522 #endif 6523 6524 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6525 sc->rx_mbuf_ptr); 6526 6527 BNX_PRINTF(sc, 6528 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6529 sc->interrupts_generated); 6530 6531 BNX_PRINTF(sc, 6532 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6533 sc->rx_interrupts); 6534 6535 BNX_PRINTF(sc, 6536 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6537 sc->tx_interrupts); 6538 6539 BNX_PRINTF(sc, 6540 " 0x%08X - (sc->last_status_idx) status block index\n", 6541 sc->last_status_idx); 6542 6543 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6544 sc->tx_prod); 6545 6546 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6547 sc->tx_cons); 6548 6549 BNX_PRINTF(sc, 6550 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6551 sc->tx_prod_bseq); 6552 BNX_PRINTF(sc, 6553 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6554 sc->tx_mbuf_alloc); 6555 6556 BNX_PRINTF(sc, 6557 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6558 sc->used_tx_bd); 6559 6560 BNX_PRINTF(sc, 6561 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6562 sc->tx_hi_watermark, sc->max_tx_bd); 6563 6564 6565 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6566 sc->rx_prod); 6567 6568 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6569 sc->rx_cons); 6570 6571 BNX_PRINTF(sc, 6572 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6573 sc->rx_prod_bseq); 6574 6575 BNX_PRINTF(sc, 6576 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6577 sc->rx_mbuf_alloc); 6578 6579 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6580 sc->free_rx_bd); 6581 6582 BNX_PRINTF(sc, 6583 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6584 sc->rx_low_watermark, sc->max_rx_bd); 6585 6586 BNX_PRINTF(sc, 6587 " 0x%08X - (sc->mbuf_alloc_failed) " 6588 "mbuf alloc failures\n", 6589 sc->mbuf_alloc_failed); 6590 6591 BNX_PRINTF(sc, 6592 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6593 "simulated mbuf alloc failures\n", 6594 sc->mbuf_sim_alloc_failed); 6595 6596 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6597 "-----------------------------\n"); 6598 } 6599 6600 void 6601 bnx_dump_hw_state(struct bnx_softc *sc) 6602 { 6603 uint32_t val1; 6604 int i; 6605 6606 aprint_debug_dev(sc->bnx_dev, 6607 "----------------------------" 6608 " Hardware State " 6609 "----------------------------\n"); 6610 6611 val1 = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 6612 BNX_PRINTF(sc, "0x%08X : bootcode version\n", val1); 6613 6614 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6615 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6616 val1, BNX_MISC_ENABLE_STATUS_BITS); 6617 6618 val1 = REG_RD(sc, BNX_DMA_STATUS); 6619 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6620 6621 val1 = REG_RD(sc, BNX_CTX_STATUS); 6622 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6623 6624 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6625 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6626 BNX_EMAC_STATUS); 6627 6628 val1 = REG_RD(sc, BNX_RPM_STATUS); 6629 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6630 6631 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6632 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6633 BNX_TBDR_STATUS); 6634 6635 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6636 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6637 BNX_TDMA_STATUS); 6638 6639 val1 = REG_RD(sc, BNX_HC_STATUS); 6640 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6641 6642 aprint_debug_dev(sc->bnx_dev, 6643 "----------------------------" 6644 "----------------" 6645 "----------------------------\n"); 6646 6647 aprint_debug_dev(sc->bnx_dev, 6648 "----------------------------" 6649 " Register Dump " 6650 "----------------------------\n"); 6651 6652 for (i = 0x400; i < 0x8000; i += 0x10) 6653 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6654 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6655 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6656 6657 aprint_debug_dev(sc->bnx_dev, 6658 "----------------------------" 6659 "----------------" 6660 "----------------------------\n"); 6661 } 6662 6663 void 6664 bnx_breakpoint(struct bnx_softc *sc) 6665 { 6666 /* Unreachable code to shut the compiler up about unused functions. */ 6667 if (0) { 6668 bnx_dump_txbd(sc, 0, NULL); 6669 bnx_dump_rxbd(sc, 0, NULL); 6670 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6671 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6672 bnx_dump_l2fhdr(sc, 0, NULL); 6673 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6674 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6675 bnx_dump_status_block(sc); 6676 bnx_dump_stats_block(sc); 6677 bnx_dump_driver_state(sc); 6678 bnx_dump_hw_state(sc); 6679 } 6680 6681 bnx_dump_driver_state(sc); 6682 /* Print the important status block fields. */ 6683 bnx_dump_status_block(sc); 6684 6685 #if 0 6686 /* Call the debugger. */ 6687 breakpoint(); 6688 #endif 6689 6690 return; 6691 } 6692 #endif 6693
Indexes created Wed Sep 24 15:09:51 GMT 2025