if_bnx.c revision 1.99
1 /* $NetBSD: if_bnx.c,v 1.99 2020/07/14 15:37:40 jdolecek Exp $ */ 2 /* $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006-2010 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 #if 0 36 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); 37 #endif 38 __KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.99 2020/07/14 15:37:40 jdolecek Exp $"); 39 40 /* 41 * The following controllers are supported by this driver: 42 * BCM5706C A2, A3 43 * BCM5706S A2, A3 44 * BCM5708C B1, B2 45 * BCM5708S B1, B2 46 * BCM5709C A1, C0 47 * BCM5709S A1, C0 48 * BCM5716 C0 49 * 50 * The following controllers are not supported by this driver: 51 * BCM5706C A0, A1 52 * BCM5706S A0, A1 53 * BCM5708C A0, B0 54 * BCM5708S A0, B0 55 * BCM5709C A0 B0, B1, B2 (pre-production) 56 * BCM5709S A0, B0, B1, B2 (pre-production) 57 */ 58 59 #include <sys/callout.h> 60 #include <sys/mutex.h> 61 62 #include <dev/pci/if_bnxreg.h> 63 #include <dev/pci/if_bnxvar.h> 64 65 #include <dev/microcode/bnx/bnxfw.h> 66 67 /****************************************************************************/ 68 /* BNX Driver Version */ 69 /****************************************************************************/ 70 #define BNX_DRIVER_VERSION "v0.9.6" 71 72 /****************************************************************************/ 73 /* BNX Debug Options */ 74 /****************************************************************************/ 75 #ifdef BNX_DEBUG 76 uint32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; 77 78 /* 0 = Never */ 79 /* 1 = 1 in 2,147,483,648 */ 80 /* 256 = 1 in 8,388,608 */ 81 /* 2048 = 1 in 1,048,576 */ 82 /* 65536 = 1 in 32,768 */ 83 /* 1048576 = 1 in 2,048 */ 84 /* 268435456 = 1 in 8 */ 85 /* 536870912 = 1 in 4 */ 86 /* 1073741824 = 1 in 2 */ 87 88 /* Controls how often the l2_fhdr frame error check will fail. */ 89 int bnx_debug_l2fhdr_status_check = 0; 90 91 /* Controls how often the unexpected attention check will fail. */ 92 int bnx_debug_unexpected_attention = 0; 93 94 /* Controls how often to simulate an mbuf allocation failure. */ 95 int bnx_debug_mbuf_allocation_failure = 0; 96 97 /* Controls how often to simulate a DMA mapping failure. */ 98 int bnx_debug_dma_map_addr_failure = 0; 99 100 /* Controls how often to simulate a bootcode failure. */ 101 int bnx_debug_bootcode_running_failure = 0; 102 #endif 103 104 /****************************************************************************/ 105 /* PCI Device ID Table */ 106 /* */ 107 /* Used by bnx_probe() to identify the devices supported by this driver. */ 108 /****************************************************************************/ 109 static const struct bnx_product { 110 pci_vendor_id_t bp_vendor; 111 pci_product_id_t bp_product; 112 pci_vendor_id_t bp_subvendor; 113 pci_product_id_t bp_subproduct; 114 const char *bp_name; 115 } bnx_devices[] = { 116 #ifdef PCI_SUBPRODUCT_HP_NC370T 117 { 118 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 119 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, 120 "HP NC370T Multifunction Gigabit Server Adapter" 121 }, 122 #endif 123 #ifdef PCI_SUBPRODUCT_HP_NC370i 124 { 125 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 126 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, 127 "HP NC370i Multifunction Gigabit Server Adapter" 128 }, 129 #endif 130 { 131 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, 132 0, 0, 133 "Broadcom NetXtreme II BCM5706 1000Base-T" 134 }, 135 #ifdef PCI_SUBPRODUCT_HP_NC370F 136 { 137 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 138 PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, 139 "HP NC370F Multifunction Gigabit Server Adapter" 140 }, 141 #endif 142 { 143 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, 144 0, 0, 145 "Broadcom NetXtreme II BCM5706 1000Base-SX" 146 }, 147 { 148 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, 149 0, 0, 150 "Broadcom NetXtreme II BCM5708 1000Base-T" 151 }, 152 { 153 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, 154 0, 0, 155 "Broadcom NetXtreme II BCM5708 1000Base-SX" 156 }, 157 { 158 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709, 159 0, 0, 160 "Broadcom NetXtreme II BCM5709 1000Base-T" 161 }, 162 { 163 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5709S, 164 0, 0, 165 "Broadcom NetXtreme II BCM5709 1000Base-SX" 166 }, 167 { 168 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716, 169 0, 0, 170 "Broadcom NetXtreme II BCM5716 1000Base-T" 171 }, 172 { 173 PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5716S, 174 0, 0, 175 "Broadcom NetXtreme II BCM5716 1000Base-SX" 176 }, 177 }; 178 179 180 /****************************************************************************/ 181 /* Supported Flash NVRAM device data. */ 182 /****************************************************************************/ 183 static struct flash_spec flash_table[] = 184 { 185 #define BUFFERED_FLAGS (BNX_NV_BUFFERED | BNX_NV_TRANSLATE) 186 #define NONBUFFERED_FLAGS (BNX_NV_WREN) 187 188 /* Slow EEPROM */ 189 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 190 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 191 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 192 "EEPROM - slow"}, 193 /* Expansion entry 0001 */ 194 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 195 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 0001"}, 198 /* Saifun SA25F010 (non-buffered flash) */ 199 /* strap, cfg1, & write1 need updates */ 200 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 202 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 203 "Non-buffered flash (128kB)"}, 204 /* Saifun SA25F020 (non-buffered flash) */ 205 /* strap, cfg1, & write1 need updates */ 206 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 209 "Non-buffered flash (256kB)"}, 210 /* Expansion entry 0100 */ 211 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 214 "Entry 0100"}, 215 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 216 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 217 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 218 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 219 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 220 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 221 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 223 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 224 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 225 /* Saifun SA25F005 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 230 "Non-buffered flash (64kB)"}, 231 /* Fast EEPROM */ 232 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 233 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 234 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 235 "EEPROM - fast"}, 236 /* Expansion entry 1001 */ 237 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1001"}, 241 /* Expansion entry 1010 */ 242 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1010"}, 246 /* ATMEL AT45DB011B (buffered flash) */ 247 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 250 "Buffered flash (128kB)"}, 251 /* Expansion entry 1100 */ 252 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 255 "Entry 1100"}, 256 /* Expansion entry 1101 */ 257 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 258 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 259 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 260 "Entry 1101"}, 261 /* Ateml Expansion entry 1110 */ 262 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 263 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 264 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1110 (Atmel)"}, 266 /* ATMEL AT45DB021B (buffered flash) */ 267 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 268 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 269 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 270 "Buffered flash (256kB)"}, 271 }; 272 273 /* 274 * The BCM5709 controllers transparently handle the 275 * differences between Atmel 264 byte pages and all 276 * flash devices which use 256 byte pages, so no 277 * logical-to-physical mapping is required in the 278 * driver. 279 */ 280 static struct flash_spec flash_5709 = { 281 .flags = BNX_NV_BUFFERED, 282 .page_bits = BCM5709_FLASH_PAGE_BITS, 283 .page_size = BCM5709_FLASH_PAGE_SIZE, 284 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 285 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 286 .name = "5709 buffered flash (256kB)", 287 }; 288 289 /****************************************************************************/ 290 /* OpenBSD device entry points. */ 291 /****************************************************************************/ 292 static int bnx_probe(device_t, cfdata_t, void *); 293 void bnx_attach(device_t, device_t, void *); 294 int bnx_detach(device_t, int); 295 296 /****************************************************************************/ 297 /* BNX Debug Data Structure Dump Routines */ 298 /****************************************************************************/ 299 #ifdef BNX_DEBUG 300 void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); 301 void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); 302 void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); 303 void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); 304 void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); 305 void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); 306 void bnx_dump_tx_chain(struct bnx_softc *, int, int); 307 void bnx_dump_rx_chain(struct bnx_softc *, int, int); 308 void bnx_dump_status_block(struct bnx_softc *); 309 void bnx_dump_stats_block(struct bnx_softc *); 310 void bnx_dump_driver_state(struct bnx_softc *); 311 void bnx_dump_hw_state(struct bnx_softc *); 312 void bnx_breakpoint(struct bnx_softc *); 313 #endif 314 315 /****************************************************************************/ 316 /* BNX Register/Memory Access Routines */ 317 /****************************************************************************/ 318 uint32_t bnx_reg_rd_ind(struct bnx_softc *, uint32_t); 319 void bnx_reg_wr_ind(struct bnx_softc *, uint32_t, uint32_t); 320 void bnx_ctx_wr(struct bnx_softc *, uint32_t, uint32_t, uint32_t); 321 int bnx_miibus_read_reg(device_t, int, int, uint16_t *); 322 int bnx_miibus_write_reg(device_t, int, int, uint16_t); 323 void bnx_miibus_statchg(struct ifnet *); 324 325 /****************************************************************************/ 326 /* BNX NVRAM Access Routines */ 327 /****************************************************************************/ 328 int bnx_acquire_nvram_lock(struct bnx_softc *); 329 int bnx_release_nvram_lock(struct bnx_softc *); 330 void bnx_enable_nvram_access(struct bnx_softc *); 331 void bnx_disable_nvram_access(struct bnx_softc *); 332 int bnx_nvram_read_dword(struct bnx_softc *, uint32_t, uint8_t *, 333 uint32_t); 334 int bnx_init_nvram(struct bnx_softc *); 335 int bnx_nvram_read(struct bnx_softc *, uint32_t, uint8_t *, int); 336 int bnx_nvram_test(struct bnx_softc *); 337 #ifdef BNX_NVRAM_WRITE_SUPPORT 338 int bnx_enable_nvram_write(struct bnx_softc *); 339 void bnx_disable_nvram_write(struct bnx_softc *); 340 int bnx_nvram_erase_page(struct bnx_softc *, uint32_t); 341 int bnx_nvram_write_dword(struct bnx_softc *, uint32_t, uint8_t *, 342 uint32_t); 343 int bnx_nvram_write(struct bnx_softc *, uint32_t, uint8_t *, int); 344 #endif 345 346 /****************************************************************************/ 347 /* */ 348 /****************************************************************************/ 349 void bnx_get_media(struct bnx_softc *); 350 void bnx_init_media(struct bnx_softc *); 351 int bnx_dma_alloc(struct bnx_softc *); 352 void bnx_dma_free(struct bnx_softc *); 353 void bnx_release_resources(struct bnx_softc *); 354 355 /****************************************************************************/ 356 /* BNX Firmware Synchronization and Load */ 357 /****************************************************************************/ 358 int bnx_fw_sync(struct bnx_softc *, uint32_t); 359 void bnx_load_rv2p_fw(struct bnx_softc *, uint32_t *, uint32_t, uint32_t); 360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, 361 struct fw_info *); 362 void bnx_init_cpus(struct bnx_softc *); 363 364 static void bnx_print_adapter_info(struct bnx_softc *); 365 static void bnx_probe_pci_caps(struct bnx_softc *); 366 void bnx_stop(struct ifnet *, int); 367 int bnx_reset(struct bnx_softc *, uint32_t); 368 int bnx_chipinit(struct bnx_softc *); 369 int bnx_blockinit(struct bnx_softc *); 370 static int bnx_add_buf(struct bnx_softc *, struct mbuf *, uint16_t *, 371 uint16_t *, uint32_t *); 372 int bnx_get_buf(struct bnx_softc *, uint16_t *, uint16_t *, uint32_t *); 373 374 int bnx_init_tx_chain(struct bnx_softc *); 375 void bnx_init_tx_context(struct bnx_softc *); 376 int bnx_init_rx_chain(struct bnx_softc *); 377 void bnx_init_rx_context(struct bnx_softc *); 378 void bnx_free_rx_chain(struct bnx_softc *); 379 void bnx_free_tx_chain(struct bnx_softc *); 380 381 int bnx_tx_encap(struct bnx_softc *, struct mbuf *); 382 void bnx_start(struct ifnet *); 383 int bnx_ioctl(struct ifnet *, u_long, void *); 384 void bnx_watchdog(struct ifnet *); 385 int bnx_ifmedia_upd(struct ifnet *); 386 void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); 387 int bnx_init(struct ifnet *); 388 static void bnx_mgmt_init(struct bnx_softc *); 389 390 void bnx_init_context(struct bnx_softc *); 391 void bnx_get_mac_addr(struct bnx_softc *); 392 void bnx_set_mac_addr(struct bnx_softc *); 393 void bnx_phy_intr(struct bnx_softc *); 394 void bnx_rx_intr(struct bnx_softc *); 395 void bnx_tx_intr(struct bnx_softc *); 396 void bnx_disable_intr(struct bnx_softc *); 397 void bnx_enable_intr(struct bnx_softc *); 398 399 int bnx_intr(void *); 400 void bnx_iff(struct bnx_softc *); 401 void bnx_stats_update(struct bnx_softc *); 402 void bnx_tick(void *); 403 404 struct pool *bnx_tx_pool = NULL; 405 void bnx_alloc_pkts(struct work *, void *); 406 407 /****************************************************************************/ 408 /* OpenBSD device dispatch table. */ 409 /****************************************************************************/ 410 CFATTACH_DECL3_NEW(bnx, sizeof(struct bnx_softc), 411 bnx_probe, bnx_attach, bnx_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 412 413 /****************************************************************************/ 414 /* Device probe function. */ 415 /* */ 416 /* Compares the device to the driver's list of supported devices and */ 417 /* reports back to the OS whether this is the right driver for the device. */ 418 /* */ 419 /* Returns: */ 420 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 421 /****************************************************************************/ 422 static const struct bnx_product * 423 bnx_lookup(const struct pci_attach_args *pa) 424 { 425 int i; 426 pcireg_t subid; 427 428 for (i = 0; i < __arraycount(bnx_devices); i++) { 429 if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || 430 PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) 431 continue; 432 if (!bnx_devices[i].bp_subvendor) 433 return &bnx_devices[i]; 434 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 435 if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && 436 PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) 437 return &bnx_devices[i]; 438 } 439 440 return NULL; 441 } 442 static int 443 bnx_probe(device_t parent, cfdata_t match, void *aux) 444 { 445 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 446 447 if (bnx_lookup(pa) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 /****************************************************************************/ 454 /* PCI Capabilities Probe Function. */ 455 /* */ 456 /* Walks the PCI capabiites list for the device to find what features are */ 457 /* supported. */ 458 /* */ 459 /* Returns: */ 460 /* None. */ 461 /****************************************************************************/ 462 static void 463 bnx_print_adapter_info(struct bnx_softc *sc) 464 { 465 device_t dev = sc->bnx_dev; 466 int i = 0; 467 468 aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n", 469 BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc), 470 (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT) 471 ? "Serdes " : "", sc->bnx_chipid); 472 473 /* Bus info. */ 474 if (sc->bnx_flags & BNX_PCIE_FLAG) { 475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); 476 switch (sc->link_speed) { 477 case 1: aprint_normal("2.5GT/s\n"); break; 478 case 2: aprint_normal("5GT/s\n"); break; 479 default: aprint_normal("Unknown link speed\n"); 480 } 481 } else { 482 aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n", 483 ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""), 484 (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64, 485 sc->bus_speed_mhz); 486 } 487 488 /* Firmware version and device features. */ 489 aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (", 490 sc->bnx_bc_ver, RX_PAGES, TX_PAGES); 491 492 if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) { 493 if (i > 0) aprint_normal("|"); 494 aprint_normal("2.5G"); i++; 495 } 496 497 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 498 if (i > 0) aprint_normal("|"); 499 aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver); 500 } else { 501 aprint_normal(")\n"); 502 } 503 504 aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 505 sc->bnx_rx_quick_cons_trip_int, 506 sc->bnx_rx_quick_cons_trip, 507 sc->bnx_rx_ticks_int, 508 sc->bnx_rx_ticks, 509 sc->bnx_tx_quick_cons_trip_int, 510 sc->bnx_tx_quick_cons_trip, 511 sc->bnx_tx_ticks_int, 512 sc->bnx_tx_ticks); 513 } 514 515 516 /****************************************************************************/ 517 /* PCI Capabilities Probe Function. */ 518 /* */ 519 /* Walks the PCI capabiites list for the device to find what features are */ 520 /* supported. */ 521 /* */ 522 /* Returns: */ 523 /* None. */ 524 /****************************************************************************/ 525 static void 526 bnx_probe_pci_caps(struct bnx_softc *sc) 527 { 528 struct pci_attach_args *pa = &(sc->bnx_pa); 529 pcireg_t reg; 530 531 /* Check if PCI-X capability is enabled. */ 532 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, ®, 533 NULL) != 0) { 534 sc->bnx_cap_flags |= BNX_PCIX_CAPABLE_FLAG; 535 } 536 537 /* Check if PCIe capability is enabled. */ 538 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, ®, 539 NULL) != 0) { 540 pcireg_t link_status = pci_conf_read(pa->pa_pc, pa->pa_tag, 541 reg + PCIE_LCSR); 542 DBPRINT(sc, BNX_INFO_LOAD, "PCIe link_status = " 543 "0x%08X\n", link_status); 544 sc->link_speed = (link_status & PCIE_LCSR_LINKSPEED) >> 16; 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; 546 sc->bnx_cap_flags |= BNX_PCIE_CAPABLE_FLAG; 547 sc->bnx_flags |= BNX_PCIE_FLAG; 548 } 549 550 /* Check if MSI capability is enabled. */ 551 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, ®, 552 NULL) != 0) 553 sc->bnx_cap_flags |= BNX_MSI_CAPABLE_FLAG; 554 555 /* Check if MSI-X capability is enabled. */ 556 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, ®, 557 NULL) != 0) 558 sc->bnx_cap_flags |= BNX_MSIX_CAPABLE_FLAG; 559 } 560 561 562 /****************************************************************************/ 563 /* Device attach function. */ 564 /* */ 565 /* Allocates device resources, performs secondary chip identification, */ 566 /* resets and initializes the hardware, and initializes driver instance */ 567 /* variables. */ 568 /* */ 569 /* Returns: */ 570 /* 0 on success, positive value on failure. */ 571 /****************************************************************************/ 572 void 573 bnx_attach(device_t parent, device_t self, void *aux) 574 { 575 const struct bnx_product *bp; 576 struct bnx_softc *sc = device_private(self); 577 prop_dictionary_t dict; 578 struct pci_attach_args *pa = aux; 579 pci_chipset_tag_t pc = pa->pa_pc; 580 const char *intrstr = NULL; 581 uint32_t command; 582 struct ifnet *ifp; 583 struct mii_data * const mii = &sc->bnx_mii; 584 uint32_t val; 585 int mii_flags = MIIF_FORCEANEG; 586 pcireg_t memtype; 587 char intrbuf[PCI_INTRSTR_LEN]; 588 int i, j; 589 590 if (bnx_tx_pool == NULL) { 591 bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_WAITOK); 592 pool_init(bnx_tx_pool, sizeof(struct bnx_pkt), 593 0, 0, 0, "bnxpkts", NULL, IPL_NET); 594 } 595 596 bp = bnx_lookup(pa); 597 if (bp == NULL) 598 panic("unknown device"); 599 600 sc->bnx_dev = self; 601 602 aprint_naive("\n"); 603 aprint_normal(": %s\n", bp->bp_name); 604 605 sc->bnx_pa = *pa; 606 607 /* 608 * Map control/status registers. 609 */ 610 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 611 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 612 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 613 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 614 615 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 616 aprint_error_dev(sc->bnx_dev, 617 "failed to enable memory mapping!\n"); 618 return; 619 } 620 621 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); 622 if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, 623 &sc->bnx_bhandle, NULL, &sc->bnx_size)) { 624 aprint_error_dev(sc->bnx_dev, "can't find mem space\n"); 625 return; 626 } 627 628 if (pci_intr_alloc(pa, &sc->bnx_ih, NULL, 0)) { 629 aprint_error_dev(sc->bnx_dev, "couldn't map interrupt\n"); 630 goto bnx_attach_fail; 631 } 632 intrstr = pci_intr_string(pc, sc->bnx_ih[0], intrbuf, sizeof(intrbuf)); 633 634 /* 635 * Configure byte swap and enable indirect register access. 636 * Rely on CPU to do target byte swapping on big endian systems. 637 * Access to registers outside of PCI configurtion space are not 638 * valid until this is done. 639 */ 640 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 641 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 642 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 643 644 /* Save ASIC revision info. */ 645 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); 646 647 /* 648 * Find the base address for shared memory access. 649 * Newer versions of bootcode use a signature and offset 650 * while older versions use a fixed address. 651 */ 652 val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); 653 if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) 654 sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 + 655 (sc->bnx_pa.pa_function << 2)); 656 else 657 sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; 658 659 DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); 660 661 /* Set initial device and PHY flags */ 662 sc->bnx_flags = 0; 663 sc->bnx_phy_flags = 0; 664 665 /* Fetch the bootcode revision. */ 666 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 667 for (i = 0, j = 0; i < 3; i++) { 668 uint8_t num; 669 int k, skip0; 670 671 num = (uint8_t)(val >> (24 - (i * 8))); 672 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 673 if (num >= k || !skip0 || k == 1) { 674 sc->bnx_bc_ver[j++] = (num / k) + '0'; 675 skip0 = 0; 676 } 677 } 678 if (i != 2) 679 sc->bnx_bc_ver[j++] = '.'; 680 } 681 682 /* Check if any management firmware is enabled. */ 683 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); 684 if (val & BNX_PORT_FEATURE_ASF_ENABLED) { 685 DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); 686 sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; 687 688 /* Allow time for firmware to enter the running state. */ 689 for (i = 0; i < 30; i++) { 690 val = REG_RD_IND(sc, sc->bnx_shmem_base + 691 BNX_BC_STATE_CONDITION); 692 if (val & BNX_CONDITION_MFW_RUN_MASK) 693 break; 694 DELAY(10000); 695 } 696 697 /* Check if management firmware is running. */ 698 val = REG_RD_IND(sc, sc->bnx_shmem_base + 699 BNX_BC_STATE_CONDITION); 700 val &= BNX_CONDITION_MFW_RUN_MASK; 701 if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) && 702 (val != BNX_CONDITION_MFW_RUN_NONE)) { 703 uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base + 704 BNX_MFW_VER_PTR); 705 706 /* Read the management firmware version string. */ 707 for (j = 0; j < 3; j++) { 708 val = bnx_reg_rd_ind(sc, addr + j * 4); 709 val = bswap32(val); 710 memcpy(&sc->bnx_mfw_ver[i], &val, 4); 711 i += 4; 712 } 713 } else { 714 /* May cause firmware synchronization timeouts. */ 715 BNX_PRINTF(sc, "%s(%d): Management firmware enabled " 716 "but not running!\n", __FILE__, __LINE__); 717 strcpy(sc->bnx_mfw_ver, "NOT RUNNING!"); 718 719 /* ToDo: Any action the driver should take? */ 720 } 721 } 722 723 bnx_probe_pci_caps(sc); 724 725 /* Get PCI bus information (speed and type). */ 726 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); 727 if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { 728 uint32_t clkreg; 729 730 sc->bnx_flags |= BNX_PCIX_FLAG; 731 732 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); 733 734 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 735 switch (clkreg) { 736 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 737 sc->bus_speed_mhz = 133; 738 break; 739 740 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 741 sc->bus_speed_mhz = 100; 742 break; 743 744 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 745 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 746 sc->bus_speed_mhz = 66; 747 break; 748 749 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 750 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 751 sc->bus_speed_mhz = 50; 752 break; 753 754 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 755 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 756 case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 757 sc->bus_speed_mhz = 33; 758 break; 759 } 760 } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) 761 sc->bus_speed_mhz = 66; 762 else 763 sc->bus_speed_mhz = 33; 764 765 if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) 766 sc->bnx_flags |= BNX_PCI_32BIT_FLAG; 767 768 /* Reset the controller. */ 769 if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) 770 goto bnx_attach_fail; 771 772 /* Initialize the controller. */ 773 if (bnx_chipinit(sc)) { 774 aprint_error_dev(sc->bnx_dev, 775 "Controller initialization failed!\n"); 776 goto bnx_attach_fail; 777 } 778 779 /* Perform NVRAM test. */ 780 if (bnx_nvram_test(sc)) { 781 aprint_error_dev(sc->bnx_dev, "NVRAM test failed!\n"); 782 goto bnx_attach_fail; 783 } 784 785 /* Fetch the permanent Ethernet MAC address. */ 786 bnx_get_mac_addr(sc); 787 aprint_normal_dev(sc->bnx_dev, "Ethernet address %s\n", 788 ether_sprintf(sc->eaddr)); 789 790 /* 791 * Trip points control how many BDs 792 * should be ready before generating an 793 * interrupt while ticks control how long 794 * a BD can sit in the chain before 795 * generating an interrupt. Set the default 796 * values for the RX and TX rings. 797 */ 798 799 #ifdef BNX_DEBUG 800 /* Force more frequent interrupts. */ 801 sc->bnx_tx_quick_cons_trip_int = 1; 802 sc->bnx_tx_quick_cons_trip = 1; 803 sc->bnx_tx_ticks_int = 0; 804 sc->bnx_tx_ticks = 0; 805 806 sc->bnx_rx_quick_cons_trip_int = 1; 807 sc->bnx_rx_quick_cons_trip = 1; 808 sc->bnx_rx_ticks_int = 0; 809 sc->bnx_rx_ticks = 0; 810 #else 811 sc->bnx_tx_quick_cons_trip_int = 20; 812 sc->bnx_tx_quick_cons_trip = 20; 813 sc->bnx_tx_ticks_int = 80; 814 sc->bnx_tx_ticks = 80; 815 816 sc->bnx_rx_quick_cons_trip_int = 6; 817 sc->bnx_rx_quick_cons_trip = 6; 818 sc->bnx_rx_ticks_int = 18; 819 sc->bnx_rx_ticks = 18; 820 #endif 821 822 /* Update statistics once every second. */ 823 sc->bnx_stats_ticks = 1000000 & 0xffff00; 824 825 /* Find the media type for the adapter. */ 826 bnx_get_media(sc); 827 828 /* 829 * Store config data needed by the PHY driver for 830 * backplane applications 831 */ 832 sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 833 BNX_SHARED_HW_CFG_CONFIG); 834 sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base + 835 BNX_PORT_HW_CFG_CONFIG); 836 837 /* Allocate DMA memory resources. */ 838 sc->bnx_dmatag = pa->pa_dmat; 839 if (bnx_dma_alloc(sc)) { 840 aprint_error_dev(sc->bnx_dev, 841 "DMA resource allocation failed!\n"); 842 goto bnx_attach_fail; 843 } 844 845 /* Initialize the ifnet interface. */ 846 ifp = &sc->bnx_ec.ec_if; 847 ifp->if_softc = sc; 848 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 849 ifp->if_ioctl = bnx_ioctl; 850 ifp->if_stop = bnx_stop; 851 ifp->if_start = bnx_start; 852 ifp->if_init = bnx_init; 853 ifp->if_watchdog = bnx_watchdog; 854 IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD - 1); 855 IFQ_SET_READY(&ifp->if_snd); 856 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 857 858 sc->bnx_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU | 859 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 860 sc->bnx_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 861 862 ifp->if_capabilities |= 863 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 864 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 865 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 866 867 /* create workqueue to handle packet allocations */ 868 if (workqueue_create(&sc->bnx_wq, device_xname(self), 869 bnx_alloc_pkts, sc, PRI_NONE, IPL_NET, 0) != 0) { 870 aprint_error_dev(self, "failed to create workqueue\n"); 871 goto bnx_attach_fail; 872 } 873 874 mii->mii_ifp = ifp; 875 mii->mii_readreg = bnx_miibus_read_reg; 876 mii->mii_writereg = bnx_miibus_write_reg; 877 mii->mii_statchg = bnx_miibus_statchg; 878 879 /* Handle any special PHY initialization for SerDes PHYs. */ 880 bnx_init_media(sc); 881 882 sc->bnx_ec.ec_mii = mii; 883 ifmedia_init(&mii->mii_media, 0, bnx_ifmedia_upd, bnx_ifmedia_sts); 884 885 /* set phyflags and chipid before mii_attach() */ 886 dict = device_properties(self); 887 prop_dictionary_set_uint32(dict, "phyflags", sc->bnx_phy_flags); 888 prop_dictionary_set_uint32(dict, "chipid", sc->bnx_chipid); 889 prop_dictionary_set_uint32(dict, "shared_hwcfg",sc->bnx_shared_hw_cfg); 890 prop_dictionary_set_uint32(dict, "port_hwcfg", sc->bnx_port_hw_cfg); 891 892 /* Print some useful adapter info */ 893 bnx_print_adapter_info(sc); 894 895 mii_flags |= MIIF_DOPAUSE; 896 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) 897 mii_flags |= MIIF_HAVEFIBER; 898 mii_attach(self, mii, 0xffffffff, 899 sc->bnx_phy_addr, MII_OFFSET_ANY, mii_flags); 900 901 if (LIST_EMPTY(&mii->mii_phys)) { 902 aprint_error_dev(self, "no PHY found!\n"); 903 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 904 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 905 } else 906 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 907 908 /* Attach to the Ethernet interface list. */ 909 if_attach(ifp); 910 if_deferred_start_init(ifp, NULL); 911 ether_ifattach(ifp, sc->eaddr); 912 913 callout_init(&sc->bnx_timeout, 0); 914 callout_setfunc(&sc->bnx_timeout, bnx_tick, sc); 915 916 /* Hookup IRQ last. */ 917 sc->bnx_intrhand = pci_intr_establish_xname(pc, sc->bnx_ih[0], IPL_NET, 918 bnx_intr, sc, device_xname(self)); 919 if (sc->bnx_intrhand == NULL) { 920 aprint_error_dev(self, "couldn't establish interrupt"); 921 if (intrstr != NULL) 922 aprint_error(" at %s", intrstr); 923 aprint_error("\n"); 924 goto bnx_attach_fail; 925 } 926 aprint_normal_dev(sc->bnx_dev, "interrupting at %s\n", intrstr); 927 928 if (pmf_device_register(self, NULL, NULL)) 929 pmf_class_network_register(self, ifp); 930 else 931 aprint_error_dev(self, "couldn't establish power handler\n"); 932 933 /* Print some important debugging info. */ 934 DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); 935 936 /* Get the firmware running so ASF still works. */ 937 bnx_mgmt_init(sc); 938 939 goto bnx_attach_exit; 940 941 bnx_attach_fail: 942 bnx_release_resources(sc); 943 944 bnx_attach_exit: 945 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 946 } 947 948 /****************************************************************************/ 949 /* Device detach function. */ 950 /* */ 951 /* Stops the controller, resets the controller, and releases resources. */ 952 /* */ 953 /* Returns: */ 954 /* 0 on success, positive value on failure. */ 955 /****************************************************************************/ 956 int 957 bnx_detach(device_t dev, int flags) 958 { 959 int s; 960 struct bnx_softc *sc; 961 struct ifnet *ifp; 962 963 sc = device_private(dev); 964 ifp = &sc->bnx_ec.ec_if; 965 966 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 967 968 /* Stop and reset the controller. */ 969 s = splnet(); 970 bnx_stop(ifp, 1); 971 splx(s); 972 973 pmf_device_deregister(dev); 974 callout_destroy(&sc->bnx_timeout); 975 ether_ifdetach(ifp); 976 workqueue_destroy(sc->bnx_wq); 977 978 if_detach(ifp); 979 mii_detach(&sc->bnx_mii, MII_PHY_ANY, MII_OFFSET_ANY); 980 981 /* Delete all remaining media. */ 982 ifmedia_fini(&sc->bnx_mii.mii_media); 983 984 /* Release all remaining resources. */ 985 bnx_release_resources(sc); 986 987 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 988 989 return 0; 990 } 991 992 /****************************************************************************/ 993 /* Indirect register read. */ 994 /* */ 995 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 996 /* configuration space. Using this mechanism avoids issues with posted */ 997 /* reads but is much slower than memory-mapped I/O. */ 998 /* */ 999 /* Returns: */ 1000 /* The value of the register. */ 1001 /****************************************************************************/ 1002 uint32_t 1003 bnx_reg_rd_ind(struct bnx_softc *sc, uint32_t offset) 1004 { 1005 struct pci_attach_args *pa = &(sc->bnx_pa); 1006 1007 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1008 offset); 1009 #ifdef BNX_DEBUG 1010 { 1011 uint32_t val; 1012 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 1013 BNX_PCICFG_REG_WINDOW); 1014 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " 1015 "val = 0x%08X\n", __func__, offset, val); 1016 return val; 1017 } 1018 #else 1019 return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); 1020 #endif 1021 } 1022 1023 /****************************************************************************/ 1024 /* Indirect register write. */ 1025 /* */ 1026 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1027 /* configuration space. Using this mechanism avoids issues with posted */ 1028 /* writes but is muchh slower than memory-mapped I/O. */ 1029 /* */ 1030 /* Returns: */ 1031 /* Nothing. */ 1032 /****************************************************************************/ 1033 void 1034 bnx_reg_wr_ind(struct bnx_softc *sc, uint32_t offset, uint32_t val) 1035 { 1036 struct pci_attach_args *pa = &(sc->bnx_pa); 1037 1038 DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 1039 __func__, offset, val); 1040 1041 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, 1042 offset); 1043 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); 1044 } 1045 1046 /****************************************************************************/ 1047 /* Context memory write. */ 1048 /* */ 1049 /* The NetXtreme II controller uses context memory to track connection */ 1050 /* information for L2 and higher network protocols. */ 1051 /* */ 1052 /* Returns: */ 1053 /* Nothing. */ 1054 /****************************************************************************/ 1055 void 1056 bnx_ctx_wr(struct bnx_softc *sc, uint32_t cid_addr, uint32_t ctx_offset, 1057 uint32_t ctx_val) 1058 { 1059 uint32_t idx, offset = ctx_offset + cid_addr; 1060 uint32_t val, retry_cnt = 5; 1061 1062 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1063 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1064 REG_WR(sc, BNX_CTX_CTX_CTRL, 1065 (offset | BNX_CTX_CTX_CTRL_WRITE_REQ)); 1066 1067 for (idx = 0; idx < retry_cnt; idx++) { 1068 val = REG_RD(sc, BNX_CTX_CTX_CTRL); 1069 if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0) 1070 break; 1071 DELAY(5); 1072 } 1073 1074 #if 0 1075 if (val & BNX_CTX_CTX_CTRL_WRITE_REQ) 1076 BNX_PRINTF("%s(%d); Unable to write CTX memory: " 1077 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1078 __FILE__, __LINE__, cid_addr, ctx_offset); 1079 #endif 1080 1081 } else { 1082 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1083 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1084 } 1085 } 1086 1087 /****************************************************************************/ 1088 /* PHY register read. */ 1089 /* */ 1090 /* Implements register reads on the MII bus. */ 1091 /* */ 1092 /* Returns: */ 1093 /* The value of the register. */ 1094 /****************************************************************************/ 1095 int 1096 bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val) 1097 { 1098 struct bnx_softc *sc = device_private(dev); 1099 uint32_t data; 1100 int i, rv = 0; 1101 1102 /* 1103 * The BCM5709S PHY is an IEEE Clause 45 PHY 1104 * with special mappings to work with IEEE 1105 * Clause 22 register accesses. 1106 */ 1107 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1108 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1109 reg += 0x10; 1110 } 1111 1112 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1113 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1114 data &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1115 1116 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1117 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1118 1119 DELAY(40); 1120 } 1121 1122 data = BNX_MIPHY(phy) | BNX_MIREG(reg) | 1123 BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | 1124 BNX_EMAC_MDIO_COMM_START_BUSY; 1125 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1126 1127 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1128 DELAY(10); 1129 1130 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1131 if (!(data & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1132 DELAY(5); 1133 1134 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1135 data &= BNX_EMAC_MDIO_COMM_DATA; 1136 1137 break; 1138 } 1139 } 1140 1141 if (data & BNX_EMAC_MDIO_COMM_START_BUSY) { 1142 BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " 1143 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1144 rv = ETIMEDOUT; 1145 } else { 1146 data = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1147 *val = data & 0xffff; 1148 1149 DBPRINT(sc, BNX_EXCESSIVE, 1150 "%s(): phy = %d, reg = 0x%04X, val = 0x%04hX\n", __func__, 1151 phy, (uint16_t) reg & 0xffff, *val); 1152 } 1153 1154 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1155 data = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1156 data |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1157 1158 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1159 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1160 1161 DELAY(40); 1162 } 1163 1164 return rv; 1165 } 1166 1167 /****************************************************************************/ 1168 /* PHY register write. */ 1169 /* */ 1170 /* Implements register writes on the MII bus. */ 1171 /* */ 1172 /* Returns: */ 1173 /* The value of the register. */ 1174 /****************************************************************************/ 1175 int 1176 bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val) 1177 { 1178 struct bnx_softc *sc = device_private(dev); 1179 uint32_t val1; 1180 int i, rv = 0; 1181 1182 DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " 1183 "val = 0x%04hX\n", __func__, 1184 phy, (uint16_t) reg & 0xffff, val); 1185 1186 /* 1187 * The BCM5709S PHY is an IEEE Clause 45 PHY 1188 * with special mappings to work with IEEE 1189 * Clause 22 register accesses. 1190 */ 1191 if ((sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1192 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1193 reg += 0x10; 1194 } 1195 1196 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1197 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1198 val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; 1199 1200 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1201 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1202 1203 DELAY(40); 1204 } 1205 1206 val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | 1207 BNX_EMAC_MDIO_COMM_COMMAND_WRITE | 1208 BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; 1209 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1210 1211 for (i = 0; i < BNX_PHY_TIMEOUT; i++) { 1212 DELAY(10); 1213 1214 val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); 1215 if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { 1216 DELAY(5); 1217 break; 1218 } 1219 } 1220 1221 if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { 1222 BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, 1223 __LINE__); 1224 rv = ETIMEDOUT; 1225 } 1226 1227 if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1228 val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); 1229 val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; 1230 1231 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1232 REG_RD(sc, BNX_EMAC_MDIO_MODE); 1233 1234 DELAY(40); 1235 } 1236 1237 return rv; 1238 } 1239 1240 /****************************************************************************/ 1241 /* MII bus status change. */ 1242 /* */ 1243 /* Called by the MII bus driver when the PHY establishes link to set the */ 1244 /* MAC interface registers. */ 1245 /* */ 1246 /* Returns: */ 1247 /* Nothing. */ 1248 /****************************************************************************/ 1249 void 1250 bnx_miibus_statchg(struct ifnet *ifp) 1251 { 1252 struct bnx_softc *sc = ifp->if_softc; 1253 struct mii_data *mii = &sc->bnx_mii; 1254 uint32_t rx_mode = sc->rx_mode; 1255 int val; 1256 1257 val = REG_RD(sc, BNX_EMAC_MODE); 1258 val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | 1259 BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | 1260 BNX_EMAC_MODE_25G); 1261 1262 /* 1263 * Get flow control negotiation result. 1264 */ 1265 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1266 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bnx_flowflags) { 1267 sc->bnx_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1268 mii->mii_media_active &= ~IFM_ETH_FMASK; 1269 } 1270 1271 /* Set MII or GMII interface based on the speed 1272 * negotiated by the PHY. 1273 */ 1274 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1275 case IFM_10_T: 1276 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 1277 DBPRINT(sc, BNX_INFO, "Enabling 10Mb interface.\n"); 1278 val |= BNX_EMAC_MODE_PORT_MII_10; 1279 break; 1280 } 1281 /* FALLTHROUGH */ 1282 case IFM_100_TX: 1283 DBPRINT(sc, BNX_INFO, "Enabling MII interface.\n"); 1284 val |= BNX_EMAC_MODE_PORT_MII; 1285 break; 1286 case IFM_2500_SX: 1287 DBPRINT(sc, BNX_INFO, "Enabling 2.5G MAC mode.\n"); 1288 val |= BNX_EMAC_MODE_25G; 1289 /* FALLTHROUGH */ 1290 case IFM_1000_T: 1291 case IFM_1000_SX: 1292 DBPRINT(sc, BNX_INFO, "Enabling GMII interface.\n"); 1293 val |= BNX_EMAC_MODE_PORT_GMII; 1294 break; 1295 default: 1296 val |= BNX_EMAC_MODE_PORT_GMII; 1297 break; 1298 } 1299 1300 /* Set half or full duplex based on the duplicity 1301 * negotiated by the PHY. 1302 */ 1303 if ((mii->mii_media_active & IFM_HDX) != 0) { 1304 DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); 1305 val |= BNX_EMAC_MODE_HALF_DUPLEX; 1306 } else 1307 DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); 1308 1309 REG_WR(sc, BNX_EMAC_MODE, val); 1310 1311 /* 1312 * 802.3x flow control 1313 */ 1314 if (sc->bnx_flowflags & IFM_ETH_RXPAUSE) { 1315 DBPRINT(sc, BNX_INFO, "Enabling RX mode flow control.\n"); 1316 rx_mode |= BNX_EMAC_RX_MODE_FLOW_EN; 1317 } else { 1318 DBPRINT(sc, BNX_INFO, "Disabling RX mode flow control.\n"); 1319 rx_mode &= ~BNX_EMAC_RX_MODE_FLOW_EN; 1320 } 1321 1322 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) { 1323 DBPRINT(sc, BNX_INFO, "Enabling TX mode flow control.\n"); 1324 BNX_SETBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1325 } else { 1326 DBPRINT(sc, BNX_INFO, "Disabling TX mode flow control.\n"); 1327 BNX_CLRBIT(sc, BNX_EMAC_TX_MODE, BNX_EMAC_TX_MODE_FLOW_EN); 1328 } 1329 1330 /* Only make changes if the receive mode has actually changed. */ 1331 if (rx_mode != sc->rx_mode) { 1332 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 1333 rx_mode); 1334 1335 sc->rx_mode = rx_mode; 1336 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 1337 1338 bnx_init_rx_context(sc); 1339 } 1340 } 1341 1342 /****************************************************************************/ 1343 /* Acquire NVRAM lock. */ 1344 /* */ 1345 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1346 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1347 /* for use by the driver. */ 1348 /* */ 1349 /* Returns: */ 1350 /* 0 on success, positive value on failure. */ 1351 /****************************************************************************/ 1352 int 1353 bnx_acquire_nvram_lock(struct bnx_softc *sc) 1354 { 1355 uint32_t val; 1356 int j; 1357 1358 DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); 1359 1360 /* Request access to the flash interface. */ 1361 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); 1362 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1363 val = REG_RD(sc, BNX_NVM_SW_ARB); 1364 if (val & BNX_NVM_SW_ARB_ARB_ARB2) 1365 break; 1366 1367 DELAY(5); 1368 } 1369 1370 if (j >= NVRAM_TIMEOUT_COUNT) { 1371 DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); 1372 return EBUSY; 1373 } 1374 1375 return 0; 1376 } 1377 1378 /****************************************************************************/ 1379 /* Release NVRAM lock. */ 1380 /* */ 1381 /* When the caller is finished accessing NVRAM the lock must be released. */ 1382 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1383 /* for use by the driver. */ 1384 /* */ 1385 /* Returns: */ 1386 /* 0 on success, positive value on failure. */ 1387 /****************************************************************************/ 1388 int 1389 bnx_release_nvram_lock(struct bnx_softc *sc) 1390 { 1391 int j; 1392 uint32_t val; 1393 1394 DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); 1395 1396 /* Relinquish nvram interface. */ 1397 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); 1398 1399 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1400 val = REG_RD(sc, BNX_NVM_SW_ARB); 1401 if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) 1402 break; 1403 1404 DELAY(5); 1405 } 1406 1407 if (j >= NVRAM_TIMEOUT_COUNT) { 1408 DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); 1409 return EBUSY; 1410 } 1411 1412 return 0; 1413 } 1414 1415 #ifdef BNX_NVRAM_WRITE_SUPPORT 1416 /****************************************************************************/ 1417 /* Enable NVRAM write access. */ 1418 /* */ 1419 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1420 /* */ 1421 /* Returns: */ 1422 /* 0 on success, positive value on failure. */ 1423 /****************************************************************************/ 1424 int 1425 bnx_enable_nvram_write(struct bnx_softc *sc) 1426 { 1427 uint32_t val; 1428 1429 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); 1430 1431 val = REG_RD(sc, BNX_MISC_CFG); 1432 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); 1433 1434 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 1435 int j; 1436 1437 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1438 REG_WR(sc, BNX_NVM_COMMAND, 1439 BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); 1440 1441 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1442 DELAY(5); 1443 1444 val = REG_RD(sc, BNX_NVM_COMMAND); 1445 if (val & BNX_NVM_COMMAND_DONE) 1446 break; 1447 } 1448 1449 if (j >= NVRAM_TIMEOUT_COUNT) { 1450 DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); 1451 return EBUSY; 1452 } 1453 } 1454 1455 return 0; 1456 } 1457 1458 /****************************************************************************/ 1459 /* Disable NVRAM write access. */ 1460 /* */ 1461 /* When the caller is finished writing to NVRAM write access must be */ 1462 /* disabled. */ 1463 /* */ 1464 /* Returns: */ 1465 /* Nothing. */ 1466 /****************************************************************************/ 1467 void 1468 bnx_disable_nvram_write(struct bnx_softc *sc) 1469 { 1470 uint32_t val; 1471 1472 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); 1473 1474 val = REG_RD(sc, BNX_MISC_CFG); 1475 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); 1476 } 1477 #endif 1478 1479 /****************************************************************************/ 1480 /* Enable NVRAM access. */ 1481 /* */ 1482 /* Before accessing NVRAM for read or write operations the caller must */ 1483 /* enabled NVRAM access. */ 1484 /* */ 1485 /* Returns: */ 1486 /* Nothing. */ 1487 /****************************************************************************/ 1488 void 1489 bnx_enable_nvram_access(struct bnx_softc *sc) 1490 { 1491 uint32_t val; 1492 1493 DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); 1494 1495 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1496 /* Enable both bits, even on read. */ 1497 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1498 val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); 1499 } 1500 1501 /****************************************************************************/ 1502 /* Disable NVRAM access. */ 1503 /* */ 1504 /* When the caller is finished accessing NVRAM access must be disabled. */ 1505 /* */ 1506 /* Returns: */ 1507 /* Nothing. */ 1508 /****************************************************************************/ 1509 void 1510 bnx_disable_nvram_access(struct bnx_softc *sc) 1511 { 1512 uint32_t val; 1513 1514 DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); 1515 1516 val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); 1517 1518 /* Disable both bits, even after read. */ 1519 REG_WR(sc, BNX_NVM_ACCESS_ENABLE, 1520 val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); 1521 } 1522 1523 #ifdef BNX_NVRAM_WRITE_SUPPORT 1524 /****************************************************************************/ 1525 /* Erase NVRAM page before writing. */ 1526 /* */ 1527 /* Non-buffered flash parts require that a page be erased before it is */ 1528 /* written. */ 1529 /* */ 1530 /* Returns: */ 1531 /* 0 on success, positive value on failure. */ 1532 /****************************************************************************/ 1533 int 1534 bnx_nvram_erase_page(struct bnx_softc *sc, uint32_t offset) 1535 { 1536 uint32_t cmd; 1537 int j; 1538 1539 /* Buffered flash doesn't require an erase. */ 1540 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) 1541 return 0; 1542 1543 DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); 1544 1545 /* Build an erase command. */ 1546 cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | 1547 BNX_NVM_COMMAND_DOIT; 1548 1549 /* 1550 * Clear the DONE bit separately, set the NVRAM address to erase, 1551 * and issue the erase command. 1552 */ 1553 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1554 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1555 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1556 1557 /* Wait for completion. */ 1558 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1559 uint32_t val; 1560 1561 DELAY(5); 1562 1563 val = REG_RD(sc, BNX_NVM_COMMAND); 1564 if (val & BNX_NVM_COMMAND_DONE) 1565 break; 1566 } 1567 1568 if (j >= NVRAM_TIMEOUT_COUNT) { 1569 DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); 1570 return EBUSY; 1571 } 1572 1573 return 0; 1574 } 1575 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1576 1577 /****************************************************************************/ 1578 /* Read a dword (32 bits) from NVRAM. */ 1579 /* */ 1580 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1581 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1582 /* */ 1583 /* Returns: */ 1584 /* 0 on success and the 32 bit value read, positive value on failure. */ 1585 /****************************************************************************/ 1586 int 1587 bnx_nvram_read_dword(struct bnx_softc *sc, uint32_t offset, 1588 uint8_t *ret_val, uint32_t cmd_flags) 1589 { 1590 uint32_t cmd; 1591 int i, rc = 0; 1592 1593 /* Build the command word. */ 1594 cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; 1595 1596 /* Calculate the offset for buffered flash if translation is used. */ 1597 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1598 offset = ((offset / sc->bnx_flash_info->page_size) << 1599 sc->bnx_flash_info->page_bits) + 1600 (offset % sc->bnx_flash_info->page_size); 1601 } 1602 1603 /* 1604 * Clear the DONE bit separately, set the address to read, 1605 * and issue the read. 1606 */ 1607 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1608 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1609 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1610 1611 /* Wait for completion. */ 1612 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1613 uint32_t val; 1614 1615 DELAY(5); 1616 1617 val = REG_RD(sc, BNX_NVM_COMMAND); 1618 if (val & BNX_NVM_COMMAND_DONE) { 1619 val = REG_RD(sc, BNX_NVM_READ); 1620 1621 val = be32toh(val); 1622 memcpy(ret_val, &val, 4); 1623 break; 1624 } 1625 } 1626 1627 /* Check for errors. */ 1628 if (i >= NVRAM_TIMEOUT_COUNT) { 1629 BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " 1630 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 1631 rc = EBUSY; 1632 } 1633 1634 return rc; 1635 } 1636 1637 #ifdef BNX_NVRAM_WRITE_SUPPORT 1638 /****************************************************************************/ 1639 /* Write a dword (32 bits) to NVRAM. */ 1640 /* */ 1641 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1642 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1643 /* enabled NVRAM write access. */ 1644 /* */ 1645 /* Returns: */ 1646 /* 0 on success, positive value on failure. */ 1647 /****************************************************************************/ 1648 int 1649 bnx_nvram_write_dword(struct bnx_softc *sc, uint32_t offset, uint8_t *val, 1650 uint32_t cmd_flags) 1651 { 1652 uint32_t cmd, val32; 1653 int j; 1654 1655 /* Build the command word. */ 1656 cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; 1657 1658 /* Calculate the offset for buffered flash if translation is used. */ 1659 if (ISSET(sc->bnx_flash_info->flags, BNX_NV_TRANSLATE)) { 1660 offset = ((offset / sc->bnx_flash_info->page_size) << 1661 sc->bnx_flash_info->page_bits) + 1662 (offset % sc->bnx_flash_info->page_size); 1663 } 1664 1665 /* 1666 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1667 * set the NVRAM address to write, and issue the write command 1668 */ 1669 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); 1670 memcpy(&val32, val, 4); 1671 val32 = htobe32(val32); 1672 REG_WR(sc, BNX_NVM_WRITE, val32); 1673 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); 1674 REG_WR(sc, BNX_NVM_COMMAND, cmd); 1675 1676 /* Wait for completion. */ 1677 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1678 DELAY(5); 1679 1680 if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) 1681 break; 1682 } 1683 if (j >= NVRAM_TIMEOUT_COUNT) { 1684 BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " 1685 "offset 0x%08X\n", __FILE__, __LINE__, offset); 1686 return EBUSY; 1687 } 1688 1689 return 0; 1690 } 1691 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 1692 1693 /****************************************************************************/ 1694 /* Initialize NVRAM access. */ 1695 /* */ 1696 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1697 /* access that device. */ 1698 /* */ 1699 /* Returns: */ 1700 /* 0 on success, positive value on failure. */ 1701 /****************************************************************************/ 1702 int 1703 bnx_init_nvram(struct bnx_softc *sc) 1704 { 1705 uint32_t val; 1706 int j, entry_count, rc = 0; 1707 struct flash_spec *flash; 1708 1709 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 1710 1711 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 1712 sc->bnx_flash_info = &flash_5709; 1713 goto bnx_init_nvram_get_flash_size; 1714 } 1715 1716 /* Determine the selected interface. */ 1717 val = REG_RD(sc, BNX_NVM_CFG1); 1718 1719 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1720 1721 /* 1722 * Flash reconfiguration is required to support additional 1723 * NVRAM devices not directly supported in hardware. 1724 * Check if the flash interface was reconfigured 1725 * by the bootcode. 1726 */ 1727 1728 if (val & 0x40000000) { 1729 /* Flash interface reconfigured by bootcode. */ 1730 1731 DBPRINT(sc, BNX_INFO_LOAD, 1732 "bnx_init_nvram(): Flash WAS reconfigured.\n"); 1733 1734 for (j = 0, flash = &flash_table[0]; j < entry_count; 1735 j++, flash++) { 1736 if ((val & FLASH_BACKUP_STRAP_MASK) == 1737 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1738 sc->bnx_flash_info = flash; 1739 break; 1740 } 1741 } 1742 } else { 1743 /* Flash interface not yet reconfigured. */ 1744 uint32_t mask; 1745 1746 DBPRINT(sc, BNX_INFO_LOAD, 1747 "bnx_init_nvram(): Flash was NOT reconfigured.\n"); 1748 1749 if (val & (1 << 23)) 1750 mask = FLASH_BACKUP_STRAP_MASK; 1751 else 1752 mask = FLASH_STRAP_MASK; 1753 1754 /* Look for the matching NVRAM device configuration data. */ 1755 for (j = 0, flash = &flash_table[0]; j < entry_count; 1756 j++, flash++) { 1757 /* Check if the dev matches any of the known devices. */ 1758 if ((val & mask) == (flash->strapping & mask)) { 1759 /* Found a device match. */ 1760 sc->bnx_flash_info = flash; 1761 1762 /* Request access to the flash interface. */ 1763 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1764 return rc; 1765 1766 /* Reconfigure the flash interface. */ 1767 bnx_enable_nvram_access(sc); 1768 REG_WR(sc, BNX_NVM_CFG1, flash->config1); 1769 REG_WR(sc, BNX_NVM_CFG2, flash->config2); 1770 REG_WR(sc, BNX_NVM_CFG3, flash->config3); 1771 REG_WR(sc, BNX_NVM_WRITE1, flash->write1); 1772 bnx_disable_nvram_access(sc); 1773 bnx_release_nvram_lock(sc); 1774 1775 break; 1776 } 1777 } 1778 } 1779 1780 /* Check if a matching device was found. */ 1781 if (j == entry_count) { 1782 sc->bnx_flash_info = NULL; 1783 BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1784 __FILE__, __LINE__); 1785 rc = ENODEV; 1786 } 1787 1788 bnx_init_nvram_get_flash_size: 1789 /* Write the flash config data to the shared memory interface. */ 1790 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); 1791 val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; 1792 if (val) 1793 sc->bnx_flash_size = val; 1794 else 1795 sc->bnx_flash_size = sc->bnx_flash_info->total_size; 1796 1797 DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " 1798 "0x%08X\n", sc->bnx_flash_info->total_size); 1799 1800 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 1801 1802 return rc; 1803 } 1804 1805 /****************************************************************************/ 1806 /* Read an arbitrary range of data from NVRAM. */ 1807 /* */ 1808 /* Prepares the NVRAM interface for access and reads the requested data */ 1809 /* into the supplied buffer. */ 1810 /* */ 1811 /* Returns: */ 1812 /* 0 on success and the data read, positive value on failure. */ 1813 /****************************************************************************/ 1814 int 1815 bnx_nvram_read(struct bnx_softc *sc, uint32_t offset, uint8_t *ret_buf, 1816 int buf_size) 1817 { 1818 int rc = 0; 1819 uint32_t cmd_flags, offset32, len32, extra; 1820 1821 if (buf_size == 0) 1822 return 0; 1823 1824 /* Request access to the flash interface. */ 1825 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1826 return rc; 1827 1828 /* Enable access to flash interface */ 1829 bnx_enable_nvram_access(sc); 1830 1831 len32 = buf_size; 1832 offset32 = offset; 1833 extra = 0; 1834 1835 cmd_flags = 0; 1836 1837 if (offset32 & 3) { 1838 uint8_t buf[4]; 1839 uint32_t pre_len; 1840 1841 offset32 &= ~3; 1842 pre_len = 4 - (offset & 3); 1843 1844 if (pre_len >= len32) { 1845 pre_len = len32; 1846 cmd_flags = 1847 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1848 } else 1849 cmd_flags = BNX_NVM_COMMAND_FIRST; 1850 1851 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1852 1853 if (rc) 1854 return rc; 1855 1856 memcpy(ret_buf, buf + (offset & 3), pre_len); 1857 1858 offset32 += 4; 1859 ret_buf += pre_len; 1860 len32 -= pre_len; 1861 } 1862 1863 if (len32 & 3) { 1864 extra = 4 - (len32 & 3); 1865 len32 = (len32 + 4) & ~3; 1866 } 1867 1868 if (len32 == 4) { 1869 uint8_t buf[4]; 1870 1871 if (cmd_flags) 1872 cmd_flags = BNX_NVM_COMMAND_LAST; 1873 else 1874 cmd_flags = 1875 BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; 1876 1877 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1878 1879 memcpy(ret_buf, buf, 4 - extra); 1880 } else if (len32 > 0) { 1881 uint8_t buf[4]; 1882 1883 /* Read the first word. */ 1884 if (cmd_flags) 1885 cmd_flags = 0; 1886 else 1887 cmd_flags = BNX_NVM_COMMAND_FIRST; 1888 1889 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1890 1891 /* Advance to the next dword. */ 1892 offset32 += 4; 1893 ret_buf += 4; 1894 len32 -= 4; 1895 1896 while (len32 > 4 && rc == 0) { 1897 rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); 1898 1899 /* Advance to the next dword. */ 1900 offset32 += 4; 1901 ret_buf += 4; 1902 len32 -= 4; 1903 } 1904 1905 if (rc) 1906 return rc; 1907 1908 cmd_flags = BNX_NVM_COMMAND_LAST; 1909 rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); 1910 1911 memcpy(ret_buf, buf, 4 - extra); 1912 } 1913 1914 /* Disable access to flash interface and release the lock. */ 1915 bnx_disable_nvram_access(sc); 1916 bnx_release_nvram_lock(sc); 1917 1918 return rc; 1919 } 1920 1921 #ifdef BNX_NVRAM_WRITE_SUPPORT 1922 /****************************************************************************/ 1923 /* Write an arbitrary range of data from NVRAM. */ 1924 /* */ 1925 /* Prepares the NVRAM interface for write access and writes the requested */ 1926 /* data from the supplied buffer. The caller is responsible for */ 1927 /* calculating any appropriate CRCs. */ 1928 /* */ 1929 /* Returns: */ 1930 /* 0 on success, positive value on failure. */ 1931 /****************************************************************************/ 1932 int 1933 bnx_nvram_write(struct bnx_softc *sc, uint32_t offset, uint8_t *data_buf, 1934 int buf_size) 1935 { 1936 uint32_t written, offset32, len32; 1937 uint8_t *buf, start[4], end[4]; 1938 int rc = 0; 1939 int align_start, align_end; 1940 1941 buf = data_buf; 1942 offset32 = offset; 1943 len32 = buf_size; 1944 align_start = align_end = 0; 1945 1946 if ((align_start = (offset32 & 3))) { 1947 offset32 &= ~3; 1948 len32 += align_start; 1949 if ((rc = bnx_nvram_read(sc, offset32, start, 4))) 1950 return rc; 1951 } 1952 1953 if (len32 & 3) { 1954 if ((len32 > 4) || !align_start) { 1955 align_end = 4 - (len32 & 3); 1956 len32 += align_end; 1957 if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, 1958 end, 4))) 1959 return rc; 1960 } 1961 } 1962 1963 if (align_start || align_end) { 1964 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1965 if (buf == NULL) 1966 return ENOMEM; 1967 1968 if (align_start) 1969 memcpy(buf, start, 4); 1970 1971 if (align_end) 1972 memcpy(buf + len32 - 4, end, 4); 1973 1974 memcpy(buf + align_start, data_buf, buf_size); 1975 } 1976 1977 written = 0; 1978 while ((written < len32) && (rc == 0)) { 1979 uint32_t page_start, page_end, data_start, data_end; 1980 uint32_t addr, cmd_flags; 1981 int i; 1982 uint8_t flash_buffer[264]; 1983 1984 /* Find the page_start addr */ 1985 page_start = offset32 + written; 1986 page_start -= (page_start % sc->bnx_flash_info->page_size); 1987 /* Find the page_end addr */ 1988 page_end = page_start + sc->bnx_flash_info->page_size; 1989 /* Find the data_start addr */ 1990 data_start = (written == 0) ? offset32 : page_start; 1991 /* Find the data_end addr */ 1992 data_end = (page_end > offset32 + len32) ? 1993 (offset32 + len32) : page_end; 1994 1995 /* Request access to the flash interface. */ 1996 if ((rc = bnx_acquire_nvram_lock(sc)) != 0) 1997 goto nvram_write_end; 1998 1999 /* Enable access to flash interface */ 2000 bnx_enable_nvram_access(sc); 2001 2002 cmd_flags = BNX_NVM_COMMAND_FIRST; 2003 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2004 int j; 2005 2006 /* Read the whole page into the buffer 2007 * (non-buffer flash only) */ 2008 for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { 2009 if (j == (sc->bnx_flash_info->page_size - 4)) 2010 cmd_flags |= BNX_NVM_COMMAND_LAST; 2011 2012 rc = bnx_nvram_read_dword(sc, 2013 page_start + j, 2014 &flash_buffer[j], 2015 cmd_flags); 2016 2017 if (rc) 2018 goto nvram_write_end; 2019 2020 cmd_flags = 0; 2021 } 2022 } 2023 2024 /* Enable writes to flash interface (unlock write-protect) */ 2025 if ((rc = bnx_enable_nvram_write(sc)) != 0) 2026 goto nvram_write_end; 2027 2028 /* Erase the page */ 2029 if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) 2030 goto nvram_write_end; 2031 2032 /* Re-enable the write again for the actual write */ 2033 bnx_enable_nvram_write(sc); 2034 2035 /* Loop to write back the buffer data from page_start to 2036 * data_start */ 2037 i = 0; 2038 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2039 for (addr = page_start; addr < data_start; 2040 addr += 4, i += 4) { 2041 2042 rc = bnx_nvram_write_dword(sc, addr, 2043 &flash_buffer[i], cmd_flags); 2044 2045 if (rc != 0) 2046 goto nvram_write_end; 2047 2048 cmd_flags = 0; 2049 } 2050 } 2051 2052 /* Loop to write the new data from data_start to data_end */ 2053 for (addr = data_start; addr < data_end; addr += 4, i++) { 2054 if ((addr == page_end - 4) || 2055 (ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED) 2056 && (addr == data_end - 4))) { 2057 2058 cmd_flags |= BNX_NVM_COMMAND_LAST; 2059 } 2060 2061 rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); 2062 2063 if (rc != 0) 2064 goto nvram_write_end; 2065 2066 cmd_flags = 0; 2067 buf += 4; 2068 } 2069 2070 /* Loop to write back the buffer data from data_end 2071 * to page_end */ 2072 if (!ISSET(sc->bnx_flash_info->flags, BNX_NV_BUFFERED)) { 2073 for (addr = data_end; addr < page_end; 2074 addr += 4, i += 4) { 2075 2076 if (addr == page_end-4) 2077 cmd_flags = BNX_NVM_COMMAND_LAST; 2078 2079 rc = bnx_nvram_write_dword(sc, addr, 2080 &flash_buffer[i], cmd_flags); 2081 2082 if (rc != 0) 2083 goto nvram_write_end; 2084 2085 cmd_flags = 0; 2086 } 2087 } 2088 2089 /* Disable writes to flash interface (lock write-protect) */ 2090 bnx_disable_nvram_write(sc); 2091 2092 /* Disable access to flash interface */ 2093 bnx_disable_nvram_access(sc); 2094 bnx_release_nvram_lock(sc); 2095 2096 /* Increment written */ 2097 written += data_end - data_start; 2098 } 2099 2100 nvram_write_end: 2101 if (align_start || align_end) 2102 free(buf, M_DEVBUF); 2103 2104 return rc; 2105 } 2106 #endif /* BNX_NVRAM_WRITE_SUPPORT */ 2107 2108 /****************************************************************************/ 2109 /* Verifies that NVRAM is accessible and contains valid data. */ 2110 /* */ 2111 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2112 /* correct. */ 2113 /* */ 2114 /* Returns: */ 2115 /* 0 on success, positive value on failure. */ 2116 /****************************************************************************/ 2117 int 2118 bnx_nvram_test(struct bnx_softc *sc) 2119 { 2120 uint32_t buf[BNX_NVRAM_SIZE / 4]; 2121 uint8_t *data = (uint8_t *) buf; 2122 int rc = 0; 2123 uint32_t magic, csum; 2124 2125 /* 2126 * Check that the device NVRAM is valid by reading 2127 * the magic value at offset 0. 2128 */ 2129 if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) 2130 goto bnx_nvram_test_done; 2131 2132 magic = be32toh(buf[0]); 2133 if (magic != BNX_NVRAM_MAGIC) { 2134 rc = ENODEV; 2135 BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " 2136 "Expected: 0x%08X, Found: 0x%08X\n", 2137 __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); 2138 goto bnx_nvram_test_done; 2139 } 2140 2141 /* 2142 * Verify that the device NVRAM includes valid 2143 * configuration data. 2144 */ 2145 if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) 2146 goto bnx_nvram_test_done; 2147 2148 csum = ether_crc32_le(data, 0x100); 2149 if (csum != BNX_CRC32_RESIDUAL) { 2150 rc = ENODEV; 2151 BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " 2152 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2153 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2154 goto bnx_nvram_test_done; 2155 } 2156 2157 csum = ether_crc32_le(data + 0x100, 0x100); 2158 if (csum != BNX_CRC32_RESIDUAL) { 2159 BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " 2160 "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2161 __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); 2162 rc = ENODEV; 2163 } 2164 2165 bnx_nvram_test_done: 2166 return rc; 2167 } 2168 2169 /****************************************************************************/ 2170 /* Identifies the current media type of the controller and sets the PHY */ 2171 /* address. */ 2172 /* */ 2173 /* Returns: */ 2174 /* Nothing. */ 2175 /****************************************************************************/ 2176 void 2177 bnx_get_media(struct bnx_softc *sc) 2178 { 2179 sc->bnx_phy_addr = 1; 2180 2181 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2182 uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); 2183 uint32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2184 uint32_t strap; 2185 2186 /* 2187 * The BCM5709S is software configurable 2188 * for Copper or SerDes operation. 2189 */ 2190 if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2191 DBPRINT(sc, BNX_INFO_LOAD, 2192 "5709 bonded for copper.\n"); 2193 goto bnx_get_media_exit; 2194 } else if (bond_id == BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2195 DBPRINT(sc, BNX_INFO_LOAD, 2196 "5709 bonded for dual media.\n"); 2197 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2198 goto bnx_get_media_exit; 2199 } 2200 2201 if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2202 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2203 else { 2204 strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) 2205 >> 8; 2206 } 2207 2208 if (sc->bnx_pa.pa_function == 0) { 2209 switch (strap) { 2210 case 0x4: 2211 case 0x5: 2212 case 0x6: 2213 DBPRINT(sc, BNX_INFO_LOAD, 2214 "BCM5709 s/w configured for SerDes.\n"); 2215 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2216 break; 2217 default: 2218 DBPRINT(sc, BNX_INFO_LOAD, 2219 "BCM5709 s/w configured for Copper.\n"); 2220 } 2221 } else { 2222 switch (strap) { 2223 case 0x1: 2224 case 0x2: 2225 case 0x4: 2226 DBPRINT(sc, BNX_INFO_LOAD, 2227 "BCM5709 s/w configured for SerDes.\n"); 2228 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2229 break; 2230 default: 2231 DBPRINT(sc, BNX_INFO_LOAD, 2232 "BCM5709 s/w configured for Copper.\n"); 2233 } 2234 } 2235 2236 } else if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) 2237 sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; 2238 2239 if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { 2240 uint32_t val; 2241 2242 sc->bnx_flags |= BNX_NO_WOL_FLAG; 2243 2244 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) 2245 sc->bnx_phy_flags |= BNX_PHY_IEEE_CLAUSE_45_FLAG; 2246 2247 /* 2248 * The BCM5708S, BCM5709S, and BCM5716S controllers use a 2249 * separate PHY for SerDes. 2250 */ 2251 if (BNX_CHIP_NUM(sc) != BNX_CHIP_NUM_5706) { 2252 sc->bnx_phy_addr = 2; 2253 val = REG_RD_IND(sc, sc->bnx_shmem_base + 2254 BNX_SHARED_HW_CFG_CONFIG); 2255 if (val & BNX_SHARED_HW_CFG_PHY_2_5G) { 2256 sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; 2257 DBPRINT(sc, BNX_INFO_LOAD, 2258 "Found 2.5Gb capable adapter\n"); 2259 } 2260 } 2261 } else if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 2262 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) 2263 sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; 2264 2265 bnx_get_media_exit: 2266 DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), 2267 "Using PHY address %d.\n", sc->bnx_phy_addr); 2268 } 2269 2270 /****************************************************************************/ 2271 /* Performs PHY initialization required before MII drivers access the */ 2272 /* device. */ 2273 /* */ 2274 /* Returns: */ 2275 /* Nothing. */ 2276 /****************************************************************************/ 2277 void 2278 bnx_init_media(struct bnx_softc *sc) 2279 { 2280 if (sc->bnx_phy_flags & BNX_PHY_IEEE_CLAUSE_45_FLAG) { 2281 /* 2282 * Configure the BCM5709S / BCM5716S PHYs to use traditional 2283 * IEEE Clause 22 method. Otherwise we have no way to attach 2284 * the PHY to the mii(4) layer. PHY specific configuration 2285 * is done by the mii(4) layer. 2286 */ 2287 2288 /* Select auto-negotiation MMD of the PHY. */ 2289 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2290 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2291 2292 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2293 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2294 2295 bnx_miibus_write_reg(sc->bnx_dev, sc->bnx_phy_addr, 2296 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2297 } 2298 } 2299 2300 /****************************************************************************/ 2301 /* Free any DMA memory owned by the driver. */ 2302 /* */ 2303 /* Scans through each data structre that requires DMA memory and frees */ 2304 /* the memory if allocated. */ 2305 /* */ 2306 /* Returns: */ 2307 /* Nothing. */ 2308 /****************************************************************************/ 2309 void 2310 bnx_dma_free(struct bnx_softc *sc) 2311 { 2312 int i; 2313 2314 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2315 2316 /* Destroy the status block. */ 2317 if (sc->status_block != NULL && sc->status_map != NULL) { 2318 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2319 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2320 bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); 2321 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->status_block, 2322 BNX_STATUS_BLK_SZ); 2323 bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, 2324 sc->status_rseg); 2325 bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); 2326 sc->status_block = NULL; 2327 sc->status_map = NULL; 2328 } 2329 2330 /* Destroy the statistics block. */ 2331 if (sc->stats_block != NULL && sc->stats_map != NULL) { 2332 bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); 2333 bus_dmamem_unmap(sc->bnx_dmatag, (void *)sc->stats_block, 2334 BNX_STATS_BLK_SZ); 2335 bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, 2336 sc->stats_rseg); 2337 bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); 2338 sc->stats_block = NULL; 2339 sc->stats_map = NULL; 2340 } 2341 2342 /* Free, unmap and destroy all context memory pages. */ 2343 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2344 for (i = 0; i < sc->ctx_pages; i++) { 2345 if (sc->ctx_block[i] != NULL) { 2346 bus_dmamap_unload(sc->bnx_dmatag, 2347 sc->ctx_map[i]); 2348 bus_dmamem_unmap(sc->bnx_dmatag, 2349 (void *)sc->ctx_block[i], 2350 BCM_PAGE_SIZE); 2351 bus_dmamem_free(sc->bnx_dmatag, 2352 &sc->ctx_segs[i], sc->ctx_rsegs[i]); 2353 bus_dmamap_destroy(sc->bnx_dmatag, 2354 sc->ctx_map[i]); 2355 sc->ctx_block[i] = NULL; 2356 } 2357 } 2358 } 2359 2360 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2361 for (i = 0; i < TX_PAGES; i++ ) { 2362 if (sc->tx_bd_chain[i] != NULL && 2363 sc->tx_bd_chain_map[i] != NULL) { 2364 bus_dmamap_unload(sc->bnx_dmatag, 2365 sc->tx_bd_chain_map[i]); 2366 bus_dmamem_unmap(sc->bnx_dmatag, 2367 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); 2368 bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2369 sc->tx_bd_chain_rseg[i]); 2370 bus_dmamap_destroy(sc->bnx_dmatag, 2371 sc->tx_bd_chain_map[i]); 2372 sc->tx_bd_chain[i] = NULL; 2373 sc->tx_bd_chain_map[i] = NULL; 2374 } 2375 } 2376 2377 /* Destroy the TX dmamaps. */ 2378 struct bnx_pkt *pkt; 2379 while ((pkt = TAILQ_FIRST(&sc->tx_free_pkts)) != NULL) { 2380 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 2381 sc->tx_pkt_count--; 2382 2383 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 2384 pool_put(bnx_tx_pool, pkt); 2385 } 2386 2387 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2388 for (i = 0; i < RX_PAGES; i++ ) { 2389 if (sc->rx_bd_chain[i] != NULL && 2390 sc->rx_bd_chain_map[i] != NULL) { 2391 bus_dmamap_unload(sc->bnx_dmatag, 2392 sc->rx_bd_chain_map[i]); 2393 bus_dmamem_unmap(sc->bnx_dmatag, 2394 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); 2395 bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2396 sc->rx_bd_chain_rseg[i]); 2397 2398 bus_dmamap_destroy(sc->bnx_dmatag, 2399 sc->rx_bd_chain_map[i]); 2400 sc->rx_bd_chain[i] = NULL; 2401 sc->rx_bd_chain_map[i] = NULL; 2402 } 2403 } 2404 2405 /* Unload and destroy the RX mbuf maps. */ 2406 for (i = 0; i < TOTAL_RX_BD; i++) { 2407 if (sc->rx_mbuf_map[i] != NULL) { 2408 bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2409 bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); 2410 } 2411 } 2412 2413 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2414 } 2415 2416 /****************************************************************************/ 2417 /* Allocate any DMA memory needed by the driver. */ 2418 /* */ 2419 /* Allocates DMA memory needed for the various global structures needed by */ 2420 /* hardware. */ 2421 /* */ 2422 /* Returns: */ 2423 /* 0 for success, positive value for failure. */ 2424 /****************************************************************************/ 2425 int 2426 bnx_dma_alloc(struct bnx_softc *sc) 2427 { 2428 int i, rc = 0; 2429 2430 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2431 2432 /* 2433 * Allocate DMA memory for the status block, map the memory into DMA 2434 * space, and fetch the physical address of the block. 2435 */ 2436 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, 2437 BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { 2438 aprint_error_dev(sc->bnx_dev, 2439 "Could not create status block DMA map!\n"); 2440 rc = ENOMEM; 2441 goto bnx_dma_alloc_exit; 2442 } 2443 2444 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 2445 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, 2446 &sc->status_rseg, BUS_DMA_NOWAIT)) { 2447 aprint_error_dev(sc->bnx_dev, 2448 "Could not allocate status block DMA memory!\n"); 2449 rc = ENOMEM; 2450 goto bnx_dma_alloc_exit; 2451 } 2452 2453 if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, 2454 BNX_STATUS_BLK_SZ, (void **)&sc->status_block, BUS_DMA_NOWAIT)) { 2455 aprint_error_dev(sc->bnx_dev, 2456 "Could not map status block DMA memory!\n"); 2457 rc = ENOMEM; 2458 goto bnx_dma_alloc_exit; 2459 } 2460 2461 if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, 2462 sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2463 aprint_error_dev(sc->bnx_dev, 2464 "Could not load status block DMA memory!\n"); 2465 rc = ENOMEM; 2466 goto bnx_dma_alloc_exit; 2467 } 2468 2469 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 2470 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2471 2472 sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; 2473 memset(sc->status_block, 0, BNX_STATUS_BLK_SZ); 2474 2475 /* DRC - Fix for 64 bit addresses. */ 2476 DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", 2477 (uint32_t) sc->status_block_paddr); 2478 2479 /* BCM5709 uses host memory as cache for context memory. */ 2480 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 2481 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 2482 if (sc->ctx_pages == 0) 2483 sc->ctx_pages = 1; 2484 if (sc->ctx_pages > 4) /* XXX */ 2485 sc->ctx_pages = 4; 2486 2487 DBRUNIF((sc->ctx_pages > 512), 2488 BNX_PRINTF(sc, "%s(%d): Too many CTX pages! %d > 512\n", 2489 __FILE__, __LINE__, sc->ctx_pages)); 2490 2491 2492 for (i = 0; i < sc->ctx_pages; i++) { 2493 if (bus_dmamap_create(sc->bnx_dmatag, BCM_PAGE_SIZE, 2494 1, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, 2495 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2496 &sc->ctx_map[i]) != 0) { 2497 rc = ENOMEM; 2498 goto bnx_dma_alloc_exit; 2499 } 2500 2501 if (bus_dmamem_alloc(sc->bnx_dmatag, BCM_PAGE_SIZE, 2502 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->ctx_segs[i], 2503 1, &sc->ctx_rsegs[i], BUS_DMA_NOWAIT) != 0) { 2504 rc = ENOMEM; 2505 goto bnx_dma_alloc_exit; 2506 } 2507 2508 if (bus_dmamem_map(sc->bnx_dmatag, &sc->ctx_segs[i], 2509 sc->ctx_rsegs[i], BCM_PAGE_SIZE, 2510 &sc->ctx_block[i], BUS_DMA_NOWAIT) != 0) { 2511 rc = ENOMEM; 2512 goto bnx_dma_alloc_exit; 2513 } 2514 2515 if (bus_dmamap_load(sc->bnx_dmatag, sc->ctx_map[i], 2516 sc->ctx_block[i], BCM_PAGE_SIZE, NULL, 2517 BUS_DMA_NOWAIT) != 0) { 2518 rc = ENOMEM; 2519 goto bnx_dma_alloc_exit; 2520 } 2521 2522 bzero(sc->ctx_block[i], BCM_PAGE_SIZE); 2523 } 2524 } 2525 2526 /* 2527 * Allocate DMA memory for the statistics block, map the memory into 2528 * DMA space, and fetch the physical address of the block. 2529 */ 2530 if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, 2531 BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { 2532 aprint_error_dev(sc->bnx_dev, 2533 "Could not create stats block DMA map!\n"); 2534 rc = ENOMEM; 2535 goto bnx_dma_alloc_exit; 2536 } 2537 2538 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 2539 BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, 2540 &sc->stats_rseg, BUS_DMA_NOWAIT)) { 2541 aprint_error_dev(sc->bnx_dev, 2542 "Could not allocate stats block DMA memory!\n"); 2543 rc = ENOMEM; 2544 goto bnx_dma_alloc_exit; 2545 } 2546 2547 if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, 2548 BNX_STATS_BLK_SZ, (void **)&sc->stats_block, BUS_DMA_NOWAIT)) { 2549 aprint_error_dev(sc->bnx_dev, 2550 "Could not map stats block DMA memory!\n"); 2551 rc = ENOMEM; 2552 goto bnx_dma_alloc_exit; 2553 } 2554 2555 if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, 2556 sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { 2557 aprint_error_dev(sc->bnx_dev, 2558 "Could not load status block DMA memory!\n"); 2559 rc = ENOMEM; 2560 goto bnx_dma_alloc_exit; 2561 } 2562 2563 sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; 2564 memset(sc->stats_block, 0, BNX_STATS_BLK_SZ); 2565 2566 /* DRC - Fix for 64 bit address. */ 2567 DBPRINT(sc, BNX_INFO, "stats_block_paddr = 0x%08X\n", 2568 (uint32_t) sc->stats_block_paddr); 2569 2570 /* 2571 * Allocate DMA memory for the TX buffer descriptor chain, 2572 * and fetch the physical address of the block. 2573 */ 2574 for (i = 0; i < TX_PAGES; i++) { 2575 if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, 2576 BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2577 &sc->tx_bd_chain_map[i])) { 2578 aprint_error_dev(sc->bnx_dev, 2579 "Could not create Tx desc %d DMA map!\n", i); 2580 rc = ENOMEM; 2581 goto bnx_dma_alloc_exit; 2582 } 2583 2584 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 2585 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, 2586 &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2587 aprint_error_dev(sc->bnx_dev, 2588 "Could not allocate TX desc %d DMA memory!\n", 2589 i); 2590 rc = ENOMEM; 2591 goto bnx_dma_alloc_exit; 2592 } 2593 2594 if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], 2595 sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, 2596 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { 2597 aprint_error_dev(sc->bnx_dev, 2598 "Could not map TX desc %d DMA memory!\n", i); 2599 rc = ENOMEM; 2600 goto bnx_dma_alloc_exit; 2601 } 2602 2603 if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 2604 (void *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, 2605 BUS_DMA_NOWAIT)) { 2606 aprint_error_dev(sc->bnx_dev, 2607 "Could not load TX desc %d DMA memory!\n", i); 2608 rc = ENOMEM; 2609 goto bnx_dma_alloc_exit; 2610 } 2611 2612 sc->tx_bd_chain_paddr[i] = 2613 sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; 2614 2615 /* DRC - Fix for 64 bit systems. */ 2616 DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2617 i, (uint32_t) sc->tx_bd_chain_paddr[i]); 2618 } 2619 2620 /* 2621 * Create lists to hold TX mbufs. 2622 */ 2623 TAILQ_INIT(&sc->tx_free_pkts); 2624 TAILQ_INIT(&sc->tx_used_pkts); 2625 sc->tx_pkt_count = 0; 2626 mutex_init(&sc->tx_pkt_mtx, MUTEX_DEFAULT, IPL_NET); 2627 2628 /* 2629 * Allocate DMA memory for the Rx buffer descriptor chain, 2630 * and fetch the physical address of the block. 2631 */ 2632 for (i = 0; i < RX_PAGES; i++) { 2633 if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, 2634 BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, 2635 &sc->rx_bd_chain_map[i])) { 2636 aprint_error_dev(sc->bnx_dev, 2637 "Could not create Rx desc %d DMA map!\n", i); 2638 rc = ENOMEM; 2639 goto bnx_dma_alloc_exit; 2640 } 2641 2642 if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 2643 BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, 2644 &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { 2645 aprint_error_dev(sc->bnx_dev, 2646 "Could not allocate Rx desc %d DMA memory!\n", i); 2647 rc = ENOMEM; 2648 goto bnx_dma_alloc_exit; 2649 } 2650 2651 if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], 2652 sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, 2653 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { 2654 aprint_error_dev(sc->bnx_dev, 2655 "Could not map Rx desc %d DMA memory!\n", i); 2656 rc = ENOMEM; 2657 goto bnx_dma_alloc_exit; 2658 } 2659 2660 if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2661 (void *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, 2662 BUS_DMA_NOWAIT)) { 2663 aprint_error_dev(sc->bnx_dev, 2664 "Could not load Rx desc %d DMA memory!\n", i); 2665 rc = ENOMEM; 2666 goto bnx_dma_alloc_exit; 2667 } 2668 2669 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 2670 sc->rx_bd_chain_paddr[i] = 2671 sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; 2672 2673 /* DRC - Fix for 64 bit systems. */ 2674 DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2675 i, (uint32_t) sc->rx_bd_chain_paddr[i]); 2676 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 2677 0, BNX_RX_CHAIN_PAGE_SZ, 2678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2679 } 2680 2681 /* 2682 * Create DMA maps for the Rx buffer mbufs. 2683 */ 2684 for (i = 0; i < TOTAL_RX_BD; i++) { 2685 if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_JUMBO_MRU, 2686 BNX_MAX_SEGMENTS, BNX_MAX_JUMBO_MRU, 0, BUS_DMA_NOWAIT, 2687 &sc->rx_mbuf_map[i])) { 2688 aprint_error_dev(sc->bnx_dev, 2689 "Could not create Rx mbuf %d DMA map!\n", i); 2690 rc = ENOMEM; 2691 goto bnx_dma_alloc_exit; 2692 } 2693 } 2694 2695 bnx_dma_alloc_exit: 2696 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2697 2698 return rc; 2699 } 2700 2701 /****************************************************************************/ 2702 /* Release all resources used by the driver. */ 2703 /* */ 2704 /* Releases all resources acquired by the driver including interrupts, */ 2705 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2706 /* */ 2707 /* Returns: */ 2708 /* Nothing. */ 2709 /****************************************************************************/ 2710 void 2711 bnx_release_resources(struct bnx_softc *sc) 2712 { 2713 struct pci_attach_args *pa = &(sc->bnx_pa); 2714 2715 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 2716 2717 bnx_dma_free(sc); 2718 2719 if (sc->bnx_intrhand != NULL) 2720 pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); 2721 2722 if (sc->bnx_ih != NULL) 2723 pci_intr_release(pa->pa_pc, sc->bnx_ih, 1); 2724 2725 if (sc->bnx_size) 2726 bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); 2727 2728 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 2729 } 2730 2731 /****************************************************************************/ 2732 /* Firmware synchronization. */ 2733 /* */ 2734 /* Before performing certain events such as a chip reset, synchronize with */ 2735 /* the firmware first. */ 2736 /* */ 2737 /* Returns: */ 2738 /* 0 for success, positive value for failure. */ 2739 /****************************************************************************/ 2740 int 2741 bnx_fw_sync(struct bnx_softc *sc, uint32_t msg_data) 2742 { 2743 int i, rc = 0; 2744 uint32_t val; 2745 2746 /* Don't waste any time if we've timed out before. */ 2747 if (sc->bnx_fw_timed_out) { 2748 rc = EBUSY; 2749 goto bnx_fw_sync_exit; 2750 } 2751 2752 /* Increment the message sequence number. */ 2753 sc->bnx_fw_wr_seq++; 2754 msg_data |= sc->bnx_fw_wr_seq; 2755 2756 DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", 2757 msg_data); 2758 2759 /* Send the message to the bootcode driver mailbox. */ 2760 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2761 2762 /* Wait for the bootcode to acknowledge the message. */ 2763 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2764 /* Check for a response in the bootcode firmware mailbox. */ 2765 val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); 2766 if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) 2767 break; 2768 DELAY(1000); 2769 } 2770 2771 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2772 if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && 2773 ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { 2774 BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2775 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 2776 2777 msg_data &= ~BNX_DRV_MSG_CODE; 2778 msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; 2779 2780 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); 2781 2782 sc->bnx_fw_timed_out = 1; 2783 rc = EBUSY; 2784 } 2785 2786 bnx_fw_sync_exit: 2787 return rc; 2788 } 2789 2790 /****************************************************************************/ 2791 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2792 /* */ 2793 /* Returns: */ 2794 /* Nothing. */ 2795 /****************************************************************************/ 2796 void 2797 bnx_load_rv2p_fw(struct bnx_softc *sc, uint32_t *rv2p_code, 2798 uint32_t rv2p_code_len, uint32_t rv2p_proc) 2799 { 2800 int i; 2801 uint32_t val; 2802 2803 /* Set the page size used by RV2P. */ 2804 if (rv2p_proc == RV2P_PROC2) { 2805 BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(rv2p_code, 2806 USABLE_RX_BD_PER_PAGE); 2807 } 2808 2809 for (i = 0; i < rv2p_code_len; i += 8) { 2810 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); 2811 rv2p_code++; 2812 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); 2813 rv2p_code++; 2814 2815 if (rv2p_proc == RV2P_PROC1) { 2816 val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; 2817 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); 2818 } else { 2819 val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; 2820 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); 2821 } 2822 } 2823 2824 /* Reset the processor, un-stall is done later. */ 2825 if (rv2p_proc == RV2P_PROC1) 2826 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); 2827 else 2828 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); 2829 } 2830 2831 /****************************************************************************/ 2832 /* Load RISC processor firmware. */ 2833 /* */ 2834 /* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ 2835 /* associated with a particular processor. */ 2836 /* */ 2837 /* Returns: */ 2838 /* Nothing. */ 2839 /****************************************************************************/ 2840 void 2841 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, 2842 struct fw_info *fw) 2843 { 2844 uint32_t offset; 2845 uint32_t val; 2846 2847 /* Halt the CPU. */ 2848 val = REG_RD_IND(sc, cpu_reg->mode); 2849 val |= cpu_reg->mode_value_halt; 2850 REG_WR_IND(sc, cpu_reg->mode, val); 2851 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2852 2853 /* Load the Text area. */ 2854 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2855 if (fw->text) { 2856 int j; 2857 2858 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) 2859 REG_WR_IND(sc, offset, fw->text[j]); 2860 } 2861 2862 /* Load the Data area. */ 2863 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2864 if (fw->data) { 2865 int j; 2866 2867 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) 2868 REG_WR_IND(sc, offset, fw->data[j]); 2869 } 2870 2871 /* Load the SBSS area. */ 2872 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2873 if (fw->sbss) { 2874 int j; 2875 2876 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) 2877 REG_WR_IND(sc, offset, fw->sbss[j]); 2878 } 2879 2880 /* Load the BSS area. */ 2881 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2882 if (fw->bss) { 2883 int j; 2884 2885 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) 2886 REG_WR_IND(sc, offset, fw->bss[j]); 2887 } 2888 2889 /* Load the Read-Only area. */ 2890 offset = cpu_reg->spad_base + 2891 (fw->rodata_addr - cpu_reg->mips_view_base); 2892 if (fw->rodata) { 2893 int j; 2894 2895 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) 2896 REG_WR_IND(sc, offset, fw->rodata[j]); 2897 } 2898 2899 /* Clear the pre-fetch instruction. */ 2900 REG_WR_IND(sc, cpu_reg->inst, 0); 2901 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2902 2903 /* Start the CPU. */ 2904 val = REG_RD_IND(sc, cpu_reg->mode); 2905 val &= ~cpu_reg->mode_value_halt; 2906 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2907 REG_WR_IND(sc, cpu_reg->mode, val); 2908 } 2909 2910 /****************************************************************************/ 2911 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2912 /* */ 2913 /* Loads the firmware for each CPU and starts the CPU. */ 2914 /* */ 2915 /* Returns: */ 2916 /* Nothing. */ 2917 /****************************************************************************/ 2918 void 2919 bnx_init_cpus(struct bnx_softc *sc) 2920 { 2921 struct cpu_reg cpu_reg; 2922 struct fw_info fw; 2923 2924 switch (BNX_CHIP_NUM(sc)) { 2925 case BNX_CHIP_NUM_5709: 2926 /* Initialize the RV2P processor. */ 2927 if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) { 2928 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc1, 2929 sizeof(bnx_xi90_rv2p_proc1), RV2P_PROC1); 2930 bnx_load_rv2p_fw(sc, bnx_xi90_rv2p_proc2, 2931 sizeof(bnx_xi90_rv2p_proc2), RV2P_PROC2); 2932 } else { 2933 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc1, 2934 sizeof(bnx_xi_rv2p_proc1), RV2P_PROC1); 2935 bnx_load_rv2p_fw(sc, bnx_xi_rv2p_proc2, 2936 sizeof(bnx_xi_rv2p_proc2), RV2P_PROC2); 2937 } 2938 2939 /* Initialize the RX Processor. */ 2940 cpu_reg.mode = BNX_RXP_CPU_MODE; 2941 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 2942 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 2943 cpu_reg.state = BNX_RXP_CPU_STATE; 2944 cpu_reg.state_value_clear = 0xffffff; 2945 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 2946 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 2947 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 2948 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 2949 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 2950 cpu_reg.spad_base = BNX_RXP_SCRATCH; 2951 cpu_reg.mips_view_base = 0x8000000; 2952 2953 fw.ver_major = bnx_RXP_b09FwReleaseMajor; 2954 fw.ver_minor = bnx_RXP_b09FwReleaseMinor; 2955 fw.ver_fix = bnx_RXP_b09FwReleaseFix; 2956 fw.start_addr = bnx_RXP_b09FwStartAddr; 2957 2958 fw.text_addr = bnx_RXP_b09FwTextAddr; 2959 fw.text_len = bnx_RXP_b09FwTextLen; 2960 fw.text_index = 0; 2961 fw.text = bnx_RXP_b09FwText; 2962 2963 fw.data_addr = bnx_RXP_b09FwDataAddr; 2964 fw.data_len = bnx_RXP_b09FwDataLen; 2965 fw.data_index = 0; 2966 fw.data = bnx_RXP_b09FwData; 2967 2968 fw.sbss_addr = bnx_RXP_b09FwSbssAddr; 2969 fw.sbss_len = bnx_RXP_b09FwSbssLen; 2970 fw.sbss_index = 0; 2971 fw.sbss = bnx_RXP_b09FwSbss; 2972 2973 fw.bss_addr = bnx_RXP_b09FwBssAddr; 2974 fw.bss_len = bnx_RXP_b09FwBssLen; 2975 fw.bss_index = 0; 2976 fw.bss = bnx_RXP_b09FwBss; 2977 2978 fw.rodata_addr = bnx_RXP_b09FwRodataAddr; 2979 fw.rodata_len = bnx_RXP_b09FwRodataLen; 2980 fw.rodata_index = 0; 2981 fw.rodata = bnx_RXP_b09FwRodata; 2982 2983 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 2984 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 2985 2986 /* Initialize the TX Processor. */ 2987 cpu_reg.mode = BNX_TXP_CPU_MODE; 2988 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 2989 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 2990 cpu_reg.state = BNX_TXP_CPU_STATE; 2991 cpu_reg.state_value_clear = 0xffffff; 2992 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 2993 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 2994 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 2995 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 2996 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 2997 cpu_reg.spad_base = BNX_TXP_SCRATCH; 2998 cpu_reg.mips_view_base = 0x8000000; 2999 3000 fw.ver_major = bnx_TXP_b09FwReleaseMajor; 3001 fw.ver_minor = bnx_TXP_b09FwReleaseMinor; 3002 fw.ver_fix = bnx_TXP_b09FwReleaseFix; 3003 fw.start_addr = bnx_TXP_b09FwStartAddr; 3004 3005 fw.text_addr = bnx_TXP_b09FwTextAddr; 3006 fw.text_len = bnx_TXP_b09FwTextLen; 3007 fw.text_index = 0; 3008 fw.text = bnx_TXP_b09FwText; 3009 3010 fw.data_addr = bnx_TXP_b09FwDataAddr; 3011 fw.data_len = bnx_TXP_b09FwDataLen; 3012 fw.data_index = 0; 3013 fw.data = bnx_TXP_b09FwData; 3014 3015 fw.sbss_addr = bnx_TXP_b09FwSbssAddr; 3016 fw.sbss_len = bnx_TXP_b09FwSbssLen; 3017 fw.sbss_index = 0; 3018 fw.sbss = bnx_TXP_b09FwSbss; 3019 3020 fw.bss_addr = bnx_TXP_b09FwBssAddr; 3021 fw.bss_len = bnx_TXP_b09FwBssLen; 3022 fw.bss_index = 0; 3023 fw.bss = bnx_TXP_b09FwBss; 3024 3025 fw.rodata_addr = bnx_TXP_b09FwRodataAddr; 3026 fw.rodata_len = bnx_TXP_b09FwRodataLen; 3027 fw.rodata_index = 0; 3028 fw.rodata = bnx_TXP_b09FwRodata; 3029 3030 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3031 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3032 3033 /* Initialize the TX Patch-up Processor. */ 3034 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3035 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3036 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3037 cpu_reg.state = BNX_TPAT_CPU_STATE; 3038 cpu_reg.state_value_clear = 0xffffff; 3039 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3040 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3041 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3042 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3043 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3044 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3045 cpu_reg.mips_view_base = 0x8000000; 3046 3047 fw.ver_major = bnx_TPAT_b09FwReleaseMajor; 3048 fw.ver_minor = bnx_TPAT_b09FwReleaseMinor; 3049 fw.ver_fix = bnx_TPAT_b09FwReleaseFix; 3050 fw.start_addr = bnx_TPAT_b09FwStartAddr; 3051 3052 fw.text_addr = bnx_TPAT_b09FwTextAddr; 3053 fw.text_len = bnx_TPAT_b09FwTextLen; 3054 fw.text_index = 0; 3055 fw.text = bnx_TPAT_b09FwText; 3056 3057 fw.data_addr = bnx_TPAT_b09FwDataAddr; 3058 fw.data_len = bnx_TPAT_b09FwDataLen; 3059 fw.data_index = 0; 3060 fw.data = bnx_TPAT_b09FwData; 3061 3062 fw.sbss_addr = bnx_TPAT_b09FwSbssAddr; 3063 fw.sbss_len = bnx_TPAT_b09FwSbssLen; 3064 fw.sbss_index = 0; 3065 fw.sbss = bnx_TPAT_b09FwSbss; 3066 3067 fw.bss_addr = bnx_TPAT_b09FwBssAddr; 3068 fw.bss_len = bnx_TPAT_b09FwBssLen; 3069 fw.bss_index = 0; 3070 fw.bss = bnx_TPAT_b09FwBss; 3071 3072 fw.rodata_addr = bnx_TPAT_b09FwRodataAddr; 3073 fw.rodata_len = bnx_TPAT_b09FwRodataLen; 3074 fw.rodata_index = 0; 3075 fw.rodata = bnx_TPAT_b09FwRodata; 3076 3077 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3078 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3079 3080 /* Initialize the Completion Processor. */ 3081 cpu_reg.mode = BNX_COM_CPU_MODE; 3082 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3083 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3084 cpu_reg.state = BNX_COM_CPU_STATE; 3085 cpu_reg.state_value_clear = 0xffffff; 3086 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3087 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3088 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3089 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3090 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3091 cpu_reg.spad_base = BNX_COM_SCRATCH; 3092 cpu_reg.mips_view_base = 0x8000000; 3093 3094 fw.ver_major = bnx_COM_b09FwReleaseMajor; 3095 fw.ver_minor = bnx_COM_b09FwReleaseMinor; 3096 fw.ver_fix = bnx_COM_b09FwReleaseFix; 3097 fw.start_addr = bnx_COM_b09FwStartAddr; 3098 3099 fw.text_addr = bnx_COM_b09FwTextAddr; 3100 fw.text_len = bnx_COM_b09FwTextLen; 3101 fw.text_index = 0; 3102 fw.text = bnx_COM_b09FwText; 3103 3104 fw.data_addr = bnx_COM_b09FwDataAddr; 3105 fw.data_len = bnx_COM_b09FwDataLen; 3106 fw.data_index = 0; 3107 fw.data = bnx_COM_b09FwData; 3108 3109 fw.sbss_addr = bnx_COM_b09FwSbssAddr; 3110 fw.sbss_len = bnx_COM_b09FwSbssLen; 3111 fw.sbss_index = 0; 3112 fw.sbss = bnx_COM_b09FwSbss; 3113 3114 fw.bss_addr = bnx_COM_b09FwBssAddr; 3115 fw.bss_len = bnx_COM_b09FwBssLen; 3116 fw.bss_index = 0; 3117 fw.bss = bnx_COM_b09FwBss; 3118 3119 fw.rodata_addr = bnx_COM_b09FwRodataAddr; 3120 fw.rodata_len = bnx_COM_b09FwRodataLen; 3121 fw.rodata_index = 0; 3122 fw.rodata = bnx_COM_b09FwRodata; 3123 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3124 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3125 break; 3126 default: 3127 /* Initialize the RV2P processor. */ 3128 bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), 3129 RV2P_PROC1); 3130 bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), 3131 RV2P_PROC2); 3132 3133 /* Initialize the RX Processor. */ 3134 cpu_reg.mode = BNX_RXP_CPU_MODE; 3135 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; 3136 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; 3137 cpu_reg.state = BNX_RXP_CPU_STATE; 3138 cpu_reg.state_value_clear = 0xffffff; 3139 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; 3140 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; 3141 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; 3142 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; 3143 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; 3144 cpu_reg.spad_base = BNX_RXP_SCRATCH; 3145 cpu_reg.mips_view_base = 0x8000000; 3146 3147 fw.ver_major = bnx_RXP_b06FwReleaseMajor; 3148 fw.ver_minor = bnx_RXP_b06FwReleaseMinor; 3149 fw.ver_fix = bnx_RXP_b06FwReleaseFix; 3150 fw.start_addr = bnx_RXP_b06FwStartAddr; 3151 3152 fw.text_addr = bnx_RXP_b06FwTextAddr; 3153 fw.text_len = bnx_RXP_b06FwTextLen; 3154 fw.text_index = 0; 3155 fw.text = bnx_RXP_b06FwText; 3156 3157 fw.data_addr = bnx_RXP_b06FwDataAddr; 3158 fw.data_len = bnx_RXP_b06FwDataLen; 3159 fw.data_index = 0; 3160 fw.data = bnx_RXP_b06FwData; 3161 3162 fw.sbss_addr = bnx_RXP_b06FwSbssAddr; 3163 fw.sbss_len = bnx_RXP_b06FwSbssLen; 3164 fw.sbss_index = 0; 3165 fw.sbss = bnx_RXP_b06FwSbss; 3166 3167 fw.bss_addr = bnx_RXP_b06FwBssAddr; 3168 fw.bss_len = bnx_RXP_b06FwBssLen; 3169 fw.bss_index = 0; 3170 fw.bss = bnx_RXP_b06FwBss; 3171 3172 fw.rodata_addr = bnx_RXP_b06FwRodataAddr; 3173 fw.rodata_len = bnx_RXP_b06FwRodataLen; 3174 fw.rodata_index = 0; 3175 fw.rodata = bnx_RXP_b06FwRodata; 3176 3177 DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); 3178 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3179 3180 /* Initialize the TX Processor. */ 3181 cpu_reg.mode = BNX_TXP_CPU_MODE; 3182 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; 3183 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; 3184 cpu_reg.state = BNX_TXP_CPU_STATE; 3185 cpu_reg.state_value_clear = 0xffffff; 3186 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; 3187 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; 3188 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; 3189 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; 3190 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; 3191 cpu_reg.spad_base = BNX_TXP_SCRATCH; 3192 cpu_reg.mips_view_base = 0x8000000; 3193 3194 fw.ver_major = bnx_TXP_b06FwReleaseMajor; 3195 fw.ver_minor = bnx_TXP_b06FwReleaseMinor; 3196 fw.ver_fix = bnx_TXP_b06FwReleaseFix; 3197 fw.start_addr = bnx_TXP_b06FwStartAddr; 3198 3199 fw.text_addr = bnx_TXP_b06FwTextAddr; 3200 fw.text_len = bnx_TXP_b06FwTextLen; 3201 fw.text_index = 0; 3202 fw.text = bnx_TXP_b06FwText; 3203 3204 fw.data_addr = bnx_TXP_b06FwDataAddr; 3205 fw.data_len = bnx_TXP_b06FwDataLen; 3206 fw.data_index = 0; 3207 fw.data = bnx_TXP_b06FwData; 3208 3209 fw.sbss_addr = bnx_TXP_b06FwSbssAddr; 3210 fw.sbss_len = bnx_TXP_b06FwSbssLen; 3211 fw.sbss_index = 0; 3212 fw.sbss = bnx_TXP_b06FwSbss; 3213 3214 fw.bss_addr = bnx_TXP_b06FwBssAddr; 3215 fw.bss_len = bnx_TXP_b06FwBssLen; 3216 fw.bss_index = 0; 3217 fw.bss = bnx_TXP_b06FwBss; 3218 3219 fw.rodata_addr = bnx_TXP_b06FwRodataAddr; 3220 fw.rodata_len = bnx_TXP_b06FwRodataLen; 3221 fw.rodata_index = 0; 3222 fw.rodata = bnx_TXP_b06FwRodata; 3223 3224 DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); 3225 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3226 3227 /* Initialize the TX Patch-up Processor. */ 3228 cpu_reg.mode = BNX_TPAT_CPU_MODE; 3229 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; 3230 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; 3231 cpu_reg.state = BNX_TPAT_CPU_STATE; 3232 cpu_reg.state_value_clear = 0xffffff; 3233 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; 3234 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; 3235 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; 3236 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; 3237 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; 3238 cpu_reg.spad_base = BNX_TPAT_SCRATCH; 3239 cpu_reg.mips_view_base = 0x8000000; 3240 3241 fw.ver_major = bnx_TPAT_b06FwReleaseMajor; 3242 fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; 3243 fw.ver_fix = bnx_TPAT_b06FwReleaseFix; 3244 fw.start_addr = bnx_TPAT_b06FwStartAddr; 3245 3246 fw.text_addr = bnx_TPAT_b06FwTextAddr; 3247 fw.text_len = bnx_TPAT_b06FwTextLen; 3248 fw.text_index = 0; 3249 fw.text = bnx_TPAT_b06FwText; 3250 3251 fw.data_addr = bnx_TPAT_b06FwDataAddr; 3252 fw.data_len = bnx_TPAT_b06FwDataLen; 3253 fw.data_index = 0; 3254 fw.data = bnx_TPAT_b06FwData; 3255 3256 fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; 3257 fw.sbss_len = bnx_TPAT_b06FwSbssLen; 3258 fw.sbss_index = 0; 3259 fw.sbss = bnx_TPAT_b06FwSbss; 3260 3261 fw.bss_addr = bnx_TPAT_b06FwBssAddr; 3262 fw.bss_len = bnx_TPAT_b06FwBssLen; 3263 fw.bss_index = 0; 3264 fw.bss = bnx_TPAT_b06FwBss; 3265 3266 fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; 3267 fw.rodata_len = bnx_TPAT_b06FwRodataLen; 3268 fw.rodata_index = 0; 3269 fw.rodata = bnx_TPAT_b06FwRodata; 3270 3271 DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); 3272 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3273 3274 /* Initialize the Completion Processor. */ 3275 cpu_reg.mode = BNX_COM_CPU_MODE; 3276 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; 3277 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; 3278 cpu_reg.state = BNX_COM_CPU_STATE; 3279 cpu_reg.state_value_clear = 0xffffff; 3280 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; 3281 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; 3282 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; 3283 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; 3284 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; 3285 cpu_reg.spad_base = BNX_COM_SCRATCH; 3286 cpu_reg.mips_view_base = 0x8000000; 3287 3288 fw.ver_major = bnx_COM_b06FwReleaseMajor; 3289 fw.ver_minor = bnx_COM_b06FwReleaseMinor; 3290 fw.ver_fix = bnx_COM_b06FwReleaseFix; 3291 fw.start_addr = bnx_COM_b06FwStartAddr; 3292 3293 fw.text_addr = bnx_COM_b06FwTextAddr; 3294 fw.text_len = bnx_COM_b06FwTextLen; 3295 fw.text_index = 0; 3296 fw.text = bnx_COM_b06FwText; 3297 3298 fw.data_addr = bnx_COM_b06FwDataAddr; 3299 fw.data_len = bnx_COM_b06FwDataLen; 3300 fw.data_index = 0; 3301 fw.data = bnx_COM_b06FwData; 3302 3303 fw.sbss_addr = bnx_COM_b06FwSbssAddr; 3304 fw.sbss_len = bnx_COM_b06FwSbssLen; 3305 fw.sbss_index = 0; 3306 fw.sbss = bnx_COM_b06FwSbss; 3307 3308 fw.bss_addr = bnx_COM_b06FwBssAddr; 3309 fw.bss_len = bnx_COM_b06FwBssLen; 3310 fw.bss_index = 0; 3311 fw.bss = bnx_COM_b06FwBss; 3312 3313 fw.rodata_addr = bnx_COM_b06FwRodataAddr; 3314 fw.rodata_len = bnx_COM_b06FwRodataLen; 3315 fw.rodata_index = 0; 3316 fw.rodata = bnx_COM_b06FwRodata; 3317 DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); 3318 bnx_load_cpu_fw(sc, &cpu_reg, &fw); 3319 break; 3320 } 3321 } 3322 3323 /****************************************************************************/ 3324 /* Initialize context memory. */ 3325 /* */ 3326 /* Clears the memory associated with each Context ID (CID). */ 3327 /* */ 3328 /* Returns: */ 3329 /* Nothing. */ 3330 /****************************************************************************/ 3331 void 3332 bnx_init_context(struct bnx_softc *sc) 3333 { 3334 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3335 /* DRC: Replace this constant value with a #define. */ 3336 int i, retry_cnt = 10; 3337 uint32_t val; 3338 3339 /* 3340 * BCM5709 context memory may be cached 3341 * in host memory so prepare the host memory 3342 * for access. 3343 */ 3344 val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT 3345 | (1 << 12); 3346 val |= (BCM_PAGE_BITS - 8) << 16; 3347 REG_WR(sc, BNX_CTX_COMMAND, val); 3348 3349 /* Wait for mem init command to complete. */ 3350 for (i = 0; i < retry_cnt; i++) { 3351 val = REG_RD(sc, BNX_CTX_COMMAND); 3352 if (!(val & BNX_CTX_COMMAND_MEM_INIT)) 3353 break; 3354 DELAY(2); 3355 } 3356 3357 /* ToDo: Consider returning an error here. */ 3358 3359 for (i = 0; i < sc->ctx_pages; i++) { 3360 int j; 3361 3362 /* Set the physaddr of the context memory cache. */ 3363 val = (uint32_t)(sc->ctx_segs[i].ds_addr); 3364 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val | 3365 BNX_CTX_HOST_PAGE_TBL_DATA0_VALID); 3366 val = (uint32_t) 3367 ((uint64_t)sc->ctx_segs[i].ds_addr >> 32); 3368 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val); 3369 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i | 3370 BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 3371 3372 /* Verify that the context memory write was successful. */ 3373 for (j = 0; j < retry_cnt; j++) { 3374 val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL); 3375 if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 3376 break; 3377 DELAY(5); 3378 } 3379 3380 /* ToDo: Consider returning an error here. */ 3381 } 3382 } else { 3383 uint32_t vcid_addr, offset; 3384 3385 /* 3386 * For the 5706/5708, context memory is local to the 3387 * controller, so initialize the controller context memory. 3388 */ 3389 3390 vcid_addr = GET_CID_ADDR(96); 3391 while (vcid_addr) { 3392 3393 vcid_addr -= BNX_PHY_CTX_SIZE; 3394 3395 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); 3396 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3397 3398 for (offset = 0; offset < BNX_PHY_CTX_SIZE; 3399 offset += 4) 3400 CTX_WR(sc, 0x00, offset, 0); 3401 3402 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); 3403 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); 3404 } 3405 } 3406 } 3407 3408 /****************************************************************************/ 3409 /* Fetch the permanent MAC address of the controller. */ 3410 /* */ 3411 /* Returns: */ 3412 /* Nothing. */ 3413 /****************************************************************************/ 3414 void 3415 bnx_get_mac_addr(struct bnx_softc *sc) 3416 { 3417 uint32_t mac_lo = 0, mac_hi = 0; 3418 3419 /* 3420 * The NetXtreme II bootcode populates various NIC 3421 * power-on and runtime configuration items in a 3422 * shared memory area. The factory configured MAC 3423 * address is available from both NVRAM and the 3424 * shared memory area so we'll read the value from 3425 * shared memory for speed. 3426 */ 3427 3428 mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); 3429 mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); 3430 3431 if ((mac_lo == 0) && (mac_hi == 0)) { 3432 BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3433 __FILE__, __LINE__); 3434 } else { 3435 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3436 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3437 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3438 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3439 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3440 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3441 } 3442 3443 DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " 3444 "%s\n", ether_sprintf(sc->eaddr)); 3445 } 3446 3447 /****************************************************************************/ 3448 /* Program the MAC address. */ 3449 /* */ 3450 /* Returns: */ 3451 /* Nothing. */ 3452 /****************************************************************************/ 3453 void 3454 bnx_set_mac_addr(struct bnx_softc *sc) 3455 { 3456 uint32_t val; 3457 const uint8_t *mac_addr = CLLADDR(sc->bnx_ec.ec_if.if_sadl); 3458 3459 DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " 3460 "%s\n", ether_sprintf(sc->eaddr)); 3461 3462 val = (mac_addr[0] << 8) | mac_addr[1]; 3463 3464 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); 3465 3466 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3467 (mac_addr[4] << 8) | mac_addr[5]; 3468 3469 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); 3470 } 3471 3472 /****************************************************************************/ 3473 /* Stop the controller. */ 3474 /* */ 3475 /* Returns: */ 3476 /* Nothing. */ 3477 /****************************************************************************/ 3478 void 3479 bnx_stop(struct ifnet *ifp, int disable) 3480 { 3481 struct bnx_softc *sc = ifp->if_softc; 3482 3483 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3484 3485 if (disable) { 3486 sc->bnx_detaching = 1; 3487 callout_halt(&sc->bnx_timeout, NULL); 3488 } else 3489 callout_stop(&sc->bnx_timeout); 3490 3491 mii_down(&sc->bnx_mii); 3492 3493 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3494 3495 /* Disable the transmit/receive blocks. */ 3496 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3497 REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3498 DELAY(20); 3499 3500 bnx_disable_intr(sc); 3501 3502 /* Tell firmware that the driver is going away. */ 3503 if (disable) 3504 bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); 3505 else 3506 bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); 3507 3508 /* Free RX buffers. */ 3509 bnx_free_rx_chain(sc); 3510 3511 /* Free TX buffers. */ 3512 bnx_free_tx_chain(sc); 3513 3514 ifp->if_timer = 0; 3515 3516 sc->bnx_link = 0; 3517 3518 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3519 3520 bnx_mgmt_init(sc); 3521 } 3522 3523 int 3524 bnx_reset(struct bnx_softc *sc, uint32_t reset_code) 3525 { 3526 struct pci_attach_args *pa = &(sc->bnx_pa); 3527 uint32_t val; 3528 int i, rc = 0; 3529 3530 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3531 3532 /* Wait for pending PCI transactions to complete. */ 3533 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) || 3534 (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708)) { 3535 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 3536 BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3537 BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3538 BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3539 BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3540 val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); 3541 DELAY(5); 3542 } else { 3543 /* Disable DMA */ 3544 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3545 val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3546 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3547 REG_RD(sc, BNX_MISC_NEW_CORE_CTL); /* barrier */ 3548 3549 for (i = 0; i < 100; i++) { 3550 delay(1 * 1000); 3551 val = REG_RD(sc, BNX_PCICFG_DEVICE_CONTROL); 3552 if ((val & PCIE_DCSR_TRANSACTION_PND) == 0) 3553 break; 3554 } 3555 } 3556 3557 /* Assume bootcode is running. */ 3558 sc->bnx_fw_timed_out = 0; 3559 3560 /* Give the firmware a chance to prepare for the reset. */ 3561 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); 3562 if (rc) 3563 goto bnx_reset_exit; 3564 3565 /* Set a firmware reminder that this is a soft reset. */ 3566 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, 3567 BNX_DRV_RESET_SIGNATURE_MAGIC); 3568 3569 /* Dummy read to force the chip to complete all current transactions. */ 3570 val = REG_RD(sc, BNX_MISC_ID); 3571 3572 /* Chip reset. */ 3573 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3574 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET); 3575 REG_RD(sc, BNX_MISC_COMMAND); 3576 DELAY(5); 3577 3578 val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3579 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3580 3581 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, 3582 val); 3583 } else { 3584 val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3585 BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3586 BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3587 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); 3588 3589 /* Allow up to 30us for reset to complete. */ 3590 for (i = 0; i < 10; i++) { 3591 val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); 3592 if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3593 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3594 break; 3595 } 3596 DELAY(10); 3597 } 3598 3599 /* Check that reset completed successfully. */ 3600 if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3601 BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3602 BNX_PRINTF(sc, "%s(%d): Reset failed!\n", 3603 __FILE__, __LINE__); 3604 rc = EBUSY; 3605 goto bnx_reset_exit; 3606 } 3607 } 3608 3609 /* Make sure byte swapping is properly configured. */ 3610 val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); 3611 if (val != 0x01020304) { 3612 BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3613 __FILE__, __LINE__); 3614 rc = ENODEV; 3615 goto bnx_reset_exit; 3616 } 3617 3618 /* Just completed a reset, assume that firmware is running again. */ 3619 sc->bnx_fw_timed_out = 0; 3620 3621 /* Wait for the firmware to finish its initialization. */ 3622 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); 3623 if (rc) 3624 BNX_PRINTF(sc, "%s(%d): Firmware did not complete " 3625 "initialization!\n", __FILE__, __LINE__); 3626 3627 bnx_reset_exit: 3628 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3629 3630 return rc; 3631 } 3632 3633 int 3634 bnx_chipinit(struct bnx_softc *sc) 3635 { 3636 struct pci_attach_args *pa = &(sc->bnx_pa); 3637 uint32_t val; 3638 int rc = 0; 3639 3640 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3641 3642 /* Make sure the interrupt is not active. */ 3643 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 3644 3645 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3646 /* channels and PCI clock compensation delay. */ 3647 val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | 3648 BNX_DMA_CONFIG_DATA_WORD_SWAP | 3649 #if BYTE_ORDER == BIG_ENDIAN 3650 BNX_DMA_CONFIG_CNTL_BYTE_SWAP | 3651 #endif 3652 BNX_DMA_CONFIG_CNTL_WORD_SWAP | 3653 DMA_READ_CHANS << 12 | 3654 DMA_WRITE_CHANS << 16; 3655 3656 val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3657 3658 if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3659 val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; 3660 3661 /* 3662 * This setting resolves a problem observed on certain Intel PCI 3663 * chipsets that cannot handle multiple outstanding DMA operations. 3664 * See errata E9_5706A1_65. 3665 */ 3666 if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 3667 (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && 3668 !(sc->bnx_flags & BNX_PCIX_FLAG)) 3669 val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; 3670 3671 REG_WR(sc, BNX_DMA_CONFIG, val); 3672 3673 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3674 if (sc->bnx_flags & BNX_PCIX_FLAG) { 3675 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); 3676 pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, 3677 val & ~0x20000); 3678 } 3679 3680 /* Enable the RX_V2P and Context state machines before access. */ 3681 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3682 BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3683 BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3684 BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3685 3686 /* Initialize context mapping and zero out the quick contexts. */ 3687 bnx_init_context(sc); 3688 3689 /* Initialize the on-boards CPUs */ 3690 bnx_init_cpus(sc); 3691 3692 /* Enable management frames (NC-SI) to flow to the MCP. */ 3693 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3694 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) | 3695 BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3696 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3697 } 3698 3699 /* Prepare NVRAM for access. */ 3700 if (bnx_init_nvram(sc)) { 3701 rc = ENODEV; 3702 goto bnx_chipinit_exit; 3703 } 3704 3705 /* Set the kernel bypass block size */ 3706 val = REG_RD(sc, BNX_MQ_CONFIG); 3707 val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3708 val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3709 3710 /* Enable bins used on the 5709. */ 3711 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3712 val |= BNX_MQ_CONFIG_BIN_MQ_MODE; 3713 if (BNX_CHIP_ID(sc) == BNX_CHIP_ID_5709_A1) 3714 val |= BNX_MQ_CONFIG_HALT_DIS; 3715 } 3716 3717 REG_WR(sc, BNX_MQ_CONFIG, val); 3718 3719 val = 0x10000 + (MAX_CID_CNT * BNX_MB_KERNEL_CTX_SIZE); 3720 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); 3721 REG_WR(sc, BNX_MQ_KNL_WIND_END, val); 3722 3723 val = (BCM_PAGE_BITS - 8) << 24; 3724 REG_WR(sc, BNX_RV2P_CONFIG, val); 3725 3726 /* Configure page size. */ 3727 val = REG_RD(sc, BNX_TBDR_CONFIG); 3728 val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; 3729 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3730 REG_WR(sc, BNX_TBDR_CONFIG, val); 3731 3732 #if 0 3733 /* Set the perfect match control register to default. */ 3734 REG_WR_IND(sc, BNX_RXP_PM_CTRL, 0); 3735 #endif 3736 3737 bnx_chipinit_exit: 3738 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3739 3740 return rc; 3741 } 3742 3743 /****************************************************************************/ 3744 /* Initialize the controller in preparation to send/receive traffic. */ 3745 /* */ 3746 /* Returns: */ 3747 /* 0 for success, positive value for failure. */ 3748 /****************************************************************************/ 3749 int 3750 bnx_blockinit(struct bnx_softc *sc) 3751 { 3752 uint32_t reg, val; 3753 int rc = 0; 3754 3755 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 3756 3757 /* Load the hardware default MAC address. */ 3758 bnx_set_mac_addr(sc); 3759 3760 /* Set the Ethernet backoff seed value */ 3761 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + 3762 (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3763 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); 3764 3765 sc->last_status_idx = 0; 3766 sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; 3767 3768 /* Set up link change interrupt generation. */ 3769 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); 3770 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3771 3772 /* Program the physical address of the status block. */ 3773 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr)); 3774 REG_WR(sc, BNX_HC_STATUS_ADDR_H, 3775 (uint32_t)((uint64_t)sc->status_block_paddr >> 32)); 3776 3777 /* Program the physical address of the statistics block. */ 3778 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, 3779 (uint32_t)(sc->stats_block_paddr)); 3780 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, 3781 (uint32_t)((uint64_t)sc->stats_block_paddr >> 32)); 3782 3783 /* Program various host coalescing parameters. */ 3784 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int 3785 << 16) | sc->bnx_tx_quick_cons_trip); 3786 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int 3787 << 16) | sc->bnx_rx_quick_cons_trip); 3788 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | 3789 sc->bnx_comp_prod_trip); 3790 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | 3791 sc->bnx_tx_ticks); 3792 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | 3793 sc->bnx_rx_ticks); 3794 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | 3795 sc->bnx_com_ticks); 3796 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | 3797 sc->bnx_cmd_ticks); 3798 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); 3799 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 3800 REG_WR(sc, BNX_HC_CONFIG, 3801 (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | 3802 BNX_HC_CONFIG_COLLECT_STATS)); 3803 3804 /* Clear the internal statistics counters. */ 3805 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); 3806 3807 /* Verify that bootcode is running. */ 3808 reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); 3809 3810 DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), 3811 BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3812 __FILE__, __LINE__); reg = 0); 3813 3814 if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3815 BNX_DEV_INFO_SIGNATURE_MAGIC) { 3816 BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3817 "Expected: 08%08X\n", __FILE__, __LINE__, 3818 (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), 3819 BNX_DEV_INFO_SIGNATURE_MAGIC); 3820 rc = ENODEV; 3821 goto bnx_blockinit_exit; 3822 } 3823 3824 /* Enable DMA */ 3825 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3826 val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL); 3827 val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE; 3828 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val); 3829 } 3830 3831 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3832 rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); 3833 3834 /* Disable management frames (NC-SI) from flowing to the MCP. */ 3835 if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) { 3836 val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) & 3837 ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN; 3838 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val); 3839 } 3840 3841 /* Enable all remaining blocks in the MAC. */ 3842 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 3843 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 3844 BNX_MISC_ENABLE_DEFAULT_XI); 3845 } else 3846 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); 3847 3848 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 3849 DELAY(20); 3850 3851 bnx_blockinit_exit: 3852 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 3853 3854 return rc; 3855 } 3856 3857 static int 3858 bnx_add_buf(struct bnx_softc *sc, struct mbuf *m_new, uint16_t *prod, 3859 uint16_t *chain_prod, uint32_t *prod_bseq) 3860 { 3861 bus_dmamap_t map; 3862 struct rx_bd *rxbd; 3863 uint32_t addr; 3864 int i; 3865 #ifdef BNX_DEBUG 3866 uint16_t debug_chain_prod = *chain_prod; 3867 #endif 3868 uint16_t first_chain_prod; 3869 3870 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3871 3872 /* Map the mbuf cluster into device memory. */ 3873 map = sc->rx_mbuf_map[*chain_prod]; 3874 first_chain_prod = *chain_prod; 3875 if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { 3876 BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3877 __FILE__, __LINE__); 3878 3879 m_freem(m_new); 3880 3881 DBRUNIF(1, sc->rx_mbuf_alloc--); 3882 3883 return ENOBUFS; 3884 } 3885 /* Make sure there is room in the receive chain. */ 3886 if (map->dm_nsegs > sc->free_rx_bd) { 3887 bus_dmamap_unload(sc->bnx_dmatag, map); 3888 m_freem(m_new); 3889 return EFBIG; 3890 } 3891 #ifdef BNX_DEBUG 3892 /* Track the distribution of buffer segments. */ 3893 sc->rx_mbuf_segs[map->dm_nsegs]++; 3894 #endif 3895 3896 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 3897 BUS_DMASYNC_PREREAD); 3898 3899 /* Update some debug statistics counters */ 3900 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3901 sc->rx_low_watermark = sc->free_rx_bd); 3902 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3903 3904 /* 3905 * Setup the rx_bd for the first segment 3906 */ 3907 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3908 3909 addr = (uint32_t)map->dm_segs[0].ds_addr; 3910 rxbd->rx_bd_haddr_lo = addr; 3911 addr = (uint32_t)((uint64_t)map->dm_segs[0].ds_addr >> 32); 3912 rxbd->rx_bd_haddr_hi = addr; 3913 rxbd->rx_bd_len = map->dm_segs[0].ds_len; 3914 rxbd->rx_bd_flags = RX_BD_FLAGS_START; 3915 *prod_bseq += map->dm_segs[0].ds_len; 3916 bus_dmamap_sync(sc->bnx_dmatag, 3917 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3918 sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), 3919 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3920 3921 for (i = 1; i < map->dm_nsegs; i++) { 3922 *prod = NEXT_RX_BD(*prod); 3923 *chain_prod = RX_CHAIN_IDX(*prod); 3924 3925 rxbd = 3926 &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3927 3928 addr = (uint32_t)map->dm_segs[i].ds_addr; 3929 rxbd->rx_bd_haddr_lo = addr; 3930 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 3931 rxbd->rx_bd_haddr_hi = addr; 3932 rxbd->rx_bd_len = map->dm_segs[i].ds_len; 3933 rxbd->rx_bd_flags = 0; 3934 *prod_bseq += map->dm_segs[i].ds_len; 3935 bus_dmamap_sync(sc->bnx_dmatag, 3936 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3937 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3938 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3939 } 3940 3941 rxbd->rx_bd_flags |= RX_BD_FLAGS_END; 3942 bus_dmamap_sync(sc->bnx_dmatag, 3943 sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], 3944 sizeof(struct rx_bd) * RX_IDX(*chain_prod), 3945 sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3946 3947 /* 3948 * Save the mbuf, adjust the map pointer (swap map for first and 3949 * last rx_bd entry so that rx_mbuf_ptr and rx_mbuf_map matches) 3950 * and update our counter. 3951 */ 3952 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3953 sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; 3954 sc->rx_mbuf_map[*chain_prod] = map; 3955 sc->free_rx_bd -= map->dm_nsegs; 3956 3957 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, 3958 map->dm_nsegs)); 3959 *prod = NEXT_RX_BD(*prod); 3960 *chain_prod = RX_CHAIN_IDX(*prod); 3961 3962 return 0; 3963 } 3964 3965 /****************************************************************************/ 3966 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3967 /* */ 3968 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3969 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3970 /* necessary. */ 3971 /* */ 3972 /* Returns: */ 3973 /* 0 for success, positive value for failure. */ 3974 /****************************************************************************/ 3975 int 3976 bnx_get_buf(struct bnx_softc *sc, uint16_t *prod, 3977 uint16_t *chain_prod, uint32_t *prod_bseq) 3978 { 3979 struct mbuf *m_new = NULL; 3980 int rc = 0; 3981 uint16_t min_free_bd; 3982 3983 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", 3984 __func__); 3985 3986 /* Make sure the inputs are valid. */ 3987 DBRUNIF((*chain_prod > MAX_RX_BD), 3988 aprint_error_dev(sc->bnx_dev, 3989 "RX producer out of range: 0x%04X > 0x%04X\n", 3990 *chain_prod, (uint16_t)MAX_RX_BD)); 3991 3992 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " 3993 "0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, 3994 *prod_bseq); 3995 3996 /* try to get in as many mbufs as possible */ 3997 if (sc->mbuf_alloc_size == MCLBYTES) 3998 min_free_bd = (MCLBYTES + PAGE_SIZE - 1) / PAGE_SIZE; 3999 else 4000 min_free_bd = (BNX_MAX_JUMBO_MRU + PAGE_SIZE - 1) / PAGE_SIZE; 4001 while (sc->free_rx_bd >= min_free_bd) { 4002 /* Simulate an mbuf allocation failure. */ 4003 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4004 aprint_error_dev(sc->bnx_dev, 4005 "Simulating mbuf allocation failure.\n"); 4006 sc->mbuf_sim_alloc_failed++; 4007 rc = ENOBUFS; 4008 goto bnx_get_buf_exit); 4009 4010 /* This is a new mbuf allocation. */ 4011 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4012 if (m_new == NULL) { 4013 DBPRINT(sc, BNX_WARN, 4014 "%s(%d): RX mbuf header allocation failed!\n", 4015 __FILE__, __LINE__); 4016 4017 sc->mbuf_alloc_failed++; 4018 4019 rc = ENOBUFS; 4020 goto bnx_get_buf_exit; 4021 } 4022 4023 DBRUNIF(1, sc->rx_mbuf_alloc++); 4024 4025 /* Simulate an mbuf cluster allocation failure. */ 4026 DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), 4027 m_freem(m_new); 4028 sc->rx_mbuf_alloc--; 4029 sc->mbuf_alloc_failed++; 4030 sc->mbuf_sim_alloc_failed++; 4031 rc = ENOBUFS; 4032 goto bnx_get_buf_exit); 4033 4034 if (sc->mbuf_alloc_size == MCLBYTES) 4035 MCLGET(m_new, M_DONTWAIT); 4036 else 4037 MEXTMALLOC(m_new, sc->mbuf_alloc_size, 4038 M_DONTWAIT); 4039 if (!(m_new->m_flags & M_EXT)) { 4040 DBPRINT(sc, BNX_WARN, 4041 "%s(%d): RX mbuf chain allocation failed!\n", 4042 __FILE__, __LINE__); 4043 4044 m_freem(m_new); 4045 4046 DBRUNIF(1, sc->rx_mbuf_alloc--); 4047 sc->mbuf_alloc_failed++; 4048 4049 rc = ENOBUFS; 4050 goto bnx_get_buf_exit; 4051 } 4052 4053 rc = bnx_add_buf(sc, m_new, prod, chain_prod, prod_bseq); 4054 if (rc != 0) 4055 goto bnx_get_buf_exit; 4056 } 4057 4058 bnx_get_buf_exit: 4059 DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " 4060 "= 0x%04X, prod_bseq = 0x%08X\n", __func__, *prod, 4061 *chain_prod, *prod_bseq); 4062 4063 DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", 4064 __func__); 4065 4066 return rc; 4067 } 4068 4069 void 4070 bnx_alloc_pkts(struct work * unused, void * arg) 4071 { 4072 struct bnx_softc *sc = arg; 4073 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4074 struct bnx_pkt *pkt; 4075 int i, s; 4076 4077 for (i = 0; i < 4; i++) { /* magic! */ 4078 pkt = pool_get(bnx_tx_pool, PR_WAITOK); 4079 if (pkt == NULL) 4080 break; 4081 4082 if (bus_dmamap_create(sc->bnx_dmatag, 4083 MCLBYTES * BNX_MAX_SEGMENTS, USABLE_TX_BD, 4084 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 4085 &pkt->pkt_dmamap) != 0) 4086 goto put; 4087 4088 if (!ISSET(ifp->if_flags, IFF_UP)) 4089 goto stopping; 4090 4091 mutex_enter(&sc->tx_pkt_mtx); 4092 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4093 sc->tx_pkt_count++; 4094 mutex_exit(&sc->tx_pkt_mtx); 4095 } 4096 4097 mutex_enter(&sc->tx_pkt_mtx); 4098 CLR(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 4099 mutex_exit(&sc->tx_pkt_mtx); 4100 4101 /* fire-up TX now that allocations have been done */ 4102 s = splnet(); 4103 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4104 bnx_start(ifp); 4105 splx(s); 4106 4107 return; 4108 4109 stopping: 4110 bus_dmamap_destroy(sc->bnx_dmatag, pkt->pkt_dmamap); 4111 put: 4112 pool_put(bnx_tx_pool, pkt); 4113 return; 4114 } 4115 4116 /****************************************************************************/ 4117 /* Initialize the TX context memory. */ 4118 /* */ 4119 /* Returns: */ 4120 /* Nothing */ 4121 /****************************************************************************/ 4122 void 4123 bnx_init_tx_context(struct bnx_softc *sc) 4124 { 4125 uint32_t val; 4126 4127 /* Initialize the context ID for an L2 TX chain. */ 4128 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4129 /* Set the CID type to support an L2 connection. */ 4130 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4131 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val); 4132 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4133 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val); 4134 4135 /* Point the hardware to the first page in the chain. */ 4136 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4137 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4138 BNX_L2CTX_TBDR_BHADDR_HI_XI, val); 4139 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4140 CTX_WR(sc, GET_CID_ADDR(TX_CID), 4141 BNX_L2CTX_TBDR_BHADDR_LO_XI, val); 4142 } else { 4143 /* Set the CID type to support an L2 connection. */ 4144 val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2; 4145 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); 4146 val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 4147 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); 4148 4149 /* Point the hardware to the first page in the chain. */ 4150 val = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[0] >> 32); 4151 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); 4152 val = (uint32_t)(sc->tx_bd_chain_paddr[0]); 4153 CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); 4154 } 4155 } 4156 4157 4158 /****************************************************************************/ 4159 /* Allocate memory and initialize the TX data structures. */ 4160 /* */ 4161 /* Returns: */ 4162 /* 0 for success, positive value for failure. */ 4163 /****************************************************************************/ 4164 int 4165 bnx_init_tx_chain(struct bnx_softc *sc) 4166 { 4167 struct tx_bd *txbd; 4168 uint32_t addr; 4169 int i, rc = 0; 4170 4171 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4172 4173 /* Set the initial TX producer/consumer indices. */ 4174 sc->tx_prod = 0; 4175 sc->tx_cons = 0; 4176 sc->tx_prod_bseq = 0; 4177 sc->used_tx_bd = 0; 4178 sc->max_tx_bd = USABLE_TX_BD; 4179 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 4180 DBRUNIF(1, sc->tx_full_count = 0); 4181 4182 /* 4183 * The NetXtreme II supports a linked-list structure called 4184 * a Buffer Descriptor Chain (or BD chain). A BD chain 4185 * consists of a series of 1 or more chain pages, each of which 4186 * consists of a fixed number of BD entries. 4187 * The last BD entry on each page is a pointer to the next page 4188 * in the chain, and the last pointer in the BD chain 4189 * points back to the beginning of the chain. 4190 */ 4191 4192 /* Set the TX next pointer chain entries. */ 4193 for (i = 0; i < TX_PAGES; i++) { 4194 int j; 4195 4196 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 4197 4198 /* Check if we've reached the last page. */ 4199 if (i == (TX_PAGES - 1)) 4200 j = 0; 4201 else 4202 j = i + 1; 4203 4204 addr = (uint32_t)sc->tx_bd_chain_paddr[j]; 4205 txbd->tx_bd_haddr_lo = addr; 4206 addr = (uint32_t)((uint64_t)sc->tx_bd_chain_paddr[j] >> 32); 4207 txbd->tx_bd_haddr_hi = addr; 4208 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4209 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4210 } 4211 4212 /* 4213 * Initialize the context ID for an L2 TX chain. 4214 */ 4215 bnx_init_tx_context(sc); 4216 4217 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4218 4219 return rc; 4220 } 4221 4222 /****************************************************************************/ 4223 /* Free memory and clear the TX data structures. */ 4224 /* */ 4225 /* Returns: */ 4226 /* Nothing. */ 4227 /****************************************************************************/ 4228 void 4229 bnx_free_tx_chain(struct bnx_softc *sc) 4230 { 4231 struct bnx_pkt *pkt; 4232 int i; 4233 4234 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4235 4236 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 4237 mutex_enter(&sc->tx_pkt_mtx); 4238 while ((pkt = TAILQ_FIRST(&sc->tx_used_pkts)) != NULL) { 4239 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4240 mutex_exit(&sc->tx_pkt_mtx); 4241 4242 bus_dmamap_sync(sc->bnx_dmatag, pkt->pkt_dmamap, 0, 4243 pkt->pkt_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4244 bus_dmamap_unload(sc->bnx_dmatag, pkt->pkt_dmamap); 4245 4246 m_freem(pkt->pkt_mbuf); 4247 DBRUNIF(1, sc->tx_mbuf_alloc--); 4248 4249 mutex_enter(&sc->tx_pkt_mtx); 4250 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4251 } 4252 mutex_exit(&sc->tx_pkt_mtx); 4253 4254 /* Clear each TX chain page. */ 4255 for (i = 0; i < TX_PAGES; i++) { 4256 memset(sc->tx_bd_chain[i], 0, BNX_TX_CHAIN_PAGE_SZ); 4257 bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, 4258 BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); 4259 } 4260 4261 sc->used_tx_bd = 0; 4262 4263 /* Check if we lost any mbufs in the process. */ 4264 DBRUNIF((sc->tx_mbuf_alloc), 4265 aprint_error_dev(sc->bnx_dev, 4266 "Memory leak! Lost %d mbufs from tx chain!\n", 4267 sc->tx_mbuf_alloc)); 4268 4269 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4270 } 4271 4272 /****************************************************************************/ 4273 /* Initialize the RX context memory. */ 4274 /* */ 4275 /* Returns: */ 4276 /* Nothing */ 4277 /****************************************************************************/ 4278 void 4279 bnx_init_rx_context(struct bnx_softc *sc) 4280 { 4281 uint32_t val; 4282 4283 /* Initialize the context ID for an L2 RX chain. */ 4284 val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 4285 BNX_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8); 4286 4287 if (sc->bnx_flowflags & IFM_ETH_TXPAUSE) 4288 val |= 0x000000ff; 4289 4290 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); 4291 4292 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 4293 if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { 4294 val = REG_RD(sc, BNX_MQ_MAP_L2_5); 4295 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM); 4296 } 4297 4298 /* Point the hardware to the first page in the chain. */ 4299 val = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[0] >> 32); 4300 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); 4301 val = (uint32_t)(sc->rx_bd_chain_paddr[0]); 4302 CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); 4303 } 4304 4305 /****************************************************************************/ 4306 /* Allocate memory and initialize the RX data structures. */ 4307 /* */ 4308 /* Returns: */ 4309 /* 0 for success, positive value for failure. */ 4310 /****************************************************************************/ 4311 int 4312 bnx_init_rx_chain(struct bnx_softc *sc) 4313 { 4314 struct rx_bd *rxbd; 4315 int i, rc = 0; 4316 uint16_t prod, chain_prod; 4317 uint32_t prod_bseq, addr; 4318 4319 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4320 4321 /* Initialize the RX producer and consumer indices. */ 4322 sc->rx_prod = 0; 4323 sc->rx_cons = 0; 4324 sc->rx_prod_bseq = 0; 4325 sc->free_rx_bd = USABLE_RX_BD; 4326 sc->max_rx_bd = USABLE_RX_BD; 4327 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 4328 DBRUNIF(1, sc->rx_empty_count = 0); 4329 4330 /* Initialize the RX next pointer chain entries. */ 4331 for (i = 0; i < RX_PAGES; i++) { 4332 int j; 4333 4334 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 4335 4336 /* Check if we've reached the last page. */ 4337 if (i == (RX_PAGES - 1)) 4338 j = 0; 4339 else 4340 j = i + 1; 4341 4342 /* Setup the chain page pointers. */ 4343 addr = (uint32_t)((uint64_t)sc->rx_bd_chain_paddr[j] >> 32); 4344 rxbd->rx_bd_haddr_hi = addr; 4345 addr = (uint32_t)sc->rx_bd_chain_paddr[j]; 4346 rxbd->rx_bd_haddr_lo = addr; 4347 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 4348 0, BNX_RX_CHAIN_PAGE_SZ, 4349 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4350 } 4351 4352 /* Allocate mbuf clusters for the rx_bd chain. */ 4353 prod = prod_bseq = 0; 4354 chain_prod = RX_CHAIN_IDX(prod); 4355 if (bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq)) { 4356 BNX_PRINTF(sc, 4357 "Error filling RX chain: rx_bd[0x%04X]!\n", chain_prod); 4358 } 4359 4360 /* Save the RX chain producer index. */ 4361 sc->rx_prod = prod; 4362 sc->rx_prod_bseq = prod_bseq; 4363 4364 for (i = 0; i < RX_PAGES; i++) 4365 bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, 4366 sc->rx_bd_chain_map[i]->dm_mapsize, 4367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4368 4369 /* Tell the chip about the waiting rx_bd's. */ 4370 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4371 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4372 4373 bnx_init_rx_context(sc); 4374 4375 DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 4376 4377 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4378 4379 return rc; 4380 } 4381 4382 /****************************************************************************/ 4383 /* Free memory and clear the RX data structures. */ 4384 /* */ 4385 /* Returns: */ 4386 /* Nothing. */ 4387 /****************************************************************************/ 4388 void 4389 bnx_free_rx_chain(struct bnx_softc *sc) 4390 { 4391 int i; 4392 4393 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4394 4395 /* Free any mbufs still in the RX mbuf chain. */ 4396 for (i = 0; i < TOTAL_RX_BD; i++) { 4397 if (sc->rx_mbuf_ptr[i] != NULL) { 4398 if (sc->rx_mbuf_map[i] != NULL) { 4399 bus_dmamap_sync(sc->bnx_dmatag, 4400 sc->rx_mbuf_map[i], 0, 4401 sc->rx_mbuf_map[i]->dm_mapsize, 4402 BUS_DMASYNC_POSTREAD); 4403 bus_dmamap_unload(sc->bnx_dmatag, 4404 sc->rx_mbuf_map[i]); 4405 } 4406 m_freem(sc->rx_mbuf_ptr[i]); 4407 sc->rx_mbuf_ptr[i] = NULL; 4408 DBRUNIF(1, sc->rx_mbuf_alloc--); 4409 } 4410 } 4411 4412 /* Clear each RX chain page. */ 4413 for (i = 0; i < RX_PAGES; i++) 4414 memset(sc->rx_bd_chain[i], 0, BNX_RX_CHAIN_PAGE_SZ); 4415 4416 sc->free_rx_bd = sc->max_rx_bd; 4417 4418 /* Check if we lost any mbufs in the process. */ 4419 DBRUNIF((sc->rx_mbuf_alloc), 4420 aprint_error_dev(sc->bnx_dev, 4421 "Memory leak! Lost %d mbufs from rx chain!\n", 4422 sc->rx_mbuf_alloc)); 4423 4424 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 4425 } 4426 4427 /****************************************************************************/ 4428 /* Set media options. */ 4429 /* */ 4430 /* Returns: */ 4431 /* 0 for success, positive value for failure. */ 4432 /****************************************************************************/ 4433 int 4434 bnx_ifmedia_upd(struct ifnet *ifp) 4435 { 4436 struct bnx_softc *sc; 4437 struct mii_data *mii; 4438 int rc = 0; 4439 4440 sc = ifp->if_softc; 4441 4442 mii = &sc->bnx_mii; 4443 sc->bnx_link = 0; 4444 if (mii->mii_instance) { 4445 struct mii_softc *miisc; 4446 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4447 mii_phy_reset(miisc); 4448 } 4449 mii_mediachg(mii); 4450 4451 return rc; 4452 } 4453 4454 /****************************************************************************/ 4455 /* Reports current media status. */ 4456 /* */ 4457 /* Returns: */ 4458 /* Nothing. */ 4459 /****************************************************************************/ 4460 void 4461 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4462 { 4463 struct bnx_softc *sc; 4464 struct mii_data *mii; 4465 int s; 4466 4467 sc = ifp->if_softc; 4468 4469 s = splnet(); 4470 4471 mii = &sc->bnx_mii; 4472 4473 mii_pollstat(mii); 4474 ifmr->ifm_status = mii->mii_media_status; 4475 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4476 sc->bnx_flowflags; 4477 4478 splx(s); 4479 } 4480 4481 /****************************************************************************/ 4482 /* Handles PHY generated interrupt events. */ 4483 /* */ 4484 /* Returns: */ 4485 /* Nothing. */ 4486 /****************************************************************************/ 4487 void 4488 bnx_phy_intr(struct bnx_softc *sc) 4489 { 4490 uint32_t new_link_state, old_link_state; 4491 4492 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4493 BUS_DMASYNC_POSTREAD); 4494 new_link_state = sc->status_block->status_attn_bits & 4495 STATUS_ATTN_BITS_LINK_STATE; 4496 old_link_state = sc->status_block->status_attn_bits_ack & 4497 STATUS_ATTN_BITS_LINK_STATE; 4498 4499 /* Handle any changes if the link state has changed. */ 4500 if (new_link_state != old_link_state) { 4501 DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); 4502 4503 sc->bnx_link = 0; 4504 callout_stop(&sc->bnx_timeout); 4505 bnx_tick(sc); 4506 4507 /* Update the status_attn_bits_ack field in the status block. */ 4508 if (new_link_state) { 4509 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, 4510 STATUS_ATTN_BITS_LINK_STATE); 4511 DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); 4512 } else { 4513 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, 4514 STATUS_ATTN_BITS_LINK_STATE); 4515 DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); 4516 } 4517 } 4518 4519 /* Acknowledge the link change interrupt. */ 4520 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); 4521 } 4522 4523 /****************************************************************************/ 4524 /* Handles received frame interrupt events. */ 4525 /* */ 4526 /* Returns: */ 4527 /* Nothing. */ 4528 /****************************************************************************/ 4529 void 4530 bnx_rx_intr(struct bnx_softc *sc) 4531 { 4532 struct status_block *sblk = sc->status_block; 4533 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4534 uint16_t hw_cons, sw_cons, sw_chain_cons; 4535 uint16_t sw_prod, sw_chain_prod; 4536 uint32_t sw_prod_bseq; 4537 struct l2_fhdr *l2fhdr; 4538 int i; 4539 4540 DBRUNIF(1, sc->rx_interrupts++); 4541 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4542 BUS_DMASYNC_POSTREAD); 4543 4544 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4545 for (i = 0; i < RX_PAGES; i++) 4546 bus_dmamap_sync(sc->bnx_dmatag, 4547 sc->rx_bd_chain_map[i], 0, 4548 sc->rx_bd_chain_map[i]->dm_mapsize, 4549 BUS_DMASYNC_POSTWRITE); 4550 4551 /* Get the hardware's view of the RX consumer index. */ 4552 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4553 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4554 hw_cons++; 4555 4556 /* Get working copies of the driver's view of the RX indices. */ 4557 sw_cons = sc->rx_cons; 4558 sw_prod = sc->rx_prod; 4559 sw_prod_bseq = sc->rx_prod_bseq; 4560 4561 DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4562 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4563 __func__, sw_prod, sw_cons, sw_prod_bseq); 4564 4565 /* Prevent speculative reads from getting ahead of the status block. */ 4566 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4567 BUS_SPACE_BARRIER_READ); 4568 4569 /* Update some debug statistics counters */ 4570 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4571 sc->rx_low_watermark = sc->free_rx_bd); 4572 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4573 4574 /* 4575 * Scan through the receive chain as long 4576 * as there is work to do. 4577 */ 4578 while (sw_cons != hw_cons) { 4579 struct mbuf *m; 4580 struct rx_bd *rxbd __diagused; 4581 unsigned int len; 4582 uint32_t status; 4583 4584 /* Convert the producer/consumer indices to an actual 4585 * rx_bd index. 4586 */ 4587 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4588 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4589 4590 /* Get the used rx_bd. */ 4591 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4592 sc->free_rx_bd++; 4593 4594 DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __func__); 4595 bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); 4596 4597 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4598 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4599 #ifdef DIAGNOSTIC 4600 /* Validate that this is the last rx_bd. */ 4601 if ((rxbd->rx_bd_flags & RX_BD_FLAGS_END) == 0) { 4602 printf("%s: Unexpected mbuf found in " 4603 "rx_bd[0x%04X]!\n", device_xname(sc->bnx_dev), 4604 sw_chain_cons); 4605 } 4606 #endif 4607 4608 /* DRC - ToDo: If the received packet is small, say 4609 * less than 128 bytes, allocate a new mbuf 4610 * here, copy the data to that mbuf, and 4611 * recycle the mapped jumbo frame. 4612 */ 4613 4614 /* Unmap the mbuf from DMA space. */ 4615 #ifdef DIAGNOSTIC 4616 if (sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize == 0) { 4617 printf("invalid map sw_cons 0x%x " 4618 "sw_prod 0x%x " 4619 "sw_chain_cons 0x%x " 4620 "sw_chain_prod 0x%x " 4621 "hw_cons 0x%x " 4622 "TOTAL_RX_BD_PER_PAGE 0x%x " 4623 "TOTAL_RX_BD 0x%x\n", 4624 sw_cons, sw_prod, sw_chain_cons, sw_chain_prod, 4625 hw_cons, 4626 (int)TOTAL_RX_BD_PER_PAGE, (int)TOTAL_RX_BD); 4627 } 4628 #endif 4629 bus_dmamap_sync(sc->bnx_dmatag, 4630 sc->rx_mbuf_map[sw_chain_cons], 0, 4631 sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, 4632 BUS_DMASYNC_POSTREAD); 4633 bus_dmamap_unload(sc->bnx_dmatag, 4634 sc->rx_mbuf_map[sw_chain_cons]); 4635 4636 /* Remove the mbuf from the driver's chain. */ 4637 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4638 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4639 4640 /* 4641 * Frames received on the NetXteme II are prepended 4642 * with the l2_fhdr structure which provides status 4643 * information about the received frame (including 4644 * VLAN tags and checksum info) and are also 4645 * automatically adjusted to align the IP header 4646 * (i.e. two null bytes are inserted before the 4647 * Ethernet header). 4648 */ 4649 l2fhdr = mtod(m, struct l2_fhdr *); 4650 4651 len = l2fhdr->l2_fhdr_pkt_len; 4652 status = l2fhdr->l2_fhdr_status; 4653 4654 DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), 4655 aprint_error("Simulating l2_fhdr status error.\n"); 4656 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4657 4658 /* Watch for unusual sized frames. */ 4659 DBRUNIF(((len < BNX_MIN_MTU) || 4660 (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), 4661 aprint_error_dev(sc->bnx_dev, 4662 "Unusual frame size found. " 4663 "Min(%d), Actual(%d), Max(%d)\n", 4664 (int)BNX_MIN_MTU, len, 4665 (int)BNX_MAX_JUMBO_ETHER_MTU_VLAN); 4666 4667 bnx_dump_mbuf(sc, m); 4668 bnx_breakpoint(sc)); 4669 4670 len -= ETHER_CRC_LEN; 4671 4672 /* Check the received frame for errors. */ 4673 if ((status & (L2_FHDR_ERRORS_BAD_CRC | 4674 L2_FHDR_ERRORS_PHY_DECODE | 4675 L2_FHDR_ERRORS_ALIGNMENT | 4676 L2_FHDR_ERRORS_TOO_SHORT | 4677 L2_FHDR_ERRORS_GIANT_FRAME)) || 4678 len < (BNX_MIN_MTU - ETHER_CRC_LEN) || 4679 len > 4680 (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { 4681 if_statinc(ifp, if_ierrors); 4682 DBRUNIF(1, sc->l2fhdr_status_errors++); 4683 4684 /* Reuse the mbuf for a new frame. */ 4685 if (bnx_add_buf(sc, m, &sw_prod, 4686 &sw_chain_prod, &sw_prod_bseq)) { 4687 DBRUNIF(1, bnx_breakpoint(sc)); 4688 panic("%s: Can't reuse RX mbuf!\n", 4689 device_xname(sc->bnx_dev)); 4690 } 4691 continue; 4692 } 4693 4694 /* 4695 * Get a new mbuf for the rx_bd. If no new 4696 * mbufs are available then reuse the current mbuf, 4697 * log an ierror on the interface, and generate 4698 * an error in the system log. 4699 */ 4700 if (bnx_get_buf(sc, &sw_prod, &sw_chain_prod, 4701 &sw_prod_bseq)) { 4702 DBRUN(BNX_WARN, aprint_debug_dev(sc->bnx_dev, 4703 "Failed to allocate " 4704 "new mbuf, incoming frame dropped!\n")); 4705 4706 if_statinc(ifp, if_ierrors); 4707 4708 /* Try and reuse the exisitng mbuf. */ 4709 if (bnx_add_buf(sc, m, &sw_prod, 4710 &sw_chain_prod, &sw_prod_bseq)) { 4711 DBRUNIF(1, bnx_breakpoint(sc)); 4712 panic("%s: Double mbuf allocation " 4713 "failure!", 4714 device_xname(sc->bnx_dev)); 4715 } 4716 continue; 4717 } 4718 4719 /* Skip over the l2_fhdr when passing the data up 4720 * the stack. 4721 */ 4722 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4723 4724 /* Adjust the pckt length to match the received data. */ 4725 m->m_pkthdr.len = m->m_len = len; 4726 4727 /* Send the packet to the appropriate interface. */ 4728 m_set_rcvif(m, ifp); 4729 4730 DBRUN(BNX_VERBOSE_RECV, 4731 struct ether_header *eh; 4732 eh = mtod(m, struct ether_header *); 4733 aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", 4734 __func__, ether_sprintf(eh->ether_dhost), 4735 ether_sprintf(eh->ether_shost), 4736 htons(eh->ether_type))); 4737 4738 /* Validate the checksum. */ 4739 4740 /* Check for an IP datagram. */ 4741 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4742 /* Check if the IP checksum is valid. */ 4743 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4744 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 4745 #ifdef BNX_DEBUG 4746 else 4747 DBPRINT(sc, BNX_WARN_SEND, 4748 "%s(): Invalid IP checksum " 4749 "= 0x%04X!\n", 4750 __func__, 4751 l2fhdr->l2_fhdr_ip_xsum 4752 ); 4753 #endif 4754 } 4755 4756 /* Check for a valid TCP/UDP frame. */ 4757 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4758 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4759 /* Check for a good TCP/UDP checksum. */ 4760 if ((status & 4761 (L2_FHDR_ERRORS_TCP_XSUM | 4762 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4763 m->m_pkthdr.csum_flags |= 4764 M_CSUM_TCPv4 | 4765 M_CSUM_UDPv4; 4766 } else { 4767 DBPRINT(sc, BNX_WARN_SEND, 4768 "%s(): Invalid TCP/UDP " 4769 "checksum = 0x%04X!\n", 4770 __func__, 4771 l2fhdr->l2_fhdr_tcp_udp_xsum); 4772 } 4773 } 4774 4775 /* 4776 * If we received a packet with a vlan tag, 4777 * attach that information to the packet. 4778 */ 4779 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 4780 !(sc->rx_mode & BNX_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 4781 vlan_set_tag(m, l2fhdr->l2_fhdr_vlan_tag); 4782 } 4783 4784 /* Pass the mbuf off to the upper layers. */ 4785 4786 DBPRINT(sc, BNX_VERBOSE_RECV, 4787 "%s(): Passing received frame up.\n", __func__); 4788 if_percpuq_enqueue(ifp->if_percpuq, m); 4789 DBRUNIF(1, sc->rx_mbuf_alloc--); 4790 4791 } 4792 4793 sw_cons = NEXT_RX_BD(sw_cons); 4794 4795 /* Refresh hw_cons to see if there's new work */ 4796 if (sw_cons == hw_cons) { 4797 hw_cons = sc->hw_rx_cons = 4798 sblk->status_rx_quick_consumer_index0; 4799 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == 4800 USABLE_RX_BD_PER_PAGE) 4801 hw_cons++; 4802 } 4803 4804 /* Prevent speculative reads from getting ahead of 4805 * the status block. 4806 */ 4807 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4808 BUS_SPACE_BARRIER_READ); 4809 } 4810 4811 for (i = 0; i < RX_PAGES; i++) 4812 bus_dmamap_sync(sc->bnx_dmatag, 4813 sc->rx_bd_chain_map[i], 0, 4814 sc->rx_bd_chain_map[i]->dm_mapsize, 4815 BUS_DMASYNC_PREWRITE); 4816 4817 sc->rx_cons = sw_cons; 4818 sc->rx_prod = sw_prod; 4819 sc->rx_prod_bseq = sw_prod_bseq; 4820 4821 REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); 4822 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4823 4824 DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4825 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4826 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4827 } 4828 4829 /****************************************************************************/ 4830 /* Handles transmit completion interrupt events. */ 4831 /* */ 4832 /* Returns: */ 4833 /* Nothing. */ 4834 /****************************************************************************/ 4835 void 4836 bnx_tx_intr(struct bnx_softc *sc) 4837 { 4838 struct status_block *sblk = sc->status_block; 4839 struct ifnet *ifp = &sc->bnx_ec.ec_if; 4840 struct bnx_pkt *pkt; 4841 bus_dmamap_t map; 4842 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4843 4844 DBRUNIF(1, sc->tx_interrupts++); 4845 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 4846 BUS_DMASYNC_POSTREAD); 4847 4848 /* Get the hardware's view of the TX consumer index. */ 4849 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4850 4851 /* Skip to the next entry if this is a chain page pointer. */ 4852 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4853 hw_tx_cons++; 4854 4855 sw_tx_cons = sc->tx_cons; 4856 4857 /* Prevent speculative reads from getting ahead of the status block. */ 4858 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4859 BUS_SPACE_BARRIER_READ); 4860 4861 /* Cycle through any completed TX chain page entries. */ 4862 while (sw_tx_cons != hw_tx_cons) { 4863 #ifdef BNX_DEBUG 4864 struct tx_bd *txbd = NULL; 4865 #endif 4866 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4867 4868 DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " 4869 "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", 4870 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4871 4872 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4873 aprint_error_dev(sc->bnx_dev, 4874 "TX chain consumer out of range! 0x%04X > 0x%04X\n", 4875 sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); 4876 4877 DBRUNIF(1, txbd = &sc->tx_bd_chain 4878 [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); 4879 4880 DBRUNIF((txbd == NULL), 4881 aprint_error_dev(sc->bnx_dev, 4882 "Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); 4883 bnx_breakpoint(sc)); 4884 4885 DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __func__); 4886 bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4887 4888 4889 mutex_enter(&sc->tx_pkt_mtx); 4890 pkt = TAILQ_FIRST(&sc->tx_used_pkts); 4891 if (pkt != NULL && pkt->pkt_end_desc == sw_tx_chain_cons) { 4892 TAILQ_REMOVE(&sc->tx_used_pkts, pkt, pkt_entry); 4893 mutex_exit(&sc->tx_pkt_mtx); 4894 /* 4895 * Free the associated mbuf. Remember 4896 * that only the last tx_bd of a packet 4897 * has an mbuf pointer and DMA map. 4898 */ 4899 map = pkt->pkt_dmamap; 4900 bus_dmamap_sync(sc->bnx_dmatag, map, 0, 4901 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4902 bus_dmamap_unload(sc->bnx_dmatag, map); 4903 4904 m_freem(pkt->pkt_mbuf); 4905 DBRUNIF(1, sc->tx_mbuf_alloc--); 4906 4907 if_statinc(ifp, if_opackets); 4908 4909 mutex_enter(&sc->tx_pkt_mtx); 4910 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 4911 } 4912 mutex_exit(&sc->tx_pkt_mtx); 4913 4914 sc->used_tx_bd--; 4915 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 4916 __FILE__, __LINE__, sc->used_tx_bd); 4917 4918 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4919 4920 /* Refresh hw_cons to see if there's new work. */ 4921 hw_tx_cons = sc->hw_tx_cons = 4922 sblk->status_tx_quick_consumer_index0; 4923 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == 4924 USABLE_TX_BD_PER_PAGE) 4925 hw_tx_cons++; 4926 4927 /* Prevent speculative reads from getting ahead of 4928 * the status block. 4929 */ 4930 bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, 4931 BUS_SPACE_BARRIER_READ); 4932 } 4933 4934 /* Clear the TX timeout timer. */ 4935 ifp->if_timer = 0; 4936 4937 /* Clear the tx hardware queue full flag. */ 4938 if (sc->used_tx_bd < sc->max_tx_bd) { 4939 DBRUNIF((ifp->if_flags & IFF_OACTIVE), 4940 aprint_debug_dev(sc->bnx_dev, 4941 "Open TX chain! %d/%d (used/total)\n", 4942 sc->used_tx_bd, sc->max_tx_bd)); 4943 ifp->if_flags &= ~IFF_OACTIVE; 4944 } 4945 4946 sc->tx_cons = sw_tx_cons; 4947 } 4948 4949 /****************************************************************************/ 4950 /* Disables interrupt generation. */ 4951 /* */ 4952 /* Returns: */ 4953 /* Nothing. */ 4954 /****************************************************************************/ 4955 void 4956 bnx_disable_intr(struct bnx_softc *sc) 4957 { 4958 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); 4959 REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); 4960 } 4961 4962 /****************************************************************************/ 4963 /* Enables interrupt generation. */ 4964 /* */ 4965 /* Returns: */ 4966 /* Nothing. */ 4967 /****************************************************************************/ 4968 void 4969 bnx_enable_intr(struct bnx_softc *sc) 4970 { 4971 uint32_t val; 4972 4973 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4974 BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4975 4976 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | 4977 sc->last_status_idx); 4978 4979 val = REG_RD(sc, BNX_HC_COMMAND); 4980 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); 4981 } 4982 4983 /****************************************************************************/ 4984 /* Handles controller initialization. */ 4985 /* */ 4986 /****************************************************************************/ 4987 int 4988 bnx_init(struct ifnet *ifp) 4989 { 4990 struct bnx_softc *sc = ifp->if_softc; 4991 uint32_t ether_mtu; 4992 int s, error = 0; 4993 4994 DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __func__); 4995 4996 s = splnet(); 4997 4998 bnx_stop(ifp, 0); 4999 5000 if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { 5001 aprint_error_dev(sc->bnx_dev, 5002 "Controller reset failed!\n"); 5003 goto bnx_init_exit; 5004 } 5005 5006 if ((error = bnx_chipinit(sc)) != 0) { 5007 aprint_error_dev(sc->bnx_dev, 5008 "Controller initialization failed!\n"); 5009 goto bnx_init_exit; 5010 } 5011 5012 if ((error = bnx_blockinit(sc)) != 0) { 5013 aprint_error_dev(sc->bnx_dev, 5014 "Block initialization failed!\n"); 5015 goto bnx_init_exit; 5016 } 5017 5018 /* Calculate and program the Ethernet MRU size. */ 5019 if (ifp->if_mtu <= ETHERMTU) { 5020 ether_mtu = BNX_MAX_STD_ETHER_MTU_VLAN; 5021 sc->mbuf_alloc_size = MCLBYTES; 5022 } else { 5023 ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; 5024 sc->mbuf_alloc_size = BNX_MAX_JUMBO_MRU; 5025 } 5026 5027 5028 DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", __func__, ether_mtu); 5029 5030 /* 5031 * Program the MRU and enable Jumbo frame 5032 * support. 5033 */ 5034 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | 5035 BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); 5036 5037 /* Calculate the RX Ethernet frame size for rx_bd's. */ 5038 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 5039 5040 DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 5041 "max_frame_size = %d\n", __func__, (int)MCLBYTES, 5042 sc->mbuf_alloc_size, sc->max_frame_size); 5043 5044 /* Program appropriate promiscuous/multicast filtering. */ 5045 bnx_iff(sc); 5046 5047 /* Init RX buffer descriptor chain. */ 5048 bnx_init_rx_chain(sc); 5049 5050 /* Init TX buffer descriptor chain. */ 5051 bnx_init_tx_chain(sc); 5052 5053 /* Enable host interrupts. */ 5054 bnx_enable_intr(sc); 5055 5056 mii_ifmedia_change(&sc->bnx_mii); 5057 5058 SET(ifp->if_flags, IFF_RUNNING); 5059 CLR(ifp->if_flags, IFF_OACTIVE); 5060 5061 callout_schedule(&sc->bnx_timeout, hz); 5062 5063 bnx_init_exit: 5064 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5065 5066 splx(s); 5067 5068 return error; 5069 } 5070 5071 void 5072 bnx_mgmt_init(struct bnx_softc *sc) 5073 { 5074 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5075 uint32_t val; 5076 5077 /* Check if the driver is still running and bail out if it is. */ 5078 if (ifp->if_flags & IFF_RUNNING) 5079 goto bnx_mgmt_init_exit; 5080 5081 /* Initialize the on-boards CPUs */ 5082 bnx_init_cpus(sc); 5083 5084 val = (BCM_PAGE_BITS - 8) << 24; 5085 REG_WR(sc, BNX_RV2P_CONFIG, val); 5086 5087 /* Enable all critical blocks in the MAC. */ 5088 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 5089 BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 5090 BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 5091 BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 5092 REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); 5093 DELAY(20); 5094 5095 mii_ifmedia_change(&sc->bnx_mii); 5096 5097 bnx_mgmt_init_exit: 5098 DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __func__); 5099 } 5100 5101 /****************************************************************************/ 5102 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 5103 /* memory visible to the controller. */ 5104 /* */ 5105 /* Returns: */ 5106 /* 0 for success, positive value for failure. */ 5107 /****************************************************************************/ 5108 int 5109 bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m) 5110 { 5111 struct bnx_pkt *pkt; 5112 bus_dmamap_t map; 5113 struct tx_bd *txbd = NULL; 5114 uint16_t vlan_tag = 0, flags = 0; 5115 uint16_t chain_prod, prod; 5116 #ifdef BNX_DEBUG 5117 uint16_t debug_prod; 5118 #endif 5119 uint32_t addr, prod_bseq; 5120 int i, error; 5121 bool remap = true; 5122 5123 mutex_enter(&sc->tx_pkt_mtx); 5124 pkt = TAILQ_FIRST(&sc->tx_free_pkts); 5125 if (pkt == NULL) { 5126 if (!ISSET(sc->bnx_ec.ec_if.if_flags, IFF_UP)) { 5127 mutex_exit(&sc->tx_pkt_mtx); 5128 return ENETDOWN; 5129 } 5130 5131 if (sc->tx_pkt_count <= TOTAL_TX_BD && 5132 !ISSET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG)) { 5133 workqueue_enqueue(sc->bnx_wq, &sc->bnx_wk, NULL); 5134 SET(sc->bnx_flags, BNX_ALLOC_PKTS_FLAG); 5135 } 5136 5137 mutex_exit(&sc->tx_pkt_mtx); 5138 return ENOMEM; 5139 } 5140 TAILQ_REMOVE(&sc->tx_free_pkts, pkt, pkt_entry); 5141 mutex_exit(&sc->tx_pkt_mtx); 5142 5143 /* Transfer any checksum offload flags to the bd. */ 5144 if (m->m_pkthdr.csum_flags) { 5145 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5146 flags |= TX_BD_FLAGS_IP_CKSUM; 5147 if (m->m_pkthdr.csum_flags & 5148 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 5149 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 5150 } 5151 5152 /* Transfer any VLAN tags to the bd. */ 5153 if (vlan_has_tag(m)) { 5154 flags |= TX_BD_FLAGS_VLAN_TAG; 5155 vlan_tag = vlan_get_tag(m); 5156 } 5157 5158 /* Map the mbuf into DMAable memory. */ 5159 prod = sc->tx_prod; 5160 chain_prod = TX_CHAIN_IDX(prod); 5161 map = pkt->pkt_dmamap; 5162 5163 /* Map the mbuf into our DMA address space. */ 5164 retry: 5165 error = bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m, BUS_DMA_NOWAIT); 5166 if (__predict_false(error)) { 5167 if (error == EFBIG) { 5168 if (remap == true) { 5169 struct mbuf *newm; 5170 5171 remap = false; 5172 newm = m_defrag(m, M_NOWAIT); 5173 if (newm != NULL) { 5174 m = newm; 5175 goto retry; 5176 } 5177 } 5178 } 5179 sc->tx_dma_map_failures++; 5180 goto maperr; 5181 } 5182 bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, 5183 BUS_DMASYNC_PREWRITE); 5184 /* Make sure there's room in the chain */ 5185 if (map->dm_nsegs > (sc->max_tx_bd - sc->used_tx_bd)) 5186 goto nospace; 5187 5188 /* prod points to an empty tx_bd at this point. */ 5189 prod_bseq = sc->tx_prod_bseq; 5190 #ifdef BNX_DEBUG 5191 debug_prod = chain_prod; 5192 #endif 5193 DBPRINT(sc, BNX_INFO_SEND, 5194 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 5195 "prod_bseq = 0x%08X\n", 5196 __func__, prod, chain_prod, prod_bseq); 5197 5198 /* 5199 * Cycle through each mbuf segment that makes up 5200 * the outgoing frame, gathering the mapping info 5201 * for that segment and creating a tx_bd for the 5202 * mbuf. 5203 */ 5204 for (i = 0; i < map->dm_nsegs ; i++) { 5205 chain_prod = TX_CHAIN_IDX(prod); 5206 txbd = &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 5207 5208 addr = (uint32_t)map->dm_segs[i].ds_addr; 5209 txbd->tx_bd_haddr_lo = addr; 5210 addr = (uint32_t)((uint64_t)map->dm_segs[i].ds_addr >> 32); 5211 txbd->tx_bd_haddr_hi = addr; 5212 txbd->tx_bd_mss_nbytes = map->dm_segs[i].ds_len; 5213 txbd->tx_bd_vlan_tag = vlan_tag; 5214 txbd->tx_bd_flags = flags; 5215 prod_bseq += map->dm_segs[i].ds_len; 5216 if (i == 0) 5217 txbd->tx_bd_flags |= TX_BD_FLAGS_START; 5218 prod = NEXT_TX_BD(prod); 5219 } 5220 5221 /* Set the END flag on the last TX buffer descriptor. */ 5222 txbd->tx_bd_flags |= TX_BD_FLAGS_END; 5223 5224 DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, map->dm_nsegs)); 5225 5226 DBPRINT(sc, BNX_INFO_SEND, 5227 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 5228 "prod_bseq = 0x%08X\n", 5229 __func__, prod, chain_prod, prod_bseq); 5230 5231 pkt->pkt_mbuf = m; 5232 pkt->pkt_end_desc = chain_prod; 5233 5234 mutex_enter(&sc->tx_pkt_mtx); 5235 TAILQ_INSERT_TAIL(&sc->tx_used_pkts, pkt, pkt_entry); 5236 mutex_exit(&sc->tx_pkt_mtx); 5237 5238 sc->used_tx_bd += map->dm_nsegs; 5239 DBPRINT(sc, BNX_INFO_SEND, "%s(%d) used_tx_bd %d\n", 5240 __FILE__, __LINE__, sc->used_tx_bd); 5241 5242 /* Update some debug statistics counters */ 5243 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 5244 sc->tx_hi_watermark = sc->used_tx_bd); 5245 DBRUNIF(sc->used_tx_bd == sc->max_tx_bd, sc->tx_full_count++); 5246 DBRUNIF(1, sc->tx_mbuf_alloc++); 5247 5248 DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, 5249 map->dm_nsegs)); 5250 5251 /* prod points to the next free tx_bd at this point. */ 5252 sc->tx_prod = prod; 5253 sc->tx_prod_bseq = prod_bseq; 5254 5255 return 0; 5256 5257 5258 nospace: 5259 bus_dmamap_unload(sc->bnx_dmatag, map); 5260 maperr: 5261 mutex_enter(&sc->tx_pkt_mtx); 5262 TAILQ_INSERT_TAIL(&sc->tx_free_pkts, pkt, pkt_entry); 5263 mutex_exit(&sc->tx_pkt_mtx); 5264 5265 return ENOMEM; 5266 } 5267 5268 /****************************************************************************/ 5269 /* Main transmit routine. */ 5270 /* */ 5271 /* Returns: */ 5272 /* Nothing. */ 5273 /****************************************************************************/ 5274 void 5275 bnx_start(struct ifnet *ifp) 5276 { 5277 struct bnx_softc *sc = ifp->if_softc; 5278 struct mbuf *m_head = NULL; 5279 int count = 0; 5280 #ifdef BNX_DEBUG 5281 uint16_t tx_chain_prod; 5282 #endif 5283 5284 /* If there's no link or the transmit queue is empty then just exit. */ 5285 if (!sc->bnx_link 5286 ||(ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) { 5287 DBPRINT(sc, BNX_INFO_SEND, 5288 "%s(): output active or device not running.\n", __func__); 5289 goto bnx_start_exit; 5290 } 5291 5292 /* prod points to the next free tx_bd. */ 5293 #ifdef BNX_DEBUG 5294 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5295 #endif 5296 5297 DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " 5298 "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X, " 5299 "used_tx %d max_tx %d\n", 5300 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq, 5301 sc->used_tx_bd, sc->max_tx_bd); 5302 5303 /* 5304 * Keep adding entries while there is space in the ring. 5305 */ 5306 while (sc->used_tx_bd < sc->max_tx_bd) { 5307 /* Check for any frames to send. */ 5308 IFQ_POLL(&ifp->if_snd, m_head); 5309 if (m_head == NULL) 5310 break; 5311 5312 /* 5313 * Pack the data into the transmit ring. If we 5314 * don't have room, set the OACTIVE flag to wait 5315 * for the NIC to drain the chain. 5316 */ 5317 if (bnx_tx_encap(sc, m_head)) { 5318 ifp->if_flags |= IFF_OACTIVE; 5319 DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " 5320 "business! Total tx_bd used = %d\n", 5321 sc->used_tx_bd); 5322 break; 5323 } 5324 5325 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5326 count++; 5327 5328 /* Send a copy of the frame to any BPF listeners. */ 5329 bpf_mtap(ifp, m_head, BPF_D_OUT); 5330 } 5331 5332 if (count == 0) { 5333 /* no packets were dequeued */ 5334 DBPRINT(sc, BNX_VERBOSE_SEND, 5335 "%s(): No packets were dequeued\n", __func__); 5336 goto bnx_start_exit; 5337 } 5338 5339 /* Update the driver's counters. */ 5340 #ifdef BNX_DEBUG 5341 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 5342 #endif 5343 5344 DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, " 5345 "tx_chain_prod = 0x%04X, tx_prod_bseq = 0x%08X\n", 5346 __func__, sc->tx_prod, tx_chain_prod, sc->tx_prod_bseq); 5347 5348 /* Start the transmit. */ 5349 REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); 5350 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 5351 5352 /* Set the tx timeout. */ 5353 ifp->if_timer = BNX_TX_TIMEOUT; 5354 5355 bnx_start_exit: 5356 return; 5357 } 5358 5359 /****************************************************************************/ 5360 /* Handles any IOCTL calls from the operating system. */ 5361 /* */ 5362 /* Returns: */ 5363 /* 0 for success, positive value for failure. */ 5364 /****************************************************************************/ 5365 int 5366 bnx_ioctl(struct ifnet *ifp, u_long command, void *data) 5367 { 5368 struct bnx_softc *sc = ifp->if_softc; 5369 struct ifreq *ifr = (struct ifreq *) data; 5370 struct mii_data *mii = &sc->bnx_mii; 5371 int s, error = 0; 5372 5373 s = splnet(); 5374 5375 switch (command) { 5376 case SIOCSIFFLAGS: 5377 if ((error = ifioctl_common(ifp, command, data)) != 0) 5378 break; 5379 /* XXX set an ifflags callback and let ether_ioctl 5380 * handle all of this. 5381 */ 5382 if (ISSET(ifp->if_flags, IFF_UP)) { 5383 if (ifp->if_flags & IFF_RUNNING) 5384 error = ENETRESET; 5385 else 5386 bnx_init(ifp); 5387 } else if (ifp->if_flags & IFF_RUNNING) 5388 bnx_stop(ifp, 1); 5389 break; 5390 5391 case SIOCSIFMEDIA: 5392 /* Flow control requires full-duplex mode. */ 5393 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5394 (ifr->ifr_media & IFM_FDX) == 0) 5395 ifr->ifr_media &= ~IFM_ETH_FMASK; 5396 5397 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5398 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5399 /* We can do both TXPAUSE and RXPAUSE. */ 5400 ifr->ifr_media |= 5401 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5402 } 5403 sc->bnx_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5404 } 5405 DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", 5406 sc->bnx_phy_flags); 5407 5408 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 5409 break; 5410 5411 default: 5412 error = ether_ioctl(ifp, command, data); 5413 } 5414 5415 if (error == ENETRESET) { 5416 if (ifp->if_flags & IFF_RUNNING) 5417 bnx_iff(sc); 5418 error = 0; 5419 } 5420 5421 splx(s); 5422 return error; 5423 } 5424 5425 /****************************************************************************/ 5426 /* Transmit timeout handler. */ 5427 /* */ 5428 /* Returns: */ 5429 /* Nothing. */ 5430 /****************************************************************************/ 5431 void 5432 bnx_watchdog(struct ifnet *ifp) 5433 { 5434 struct bnx_softc *sc = ifp->if_softc; 5435 5436 DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); 5437 bnx_dump_status_block(sc)); 5438 /* 5439 * If we are in this routine because of pause frames, then 5440 * don't reset the hardware. 5441 */ 5442 if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) 5443 return; 5444 5445 aprint_error_dev(sc->bnx_dev, "Watchdog timeout -- resetting!\n"); 5446 5447 /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ 5448 5449 bnx_init(ifp); 5450 5451 if_statinc(ifp, if_oerrors); 5452 } 5453 5454 /* 5455 * Interrupt handler. 5456 */ 5457 /****************************************************************************/ 5458 /* Main interrupt entry point. Verifies that the controller generated the */ 5459 /* interrupt and then calls a separate routine for handle the various */ 5460 /* interrupt causes (PHY, TX, RX). */ 5461 /* */ 5462 /* Returns: */ 5463 /* 0 for success, positive value for failure. */ 5464 /****************************************************************************/ 5465 int 5466 bnx_intr(void *xsc) 5467 { 5468 struct bnx_softc *sc = xsc; 5469 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5470 uint32_t status_attn_bits; 5471 uint16_t status_idx; 5472 const struct status_block *sblk; 5473 int rv = 0; 5474 5475 if (!device_is_active(sc->bnx_dev) || 5476 (ifp->if_flags & IFF_RUNNING) == 0) 5477 return 0; 5478 5479 DBRUNIF(1, sc->interrupts_generated++); 5480 5481 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5482 sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 5483 5484 sblk = sc->status_block; 5485 /* 5486 * If the hardware status block index 5487 * matches the last value read by the 5488 * driver and we haven't asserted our 5489 * interrupt then there's nothing to do. 5490 */ 5491 status_idx = sblk->status_idx; 5492 if ((status_idx != sc->last_status_idx) || 5493 !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), 5494 BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { 5495 rv = 1; 5496 5497 /* Ack the interrupt */ 5498 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, 5499 BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | status_idx); 5500 5501 status_attn_bits = sblk->status_attn_bits; 5502 5503 DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), 5504 aprint_debug("Simulating unexpected status attention bit set."); 5505 status_attn_bits = status_attn_bits | 5506 STATUS_ATTN_BITS_PARITY_ERROR); 5507 5508 /* Was it a link change interrupt? */ 5509 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5510 (sblk->status_attn_bits_ack & 5511 STATUS_ATTN_BITS_LINK_STATE)) 5512 bnx_phy_intr(sc); 5513 5514 /* If any other attention is asserted then the chip is toast. */ 5515 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5516 (sblk->status_attn_bits_ack & 5517 ~STATUS_ATTN_BITS_LINK_STATE))) { 5518 DBRUN(sc->unexpected_attentions++); 5519 5520 BNX_PRINTF(sc, "Fatal attention detected: 0x%08X\n", 5521 sblk->status_attn_bits); 5522 5523 DBRUNIF((bnx_debug_unexpected_attention == 0), 5524 bnx_breakpoint(sc)); 5525 5526 bnx_init(ifp); 5527 goto out; 5528 } 5529 5530 /* Check for any completed RX frames. */ 5531 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5532 bnx_rx_intr(sc); 5533 5534 /* Check for any completed TX frames. */ 5535 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5536 bnx_tx_intr(sc); 5537 5538 /* 5539 * Save the status block index value for use during the 5540 * next interrupt. 5541 */ 5542 sc->last_status_idx = status_idx; 5543 5544 /* Start moving packets again */ 5545 if (ifp->if_flags & IFF_RUNNING) 5546 if_schedule_deferred_start(ifp); 5547 } 5548 5549 out: 5550 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, 5551 sc->status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 5552 5553 return rv; 5554 } 5555 5556 /****************************************************************************/ 5557 /* Programs the various packet receive modes (broadcast and multicast). */ 5558 /* */ 5559 /* Returns: */ 5560 /* Nothing. */ 5561 /****************************************************************************/ 5562 void 5563 bnx_iff(struct bnx_softc *sc) 5564 { 5565 struct ethercom *ec = &sc->bnx_ec; 5566 struct ifnet *ifp = &ec->ec_if; 5567 struct ether_multi *enm; 5568 struct ether_multistep step; 5569 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5570 uint32_t rx_mode, sort_mode; 5571 int h, i; 5572 5573 /* Initialize receive mode default settings. */ 5574 rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | 5575 BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); 5576 sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; 5577 ifp->if_flags &= ~IFF_ALLMULTI; 5578 5579 /* 5580 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5581 * be enbled. 5582 */ 5583 if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) 5584 rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; 5585 5586 /* 5587 * Check for promiscuous, all multicast, or selected 5588 * multicast address filtering. 5589 */ 5590 if (ifp->if_flags & IFF_PROMISC) { 5591 DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); 5592 5593 ifp->if_flags |= IFF_ALLMULTI; 5594 /* Enable promiscuous mode. */ 5595 rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; 5596 sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; 5597 } else if (ifp->if_flags & IFF_ALLMULTI) { 5598 allmulti: 5599 DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); 5600 5601 ifp->if_flags |= IFF_ALLMULTI; 5602 /* Enable all multicast addresses. */ 5603 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5604 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5605 0xffffffff); 5606 sort_mode |= BNX_RPM_SORT_USER0_MC_EN; 5607 } else { 5608 /* Accept one or more multicast(s). */ 5609 DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); 5610 5611 ETHER_LOCK(ec); 5612 ETHER_FIRST_MULTI(step, ec, enm); 5613 while (enm != NULL) { 5614 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 5615 ETHER_ADDR_LEN)) { 5616 ETHER_UNLOCK(ec); 5617 goto allmulti; 5618 } 5619 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 5620 0xFF; 5621 hashes[(h & 0xE0) >> 5] |= __BIT(h & 0x1F); 5622 ETHER_NEXT_MULTI(step, enm); 5623 } 5624 ETHER_UNLOCK(ec); 5625 5626 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5627 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), 5628 hashes[i]); 5629 5630 sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; 5631 } 5632 5633 /* Only make changes if the receive mode has actually changed. */ 5634 if (rx_mode != sc->rx_mode) { 5635 DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5636 rx_mode); 5637 5638 sc->rx_mode = rx_mode; 5639 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); 5640 } 5641 5642 /* Disable and clear the exisitng sort before enabling a new sort. */ 5643 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); 5644 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); 5645 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); 5646 } 5647 5648 /****************************************************************************/ 5649 /* Called periodically to updates statistics from the controllers */ 5650 /* statistics block. */ 5651 /* */ 5652 /* Returns: */ 5653 /* Nothing. */ 5654 /****************************************************************************/ 5655 void 5656 bnx_stats_update(struct bnx_softc *sc) 5657 { 5658 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5659 struct statistics_block *stats; 5660 5661 DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __func__); 5662 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 5663 BUS_DMASYNC_POSTREAD); 5664 5665 stats = (struct statistics_block *)sc->stats_block; 5666 5667 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 5668 uint64_t value; 5669 5670 /* 5671 * Update the interface statistics from the 5672 * hardware statistics. 5673 */ 5674 value = (u_long)stats->stat_EtherStatsCollisions; 5675 if_statadd_ref(nsr, if_collisions, value - sc->if_stat_collisions); 5676 sc->if_stat_collisions = value; 5677 5678 value = (u_long)stats->stat_EtherStatsUndersizePkts + 5679 (u_long)stats->stat_EtherStatsOverrsizePkts + 5680 (u_long)stats->stat_IfInMBUFDiscards + 5681 (u_long)stats->stat_Dot3StatsAlignmentErrors + 5682 (u_long)stats->stat_Dot3StatsFCSErrors; 5683 if_statadd_ref(nsr, if_ierrors, value - sc->if_stat_ierrors); 5684 sc->if_stat_ierrors = value; 5685 5686 value = (u_long) 5687 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5688 (u_long)stats->stat_Dot3StatsExcessiveCollisions + 5689 (u_long)stats->stat_Dot3StatsLateCollisions; 5690 if_statadd_ref(nsr, if_oerrors, value - sc->if_stat_oerrors); 5691 sc->if_stat_oerrors = value; 5692 5693 /* 5694 * Certain controllers don't report 5695 * carrier sense errors correctly. 5696 * See errata E11_5708CA0_1165. 5697 */ 5698 if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && 5699 !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) { 5700 if_statadd_ref(nsr, if_oerrors, 5701 (u_long) stats->stat_Dot3StatsCarrierSenseErrors); 5702 } 5703 5704 IF_STAT_PUTREF(ifp); 5705 5706 /* 5707 * Update the sysctl statistics from the 5708 * hardware statistics. 5709 */ 5710 sc->stat_IfHCInOctets = ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + 5711 (uint64_t) stats->stat_IfHCInOctets_lo; 5712 5713 sc->stat_IfHCInBadOctets = 5714 ((uint64_t) stats->stat_IfHCInBadOctets_hi << 32) + 5715 (uint64_t) stats->stat_IfHCInBadOctets_lo; 5716 5717 sc->stat_IfHCOutOctets = 5718 ((uint64_t) stats->stat_IfHCOutOctets_hi << 32) + 5719 (uint64_t) stats->stat_IfHCOutOctets_lo; 5720 5721 sc->stat_IfHCOutBadOctets = 5722 ((uint64_t) stats->stat_IfHCOutBadOctets_hi << 32) + 5723 (uint64_t) stats->stat_IfHCOutBadOctets_lo; 5724 5725 sc->stat_IfHCInUcastPkts = 5726 ((uint64_t) stats->stat_IfHCInUcastPkts_hi << 32) + 5727 (uint64_t) stats->stat_IfHCInUcastPkts_lo; 5728 5729 sc->stat_IfHCInMulticastPkts = 5730 ((uint64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + 5731 (uint64_t) stats->stat_IfHCInMulticastPkts_lo; 5732 5733 sc->stat_IfHCInBroadcastPkts = 5734 ((uint64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5735 (uint64_t) stats->stat_IfHCInBroadcastPkts_lo; 5736 5737 sc->stat_IfHCOutUcastPkts = 5738 ((uint64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + 5739 (uint64_t) stats->stat_IfHCOutUcastPkts_lo; 5740 5741 sc->stat_IfHCOutMulticastPkts = 5742 ((uint64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5743 (uint64_t) stats->stat_IfHCOutMulticastPkts_lo; 5744 5745 sc->stat_IfHCOutBroadcastPkts = 5746 ((uint64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5747 (uint64_t) stats->stat_IfHCOutBroadcastPkts_lo; 5748 5749 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5750 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5751 5752 sc->stat_Dot3StatsCarrierSenseErrors = 5753 stats->stat_Dot3StatsCarrierSenseErrors; 5754 5755 sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; 5756 5757 sc->stat_Dot3StatsAlignmentErrors = 5758 stats->stat_Dot3StatsAlignmentErrors; 5759 5760 sc->stat_Dot3StatsSingleCollisionFrames = 5761 stats->stat_Dot3StatsSingleCollisionFrames; 5762 5763 sc->stat_Dot3StatsMultipleCollisionFrames = 5764 stats->stat_Dot3StatsMultipleCollisionFrames; 5765 5766 sc->stat_Dot3StatsDeferredTransmissions = 5767 stats->stat_Dot3StatsDeferredTransmissions; 5768 5769 sc->stat_Dot3StatsExcessiveCollisions = 5770 stats->stat_Dot3StatsExcessiveCollisions; 5771 5772 sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; 5773 5774 sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; 5775 5776 sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; 5777 5778 sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; 5779 5780 sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; 5781 5782 sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; 5783 5784 sc->stat_EtherStatsPktsRx64Octets = 5785 stats->stat_EtherStatsPktsRx64Octets; 5786 5787 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5788 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5789 5790 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5791 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5792 5793 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5794 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5795 5796 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5797 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5798 5799 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5800 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5801 5802 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5803 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5804 5805 sc->stat_EtherStatsPktsTx64Octets = 5806 stats->stat_EtherStatsPktsTx64Octets; 5807 5808 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5809 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5810 5811 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5812 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5813 5814 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5815 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5816 5817 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5818 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5819 5820 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5821 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5822 5823 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5824 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5825 5826 sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; 5827 5828 sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; 5829 5830 sc->stat_OutXonSent = stats->stat_OutXonSent; 5831 5832 sc->stat_OutXoffSent = stats->stat_OutXoffSent; 5833 5834 sc->stat_FlowControlDone = stats->stat_FlowControlDone; 5835 5836 sc->stat_MacControlFramesReceived = 5837 stats->stat_MacControlFramesReceived; 5838 5839 sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; 5840 5841 sc->stat_IfInFramesL2FilterDiscards = 5842 stats->stat_IfInFramesL2FilterDiscards; 5843 5844 sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; 5845 5846 sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; 5847 5848 sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; 5849 5850 sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; 5851 5852 sc->stat_CatchupInRuleCheckerDiscards = 5853 stats->stat_CatchupInRuleCheckerDiscards; 5854 5855 sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; 5856 5857 sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; 5858 5859 sc->stat_CatchupInRuleCheckerP4Hit = 5860 stats->stat_CatchupInRuleCheckerP4Hit; 5861 5862 DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __func__); 5863 } 5864 5865 void 5866 bnx_tick(void *xsc) 5867 { 5868 struct bnx_softc *sc = xsc; 5869 struct ifnet *ifp = &sc->bnx_ec.ec_if; 5870 struct mii_data *mii; 5871 uint32_t msg; 5872 uint16_t prod, chain_prod; 5873 uint32_t prod_bseq; 5874 int s = splnet(); 5875 5876 /* Tell the firmware that the driver is still running. */ 5877 #ifdef BNX_DEBUG 5878 msg = (uint32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5879 #else 5880 msg = (uint32_t)++sc->bnx_fw_drv_pulse_wr_seq; 5881 #endif 5882 REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); 5883 5884 /* Update the statistics from the hardware statistics block. */ 5885 bnx_stats_update(sc); 5886 5887 /* Schedule the next tick. */ 5888 if (!sc->bnx_detaching) 5889 callout_schedule(&sc->bnx_timeout, hz); 5890 5891 if (sc->bnx_link) 5892 goto bnx_tick_exit; 5893 5894 mii = &sc->bnx_mii; 5895 mii_tick(mii); 5896 5897 /* Check if the link has come up. */ 5898 if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && 5899 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5900 sc->bnx_link++; 5901 /* Now that link is up, handle any outstanding TX traffic. */ 5902 if_schedule_deferred_start(ifp); 5903 } 5904 5905 bnx_tick_exit: 5906 /* try to get more RX buffers, just in case */ 5907 prod = sc->rx_prod; 5908 prod_bseq = sc->rx_prod_bseq; 5909 chain_prod = RX_CHAIN_IDX(prod); 5910 bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); 5911 sc->rx_prod = prod; 5912 sc->rx_prod_bseq = prod_bseq; 5913 5914 splx(s); 5915 return; 5916 } 5917 5918 /****************************************************************************/ 5919 /* BNX Debug Routines */ 5920 /****************************************************************************/ 5921 #ifdef BNX_DEBUG 5922 5923 /****************************************************************************/ 5924 /* Prints out information about an mbuf. */ 5925 /* */ 5926 /* Returns: */ 5927 /* Nothing. */ 5928 /****************************************************************************/ 5929 void 5930 bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) 5931 { 5932 struct mbuf *mp = m; 5933 5934 if (m == NULL) { 5935 /* Index out of range. */ 5936 aprint_error("mbuf ptr is null!\n"); 5937 return; 5938 } 5939 5940 while (mp) { 5941 aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", 5942 mp, mp->m_len); 5943 5944 if (mp->m_flags & M_EXT) 5945 aprint_debug("M_EXT "); 5946 if (mp->m_flags & M_PKTHDR) 5947 aprint_debug("M_PKTHDR "); 5948 aprint_debug("\n"); 5949 5950 if (mp->m_flags & M_EXT) 5951 aprint_debug("- m_ext: vaddr = %p, " 5952 "ext_size = 0x%04zX\n", mp, mp->m_ext.ext_size); 5953 5954 mp = mp->m_next; 5955 } 5956 } 5957 5958 /****************************************************************************/ 5959 /* Prints out the mbufs in the TX mbuf chain. */ 5960 /* */ 5961 /* Returns: */ 5962 /* Nothing. */ 5963 /****************************************************************************/ 5964 void 5965 bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5966 { 5967 #if 0 5968 struct mbuf *m; 5969 int i; 5970 5971 aprint_debug_dev(sc->bnx_dev, 5972 "----------------------------" 5973 " tx mbuf data " 5974 "----------------------------\n"); 5975 5976 for (i = 0; i < count; i++) { 5977 m = sc->tx_mbuf_ptr[chain_prod]; 5978 BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 5979 bnx_dump_mbuf(sc, m); 5980 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 5981 } 5982 5983 aprint_debug_dev(sc->bnx_dev, 5984 "--------------------------------------------" 5985 "----------------------------\n"); 5986 #endif 5987 } 5988 5989 /* 5990 * This routine prints the RX mbuf chain. 5991 */ 5992 void 5993 bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) 5994 { 5995 struct mbuf *m; 5996 int i; 5997 5998 aprint_debug_dev(sc->bnx_dev, 5999 "----------------------------" 6000 " rx mbuf data " 6001 "----------------------------\n"); 6002 6003 for (i = 0; i < count; i++) { 6004 m = sc->rx_mbuf_ptr[chain_prod]; 6005 BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6006 bnx_dump_mbuf(sc, m); 6007 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6008 } 6009 6010 6011 aprint_debug_dev(sc->bnx_dev, 6012 "--------------------------------------------" 6013 "----------------------------\n"); 6014 } 6015 6016 void 6017 bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) 6018 { 6019 if (idx > MAX_TX_BD) 6020 /* Index out of range. */ 6021 BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6022 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6023 /* TX Chain page pointer. */ 6024 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " 6025 "page pointer\n", idx, txbd->tx_bd_haddr_hi, 6026 txbd->tx_bd_haddr_lo); 6027 else 6028 /* Normal tx_bd entry. */ 6029 BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6030 "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, 6031 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6032 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6033 txbd->tx_bd_flags); 6034 } 6035 6036 void 6037 bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) 6038 { 6039 if (idx > MAX_RX_BD) 6040 /* Index out of range. */ 6041 BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6042 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6043 /* TX Chain page pointer. */ 6044 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 6045 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 6046 rxbd->rx_bd_haddr_lo); 6047 else 6048 /* Normal tx_bd entry. */ 6049 BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 6050 "0x%08X, flags = 0x%08X\n", idx, 6051 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6052 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6053 } 6054 6055 void 6056 bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6057 { 6058 BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6059 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6060 "tcp_udp_xsum = 0x%04X\n", idx, 6061 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6062 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6063 l2fhdr->l2_fhdr_tcp_udp_xsum); 6064 } 6065 6066 /* 6067 * This routine prints the TX chain. 6068 */ 6069 void 6070 bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) 6071 { 6072 struct tx_bd *txbd; 6073 int i; 6074 6075 /* First some info about the tx_bd chain structure. */ 6076 aprint_debug_dev(sc->bnx_dev, 6077 "----------------------------" 6078 " tx_bd chain " 6079 "----------------------------\n"); 6080 6081 BNX_PRINTF(sc, 6082 "page size = 0x%08X, tx chain pages = 0x%08X\n", 6083 (uint32_t)BCM_PAGE_SIZE, (uint32_t) TX_PAGES); 6084 6085 BNX_PRINTF(sc, 6086 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6087 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE); 6088 6089 BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); 6090 6091 aprint_error_dev(sc->bnx_dev, "" 6092 "-----------------------------" 6093 " tx_bd data " 6094 "-----------------------------\n"); 6095 6096 /* Now print out the tx_bd's themselves. */ 6097 for (i = 0; i < count; i++) { 6098 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6099 bnx_dump_txbd(sc, tx_prod, txbd); 6100 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6101 } 6102 6103 aprint_debug_dev(sc->bnx_dev, 6104 "-----------------------------" 6105 "--------------" 6106 "-----------------------------\n"); 6107 } 6108 6109 /* 6110 * This routine prints the RX chain. 6111 */ 6112 void 6113 bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) 6114 { 6115 struct rx_bd *rxbd; 6116 int i; 6117 6118 /* First some info about the tx_bd chain structure. */ 6119 aprint_debug_dev(sc->bnx_dev, 6120 "----------------------------" 6121 " rx_bd chain " 6122 "----------------------------\n"); 6123 6124 aprint_debug_dev(sc->bnx_dev, "----- RX_BD Chain -----\n"); 6125 6126 BNX_PRINTF(sc, 6127 "page size = 0x%08X, rx chain pages = 0x%08X\n", 6128 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); 6129 6130 BNX_PRINTF(sc, 6131 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6132 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE); 6133 6134 BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); 6135 6136 aprint_error_dev(sc->bnx_dev, 6137 "----------------------------" 6138 " rx_bd data " 6139 "----------------------------\n"); 6140 6141 /* Now print out the rx_bd's themselves. */ 6142 for (i = 0; i < count; i++) { 6143 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6144 bnx_dump_rxbd(sc, rx_prod, rxbd); 6145 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6146 } 6147 6148 aprint_debug_dev(sc->bnx_dev, 6149 "----------------------------" 6150 "--------------" 6151 "----------------------------\n"); 6152 } 6153 6154 /* 6155 * This routine prints the status block. 6156 */ 6157 void 6158 bnx_dump_status_block(struct bnx_softc *sc) 6159 { 6160 struct status_block *sblk; 6161 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6162 BUS_DMASYNC_POSTREAD); 6163 6164 sblk = sc->status_block; 6165 6166 aprint_debug_dev(sc->bnx_dev, "----------------------------- " 6167 "Status Block -----------------------------\n"); 6168 6169 BNX_PRINTF(sc, 6170 "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6171 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6172 sblk->status_idx); 6173 6174 BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6175 sblk->status_rx_quick_consumer_index0, 6176 sblk->status_tx_quick_consumer_index0); 6177 6178 BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6179 6180 /* Theses indices are not used for normal L2 drivers. */ 6181 if (sblk->status_rx_quick_consumer_index1 || 6182 sblk->status_tx_quick_consumer_index1) 6183 BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6184 sblk->status_rx_quick_consumer_index1, 6185 sblk->status_tx_quick_consumer_index1); 6186 6187 if (sblk->status_rx_quick_consumer_index2 || 6188 sblk->status_tx_quick_consumer_index2) 6189 BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6190 sblk->status_rx_quick_consumer_index2, 6191 sblk->status_tx_quick_consumer_index2); 6192 6193 if (sblk->status_rx_quick_consumer_index3 || 6194 sblk->status_tx_quick_consumer_index3) 6195 BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6196 sblk->status_rx_quick_consumer_index3, 6197 sblk->status_tx_quick_consumer_index3); 6198 6199 if (sblk->status_rx_quick_consumer_index4 || 6200 sblk->status_rx_quick_consumer_index5) 6201 BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6202 sblk->status_rx_quick_consumer_index4, 6203 sblk->status_rx_quick_consumer_index5); 6204 6205 if (sblk->status_rx_quick_consumer_index6 || 6206 sblk->status_rx_quick_consumer_index7) 6207 BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6208 sblk->status_rx_quick_consumer_index6, 6209 sblk->status_rx_quick_consumer_index7); 6210 6211 if (sblk->status_rx_quick_consumer_index8 || 6212 sblk->status_rx_quick_consumer_index9) 6213 BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6214 sblk->status_rx_quick_consumer_index8, 6215 sblk->status_rx_quick_consumer_index9); 6216 6217 if (sblk->status_rx_quick_consumer_index10 || 6218 sblk->status_rx_quick_consumer_index11) 6219 BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6220 sblk->status_rx_quick_consumer_index10, 6221 sblk->status_rx_quick_consumer_index11); 6222 6223 if (sblk->status_rx_quick_consumer_index12 || 6224 sblk->status_rx_quick_consumer_index13) 6225 BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6226 sblk->status_rx_quick_consumer_index12, 6227 sblk->status_rx_quick_consumer_index13); 6228 6229 if (sblk->status_rx_quick_consumer_index14 || 6230 sblk->status_rx_quick_consumer_index15) 6231 BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6232 sblk->status_rx_quick_consumer_index14, 6233 sblk->status_rx_quick_consumer_index15); 6234 6235 if (sblk->status_completion_producer_index || 6236 sblk->status_cmd_consumer_index) 6237 BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6238 sblk->status_completion_producer_index, 6239 sblk->status_cmd_consumer_index); 6240 6241 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6242 "-----------------------------\n"); 6243 } 6244 6245 /* 6246 * This routine prints the statistics block. 6247 */ 6248 void 6249 bnx_dump_stats_block(struct bnx_softc *sc) 6250 { 6251 struct statistics_block *sblk; 6252 bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, 6253 BUS_DMASYNC_POSTREAD); 6254 6255 sblk = sc->stats_block; 6256 6257 aprint_debug_dev(sc->bnx_dev, "" 6258 "-----------------------------" 6259 " Stats Block " 6260 "-----------------------------\n"); 6261 6262 BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6263 "IfHcInBadOctets = 0x%08X:%08X\n", 6264 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6265 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6266 6267 BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6268 "IfHcOutBadOctets = 0x%08X:%08X\n", 6269 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6270 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6271 6272 BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6273 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6274 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6275 sblk->stat_IfHCInMulticastPkts_hi, 6276 sblk->stat_IfHCInMulticastPkts_lo); 6277 6278 BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6279 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6280 sblk->stat_IfHCInBroadcastPkts_hi, 6281 sblk->stat_IfHCInBroadcastPkts_lo, 6282 sblk->stat_IfHCOutUcastPkts_hi, 6283 sblk->stat_IfHCOutUcastPkts_lo); 6284 6285 BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " 6286 "IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6287 sblk->stat_IfHCOutMulticastPkts_hi, 6288 sblk->stat_IfHCOutMulticastPkts_lo, 6289 sblk->stat_IfHCOutBroadcastPkts_hi, 6290 sblk->stat_IfHCOutBroadcastPkts_lo); 6291 6292 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6293 BNX_PRINTF(sc, "0x%08X : " 6294 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6295 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6296 6297 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6298 BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6299 sblk->stat_Dot3StatsCarrierSenseErrors); 6300 6301 if (sblk->stat_Dot3StatsFCSErrors) 6302 BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6303 sblk->stat_Dot3StatsFCSErrors); 6304 6305 if (sblk->stat_Dot3StatsAlignmentErrors) 6306 BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6307 sblk->stat_Dot3StatsAlignmentErrors); 6308 6309 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6310 BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6311 sblk->stat_Dot3StatsSingleCollisionFrames); 6312 6313 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6314 BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6315 sblk->stat_Dot3StatsMultipleCollisionFrames); 6316 6317 if (sblk->stat_Dot3StatsDeferredTransmissions) 6318 BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6319 sblk->stat_Dot3StatsDeferredTransmissions); 6320 6321 if (sblk->stat_Dot3StatsExcessiveCollisions) 6322 BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6323 sblk->stat_Dot3StatsExcessiveCollisions); 6324 6325 if (sblk->stat_Dot3StatsLateCollisions) 6326 BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6327 sblk->stat_Dot3StatsLateCollisions); 6328 6329 if (sblk->stat_EtherStatsCollisions) 6330 BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6331 sblk->stat_EtherStatsCollisions); 6332 6333 if (sblk->stat_EtherStatsFragments) 6334 BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6335 sblk->stat_EtherStatsFragments); 6336 6337 if (sblk->stat_EtherStatsJabbers) 6338 BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6339 sblk->stat_EtherStatsJabbers); 6340 6341 if (sblk->stat_EtherStatsUndersizePkts) 6342 BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6343 sblk->stat_EtherStatsUndersizePkts); 6344 6345 if (sblk->stat_EtherStatsOverrsizePkts) 6346 BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6347 sblk->stat_EtherStatsOverrsizePkts); 6348 6349 if (sblk->stat_EtherStatsPktsRx64Octets) 6350 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6351 sblk->stat_EtherStatsPktsRx64Octets); 6352 6353 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6354 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6355 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6356 6357 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6358 BNX_PRINTF(sc, "0x%08X : " 6359 "EtherStatsPktsRx128Octetsto255Octets\n", 6360 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6361 6362 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6363 BNX_PRINTF(sc, "0x%08X : " 6364 "EtherStatsPktsRx256Octetsto511Octets\n", 6365 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6366 6367 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6368 BNX_PRINTF(sc, "0x%08X : " 6369 "EtherStatsPktsRx512Octetsto1023Octets\n", 6370 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6371 6372 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6373 BNX_PRINTF(sc, "0x%08X : " 6374 "EtherStatsPktsRx1024Octetsto1522Octets\n", 6375 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6376 6377 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6378 BNX_PRINTF(sc, "0x%08X : " 6379 "EtherStatsPktsRx1523Octetsto9022Octets\n", 6380 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6381 6382 if (sblk->stat_EtherStatsPktsTx64Octets) 6383 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6384 sblk->stat_EtherStatsPktsTx64Octets); 6385 6386 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6387 BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6388 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6389 6390 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6391 BNX_PRINTF(sc, "0x%08X : " 6392 "EtherStatsPktsTx128Octetsto255Octets\n", 6393 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6394 6395 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6396 BNX_PRINTF(sc, "0x%08X : " 6397 "EtherStatsPktsTx256Octetsto511Octets\n", 6398 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6399 6400 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6401 BNX_PRINTF(sc, "0x%08X : " 6402 "EtherStatsPktsTx512Octetsto1023Octets\n", 6403 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6404 6405 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6406 BNX_PRINTF(sc, "0x%08X : " 6407 "EtherStatsPktsTx1024Octetsto1522Octets\n", 6408 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6409 6410 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6411 BNX_PRINTF(sc, "0x%08X : " 6412 "EtherStatsPktsTx1523Octetsto9022Octets\n", 6413 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6414 6415 if (sblk->stat_XonPauseFramesReceived) 6416 BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6417 sblk->stat_XonPauseFramesReceived); 6418 6419 if (sblk->stat_XoffPauseFramesReceived) 6420 BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6421 sblk->stat_XoffPauseFramesReceived); 6422 6423 if (sblk->stat_OutXonSent) 6424 BNX_PRINTF(sc, "0x%08X : OutXonSent\n", 6425 sblk->stat_OutXonSent); 6426 6427 if (sblk->stat_OutXoffSent) 6428 BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", 6429 sblk->stat_OutXoffSent); 6430 6431 if (sblk->stat_FlowControlDone) 6432 BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", 6433 sblk->stat_FlowControlDone); 6434 6435 if (sblk->stat_MacControlFramesReceived) 6436 BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6437 sblk->stat_MacControlFramesReceived); 6438 6439 if (sblk->stat_XoffStateEntered) 6440 BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6441 sblk->stat_XoffStateEntered); 6442 6443 if (sblk->stat_IfInFramesL2FilterDiscards) 6444 BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6445 sblk->stat_IfInFramesL2FilterDiscards); 6446 6447 if (sblk->stat_IfInRuleCheckerDiscards) 6448 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6449 sblk->stat_IfInRuleCheckerDiscards); 6450 6451 if (sblk->stat_IfInFTQDiscards) 6452 BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6453 sblk->stat_IfInFTQDiscards); 6454 6455 if (sblk->stat_IfInMBUFDiscards) 6456 BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6457 sblk->stat_IfInMBUFDiscards); 6458 6459 if (sblk->stat_IfInRuleCheckerP4Hit) 6460 BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6461 sblk->stat_IfInRuleCheckerP4Hit); 6462 6463 if (sblk->stat_CatchupInRuleCheckerDiscards) 6464 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6465 sblk->stat_CatchupInRuleCheckerDiscards); 6466 6467 if (sblk->stat_CatchupInFTQDiscards) 6468 BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6469 sblk->stat_CatchupInFTQDiscards); 6470 6471 if (sblk->stat_CatchupInMBUFDiscards) 6472 BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6473 sblk->stat_CatchupInMBUFDiscards); 6474 6475 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6476 BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6477 sblk->stat_CatchupInRuleCheckerP4Hit); 6478 6479 aprint_debug_dev(sc->bnx_dev, 6480 "-----------------------------" 6481 "--------------" 6482 "-----------------------------\n"); 6483 } 6484 6485 void 6486 bnx_dump_driver_state(struct bnx_softc *sc) 6487 { 6488 aprint_debug_dev(sc->bnx_dev, 6489 "-----------------------------" 6490 " Driver State " 6491 "-----------------------------\n"); 6492 6493 BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " 6494 "address\n", sc); 6495 6496 BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", 6497 sc->status_block); 6498 6499 BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " 6500 "address\n", sc->stats_block); 6501 6502 BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " 6503 "address\n", sc->tx_bd_chain); 6504 6505 #if 0 6506 BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6507 sc->rx_bd_chain); 6508 6509 BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6510 sc->tx_mbuf_ptr); 6511 #endif 6512 6513 BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6514 sc->rx_mbuf_ptr); 6515 6516 BNX_PRINTF(sc, 6517 " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6518 sc->interrupts_generated); 6519 6520 BNX_PRINTF(sc, 6521 " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6522 sc->rx_interrupts); 6523 6524 BNX_PRINTF(sc, 6525 " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6526 sc->tx_interrupts); 6527 6528 BNX_PRINTF(sc, 6529 " 0x%08X - (sc->last_status_idx) status block index\n", 6530 sc->last_status_idx); 6531 6532 BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6533 sc->tx_prod); 6534 6535 BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6536 sc->tx_cons); 6537 6538 BNX_PRINTF(sc, 6539 " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6540 sc->tx_prod_bseq); 6541 BNX_PRINTF(sc, 6542 " 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 6543 sc->tx_mbuf_alloc); 6544 6545 BNX_PRINTF(sc, 6546 " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6547 sc->used_tx_bd); 6548 6549 BNX_PRINTF(sc, 6550 " 0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6551 sc->tx_hi_watermark, sc->max_tx_bd); 6552 6553 6554 BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6555 sc->rx_prod); 6556 6557 BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6558 sc->rx_cons); 6559 6560 BNX_PRINTF(sc, 6561 " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6562 sc->rx_prod_bseq); 6563 6564 BNX_PRINTF(sc, 6565 " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6566 sc->rx_mbuf_alloc); 6567 6568 BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6569 sc->free_rx_bd); 6570 6571 BNX_PRINTF(sc, 6572 "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6573 sc->rx_low_watermark, sc->max_rx_bd); 6574 6575 BNX_PRINTF(sc, 6576 " 0x%08X - (sc->mbuf_alloc_failed) " 6577 "mbuf alloc failures\n", 6578 sc->mbuf_alloc_failed); 6579 6580 BNX_PRINTF(sc, 6581 " 0x%0X - (sc->mbuf_sim_allocated_failed) " 6582 "simulated mbuf alloc failures\n", 6583 sc->mbuf_sim_alloc_failed); 6584 6585 aprint_debug_dev(sc->bnx_dev, "-------------------------------------------" 6586 "-----------------------------\n"); 6587 } 6588 6589 void 6590 bnx_dump_hw_state(struct bnx_softc *sc) 6591 { 6592 uint32_t val1; 6593 int i; 6594 6595 aprint_debug_dev(sc->bnx_dev, 6596 "----------------------------" 6597 " Hardware State " 6598 "----------------------------\n"); 6599 6600 val1 = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV); 6601 BNX_PRINTF(sc, "0x%08X : bootcode version\n", val1); 6602 6603 val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); 6604 BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6605 val1, BNX_MISC_ENABLE_STATUS_BITS); 6606 6607 val1 = REG_RD(sc, BNX_DMA_STATUS); 6608 BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); 6609 6610 val1 = REG_RD(sc, BNX_CTX_STATUS); 6611 BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); 6612 6613 val1 = REG_RD(sc, BNX_EMAC_STATUS); 6614 BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, 6615 BNX_EMAC_STATUS); 6616 6617 val1 = REG_RD(sc, BNX_RPM_STATUS); 6618 BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); 6619 6620 val1 = REG_RD(sc, BNX_TBDR_STATUS); 6621 BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, 6622 BNX_TBDR_STATUS); 6623 6624 val1 = REG_RD(sc, BNX_TDMA_STATUS); 6625 BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, 6626 BNX_TDMA_STATUS); 6627 6628 val1 = REG_RD(sc, BNX_HC_STATUS); 6629 BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); 6630 6631 aprint_debug_dev(sc->bnx_dev, 6632 "----------------------------" 6633 "----------------" 6634 "----------------------------\n"); 6635 6636 aprint_debug_dev(sc->bnx_dev, 6637 "----------------------------" 6638 " Register Dump " 6639 "----------------------------\n"); 6640 6641 for (i = 0x400; i < 0x8000; i += 0x10) 6642 BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6643 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6644 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6645 6646 aprint_debug_dev(sc->bnx_dev, 6647 "----------------------------" 6648 "----------------" 6649 "----------------------------\n"); 6650 } 6651 6652 void 6653 bnx_breakpoint(struct bnx_softc *sc) 6654 { 6655 /* Unreachable code to shut the compiler up about unused functions. */ 6656 if (0) { 6657 bnx_dump_txbd(sc, 0, NULL); 6658 bnx_dump_rxbd(sc, 0, NULL); 6659 bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6660 bnx_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 6661 bnx_dump_l2fhdr(sc, 0, NULL); 6662 bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); 6663 bnx_dump_rx_chain(sc, 0, sc->max_rx_bd); 6664 bnx_dump_status_block(sc); 6665 bnx_dump_stats_block(sc); 6666 bnx_dump_driver_state(sc); 6667 bnx_dump_hw_state(sc); 6668 } 6669 6670 bnx_dump_driver_state(sc); 6671 /* Print the important status block fields. */ 6672 bnx_dump_status_block(sc); 6673 6674 #if 0 6675 /* Call the debugger. */ 6676 breakpoint(); 6677 #endif 6678 6679 return; 6680 } 6681 #endif 6682
Indexes created Thu Sep 25 02:09:54 GMT 2025