if_bnxreg.h revision 1.7
1 /* $NetBSD: if_bnxreg.h,v 1.7 2008/06/24 10:17:45 gmcgarry Exp $ */ 2 /* $OpenBSD: if_bnxreg.h,v 1.17 2006/11/20 21:26:27 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2006 Broadcom Corporation 6 * David Christensen <davidch (at) broadcom.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written consent. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ 33 */ 34 35 #undef BNX_DEBUG 36 37 #ifndef _BNX_H_DEFINED 38 #define _BNX_H_DEFINED 39 40 #ifdef _KERNEL_OPT 41 #include "bpfilter.h" 42 #include "opt_inet.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/socket.h> 53 #include <sys/sysctl.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_inarp.h> 66 #endif 67 68 #include <net/if_vlanvar.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #define ETHER_ALIGN 2 84 85 /****************************************************************************/ 86 /* Debugging macros and definitions. */ 87 /****************************************************************************/ 88 #define BNX_CP_LOAD 0x00000001 89 #define BNX_CP_SEND 0x00000002 90 #define BNX_CP_RECV 0x00000004 91 #define BNX_CP_INTR 0x00000008 92 #define BNX_CP_UNLOAD 0x00000010 93 #define BNX_CP_RESET 0x00000020 94 #define BNX_CP_ALL 0x00FFFFFF 95 96 #define BNX_CP_MASK 0x00FFFFFF 97 98 #define BNX_LEVEL_FATAL 0x00000000 99 #define BNX_LEVEL_WARN 0x01000000 100 #define BNX_LEVEL_INFO 0x02000000 101 #define BNX_LEVEL_VERBOSE 0x03000000 102 #define BNX_LEVEL_EXCESSIVE 0x04000000 103 104 #define BNX_LEVEL_MASK 0xFF000000 105 106 #define BNX_WARN_LOAD (BNX_CP_LOAD | BNX_LEVEL_WARN) 107 #define BNX_INFO_LOAD (BNX_CP_LOAD | BNX_LEVEL_INFO) 108 #define BNX_VERBOSE_LOAD (BNX_CP_LOAD | BNX_LEVEL_VERBOSE) 109 #define BNX_EXCESSIVE_LOAD (BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE) 110 111 #define BNX_WARN_SEND (BNX_CP_SEND | BNX_LEVEL_WARN) 112 #define BNX_INFO_SEND (BNX_CP_SEND | BNX_LEVEL_INFO) 113 #define BNX_VERBOSE_SEND (BNX_CP_SEND | BNX_LEVEL_VERBOSE) 114 #define BNX_EXCESSIVE_SEND (BNX_CP_SEND | BNX_LEVEL_EXCESSIVE) 115 116 #define BNX_WARN_RECV (BNX_CP_RECV | BNX_LEVEL_WARN) 117 #define BNX_INFO_RECV (BNX_CP_RECV | BNX_LEVEL_INFO) 118 #define BNX_VERBOSE_RECV (BNX_CP_RECV | BNX_LEVEL_VERBOSE) 119 #define BNX_EXCESSIVE_RECV (BNX_CP_RECV | BNX_LEVEL_EXCESSIVE) 120 121 #define BNX_WARN_INTR (BNX_CP_INTR | BNX_LEVEL_WARN) 122 #define BNX_INFO_INTR (BNX_CP_INTR | BNX_LEVEL_INFO) 123 #define BNX_VERBOSE_INTR (BNX_CP_INTR | BNX_LEVEL_VERBOSE) 124 #define BNX_EXCESSIVE_INTR (BNX_CP_INTR | BNX_LEVEL_EXCESSIVE) 125 126 #define BNX_WARN_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_WARN) 127 #define BNX_INFO_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_INFO) 128 #define BNX_VERBOSE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE) 129 #define BNX_EXCESSIVE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE) 130 131 #define BNX_WARN_RESET (BNX_CP_RESET | BNX_LEVEL_WARN) 132 #define BNX_INFO_RESET (BNX_CP_RESET | BNX_LEVEL_INFO) 133 #define BNX_VERBOSE_RESET (BNX_CP_RESET | BNX_LEVEL_VERBOSE) 134 #define BNX_EXCESSIVE_RESET (BNX_CP_RESET | BNX_LEVEL_EXCESSIVE) 135 136 #define BNX_FATAL (BNX_CP_ALL | BNX_LEVEL_FATAL) 137 #define BNX_WARN (BNX_CP_ALL | BNX_LEVEL_WARN) 138 #define BNX_INFO (BNX_CP_ALL | BNX_LEVEL_INFO) 139 #define BNX_VERBOSE (BNX_CP_ALL | BNX_LEVEL_VERBOSE) 140 #define BNX_EXCESSIVE (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE) 141 142 #define BNX_CODE_PATH(cp) ((cp & BNX_CP_MASK) & bnx_debug) 143 #define BNX_MSG_LEVEL(lv) ((lv & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK)) 144 #define BNX_LOG_MSG(m) (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m)) 145 146 #ifdef BNX_DEBUG 147 148 /* Print a message based on the logging level and code path. */ 149 #define DBPRINT(sc, level, format, args...) \ 150 if (BNX_LOG_MSG(level)) { \ 151 aprint_debug_dev(sc->bnx_dev, format, ## args); \ 152 } 153 154 /* Runs a particular command based on the logging level and code path. */ 155 #define DBRUN(m, args...) \ 156 if (BNX_LOG_MSG(m)) { \ 157 args; \ 158 } 159 160 /* Runs a particular command based on the logging level. */ 161 #define DBRUNLV(level, args...) \ 162 if (BNX_MSG_LEVEL(level)) { \ 163 args; \ 164 } 165 166 /* Runs a particular command based on the code path. */ 167 #define DBRUNCP(cp, args...) \ 168 if (BNX_CODE_PATH(cp)) { \ 169 args; \ 170 } 171 172 /* Runs a particular command based on a condition. */ 173 #define DBRUNIF(cond, args...) \ 174 if (cond) { \ 175 args; \ 176 } 177 #if 0 178 /* Needed for random() function which is only used in debugging. */ 179 #include <sys/random.h> 180 #endif 181 182 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 183 #define DB_RANDOMFALSE(defects) (random() > defects) 184 #define DB_OR_RANDOMFALSE(defects) || (random() > defects) 185 #define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) 186 187 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 188 #define DB_RANDOMTRUE(defects) (random() < defects) 189 #define DB_OR_RANDOMTRUE(defects) || (random() < defects) 190 #define DB_AND_RANDOMTRUE(defects) && (random() < defects) 191 192 #else 193 194 #define DBPRINT(level, format, ...) 195 #define DBRUN(m, ...) 196 #define DBRUNLV(level, ...) 197 #define DBRUNCP(cp, ...) 198 #define DBRUNIF(cond, ...) 199 #define DB_RANDOMFALSE(defects) 200 #define DB_OR_RANDOMFALSE(percent) 201 #define DB_AND_RANDOMFALSE(percent) 202 #define DB_RANDOMTRUE(defects) 203 #define DB_OR_RANDOMTRUE(percent) 204 #define DB_AND_RANDOMTRUE(percent) 205 206 #endif /* BNX_DEBUG */ 207 208 209 /****************************************************************************/ 210 /* Device identification definitions. */ 211 /****************************************************************************/ 212 #define BRCM_VENDORID 0x14E4 213 #define BRCM_DEVICEID_BCM5706 0x164A 214 #define BRCM_DEVICEID_BCM5706S 0x16AA 215 #define BRCM_DEVICEID_BCM5708 0x164C 216 #define BRCM_DEVICEID_BCM5708S 0x16AC 217 218 #define HP_VENDORID 0x103C 219 220 #define PCI_ANY_ID (u_int16_t) (~0U) 221 222 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 223 224 #define BNX_CHIP_NUM(sc) (((sc)->bnx_chipid) & 0xffff0000) 225 #define BNX_CHIP_NUM_5706 0x57060000 226 #define BNX_CHIP_NUM_5708 0x57080000 227 228 #define BNX_CHIP_REV(sc) (((sc)->bnx_chipid) & 0x0000f000) 229 #define BNX_CHIP_REV_Ax 0x00000000 230 #define BNX_CHIP_REV_Bx 0x00001000 231 #define BNX_CHIP_REV_Cx 0x00002000 232 233 #define BNX_CHIP_METAL(sc) (((sc)->bnx_chipid) & 0x00000ff0) 234 #define BNX_CHIP_BOND(bp) (((sc)->bnx_chipid) & 0x0000000f) 235 236 #define BNX_CHIP_ID(sc) (((sc)->bnx_chipid) & 0xfffffff0) 237 #define BNX_CHIP_ID_5706_A0 0x57060000 238 #define BNX_CHIP_ID_5706_A1 0x57060010 239 #define BNX_CHIP_ID_5706_A2 0x57060020 240 #define BNX_CHIP_ID_5708_A0 0x57080000 241 #define BNX_CHIP_ID_5708_B0 0x57081000 242 #define BNX_CHIP_ID_5708_B1 0x57081010 243 244 #define BNX_CHIP_BOND_ID(sc) (((sc)->bnx_chipid) & 0xf) 245 246 /* A serdes chip will have the first bit of the bond id set. */ 247 #define BNX_CHIP_BOND_ID_SERDES_BIT 0x01 248 249 250 /* shorthand one */ 251 #define BNX_ASICREV(x) ((x) >> 28) 252 #define BNX_ASICREV_BCM5700 0x06 253 254 /* chip revisions */ 255 #define BNX_CHIPREV(x) ((x) >> 24) 256 #define BNX_CHIPREV_5700_AX 0x70 257 #define BNX_CHIPREV_5700_BX 0x71 258 #define BNX_CHIPREV_5700_CX 0x72 259 #define BNX_CHIPREV_5701_AX 0x00 260 261 struct bnx_type { 262 u_int16_t bnx_vid; 263 u_int16_t bnx_did; 264 u_int16_t bnx_svid; 265 u_int16_t bnx_sdid; 266 char *bnx_name; 267 }; 268 269 /****************************************************************************/ 270 /* Byte order conversions. */ 271 /****************************************************************************/ 272 #define betoh32(x) be32toh(x) 273 #define bnx_htobe16(x) htobe16(x) 274 #define bnx_htobe32(x) htobe32(x) 275 #define bnx_htobe64(x) htobe64(x) 276 #define bnx_htole16(x) htole16(x) 277 #define bnx_htole32(x) htole32(x) 278 #define bnx_htole64(x) htole64(x) 279 280 #define bnx_be16toh(x) betoh16(x) 281 #define bnx_be32toh(x) betoh32(x) 282 #define bnx_be64toh(x) betoh64(x) 283 #define bnx_le16toh(x) letoh16(x) 284 #define bnx_le32toh(x) letoh32(x) 285 #define bnx_le64toh(x) letoh64(x) 286 287 288 /****************************************************************************/ 289 /* NVRAM Access */ 290 /****************************************************************************/ 291 292 /* Buffered flash (Atmel: AT45DB011B) specific information */ 293 #define SEEPROM_PAGE_BITS 2 294 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 295 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 296 #define SEEPROM_PAGE_SIZE 4 297 #define SEEPROM_TOTAL_SIZE 65536 298 299 #define BUFFERED_FLASH_PAGE_BITS 9 300 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 301 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 302 #define BUFFERED_FLASH_PAGE_SIZE 264 303 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000 304 305 #define SAIFUN_FLASH_PAGE_BITS 8 306 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 307 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 308 #define SAIFUN_FLASH_PAGE_SIZE 256 309 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 310 311 #define ST_MICRO_FLASH_PAGE_BITS 8 312 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 313 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 314 #define ST_MICRO_FLASH_PAGE_SIZE 256 315 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 316 317 #define NVRAM_TIMEOUT_COUNT 30000 318 #define BNX_FLASHDESC_MAX 64 319 320 #define FLASH_STRAP_MASK (BNX_NVM_CFG1_FLASH_MODE | \ 321 BNX_NVM_CFG1_BUFFER_MODE | \ 322 BNX_NVM_CFG1_PROTECT_MODE | \ 323 BNX_NVM_CFG1_FLASH_SIZE) 324 325 #define FLASH_BACKUP_STRAP_MASK (0xf << 26) 326 327 struct flash_spec { 328 u_int32_t strapping; 329 u_int32_t config1; 330 u_int32_t config2; 331 u_int32_t config3; 332 u_int32_t write1; 333 u_int32_t buffered; 334 u_int32_t page_bits; 335 u_int32_t page_size; 336 u_int32_t addr_mask; 337 u_int32_t total_size; 338 const u_int8_t *name; 339 }; 340 341 342 /****************************************************************************/ 343 /* Shared Memory layout */ 344 /* The BNX bootcode will initialize this data area with port configurtion */ 345 /* information which can be accessed by the driver. */ 346 /****************************************************************************/ 347 348 /* 349 * This value (in milliseconds) determines the frequency of the driver 350 * issuing the PULSE message code. The firmware monitors this periodic 351 * pulse to determine when to switch to an OS-absent mode. 352 */ 353 #define DRV_PULSE_PERIOD_MS 250 354 355 /* 356 * This value (in milliseconds) determines how long the driver should 357 * wait for an acknowledgement from the firmware before timing out. Once 358 * the firmware has timed out, the driver will assume there is no firmware 359 * running and there won't be any firmware-driver synchronization during a 360 * driver reset. 361 */ 362 #define FW_ACK_TIME_OUT_MS 100 363 364 365 #define BNX_DRV_RESET_SIGNATURE 0x00000000 366 #define BNX_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 367 368 #define BNX_DRV_MB 0x00000004 369 #define BNX_DRV_MSG_CODE 0xff000000 370 #define BNX_DRV_MSG_CODE_RESET 0x01000000 371 #define BNX_DRV_MSG_CODE_UNLOAD 0x02000000 372 #define BNX_DRV_MSG_CODE_SHUTDOWN 0x03000000 373 #define BNX_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 374 #define BNX_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 375 #define BNX_DRV_MSG_CODE_PULSE 0x06000000 376 #define BNX_DRV_MSG_CODE_DIAG 0x07000000 377 #define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 378 379 #define BNX_DRV_MSG_DATA 0x00ff0000 380 #define BNX_DRV_MSG_DATA_WAIT0 0x00010000 381 #define BNX_DRV_MSG_DATA_WAIT1 0x00020000 382 #define BNX_DRV_MSG_DATA_WAIT2 0x00030000 383 #define BNX_DRV_MSG_DATA_WAIT3 0x00040000 384 385 #define BNX_DRV_MSG_SEQ 0x0000ffff 386 387 #define BNX_FW_MB 0x00000008 388 #define BNX_FW_MSG_ACK 0x0000ffff 389 #define BNX_FW_MSG_STATUS_MASK 0x00ff0000 390 #define BNX_FW_MSG_STATUS_OK 0x00000000 391 #define BNX_FW_MSG_STATUS_FAILURE 0x00ff0000 392 393 #define BNX_LINK_STATUS 0x0000000c 394 #define BNX_LINK_STATUS_INIT_VALUE 0xffffffff 395 #define BNX_LINK_STATUS_LINK_UP 0x1 396 #define BNX_LINK_STATUS_LINK_DOWN 0x0 397 #define BNX_LINK_STATUS_SPEED_MASK 0x1e 398 #define BNX_LINK_STATUS_AN_INCOMPLETE (0<<1) 399 #define BNX_LINK_STATUS_10HALF (1<<1) 400 #define BNX_LINK_STATUS_10FULL (2<<1) 401 #define BNX_LINK_STATUS_100HALF (3<<1) 402 #define BNX_LINK_STATUS_100BASE_T4 (4<<1) 403 #define BNX_LINK_STATUS_100FULL (5<<1) 404 #define BNX_LINK_STATUS_1000HALF (6<<1) 405 #define BNX_LINK_STATUS_1000FULL (7<<1) 406 #define BNX_LINK_STATUS_2500HALF (8<<1) 407 #define BNX_LINK_STATUS_2500FULL (9<<1) 408 #define BNX_LINK_STATUS_AN_ENABLED (1<<5) 409 #define BNX_LINK_STATUS_AN_COMPLETE (1<<6) 410 #define BNX_LINK_STATUS_PARALLEL_DET (1<<7) 411 #define BNX_LINK_STATUS_RESERVED (1<<8) 412 #define BNX_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 413 #define BNX_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 414 #define BNX_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 415 #define BNX_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 416 #define BNX_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 417 #define BNX_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 418 #define BNX_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 419 #define BNX_LINK_STATUS_TX_FC_ENABLED (1<<16) 420 #define BNX_LINK_STATUS_RX_FC_ENABLED (1<<17) 421 #define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 422 #define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 423 #define BNX_LINK_STATUS_SERDES_LINK (1<<20) 424 #define BNX_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 425 #define BNX_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 426 427 #define BNX_DRV_PULSE_MB 0x00000010 428 #define BNX_DRV_PULSE_SEQ_MASK 0x00007fff 429 430 /* Indicate to the firmware not to go into the 431 * OS absent when it is not getting driver pulse. 432 * This is used for debugging. */ 433 #define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 434 435 #define BNX_DEV_INFO_SIGNATURE 0x00000020 436 #define BNX_DEV_INFO_SIGNATURE_MAGIC 0x44564900 437 #define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 438 #define BNX_DEV_INFO_FEATURE_CFG_VALID 0x01 439 #define BNX_DEV_INFO_SECONDARY_PORT 0x80 440 #define BNX_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 441 442 #define BNX_SHARED_HW_CFG_PART_NUM 0x00000024 443 444 #define BNX_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 445 #define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 446 #define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 447 #define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 448 #define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 449 450 #define BNX_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 451 #define BNX_SHARED_HW_CFG_CONFIG 0x0000003c 452 #define BNX_SHARED_HW_CFG_DESIGN_NIC 0 453 #define BNX_SHARED_HW_CFG_DESIGN_LOM 0x1 454 #define BNX_SHARED_HW_CFG_PHY_COPPER 0 455 #define BNX_SHARED_HW_CFG_PHY_FIBER 0x2 456 #define BNX_SHARED_HW_CFG_PHY_2_5G 0x20 457 #define BNX_SHARED_HW_CFG_PHY_BACKPLANE 0x40 458 #define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 459 #define BNX_SHARED_HW_CFG_LED_MODE_MASK 0x300 460 #define BNX_SHARED_HW_CFG_LED_MODE_MAC 0 461 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 462 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 463 464 #define BNX_SHARED_HW_CFG_CONFIG2 0x00000040 465 #define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 466 467 #define BNX_DEV_INFO_BC_REV 0x0000004c 468 469 #define BNX_PORT_HW_CFG_MAC_UPPER 0x00000050 470 #define BNX_PORT_HW_CFG_UPPERMAC_MASK 0xffff 471 472 #define BNX_PORT_HW_CFG_MAC_LOWER 0x00000054 473 #define BNX_PORT_HW_CFG_CONFIG 0x00000058 474 #define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 475 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 476 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 477 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 478 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 479 480 #define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 481 #define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 482 #define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 483 #define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 484 #define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 485 #define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 486 487 #define BNX_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 488 489 #define BNX_DEV_INFO_FORMAT_REV 0x000000c4 490 #define BNX_DEV_INFO_FORMAT_REV_MASK 0xff000000 491 #define BNX_DEV_INFO_FORMAT_REV_ID ('A' << 24) 492 493 #define BNX_SHARED_FEATURE 0x000000c8 494 #define BNX_SHARED_FEATURE_MASK 0xffffffff 495 496 #define BNX_PORT_FEATURE 0x000000d8 497 #define BNX_PORT2_FEATURE 0x00000014c 498 #define BNX_PORT_FEATURE_WOL_ENABLED 0x01000000 499 #define BNX_PORT_FEATURE_MBA_ENABLED 0x02000000 500 #define BNX_PORT_FEATURE_ASF_ENABLED 0x04000000 501 #define BNX_PORT_FEATURE_IMD_ENABLED 0x08000000 502 #define BNX_PORT_FEATURE_BAR1_SIZE_MASK 0xf 503 #define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 504 #define BNX_PORT_FEATURE_BAR1_SIZE_64K 0x1 505 #define BNX_PORT_FEATURE_BAR1_SIZE_128K 0x2 506 #define BNX_PORT_FEATURE_BAR1_SIZE_256K 0x3 507 #define BNX_PORT_FEATURE_BAR1_SIZE_512K 0x4 508 #define BNX_PORT_FEATURE_BAR1_SIZE_1M 0x5 509 #define BNX_PORT_FEATURE_BAR1_SIZE_2M 0x6 510 #define BNX_PORT_FEATURE_BAR1_SIZE_4M 0x7 511 #define BNX_PORT_FEATURE_BAR1_SIZE_8M 0x8 512 #define BNX_PORT_FEATURE_BAR1_SIZE_16M 0x9 513 #define BNX_PORT_FEATURE_BAR1_SIZE_32M 0xa 514 #define BNX_PORT_FEATURE_BAR1_SIZE_64M 0xb 515 #define BNX_PORT_FEATURE_BAR1_SIZE_128M 0xc 516 #define BNX_PORT_FEATURE_BAR1_SIZE_256M 0xd 517 #define BNX_PORT_FEATURE_BAR1_SIZE_512M 0xe 518 #define BNX_PORT_FEATURE_BAR1_SIZE_1G 0xf 519 520 #define BNX_PORT_FEATURE_WOL 0xdc 521 #define BNX_PORT2_FEATURE_WOL 0x150 522 #define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 523 #define BNX_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 524 #define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 525 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 526 #define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 527 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 528 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 529 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 530 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 531 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 532 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 533 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 534 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 535 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 536 #define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 537 #define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 538 #define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 539 540 #define BNX_PORT_FEATURE_MBA 0xe0 541 #define BNX_PORT2_FEATURE_MBA 0x154 542 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 543 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 544 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 545 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 546 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 547 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 548 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 549 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 550 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 551 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 552 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 553 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 554 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 555 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 556 #define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 557 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 558 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 559 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 560 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 561 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 562 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 563 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 564 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 565 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 566 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 567 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 568 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 569 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 570 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 571 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 572 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 573 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 574 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 575 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 576 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 577 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 578 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 579 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 580 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 581 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 582 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 583 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 584 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 585 586 #define BNX_PORT_FEATURE_IMD 0xe4 587 #define BNX_PORT2_FEATURE_IMD 0x158 588 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 589 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 590 591 #define BNX_PORT_FEATURE_VLAN 0xe8 592 #define BNX_PORT2_FEATURE_VLAN 0x15c 593 #define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 594 #define BNX_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 595 596 #define BNX_BC_STATE_RESET_TYPE 0x000001c0 597 #define BNX_BC_STATE_RESET_TYPE_SIG 0x00005254 598 #define BNX_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 599 #define BNX_BC_STATE_RESET_TYPE_NONE (BNX_BC_STATE_RESET_TYPE_SIG | \ 600 0x00010000) 601 #define BNX_BC_STATE_RESET_TYPE_PCI (BNX_BC_STATE_RESET_TYPE_SIG | \ 602 0x00020000) 603 #define BNX_BC_STATE_RESET_TYPE_VAUX (BNX_BC_STATE_RESET_TYPE_SIG | \ 604 0x00030000) 605 #define BNX_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 606 #define BNX_BC_STATE_RESET_TYPE_DRV_RESET (BNX_BC_STATE_RESET_TYPE_SIG | \ 607 DRV_MSG_CODE_RESET) 608 #define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX_BC_STATE_RESET_TYPE_SIG | \ 609 DRV_MSG_CODE_UNLOAD) 610 #define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX_BC_STATE_RESET_TYPE_SIG | \ 611 DRV_MSG_CODE_SHUTDOWN) 612 #define BNX_BC_STATE_RESET_TYPE_DRV_WOL (BNX_BC_STATE_RESET_TYPE_SIG | \ 613 DRV_MSG_CODE_WOL) 614 #define BNX_BC_STATE_RESET_TYPE_DRV_DIAG (BNX_BC_STATE_RESET_TYPE_SIG | \ 615 DRV_MSG_CODE_DIAG) 616 #define BNX_BC_STATE_RESET_TYPE_VALUE(msg) (BNX_BC_STATE_RESET_TYPE_SIG | \ 617 (msg)) 618 619 #define BNX_BC_STATE 0x000001c4 620 #define BNX_BC_STATE_ERR_MASK 0x0000ff00 621 #define BNX_BC_STATE_SIGN 0x42530000 622 #define BNX_BC_STATE_SIGN_MASK 0xffff0000 623 #define BNX_BC_STATE_BC1_START (BNX_BC_STATE_SIGN | 0x1) 624 #define BNX_BC_STATE_GET_NVM_CFG1 (BNX_BC_STATE_SIGN | 0x2) 625 #define BNX_BC_STATE_PROG_BAR (BNX_BC_STATE_SIGN | 0x3) 626 #define BNX_BC_STATE_INIT_VID (BNX_BC_STATE_SIGN | 0x4) 627 #define BNX_BC_STATE_GET_NVM_CFG2 (BNX_BC_STATE_SIGN | 0x5) 628 #define BNX_BC_STATE_APPLY_WKARND (BNX_BC_STATE_SIGN | 0x6) 629 #define BNX_BC_STATE_LOAD_BC2 (BNX_BC_STATE_SIGN | 0x7) 630 #define BNX_BC_STATE_GOING_BC2 (BNX_BC_STATE_SIGN | 0x8) 631 #define BNX_BC_STATE_GOING_DIAG (BNX_BC_STATE_SIGN | 0x9) 632 #define BNX_BC_STATE_RT_FINAL_INIT (BNX_BC_STATE_SIGN | 0x81) 633 #define BNX_BC_STATE_RT_WKARND (BNX_BC_STATE_SIGN | 0x82) 634 #define BNX_BC_STATE_RT_DRV_PULSE (BNX_BC_STATE_SIGN | 0x83) 635 #define BNX_BC_STATE_RT_FIOEVTS (BNX_BC_STATE_SIGN | 0x84) 636 #define BNX_BC_STATE_RT_DRV_CMD (BNX_BC_STATE_SIGN | 0x85) 637 #define BNX_BC_STATE_RT_LOW_POWER (BNX_BC_STATE_SIGN | 0x86) 638 #define BNX_BC_STATE_RT_SET_WOL (BNX_BC_STATE_SIGN | 0x87) 639 #define BNX_BC_STATE_RT_OTHER_FW (BNX_BC_STATE_SIGN | 0x88) 640 #define BNX_BC_STATE_RT_GOING_D3 (BNX_BC_STATE_SIGN | 0x89) 641 #define BNX_BC_STATE_ERR_BAD_VERSION (BNX_BC_STATE_SIGN | 0x0100) 642 #define BNX_BC_STATE_ERR_BAD_BC2_CRC (BNX_BC_STATE_SIGN | 0x0200) 643 #define BNX_BC_STATE_ERR_BC1_LOOP (BNX_BC_STATE_SIGN | 0x0300) 644 #define BNX_BC_STATE_ERR_UNKNOWN_CMD (BNX_BC_STATE_SIGN | 0x0400) 645 #define BNX_BC_STATE_ERR_DRV_DEAD (BNX_BC_STATE_SIGN | 0x0500) 646 #define BNX_BC_STATE_ERR_NO_RXP (BNX_BC_STATE_SIGN | 0x0600) 647 #define BNX_BC_STATE_ERR_TOO_MANY_RBUF (BNX_BC_STATE_SIGN | 0x0700) 648 649 #define BNX_BC_STATE_DEBUG_CMD 0x1dc 650 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 651 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 652 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 653 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 654 655 #define HOST_VIEW_SHMEM_BASE 0x167c00 656 657 /* 658 * PCI registers defined in the PCI 2.2 spec. 659 */ 660 #define BNX_PCI_BAR0 0x10 661 #define BNX_PCI_PCIX_CMD 0x40 662 663 /****************************************************************************/ 664 /* Convenience definitions. */ 665 /****************************************************************************/ 666 #define BNX_PRINTF(sc, fmt, ...) aprint_error_dev(sc->bnx_dev, fmt, __VA_ARGS__) 667 668 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 669 #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) 670 #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 671 #define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) 672 #define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) 673 #define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) 674 #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 675 #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 676 #define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 677 #define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 678 679 #define BNX_STATS(x) (u_long) stats->stat_ ## x ## _lo 680 681 /* 682 * The following data structures are generated from RTL code. 683 * Do not modify any values below this line. 684 */ 685 686 /****************************************************************************/ 687 /* Do not modify any of the following data structures, they are generated */ 688 /* from RTL code. */ 689 /* */ 690 /* Begin machine generated definitions. */ 691 /****************************************************************************/ 692 693 /* 694 * tx_bd definition 695 */ 696 struct tx_bd { 697 u_int32_t tx_bd_haddr_hi; 698 u_int32_t tx_bd_haddr_lo; 699 u_int32_t tx_bd_mss_nbytes; 700 u_int16_t tx_bd_flags; 701 u_int16_t tx_bd_vlan_tag; 702 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 703 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 704 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 705 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 706 #define TX_BD_FLAGS_COAL_NOW (1<<4) 707 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 708 #define TX_BD_FLAGS_END (1<<6) 709 #define TX_BD_FLAGS_START (1<<7) 710 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 711 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 712 #define TX_BD_FLAGS_SW_SNAP (1<<14) 713 #define TX_BD_FLAGS_SW_LSO (1<<15) 714 715 }; 716 717 718 /* 719 * rx_bd definition 720 */ 721 struct rx_bd { 722 u_int32_t rx_bd_haddr_hi; 723 u_int32_t rx_bd_haddr_lo; 724 u_int32_t rx_bd_len; 725 u_int32_t rx_bd_flags; 726 #define RX_BD_FLAGS_NOPUSH (1<<0) 727 #define RX_BD_FLAGS_DUMMY (1<<1) 728 #define RX_BD_FLAGS_END (1<<2) 729 #define RX_BD_FLAGS_START (1<<3) 730 731 }; 732 733 734 /* 735 * status_block definition 736 */ 737 struct status_block { 738 u_int32_t status_attn_bits; 739 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 740 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 741 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 742 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 743 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 744 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 745 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 746 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 747 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 748 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 749 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 750 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 751 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 752 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 753 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 754 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 755 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 756 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 757 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 758 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 759 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 760 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 761 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 762 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 763 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 764 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 765 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 766 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 767 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 768 769 u_int32_t status_attn_bits_ack; 770 #if BYTE_ORDER == BIG_ENDIAN 771 u_int16_t status_tx_quick_consumer_index0; 772 u_int16_t status_tx_quick_consumer_index1; 773 u_int16_t status_tx_quick_consumer_index2; 774 u_int16_t status_tx_quick_consumer_index3; 775 u_int16_t status_rx_quick_consumer_index0; 776 u_int16_t status_rx_quick_consumer_index1; 777 u_int16_t status_rx_quick_consumer_index2; 778 u_int16_t status_rx_quick_consumer_index3; 779 u_int16_t status_rx_quick_consumer_index4; 780 u_int16_t status_rx_quick_consumer_index5; 781 u_int16_t status_rx_quick_consumer_index6; 782 u_int16_t status_rx_quick_consumer_index7; 783 u_int16_t status_rx_quick_consumer_index8; 784 u_int16_t status_rx_quick_consumer_index9; 785 u_int16_t status_rx_quick_consumer_index10; 786 u_int16_t status_rx_quick_consumer_index11; 787 u_int16_t status_rx_quick_consumer_index12; 788 u_int16_t status_rx_quick_consumer_index13; 789 u_int16_t status_rx_quick_consumer_index14; 790 u_int16_t status_rx_quick_consumer_index15; 791 u_int16_t status_completion_producer_index; 792 u_int16_t status_cmd_consumer_index; 793 u_int16_t status_idx; 794 u_int16_t status_unused; 795 #elif BYTE_ORDER == LITTLE_ENDIAN 796 u_int16_t status_tx_quick_consumer_index1; 797 u_int16_t status_tx_quick_consumer_index0; 798 u_int16_t status_tx_quick_consumer_index3; 799 u_int16_t status_tx_quick_consumer_index2; 800 u_int16_t status_rx_quick_consumer_index1; 801 u_int16_t status_rx_quick_consumer_index0; 802 u_int16_t status_rx_quick_consumer_index3; 803 u_int16_t status_rx_quick_consumer_index2; 804 u_int16_t status_rx_quick_consumer_index5; 805 u_int16_t status_rx_quick_consumer_index4; 806 u_int16_t status_rx_quick_consumer_index7; 807 u_int16_t status_rx_quick_consumer_index6; 808 u_int16_t status_rx_quick_consumer_index9; 809 u_int16_t status_rx_quick_consumer_index8; 810 u_int16_t status_rx_quick_consumer_index11; 811 u_int16_t status_rx_quick_consumer_index10; 812 u_int16_t status_rx_quick_consumer_index13; 813 u_int16_t status_rx_quick_consumer_index12; 814 u_int16_t status_rx_quick_consumer_index15; 815 u_int16_t status_rx_quick_consumer_index14; 816 u_int16_t status_cmd_consumer_index; 817 u_int16_t status_completion_producer_index; 818 u_int16_t status_unused; 819 u_int16_t status_idx; 820 #endif 821 }; 822 823 824 /* 825 * statistics_block definition 826 */ 827 struct statistics_block { 828 u_int32_t stat_IfHCInOctets_hi; 829 u_int32_t stat_IfHCInOctets_lo; 830 u_int32_t stat_IfHCInBadOctets_hi; 831 u_int32_t stat_IfHCInBadOctets_lo; 832 u_int32_t stat_IfHCOutOctets_hi; 833 u_int32_t stat_IfHCOutOctets_lo; 834 u_int32_t stat_IfHCOutBadOctets_hi; 835 u_int32_t stat_IfHCOutBadOctets_lo; 836 u_int32_t stat_IfHCInUcastPkts_hi; 837 u_int32_t stat_IfHCInUcastPkts_lo; 838 u_int32_t stat_IfHCInMulticastPkts_hi; 839 u_int32_t stat_IfHCInMulticastPkts_lo; 840 u_int32_t stat_IfHCInBroadcastPkts_hi; 841 u_int32_t stat_IfHCInBroadcastPkts_lo; 842 u_int32_t stat_IfHCOutUcastPkts_hi; 843 u_int32_t stat_IfHCOutUcastPkts_lo; 844 u_int32_t stat_IfHCOutMulticastPkts_hi; 845 u_int32_t stat_IfHCOutMulticastPkts_lo; 846 u_int32_t stat_IfHCOutBroadcastPkts_hi; 847 u_int32_t stat_IfHCOutBroadcastPkts_lo; 848 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 849 u_int32_t stat_Dot3StatsCarrierSenseErrors; 850 u_int32_t stat_Dot3StatsFCSErrors; 851 u_int32_t stat_Dot3StatsAlignmentErrors; 852 u_int32_t stat_Dot3StatsSingleCollisionFrames; 853 u_int32_t stat_Dot3StatsMultipleCollisionFrames; 854 u_int32_t stat_Dot3StatsDeferredTransmissions; 855 u_int32_t stat_Dot3StatsExcessiveCollisions; 856 u_int32_t stat_Dot3StatsLateCollisions; 857 u_int32_t stat_EtherStatsCollisions; 858 u_int32_t stat_EtherStatsFragments; 859 u_int32_t stat_EtherStatsJabbers; 860 u_int32_t stat_EtherStatsUndersizePkts; 861 u_int32_t stat_EtherStatsOverrsizePkts; 862 u_int32_t stat_EtherStatsPktsRx64Octets; 863 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; 864 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; 865 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; 866 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 867 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 868 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 869 u_int32_t stat_EtherStatsPktsTx64Octets; 870 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; 871 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; 872 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; 873 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 874 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 875 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 876 u_int32_t stat_XonPauseFramesReceived; 877 u_int32_t stat_XoffPauseFramesReceived; 878 u_int32_t stat_OutXonSent; 879 u_int32_t stat_OutXoffSent; 880 u_int32_t stat_FlowControlDone; 881 u_int32_t stat_MacControlFramesReceived; 882 u_int32_t stat_XoffStateEntered; 883 u_int32_t stat_IfInFramesL2FilterDiscards; 884 u_int32_t stat_IfInRuleCheckerDiscards; 885 u_int32_t stat_IfInFTQDiscards; 886 u_int32_t stat_IfInMBUFDiscards; 887 u_int32_t stat_IfInRuleCheckerP4Hit; 888 u_int32_t stat_CatchupInRuleCheckerDiscards; 889 u_int32_t stat_CatchupInFTQDiscards; 890 u_int32_t stat_CatchupInMBUFDiscards; 891 u_int32_t stat_CatchupInRuleCheckerP4Hit; 892 u_int32_t stat_GenStat00; 893 u_int32_t stat_GenStat01; 894 u_int32_t stat_GenStat02; 895 u_int32_t stat_GenStat03; 896 u_int32_t stat_GenStat04; 897 u_int32_t stat_GenStat05; 898 u_int32_t stat_GenStat06; 899 u_int32_t stat_GenStat07; 900 u_int32_t stat_GenStat08; 901 u_int32_t stat_GenStat09; 902 u_int32_t stat_GenStat10; 903 u_int32_t stat_GenStat11; 904 u_int32_t stat_GenStat12; 905 u_int32_t stat_GenStat13; 906 u_int32_t stat_GenStat14; 907 u_int32_t stat_GenStat15; 908 }; 909 910 911 /* 912 * l2_fhdr definition 913 */ 914 struct l2_fhdr { 915 u_int32_t l2_fhdr_status; 916 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 917 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 918 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 919 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 920 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 921 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 922 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 923 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 924 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 925 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 926 927 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 928 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 929 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 930 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 931 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 932 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 933 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 934 935 u_int32_t l2_fhdr_hash; 936 #if BYTE_ORDER == BIG_ENDIAN 937 u_int16_t l2_fhdr_pkt_len; 938 u_int16_t l2_fhdr_vlan_tag; 939 u_int16_t l2_fhdr_ip_xsum; 940 u_int16_t l2_fhdr_tcp_udp_xsum; 941 #elif BYTE_ORDER == LITTLE_ENDIAN 942 u_int16_t l2_fhdr_vlan_tag; 943 u_int16_t l2_fhdr_pkt_len; 944 u_int16_t l2_fhdr_tcp_udp_xsum; 945 u_int16_t l2_fhdr_ip_xsum; 946 #endif 947 }; 948 949 950 /* 951 * l2_context definition 952 */ 953 #define BNX_L2CTX_TYPE 0x00000000 954 #define BNX_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 955 #define BNX_L2CTX_TYPE_TYPE (0xf<<28) 956 #define BNX_L2CTX_TYPE_TYPE_EMPTY (0<<28) 957 #define BNX_L2CTX_TYPE_TYPE_L2 (1<<28) 958 959 #define BNX_L2CTX_TX_HOST_BIDX 0x00000088 960 #define BNX_L2CTX_EST_NBD 0x00000088 961 #define BNX_L2CTX_CMD_TYPE 0x00000088 962 #define BNX_L2CTX_CMD_TYPE_TYPE (0xf<<24) 963 #define BNX_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) 964 #define BNX_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) 965 966 #define BNX_L2CTX_TX_HOST_BSEQ 0x00000090 967 #define BNX_L2CTX_TSCH_BSEQ 0x00000094 968 #define BNX_L2CTX_TBDR_BSEQ 0x00000098 969 #define BNX_L2CTX_TBDR_BOFF 0x0000009c 970 #define BNX_L2CTX_TBDR_BIDX 0x0000009c 971 #define BNX_L2CTX_TBDR_BHADDR_HI 0x000000a0 972 #define BNX_L2CTX_TBDR_BHADDR_LO 0x000000a4 973 #define BNX_L2CTX_TXP_BOFF 0x000000a8 974 #define BNX_L2CTX_TXP_BIDX 0x000000a8 975 #define BNX_L2CTX_TXP_BSEQ 0x000000ac 976 977 978 /* 979 * l2_bd_chain_context definition 980 */ 981 #define BNX_L2CTX_BD_PRE_READ 0x00000000 982 #define BNX_L2CTX_CTX_SIZE 0x00000000 983 #define BNX_L2CTX_CTX_TYPE 0x00000000 984 #define BNX_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 985 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 986 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 987 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 988 989 #define BNX_L2CTX_HOST_BDIDX 0x00000004 990 #define BNX_L2CTX_HOST_BSEQ 0x00000008 991 #define BNX_L2CTX_NX_BSEQ 0x0000000c 992 #define BNX_L2CTX_NX_BDHADDR_HI 0x00000010 993 #define BNX_L2CTX_NX_BDHADDR_LO 0x00000014 994 #define BNX_L2CTX_NX_BDIDX 0x00000018 995 996 997 /* 998 * pci_config_l definition 999 * offset: 0000 1000 */ 1001 #define BNX_PCICFG_MISC_CONFIG 0x00000068 1002 #define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1003 #define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1004 #define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1005 #define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1006 #define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1007 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1008 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1009 #define BNX_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1010 #define BNX_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1011 #define BNX_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1012 #define BNX_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1013 1014 #define BNX_PCICFG_MISC_STATUS 0x0000006c 1015 #define BNX_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1016 #define BNX_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1017 #define BNX_PCICFG_MISC_STATUS_M66EN (1L<<2) 1018 #define BNX_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1019 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1020 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1021 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1022 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1023 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1024 1025 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1026 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1027 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1028 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1029 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1030 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1031 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1032 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1033 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1034 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1035 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1036 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1037 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1038 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1039 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1040 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1041 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1042 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1043 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1044 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1045 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1046 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1047 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1048 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1049 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1050 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1051 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1052 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1053 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1054 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1055 1056 #define BNX_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1057 #define BNX_PCICFG_REG_WINDOW 0x00000080 1058 #define BNX_PCICFG_INT_ACK_CMD 0x00000084 1059 #define BNX_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1060 #define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1061 #define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1062 #define BNX_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1063 1064 #define BNX_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1065 #define BNX_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1066 #define BNX_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1067 #define BNX_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1068 1069 1070 /* 1071 * pci_reg definition 1072 * offset: 0x400 1073 */ 1074 #define BNX_PCI_GRC_WINDOW_ADDR 0x00000400 1075 #define BNX_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1076 1077 #define BNX_PCI_CONFIG_1 0x00000404 1078 #define BNX_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1079 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1080 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1081 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1082 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1083 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1084 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1085 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1086 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1087 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1088 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1089 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1090 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1091 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1092 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1093 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1094 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1095 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1096 1097 #define BNX_PCI_CONFIG_2 0x00000408 1098 #define BNX_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1099 #define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1100 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1101 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1102 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1103 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1104 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1105 #define BNX_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1106 #define BNX_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1107 #define BNX_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1108 #define BNX_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1109 #define BNX_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1110 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1111 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1112 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1113 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1114 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1115 #define BNX_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1116 #define BNX_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1117 #define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1118 #define BNX_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1119 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1120 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1121 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1122 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1123 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1124 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1125 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1126 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1127 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1128 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1129 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1130 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1131 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1132 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1133 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1134 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1135 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1136 #define BNX_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1137 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1138 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1139 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1140 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1141 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1142 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1143 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1144 #define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1145 1146 #define BNX_PCI_CONFIG_3 0x0000040c 1147 #define BNX_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1148 #define BNX_PCI_CONFIG_3_FORCE_PME (1L<<24) 1149 #define BNX_PCI_CONFIG_3_PME_STATUS (1L<<25) 1150 #define BNX_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1151 #define BNX_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1152 #define BNX_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1153 #define BNX_PCI_CONFIG_3_PCI_POWER (1L<<31) 1154 1155 #define BNX_PCI_PM_DATA_A 0x00000410 1156 #define BNX_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1157 #define BNX_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1158 #define BNX_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1159 #define BNX_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1160 1161 #define BNX_PCI_PM_DATA_B 0x00000414 1162 #define BNX_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1163 #define BNX_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1164 #define BNX_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1165 #define BNX_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1166 1167 #define BNX_PCI_SWAP_DIAG0 0x00000418 1168 #define BNX_PCI_SWAP_DIAG1 0x0000041c 1169 #define BNX_PCI_EXP_ROM_ADDR 0x00000420 1170 #define BNX_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1171 #define BNX_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1172 1173 #define BNX_PCI_EXP_ROM_DATA 0x00000424 1174 #define BNX_PCI_VPD_INTF 0x00000428 1175 #define BNX_PCI_VPD_INTF_INTF_REQ (1L<<0) 1176 1177 #define BNX_PCI_VPD_ADDR_FLAG 0x0000042c 1178 #define BNX_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1179 #define BNX_PCI_VPD_ADDR_FLAG_WR (1<<15) 1180 1181 #define BNX_PCI_VPD_DATA 0x00000430 1182 #define BNX_PCI_ID_VAL1 0x00000434 1183 #define BNX_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1184 #define BNX_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1185 1186 #define BNX_PCI_ID_VAL2 0x00000438 1187 #define BNX_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1188 #define BNX_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1189 1190 #define BNX_PCI_ID_VAL3 0x0000043c 1191 #define BNX_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1192 #define BNX_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1193 1194 #define BNX_PCI_ID_VAL4 0x00000440 1195 #define BNX_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1196 #define BNX_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1197 #define BNX_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1198 #define BNX_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1199 #define BNX_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1200 #define BNX_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1201 #define BNX_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1202 #define BNX_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1203 #define BNX_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1204 #define BNX_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1205 #define BNX_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1206 #define BNX_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1207 #define BNX_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1208 #define BNX_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1209 #define BNX_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1210 #define BNX_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1211 #define BNX_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1212 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1213 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1214 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1215 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1216 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1217 #define BNX_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1218 #define BNX_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1219 #define BNX_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1220 #define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1221 #define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1222 #define BNX_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1223 #define BNX_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1224 #define BNX_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1225 1226 #define BNX_PCI_ID_VAL5 0x00000444 1227 #define BNX_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1228 #define BNX_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1229 #define BNX_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1230 #define BNX_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1231 #define BNX_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1232 #define BNX_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1233 1234 #define BNX_PCI_PCIX_EXTENDED_STATUS 0x00000448 1235 #define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1236 #define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1237 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1238 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1239 1240 #define BNX_PCI_ID_VAL6 0x0000044c 1241 #define BNX_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1242 #define BNX_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1243 #define BNX_PCI_ID_VAL6_BIST (0xffL<<16) 1244 1245 #define BNX_PCI_MSI_DATA 0x00000450 1246 #define BNX_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1247 1248 #define BNX_PCI_MSI_ADDR_H 0x00000454 1249 #define BNX_PCI_MSI_ADDR_L 0x00000458 1250 1251 1252 /* 1253 * misc_reg definition 1254 * offset: 0x800 1255 */ 1256 #define BNX_MISC_COMMAND 0x00000800 1257 #define BNX_MISC_COMMAND_ENABLE_ALL (1L<<0) 1258 #define BNX_MISC_COMMAND_DISABLE_ALL (1L<<1) 1259 #define BNX_MISC_COMMAND_CORE_RESET (1L<<4) 1260 #define BNX_MISC_COMMAND_HARD_RESET (1L<<5) 1261 #define BNX_MISC_COMMAND_PAR_ERROR (1L<<8) 1262 #define BNX_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1263 1264 #define BNX_MISC_CFG 0x00000804 1265 #define BNX_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 1266 #define BNX_MISC_CFG_NVM_WR_EN (0x3L<<1) 1267 #define BNX_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1268 #define BNX_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1269 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1270 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1271 #define BNX_MISC_CFG_BIST_EN (1L<<3) 1272 #define BNX_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1273 #define BNX_MISC_CFG_BYPASS_BSCAN (1L<<5) 1274 #define BNX_MISC_CFG_BYPASS_EJTAG (1L<<6) 1275 #define BNX_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1276 #define BNX_MISC_CFG_LEDMODE (0x3L<<8) 1277 #define BNX_MISC_CFG_LEDMODE_MAC (0L<<8) 1278 #define BNX_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 1279 #define BNX_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 1280 1281 #define BNX_MISC_ID 0x00000808 1282 #define BNX_MISC_ID_BOND_ID (0xfL<<0) 1283 #define BNX_MISC_ID_CHIP_METAL (0xffL<<4) 1284 #define BNX_MISC_ID_CHIP_REV (0xfL<<12) 1285 #define BNX_MISC_ID_CHIP_NUM (0xffffL<<16) 1286 1287 #define BNX_MISC_ENABLE_STATUS_BITS 0x0000080c 1288 #define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1289 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1290 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1291 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1292 #define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1293 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1294 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1295 #define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1296 #define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1297 #define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1298 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1299 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1300 #define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1301 #define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1302 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1303 #define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1304 #define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1305 #define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1306 #define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1307 #define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1308 #define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1309 #define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1310 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1311 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1312 #define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1313 #define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1314 #define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1315 #define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1316 1317 #define BNX_MISC_ENABLE_SET_BITS 0x00000810 1318 #define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1319 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1320 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1321 #define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1322 #define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1323 #define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1324 #define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1325 #define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1326 #define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1327 #define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1328 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1329 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1330 #define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1331 #define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1332 #define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1333 #define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1334 #define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1335 #define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1336 #define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1337 #define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1338 #define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1339 #define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1340 #define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1341 #define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1342 #define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1343 #define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1344 #define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1345 #define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1346 1347 #define BNX_MISC_ENABLE_CLR_BITS 0x00000814 1348 #define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1349 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1350 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1351 #define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1352 #define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1353 #define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1354 #define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1355 #define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1356 #define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1357 #define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1358 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1359 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1360 #define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1361 #define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1362 #define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1363 #define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1364 #define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1365 #define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1366 #define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1367 #define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1368 #define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1369 #define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1370 #define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1371 #define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1372 #define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1373 #define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1374 #define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1375 #define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1376 1377 #define BNX_MISC_CLOCK_CONTROL_BITS 0x00000818 1378 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1379 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1380 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1381 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1382 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1383 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1384 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1385 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1386 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1387 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1388 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1389 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1390 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1391 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1392 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1393 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1394 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1395 #define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1396 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1397 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1398 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1399 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1400 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1401 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1402 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1403 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1404 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1405 #define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1406 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1407 1408 #define BNX_MISC_GPIO 0x0000081c 1409 #define BNX_MISC_GPIO_VALUE (0xffL<<0) 1410 #define BNX_MISC_GPIO_SET (0xffL<<8) 1411 #define BNX_MISC_GPIO_CLR (0xffL<<16) 1412 #define BNX_MISC_GPIO_FLOAT (0xffL<<24) 1413 1414 #define BNX_MISC_GPIO_INT 0x00000820 1415 #define BNX_MISC_GPIO_INT_INT_STATE (0xfL<<0) 1416 #define BNX_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 1417 #define BNX_MISC_GPIO_INT_OLD_SET (0xfL<<16) 1418 #define BNX_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 1419 1420 #define BNX_MISC_CONFIG_LFSR 0x00000824 1421 #define BNX_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1422 1423 #define BNX_MISC_LFSR_MASK_BITS 0x00000828 1424 #define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1425 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1426 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1427 #define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1428 #define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1429 #define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1430 #define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1431 #define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1432 #define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1433 #define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1434 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1435 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1436 #define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1437 #define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1438 #define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1439 #define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1440 #define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1441 #define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1442 #define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1443 #define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1444 #define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1445 #define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1446 #define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1447 #define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1448 #define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1449 #define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1450 #define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1451 #define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1452 1453 #define BNX_MISC_ARB_REQ0 0x0000082c 1454 #define BNX_MISC_ARB_REQ1 0x00000830 1455 #define BNX_MISC_ARB_REQ2 0x00000834 1456 #define BNX_MISC_ARB_REQ3 0x00000838 1457 #define BNX_MISC_ARB_REQ4 0x0000083c 1458 #define BNX_MISC_ARB_FREE0 0x00000840 1459 #define BNX_MISC_ARB_FREE1 0x00000844 1460 #define BNX_MISC_ARB_FREE2 0x00000848 1461 #define BNX_MISC_ARB_FREE3 0x0000084c 1462 #define BNX_MISC_ARB_FREE4 0x00000850 1463 #define BNX_MISC_ARB_REQ_STATUS0 0x00000854 1464 #define BNX_MISC_ARB_REQ_STATUS1 0x00000858 1465 #define BNX_MISC_ARB_REQ_STATUS2 0x0000085c 1466 #define BNX_MISC_ARB_REQ_STATUS3 0x00000860 1467 #define BNX_MISC_ARB_REQ_STATUS4 0x00000864 1468 #define BNX_MISC_ARB_GNT0 0x00000868 1469 #define BNX_MISC_ARB_GNT0_0 (0x7L<<0) 1470 #define BNX_MISC_ARB_GNT0_1 (0x7L<<4) 1471 #define BNX_MISC_ARB_GNT0_2 (0x7L<<8) 1472 #define BNX_MISC_ARB_GNT0_3 (0x7L<<12) 1473 #define BNX_MISC_ARB_GNT0_4 (0x7L<<16) 1474 #define BNX_MISC_ARB_GNT0_5 (0x7L<<20) 1475 #define BNX_MISC_ARB_GNT0_6 (0x7L<<24) 1476 #define BNX_MISC_ARB_GNT0_7 (0x7L<<28) 1477 1478 #define BNX_MISC_ARB_GNT1 0x0000086c 1479 #define BNX_MISC_ARB_GNT1_8 (0x7L<<0) 1480 #define BNX_MISC_ARB_GNT1_9 (0x7L<<4) 1481 #define BNX_MISC_ARB_GNT1_10 (0x7L<<8) 1482 #define BNX_MISC_ARB_GNT1_11 (0x7L<<12) 1483 #define BNX_MISC_ARB_GNT1_12 (0x7L<<16) 1484 #define BNX_MISC_ARB_GNT1_13 (0x7L<<20) 1485 #define BNX_MISC_ARB_GNT1_14 (0x7L<<24) 1486 #define BNX_MISC_ARB_GNT1_15 (0x7L<<28) 1487 1488 #define BNX_MISC_ARB_GNT2 0x00000870 1489 #define BNX_MISC_ARB_GNT2_16 (0x7L<<0) 1490 #define BNX_MISC_ARB_GNT2_17 (0x7L<<4) 1491 #define BNX_MISC_ARB_GNT2_18 (0x7L<<8) 1492 #define BNX_MISC_ARB_GNT2_19 (0x7L<<12) 1493 #define BNX_MISC_ARB_GNT2_20 (0x7L<<16) 1494 #define BNX_MISC_ARB_GNT2_21 (0x7L<<20) 1495 #define BNX_MISC_ARB_GNT2_22 (0x7L<<24) 1496 #define BNX_MISC_ARB_GNT2_23 (0x7L<<28) 1497 1498 #define BNX_MISC_ARB_GNT3 0x00000874 1499 #define BNX_MISC_ARB_GNT3_24 (0x7L<<0) 1500 #define BNX_MISC_ARB_GNT3_25 (0x7L<<4) 1501 #define BNX_MISC_ARB_GNT3_26 (0x7L<<8) 1502 #define BNX_MISC_ARB_GNT3_27 (0x7L<<12) 1503 #define BNX_MISC_ARB_GNT3_28 (0x7L<<16) 1504 #define BNX_MISC_ARB_GNT3_29 (0x7L<<20) 1505 #define BNX_MISC_ARB_GNT3_30 (0x7L<<24) 1506 #define BNX_MISC_ARB_GNT3_31 (0x7L<<28) 1507 1508 #define BNX_MISC_PRBS_CONTROL 0x00000878 1509 #define BNX_MISC_PRBS_CONTROL_EN (1L<<0) 1510 #define BNX_MISC_PRBS_CONTROL_RSTB (1L<<1) 1511 #define BNX_MISC_PRBS_CONTROL_INV (1L<<2) 1512 #define BNX_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1513 #define BNX_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1514 #define BNX_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) 1515 #define BNX_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) 1516 #define BNX_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) 1517 #define BNX_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) 1518 1519 #define BNX_MISC_PRBS_STATUS 0x0000087c 1520 #define BNX_MISC_PRBS_STATUS_LOCK (1L<<0) 1521 #define BNX_MISC_PRBS_STATUS_STKY (1L<<1) 1522 #define BNX_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) 1523 #define BNX_MISC_PRBS_STATUS_STATE (0xfL<<16) 1524 1525 #define BNX_MISC_SM_ASF_CONTROL 0x00000880 1526 #define BNX_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1527 #define BNX_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1528 #define BNX_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1529 #define BNX_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1530 #define BNX_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1531 #define BNX_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1532 #define BNX_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1533 #define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1534 #define BNX_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1535 #define BNX_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1536 #define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1537 #define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1538 #define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1539 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1540 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1541 #define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1542 #define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1543 1544 #define BNX_MISC_SMB_IN 0x00000884 1545 #define BNX_MISC_SMB_IN_DAT_IN (0xffL<<0) 1546 #define BNX_MISC_SMB_IN_RDY (1L<<8) 1547 #define BNX_MISC_SMB_IN_DONE (1L<<9) 1548 #define BNX_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1549 #define BNX_MISC_SMB_IN_STATUS (0x7L<<11) 1550 #define BNX_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1551 #define BNX_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1552 #define BNX_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1553 #define BNX_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1554 #define BNX_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1555 1556 #define BNX_MISC_SMB_OUT 0x00000888 1557 #define BNX_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1558 #define BNX_MISC_SMB_OUT_RDY (1L<<8) 1559 #define BNX_MISC_SMB_OUT_START (1L<<9) 1560 #define BNX_MISC_SMB_OUT_LAST (1L<<10) 1561 #define BNX_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1562 #define BNX_MISC_SMB_OUT_ENB_PEC (1L<<12) 1563 #define BNX_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1564 #define BNX_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1565 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1566 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1567 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1568 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1569 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1570 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1571 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1572 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1573 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1574 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) 1575 #define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1576 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1577 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1578 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1579 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1580 1581 #define BNX_MISC_SMB_WATCHDOG 0x0000088c 1582 #define BNX_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1583 1584 #define BNX_MISC_SMB_HEARTBEAT 0x00000890 1585 #define BNX_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1586 1587 #define BNX_MISC_SMB_POLL_ASF 0x00000894 1588 #define BNX_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1589 1590 #define BNX_MISC_SMB_POLL_LEGACY 0x00000898 1591 #define BNX_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1592 1593 #define BNX_MISC_SMB_RETRAN 0x0000089c 1594 #define BNX_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1595 1596 #define BNX_MISC_SMB_TIMESTAMP 0x000008a0 1597 #define BNX_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1598 1599 #define BNX_MISC_PERR_ENA0 0x000008a4 1600 #define BNX_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1601 #define BNX_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1602 #define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1603 #define BNX_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1604 #define BNX_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1605 #define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1606 #define BNX_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1607 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1608 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1609 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1610 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1611 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1612 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1613 #define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1614 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1615 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1616 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1617 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1618 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1619 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1620 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1621 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1622 #define BNX_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1623 #define BNX_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1624 #define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1625 #define BNX_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1626 #define BNX_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1627 #define BNX_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1628 #define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1629 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1630 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1631 #define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1632 1633 #define BNX_MISC_PERR_ENA1 0x000008a8 1634 #define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1635 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1636 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1637 #define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1638 #define BNX_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1639 #define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1640 #define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1641 #define BNX_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1642 #define BNX_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1643 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1644 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1645 #define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1646 #define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1647 #define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1648 #define BNX_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1649 #define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1650 #define BNX_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1651 #define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1652 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1653 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1654 #define BNX_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1655 #define BNX_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1656 #define BNX_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1657 #define BNX_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1658 #define BNX_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1659 #define BNX_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1660 #define BNX_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1661 #define BNX_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1662 #define BNX_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1663 #define BNX_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1664 #define BNX_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1665 #define BNX_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1666 1667 #define BNX_MISC_PERR_ENA2 0x000008ac 1668 #define BNX_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1669 #define BNX_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1670 #define BNX_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1671 #define BNX_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1672 #define BNX_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1673 #define BNX_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1674 #define BNX_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1675 #define BNX_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1676 #define BNX_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1677 1678 #define BNX_MISC_DEBUG_VECTOR_SEL 0x000008b0 1679 #define BNX_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1680 #define BNX_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1681 1682 #define BNX_MISC_VREG_CONTROL 0x000008b4 1683 #define BNX_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1684 #define BNX_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1685 1686 #define BNX_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1687 #define BNX_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1688 1689 #define BNX_MISC_UNUSED0 0x000008bc 1690 1691 1692 /* 1693 * nvm_reg definition 1694 * offset: 0x6400 1695 */ 1696 #define BNX_NVM_COMMAND 0x00006400 1697 #define BNX_NVM_COMMAND_RST (1L<<0) 1698 #define BNX_NVM_COMMAND_DONE (1L<<3) 1699 #define BNX_NVM_COMMAND_DOIT (1L<<4) 1700 #define BNX_NVM_COMMAND_WR (1L<<5) 1701 #define BNX_NVM_COMMAND_ERASE (1L<<6) 1702 #define BNX_NVM_COMMAND_FIRST (1L<<7) 1703 #define BNX_NVM_COMMAND_LAST (1L<<8) 1704 #define BNX_NVM_COMMAND_WREN (1L<<16) 1705 #define BNX_NVM_COMMAND_WRDI (1L<<17) 1706 #define BNX_NVM_COMMAND_EWSR (1L<<18) 1707 #define BNX_NVM_COMMAND_WRSR (1L<<19) 1708 1709 #define BNX_NVM_STATUS 0x00006404 1710 #define BNX_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1711 #define BNX_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1712 #define BNX_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1713 1714 #define BNX_NVM_WRITE 0x00006408 1715 #define BNX_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1716 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 1717 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 1718 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 1719 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 1720 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1721 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1722 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1723 1724 #define BNX_NVM_ADDR 0x0000640c 1725 #define BNX_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1726 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 1727 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 1728 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 1729 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 1730 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1731 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1732 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1733 1734 #define BNX_NVM_READ 0x00006410 1735 #define BNX_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1736 #define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 1737 #define BNX_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 1738 #define BNX_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 1739 #define BNX_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 1740 #define BNX_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1741 #define BNX_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1742 #define BNX_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1743 1744 #define BNX_NVM_CFG1 0x00006414 1745 #define BNX_NVM_CFG1_FLASH_MODE (1L<<0) 1746 #define BNX_NVM_CFG1_BUFFER_MODE (1L<<1) 1747 #define BNX_NVM_CFG1_PASS_MODE (1L<<2) 1748 #define BNX_NVM_CFG1_BITBANG_MODE (1L<<3) 1749 #define BNX_NVM_CFG1_STATUS_BIT (0x7L<<4) 1750 #define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 1751 #define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1752 #define BNX_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1753 #define BNX_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1754 #define BNX_NVM_CFG1_PROTECT_MODE (1L<<24) 1755 #define BNX_NVM_CFG1_FLASH_SIZE (1L<<25) 1756 #define BNX_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1757 1758 #define BNX_NVM_CFG2 0x00006418 1759 #define BNX_NVM_CFG2_ERASE_CMD (0xffL<<0) 1760 #define BNX_NVM_CFG2_DUMMY (0xffL<<8) 1761 #define BNX_NVM_CFG2_STATUS_CMD (0xffL<<16) 1762 1763 #define BNX_NVM_CFG3 0x0000641c 1764 #define BNX_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1765 #define BNX_NVM_CFG3_WRITE_CMD (0xffL<<8) 1766 #define BNX_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 1767 #define BNX_NVM_CFG3_READ_CMD (0xffL<<24) 1768 1769 #define BNX_NVM_SW_ARB 0x00006420 1770 #define BNX_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 1771 #define BNX_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1772 #define BNX_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 1773 #define BNX_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 1774 #define BNX_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 1775 #define BNX_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1776 #define BNX_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 1777 #define BNX_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 1778 #define BNX_NVM_SW_ARB_ARB_ARB0 (1L<<8) 1779 #define BNX_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1780 #define BNX_NVM_SW_ARB_ARB_ARB2 (1L<<10) 1781 #define BNX_NVM_SW_ARB_ARB_ARB3 (1L<<11) 1782 #define BNX_NVM_SW_ARB_REQ0 (1L<<12) 1783 #define BNX_NVM_SW_ARB_REQ1 (1L<<13) 1784 #define BNX_NVM_SW_ARB_REQ2 (1L<<14) 1785 #define BNX_NVM_SW_ARB_REQ3 (1L<<15) 1786 1787 #define BNX_NVM_ACCESS_ENABLE 0x00006424 1788 #define BNX_NVM_ACCESS_ENABLE_EN (1L<<0) 1789 #define BNX_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1790 1791 #define BNX_NVM_WRITE1 0x00006428 1792 #define BNX_NVM_WRITE1_WREN_CMD (0xffL<<0) 1793 #define BNX_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1794 #define BNX_NVM_WRITE1_SR_DATA (0xffL<<16) 1795 1796 1797 1798 /* 1799 * dma_reg definition 1800 * offset: 0xc00 1801 */ 1802 #define BNX_DMA_COMMAND 0x00000c00 1803 #define BNX_DMA_COMMAND_ENABLE (1L<<0) 1804 1805 #define BNX_DMA_STATUS 0x00000c04 1806 #define BNX_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 1807 #define BNX_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 1808 #define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 1809 #define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 1810 #define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 1811 #define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 1812 #define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 1813 #define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 1814 #define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1815 #define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1816 #define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 1817 1818 #define BNX_DMA_CONFIG 0x00000c08 1819 #define BNX_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 1820 #define BNX_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 1821 #define BNX_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 1822 #define BNX_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 1823 #define BNX_DMA_CONFIG_ONE_DMA (1L<<6) 1824 #define BNX_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 1825 #define BNX_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 1826 #define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 1827 #define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 1828 #define BNX_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 1829 #define BNX_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 1830 #define BNX_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 1831 #define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 1832 #define BNX_DMA_CONFIG_BIG_SIZE (0xfL<<24) 1833 #define BNX_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 1834 #define BNX_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 1835 #define BNX_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 1836 #define BNX_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 1837 #define BNX_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 1838 1839 #define BNX_DMA_BLACKOUT 0x00000c0c 1840 #define BNX_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 1841 #define BNX_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 1842 #define BNX_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 1843 1844 #define BNX_DMA_RCHAN_STAT 0x00000c30 1845 #define BNX_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1846 #define BNX_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 1847 #define BNX_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1848 #define BNX_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 1849 #define BNX_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1850 #define BNX_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 1851 #define BNX_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1852 #define BNX_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 1853 #define BNX_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1854 #define BNX_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 1855 #define BNX_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1856 #define BNX_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 1857 #define BNX_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1858 #define BNX_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 1859 #define BNX_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1860 #define BNX_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 1861 1862 #define BNX_DMA_WCHAN_STAT 0x00000c34 1863 #define BNX_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1864 #define BNX_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 1865 #define BNX_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1866 #define BNX_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 1867 #define BNX_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1868 #define BNX_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 1869 #define BNX_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1870 #define BNX_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 1871 #define BNX_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1872 #define BNX_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 1873 #define BNX_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1874 #define BNX_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 1875 #define BNX_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1876 #define BNX_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 1877 #define BNX_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1878 #define BNX_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 1879 1880 #define BNX_DMA_RCHAN_ASSIGNMENT 0x00000c38 1881 #define BNX_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 1882 #define BNX_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 1883 #define BNX_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 1884 #define BNX_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 1885 #define BNX_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 1886 #define BNX_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 1887 #define BNX_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 1888 #define BNX_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 1889 1890 #define BNX_DMA_WCHAN_ASSIGNMENT 0x00000c3c 1891 #define BNX_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 1892 #define BNX_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 1893 #define BNX_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 1894 #define BNX_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 1895 #define BNX_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 1896 #define BNX_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 1897 #define BNX_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 1898 #define BNX_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 1899 1900 #define BNX_DMA_RCHAN_STAT_00 0x00000c40 1901 #define BNX_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1902 1903 #define BNX_DMA_RCHAN_STAT_01 0x00000c44 1904 #define BNX_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1905 1906 #define BNX_DMA_RCHAN_STAT_02 0x00000c48 1907 #define BNX_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 1908 #define BNX_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 1909 #define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 1910 #define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1911 1912 #define BNX_DMA_RCHAN_STAT_10 0x00000c4c 1913 #define BNX_DMA_RCHAN_STAT_11 0x00000c50 1914 #define BNX_DMA_RCHAN_STAT_12 0x00000c54 1915 #define BNX_DMA_RCHAN_STAT_20 0x00000c58 1916 #define BNX_DMA_RCHAN_STAT_21 0x00000c5c 1917 #define BNX_DMA_RCHAN_STAT_22 0x00000c60 1918 #define BNX_DMA_RCHAN_STAT_30 0x00000c64 1919 #define BNX_DMA_RCHAN_STAT_31 0x00000c68 1920 #define BNX_DMA_RCHAN_STAT_32 0x00000c6c 1921 #define BNX_DMA_RCHAN_STAT_40 0x00000c70 1922 #define BNX_DMA_RCHAN_STAT_41 0x00000c74 1923 #define BNX_DMA_RCHAN_STAT_42 0x00000c78 1924 #define BNX_DMA_RCHAN_STAT_50 0x00000c7c 1925 #define BNX_DMA_RCHAN_STAT_51 0x00000c80 1926 #define BNX_DMA_RCHAN_STAT_52 0x00000c84 1927 #define BNX_DMA_RCHAN_STAT_60 0x00000c88 1928 #define BNX_DMA_RCHAN_STAT_61 0x00000c8c 1929 #define BNX_DMA_RCHAN_STAT_62 0x00000c90 1930 #define BNX_DMA_RCHAN_STAT_70 0x00000c94 1931 #define BNX_DMA_RCHAN_STAT_71 0x00000c98 1932 #define BNX_DMA_RCHAN_STAT_72 0x00000c9c 1933 #define BNX_DMA_WCHAN_STAT_00 0x00000ca0 1934 #define BNX_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1935 1936 #define BNX_DMA_WCHAN_STAT_01 0x00000ca4 1937 #define BNX_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1938 1939 #define BNX_DMA_WCHAN_STAT_02 0x00000ca8 1940 #define BNX_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 1941 #define BNX_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 1942 #define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 1943 #define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1944 1945 #define BNX_DMA_WCHAN_STAT_10 0x00000cac 1946 #define BNX_DMA_WCHAN_STAT_11 0x00000cb0 1947 #define BNX_DMA_WCHAN_STAT_12 0x00000cb4 1948 #define BNX_DMA_WCHAN_STAT_20 0x00000cb8 1949 #define BNX_DMA_WCHAN_STAT_21 0x00000cbc 1950 #define BNX_DMA_WCHAN_STAT_22 0x00000cc0 1951 #define BNX_DMA_WCHAN_STAT_30 0x00000cc4 1952 #define BNX_DMA_WCHAN_STAT_31 0x00000cc8 1953 #define BNX_DMA_WCHAN_STAT_32 0x00000ccc 1954 #define BNX_DMA_WCHAN_STAT_40 0x00000cd0 1955 #define BNX_DMA_WCHAN_STAT_41 0x00000cd4 1956 #define BNX_DMA_WCHAN_STAT_42 0x00000cd8 1957 #define BNX_DMA_WCHAN_STAT_50 0x00000cdc 1958 #define BNX_DMA_WCHAN_STAT_51 0x00000ce0 1959 #define BNX_DMA_WCHAN_STAT_52 0x00000ce4 1960 #define BNX_DMA_WCHAN_STAT_60 0x00000ce8 1961 #define BNX_DMA_WCHAN_STAT_61 0x00000cec 1962 #define BNX_DMA_WCHAN_STAT_62 0x00000cf0 1963 #define BNX_DMA_WCHAN_STAT_70 0x00000cf4 1964 #define BNX_DMA_WCHAN_STAT_71 0x00000cf8 1965 #define BNX_DMA_WCHAN_STAT_72 0x00000cfc 1966 #define BNX_DMA_ARB_STAT_00 0x00000d00 1967 #define BNX_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 1968 #define BNX_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 1969 #define BNX_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 1970 1971 #define BNX_DMA_ARB_STAT_01 0x00000d04 1972 #define BNX_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 1973 #define BNX_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 1974 #define BNX_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 1975 #define BNX_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 1976 #define BNX_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 1977 #define BNX_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 1978 #define BNX_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 1979 #define BNX_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 1980 1981 #define BNX_DMA_FUSE_CTRL0_CMD 0x00000f00 1982 #define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 1983 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 1984 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 1985 #define BNX_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 1986 #define BNX_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 1987 1988 #define BNX_DMA_FUSE_CTRL0_DATA 0x00000f04 1989 #define BNX_DMA_FUSE_CTRL1_CMD 0x00000f08 1990 #define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 1991 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 1992 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 1993 #define BNX_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 1994 #define BNX_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 1995 1996 #define BNX_DMA_FUSE_CTRL1_DATA 0x00000f0c 1997 #define BNX_DMA_FUSE_CTRL2_CMD 0x00000f10 1998 #define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 1999 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2000 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2001 #define BNX_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2002 #define BNX_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2003 2004 #define BNX_DMA_FUSE_CTRL2_DATA 0x00000f14 2005 2006 2007 /* 2008 * context_reg definition 2009 * offset: 0x1000 2010 */ 2011 #define BNX_CTX_COMMAND 0x00001000 2012 #define BNX_CTX_COMMAND_ENABLED (1L<<0) 2013 2014 #define BNX_CTX_STATUS 0x00001004 2015 #define BNX_CTX_STATUS_LOCK_WAIT (1L<<0) 2016 #define BNX_CTX_STATUS_READ_STAT (1L<<16) 2017 #define BNX_CTX_STATUS_WRITE_STAT (1L<<17) 2018 #define BNX_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2019 #define BNX_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2020 2021 #define BNX_CTX_VIRT_ADDR 0x00001008 2022 #define BNX_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2023 2024 #define BNX_CTX_PAGE_TBL 0x0000100c 2025 #define BNX_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2026 2027 #define BNX_CTX_DATA_ADR 0x00001010 2028 #define BNX_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2029 2030 #define BNX_CTX_DATA 0x00001014 2031 #define BNX_CTX_LOCK 0x00001018 2032 #define BNX_CTX_LOCK_TYPE (0x7L<<0) 2033 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2034 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2035 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2036 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2037 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2038 #define BNX_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2039 #define BNX_CTX_LOCK_GRANTED (1L<<26) 2040 #define BNX_CTX_LOCK_MODE (0x7L<<27) 2041 #define BNX_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2042 #define BNX_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2043 #define BNX_CTX_LOCK_MODE_SURE (0x2L<<27) 2044 #define BNX_CTX_LOCK_STATUS (1L<<30) 2045 #define BNX_CTX_LOCK_REQ (1L<<31) 2046 2047 #define BNX_CTX_ACCESS_STATUS 0x00001040 2048 #define BNX_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2049 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2050 #define BNX_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2051 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2052 #define BNX_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2053 2054 #define BNX_CTX_DBG_LOCK_STATUS 0x00001044 2055 #define BNX_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2056 #define BNX_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2057 2058 #define BNX_CTX_CHNL_LOCK_STATUS_0 0x00001080 2059 #define BNX_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2060 #define BNX_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2061 #define BNX_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2062 2063 #define BNX_CTX_CHNL_LOCK_STATUS_1 0x00001084 2064 #define BNX_CTX_CHNL_LOCK_STATUS_2 0x00001088 2065 #define BNX_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2066 #define BNX_CTX_CHNL_LOCK_STATUS_4 0x00001090 2067 #define BNX_CTX_CHNL_LOCK_STATUS_5 0x00001094 2068 #define BNX_CTX_CHNL_LOCK_STATUS_6 0x00001098 2069 #define BNX_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2070 #define BNX_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2071 2072 2073 /* 2074 * emac_reg definition 2075 * offset: 0x1400 2076 */ 2077 #define BNX_EMAC_MODE 0x00001400 2078 #define BNX_EMAC_MODE_RESET (1L<<0) 2079 #define BNX_EMAC_MODE_HALF_DUPLEX (1L<<1) 2080 #define BNX_EMAC_MODE_PORT (0x3L<<2) 2081 #define BNX_EMAC_MODE_PORT_NONE (0L<<2) 2082 #define BNX_EMAC_MODE_PORT_MII (1L<<2) 2083 #define BNX_EMAC_MODE_PORT_GMII (2L<<2) 2084 #define BNX_EMAC_MODE_PORT_MII_10 (3L<<2) 2085 #define BNX_EMAC_MODE_MAC_LOOP (1L<<4) 2086 #define BNX_EMAC_MODE_25G (1L<<5) 2087 #define BNX_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2088 #define BNX_EMAC_MODE_TX_BURST (1L<<8) 2089 #define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2090 #define BNX_EMAC_MODE_EXT_LINK_POL (1L<<10) 2091 #define BNX_EMAC_MODE_FORCE_LINK (1L<<11) 2092 #define BNX_EMAC_MODE_MPKT (1L<<18) 2093 #define BNX_EMAC_MODE_MPKT_RCVD (1L<<19) 2094 #define BNX_EMAC_MODE_ACPI_RCVD (1L<<20) 2095 2096 #define BNX_EMAC_STATUS 0x00001404 2097 #define BNX_EMAC_STATUS_LINK (1L<<11) 2098 #define BNX_EMAC_STATUS_LINK_CHANGE (1L<<12) 2099 #define BNX_EMAC_STATUS_MI_COMPLETE (1L<<22) 2100 #define BNX_EMAC_STATUS_MI_INT (1L<<23) 2101 #define BNX_EMAC_STATUS_AP_ERROR (1L<<24) 2102 #define BNX_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2103 2104 #define BNX_EMAC_ATTENTION_ENA 0x00001408 2105 #define BNX_EMAC_ATTENTION_ENA_LINK (1L<<11) 2106 #define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2107 #define BNX_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2108 #define BNX_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2109 2110 #define BNX_EMAC_LED 0x0000140c 2111 #define BNX_EMAC_LED_OVERRIDE (1L<<0) 2112 #define BNX_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2113 #define BNX_EMAC_LED_100MB_OVERRIDE (1L<<2) 2114 #define BNX_EMAC_LED_10MB_OVERRIDE (1L<<3) 2115 #define BNX_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2116 #define BNX_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2117 #define BNX_EMAC_LED_TRAFFIC (1L<<6) 2118 #define BNX_EMAC_LED_1000MB (1L<<7) 2119 #define BNX_EMAC_LED_100MB (1L<<8) 2120 #define BNX_EMAC_LED_10MB (1L<<9) 2121 #define BNX_EMAC_LED_TRAFFIC_STAT (1L<<10) 2122 #define BNX_EMAC_LED_BLNK_RATE (0xfffL<<19) 2123 #define BNX_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2124 2125 #define BNX_EMAC_MAC_MATCH0 0x00001410 2126 #define BNX_EMAC_MAC_MATCH1 0x00001414 2127 #define BNX_EMAC_MAC_MATCH2 0x00001418 2128 #define BNX_EMAC_MAC_MATCH3 0x0000141c 2129 #define BNX_EMAC_MAC_MATCH4 0x00001420 2130 #define BNX_EMAC_MAC_MATCH5 0x00001424 2131 #define BNX_EMAC_MAC_MATCH6 0x00001428 2132 #define BNX_EMAC_MAC_MATCH7 0x0000142c 2133 #define BNX_EMAC_MAC_MATCH8 0x00001430 2134 #define BNX_EMAC_MAC_MATCH9 0x00001434 2135 #define BNX_EMAC_MAC_MATCH10 0x00001438 2136 #define BNX_EMAC_MAC_MATCH11 0x0000143c 2137 #define BNX_EMAC_MAC_MATCH12 0x00001440 2138 #define BNX_EMAC_MAC_MATCH13 0x00001444 2139 #define BNX_EMAC_MAC_MATCH14 0x00001448 2140 #define BNX_EMAC_MAC_MATCH15 0x0000144c 2141 #define BNX_EMAC_MAC_MATCH16 0x00001450 2142 #define BNX_EMAC_MAC_MATCH17 0x00001454 2143 #define BNX_EMAC_MAC_MATCH18 0x00001458 2144 #define BNX_EMAC_MAC_MATCH19 0x0000145c 2145 #define BNX_EMAC_MAC_MATCH20 0x00001460 2146 #define BNX_EMAC_MAC_MATCH21 0x00001464 2147 #define BNX_EMAC_MAC_MATCH22 0x00001468 2148 #define BNX_EMAC_MAC_MATCH23 0x0000146c 2149 #define BNX_EMAC_MAC_MATCH24 0x00001470 2150 #define BNX_EMAC_MAC_MATCH25 0x00001474 2151 #define BNX_EMAC_MAC_MATCH26 0x00001478 2152 #define BNX_EMAC_MAC_MATCH27 0x0000147c 2153 #define BNX_EMAC_MAC_MATCH28 0x00001480 2154 #define BNX_EMAC_MAC_MATCH29 0x00001484 2155 #define BNX_EMAC_MAC_MATCH30 0x00001488 2156 #define BNX_EMAC_MAC_MATCH31 0x0000148c 2157 #define BNX_EMAC_BACKOFF_SEED 0x00001498 2158 #define BNX_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2159 2160 #define BNX_EMAC_RX_MTU_SIZE 0x0000149c 2161 #define BNX_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2162 #define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2163 2164 #define BNX_EMAC_SERDES_CNTL 0x000014a4 2165 #define BNX_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2166 #define BNX_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2167 #define BNX_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2168 #define BNX_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2169 #define BNX_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2170 #define BNX_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2171 #define BNX_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2172 #define BNX_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2173 #define BNX_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2174 #define BNX_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2175 #define BNX_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2176 #define BNX_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2177 #define BNX_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2178 #define BNX_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2179 #define BNX_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2180 #define BNX_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2181 2182 #define BNX_EMAC_SERDES_STATUS 0x000014a8 2183 #define BNX_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2184 #define BNX_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2185 2186 #define BNX_EMAC_MDIO_COMM 0x000014ac 2187 #define BNX_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2188 #define BNX_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2189 #define BNX_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2190 #define BNX_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2191 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2192 #define BNX_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2193 #define BNX_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2194 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2195 #define BNX_EMAC_MDIO_COMM_FAIL (1L<<28) 2196 #define BNX_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2197 #define BNX_EMAC_MDIO_COMM_DISEXT (1L<<30) 2198 2199 #define BNX_EMAC_MDIO_STATUS 0x000014b0 2200 #define BNX_EMAC_MDIO_STATUS_LINK (1L<<0) 2201 #define BNX_EMAC_MDIO_STATUS_10MB (1L<<1) 2202 2203 #define BNX_EMAC_MDIO_MODE 0x000014b4 2204 #define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2205 #define BNX_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2206 #define BNX_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2207 #define BNX_EMAC_MDIO_MODE_MDIO (1L<<9) 2208 #define BNX_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2209 #define BNX_EMAC_MDIO_MODE_MDC (1L<<11) 2210 #define BNX_EMAC_MDIO_MODE_MDINT (1L<<12) 2211 #define BNX_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2212 2213 #define BNX_EMAC_MDIO_AUTO_STATUS 0x000014b8 2214 #define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2215 2216 #define BNX_EMAC_TX_MODE 0x000014bc 2217 #define BNX_EMAC_TX_MODE_RESET (1L<<0) 2218 #define BNX_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2219 #define BNX_EMAC_TX_MODE_FLOW_EN (1L<<4) 2220 #define BNX_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2221 #define BNX_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2222 #define BNX_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2223 2224 #define BNX_EMAC_TX_STATUS 0x000014c0 2225 #define BNX_EMAC_TX_STATUS_XOFFED (1L<<0) 2226 #define BNX_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2227 #define BNX_EMAC_TX_STATUS_XON_SENT (1L<<2) 2228 #define BNX_EMAC_TX_STATUS_LINK_UP (1L<<3) 2229 #define BNX_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2230 2231 #define BNX_EMAC_TX_LENGTHS 0x000014c4 2232 #define BNX_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2233 #define BNX_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2234 #define BNX_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2235 2236 #define BNX_EMAC_RX_MODE 0x000014c8 2237 #define BNX_EMAC_RX_MODE_RESET (1L<<0) 2238 #define BNX_EMAC_RX_MODE_FLOW_EN (1L<<2) 2239 #define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2240 #define BNX_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2241 #define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2242 #define BNX_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2243 #define BNX_EMAC_RX_MODE_LLC_CHK (1L<<7) 2244 #define BNX_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2245 #define BNX_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2246 #define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2247 #define BNX_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2248 #define BNX_EMAC_RX_MODE_SORT_MODE (1L<<12) 2249 2250 #define BNX_EMAC_RX_STATUS 0x000014cc 2251 #define BNX_EMAC_RX_STATUS_FFED (1L<<0) 2252 #define BNX_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2253 #define BNX_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2254 2255 #define BNX_EMAC_MULTICAST_HASH0 0x000014d0 2256 #define BNX_EMAC_MULTICAST_HASH1 0x000014d4 2257 #define BNX_EMAC_MULTICAST_HASH2 0x000014d8 2258 #define BNX_EMAC_MULTICAST_HASH3 0x000014dc 2259 #define BNX_EMAC_MULTICAST_HASH4 0x000014e0 2260 #define BNX_EMAC_MULTICAST_HASH5 0x000014e4 2261 #define BNX_EMAC_MULTICAST_HASH6 0x000014e8 2262 #define BNX_EMAC_MULTICAST_HASH7 0x000014ec 2263 #define BNX_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2264 #define BNX_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2265 #define BNX_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2266 #define BNX_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2267 #define BNX_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2268 #define BNX_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2269 #define BNX_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2270 #define BNX_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2271 #define BNX_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2272 #define BNX_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2273 #define BNX_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2274 #define BNX_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2275 #define BNX_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2276 #define BNX_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2277 #define BNX_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2278 #define BNX_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2279 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2280 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2281 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2282 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2283 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2284 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2285 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2286 #define BNX_EMAC_RXMAC_DEBUG0 0x0000155c 2287 #define BNX_EMAC_RXMAC_DEBUG1 0x00001560 2288 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2289 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2290 #define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2291 #define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2292 #define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2293 #define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2294 #define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2295 #define BNX_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2296 #define BNX_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2297 2298 #define BNX_EMAC_RXMAC_DEBUG2 0x00001564 2299 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2300 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2301 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2302 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2303 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2304 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2305 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2306 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2307 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2308 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2309 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2310 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2311 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2312 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2313 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2314 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2315 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2316 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2317 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2318 #define BNX_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2319 #define BNX_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2320 #define BNX_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2321 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2322 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2323 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2324 #define BNX_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2325 #define BNX_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2326 2327 #define BNX_EMAC_RXMAC_DEBUG3 0x00001568 2328 #define BNX_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2329 #define BNX_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2330 2331 #define BNX_EMAC_RXMAC_DEBUG4 0x0000156c 2332 #define BNX_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2333 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2334 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2335 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2336 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2337 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2338 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2339 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2340 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2341 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2342 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2343 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2344 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2345 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2346 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2347 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2348 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2349 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2350 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2351 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2352 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2353 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2354 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2355 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2356 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2357 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2358 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2359 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2360 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2361 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2362 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2363 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2364 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2365 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2366 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2367 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2368 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2369 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2370 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2371 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2372 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2373 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2374 #define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2375 #define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2376 #define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2377 #define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2378 #define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2379 #define BNX_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2380 #define BNX_EMAC_RXMAC_DEBUG4_START (1L<<28) 2381 2382 #define BNX_EMAC_RXMAC_DEBUG5 0x00001570 2383 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2384 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2385 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2386 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2387 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2388 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2389 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2390 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2391 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2392 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2393 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2394 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2395 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2396 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2397 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2398 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2399 #define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2400 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2401 #define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2402 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2403 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2404 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2405 #define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2406 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2407 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2408 #define BNX_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2409 2410 #define BNX_EMAC_RX_STAT_AC0 0x00001580 2411 #define BNX_EMAC_RX_STAT_AC1 0x00001584 2412 #define BNX_EMAC_RX_STAT_AC2 0x00001588 2413 #define BNX_EMAC_RX_STAT_AC3 0x0000158c 2414 #define BNX_EMAC_RX_STAT_AC4 0x00001590 2415 #define BNX_EMAC_RX_STAT_AC5 0x00001594 2416 #define BNX_EMAC_RX_STAT_AC6 0x00001598 2417 #define BNX_EMAC_RX_STAT_AC7 0x0000159c 2418 #define BNX_EMAC_RX_STAT_AC8 0x000015a0 2419 #define BNX_EMAC_RX_STAT_AC9 0x000015a4 2420 #define BNX_EMAC_RX_STAT_AC10 0x000015a8 2421 #define BNX_EMAC_RX_STAT_AC11 0x000015ac 2422 #define BNX_EMAC_RX_STAT_AC12 0x000015b0 2423 #define BNX_EMAC_RX_STAT_AC13 0x000015b4 2424 #define BNX_EMAC_RX_STAT_AC14 0x000015b8 2425 #define BNX_EMAC_RX_STAT_AC15 0x000015bc 2426 #define BNX_EMAC_RX_STAT_AC16 0x000015c0 2427 #define BNX_EMAC_RX_STAT_AC17 0x000015c4 2428 #define BNX_EMAC_RX_STAT_AC18 0x000015c8 2429 #define BNX_EMAC_RX_STAT_AC19 0x000015cc 2430 #define BNX_EMAC_RX_STAT_AC20 0x000015d0 2431 #define BNX_EMAC_RX_STAT_AC21 0x000015d4 2432 #define BNX_EMAC_RX_STAT_AC22 0x000015d8 2433 #define BNX_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2434 #define BNX_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2435 #define BNX_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2436 #define BNX_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2437 #define BNX_EMAC_TX_STAT_OUTXONSENT 0x0000160c 2438 #define BNX_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 2439 #define BNX_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 2440 #define BNX_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 2441 #define BNX_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 2442 #define BNX_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 2443 #define BNX_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 2444 #define BNX_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 2445 #define BNX_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 2446 #define BNX_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 2447 #define BNX_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 2448 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 2449 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 2450 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 2451 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2452 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2453 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2454 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2455 #define BNX_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2456 #define BNX_EMAC_TXMAC_DEBUG0 0x00001658 2457 #define BNX_EMAC_TXMAC_DEBUG1 0x0000165c 2458 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 2459 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 2460 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 2461 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 2462 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 2463 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 2464 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 2465 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 2466 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 2467 #define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 2468 #define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 2469 #define BNX_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 2470 #define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 2471 #define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 2472 #define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 2473 #define BNX_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 2474 #define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 2475 #define BNX_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 2476 #define BNX_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 2477 2478 #define BNX_EMAC_TXMAC_DEBUG2 0x00001660 2479 #define BNX_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 2480 #define BNX_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 2481 #define BNX_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 2482 #define BNX_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 2483 2484 #define BNX_EMAC_TXMAC_DEBUG3 0x00001664 2485 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 2486 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 2487 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 2488 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 2489 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 2490 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 2491 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 2492 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 2493 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 2494 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 2495 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 2496 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 2497 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 2498 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 2499 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 2500 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 2501 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 2502 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 2503 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 2504 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 2505 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 2506 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 2507 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 2508 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 2509 #define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 2510 #define BNX_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 2511 #define BNX_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 2512 #define BNX_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 2513 2514 #define BNX_EMAC_TXMAC_DEBUG4 0x00001668 2515 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 2516 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 2517 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 2518 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 2519 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 2520 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 2521 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 2522 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 2523 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 2524 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 2525 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 2526 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 2527 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 2528 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 2529 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 2530 #define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 2531 #define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 2532 #define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 2533 #define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 2534 #define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 2535 #define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 2536 #define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 2537 #define BNX_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 2538 #define BNX_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 2539 #define BNX_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 2540 #define BNX_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 2541 #define BNX_EMAC_TXMAC_DEBUG4_GO (1L<<31) 2542 2543 #define BNX_EMAC_TX_STAT_AC0 0x00001680 2544 #define BNX_EMAC_TX_STAT_AC1 0x00001684 2545 #define BNX_EMAC_TX_STAT_AC2 0x00001688 2546 #define BNX_EMAC_TX_STAT_AC3 0x0000168c 2547 #define BNX_EMAC_TX_STAT_AC4 0x00001690 2548 #define BNX_EMAC_TX_STAT_AC5 0x00001694 2549 #define BNX_EMAC_TX_STAT_AC6 0x00001698 2550 #define BNX_EMAC_TX_STAT_AC7 0x0000169c 2551 #define BNX_EMAC_TX_STAT_AC8 0x000016a0 2552 #define BNX_EMAC_TX_STAT_AC9 0x000016a4 2553 #define BNX_EMAC_TX_STAT_AC10 0x000016a8 2554 #define BNX_EMAC_TX_STAT_AC11 0x000016ac 2555 #define BNX_EMAC_TX_STAT_AC12 0x000016b0 2556 #define BNX_EMAC_TX_STAT_AC13 0x000016b4 2557 #define BNX_EMAC_TX_STAT_AC14 0x000016b8 2558 #define BNX_EMAC_TX_STAT_AC15 0x000016bc 2559 #define BNX_EMAC_TX_STAT_AC16 0x000016c0 2560 #define BNX_EMAC_TX_STAT_AC17 0x000016c4 2561 #define BNX_EMAC_TX_STAT_AC18 0x000016c8 2562 #define BNX_EMAC_TX_STAT_AC19 0x000016cc 2563 #define BNX_EMAC_TX_STAT_AC20 0x000016d0 2564 #define BNX_EMAC_TX_STAT_AC21 0x000016d4 2565 #define BNX_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 2566 2567 2568 /* 2569 * rpm_reg definition 2570 * offset: 0x1800 2571 */ 2572 #define BNX_RPM_COMMAND 0x00001800 2573 #define BNX_RPM_COMMAND_ENABLED (1L<<0) 2574 #define BNX_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 2575 2576 #define BNX_RPM_STATUS 0x00001804 2577 #define BNX_RPM_STATUS_MBUF_WAIT (1L<<0) 2578 #define BNX_RPM_STATUS_FREE_WAIT (1L<<1) 2579 2580 #define BNX_RPM_CONFIG 0x00001808 2581 #define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 2582 #define BNX_RPM_CONFIG_ACPI_ENA (1L<<1) 2583 #define BNX_RPM_CONFIG_ACPI_KEEP (1L<<2) 2584 #define BNX_RPM_CONFIG_MP_KEEP (1L<<3) 2585 #define BNX_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 2586 #define BNX_RPM_CONFIG_IGNORE_VLAN (1L<<31) 2587 2588 #define BNX_RPM_VLAN_MATCH0 0x00001810 2589 #define BNX_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 2590 2591 #define BNX_RPM_VLAN_MATCH1 0x00001814 2592 #define BNX_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 2593 2594 #define BNX_RPM_VLAN_MATCH2 0x00001818 2595 #define BNX_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 2596 2597 #define BNX_RPM_VLAN_MATCH3 0x0000181c 2598 #define BNX_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 2599 2600 #define BNX_RPM_SORT_USER0 0x00001820 2601 #define BNX_RPM_SORT_USER0_PM_EN (0xffffL<<0) 2602 #define BNX_RPM_SORT_USER0_BC_EN (1L<<16) 2603 #define BNX_RPM_SORT_USER0_MC_EN (1L<<17) 2604 #define BNX_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 2605 #define BNX_RPM_SORT_USER0_PROM_EN (1L<<19) 2606 #define BNX_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 2607 #define BNX_RPM_SORT_USER0_PROM_VLAN (1L<<24) 2608 #define BNX_RPM_SORT_USER0_ENA (1L<<31) 2609 2610 #define BNX_RPM_SORT_USER1 0x00001824 2611 #define BNX_RPM_SORT_USER1_PM_EN (0xffffL<<0) 2612 #define BNX_RPM_SORT_USER1_BC_EN (1L<<16) 2613 #define BNX_RPM_SORT_USER1_MC_EN (1L<<17) 2614 #define BNX_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 2615 #define BNX_RPM_SORT_USER1_PROM_EN (1L<<19) 2616 #define BNX_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 2617 #define BNX_RPM_SORT_USER1_PROM_VLAN (1L<<24) 2618 #define BNX_RPM_SORT_USER1_ENA (1L<<31) 2619 2620 #define BNX_RPM_SORT_USER2 0x00001828 2621 #define BNX_RPM_SORT_USER2_PM_EN (0xffffL<<0) 2622 #define BNX_RPM_SORT_USER2_BC_EN (1L<<16) 2623 #define BNX_RPM_SORT_USER2_MC_EN (1L<<17) 2624 #define BNX_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 2625 #define BNX_RPM_SORT_USER2_PROM_EN (1L<<19) 2626 #define BNX_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 2627 #define BNX_RPM_SORT_USER2_PROM_VLAN (1L<<24) 2628 #define BNX_RPM_SORT_USER2_ENA (1L<<31) 2629 2630 #define BNX_RPM_SORT_USER3 0x0000182c 2631 #define BNX_RPM_SORT_USER3_PM_EN (0xffffL<<0) 2632 #define BNX_RPM_SORT_USER3_BC_EN (1L<<16) 2633 #define BNX_RPM_SORT_USER3_MC_EN (1L<<17) 2634 #define BNX_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 2635 #define BNX_RPM_SORT_USER3_PROM_EN (1L<<19) 2636 #define BNX_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 2637 #define BNX_RPM_SORT_USER3_PROM_VLAN (1L<<24) 2638 #define BNX_RPM_SORT_USER3_ENA (1L<<31) 2639 2640 #define BNX_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 2641 #define BNX_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 2642 #define BNX_RPM_STAT_IFINFTQDISCARDS 0x00001848 2643 #define BNX_RPM_STAT_IFINMBUFDISCARD 0x0000184c 2644 #define BNX_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 2645 #define BNX_RPM_STAT_AC0 0x00001880 2646 #define BNX_RPM_STAT_AC1 0x00001884 2647 #define BNX_RPM_STAT_AC2 0x00001888 2648 #define BNX_RPM_STAT_AC3 0x0000188c 2649 #define BNX_RPM_STAT_AC4 0x00001890 2650 #define BNX_RPM_RC_CNTL_0 0x00001900 2651 #define BNX_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 2652 #define BNX_RPM_RC_CNTL_0_CLASS (0x7L<<8) 2653 #define BNX_RPM_RC_CNTL_0_PRIORITY (1L<<11) 2654 #define BNX_RPM_RC_CNTL_0_P4 (1L<<12) 2655 #define BNX_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 2656 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 2657 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 2658 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 2659 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 2660 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 2661 #define BNX_RPM_RC_CNTL_0_COMP (0x3L<<16) 2662 #define BNX_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 2663 #define BNX_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 2664 #define BNX_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 2665 #define BNX_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 2666 #define BNX_RPM_RC_CNTL_0_SBIT (1L<<19) 2667 #define BNX_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 2668 #define BNX_RPM_RC_CNTL_0_MAP (1L<<24) 2669 #define BNX_RPM_RC_CNTL_0_DISCARD (1L<<25) 2670 #define BNX_RPM_RC_CNTL_0_MASK (1L<<26) 2671 #define BNX_RPM_RC_CNTL_0_P1 (1L<<27) 2672 #define BNX_RPM_RC_CNTL_0_P2 (1L<<28) 2673 #define BNX_RPM_RC_CNTL_0_P3 (1L<<29) 2674 #define BNX_RPM_RC_CNTL_0_NBIT (1L<<30) 2675 2676 #define BNX_RPM_RC_VALUE_MASK_0 0x00001904 2677 #define BNX_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 2678 #define BNX_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 2679 2680 #define BNX_RPM_RC_CNTL_1 0x00001908 2681 #define BNX_RPM_RC_CNTL_1_A (0x3ffffL<<0) 2682 #define BNX_RPM_RC_CNTL_1_B (0xfffL<<19) 2683 2684 #define BNX_RPM_RC_VALUE_MASK_1 0x0000190c 2685 #define BNX_RPM_RC_CNTL_2 0x00001910 2686 #define BNX_RPM_RC_CNTL_2_A (0x3ffffL<<0) 2687 #define BNX_RPM_RC_CNTL_2_B (0xfffL<<19) 2688 2689 #define BNX_RPM_RC_VALUE_MASK_2 0x00001914 2690 #define BNX_RPM_RC_CNTL_3 0x00001918 2691 #define BNX_RPM_RC_CNTL_3_A (0x3ffffL<<0) 2692 #define BNX_RPM_RC_CNTL_3_B (0xfffL<<19) 2693 2694 #define BNX_RPM_RC_VALUE_MASK_3 0x0000191c 2695 #define BNX_RPM_RC_CNTL_4 0x00001920 2696 #define BNX_RPM_RC_CNTL_4_A (0x3ffffL<<0) 2697 #define BNX_RPM_RC_CNTL_4_B (0xfffL<<19) 2698 2699 #define BNX_RPM_RC_VALUE_MASK_4 0x00001924 2700 #define BNX_RPM_RC_CNTL_5 0x00001928 2701 #define BNX_RPM_RC_CNTL_5_A (0x3ffffL<<0) 2702 #define BNX_RPM_RC_CNTL_5_B (0xfffL<<19) 2703 2704 #define BNX_RPM_RC_VALUE_MASK_5 0x0000192c 2705 #define BNX_RPM_RC_CNTL_6 0x00001930 2706 #define BNX_RPM_RC_CNTL_6_A (0x3ffffL<<0) 2707 #define BNX_RPM_RC_CNTL_6_B (0xfffL<<19) 2708 2709 #define BNX_RPM_RC_VALUE_MASK_6 0x00001934 2710 #define BNX_RPM_RC_CNTL_7 0x00001938 2711 #define BNX_RPM_RC_CNTL_7_A (0x3ffffL<<0) 2712 #define BNX_RPM_RC_CNTL_7_B (0xfffL<<19) 2713 2714 #define BNX_RPM_RC_VALUE_MASK_7 0x0000193c 2715 #define BNX_RPM_RC_CNTL_8 0x00001940 2716 #define BNX_RPM_RC_CNTL_8_A (0x3ffffL<<0) 2717 #define BNX_RPM_RC_CNTL_8_B (0xfffL<<19) 2718 2719 #define BNX_RPM_RC_VALUE_MASK_8 0x00001944 2720 #define BNX_RPM_RC_CNTL_9 0x00001948 2721 #define BNX_RPM_RC_CNTL_9_A (0x3ffffL<<0) 2722 #define BNX_RPM_RC_CNTL_9_B (0xfffL<<19) 2723 2724 #define BNX_RPM_RC_VALUE_MASK_9 0x0000194c 2725 #define BNX_RPM_RC_CNTL_10 0x00001950 2726 #define BNX_RPM_RC_CNTL_10_A (0x3ffffL<<0) 2727 #define BNX_RPM_RC_CNTL_10_B (0xfffL<<19) 2728 2729 #define BNX_RPM_RC_VALUE_MASK_10 0x00001954 2730 #define BNX_RPM_RC_CNTL_11 0x00001958 2731 #define BNX_RPM_RC_CNTL_11_A (0x3ffffL<<0) 2732 #define BNX_RPM_RC_CNTL_11_B (0xfffL<<19) 2733 2734 #define BNX_RPM_RC_VALUE_MASK_11 0x0000195c 2735 #define BNX_RPM_RC_CNTL_12 0x00001960 2736 #define BNX_RPM_RC_CNTL_12_A (0x3ffffL<<0) 2737 #define BNX_RPM_RC_CNTL_12_B (0xfffL<<19) 2738 2739 #define BNX_RPM_RC_VALUE_MASK_12 0x00001964 2740 #define BNX_RPM_RC_CNTL_13 0x00001968 2741 #define BNX_RPM_RC_CNTL_13_A (0x3ffffL<<0) 2742 #define BNX_RPM_RC_CNTL_13_B (0xfffL<<19) 2743 2744 #define BNX_RPM_RC_VALUE_MASK_13 0x0000196c 2745 #define BNX_RPM_RC_CNTL_14 0x00001970 2746 #define BNX_RPM_RC_CNTL_14_A (0x3ffffL<<0) 2747 #define BNX_RPM_RC_CNTL_14_B (0xfffL<<19) 2748 2749 #define BNX_RPM_RC_VALUE_MASK_14 0x00001974 2750 #define BNX_RPM_RC_CNTL_15 0x00001978 2751 #define BNX_RPM_RC_CNTL_15_A (0x3ffffL<<0) 2752 #define BNX_RPM_RC_CNTL_15_B (0xfffL<<19) 2753 2754 #define BNX_RPM_RC_VALUE_MASK_15 0x0000197c 2755 #define BNX_RPM_RC_CONFIG 0x00001980 2756 #define BNX_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 2757 #define BNX_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 2758 2759 #define BNX_RPM_DEBUG0 0x00001984 2760 #define BNX_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 2761 #define BNX_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 2762 #define BNX_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 2763 #define BNX_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 2764 #define BNX_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 2765 #define BNX_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 2766 #define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 2767 #define BNX_RPM_DEBUG0_LLC_SNAP (1L<<22) 2768 #define BNX_RPM_DEBUG0_FM_STARTED (1L<<23) 2769 #define BNX_RPM_DEBUG0_DONE (1L<<24) 2770 #define BNX_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 2771 #define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 2772 #define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 2773 #define BNX_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 2774 #define BNX_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 2775 2776 #define BNX_RPM_DEBUG1 0x00001988 2777 #define BNX_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 2778 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 2779 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 2780 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 2781 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 2782 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 2783 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 2784 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 2785 #define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 2786 #define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 2787 #define BNX_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 2788 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 2789 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 2790 #define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 2791 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 2792 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 2793 #define BNX_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 2794 #define BNX_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 2795 #define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 2796 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 2797 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 2798 #define BNX_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 2799 2800 #define BNX_RPM_DEBUG2 0x0000198c 2801 #define BNX_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 2802 #define BNX_RPM_DEBUG2_IP_BCNT (0xffL<<16) 2803 #define BNX_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 2804 #define BNX_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 2805 #define BNX_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 2806 #define BNX_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 2807 #define BNX_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 2808 #define BNX_RPM_DEBUG2_FM_DISCARD (1L<<29) 2809 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 2810 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 2811 2812 #define BNX_RPM_DEBUG3 0x00001990 2813 #define BNX_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 2814 #define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 2815 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 2816 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 2817 #define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 2818 #define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 2819 #define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 2820 #define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 2821 #define BNX_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 2822 #define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 2823 #define BNX_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 2824 #define BNX_RPM_DEBUG3_DROP_NXT (1L<<23) 2825 #define BNX_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 2826 #define BNX_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 2827 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 2828 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 2829 #define BNX_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 2830 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 2831 #define BNX_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 2832 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 2833 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 2834 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 2835 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 2836 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 2837 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 2838 #define BNX_RPM_DEBUG3_MBFREE_FSM (1L<<29) 2839 #define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 2840 #define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 2841 #define BNX_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 2842 #define BNX_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 2843 #define BNX_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 2844 #define BNX_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 2845 2846 #define BNX_RPM_DEBUG4 0x00001994 2847 #define BNX_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 2848 #define BNX_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 2849 #define BNX_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 2850 #define BNX_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 2851 2852 #define BNX_RPM_DEBUG5 0x00001998 2853 #define BNX_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 2854 #define BNX_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 2855 #define BNX_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 2856 #define BNX_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 2857 #define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 2858 #define BNX_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 2859 #define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 2860 #define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 2861 #define BNX_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 2862 #define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 2863 #define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 2864 #define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 2865 #define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 2866 #define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 2867 #define BNX_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 2868 #define BNX_RPM_DEBUG5_HOLDREG_RD (1L<<31) 2869 2870 #define BNX_RPM_DEBUG6 0x0000199c 2871 #define BNX_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 2872 #define BNX_RPM_DEBUG6_VEC (0xffffL<<16) 2873 2874 #define BNX_RPM_DEBUG7 0x000019a0 2875 #define BNX_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 2876 2877 #define BNX_RPM_DEBUG8 0x000019a4 2878 #define BNX_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 2879 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 2880 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 2881 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 2882 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 2883 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 2884 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 2885 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 2886 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 2887 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 2888 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 2889 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 2890 #define BNX_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 2891 #define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 2892 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 2893 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 2894 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 2895 #define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 2896 #define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 2897 #define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 2898 #define BNX_RPM_DEBUG8_EOF_DET (1L<<12) 2899 #define BNX_RPM_DEBUG8_SOF_DET (1L<<13) 2900 #define BNX_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 2901 #define BNX_RPM_DEBUG8_ALL_DONE (1L<<15) 2902 #define BNX_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 2903 #define BNX_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 2904 2905 #define BNX_RPM_DEBUG9 0x000019a8 2906 #define BNX_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 2907 #define BNX_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 2908 #define BNX_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 2909 #define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 2910 #define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 2911 #define BNX_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 2912 #define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 2913 2914 #define BNX_RPM_ACPI_DBG_BUF_W00 0x000019c0 2915 #define BNX_RPM_ACPI_DBG_BUF_W01 0x000019c4 2916 #define BNX_RPM_ACPI_DBG_BUF_W02 0x000019c8 2917 #define BNX_RPM_ACPI_DBG_BUF_W03 0x000019cc 2918 #define BNX_RPM_ACPI_DBG_BUF_W10 0x000019d0 2919 #define BNX_RPM_ACPI_DBG_BUF_W11 0x000019d4 2920 #define BNX_RPM_ACPI_DBG_BUF_W12 0x000019d8 2921 #define BNX_RPM_ACPI_DBG_BUF_W13 0x000019dc 2922 #define BNX_RPM_ACPI_DBG_BUF_W20 0x000019e0 2923 #define BNX_RPM_ACPI_DBG_BUF_W21 0x000019e4 2924 #define BNX_RPM_ACPI_DBG_BUF_W22 0x000019e8 2925 #define BNX_RPM_ACPI_DBG_BUF_W23 0x000019ec 2926 #define BNX_RPM_ACPI_DBG_BUF_W30 0x000019f0 2927 #define BNX_RPM_ACPI_DBG_BUF_W31 0x000019f4 2928 #define BNX_RPM_ACPI_DBG_BUF_W32 0x000019f8 2929 #define BNX_RPM_ACPI_DBG_BUF_W33 0x000019fc 2930 2931 2932 /* 2933 * rbuf_reg definition 2934 * offset: 0x200000 2935 */ 2936 #define BNX_RBUF_COMMAND 0x00200000 2937 #define BNX_RBUF_COMMAND_ENABLED (1L<<0) 2938 #define BNX_RBUF_COMMAND_FREE_INIT (1L<<1) 2939 #define BNX_RBUF_COMMAND_RAM_INIT (1L<<2) 2940 #define BNX_RBUF_COMMAND_OVER_FREE (1L<<4) 2941 #define BNX_RBUF_COMMAND_ALLOC_REQ (1L<<5) 2942 2943 #define BNX_RBUF_STATUS1 0x00200004 2944 #define BNX_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 2945 2946 #define BNX_RBUF_STATUS2 0x00200008 2947 #define BNX_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 2948 #define BNX_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 2949 2950 #define BNX_RBUF_CONFIG 0x0020000c 2951 #define BNX_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 2952 #define BNX_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 2953 2954 #define BNX_RBUF_FW_BUF_ALLOC 0x00200010 2955 #define BNX_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 2956 2957 #define BNX_RBUF_FW_BUF_FREE 0x00200014 2958 #define BNX_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 2959 #define BNX_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 2960 #define BNX_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 2961 2962 #define BNX_RBUF_FW_BUF_SEL 0x00200018 2963 #define BNX_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 2964 #define BNX_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 2965 #define BNX_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 2966 2967 #define BNX_RBUF_CONFIG2 0x0020001c 2968 #define BNX_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 2969 #define BNX_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 2970 2971 #define BNX_RBUF_CONFIG3 0x00200020 2972 #define BNX_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 2973 #define BNX_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 2974 2975 #define BNX_RBUF_PKT_DATA 0x00208000 2976 #define BNX_RBUF_CLIST_DATA 0x00210000 2977 #define BNX_RBUF_BUF_DATA 0x00220000 2978 2979 2980 /* 2981 * rv2p_reg definition 2982 * offset: 0x2800 2983 */ 2984 #define BNX_RV2P_COMMAND 0x00002800 2985 #define BNX_RV2P_COMMAND_ENABLED (1L<<0) 2986 #define BNX_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 2987 #define BNX_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 2988 #define BNX_RV2P_COMMAND_ABORT0 (1L<<4) 2989 #define BNX_RV2P_COMMAND_ABORT1 (1L<<5) 2990 #define BNX_RV2P_COMMAND_ABORT2 (1L<<6) 2991 #define BNX_RV2P_COMMAND_ABORT3 (1L<<7) 2992 #define BNX_RV2P_COMMAND_ABORT4 (1L<<8) 2993 #define BNX_RV2P_COMMAND_ABORT5 (1L<<9) 2994 #define BNX_RV2P_COMMAND_PROC1_RESET (1L<<16) 2995 #define BNX_RV2P_COMMAND_PROC2_RESET (1L<<17) 2996 #define BNX_RV2P_COMMAND_CTXIF_RESET (1L<<18) 2997 2998 #define BNX_RV2P_STATUS 0x00002804 2999 #define BNX_RV2P_STATUS_ALWAYS_0 (1L<<0) 3000 #define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3001 #define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3002 #define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3003 #define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3004 #define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3005 #define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3006 3007 #define BNX_RV2P_CONFIG 0x00002808 3008 #define BNX_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3009 #define BNX_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3010 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3011 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3012 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3013 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3014 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3015 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3016 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3017 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3018 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3019 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3020 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3021 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3022 #define BNX_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3023 #define BNX_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3024 #define BNX_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3025 #define BNX_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3026 #define BNX_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3027 #define BNX_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3028 #define BNX_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3029 #define BNX_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3030 #define BNX_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3031 #define BNX_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3032 #define BNX_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3033 #define BNX_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3034 #define BNX_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3035 #define BNX_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3036 3037 #define BNX_RV2P_GEN_BFR_ADDR_0 0x00002810 3038 #define BNX_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3039 3040 #define BNX_RV2P_GEN_BFR_ADDR_1 0x00002814 3041 #define BNX_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3042 3043 #define BNX_RV2P_GEN_BFR_ADDR_2 0x00002818 3044 #define BNX_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3045 3046 #define BNX_RV2P_GEN_BFR_ADDR_3 0x0000281c 3047 #define BNX_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3048 3049 #define BNX_RV2P_INSTR_HIGH 0x00002830 3050 #define BNX_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3051 3052 #define BNX_RV2P_INSTR_LOW 0x00002834 3053 #define BNX_RV2P_PROC1_ADDR_CMD 0x00002838 3054 #define BNX_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3055 #define BNX_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3056 3057 #define BNX_RV2P_PROC2_ADDR_CMD 0x0000283c 3058 #define BNX_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3059 #define BNX_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3060 3061 #define BNX_RV2P_PROC1_GRC_DEBUG 0x00002840 3062 #define BNX_RV2P_PROC2_GRC_DEBUG 0x00002844 3063 #define BNX_RV2P_GRC_PROC_DEBUG 0x00002848 3064 #define BNX_RV2P_DEBUG_VECT_PEEK 0x0000284c 3065 #define BNX_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3066 #define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3067 #define BNX_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3068 #define BNX_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3069 #define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3070 #define BNX_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3071 3072 #define BNX_RV2P_PFTQ_DATA 0x00002b40 3073 #define BNX_RV2P_PFTQ_CMD 0x00002b78 3074 #define BNX_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3075 #define BNX_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3076 #define BNX_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3077 #define BNX_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3078 #define BNX_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3079 #define BNX_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3080 #define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3081 #define BNX_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3082 #define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3083 #define BNX_RV2P_PFTQ_CMD_POP (1L<<30) 3084 #define BNX_RV2P_PFTQ_CMD_BUSY (1L<<31) 3085 3086 #define BNX_RV2P_PFTQ_CTL 0x00002b7c 3087 #define BNX_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3088 #define BNX_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3089 #define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3090 #define BNX_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3091 #define BNX_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3092 3093 #define BNX_RV2P_TFTQ_DATA 0x00002b80 3094 #define BNX_RV2P_TFTQ_CMD 0x00002bb8 3095 #define BNX_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3096 #define BNX_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3097 #define BNX_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3098 #define BNX_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3099 #define BNX_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3100 #define BNX_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3101 #define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3102 #define BNX_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3103 #define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3104 #define BNX_RV2P_TFTQ_CMD_POP (1L<<30) 3105 #define BNX_RV2P_TFTQ_CMD_BUSY (1L<<31) 3106 3107 #define BNX_RV2P_TFTQ_CTL 0x00002bbc 3108 #define BNX_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3109 #define BNX_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3110 #define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3111 #define BNX_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3112 #define BNX_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3113 3114 #define BNX_RV2P_MFTQ_DATA 0x00002bc0 3115 #define BNX_RV2P_MFTQ_CMD 0x00002bf8 3116 #define BNX_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3117 #define BNX_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3118 #define BNX_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3119 #define BNX_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3120 #define BNX_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3121 #define BNX_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3122 #define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3123 #define BNX_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3124 #define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3125 #define BNX_RV2P_MFTQ_CMD_POP (1L<<30) 3126 #define BNX_RV2P_MFTQ_CMD_BUSY (1L<<31) 3127 3128 #define BNX_RV2P_MFTQ_CTL 0x00002bfc 3129 #define BNX_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3130 #define BNX_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3131 #define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3132 #define BNX_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3133 #define BNX_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3134 3135 3136 3137 /* 3138 * mq_reg definition 3139 * offset: 0x3c00 3140 */ 3141 #define BNX_MQ_COMMAND 0x00003c00 3142 #define BNX_MQ_COMMAND_ENABLED (1L<<0) 3143 #define BNX_MQ_COMMAND_OVERFLOW (1L<<4) 3144 #define BNX_MQ_COMMAND_WR_ERROR (1L<<5) 3145 #define BNX_MQ_COMMAND_RD_ERROR (1L<<6) 3146 3147 #define BNX_MQ_STATUS 0x00003c04 3148 #define BNX_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3149 #define BNX_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3150 #define BNX_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3151 3152 #define BNX_MQ_CONFIG 0x00003c08 3153 #define BNX_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3154 #define BNX_MQ_CONFIG_HALT_DIS (1L<<1) 3155 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3156 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3157 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3158 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3159 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3160 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3161 #define BNX_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3162 #define BNX_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3163 3164 #define BNX_MQ_ENQUEUE1 0x00003c0c 3165 #define BNX_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3166 #define BNX_MQ_ENQUEUE1_CID (0x3fffL<<8) 3167 #define BNX_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3168 #define BNX_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3169 3170 #define BNX_MQ_ENQUEUE2 0x00003c10 3171 #define BNX_MQ_BAD_WR_ADDR 0x00003c14 3172 #define BNX_MQ_BAD_RD_ADDR 0x00003c18 3173 #define BNX_MQ_KNL_BYP_WIND_START 0x00003c1c 3174 #define BNX_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3175 3176 #define BNX_MQ_KNL_WIND_END 0x00003c20 3177 #define BNX_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3178 3179 #define BNX_MQ_KNL_WRITE_MASK1 0x00003c24 3180 #define BNX_MQ_KNL_TX_MASK1 0x00003c28 3181 #define BNX_MQ_KNL_CMD_MASK1 0x00003c2c 3182 #define BNX_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3183 #define BNX_MQ_KNL_RX_V2P_MASK1 0x00003c34 3184 #define BNX_MQ_KNL_WRITE_MASK2 0x00003c38 3185 #define BNX_MQ_KNL_TX_MASK2 0x00003c3c 3186 #define BNX_MQ_KNL_CMD_MASK2 0x00003c40 3187 #define BNX_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3188 #define BNX_MQ_KNL_RX_V2P_MASK2 0x00003c48 3189 #define BNX_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3190 #define BNX_MQ_KNL_BYP_TX_MASK1 0x00003c50 3191 #define BNX_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3192 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3193 #define BNX_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3194 #define BNX_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3195 #define BNX_MQ_KNL_BYP_TX_MASK2 0x00003c64 3196 #define BNX_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3197 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3198 #define BNX_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3199 #define BNX_MQ_MEM_WR_ADDR 0x00003c74 3200 #define BNX_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3201 3202 #define BNX_MQ_MEM_WR_DATA0 0x00003c78 3203 #define BNX_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3204 3205 #define BNX_MQ_MEM_WR_DATA1 0x00003c7c 3206 #define BNX_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3207 3208 #define BNX_MQ_MEM_WR_DATA2 0x00003c80 3209 #define BNX_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3210 3211 #define BNX_MQ_MEM_RD_ADDR 0x00003c84 3212 #define BNX_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3213 3214 #define BNX_MQ_MEM_RD_DATA0 0x00003c88 3215 #define BNX_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3216 3217 #define BNX_MQ_MEM_RD_DATA1 0x00003c8c 3218 #define BNX_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3219 3220 #define BNX_MQ_MEM_RD_DATA2 0x00003c90 3221 #define BNX_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3222 3223 3224 3225 /* 3226 * tbdr_reg definition 3227 * offset: 0x5000 3228 */ 3229 #define BNX_TBDR_COMMAND 0x00005000 3230 #define BNX_TBDR_COMMAND_ENABLE (1L<<0) 3231 #define BNX_TBDR_COMMAND_SOFT_RST (1L<<1) 3232 #define BNX_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3233 3234 #define BNX_TBDR_STATUS 0x00005004 3235 #define BNX_TBDR_STATUS_DMA_WAIT (1L<<0) 3236 #define BNX_TBDR_STATUS_FTQ_WAIT (1L<<1) 3237 #define BNX_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3238 #define BNX_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3239 #define BNX_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3240 #define BNX_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3241 #define BNX_TBDR_STATUS_BURST_CNT (1L<<6) 3242 3243 #define BNX_TBDR_CONFIG 0x00005008 3244 #define BNX_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3245 #define BNX_TBDR_CONFIG_SWAP_MODE (1L<<8) 3246 #define BNX_TBDR_CONFIG_PRIORITY (1L<<9) 3247 #define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3248 #define BNX_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3249 #define BNX_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3250 #define BNX_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3251 #define BNX_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3252 #define BNX_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3253 #define BNX_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3254 #define BNX_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3255 #define BNX_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3256 #define BNX_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3257 #define BNX_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3258 #define BNX_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3259 #define BNX_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3260 #define BNX_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3261 #define BNX_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3262 3263 #define BNX_TBDR_DEBUG_VECT_PEEK 0x0000500c 3264 #define BNX_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3265 #define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3266 #define BNX_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3267 #define BNX_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3268 #define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3269 #define BNX_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3270 3271 #define BNX_TBDR_FTQ_DATA 0x000053c0 3272 #define BNX_TBDR_FTQ_CMD 0x000053f8 3273 #define BNX_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 3274 #define BNX_TBDR_FTQ_CMD_WR_TOP (1L<<10) 3275 #define BNX_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 3276 #define BNX_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 3277 #define BNX_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 3278 #define BNX_TBDR_FTQ_CMD_RD_DATA (1L<<26) 3279 #define BNX_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 3280 #define BNX_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 3281 #define BNX_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 3282 #define BNX_TBDR_FTQ_CMD_POP (1L<<30) 3283 #define BNX_TBDR_FTQ_CMD_BUSY (1L<<31) 3284 3285 #define BNX_TBDR_FTQ_CTL 0x000053fc 3286 #define BNX_TBDR_FTQ_CTL_INTERVENE (1L<<0) 3287 #define BNX_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 3288 #define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3289 #define BNX_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3290 #define BNX_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3291 3292 3293 3294 /* 3295 * tdma_reg definition 3296 * offset: 0x5c00 3297 */ 3298 #define BNX_TDMA_COMMAND 0x00005c00 3299 #define BNX_TDMA_COMMAND_ENABLED (1L<<0) 3300 #define BNX_TDMA_COMMAND_MASTER_ABORT (1L<<4) 3301 #define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 3302 3303 #define BNX_TDMA_STATUS 0x00005c04 3304 #define BNX_TDMA_STATUS_DMA_WAIT (1L<<0) 3305 #define BNX_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 3306 #define BNX_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 3307 #define BNX_TDMA_STATUS_LOCK_WAIT (1L<<3) 3308 #define BNX_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 3309 #define BNX_TDMA_STATUS_BURST_CNT (1L<<17) 3310 3311 #define BNX_TDMA_CONFIG 0x00005c08 3312 #define BNX_TDMA_CONFIG_ONE_DMA (1L<<0) 3313 #define BNX_TDMA_CONFIG_ONE_RECORD (1L<<1) 3314 #define BNX_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 3315 #define BNX_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 3316 #define BNX_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 3317 #define BNX_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 3318 #define BNX_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 3319 #define BNX_TDMA_CONFIG_LINE_SZ (0xfL<<8) 3320 #define BNX_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 3321 #define BNX_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 3322 #define BNX_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 3323 #define BNX_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 3324 #define BNX_TDMA_CONFIG_ALIGN_ENA (1L<<15) 3325 #define BNX_TDMA_CONFIG_CHK_L2_BD (1L<<16) 3326 #define BNX_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 3327 3328 #define BNX_TDMA_PAYLOAD_PROD 0x00005c0c 3329 #define BNX_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 3330 3331 #define BNX_TDMA_DBG_WATCHDOG 0x00005c10 3332 #define BNX_TDMA_DBG_TRIGGER 0x00005c14 3333 #define BNX_TDMA_DMAD_FSM 0x00005c80 3334 #define BNX_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 3335 #define BNX_TDMA_DMAD_FSM_PUSH (0xfL<<4) 3336 #define BNX_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 3337 #define BNX_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 3338 #define BNX_TDMA_DMAD_FSM_DR_INTF (1L<<16) 3339 #define BNX_TDMA_DMAD_FSM_DMAD (0x7L<<20) 3340 #define BNX_TDMA_DMAD_FSM_BD (0xfL<<24) 3341 3342 #define BNX_TDMA_DMAD_STATUS 0x00005c84 3343 #define BNX_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 3344 #define BNX_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 3345 #define BNX_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 3346 #define BNX_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 3347 3348 #define BNX_TDMA_DR_INTF_FSM 0x00005c88 3349 #define BNX_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 3350 #define BNX_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 3351 #define BNX_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 3352 #define BNX_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 3353 #define BNX_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 3354 3355 #define BNX_TDMA_DR_INTF_STATUS 0x00005c8c 3356 #define BNX_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 3357 #define BNX_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 3358 #define BNX_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 3359 #define BNX_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 3360 #define BNX_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 3361 3362 #define BNX_TDMA_FTQ_DATA 0x00005fc0 3363 #define BNX_TDMA_FTQ_CMD 0x00005ff8 3364 #define BNX_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 3365 #define BNX_TDMA_FTQ_CMD_WR_TOP (1L<<10) 3366 #define BNX_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 3367 #define BNX_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 3368 #define BNX_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 3369 #define BNX_TDMA_FTQ_CMD_RD_DATA (1L<<26) 3370 #define BNX_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 3371 #define BNX_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 3372 #define BNX_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 3373 #define BNX_TDMA_FTQ_CMD_POP (1L<<30) 3374 #define BNX_TDMA_FTQ_CMD_BUSY (1L<<31) 3375 3376 #define BNX_TDMA_FTQ_CTL 0x00005ffc 3377 #define BNX_TDMA_FTQ_CTL_INTERVENE (1L<<0) 3378 #define BNX_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 3379 #define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3380 #define BNX_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3381 #define BNX_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3382 3383 3384 3385 /* 3386 * hc_reg definition 3387 * offset: 0x6800 3388 */ 3389 #define BNX_HC_COMMAND 0x00006800 3390 #define BNX_HC_COMMAND_ENABLE (1L<<0) 3391 #define BNX_HC_COMMAND_SKIP_ABORT (1L<<4) 3392 #define BNX_HC_COMMAND_COAL_NOW (1L<<16) 3393 #define BNX_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 3394 #define BNX_HC_COMMAND_STATS_NOW (1L<<18) 3395 #define BNX_HC_COMMAND_FORCE_INT (0x3L<<19) 3396 #define BNX_HC_COMMAND_FORCE_INT_NULL (0L<<19) 3397 #define BNX_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 3398 #define BNX_HC_COMMAND_FORCE_INT_LOW (2L<<19) 3399 #define BNX_HC_COMMAND_FORCE_INT_FREE (3L<<19) 3400 #define BNX_HC_COMMAND_CLR_STAT_NOW (1L<<21) 3401 3402 #define BNX_HC_STATUS 0x00006804 3403 #define BNX_HC_STATUS_MASTER_ABORT (1L<<0) 3404 #define BNX_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 3405 #define BNX_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 3406 #define BNX_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 3407 #define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 3408 #define BNX_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 3409 #define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 3410 #define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 3411 #define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 3412 #define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 3413 3414 #define BNX_HC_CONFIG 0x00006808 3415 #define BNX_HC_CONFIG_COLLECT_STATS (1L<<0) 3416 #define BNX_HC_CONFIG_RX_TMR_MODE (1L<<1) 3417 #define BNX_HC_CONFIG_TX_TMR_MODE (1L<<2) 3418 #define BNX_HC_CONFIG_COM_TMR_MODE (1L<<3) 3419 #define BNX_HC_CONFIG_CMD_TMR_MODE (1L<<4) 3420 #define BNX_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 3421 #define BNX_HC_CONFIG_STATUS_PRIORITY (1L<<6) 3422 #define BNX_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 3423 3424 #define BNX_HC_ATTN_BITS_ENABLE 0x0000680c 3425 #define BNX_HC_STATUS_ADDR_L 0x00006810 3426 #define BNX_HC_STATUS_ADDR_H 0x00006814 3427 #define BNX_HC_STATISTICS_ADDR_L 0x00006818 3428 #define BNX_HC_STATISTICS_ADDR_H 0x0000681c 3429 #define BNX_HC_TX_QUICK_CONS_TRIP 0x00006820 3430 #define BNX_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3431 #define BNX_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 3432 3433 #define BNX_HC_COMP_PROD_TRIP 0x00006824 3434 #define BNX_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 3435 #define BNX_HC_COMP_PROD_TRIP_INT (0xffL<<16) 3436 3437 #define BNX_HC_RX_QUICK_CONS_TRIP 0x00006828 3438 #define BNX_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3439 #define BNX_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 3440 3441 #define BNX_HC_RX_TICKS 0x0000682c 3442 #define BNX_HC_RX_TICKS_VALUE (0x3ffL<<0) 3443 #define BNX_HC_RX_TICKS_INT (0x3ffL<<16) 3444 3445 #define BNX_HC_TX_TICKS 0x00006830 3446 #define BNX_HC_TX_TICKS_VALUE (0x3ffL<<0) 3447 #define BNX_HC_TX_TICKS_INT (0x3ffL<<16) 3448 3449 #define BNX_HC_COM_TICKS 0x00006834 3450 #define BNX_HC_COM_TICKS_VALUE (0x3ffL<<0) 3451 #define BNX_HC_COM_TICKS_INT (0x3ffL<<16) 3452 3453 #define BNX_HC_CMD_TICKS 0x00006838 3454 #define BNX_HC_CMD_TICKS_VALUE (0x3ffL<<0) 3455 #define BNX_HC_CMD_TICKS_INT (0x3ffL<<16) 3456 3457 #define BNX_HC_PERIODIC_TICKS 0x0000683c 3458 #define BNX_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 3459 3460 #define BNX_HC_STAT_COLLECT_TICKS 0x00006840 3461 #define BNX_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 3462 3463 #define BNX_HC_STATS_TICKS 0x00006844 3464 #define BNX_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 3465 3466 #define BNX_HC_STAT_MEM_DATA 0x0000684c 3467 #define BNX_HC_STAT_GEN_SEL_0 0x00006850 3468 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 3469 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 3470 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 3471 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 3472 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 3473 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 3474 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 3475 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 3476 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 3477 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 3478 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 3479 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 3480 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 3481 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 3482 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 3483 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 3484 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 3485 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 3486 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 3487 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 3488 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 3489 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 3490 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 3491 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 3492 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 3493 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 3494 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 3495 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 3496 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 3497 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 3498 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 3499 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 3500 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 3501 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 3502 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 3503 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 3504 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 3505 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 3506 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 3507 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 3508 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 3509 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 3510 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 3511 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 3512 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 3513 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 3514 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 3515 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 3516 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 3517 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 3518 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 3519 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 3520 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 3521 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 3522 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 3523 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 3524 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 3525 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 3526 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 3527 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 3528 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 3529 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 3530 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 3531 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 3532 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 3533 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 3534 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 3535 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 3536 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 3537 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 3538 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 3539 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 3540 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 3541 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 3542 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 3543 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 3544 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 3545 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 3546 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 3547 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 3548 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 3549 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 3550 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 3551 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 3552 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 3553 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 3554 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 3555 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 3556 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 3557 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 3558 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 3559 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 3560 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 3561 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 3562 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 3563 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 3564 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 3565 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 3566 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 3567 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 3568 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 3569 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 3570 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 3571 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 3572 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 3573 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 3574 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 3575 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 3576 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 3577 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 3578 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 3579 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 3580 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 3581 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 3582 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 3583 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 3584 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 3585 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 3586 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 3587 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 3588 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 3589 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 3590 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 3591 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 3592 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 3593 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 3594 3595 #define BNX_HC_STAT_GEN_SEL_1 0x00006854 3596 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 3597 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 3598 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 3599 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 3600 3601 #define BNX_HC_STAT_GEN_SEL_2 0x00006858 3602 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 3603 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 3604 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 3605 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 3606 3607 #define BNX_HC_STAT_GEN_SEL_3 0x0000685c 3608 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 3609 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 3610 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 3611 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 3612 3613 #define BNX_HC_STAT_GEN_STAT0 0x00006888 3614 #define BNX_HC_STAT_GEN_STAT1 0x0000688c 3615 #define BNX_HC_STAT_GEN_STAT2 0x00006890 3616 #define BNX_HC_STAT_GEN_STAT3 0x00006894 3617 #define BNX_HC_STAT_GEN_STAT4 0x00006898 3618 #define BNX_HC_STAT_GEN_STAT5 0x0000689c 3619 #define BNX_HC_STAT_GEN_STAT6 0x000068a0 3620 #define BNX_HC_STAT_GEN_STAT7 0x000068a4 3621 #define BNX_HC_STAT_GEN_STAT8 0x000068a8 3622 #define BNX_HC_STAT_GEN_STAT9 0x000068ac 3623 #define BNX_HC_STAT_GEN_STAT10 0x000068b0 3624 #define BNX_HC_STAT_GEN_STAT11 0x000068b4 3625 #define BNX_HC_STAT_GEN_STAT12 0x000068b8 3626 #define BNX_HC_STAT_GEN_STAT13 0x000068bc 3627 #define BNX_HC_STAT_GEN_STAT14 0x000068c0 3628 #define BNX_HC_STAT_GEN_STAT15 0x000068c4 3629 #define BNX_HC_STAT_GEN_STAT_AC0 0x000068c8 3630 #define BNX_HC_STAT_GEN_STAT_AC1 0x000068cc 3631 #define BNX_HC_STAT_GEN_STAT_AC2 0x000068d0 3632 #define BNX_HC_STAT_GEN_STAT_AC3 0x000068d4 3633 #define BNX_HC_STAT_GEN_STAT_AC4 0x000068d8 3634 #define BNX_HC_STAT_GEN_STAT_AC5 0x000068dc 3635 #define BNX_HC_STAT_GEN_STAT_AC6 0x000068e0 3636 #define BNX_HC_STAT_GEN_STAT_AC7 0x000068e4 3637 #define BNX_HC_STAT_GEN_STAT_AC8 0x000068e8 3638 #define BNX_HC_STAT_GEN_STAT_AC9 0x000068ec 3639 #define BNX_HC_STAT_GEN_STAT_AC10 0x000068f0 3640 #define BNX_HC_STAT_GEN_STAT_AC11 0x000068f4 3641 #define BNX_HC_STAT_GEN_STAT_AC12 0x000068f8 3642 #define BNX_HC_STAT_GEN_STAT_AC13 0x000068fc 3643 #define BNX_HC_STAT_GEN_STAT_AC14 0x00006900 3644 #define BNX_HC_STAT_GEN_STAT_AC15 0x00006904 3645 #define BNX_HC_VIS 0x00006908 3646 #define BNX_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 3647 #define BNX_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 3648 #define BNX_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 3649 #define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 3650 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 3651 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 3652 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 3653 #define BNX_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 3654 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 3655 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 3656 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 3657 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 3658 #define BNX_HC_VIS_DMA_STAT_STATE (0xfL<<8) 3659 #define BNX_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 3660 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 3661 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 3662 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 3663 #define BNX_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 3664 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 3665 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 3666 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 3667 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 3668 #define BNX_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 3669 #define BNX_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 3670 #define BNX_HC_VIS_DMA_MSI_STATE (0x7L<<12) 3671 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 3672 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 3673 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 3674 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 3675 3676 #define BNX_HC_VIS_1 0x0000690c 3677 #define BNX_HC_VIS_1_HW_INTACK_STATE (1L<<4) 3678 #define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 3679 #define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 3680 #define BNX_HC_VIS_1_SW_INTACK_STATE (1L<<5) 3681 #define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 3682 #define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 3683 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 3684 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 3685 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 3686 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 3687 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 3688 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 3689 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 3690 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 3691 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 3692 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 3693 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 3694 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 3695 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 3696 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 3697 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 3698 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 3699 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 3700 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 3701 #define BNX_HC_VIS_1_INT_GEN_STATE (1L<<23) 3702 #define BNX_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 3703 #define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 3704 #define BNX_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 3705 #define BNX_HC_VIS_1_INT_B (1L<<27) 3706 3707 #define BNX_HC_DEBUG_VECT_PEEK 0x00006910 3708 #define BNX_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3709 #define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3710 #define BNX_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3711 #define BNX_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3712 #define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3713 #define BNX_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3714 3715 3716 3717 /* 3718 * txp_reg definition 3719 * offset: 0x40000 3720 */ 3721 #define BNX_TXP_CPU_MODE 0x00045000 3722 #define BNX_TXP_CPU_MODE_LOCAL_RST (1L<<0) 3723 #define BNX_TXP_CPU_MODE_STEP_ENA (1L<<1) 3724 #define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3725 #define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3726 #define BNX_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 3727 #define BNX_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3728 #define BNX_TXP_CPU_MODE_SOFT_HALT (1L<<10) 3729 #define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3730 #define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3731 #define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3732 #define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3733 3734 #define BNX_TXP_CPU_STATE 0x00045004 3735 #define BNX_TXP_CPU_STATE_BREAKPOINT (1L<<0) 3736 #define BNX_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3737 #define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3738 #define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3739 #define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3740 #define BNX_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3741 #define BNX_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3742 #define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3743 #define BNX_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 3744 #define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3745 #define BNX_TXP_CPU_STATE_INTERRRUPT (1L<<12) 3746 #define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3747 #define BNX_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3748 #define BNX_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 3749 3750 #define BNX_TXP_CPU_EVENT_MASK 0x00045008 3751 #define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3752 #define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3753 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3754 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3755 #define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3756 #define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3757 #define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3758 #define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3759 #define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3760 #define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3761 #define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3762 3763 #define BNX_TXP_CPU_PROGRAM_COUNTER 0x0004501c 3764 #define BNX_TXP_CPU_INSTRUCTION 0x00045020 3765 #define BNX_TXP_CPU_DATA_ACCESS 0x00045024 3766 #define BNX_TXP_CPU_INTERRUPT_ENABLE 0x00045028 3767 #define BNX_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 3768 #define BNX_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 3769 #define BNX_TXP_CPU_HW_BREAKPOINT 0x00045034 3770 #define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3771 #define BNX_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3772 3773 #define BNX_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 3774 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3775 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3776 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3777 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3778 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3779 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3780 3781 #define BNX_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 3782 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3783 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3784 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3785 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3786 3787 #define BNX_TXP_CPU_REG_FILE 0x00045200 3788 #define BNX_TXP_FTQ_DATA 0x000453c0 3789 #define BNX_TXP_FTQ_CMD 0x000453f8 3790 #define BNX_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 3791 #define BNX_TXP_FTQ_CMD_WR_TOP (1L<<10) 3792 #define BNX_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 3793 #define BNX_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 3794 #define BNX_TXP_FTQ_CMD_SFT_RESET (1L<<25) 3795 #define BNX_TXP_FTQ_CMD_RD_DATA (1L<<26) 3796 #define BNX_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 3797 #define BNX_TXP_FTQ_CMD_ADD_DATA (1L<<28) 3798 #define BNX_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 3799 #define BNX_TXP_FTQ_CMD_POP (1L<<30) 3800 #define BNX_TXP_FTQ_CMD_BUSY (1L<<31) 3801 3802 #define BNX_TXP_FTQ_CTL 0x000453fc 3803 #define BNX_TXP_FTQ_CTL_INTERVENE (1L<<0) 3804 #define BNX_TXP_FTQ_CTL_OVERFLOW (1L<<1) 3805 #define BNX_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3806 #define BNX_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3807 #define BNX_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3808 3809 #define BNX_TXP_SCRATCH 0x00060000 3810 3811 3812 /* 3813 * tpat_reg definition 3814 * offset: 0x80000 3815 */ 3816 #define BNX_TPAT_CPU_MODE 0x00085000 3817 #define BNX_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 3818 #define BNX_TPAT_CPU_MODE_STEP_ENA (1L<<1) 3819 #define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3820 #define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3821 #define BNX_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 3822 #define BNX_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 3823 #define BNX_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 3824 #define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3825 #define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3826 #define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3827 #define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3828 3829 #define BNX_TPAT_CPU_STATE 0x00085004 3830 #define BNX_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 3831 #define BNX_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 3832 #define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3833 #define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3834 #define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3835 #define BNX_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 3836 #define BNX_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 3837 #define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3838 #define BNX_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 3839 #define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3840 #define BNX_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 3841 #define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3842 #define BNX_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 3843 #define BNX_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 3844 3845 #define BNX_TPAT_CPU_EVENT_MASK 0x00085008 3846 #define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3847 #define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3848 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3849 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3850 #define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3851 #define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3852 #define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3853 #define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3854 #define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3855 #define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3856 #define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3857 3858 #define BNX_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 3859 #define BNX_TPAT_CPU_INSTRUCTION 0x00085020 3860 #define BNX_TPAT_CPU_DATA_ACCESS 0x00085024 3861 #define BNX_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 3862 #define BNX_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 3863 #define BNX_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 3864 #define BNX_TPAT_CPU_HW_BREAKPOINT 0x00085034 3865 #define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3866 #define BNX_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3867 3868 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 3869 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3870 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3871 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3872 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3873 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3874 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3875 3876 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 3877 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3878 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3879 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3880 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3881 3882 #define BNX_TPAT_CPU_REG_FILE 0x00085200 3883 #define BNX_TPAT_FTQ_DATA 0x000853c0 3884 #define BNX_TPAT_FTQ_CMD 0x000853f8 3885 #define BNX_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 3886 #define BNX_TPAT_FTQ_CMD_WR_TOP (1L<<10) 3887 #define BNX_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 3888 #define BNX_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 3889 #define BNX_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 3890 #define BNX_TPAT_FTQ_CMD_RD_DATA (1L<<26) 3891 #define BNX_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 3892 #define BNX_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 3893 #define BNX_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 3894 #define BNX_TPAT_FTQ_CMD_POP (1L<<30) 3895 #define BNX_TPAT_FTQ_CMD_BUSY (1L<<31) 3896 3897 #define BNX_TPAT_FTQ_CTL 0x000853fc 3898 #define BNX_TPAT_FTQ_CTL_INTERVENE (1L<<0) 3899 #define BNX_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 3900 #define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3901 #define BNX_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3902 #define BNX_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3903 3904 #define BNX_TPAT_SCRATCH 0x000a0000 3905 3906 3907 /* 3908 * rxp_reg definition 3909 * offset: 0xc0000 3910 */ 3911 #define BNX_RXP_CPU_MODE 0x000c5000 3912 #define BNX_RXP_CPU_MODE_LOCAL_RST (1L<<0) 3913 #define BNX_RXP_CPU_MODE_STEP_ENA (1L<<1) 3914 #define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3915 #define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3916 #define BNX_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 3917 #define BNX_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3918 #define BNX_RXP_CPU_MODE_SOFT_HALT (1L<<10) 3919 #define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3920 #define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3921 #define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3922 #define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3923 3924 #define BNX_RXP_CPU_STATE 0x000c5004 3925 #define BNX_RXP_CPU_STATE_BREAKPOINT (1L<<0) 3926 #define BNX_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3927 #define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3928 #define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3929 #define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3930 #define BNX_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3931 #define BNX_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3932 #define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3933 #define BNX_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 3934 #define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3935 #define BNX_RXP_CPU_STATE_INTERRRUPT (1L<<12) 3936 #define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3937 #define BNX_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3938 #define BNX_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 3939 3940 #define BNX_RXP_CPU_EVENT_MASK 0x000c5008 3941 #define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3942 #define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3943 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3944 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3945 #define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3946 #define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3947 #define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3948 #define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3949 #define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3950 #define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3951 #define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3952 3953 #define BNX_RXP_CPU_PROGRAM_COUNTER 0x000c501c 3954 #define BNX_RXP_CPU_INSTRUCTION 0x000c5020 3955 #define BNX_RXP_CPU_DATA_ACCESS 0x000c5024 3956 #define BNX_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 3957 #define BNX_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 3958 #define BNX_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 3959 #define BNX_RXP_CPU_HW_BREAKPOINT 0x000c5034 3960 #define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3961 #define BNX_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3962 3963 #define BNX_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 3964 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3965 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3966 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3967 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3968 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3969 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3970 3971 #define BNX_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 3972 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3973 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3974 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3975 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3976 3977 #define BNX_RXP_CPU_REG_FILE 0x000c5200 3978 #define BNX_RXP_CFTQ_DATA 0x000c5380 3979 #define BNX_RXP_CFTQ_CMD 0x000c53b8 3980 #define BNX_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 3981 #define BNX_RXP_CFTQ_CMD_WR_TOP (1L<<10) 3982 #define BNX_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 3983 #define BNX_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 3984 #define BNX_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 3985 #define BNX_RXP_CFTQ_CMD_RD_DATA (1L<<26) 3986 #define BNX_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 3987 #define BNX_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 3988 #define BNX_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 3989 #define BNX_RXP_CFTQ_CMD_POP (1L<<30) 3990 #define BNX_RXP_CFTQ_CMD_BUSY (1L<<31) 3991 3992 #define BNX_RXP_CFTQ_CTL 0x000c53bc 3993 #define BNX_RXP_CFTQ_CTL_INTERVENE (1L<<0) 3994 #define BNX_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 3995 #define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 3996 #define BNX_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3997 #define BNX_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3998 3999 #define BNX_RXP_FTQ_DATA 0x000c53c0 4000 #define BNX_RXP_FTQ_CMD 0x000c53f8 4001 #define BNX_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4002 #define BNX_RXP_FTQ_CMD_WR_TOP (1L<<10) 4003 #define BNX_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4004 #define BNX_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4005 #define BNX_RXP_FTQ_CMD_SFT_RESET (1L<<25) 4006 #define BNX_RXP_FTQ_CMD_RD_DATA (1L<<26) 4007 #define BNX_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4008 #define BNX_RXP_FTQ_CMD_ADD_DATA (1L<<28) 4009 #define BNX_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4010 #define BNX_RXP_FTQ_CMD_POP (1L<<30) 4011 #define BNX_RXP_FTQ_CMD_BUSY (1L<<31) 4012 4013 #define BNX_RXP_FTQ_CTL 0x000c53fc 4014 #define BNX_RXP_FTQ_CTL_INTERVENE (1L<<0) 4015 #define BNX_RXP_FTQ_CTL_OVERFLOW (1L<<1) 4016 #define BNX_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4017 #define BNX_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4018 #define BNX_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4019 4020 #define BNX_RXP_SCRATCH 0x000e0000 4021 4022 4023 /* 4024 * com_reg definition 4025 * offset: 0x100000 4026 */ 4027 #define BNX_COM_CPU_MODE 0x00105000 4028 #define BNX_COM_CPU_MODE_LOCAL_RST (1L<<0) 4029 #define BNX_COM_CPU_MODE_STEP_ENA (1L<<1) 4030 #define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4031 #define BNX_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4032 #define BNX_COM_CPU_MODE_MSG_BIT1 (1L<<6) 4033 #define BNX_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 4034 #define BNX_COM_CPU_MODE_SOFT_HALT (1L<<10) 4035 #define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4036 #define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4037 #define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4038 #define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4039 4040 #define BNX_COM_CPU_STATE 0x00105004 4041 #define BNX_COM_CPU_STATE_BREAKPOINT (1L<<0) 4042 #define BNX_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 4043 #define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4044 #define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4045 #define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4046 #define BNX_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 4047 #define BNX_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 4048 #define BNX_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4049 #define BNX_COM_CPU_STATE_SOFT_HALTED (1L<<10) 4050 #define BNX_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4051 #define BNX_COM_CPU_STATE_INTERRRUPT (1L<<12) 4052 #define BNX_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4053 #define BNX_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 4054 #define BNX_COM_CPU_STATE_BLOCKED_READ (1L<<31) 4055 4056 #define BNX_COM_CPU_EVENT_MASK 0x00105008 4057 #define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4058 #define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4059 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4060 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4061 #define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4062 #define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4063 #define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4064 #define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4065 #define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4066 #define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4067 #define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4068 4069 #define BNX_COM_CPU_PROGRAM_COUNTER 0x0010501c 4070 #define BNX_COM_CPU_INSTRUCTION 0x00105020 4071 #define BNX_COM_CPU_DATA_ACCESS 0x00105024 4072 #define BNX_COM_CPU_INTERRUPT_ENABLE 0x00105028 4073 #define BNX_COM_CPU_INTERRUPT_VECTOR 0x0010502c 4074 #define BNX_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 4075 #define BNX_COM_CPU_HW_BREAKPOINT 0x00105034 4076 #define BNX_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4077 #define BNX_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4078 4079 #define BNX_COM_CPU_DEBUG_VECT_PEEK 0x00105038 4080 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4081 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4082 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4083 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4084 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4085 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4086 4087 #define BNX_COM_CPU_LAST_BRANCH_ADDR 0x00105048 4088 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4089 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4090 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4091 #define BNX_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4092 4093 #define BNX_COM_CPU_REG_FILE 0x00105200 4094 #define BNX_COM_COMXQ_FTQ_DATA 0x00105340 4095 #define BNX_COM_COMXQ_FTQ_CMD 0x00105378 4096 #define BNX_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4097 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 4098 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4099 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4100 #define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 4101 #define BNX_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 4102 #define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4103 #define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 4104 #define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4105 #define BNX_COM_COMXQ_FTQ_CMD_POP (1L<<30) 4106 #define BNX_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 4107 4108 #define BNX_COM_COMXQ_FTQ_CTL 0x0010537c 4109 #define BNX_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 4110 #define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 4111 #define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4112 #define BNX_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4113 #define BNX_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4114 4115 #define BNX_COM_COMTQ_FTQ_DATA 0x00105380 4116 #define BNX_COM_COMTQ_FTQ_CMD 0x001053b8 4117 #define BNX_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4118 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 4119 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4120 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4121 #define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 4122 #define BNX_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 4123 #define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4124 #define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 4125 #define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4126 #define BNX_COM_COMTQ_FTQ_CMD_POP (1L<<30) 4127 #define BNX_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 4128 4129 #define BNX_COM_COMTQ_FTQ_CTL 0x001053bc 4130 #define BNX_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 4131 #define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 4132 #define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4133 #define BNX_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4134 #define BNX_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4135 4136 #define BNX_COM_COMQ_FTQ_DATA 0x001053c0 4137 #define BNX_COM_COMQ_FTQ_CMD 0x001053f8 4138 #define BNX_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4139 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 4140 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4141 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4142 #define BNX_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 4143 #define BNX_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 4144 #define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4145 #define BNX_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 4146 #define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4147 #define BNX_COM_COMQ_FTQ_CMD_POP (1L<<30) 4148 #define BNX_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 4149 4150 #define BNX_COM_COMQ_FTQ_CTL 0x001053fc 4151 #define BNX_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 4152 #define BNX_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 4153 #define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4154 #define BNX_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4155 #define BNX_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4156 4157 #define BNX_COM_SCRATCH 0x00120000 4158 4159 4160 /* 4161 * cp_reg definition 4162 * offset: 0x180000 4163 */ 4164 #define BNX_CP_CPU_MODE 0x00185000 4165 #define BNX_CP_CPU_MODE_LOCAL_RST (1L<<0) 4166 #define BNX_CP_CPU_MODE_STEP_ENA (1L<<1) 4167 #define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4168 #define BNX_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4169 #define BNX_CP_CPU_MODE_MSG_BIT1 (1L<<6) 4170 #define BNX_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4171 #define BNX_CP_CPU_MODE_SOFT_HALT (1L<<10) 4172 #define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4173 #define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4174 #define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4175 #define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4176 4177 #define BNX_CP_CPU_STATE 0x00185004 4178 #define BNX_CP_CPU_STATE_BREAKPOINT (1L<<0) 4179 #define BNX_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4180 #define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4181 #define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4182 #define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4183 #define BNX_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4184 #define BNX_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 4185 #define BNX_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4186 #define BNX_CP_CPU_STATE_SOFT_HALTED (1L<<10) 4187 #define BNX_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4188 #define BNX_CP_CPU_STATE_INTERRRUPT (1L<<12) 4189 #define BNX_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4190 #define BNX_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4191 #define BNX_CP_CPU_STATE_BLOCKED_READ (1L<<31) 4192 4193 #define BNX_CP_CPU_EVENT_MASK 0x00185008 4194 #define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4195 #define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4196 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4197 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4198 #define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4199 #define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4200 #define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4201 #define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4202 #define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4203 #define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4204 #define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4205 4206 #define BNX_CP_CPU_PROGRAM_COUNTER 0x0018501c 4207 #define BNX_CP_CPU_INSTRUCTION 0x00185020 4208 #define BNX_CP_CPU_DATA_ACCESS 0x00185024 4209 #define BNX_CP_CPU_INTERRUPT_ENABLE 0x00185028 4210 #define BNX_CP_CPU_INTERRUPT_VECTOR 0x0018502c 4211 #define BNX_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 4212 #define BNX_CP_CPU_HW_BREAKPOINT 0x00185034 4213 #define BNX_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4214 #define BNX_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4215 4216 #define BNX_CP_CPU_DEBUG_VECT_PEEK 0x00185038 4217 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4218 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4219 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4220 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4221 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4222 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4223 4224 #define BNX_CP_CPU_LAST_BRANCH_ADDR 0x00185048 4225 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4226 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4227 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4228 #define BNX_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4229 4230 #define BNX_CP_CPU_REG_FILE 0x00185200 4231 #define BNX_CP_CPQ_FTQ_DATA 0x001853c0 4232 #define BNX_CP_CPQ_FTQ_CMD 0x001853f8 4233 #define BNX_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4234 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 4235 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4236 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4237 #define BNX_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 4238 #define BNX_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 4239 #define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4240 #define BNX_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 4241 #define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4242 #define BNX_CP_CPQ_FTQ_CMD_POP (1L<<30) 4243 #define BNX_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 4244 4245 #define BNX_CP_CPQ_FTQ_CTL 0x001853fc 4246 #define BNX_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 4247 #define BNX_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 4248 #define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4249 #define BNX_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4250 #define BNX_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4251 4252 #define BNX_CP_SCRATCH 0x001a0000 4253 4254 4255 /* 4256 * mcp_reg definition 4257 * offset: 0x140000 4258 */ 4259 #define BNX_MCP_CPU_MODE 0x00145000 4260 #define BNX_MCP_CPU_MODE_LOCAL_RST (1L<<0) 4261 #define BNX_MCP_CPU_MODE_STEP_ENA (1L<<1) 4262 #define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4263 #define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4264 #define BNX_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 4265 #define BNX_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4266 #define BNX_MCP_CPU_MODE_SOFT_HALT (1L<<10) 4267 #define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4268 #define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4269 #define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4270 #define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4271 4272 #define BNX_MCP_CPU_STATE 0x00145004 4273 #define BNX_MCP_CPU_STATE_BREAKPOINT (1L<<0) 4274 #define BNX_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4275 #define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4276 #define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4277 #define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4278 #define BNX_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4279 #define BNX_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 4280 #define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4281 #define BNX_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 4282 #define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4283 #define BNX_MCP_CPU_STATE_INTERRRUPT (1L<<12) 4284 #define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4285 #define BNX_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4286 #define BNX_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 4287 4288 #define BNX_MCP_CPU_EVENT_MASK 0x00145008 4289 #define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4290 #define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4291 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4292 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4293 #define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4294 #define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4295 #define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4296 #define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4297 #define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4298 #define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4299 #define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4300 4301 #define BNX_MCP_CPU_PROGRAM_COUNTER 0x0014501c 4302 #define BNX_MCP_CPU_INSTRUCTION 0x00145020 4303 #define BNX_MCP_CPU_DATA_ACCESS 0x00145024 4304 #define BNX_MCP_CPU_INTERRUPT_ENABLE 0x00145028 4305 #define BNX_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 4306 #define BNX_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 4307 #define BNX_MCP_CPU_HW_BREAKPOINT 0x00145034 4308 #define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4309 #define BNX_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4310 4311 #define BNX_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 4312 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4313 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4314 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4315 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4316 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4317 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4318 4319 #define BNX_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 4320 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4321 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4322 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4323 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4324 4325 #define BNX_MCP_CPU_REG_FILE 0x00145200 4326 #define BNX_MCP_MCPQ_FTQ_DATA 0x001453c0 4327 #define BNX_MCP_MCPQ_FTQ_CMD 0x001453f8 4328 #define BNX_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4329 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 4330 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4331 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4332 #define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 4333 #define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 4334 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4335 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 4336 #define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4337 #define BNX_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 4338 #define BNX_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 4339 4340 #define BNX_MCP_MCPQ_FTQ_CTL 0x001453fc 4341 #define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 4342 #define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 4343 #define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4344 #define BNX_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4345 #define BNX_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4346 4347 #define BNX_MCP_ROM 0x00150000 4348 #define BNX_MCP_SCRATCH 0x00160000 4349 4350 #define BNX_SHM_HDR_SIGNATURE BNX_MCP_SCRATCH 4351 #define BNX_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 4352 #define BNX_SHM_HDR_SIGNATURE_SIG 0x53530000 4353 #define BNX_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 4354 #define BNX_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 4355 4356 #define BNX_SHM_HDR_ADDR_0 BNX_MCP_SCRATCH + 4 4357 #define BNX_SHM_HDR_ADDR_1 BNX_MCP_SCRATCH + 8 4358 4359 /****************************************************************************/ 4360 /* End machine generated definitions. */ 4361 /****************************************************************************/ 4362 4363 #define NUM_MC_HASH_REGISTERS 8 4364 4365 4366 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 4367 #define PHY_BCM5706_PHY_ID 0x00206160 4368 4369 #define PHY_ID(id) ((id) & 0xfffffff0) 4370 #define PHY_REV_ID(id) ((id) & 0xf) 4371 4372 /* 5708 Serdes PHY registers */ 4373 4374 #define BCM5708S_UP1 0xb 4375 4376 #define BCM5708S_UP1_2G5 0x1 4377 4378 #define BCM5708S_BLK_ADDR 0x1f 4379 4380 #define BCM5708S_BLK_ADDR_DIG 0x0000 4381 #define BCM5708S_BLK_ADDR_DIG3 0x0002 4382 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005 4383 4384 /* Digital Block */ 4385 #define BCM5708S_1000X_CTL1 0x10 4386 4387 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 4388 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 4389 4390 #define BCM5708S_1000X_CTL2 0x11 4391 4392 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 4393 4394 #define BCM5708S_1000X_STAT1 0x14 4395 4396 #define BCM5708S_1000X_STAT1_SGMII 0x0001 4397 #define BCM5708S_1000X_STAT1_LINK 0x0002 4398 #define BCM5708S_1000X_STAT1_FD 0x0004 4399 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 4400 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000 4401 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008 4402 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 4403 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 4404 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 4405 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 4406 4407 /* Digital3 Block */ 4408 #define BCM5708S_DIG_3_0 0x10 4409 4410 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001 4411 4412 /* Tx/Misc Block */ 4413 #define BCM5708S_TX_ACTL1 0x15 4414 4415 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 4416 4417 #define BCM5708S_TX_ACTL3 0x17 4418 4419 #define RX_COPY_THRESH 92 4420 4421 #define DMA_READ_CHANS 5 4422 #define DMA_WRITE_CHANS 3 4423 4424 /* Use the natural page size of the host CPU. */ 4425 /* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ 4426 #define BCM_PAGE_BITS PAGE_SHIFT 4427 #define BCM_PAGE_SIZE PAGE_SIZE 4428 4429 #define TX_PAGES 2 4430 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 4431 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 4432 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) 4433 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) 4434 #define MAX_TX_BD (TOTAL_TX_BD - 1) 4435 #define BNX_TX_SLACK_SPACE 16 4436 4437 #define RX_PAGES 2 4438 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4439 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 4440 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) 4441 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) 4442 #define MAX_RX_BD (TOTAL_RX_BD - 1) 4443 #define BNX_RX_SLACK_SPACE (MAX_RX_BD - 8) 4444 4445 #define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 4446 (USABLE_TX_BD_PER_PAGE - 1)) ? \ 4447 (x) + 2 : (x) + 1 4448 4449 #define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) 4450 4451 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) 4452 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 4453 4454 #define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 4455 (USABLE_RX_BD_PER_PAGE - 1)) ? \ 4456 (x) + 2 : (x) + 1 4457 4458 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) 4459 4460 #define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8) 4461 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 4462 4463 /* Context size. */ 4464 #define CTX_SHIFT 7 4465 #define CTX_SIZE (1 << CTX_SHIFT) 4466 #define CTX_MASK (CTX_SIZE - 1) 4467 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 4468 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 4469 4470 #define PHY_CTX_SHIFT 6 4471 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 4472 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 4473 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 4474 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 4475 4476 #define MB_KERNEL_CTX_SHIFT 8 4477 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 4478 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 4479 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 4480 4481 #define MAX_CID_CNT 0x4000 4482 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 4483 #define INVALID_CID_ADDR 0xffffffff 4484 4485 #define TX_CID 16 4486 #define RX_CID 0 4487 4488 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 4489 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 4490 4491 /****************************************************************************/ 4492 /* BNX Processor Firmwware Load Definitions */ 4493 /****************************************************************************/ 4494 4495 struct cpu_reg { 4496 u_int32_t mode; 4497 u_int32_t mode_value_halt; 4498 u_int32_t mode_value_sstep; 4499 4500 u_int32_t state; 4501 u_int32_t state_value_clear; 4502 4503 u_int32_t gpr0; 4504 u_int32_t evmask; 4505 u_int32_t pc; 4506 u_int32_t inst; 4507 u_int32_t bp; 4508 4509 u_int32_t spad_base; 4510 4511 u_int32_t mips_view_base; 4512 }; 4513 4514 struct fw_info { 4515 u_int32_t ver_major; 4516 u_int32_t ver_minor; 4517 u_int32_t ver_fix; 4518 4519 u_int32_t start_addr; 4520 4521 /* Text section. */ 4522 u_int32_t text_addr; 4523 u_int32_t text_len; 4524 u_int32_t text_index; 4525 u_int32_t *text; 4526 4527 /* Data section. */ 4528 u_int32_t data_addr; 4529 u_int32_t data_len; 4530 u_int32_t data_index; 4531 u_int32_t *data; 4532 4533 /* SBSS section. */ 4534 u_int32_t sbss_addr; 4535 u_int32_t sbss_len; 4536 u_int32_t sbss_index; 4537 u_int32_t *sbss; 4538 4539 /* BSS section. */ 4540 u_int32_t bss_addr; 4541 u_int32_t bss_len; 4542 u_int32_t bss_index; 4543 u_int32_t *bss; 4544 4545 /* Read-only section. */ 4546 u_int32_t rodata_addr; 4547 u_int32_t rodata_len; 4548 u_int32_t rodata_index; 4549 u_int32_t *rodata; 4550 }; 4551 4552 #define RV2P_PROC1 0 4553 #define RV2P_PROC2 1 4554 4555 #define BNX_MIREG(x) ((x & 0x1F) << 16) 4556 #define BNX_MIPHY(x) ((x & 0x1F) << 21) 4557 #define BNX_PHY_TIMEOUT 50 4558 4559 #define BNX_NVRAM_SIZE 0x200 4560 #define BNX_NVRAM_MAGIC 0x669955aa 4561 #define BNX_CRC32_RESIDUAL 0xdebb20e3 4562 4563 #define BNX_TX_TIMEOUT 5 4564 4565 #define BNX_MAX_SEGMENTS 8 4566 #define BNX_DMA_ALIGN 8 4567 #define BNX_DMA_BOUNDARY 0 4568 4569 #define BNX_MIN_MTU 60 4570 #define BNX_MIN_ETHER_MTU 64 4571 4572 #define BNX_MAX_STD_MTU 1500 4573 #define BNX_MAX_STD_ETHER_MTU 1518 4574 #define BNX_MAX_STD_ETHER_MTU_VLAN 1522 4575 4576 #define BNX_MAX_JUMBO_MTU 9000 4577 #define BNX_MAX_JUMBO_ETHER_MTU 9018 4578 #define BNX_MAX_JUMBO_ETHER_MTU_VLAN 9022 4579 4580 #define BNX_MAX_MRU 9216 4581 4582 /****************************************************************************/ 4583 /* BNX Device State Data Structure */ 4584 /****************************************************************************/ 4585 4586 #define BNX_STATUS_BLK_SZ sizeof(struct status_block) 4587 #define BNX_STATS_BLK_SZ sizeof(struct statistics_block) 4588 #define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4589 #define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4590 4591 struct bnx_softc 4592 { 4593 device_t bnx_dev; 4594 struct ethercom bnx_ec; 4595 struct pci_attach_args bnx_pa; 4596 4597 struct ifmedia bnx_ifmedia; /* TBI media info */ 4598 4599 bus_space_tag_t bnx_btag; /* Device bus tag */ 4600 bus_space_handle_t bnx_bhandle; /* Device bus handle */ 4601 bus_size_t bnx_size; 4602 4603 void *bnx_intrhand; /* Interrupt handler */ 4604 void *bnx_powerhook; 4605 void *bnx_shutdownhook; 4606 4607 /* ASIC Chip ID. */ 4608 u_int32_t bnx_chipid; 4609 4610 /* General controller flags. */ 4611 u_int32_t bnx_flags; 4612 #define BNX_PCIX_FLAG 0x01 4613 #define BNX_PCI_32BIT_FLAG 0x02 4614 #define BNX_ONE_TDMA_FLAG 0x04 /* Deprecated */ 4615 #define BNX_NO_WOL_FLAG 0x08 4616 #define BNX_USING_DAC_FLAG 0x10 4617 #define BNX_USING_MSI_FLAG 0x20 4618 #define BNX_MFW_ENABLE_FLAG 0x40 4619 4620 /* PHY specific flags. */ 4621 u_int32_t bnx_phy_flags; 4622 #define BNX_PHY_SERDES_FLAG 1 4623 #define BNX_PHY_CRC_FIX_FLAG 2 4624 #define BNX_PHY_PARALLEL_DETECT_FLAG 4 4625 #define BNX_PHY_2_5G_CAPABLE_FLAG 8 4626 #define BNX_PHY_INT_MODE_MASK_FLAG 0x300 4627 #define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 4628 #define BNX_PHY_INT_MODE_LINK_READY_FLAG 0x200 4629 4630 int bnx_if_flags; 4631 4632 u_int16_t bus_speed_mhz; /* PCI bus speed */ 4633 struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ 4634 u_int32_t bnx_flash_size; /* Flash NVRAM size */ 4635 u_int32_t bnx_shmem_base; /* Shared Memory base address */ 4636 char * bnx_name; /* Name string */ 4637 4638 /* Tracks the version of bootcode firmware. */ 4639 u_int32_t bnx_fw_ver; 4640 4641 /* Tracks the state of the firmware. 0 = Running while any */ 4642 /* other value indicates that the firmware is not responding. */ 4643 u_int16_t bnx_fw_timed_out; 4644 4645 /* An incrementing sequence used to coordinate messages passed */ 4646 /* from the driver to the firmware. */ 4647 u_int16_t bnx_fw_wr_seq; 4648 4649 /* An incrementing sequence used to let the firmware know that */ 4650 /* the driver is still operating. Without the pulse, management */ 4651 /* firmware such as IPMI or UMP will operate in OS absent state. */ 4652 u_int16_t bnx_fw_drv_pulse_wr_seq; 4653 4654 /* Ethernet MAC address. */ 4655 u_char eaddr[6]; 4656 4657 /* These setting are used by the host coalescing (HC) block to */ 4658 /* to control how often the status block, statistics block and */ 4659 /* interrupts are generated. */ 4660 u_int16_t bnx_tx_quick_cons_trip_int; 4661 u_int16_t bnx_tx_quick_cons_trip; 4662 u_int16_t bnx_rx_quick_cons_trip_int; 4663 u_int16_t bnx_rx_quick_cons_trip; 4664 u_int16_t bnx_comp_prod_trip_int; 4665 u_int16_t bnx_comp_prod_trip; 4666 u_int16_t bnx_tx_ticks_int; 4667 u_int16_t bnx_tx_ticks; 4668 u_int16_t bnx_rx_ticks_int; 4669 u_int16_t bnx_rx_ticks; 4670 u_int16_t bnx_com_ticks_int; 4671 u_int16_t bnx_com_ticks; 4672 u_int16_t bnx_cmd_ticks_int; 4673 u_int16_t bnx_cmd_ticks; 4674 u_int32_t bnx_stats_ticks; 4675 4676 /* The address of the integrated PHY on the MII bus. */ 4677 int bnx_phy_addr; 4678 4679 /* The device handle for the MII bus child device. */ 4680 struct mii_data bnx_mii; 4681 4682 /* Driver maintained TX chain pointers and byte counter. */ 4683 u_int16_t rx_prod; 4684 u_int16_t rx_cons; 4685 u_int32_t rx_prod_bseq; /* Counts the bytes used. */ 4686 u_int16_t tx_prod; 4687 u_int16_t tx_cons; 4688 u_int32_t tx_prod_bseq; /* Counts the bytes used. */ 4689 4690 struct callout bnx_timeout; 4691 4692 /* Frame size and mbuf allocation size for RX frames. */ 4693 u_int32_t max_frame_size; 4694 int mbuf_alloc_size; 4695 4696 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 4697 u_int32_t rx_mode; 4698 4699 /* Bus tag for the bnx controller. */ 4700 bus_dma_tag_t bnx_dmatag; 4701 4702 /* H/W maintained TX buffer descriptor chain structure. */ 4703 bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; 4704 int tx_bd_chain_rseg[TX_PAGES]; 4705 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 4706 struct tx_bd *tx_bd_chain[TX_PAGES]; 4707 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 4708 4709 /* H/W maintained RX buffer descriptor chain structure. */ 4710 bus_dma_segment_t rx_bd_chain_seg[TX_PAGES]; 4711 int rx_bd_chain_rseg[TX_PAGES]; 4712 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 4713 struct rx_bd *rx_bd_chain[RX_PAGES]; 4714 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 4715 4716 /* H/W maintained status block. */ 4717 bus_dma_segment_t status_seg; 4718 int status_rseg; 4719 bus_dmamap_t status_map; 4720 struct status_block *status_block; /* virtual address */ 4721 bus_addr_t status_block_paddr; /* Physical address */ 4722 4723 /* Driver maintained status block values. */ 4724 u_int16_t last_status_idx; 4725 u_int16_t hw_rx_cons; 4726 u_int16_t hw_tx_cons; 4727 4728 /* H/W maintained statistics block. */ 4729 bus_dma_segment_t stats_seg; 4730 int stats_rseg; 4731 bus_dmamap_t stats_map; 4732 struct statistics_block *stats_block; /* Virtual address */ 4733 bus_addr_t stats_block_paddr; /* Physical address */ 4734 4735 /* Bus tag for RX/TX mbufs. */ 4736 bus_dma_segment_t rx_mbuf_seg; 4737 int rx_mbuf_rseg; 4738 bus_dma_segment_t tx_mbuf_seg; 4739 int tx_mbuf_rseg; 4740 4741 /* S/W maintained mbuf TX chain structure. */ 4742 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; 4743 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; 4744 4745 /* S/W maintained mbuf RX chain structure. */ 4746 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 4747 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 4748 4749 /* Track the number of rx_bd and tx_bd's in use. */ 4750 u_int16_t free_rx_bd; 4751 u_int16_t used_tx_bd; 4752 4753 /* Provides access to hardware statistics through sysctl. */ 4754 u_int64_t stat_IfHCInOctets; 4755 u_int64_t stat_IfHCInBadOctets; 4756 u_int64_t stat_IfHCOutOctets; 4757 u_int64_t stat_IfHCOutBadOctets; 4758 u_int64_t stat_IfHCInUcastPkts; 4759 u_int64_t stat_IfHCInMulticastPkts; 4760 u_int64_t stat_IfHCInBroadcastPkts; 4761 u_int64_t stat_IfHCOutUcastPkts; 4762 u_int64_t stat_IfHCOutMulticastPkts; 4763 u_int64_t stat_IfHCOutBroadcastPkts; 4764 4765 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4766 u_int32_t stat_Dot3StatsCarrierSenseErrors; 4767 u_int32_t stat_Dot3StatsFCSErrors; 4768 u_int32_t stat_Dot3StatsAlignmentErrors; 4769 u_int32_t stat_Dot3StatsSingleCollisionFrames; 4770 u_int32_t stat_Dot3StatsMultipleCollisionFrames; 4771 u_int32_t stat_Dot3StatsDeferredTransmissions; 4772 u_int32_t stat_Dot3StatsExcessiveCollisions; 4773 u_int32_t stat_Dot3StatsLateCollisions; 4774 u_int32_t stat_EtherStatsCollisions; 4775 u_int32_t stat_EtherStatsFragments; 4776 u_int32_t stat_EtherStatsJabbers; 4777 u_int32_t stat_EtherStatsUndersizePkts; 4778 u_int32_t stat_EtherStatsOverrsizePkts; 4779 u_int32_t stat_EtherStatsPktsRx64Octets; 4780 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; 4781 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; 4782 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; 4783 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 4784 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 4785 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 4786 u_int32_t stat_EtherStatsPktsTx64Octets; 4787 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; 4788 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; 4789 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; 4790 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 4791 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 4792 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 4793 u_int32_t stat_XonPauseFramesReceived; 4794 u_int32_t stat_XoffPauseFramesReceived; 4795 u_int32_t stat_OutXonSent; 4796 u_int32_t stat_OutXoffSent; 4797 u_int32_t stat_FlowControlDone; 4798 u_int32_t stat_MacControlFramesReceived; 4799 u_int32_t stat_XoffStateEntered; 4800 u_int32_t stat_IfInFramesL2FilterDiscards; 4801 u_int32_t stat_IfInRuleCheckerDiscards; 4802 u_int32_t stat_IfInFTQDiscards; 4803 u_int32_t stat_IfInMBUFDiscards; 4804 u_int32_t stat_IfInRuleCheckerP4Hit; 4805 u_int32_t stat_CatchupInRuleCheckerDiscards; 4806 u_int32_t stat_CatchupInFTQDiscards; 4807 u_int32_t stat_CatchupInMBUFDiscards; 4808 u_int32_t stat_CatchupInRuleCheckerP4Hit; 4809 4810 #ifdef BNX_DEBUG 4811 /* Track the number of enqueued mbufs. */ 4812 int tx_mbuf_alloc; 4813 int rx_mbuf_alloc; 4814 4815 /* Track how many and what type of interrupts are generated. */ 4816 u_int32_t interrupts_generated; 4817 u_int32_t interrupts_handled; 4818 u_int32_t rx_interrupts; 4819 u_int32_t tx_interrupts; 4820 4821 u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ 4822 u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ 4823 u_int32_t mbuf_alloc_failed; /* Mbuf allocation failure counter. */ 4824 u_int32_t l2fhdr_status_errors; 4825 u_int32_t unexpected_attentions; 4826 u_int32_t lost_status_block_updates; 4827 #endif 4828 }; 4829 4830 #endif /* #ifndef _BNX_H_DEFINED */ 4831
Indexes created Mon Sep 29 13:09:55 GMT 2025