if_bwfm_pci.h revision 1.1.2.2
1 /* $OpenBSD: if_bwfm_pci.h,v 1.2 2018/01/05 23:30:16 patrick Exp $ */ 2 /* 3 * Copyright (c) 2010-2016 Broadcom Corporation 4 * Copyright (c) 2017 Patrick Wildt <patrick (at) blueri.se> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Registers */ 20 #define BWFM_PCI_BAR0_WINDOW 0x80 21 #define BWFM_PCI_BAR0_REG_SIZE 0x1000 22 23 #define BWFM_PCI_ARMCR4REG_BANKIDX 0x40 24 #define BWFM_PCI_ARMCR4REG_BANKPDA 0x4C 25 26 #define BWFM_PCI_PCIE2REG_INTMASK 0x24 27 #define BWFM_PCI_PCIE2REG_MAILBOXINT 0x48 28 #define BWFM_PCI_PCIE2REG_MAILBOXMASK 0x4C 29 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_0 0x0100 30 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_1 0x0200 31 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 0x10000 32 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 0x20000 33 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 0x40000 34 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 0x80000 35 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x100000 36 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x200000 37 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x400000 38 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x800000 39 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H_DB \ 40 (BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \ 41 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \ 42 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \ 43 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \ 44 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \ 45 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ 46 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ 47 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1) 48 49 #define BWFM_PCI_PCIE2REG_CONFIGADDR 0x120 50 #define BWFM_PCI_PCIE2REG_CONFIGDATA 0x124 51 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX 0x140 52 53 #define BWFM_PCI_CFGREG_STATUS_CMD 0x004 54 #define BWFM_PCI_CFGREG_PM_CSR 0x04C 55 #define BWFM_PCI_CFGREG_MSI_CAP 0x058 56 #define BWFM_PCI_CFGREG_MSI_ADDR_L 0x05C 57 #define BWFM_PCI_CFGREG_MSI_ADDR_H 0x060 58 #define BWFM_PCI_CFGREG_MSI_DATA 0x064 59 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL 0x0BC 60 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL_ASPM_ENAB 0x3 61 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL2 0x0DC 62 #define BWFM_PCI_CFGREG_RBAR_CTRL 0x228 63 #define BWFM_PCI_CFGREG_PML1_SUB_CTRL1 0x248 64 #define BWFM_PCI_CFGREG_REG_BAR2_CONFIG 0x4E0 65 #define BWFM_PCI_CFGREG_REG_BAR3_CONFIG 0x4F4 66 67 #define BWFM_RAMSIZE 0x6c 68 #define BWFM_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 69 70 #define BWFM_SHARED_INFO 0x000 71 #define BWFM_SHARED_INFO_MIN_VERSION 5 72 #define BWFM_SHARED_INFO_MAX_VERSION 6 73 #define BWFM_SHARED_INFO_VERSION_MASK 0x00FF 74 #define BWFM_SHARED_INFO_DMA_INDEX 0x10000 75 #define BWFM_SHARED_INFO_DMA_2B_IDX 0x100000 76 #define BWFM_SHARED_CONSOLE_ADDR 0x14 77 #define BWFM_SHARED_MAX_RXBUFPOST 0x22 78 #define BWFM_SHARED_MAX_RXBUFPOST_DEFAULT 255 79 #define BWFM_SHARED_RX_DATAOFFSET 0x24 80 #define BWFM_SHARED_HTOD_MB_DATA_ADDR 0x28 81 #define BWFM_SHARED_DTOH_MB_DATA_ADDR 0x2c 82 #define BWFM_SHARED_RING_INFO_ADDR 0x30 83 #define BWFM_SHARED_DMA_SCRATCH_LEN 0x34 84 #define BWFM_SHARED_DMA_SCRATCH_ADDR_LOW 0x38 85 #define BWFM_SHARED_DMA_SCRATCH_ADDR_HIGH 0x3c 86 #define BWFM_SHARED_DMA_RINGUPD_LEN 0x40 87 #define BWFM_SHARED_DMA_RINGUPD_ADDR_LOW 0x44 88 #define BWFM_SHARED_DMA_RINGUPD_ADDR_HIGH 0x48 89 90 #define BWFM_RING_MAX_ITEM 0x04 91 #define BWFM_RING_LEN_ITEMS 0x06 92 #define BWFM_RING_MEM_BASE_ADDR_LOW 0x08 93 #define BWFM_RING_MEM_BASE_ADDR_HIGH 0x0c 94 #define BWFM_RING_MEM_SZ 16 95 96 #define BWFM_CONSOLE_BUFADDR 0x08 97 #define BWFM_CONSOLE_BUFSIZE 0x0c 98 #define BWFM_CONSOLE_WRITEIDX 0x10 99 100 struct bwfm_pci_ringinfo { 101 uint32_t ringmem; 102 uint32_t h2d_w_idx_ptr; 103 uint32_t h2d_r_idx_ptr; 104 uint32_t d2h_w_idx_ptr; 105 uint32_t d2h_r_idx_ptr; 106 uint32_t h2d_w_idx_hostaddr_low; 107 uint32_t h2d_w_idx_hostaddr_high; 108 uint32_t h2d_r_idx_hostaddr_low; 109 uint32_t h2d_r_idx_hostaddr_high; 110 uint32_t d2h_w_idx_hostaddr_low; 111 uint32_t d2h_w_idx_hostaddr_high; 112 uint32_t d2h_r_idx_hostaddr_low; 113 uint32_t d2h_r_idx_hostaddr_high; 114 uint16_t max_flowrings; 115 uint16_t max_submissionrings; 116 uint16_t max_completionrings; 117 }; 118 119 /* Msgbuf defines */ 120 #define MSGBUF_IOCTL_RESP_TIMEOUT 2000 /* msecs */ 121 #define MSGBUF_IOCTL_REQ_PKTID 0xFFFE 122 #define MSGBUF_MAX_PKT_SIZE 2048 123 124 #define MSGBUF_TYPE_GEN_STATUS 0x1 125 #define MSGBUF_TYPE_RING_STATUS 0x2 126 #define MSGBUF_TYPE_FLOW_RING_CREATE 0x3 127 #define MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT 0x4 128 #define MSGBUF_TYPE_FLOW_RING_DELETE 0x5 129 #define MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT 0x6 130 #define MSGBUF_TYPE_FLOW_RING_FLUSH 0x7 131 #define MSGBUF_TYPE_FLOW_RING_FLUSH_CMPLT 0x8 132 #define MSGBUF_TYPE_IOCTLPTR_REQ 0x9 133 #define MSGBUF_TYPE_IOCTLPTR_REQ_ACK 0xA 134 #define MSGBUF_TYPE_IOCTLRESP_BUF_POST 0xB 135 #define MSGBUF_TYPE_IOCTL_CMPLT 0xC 136 #define MSGBUF_TYPE_EVENT_BUF_POST 0xD 137 #define MSGBUF_TYPE_WL_EVENT 0xE 138 #define MSGBUF_TYPE_TX_POST 0xF 139 #define MSGBUF_TYPE_TX_STATUS 0x10 140 #define MSGBUF_TYPE_RXBUF_POST 0x11 141 #define MSGBUF_TYPE_RX_CMPLT 0x12 142 #define MSGBUF_TYPE_LPBK_DMAXFER 0x13 143 #define MSGBUF_TYPE_LPBK_DMAXFER_CMPLT 0x14 144 145 struct msgbuf_common_hdr { 146 uint8_t msgtype; 147 uint8_t ifidx; 148 uint8_t flags; 149 uint8_t rsvd0; 150 uint32_t request_id; 151 }; 152 153 struct msgbuf_buf_addr { 154 uint32_t low_addr; 155 uint32_t high_addr; 156 }; 157 158 struct msgbuf_ioctl_req_hdr { 159 struct msgbuf_common_hdr msg; 160 uint32_t cmd; 161 uint16_t trans_id; 162 uint16_t input_buf_len; 163 uint16_t output_buf_len; 164 uint16_t rsvd0[3]; 165 struct msgbuf_buf_addr req_buf_addr; 166 uint32_t rsvd1[2]; 167 }; 168 169 struct msgbuf_tx_msghdr { 170 struct msgbuf_common_hdr msg; 171 uint8_t txhdr[ETHER_HDR_LEN]; 172 uint8_t flags; 173 #define BWFM_MSGBUF_PKT_FLAGS_FRAME_802_3 (1 << 0) 174 #define BWFM_MSGBUF_PKT_FLAGS_PRIO_SHIFT 5 175 uint8_t seg_cnt; 176 struct msgbuf_buf_addr metadata_buf_addr; 177 struct msgbuf_buf_addr data_buf_addr; 178 uint16_t metadata_buf_len; 179 uint16_t data_len; 180 uint32_t rsvd0; 181 }; 182 183 struct msgbuf_rx_bufpost { 184 struct msgbuf_common_hdr msg; 185 uint16_t metadata_buf_len; 186 uint16_t data_buf_len; 187 uint32_t rsvd0; 188 struct msgbuf_buf_addr metadata_buf_addr; 189 struct msgbuf_buf_addr data_buf_addr; 190 }; 191 192 struct msgbuf_rx_ioctl_resp_or_event { 193 struct msgbuf_common_hdr msg; 194 uint16_t host_buf_len; 195 uint16_t rsvd0[3]; 196 struct msgbuf_buf_addr host_buf_addr; 197 uint32_t rsvd1[4]; 198 }; 199 200 struct msgbuf_completion_hdr { 201 uint16_t status; 202 uint16_t flow_ring_id; 203 }; 204 205 struct msgbuf_rx_event { 206 struct msgbuf_common_hdr msg; 207 struct msgbuf_completion_hdr compl_hdr; 208 uint16_t event_data_len; 209 uint16_t seqnum; 210 uint16_t rsvd0[4]; 211 }; 212 213 struct msgbuf_ioctl_resp_hdr { 214 struct msgbuf_common_hdr msg; 215 struct msgbuf_completion_hdr compl_hdr; 216 uint16_t resp_len; 217 uint16_t trans_id; 218 uint32_t cmd; 219 uint32_t rsvd0; 220 }; 221 222 struct msgbuf_tx_status { 223 struct msgbuf_common_hdr msg; 224 struct msgbuf_completion_hdr compl_hdr; 225 uint16_t metadata_len; 226 uint16_t tx_status; 227 }; 228 229 struct msgbuf_rx_complete { 230 struct msgbuf_common_hdr msg; 231 struct msgbuf_completion_hdr compl_hdr; 232 uint16_t metadata_len; 233 uint16_t data_len; 234 uint16_t data_offset; 235 uint16_t flags; 236 uint32_t rx_status_0; 237 uint32_t rx_status_1; 238 uint32_t rsvd0; 239 }; 240 241 struct msgbuf_tx_flowring_create_req { 242 struct msgbuf_common_hdr msg; 243 uint8_t da[ETHER_ADDR_LEN]; 244 uint8_t sa[ETHER_ADDR_LEN]; 245 uint8_t tid; 246 uint8_t if_flags; 247 uint16_t flow_ring_id; 248 uint8_t tc; 249 uint8_t priority; 250 uint16_t int_vector; 251 uint16_t max_items; 252 uint16_t len_item; 253 struct msgbuf_buf_addr flow_ring_addr; 254 }; 255 256 struct msgbuf_tx_flowring_delete_req { 257 struct msgbuf_common_hdr msg; 258 uint16_t flow_ring_id; 259 uint16_t reason; 260 uint32_t rsvd0[7]; 261 }; 262 263 struct msgbuf_flowring_create_resp { 264 struct msgbuf_common_hdr msg; 265 struct msgbuf_completion_hdr compl_hdr; 266 uint32_t rsvd0[3]; 267 }; 268 269 struct msgbuf_flowring_delete_resp { 270 struct msgbuf_common_hdr msg; 271 struct msgbuf_completion_hdr compl_hdr; 272 uint32_t rsvd0[3]; 273 }; 274 275 struct msgbuf_flowring_flush_resp { 276 struct msgbuf_common_hdr msg; 277 struct msgbuf_completion_hdr compl_hdr; 278 uint32_t rsvd0[3]; 279 }; 280
Indexes created Wed Oct 15 16:09:53 GMT 2025