if_cas.c revision 1.48 1 1.48 riastrad /* $NetBSD: if_cas.c,v 1.48 2024/06/29 12:11:11 riastradh Exp $ */
2 1.1 jdc /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */
3 1.1 jdc
4 1.1 jdc /*
5 1.1 jdc *
6 1.1 jdc * Copyright (C) 2007 Mark Kettenis.
7 1.1 jdc * Copyright (C) 2001 Eduardo Horvath.
8 1.1 jdc * All rights reserved.
9 1.1 jdc *
10 1.1 jdc *
11 1.1 jdc * Redistribution and use in source and binary forms, with or without
12 1.1 jdc * modification, are permitted provided that the following conditions
13 1.1 jdc * are met:
14 1.1 jdc * 1. Redistributions of source code must retain the above copyright
15 1.1 jdc * notice, this list of conditions and the following disclaimer.
16 1.1 jdc * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 jdc * notice, this list of conditions and the following disclaimer in the
18 1.1 jdc * documentation and/or other materials provided with the distribution.
19 1.1 jdc *
20 1.1 jdc * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
21 1.1 jdc * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 1.1 jdc * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 1.1 jdc * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
24 1.1 jdc * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 1.1 jdc * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 1.1 jdc * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 1.1 jdc * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 1.1 jdc * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 1.1 jdc * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 1.1 jdc * SUCH DAMAGE.
31 1.1 jdc *
32 1.1 jdc */
33 1.1 jdc
34 1.1 jdc /*
35 1.1 jdc * Driver for Sun Cassini ethernet controllers.
36 1.1 jdc *
37 1.1 jdc * There are basically two variants of this chip: Cassini and
38 1.1 jdc * Cassini+. We can distinguish between the two by revision: 0x10 and
39 1.1 jdc * up are Cassini+. The most important difference is that Cassini+
40 1.1 jdc * has a second RX descriptor ring. Cassini+ will not work without
41 1.1 jdc * configuring that second ring. However, since we don't use it we
42 1.1 jdc * don't actually fill the descriptors, and only hand off the first
43 1.1 jdc * four to the chip.
44 1.1 jdc */
45 1.1 jdc
46 1.1 jdc #include <sys/cdefs.h>
47 1.48 riastrad __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.48 2024/06/29 12:11:11 riastradh Exp $");
48 1.1 jdc
49 1.13 jmcneill #ifndef _MODULE
50 1.1 jdc #include "opt_inet.h"
51 1.13 jmcneill #endif
52 1.1 jdc
53 1.1 jdc #include <sys/param.h>
54 1.1 jdc #include <sys/systm.h>
55 1.1 jdc #include <sys/callout.h>
56 1.1 jdc #include <sys/mbuf.h>
57 1.1 jdc #include <sys/syslog.h>
58 1.1 jdc #include <sys/kernel.h>
59 1.1 jdc #include <sys/socket.h>
60 1.1 jdc #include <sys/ioctl.h>
61 1.1 jdc #include <sys/errno.h>
62 1.1 jdc #include <sys/device.h>
63 1.13 jmcneill #include <sys/module.h>
64 1.1 jdc
65 1.1 jdc #include <machine/endian.h>
66 1.1 jdc
67 1.1 jdc #include <net/if.h>
68 1.1 jdc #include <net/if_dl.h>
69 1.1 jdc #include <net/if_media.h>
70 1.1 jdc #include <net/if_ether.h>
71 1.1 jdc
72 1.1 jdc #ifdef INET
73 1.1 jdc #include <netinet/in.h>
74 1.1 jdc #include <netinet/in_systm.h>
75 1.1 jdc #include <netinet/in_var.h>
76 1.1 jdc #include <netinet/ip.h>
77 1.1 jdc #include <netinet/tcp.h>
78 1.1 jdc #include <netinet/udp.h>
79 1.1 jdc #endif
80 1.1 jdc
81 1.1 jdc #include <net/bpf.h>
82 1.1 jdc
83 1.1 jdc #include <sys/bus.h>
84 1.1 jdc #include <sys/intr.h>
85 1.23 riastrad #include <sys/rndsource.h>
86 1.1 jdc
87 1.1 jdc #include <dev/mii/mii.h>
88 1.1 jdc #include <dev/mii/miivar.h>
89 1.1 jdc #include <dev/mii/mii_bitbang.h>
90 1.1 jdc
91 1.1 jdc #include <dev/pci/pcivar.h>
92 1.1 jdc #include <dev/pci/pcireg.h>
93 1.1 jdc #include <dev/pci/pcidevs.h>
94 1.5 jdc #include <prop/proplib.h>
95 1.1 jdc
96 1.1 jdc #include <dev/pci/if_casreg.h>
97 1.1 jdc #include <dev/pci/if_casvar.h>
98 1.1 jdc
99 1.1 jdc #define TRIES 10000
100 1.1 jdc
101 1.3 jdc static bool cas_estintr(struct cas_softc *sc, int);
102 1.1 jdc bool cas_shutdown(device_t, int);
103 1.6 dyoung static bool cas_suspend(device_t, const pmf_qual_t *);
104 1.6 dyoung static bool cas_resume(device_t, const pmf_qual_t *);
105 1.1 jdc static int cas_detach(device_t, int);
106 1.1 jdc static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage);
107 1.1 jdc
108 1.1 jdc int cas_match(device_t, cfdata_t, void *);
109 1.1 jdc void cas_attach(device_t, device_t, void *);
110 1.1 jdc
111 1.1 jdc
112 1.1 jdc CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc),
113 1.1 jdc cas_match, cas_attach, cas_detach, NULL, NULL, NULL,
114 1.1 jdc DVF_DETACH_SHUTDOWN);
115 1.1 jdc
116 1.37 msaitoh int cas_pci_readvpd(struct cas_softc *, struct pci_attach_args *, uint8_t *);
117 1.1 jdc
118 1.1 jdc void cas_config(struct cas_softc *, const uint8_t *);
119 1.1 jdc void cas_start(struct ifnet *);
120 1.1 jdc void cas_stop(struct ifnet *, int);
121 1.1 jdc int cas_ioctl(struct ifnet *, u_long, void *);
122 1.1 jdc void cas_tick(void *);
123 1.1 jdc void cas_watchdog(struct ifnet *);
124 1.1 jdc int cas_init(struct ifnet *);
125 1.1 jdc void cas_init_regs(struct cas_softc *);
126 1.1 jdc int cas_ringsize(int);
127 1.1 jdc int cas_cringsize(int);
128 1.1 jdc int cas_meminit(struct cas_softc *);
129 1.1 jdc void cas_mifinit(struct cas_softc *);
130 1.1 jdc int cas_bitwait(struct cas_softc *, bus_space_handle_t, int,
131 1.33 msaitoh uint32_t, uint32_t);
132 1.1 jdc void cas_reset(struct cas_softc *);
133 1.1 jdc int cas_reset_rx(struct cas_softc *);
134 1.1 jdc int cas_reset_tx(struct cas_softc *);
135 1.1 jdc int cas_disable_rx(struct cas_softc *);
136 1.1 jdc int cas_disable_tx(struct cas_softc *);
137 1.1 jdc void cas_rxdrain(struct cas_softc *);
138 1.33 msaitoh int cas_add_rxbuf(struct cas_softc *, int);
139 1.1 jdc void cas_iff(struct cas_softc *);
140 1.33 msaitoh int cas_encap(struct cas_softc *, struct mbuf *, uint32_t *);
141 1.1 jdc
142 1.1 jdc /* MII methods & callbacks */
143 1.30 msaitoh int cas_mii_readreg(device_t, int, int, uint16_t*);
144 1.30 msaitoh int cas_mii_writereg(device_t, int, int, uint16_t);
145 1.18 matt void cas_mii_statchg(struct ifnet *);
146 1.30 msaitoh int cas_pcs_readreg(device_t, int, int, uint16_t *);
147 1.30 msaitoh int cas_pcs_writereg(device_t, int, int, uint16_t);
148 1.1 jdc
149 1.1 jdc int cas_mediachange(struct ifnet *);
150 1.1 jdc void cas_mediastatus(struct ifnet *, struct ifmediareq *);
151 1.1 jdc
152 1.1 jdc int cas_eint(struct cas_softc *, u_int);
153 1.1 jdc int cas_rint(struct cas_softc *);
154 1.33 msaitoh int cas_tint(struct cas_softc *, uint32_t);
155 1.1 jdc int cas_pint(struct cas_softc *);
156 1.1 jdc int cas_intr(void *);
157 1.1 jdc
158 1.1 jdc #ifdef CAS_DEBUG
159 1.1 jdc #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \
160 1.1 jdc printf x
161 1.1 jdc #else
162 1.1 jdc #define DPRINTF(sc, x) /* nothing */
163 1.1 jdc #endif
164 1.1 jdc
165 1.45 thorpej static const struct device_compatible_entry compat_data[] = {
166 1.45 thorpej { .id = PCI_ID_CODE(PCI_VENDOR_SUN,
167 1.45 thorpej PCI_PRODUCT_SUN_CASSINI),
168 1.45 thorpej .value = CAS_CAS },
169 1.45 thorpej
170 1.45 thorpej { .id = PCI_ID_CODE(PCI_VENDOR_NS,
171 1.45 thorpej PCI_PRODUCT_NS_SATURN),
172 1.45 thorpej .value = CAS_SATURN },
173 1.45 thorpej
174 1.45 thorpej PCI_COMPAT_EOL
175 1.37 msaitoh };
176 1.37 msaitoh
177 1.37 msaitoh #define CAS_LOCAL_MAC_ADDRESS "local-mac-address"
178 1.37 msaitoh #define CAS_PHY_INTERFACE "phy-interface"
179 1.37 msaitoh #define CAS_PHY_TYPE "phy-type"
180 1.37 msaitoh #define CAS_PHY_TYPE_PCS "pcs"
181 1.37 msaitoh
182 1.1 jdc int
183 1.1 jdc cas_match(device_t parent, cfdata_t cf, void *aux)
184 1.1 jdc {
185 1.1 jdc struct pci_attach_args *pa = aux;
186 1.1 jdc
187 1.45 thorpej return pci_compatible_match(pa, compat_data);
188 1.1 jdc }
189 1.1 jdc
190 1.1 jdc #define PROMHDR_PTR_DATA 0x18
191 1.1 jdc #define PROMDATA_PTR_VPD 0x08
192 1.1 jdc #define PROMDATA_DATA2 0x0a
193 1.1 jdc
194 1.33 msaitoh static const uint8_t cas_promhdr[] = { 0x55, 0xaa };
195 1.33 msaitoh static const uint8_t cas_promdat[] = {
196 1.1 jdc 'P', 'C', 'I', 'R',
197 1.1 jdc PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8,
198 1.1 jdc PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8
199 1.1 jdc };
200 1.33 msaitoh static const uint8_t cas_promdat_ns[] = {
201 1.11 jnemeth 'P', 'C', 'I', 'R',
202 1.11 jnemeth PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8,
203 1.11 jnemeth PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8
204 1.11 jnemeth };
205 1.1 jdc
206 1.33 msaitoh static const uint8_t cas_promdat2[] = {
207 1.1 jdc 0x18, 0x00, /* structure length */
208 1.1 jdc 0x00, /* structure revision */
209 1.1 jdc 0x00, /* interface revision */
210 1.1 jdc PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */
211 1.1 jdc PCI_CLASS_NETWORK /* class code */
212 1.1 jdc };
213 1.1 jdc
214 1.32 msaitoh #define CAS_LMA_MAXNUM 4
215 1.1 jdc int
216 1.37 msaitoh cas_pci_readvpd(struct cas_softc *sc, struct pci_attach_args *pa,
217 1.1 jdc uint8_t *enaddr)
218 1.1 jdc {
219 1.1 jdc struct pci_vpd_largeres *res;
220 1.1 jdc struct pci_vpd *vpd;
221 1.1 jdc bus_space_handle_t romh;
222 1.1 jdc bus_space_tag_t romt;
223 1.1 jdc bus_size_t romsize = 0;
224 1.32 msaitoh uint8_t enaddrs[CAS_LMA_MAXNUM][ETHER_ADDR_LEN];
225 1.37 msaitoh bool pcs[4] = {false, false, false, false};
226 1.33 msaitoh uint8_t buf[32], *desc;
227 1.1 jdc pcireg_t address;
228 1.37 msaitoh int dataoff, vpdoff, len, lma = 0, phy = 0;
229 1.32 msaitoh int i, rv = -1;
230 1.1 jdc
231 1.1 jdc if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0,
232 1.1 jdc &romt, &romh, NULL, &romsize))
233 1.1 jdc return (-1);
234 1.1 jdc
235 1.1 jdc address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
236 1.1 jdc address |= PCI_MAPREG_ROM_ENABLE;
237 1.1 jdc pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address);
238 1.1 jdc
239 1.1 jdc bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf));
240 1.1 jdc if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr)))
241 1.1 jdc goto fail;
242 1.1 jdc
243 1.1 jdc dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8);
244 1.1 jdc if (dataoff < 0x1c)
245 1.1 jdc goto fail;
246 1.1 jdc
247 1.1 jdc bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf));
248 1.11 jnemeth if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) &&
249 1.11 jnemeth bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) ||
250 1.1 jdc bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2)))
251 1.1 jdc goto fail;
252 1.1 jdc
253 1.1 jdc vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8);
254 1.1 jdc if (vpdoff < 0x1c)
255 1.1 jdc goto fail;
256 1.1 jdc
257 1.1 jdc next:
258 1.1 jdc bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf));
259 1.1 jdc if (!PCI_VPDRES_ISLARGE(buf[0]))
260 1.1 jdc goto fail;
261 1.1 jdc
262 1.1 jdc res = (struct pci_vpd_largeres *)buf;
263 1.1 jdc vpdoff += sizeof(*res);
264 1.1 jdc
265 1.1 jdc len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb);
266 1.33 msaitoh switch (PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) {
267 1.1 jdc case PCI_VPDRES_TYPE_IDENTIFIER_STRING:
268 1.1 jdc /* Skip identifier string. */
269 1.1 jdc vpdoff += len;
270 1.1 jdc goto next;
271 1.1 jdc
272 1.1 jdc case PCI_VPDRES_TYPE_VPD:
273 1.37 msaitoh #ifdef CAS_DEBUG
274 1.37 msaitoh printf("\n");
275 1.37 msaitoh for (i = 0; i < len; i++) {
276 1.37 msaitoh uint8_t byte;
277 1.37 msaitoh if (i % 16 == 0)
278 1.37 msaitoh printf("%04x :", i);
279 1.37 msaitoh byte = bus_space_read_1(romt, romh, vpdoff + i);
280 1.37 msaitoh printf(" %02x", byte);
281 1.37 msaitoh if (i % 16 == 15)
282 1.37 msaitoh printf("\n");
283 1.37 msaitoh }
284 1.37 msaitoh printf("\n");
285 1.37 msaitoh #endif
286 1.37 msaitoh
287 1.1 jdc while (len > 0) {
288 1.1 jdc bus_space_read_region_1(romt, romh, vpdoff,
289 1.1 jdc buf, sizeof(buf));
290 1.1 jdc
291 1.1 jdc vpd = (struct pci_vpd *)buf;
292 1.1 jdc vpdoff += sizeof(*vpd) + vpd->vpd_len;
293 1.1 jdc len -= sizeof(*vpd) + vpd->vpd_len;
294 1.1 jdc
295 1.1 jdc /*
296 1.1 jdc * We're looking for an "Enhanced" VPD...
297 1.1 jdc */
298 1.1 jdc if (vpd->vpd_key0 != 'Z')
299 1.1 jdc continue;
300 1.1 jdc
301 1.1 jdc desc = buf + sizeof(*vpd);
302 1.1 jdc
303 1.19 christos /*
304 1.1 jdc * ...which is an instance property...
305 1.1 jdc */
306 1.1 jdc if (desc[0] != 'I')
307 1.1 jdc continue;
308 1.1 jdc desc += 3;
309 1.1 jdc
310 1.37 msaitoh if (desc[0] == 'B' || desc[1] == ETHER_ADDR_LEN) {
311 1.37 msaitoh /*
312 1.37 msaitoh * ...that's a byte array with the proper
313 1.37 msaitoh * length for a MAC address...
314 1.37 msaitoh */
315 1.37 msaitoh desc += 2;
316 1.37 msaitoh
317 1.37 msaitoh /*
318 1.37 msaitoh * ...named "local-mac-address".
319 1.37 msaitoh */
320 1.37 msaitoh if (strcmp(desc, CAS_LOCAL_MAC_ADDRESS) != 0)
321 1.37 msaitoh continue;
322 1.37 msaitoh desc += sizeof(CAS_LOCAL_MAC_ADDRESS);
323 1.37 msaitoh
324 1.37 msaitoh if (lma == CAS_LMA_MAXNUM)
325 1.37 msaitoh continue;
326 1.37 msaitoh
327 1.37 msaitoh memcpy(enaddrs[lma], desc, ETHER_ADDR_LEN);
328 1.37 msaitoh lma++;
329 1.37 msaitoh rv = 0;
330 1.1 jdc continue;
331 1.37 msaitoh } else if (desc[0] == 'S') {
332 1.37 msaitoh size_t k;
333 1.37 msaitoh
334 1.37 msaitoh /* String */
335 1.37 msaitoh desc += 2;
336 1.37 msaitoh #ifdef CAS_DEBUG
337 1.37 msaitoh /* ...named "pcs". */
338 1.37 msaitoh printf("STR: \"%s\"\n", desc);
339 1.37 msaitoh if (strcmp(desc, CAS_PHY_TYPE_PCS) != 0)
340 1.37 msaitoh continue;
341 1.37 msaitoh desc += sizeof(CAS_PHY_TYPE_PCS);
342 1.37 msaitoh printf("STR: \"%s\"\n", desc);
343 1.37 msaitoh #endif
344 1.37 msaitoh /* ...named "phy-interface" or "phy-type". */
345 1.37 msaitoh if (strcmp(desc, CAS_PHY_INTERFACE) == 0)
346 1.37 msaitoh k = sizeof(CAS_PHY_INTERFACE);
347 1.37 msaitoh else if (strcmp(desc, CAS_PHY_TYPE) == 0)
348 1.37 msaitoh k = sizeof(CAS_PHY_TYPE);
349 1.37 msaitoh else
350 1.37 msaitoh continue;
351 1.1 jdc
352 1.37 msaitoh desc += k;
353 1.37 msaitoh #ifdef CAS_DEBUG
354 1.37 msaitoh printf("STR: \"%s\"\n", desc);
355 1.37 msaitoh #endif
356 1.37 msaitoh if (strcmp(desc, CAS_PHY_TYPE_PCS) == 0)
357 1.37 msaitoh pcs[phy] = true;
358 1.37 msaitoh phy++;
359 1.1 jdc continue;
360 1.37 msaitoh }
361 1.1 jdc }
362 1.1 jdc break;
363 1.1 jdc
364 1.1 jdc default:
365 1.1 jdc goto fail;
366 1.1 jdc }
367 1.1 jdc
368 1.32 msaitoh /*
369 1.32 msaitoh * Multi port card has bridge chip. The device number is fixed:
370 1.32 msaitoh * e.g.
371 1.32 msaitoh * p0: 005:00:0
372 1.32 msaitoh * p1: 005:01:0
373 1.32 msaitoh * p2: 006:02:0
374 1.32 msaitoh * p3: 006:03:0
375 1.32 msaitoh */
376 1.37 msaitoh if (enaddr != 0) {
377 1.37 msaitoh i = 0;
378 1.37 msaitoh if ((lma > 1) && (pa->pa_device < CAS_LMA_MAXNUM)
379 1.37 msaitoh && (pa->pa_device < lma))
380 1.37 msaitoh i = pa->pa_device;
381 1.37 msaitoh memcpy(enaddr, enaddrs[i], ETHER_ADDR_LEN);
382 1.37 msaitoh }
383 1.37 msaitoh if (pcs[pa->pa_device])
384 1.37 msaitoh sc->sc_flags |= CAS_SERDES;
385 1.1 jdc fail:
386 1.1 jdc if (romsize != 0)
387 1.1 jdc bus_space_unmap(romt, romh, romsize);
388 1.1 jdc
389 1.1 jdc address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM);
390 1.1 jdc address &= ~PCI_MAPREG_ROM_ENABLE;
391 1.1 jdc pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address);
392 1.1 jdc
393 1.1 jdc return (rv);
394 1.1 jdc }
395 1.1 jdc
396 1.1 jdc void
397 1.1 jdc cas_attach(device_t parent, device_t self, void *aux)
398 1.1 jdc {
399 1.1 jdc struct pci_attach_args *pa = aux;
400 1.45 thorpej const struct device_compatible_entry *dce;
401 1.1 jdc struct cas_softc *sc = device_private(self);
402 1.5 jdc prop_data_t data;
403 1.1 jdc uint8_t enaddr[ETHER_ADDR_LEN];
404 1.1 jdc
405 1.1 jdc sc->sc_dev = self;
406 1.15 drochner pci_aprint_devinfo(pa, NULL);
407 1.1 jdc sc->sc_rev = PCI_REVISION(pa->pa_class);
408 1.41 thorpej
409 1.41 thorpej if (pci_dma64_available(pa))
410 1.41 thorpej sc->sc_dmatag = pa->pa_dmat64;
411 1.41 thorpej else
412 1.41 thorpej sc->sc_dmatag = pa->pa_dmat;
413 1.1 jdc
414 1.45 thorpej dce = pci_compatible_lookup(pa, compat_data);
415 1.45 thorpej KASSERT(dce != NULL);
416 1.45 thorpej sc->sc_variant = (u_int)dce->value;
417 1.45 thorpej
418 1.37 msaitoh aprint_debug_dev(sc->sc_dev, "variant = %d\n", sc->sc_variant);
419 1.37 msaitoh
420 1.1 jdc #define PCI_CAS_BASEADDR 0x10
421 1.1 jdc if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0,
422 1.1 jdc &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) {
423 1.1 jdc aprint_error_dev(sc->sc_dev,
424 1.1 jdc "unable to map device registers\n");
425 1.1 jdc return;
426 1.1 jdc }
427 1.1 jdc
428 1.5 jdc if ((data = prop_dictionary_get(device_properties(sc->sc_dev),
429 1.5 jdc "mac-address")) != NULL)
430 1.43 msaitoh memcpy(enaddr, prop_data_value(data), ETHER_ADDR_LEN);
431 1.37 msaitoh if (cas_pci_readvpd(sc, pa, (data == NULL) ? enaddr : 0) != 0) {
432 1.1 jdc aprint_error_dev(sc->sc_dev, "no Ethernet address found\n");
433 1.10 jnemeth memset(enaddr, 0, sizeof(enaddr));
434 1.10 jnemeth }
435 1.1 jdc
436 1.1 jdc sc->sc_burst = 16; /* XXX */
437 1.1 jdc
438 1.1 jdc sc->sc_att_stage = CAS_ATT_BACKEND_0;
439 1.1 jdc
440 1.1 jdc if (pci_intr_map(pa, &sc->sc_handle) != 0) {
441 1.1 jdc aprint_error_dev(sc->sc_dev, "unable to map interrupt\n");
442 1.1 jdc bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
443 1.1 jdc return;
444 1.1 jdc }
445 1.1 jdc sc->sc_pc = pa->pa_pc;
446 1.3 jdc if (!cas_estintr(sc, CAS_INTR_PCI)) {
447 1.1 jdc bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
448 1.1 jdc aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n");
449 1.1 jdc return;
450 1.1 jdc }
451 1.1 jdc
452 1.1 jdc sc->sc_att_stage = CAS_ATT_BACKEND_1;
453 1.1 jdc
454 1.1 jdc /*
455 1.1 jdc * call the main configure
456 1.1 jdc */
457 1.1 jdc cas_config(sc, enaddr);
458 1.1 jdc
459 1.1 jdc if (pmf_device_register1(sc->sc_dev,
460 1.1 jdc cas_suspend, cas_resume, cas_shutdown))
461 1.1 jdc pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if);
462 1.1 jdc else
463 1.1 jdc aprint_error_dev(sc->sc_dev,
464 1.1 jdc "could not establish power handlers\n");
465 1.1 jdc
466 1.1 jdc sc->sc_att_stage = CAS_ATT_FINISHED;
467 1.1 jdc /*FALLTHROUGH*/
468 1.1 jdc }
469 1.1 jdc
470 1.1 jdc /*
471 1.1 jdc * cas_config:
472 1.1 jdc *
473 1.1 jdc * Attach a Cassini interface to the system.
474 1.1 jdc */
475 1.1 jdc void
476 1.1 jdc cas_config(struct cas_softc *sc, const uint8_t *enaddr)
477 1.1 jdc {
478 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
479 1.1 jdc struct mii_data *mii = &sc->sc_mii;
480 1.1 jdc struct mii_softc *child;
481 1.37 msaitoh uint32_t reg;
482 1.1 jdc int i, error;
483 1.1 jdc
484 1.1 jdc /* Make sure the chip is stopped. */
485 1.1 jdc ifp->if_softc = sc;
486 1.1 jdc cas_reset(sc);
487 1.1 jdc
488 1.1 jdc /*
489 1.1 jdc * Allocate the control data structures, and create and load the
490 1.1 jdc * DMA map for it.
491 1.1 jdc */
492 1.1 jdc if ((error = bus_dmamem_alloc(sc->sc_dmatag,
493 1.1 jdc sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg,
494 1.1 jdc 1, &sc->sc_cdnseg, 0)) != 0) {
495 1.1 jdc aprint_error_dev(sc->sc_dev,
496 1.1 jdc "unable to allocate control data, error = %d\n",
497 1.1 jdc error);
498 1.1 jdc cas_partial_detach(sc, CAS_ATT_0);
499 1.1 jdc }
500 1.1 jdc
501 1.1 jdc /* XXX should map this in with correct endianness */
502 1.33 msaitoh if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg,
503 1.33 msaitoh sc->sc_cdnseg, sizeof(struct cas_control_data),
504 1.33 msaitoh (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) {
505 1.1 jdc aprint_error_dev(sc->sc_dev,
506 1.1 jdc "unable to map control data, error = %d\n", error);
507 1.1 jdc cas_partial_detach(sc, CAS_ATT_1);
508 1.1 jdc }
509 1.1 jdc
510 1.1 jdc if ((error = bus_dmamap_create(sc->sc_dmatag,
511 1.1 jdc sizeof(struct cas_control_data), 1,
512 1.1 jdc sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
513 1.1 jdc aprint_error_dev(sc->sc_dev,
514 1.33 msaitoh "unable to create control data DMA map, error = %d\n",
515 1.33 msaitoh error);
516 1.1 jdc cas_partial_detach(sc, CAS_ATT_2);
517 1.1 jdc }
518 1.1 jdc
519 1.1 jdc if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap,
520 1.1 jdc sc->sc_control_data, sizeof(struct cas_control_data), NULL,
521 1.1 jdc 0)) != 0) {
522 1.1 jdc aprint_error_dev(sc->sc_dev,
523 1.1 jdc "unable to load control data DMA map, error = %d\n",
524 1.1 jdc error);
525 1.1 jdc cas_partial_detach(sc, CAS_ATT_3);
526 1.1 jdc }
527 1.1 jdc
528 1.1 jdc memset(sc->sc_control_data, 0, sizeof(struct cas_control_data));
529 1.1 jdc
530 1.1 jdc /*
531 1.1 jdc * Create the receive buffer DMA maps.
532 1.1 jdc */
533 1.1 jdc for (i = 0; i < CAS_NRXDESC; i++) {
534 1.1 jdc bus_dma_segment_t seg;
535 1.1 jdc char *kva;
536 1.1 jdc int rseg;
537 1.1 jdc
538 1.1 jdc if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE,
539 1.1 jdc CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
540 1.1 jdc aprint_error_dev(sc->sc_dev,
541 1.1 jdc "unable to alloc rx DMA mem %d, error = %d\n",
542 1.1 jdc i, error);
543 1.1 jdc cas_partial_detach(sc, CAS_ATT_5);
544 1.1 jdc }
545 1.1 jdc sc->sc_rxsoft[i].rxs_dmaseg = seg;
546 1.1 jdc
547 1.1 jdc if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
548 1.1 jdc CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) {
549 1.1 jdc aprint_error_dev(sc->sc_dev,
550 1.1 jdc "unable to alloc rx DMA mem %d, error = %d\n",
551 1.1 jdc i, error);
552 1.1 jdc cas_partial_detach(sc, CAS_ATT_5);
553 1.1 jdc }
554 1.1 jdc sc->sc_rxsoft[i].rxs_kva = kva;
555 1.1 jdc
556 1.1 jdc if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1,
557 1.1 jdc CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
558 1.1 jdc aprint_error_dev(sc->sc_dev,
559 1.1 jdc "unable to create rx DMA map %d, error = %d\n",
560 1.1 jdc i, error);
561 1.1 jdc cas_partial_detach(sc, CAS_ATT_5);
562 1.1 jdc }
563 1.1 jdc
564 1.1 jdc if ((error = bus_dmamap_load(sc->sc_dmatag,
565 1.1 jdc sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL,
566 1.1 jdc BUS_DMA_NOWAIT)) != 0) {
567 1.1 jdc aprint_error_dev(sc->sc_dev,
568 1.1 jdc "unable to load rx DMA map %d, error = %d\n",
569 1.1 jdc i, error);
570 1.1 jdc cas_partial_detach(sc, CAS_ATT_5);
571 1.1 jdc }
572 1.1 jdc }
573 1.1 jdc
574 1.1 jdc /*
575 1.1 jdc * Create the transmit buffer DMA maps.
576 1.1 jdc */
577 1.1 jdc for (i = 0; i < CAS_NTXDESC; i++) {
578 1.1 jdc if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES,
579 1.1 jdc CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
580 1.1 jdc &sc->sc_txd[i].sd_map)) != 0) {
581 1.1 jdc aprint_error_dev(sc->sc_dev,
582 1.1 jdc "unable to create tx DMA map %d, error = %d\n",
583 1.1 jdc i, error);
584 1.1 jdc cas_partial_detach(sc, CAS_ATT_6);
585 1.1 jdc }
586 1.1 jdc sc->sc_txd[i].sd_mbuf = NULL;
587 1.1 jdc }
588 1.1 jdc
589 1.1 jdc /*
590 1.1 jdc * From this point forward, the attachment cannot fail. A failure
591 1.1 jdc * before this point releases all resources that may have been
592 1.1 jdc * allocated.
593 1.1 jdc */
594 1.1 jdc
595 1.1 jdc /* Announce ourselves. */
596 1.1 jdc aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
597 1.1 jdc ether_sprintf(enaddr));
598 1.7 mrg aprint_naive(": Ethernet controller\n");
599 1.1 jdc
600 1.1 jdc /* Get RX FIFO size */
601 1.1 jdc sc->sc_rxfifosize = 16 * 1024;
602 1.1 jdc
603 1.1 jdc /* Initialize ifnet structure. */
604 1.1 jdc strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
605 1.1 jdc ifp->if_softc = sc;
606 1.31 msaitoh ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
607 1.1 jdc ifp->if_start = cas_start;
608 1.1 jdc ifp->if_ioctl = cas_ioctl;
609 1.1 jdc ifp->if_watchdog = cas_watchdog;
610 1.1 jdc ifp->if_stop = cas_stop;
611 1.1 jdc ifp->if_init = cas_init;
612 1.1 jdc IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1);
613 1.1 jdc IFQ_SET_READY(&ifp->if_snd);
614 1.1 jdc
615 1.1 jdc /* Initialize ifmedia structures and MII info */
616 1.1 jdc mii->mii_ifp = ifp;
617 1.1 jdc mii->mii_readreg = cas_mii_readreg;
618 1.1 jdc mii->mii_writereg = cas_mii_writereg;
619 1.1 jdc mii->mii_statchg = cas_mii_statchg;
620 1.1 jdc
621 1.1 jdc ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus);
622 1.1 jdc sc->sc_ethercom.ec_mii = mii;
623 1.1 jdc
624 1.1 jdc bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0);
625 1.1 jdc
626 1.1 jdc cas_mifinit(sc);
627 1.1 jdc
628 1.37 msaitoh if (sc->sc_mif_config & (CAS_MIF_CONFIG_MDI1 | CAS_MIF_CONFIG_MDI0)) {
629 1.37 msaitoh if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) {
630 1.37 msaitoh sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL;
631 1.37 msaitoh bus_space_write_4(sc->sc_memt, sc->sc_memh,
632 1.37 msaitoh CAS_MIF_CONFIG, sc->sc_mif_config);
633 1.37 msaitoh }
634 1.37 msaitoh /* Enable/unfreeze the GMII pins of Saturn. */
635 1.37 msaitoh if (sc->sc_variant == CAS_SATURN) {
636 1.37 msaitoh reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
637 1.37 msaitoh CAS_SATURN_PCFG) & ~CAS_SATURN_PCFG_FSI;
638 1.37 msaitoh if ((sc->sc_mif_config & CAS_MIF_CONFIG_MDI0) != 0)
639 1.37 msaitoh reg |= CAS_SATURN_PCFG_FSI;
640 1.37 msaitoh bus_space_write_4(sc->sc_memt, sc->sc_memh,
641 1.37 msaitoh CAS_SATURN_PCFG, reg);
642 1.37 msaitoh /* Read to flush */
643 1.37 msaitoh bus_space_read_4(sc->sc_memt, sc->sc_memh,
644 1.37 msaitoh CAS_SATURN_PCFG);
645 1.37 msaitoh DELAY(10000);
646 1.37 msaitoh }
647 1.1 jdc }
648 1.1 jdc
649 1.1 jdc mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
650 1.1 jdc MII_OFFSET_ANY, 0);
651 1.1 jdc
652 1.1 jdc child = LIST_FIRST(&mii->mii_phys);
653 1.1 jdc if (child == NULL &&
654 1.33 msaitoh sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0 | CAS_MIF_CONFIG_MDI1)) {
655 1.19 christos /*
656 1.1 jdc * Try the external PCS SERDES if we didn't find any
657 1.1 jdc * MII devices.
658 1.1 jdc */
659 1.1 jdc bus_space_write_4(sc->sc_memt, sc->sc_memh,
660 1.1 jdc CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES);
661 1.1 jdc
662 1.1 jdc bus_space_write_4(sc->sc_memt, sc->sc_memh,
663 1.1 jdc CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE);
664 1.1 jdc
665 1.1 jdc mii->mii_readreg = cas_pcs_readreg;
666 1.1 jdc mii->mii_writereg = cas_pcs_writereg;
667 1.1 jdc
668 1.1 jdc mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
669 1.1 jdc MII_OFFSET_ANY, MIIF_NOISOLATE);
670 1.1 jdc }
671 1.1 jdc
672 1.1 jdc child = LIST_FIRST(&mii->mii_phys);
673 1.1 jdc if (child == NULL) {
674 1.1 jdc /* No PHY attached */
675 1.33 msaitoh ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL);
676 1.33 msaitoh ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL);
677 1.1 jdc } else {
678 1.1 jdc /*
679 1.1 jdc * Walk along the list of attached MII devices and
680 1.1 jdc * establish an `MII instance' to `phy number'
681 1.1 jdc * mapping. We'll use this mapping in media change
682 1.1 jdc * requests to determine which phy to use to program
683 1.1 jdc * the MIF configuration register.
684 1.1 jdc */
685 1.1 jdc for (; child != NULL; child = LIST_NEXT(child, mii_list)) {
686 1.1 jdc /*
687 1.1 jdc * Note: we support just two PHYs: the built-in
688 1.1 jdc * internal device and an external on the MII
689 1.1 jdc * connector.
690 1.1 jdc */
691 1.1 jdc if (child->mii_phy > 1 || child->mii_inst > 1) {
692 1.1 jdc aprint_error_dev(sc->sc_dev,
693 1.1 jdc "cannot accommodate MII device %s"
694 1.1 jdc " at phy %d, instance %d\n",
695 1.1 jdc device_xname(child->mii_dev),
696 1.1 jdc child->mii_phy, child->mii_inst);
697 1.1 jdc continue;
698 1.1 jdc }
699 1.1 jdc
700 1.1 jdc sc->sc_phys[child->mii_inst] = child->mii_phy;
701 1.1 jdc }
702 1.1 jdc
703 1.1 jdc /*
704 1.1 jdc * XXX - we can really do the following ONLY if the
705 1.1 jdc * phy indeed has the auto negotiation capability!!
706 1.1 jdc */
707 1.33 msaitoh ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
708 1.1 jdc }
709 1.1 jdc
710 1.1 jdc /* claim 802.1q capability */
711 1.1 jdc sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
712 1.1 jdc
713 1.1 jdc /* Attach the interface. */
714 1.1 jdc if_attach(ifp);
715 1.25 ozaki if_deferred_start_init(ifp, NULL);
716 1.1 jdc ether_ifattach(ifp, enaddr);
717 1.1 jdc
718 1.1 jdc rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
719 1.22 tls RND_TYPE_NET, RND_FLAG_DEFAULT);
720 1.1 jdc
721 1.1 jdc evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR,
722 1.1 jdc NULL, device_xname(sc->sc_dev), "interrupts");
723 1.1 jdc
724 1.1 jdc callout_init(&sc->sc_tick_ch, 0);
725 1.40 thorpej callout_setfunc(&sc->sc_tick_ch, cas_tick, sc);
726 1.1 jdc
727 1.1 jdc return;
728 1.1 jdc }
729 1.1 jdc
730 1.1 jdc int
731 1.1 jdc cas_detach(device_t self, int flags)
732 1.1 jdc {
733 1.1 jdc int i;
734 1.1 jdc struct cas_softc *sc = device_private(self);
735 1.3 jdc bus_space_tag_t t = sc->sc_memt;
736 1.3 jdc bus_space_handle_t h = sc->sc_memh;
737 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
738 1.1 jdc
739 1.1 jdc /*
740 1.1 jdc * Free any resources we've allocated during the failed attach
741 1.1 jdc * attempt. Do this in reverse order and fall through.
742 1.1 jdc */
743 1.1 jdc switch (sc->sc_att_stage) {
744 1.1 jdc case CAS_ATT_FINISHED:
745 1.3 jdc bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0);
746 1.1 jdc pmf_device_deregister(self);
747 1.1 jdc cas_stop(&sc->sc_ethercom.ec_if, 1);
748 1.1 jdc evcnt_detach(&sc->sc_ev_intr);
749 1.1 jdc
750 1.1 jdc rnd_detach_source(&sc->rnd_source);
751 1.1 jdc
752 1.1 jdc ether_ifdetach(ifp);
753 1.1 jdc if_detach(ifp);
754 1.1 jdc
755 1.1 jdc callout_destroy(&sc->sc_tick_ch);
756 1.1 jdc
757 1.1 jdc mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
758 1.1 jdc
759 1.44 mrg ifmedia_fini(&sc->sc_mii.mii_media);
760 1.44 mrg
761 1.1 jdc /*FALLTHROUGH*/
762 1.1 jdc case CAS_ATT_MII:
763 1.1 jdc case CAS_ATT_7:
764 1.1 jdc case CAS_ATT_6:
765 1.1 jdc for (i = 0; i < CAS_NTXDESC; i++) {
766 1.1 jdc if (sc->sc_txd[i].sd_map != NULL)
767 1.1 jdc bus_dmamap_destroy(sc->sc_dmatag,
768 1.1 jdc sc->sc_txd[i].sd_map);
769 1.1 jdc }
770 1.1 jdc /*FALLTHROUGH*/
771 1.1 jdc case CAS_ATT_5:
772 1.1 jdc for (i = 0; i < CAS_NRXDESC; i++) {
773 1.1 jdc if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
774 1.1 jdc bus_dmamap_unload(sc->sc_dmatag,
775 1.3 jdc sc->sc_rxsoft[i].rxs_dmamap);
776 1.1 jdc if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
777 1.1 jdc bus_dmamap_destroy(sc->sc_dmatag,
778 1.1 jdc sc->sc_rxsoft[i].rxs_dmamap);
779 1.1 jdc if (sc->sc_rxsoft[i].rxs_kva != NULL)
780 1.1 jdc bus_dmamem_unmap(sc->sc_dmatag,
781 1.1 jdc sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE);
782 1.1 jdc /* XXX need to check that bus_dmamem_alloc suceeded
783 1.1 jdc if (sc->sc_rxsoft[i].rxs_dmaseg != NULL)
784 1.1 jdc */
785 1.46 joerg bus_dmamem_free(sc->sc_dmatag,
786 1.46 joerg &(sc->sc_rxsoft[i].rxs_dmaseg), 1);
787 1.1 jdc }
788 1.1 jdc bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap);
789 1.1 jdc /*FALLTHROUGH*/
790 1.1 jdc case CAS_ATT_4:
791 1.1 jdc case CAS_ATT_3:
792 1.1 jdc bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap);
793 1.1 jdc /*FALLTHROUGH*/
794 1.1 jdc case CAS_ATT_2:
795 1.1 jdc bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data,
796 1.1 jdc sizeof(struct cas_control_data));
797 1.1 jdc /*FALLTHROUGH*/
798 1.1 jdc case CAS_ATT_1:
799 1.1 jdc bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg);
800 1.1 jdc /*FALLTHROUGH*/
801 1.1 jdc case CAS_ATT_0:
802 1.1 jdc sc->sc_att_stage = CAS_ATT_0;
803 1.1 jdc /*FALLTHROUGH*/
804 1.1 jdc case CAS_ATT_BACKEND_2:
805 1.1 jdc case CAS_ATT_BACKEND_1:
806 1.1 jdc if (sc->sc_ih != NULL) {
807 1.1 jdc pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
808 1.1 jdc sc->sc_ih = NULL;
809 1.1 jdc }
810 1.1 jdc bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
811 1.1 jdc /*FALLTHROUGH*/
812 1.1 jdc case CAS_ATT_BACKEND_0:
813 1.1 jdc break;
814 1.1 jdc }
815 1.1 jdc return 0;
816 1.1 jdc }
817 1.1 jdc
818 1.1 jdc static void
819 1.1 jdc cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage)
820 1.1 jdc {
821 1.1 jdc cfattach_t ca = device_cfattach(sc->sc_dev);
822 1.1 jdc
823 1.1 jdc sc->sc_att_stage = stage;
824 1.1 jdc (*ca->ca_detach)(sc->sc_dev, 0);
825 1.1 jdc }
826 1.1 jdc
827 1.1 jdc void
828 1.1 jdc cas_tick(void *arg)
829 1.1 jdc {
830 1.1 jdc struct cas_softc *sc = arg;
831 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
832 1.1 jdc bus_space_tag_t t = sc->sc_memt;
833 1.1 jdc bus_space_handle_t mac = sc->sc_memh;
834 1.1 jdc int s;
835 1.33 msaitoh uint32_t v;
836 1.1 jdc
837 1.38 thorpej net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
838 1.38 thorpej
839 1.1 jdc /* unload collisions counters */
840 1.1 jdc v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) +
841 1.1 jdc bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT);
842 1.48 riastrad if_statadd_ref(ifp, nsr, if_collisions, v +
843 1.1 jdc bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) +
844 1.38 thorpej bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT));
845 1.48 riastrad if_statadd_ref(ifp, nsr, if_oerrors, v);
846 1.1 jdc
847 1.1 jdc /* read error counters */
848 1.48 riastrad if_statadd_ref(ifp, nsr, if_ierrors,
849 1.1 jdc bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) +
850 1.1 jdc bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) +
851 1.1 jdc bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) +
852 1.38 thorpej bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL));
853 1.38 thorpej
854 1.38 thorpej IF_STAT_PUTREF(ifp);
855 1.1 jdc
856 1.1 jdc /* clear the hardware counters */
857 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0);
858 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0);
859 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0);
860 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0);
861 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0);
862 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0);
863 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0);
864 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0);
865 1.1 jdc
866 1.1 jdc s = splnet();
867 1.1 jdc mii_tick(&sc->sc_mii);
868 1.1 jdc splx(s);
869 1.1 jdc
870 1.40 thorpej callout_schedule(&sc->sc_tick_ch, hz);
871 1.1 jdc }
872 1.1 jdc
873 1.1 jdc int
874 1.1 jdc cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r,
875 1.33 msaitoh uint32_t clr, uint32_t set)
876 1.1 jdc {
877 1.1 jdc int i;
878 1.33 msaitoh uint32_t reg;
879 1.1 jdc
880 1.1 jdc for (i = TRIES; i--; DELAY(100)) {
881 1.1 jdc reg = bus_space_read_4(sc->sc_memt, h, r);
882 1.1 jdc if ((reg & clr) == 0 && (reg & set) == set)
883 1.1 jdc return (1);
884 1.1 jdc }
885 1.1 jdc
886 1.1 jdc return (0);
887 1.1 jdc }
888 1.1 jdc
889 1.1 jdc void
890 1.1 jdc cas_reset(struct cas_softc *sc)
891 1.1 jdc {
892 1.1 jdc bus_space_tag_t t = sc->sc_memt;
893 1.1 jdc bus_space_handle_t h = sc->sc_memh;
894 1.1 jdc int s;
895 1.1 jdc
896 1.1 jdc s = splnet();
897 1.1 jdc DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev)));
898 1.1 jdc cas_reset_rx(sc);
899 1.1 jdc cas_reset_tx(sc);
900 1.1 jdc
901 1.9 mrg /* Disable interrupts */
902 1.9 mrg bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0);
903 1.9 mrg
904 1.1 jdc /* Do a full reset */
905 1.1 jdc bus_space_write_4(t, h, CAS_RESET,
906 1.1 jdc CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS);
907 1.1 jdc if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0))
908 1.1 jdc aprint_error_dev(sc->sc_dev, "cannot reset device\n");
909 1.1 jdc splx(s);
910 1.1 jdc }
911 1.1 jdc
912 1.1 jdc
913 1.1 jdc /*
914 1.1 jdc * cas_rxdrain:
915 1.1 jdc *
916 1.1 jdc * Drain the receive queue.
917 1.1 jdc */
918 1.1 jdc void
919 1.1 jdc cas_rxdrain(struct cas_softc *sc)
920 1.1 jdc {
921 1.1 jdc /* Nothing to do yet. */
922 1.1 jdc }
923 1.1 jdc
924 1.1 jdc /*
925 1.1 jdc * Reset the whole thing.
926 1.1 jdc */
927 1.1 jdc void
928 1.1 jdc cas_stop(struct ifnet *ifp, int disable)
929 1.1 jdc {
930 1.1 jdc struct cas_softc *sc = (struct cas_softc *)ifp->if_softc;
931 1.1 jdc struct cas_sxd *sd;
932 1.33 msaitoh uint32_t i;
933 1.1 jdc
934 1.1 jdc DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev)));
935 1.1 jdc
936 1.1 jdc callout_stop(&sc->sc_tick_ch);
937 1.1 jdc
938 1.1 jdc /*
939 1.1 jdc * Mark the interface down and cancel the watchdog timer.
940 1.1 jdc */
941 1.1 jdc ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
942 1.1 jdc ifp->if_timer = 0;
943 1.1 jdc
944 1.1 jdc mii_down(&sc->sc_mii);
945 1.1 jdc
946 1.1 jdc cas_reset_rx(sc);
947 1.1 jdc cas_reset_tx(sc);
948 1.1 jdc
949 1.1 jdc /*
950 1.1 jdc * Release any queued transmit buffers.
951 1.1 jdc */
952 1.1 jdc for (i = 0; i < CAS_NTXDESC; i++) {
953 1.1 jdc sd = &sc->sc_txd[i];
954 1.1 jdc if (sd->sd_mbuf != NULL) {
955 1.1 jdc bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
956 1.1 jdc sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
957 1.1 jdc bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
958 1.1 jdc m_freem(sd->sd_mbuf);
959 1.1 jdc sd->sd_mbuf = NULL;
960 1.1 jdc }
961 1.1 jdc }
962 1.1 jdc sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0;
963 1.1 jdc
964 1.1 jdc if (disable)
965 1.1 jdc cas_rxdrain(sc);
966 1.1 jdc }
967 1.1 jdc
968 1.1 jdc
969 1.1 jdc /*
970 1.1 jdc * Reset the receiver
971 1.1 jdc */
972 1.1 jdc int
973 1.1 jdc cas_reset_rx(struct cas_softc *sc)
974 1.1 jdc {
975 1.1 jdc bus_space_tag_t t = sc->sc_memt;
976 1.1 jdc bus_space_handle_t h = sc->sc_memh;
977 1.1 jdc
978 1.1 jdc /*
979 1.1 jdc * Resetting while DMA is in progress can cause a bus hang, so we
980 1.1 jdc * disable DMA first.
981 1.1 jdc */
982 1.1 jdc cas_disable_rx(sc);
983 1.1 jdc bus_space_write_4(t, h, CAS_RX_CONFIG, 0);
984 1.1 jdc /* Wait till it finishes */
985 1.1 jdc if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0))
986 1.1 jdc aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n");
987 1.1 jdc /* Wait 5ms extra. */
988 1.1 jdc delay(5000);
989 1.1 jdc
990 1.1 jdc /* Finally, reset the ERX */
991 1.1 jdc bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX);
992 1.1 jdc /* Wait till it finishes */
993 1.1 jdc if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) {
994 1.1 jdc aprint_error_dev(sc->sc_dev, "cannot reset receiver\n");
995 1.1 jdc return (1);
996 1.1 jdc }
997 1.1 jdc return (0);
998 1.1 jdc }
999 1.1 jdc
1000 1.1 jdc
1001 1.1 jdc /*
1002 1.1 jdc * Reset the transmitter
1003 1.1 jdc */
1004 1.1 jdc int
1005 1.1 jdc cas_reset_tx(struct cas_softc *sc)
1006 1.1 jdc {
1007 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1008 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1009 1.1 jdc
1010 1.1 jdc /*
1011 1.1 jdc * Resetting while DMA is in progress can cause a bus hang, so we
1012 1.1 jdc * disable DMA first.
1013 1.1 jdc */
1014 1.1 jdc cas_disable_tx(sc);
1015 1.1 jdc bus_space_write_4(t, h, CAS_TX_CONFIG, 0);
1016 1.1 jdc /* Wait till it finishes */
1017 1.1 jdc if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0))
1018 1.1 jdc aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n");
1019 1.1 jdc /* Wait 5ms extra. */
1020 1.1 jdc delay(5000);
1021 1.1 jdc
1022 1.1 jdc /* Finally, reset the ETX */
1023 1.1 jdc bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX);
1024 1.1 jdc /* Wait till it finishes */
1025 1.1 jdc if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) {
1026 1.1 jdc aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n");
1027 1.1 jdc return (1);
1028 1.1 jdc }
1029 1.1 jdc return (0);
1030 1.1 jdc }
1031 1.1 jdc
1032 1.1 jdc /*
1033 1.1 jdc * Disable receiver.
1034 1.1 jdc */
1035 1.1 jdc int
1036 1.1 jdc cas_disable_rx(struct cas_softc *sc)
1037 1.1 jdc {
1038 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1039 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1040 1.33 msaitoh uint32_t cfg;
1041 1.1 jdc
1042 1.1 jdc /* Flip the enable bit */
1043 1.1 jdc cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG);
1044 1.1 jdc cfg &= ~CAS_MAC_RX_ENABLE;
1045 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg);
1046 1.1 jdc
1047 1.1 jdc /* Wait for it to finish */
1048 1.1 jdc return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0));
1049 1.1 jdc }
1050 1.1 jdc
1051 1.1 jdc /*
1052 1.1 jdc * Disable transmitter.
1053 1.1 jdc */
1054 1.1 jdc int
1055 1.1 jdc cas_disable_tx(struct cas_softc *sc)
1056 1.1 jdc {
1057 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1058 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1059 1.33 msaitoh uint32_t cfg;
1060 1.1 jdc
1061 1.1 jdc /* Flip the enable bit */
1062 1.1 jdc cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG);
1063 1.1 jdc cfg &= ~CAS_MAC_TX_ENABLE;
1064 1.1 jdc bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg);
1065 1.1 jdc
1066 1.1 jdc /* Wait for it to finish */
1067 1.1 jdc return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0));
1068 1.1 jdc }
1069 1.1 jdc
1070 1.1 jdc /*
1071 1.1 jdc * Initialize interface.
1072 1.1 jdc */
1073 1.1 jdc int
1074 1.1 jdc cas_meminit(struct cas_softc *sc)
1075 1.1 jdc {
1076 1.20 martin int i;
1077 1.1 jdc
1078 1.1 jdc /*
1079 1.1 jdc * Initialize the transmit descriptor ring.
1080 1.1 jdc */
1081 1.1 jdc for (i = 0; i < CAS_NTXDESC; i++) {
1082 1.1 jdc sc->sc_txdescs[i].cd_flags = 0;
1083 1.1 jdc sc->sc_txdescs[i].cd_addr = 0;
1084 1.1 jdc }
1085 1.1 jdc CAS_CDTXSYNC(sc, 0, CAS_NTXDESC,
1086 1.33 msaitoh BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1087 1.1 jdc
1088 1.1 jdc /*
1089 1.1 jdc * Initialize the receive descriptor and receive job
1090 1.1 jdc * descriptor rings.
1091 1.1 jdc */
1092 1.1 jdc for (i = 0; i < CAS_NRXDESC; i++)
1093 1.1 jdc CAS_INIT_RXDESC(sc, i, i);
1094 1.1 jdc sc->sc_rxdptr = 0;
1095 1.1 jdc sc->sc_rxptr = 0;
1096 1.1 jdc
1097 1.1 jdc /*
1098 1.1 jdc * Initialize the receive completion ring.
1099 1.1 jdc */
1100 1.1 jdc for (i = 0; i < CAS_NRXCOMP; i++) {
1101 1.1 jdc sc->sc_rxcomps[i].cc_word[0] = 0;
1102 1.1 jdc sc->sc_rxcomps[i].cc_word[1] = 0;
1103 1.1 jdc sc->sc_rxcomps[i].cc_word[2] = 0;
1104 1.1 jdc sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN);
1105 1.1 jdc CAS_CDRXCSYNC(sc, i,
1106 1.33 msaitoh BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1107 1.1 jdc }
1108 1.1 jdc
1109 1.1 jdc return (0);
1110 1.1 jdc }
1111 1.1 jdc
1112 1.1 jdc int
1113 1.1 jdc cas_ringsize(int sz)
1114 1.1 jdc {
1115 1.1 jdc switch (sz) {
1116 1.1 jdc case 32:
1117 1.1 jdc return CAS_RING_SZ_32;
1118 1.1 jdc case 64:
1119 1.1 jdc return CAS_RING_SZ_64;
1120 1.1 jdc case 128:
1121 1.1 jdc return CAS_RING_SZ_128;
1122 1.1 jdc case 256:
1123 1.1 jdc return CAS_RING_SZ_256;
1124 1.1 jdc case 512:
1125 1.1 jdc return CAS_RING_SZ_512;
1126 1.1 jdc case 1024:
1127 1.1 jdc return CAS_RING_SZ_1024;
1128 1.1 jdc case 2048:
1129 1.1 jdc return CAS_RING_SZ_2048;
1130 1.1 jdc case 4096:
1131 1.1 jdc return CAS_RING_SZ_4096;
1132 1.1 jdc case 8192:
1133 1.1 jdc return CAS_RING_SZ_8192;
1134 1.1 jdc default:
1135 1.1 jdc aprint_error("cas: invalid Receive Descriptor ring size %d\n",
1136 1.1 jdc sz);
1137 1.1 jdc return CAS_RING_SZ_32;
1138 1.1 jdc }
1139 1.1 jdc }
1140 1.1 jdc
1141 1.1 jdc int
1142 1.1 jdc cas_cringsize(int sz)
1143 1.1 jdc {
1144 1.1 jdc int i;
1145 1.1 jdc
1146 1.1 jdc for (i = 0; i < 9; i++)
1147 1.1 jdc if (sz == (128 << i))
1148 1.1 jdc return i;
1149 1.1 jdc
1150 1.1 jdc aprint_error("cas: invalid completion ring size %d\n", sz);
1151 1.1 jdc return 128;
1152 1.1 jdc }
1153 1.1 jdc
1154 1.1 jdc /*
1155 1.1 jdc * Initialization of interface; set up initialization block
1156 1.1 jdc * and transmit/receive descriptor rings.
1157 1.1 jdc */
1158 1.1 jdc int
1159 1.1 jdc cas_init(struct ifnet *ifp)
1160 1.1 jdc {
1161 1.1 jdc struct cas_softc *sc = (struct cas_softc *)ifp->if_softc;
1162 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1163 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1164 1.1 jdc int s;
1165 1.1 jdc u_int max_frame_size;
1166 1.33 msaitoh uint32_t v;
1167 1.1 jdc
1168 1.1 jdc s = splnet();
1169 1.1 jdc
1170 1.1 jdc DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev)));
1171 1.1 jdc /*
1172 1.1 jdc * Initialization sequence. The numbered steps below correspond
1173 1.1 jdc * to the sequence outlined in section 6.3.5.1 in the Ethernet
1174 1.1 jdc * Channel Engine manual (part of the PCIO manual).
1175 1.1 jdc * See also the STP2002-STQ document from Sun Microsystems.
1176 1.1 jdc */
1177 1.1 jdc
1178 1.1 jdc /* step 1 & 2. Reset the Ethernet Channel */
1179 1.1 jdc cas_stop(ifp, 0);
1180 1.1 jdc cas_reset(sc);
1181 1.1 jdc DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev)));
1182 1.1 jdc
1183 1.1 jdc /* Re-initialize the MIF */
1184 1.1 jdc cas_mifinit(sc);
1185 1.1 jdc
1186 1.1 jdc /* step 3. Setup data structures in host memory */
1187 1.1 jdc cas_meminit(sc);
1188 1.1 jdc
1189 1.1 jdc /* step 4. TX MAC registers & counters */
1190 1.1 jdc cas_init_regs(sc);
1191 1.1 jdc max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN;
1192 1.1 jdc v = (max_frame_size) | (0x2000 << 16) /* Burst size */;
1193 1.1 jdc bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v);
1194 1.1 jdc
1195 1.1 jdc /* step 5. RX MAC registers & counters */
1196 1.1 jdc cas_iff(sc);
1197 1.1 jdc
1198 1.1 jdc /* step 6 & 7. Program Descriptor Ring Base Addresses */
1199 1.1 jdc KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0);
1200 1.1 jdc bus_space_write_4(t, h, CAS_TX_RING_PTR_HI,
1201 1.42 thorpej BUS_ADDR_HI32(CAS_CDTXADDR(sc, 0)));
1202 1.42 thorpej bus_space_write_4(t, h, CAS_TX_RING_PTR_LO,
1203 1.42 thorpej BUS_ADDR_LO32(CAS_CDTXADDR(sc, 0)));
1204 1.1 jdc
1205 1.1 jdc KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0);
1206 1.1 jdc bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI,
1207 1.42 thorpej BUS_ADDR_HI32(CAS_CDRXADDR(sc, 0)));
1208 1.42 thorpej bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO,
1209 1.42 thorpej BUS_ADDR_LO32(CAS_CDRXADDR(sc, 0)));
1210 1.1 jdc
1211 1.1 jdc KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0);
1212 1.1 jdc bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI,
1213 1.42 thorpej BUS_ADDR_HI32(CAS_CDRXCADDR(sc, 0)));
1214 1.42 thorpej bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO,
1215 1.42 thorpej BUS_ADDR_LO32(CAS_CDRXCADDR(sc, 0)));
1216 1.1 jdc
1217 1.1 jdc if (CAS_PLUS(sc)) {
1218 1.1 jdc KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0);
1219 1.1 jdc bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2,
1220 1.42 thorpej BUS_ADDR_HI32(CAS_CDRXADDR2(sc, 0)));
1221 1.1 jdc bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2,
1222 1.42 thorpej BUS_ADDR_LO32(CAS_CDRXADDR2(sc, 0)));
1223 1.1 jdc }
1224 1.1 jdc
1225 1.1 jdc /* step 8. Global Configuration & Interrupt Mask */
1226 1.3 jdc cas_estintr(sc, CAS_INTR_REG);
1227 1.1 jdc
1228 1.1 jdc /* step 9. ETX Configuration: use mostly default values */
1229 1.1 jdc
1230 1.1 jdc /* Enable DMA */
1231 1.1 jdc v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10;
1232 1.1 jdc bus_space_write_4(t, h, CAS_TX_CONFIG,
1233 1.33 msaitoh v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29));
1234 1.1 jdc bus_space_write_4(t, h, CAS_TX_KICK, 0);
1235 1.1 jdc
1236 1.1 jdc /* step 10. ERX Configuration */
1237 1.1 jdc
1238 1.1 jdc /* Encode Receive Descriptor ring size */
1239 1.1 jdc v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT;
1240 1.1 jdc if (CAS_PLUS(sc))
1241 1.1 jdc v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT;
1242 1.1 jdc
1243 1.1 jdc /* Encode Receive Completion ring size */
1244 1.1 jdc v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT;
1245 1.1 jdc
1246 1.1 jdc /* Enable DMA */
1247 1.1 jdc bus_space_write_4(t, h, CAS_RX_CONFIG,
1248 1.33 msaitoh v|(2<<CAS_RX_CONFIG_FBOFF_SHFT) | CAS_RX_CONFIG_RXDMA_EN);
1249 1.1 jdc
1250 1.1 jdc /*
1251 1.1 jdc * The following value is for an OFF Threshold of about 3/4 full
1252 1.1 jdc * and an ON Threshold of 1/4 full.
1253 1.1 jdc */
1254 1.1 jdc bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH,
1255 1.1 jdc (3 * sc->sc_rxfifosize / 256) |
1256 1.1 jdc ((sc->sc_rxfifosize / 256) << 12));
1257 1.1 jdc bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6);
1258 1.1 jdc
1259 1.1 jdc /* step 11. Configure Media */
1260 1.1 jdc mii_ifmedia_change(&sc->sc_mii);
1261 1.1 jdc
1262 1.1 jdc /* step 12. RX_MAC Configuration Register */
1263 1.1 jdc v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG);
1264 1.1 jdc v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC;
1265 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v);
1266 1.1 jdc
1267 1.1 jdc /* step 14. Issue Transmit Pending command */
1268 1.1 jdc
1269 1.1 jdc /* step 15. Give the receiver a swift kick */
1270 1.1 jdc bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4);
1271 1.1 jdc if (CAS_PLUS(sc))
1272 1.1 jdc bus_space_write_4(t, h, CAS_RX_KICK2, 4);
1273 1.1 jdc
1274 1.1 jdc /* Start the one second timer. */
1275 1.40 thorpej callout_schedule(&sc->sc_tick_ch, hz);
1276 1.1 jdc
1277 1.1 jdc ifp->if_flags |= IFF_RUNNING;
1278 1.1 jdc ifp->if_flags &= ~IFF_OACTIVE;
1279 1.1 jdc ifp->if_timer = 0;
1280 1.1 jdc splx(s);
1281 1.1 jdc
1282 1.1 jdc return (0);
1283 1.1 jdc }
1284 1.1 jdc
1285 1.1 jdc void
1286 1.1 jdc cas_init_regs(struct cas_softc *sc)
1287 1.1 jdc {
1288 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1289 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1290 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1291 1.1 jdc const u_char *laddr = CLLADDR(ifp->if_sadl);
1292 1.33 msaitoh uint32_t v, r;
1293 1.1 jdc
1294 1.1 jdc /* These regs are not cleared on reset */
1295 1.1 jdc sc->sc_inited = 0;
1296 1.1 jdc if (!sc->sc_inited) {
1297 1.1 jdc /* Load recommended values */
1298 1.1 jdc bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00);
1299 1.1 jdc bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08);
1300 1.1 jdc bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04);
1301 1.1 jdc
1302 1.1 jdc bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1303 1.1 jdc /* Max frame and max burst size */
1304 1.1 jdc v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */;
1305 1.1 jdc bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v);
1306 1.1 jdc
1307 1.1 jdc bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07);
1308 1.1 jdc bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04);
1309 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10);
1310 1.1 jdc bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088);
1311 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED,
1312 1.1 jdc ((laddr[5]<<8)|laddr[4])&0x3ff);
1313 1.1 jdc
1314 1.1 jdc /* Secondary MAC addresses set to 0:0:0:0:0:0 */
1315 1.1 jdc for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4)
1316 1.3 jdc bus_space_write_4(t, h, r, 0);
1317 1.1 jdc
1318 1.1 jdc /* MAC control addr set to 0:1:c2:0:1:80 */
1319 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001);
1320 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200);
1321 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180);
1322 1.1 jdc
1323 1.1 jdc /* MAC filter addr set to 0:0:0:0:0:0 */
1324 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0);
1325 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0);
1326 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0);
1327 1.1 jdc
1328 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0);
1329 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0);
1330 1.1 jdc
1331 1.1 jdc /* Hash table initialized to 0 */
1332 1.1 jdc for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4)
1333 1.1 jdc bus_space_write_4(t, h, r, 0);
1334 1.1 jdc
1335 1.1 jdc sc->sc_inited = 1;
1336 1.1 jdc }
1337 1.1 jdc
1338 1.1 jdc /* Counters need to be zeroed */
1339 1.1 jdc bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0);
1340 1.1 jdc bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0);
1341 1.1 jdc bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0);
1342 1.1 jdc bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0);
1343 1.1 jdc bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0);
1344 1.1 jdc bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0);
1345 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0);
1346 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0);
1347 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0);
1348 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0);
1349 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0);
1350 1.1 jdc
1351 1.1 jdc /* Un-pause stuff */
1352 1.1 jdc bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0);
1353 1.1 jdc
1354 1.1 jdc /*
1355 1.1 jdc * Set the station address.
1356 1.1 jdc */
1357 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]);
1358 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]);
1359 1.1 jdc bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]);
1360 1.1 jdc }
1361 1.1 jdc
1362 1.1 jdc /*
1363 1.1 jdc * Receive interrupt.
1364 1.1 jdc */
1365 1.1 jdc int
1366 1.1 jdc cas_rint(struct cas_softc *sc)
1367 1.1 jdc {
1368 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1369 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1370 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1371 1.1 jdc struct cas_rxsoft *rxs;
1372 1.1 jdc struct mbuf *m;
1373 1.33 msaitoh uint64_t word[4];
1374 1.1 jdc int len, off, idx;
1375 1.1 jdc int i, skip;
1376 1.1 jdc void *cp;
1377 1.1 jdc
1378 1.1 jdc for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) {
1379 1.1 jdc CAS_CDRXCSYNC(sc, i,
1380 1.33 msaitoh BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1381 1.1 jdc
1382 1.1 jdc word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]);
1383 1.1 jdc word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]);
1384 1.1 jdc word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]);
1385 1.1 jdc word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]);
1386 1.1 jdc
1387 1.1 jdc /* Stop if the hardware still owns the descriptor. */
1388 1.1 jdc if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN)
1389 1.1 jdc break;
1390 1.1 jdc
1391 1.1 jdc len = CAS_RC1_HDR_LEN(word[1]);
1392 1.1 jdc if (len > 0) {
1393 1.1 jdc off = CAS_RC1_HDR_OFF(word[1]);
1394 1.1 jdc idx = CAS_RC1_HDR_IDX(word[1]);
1395 1.1 jdc rxs = &sc->sc_rxsoft[idx];
1396 1.1 jdc
1397 1.1 jdc DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n",
1398 1.1 jdc idx, off, len));
1399 1.1 jdc
1400 1.1 jdc bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
1401 1.1 jdc rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1402 1.1 jdc
1403 1.1 jdc cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN;
1404 1.28 maxv m = m_devget(cp, len, 0, ifp);
1405 1.33 msaitoh
1406 1.1 jdc if (word[0] & CAS_RC0_RELEASE_HDR)
1407 1.1 jdc cas_add_rxbuf(sc, idx);
1408 1.1 jdc
1409 1.1 jdc if (m != NULL) {
1410 1.1 jdc
1411 1.1 jdc /*
1412 1.1 jdc * Pass this up to any BPF listeners, but only
1413 1.1 jdc * pass it up the stack if its for us.
1414 1.1 jdc */
1415 1.1 jdc m->m_pkthdr.csum_flags = 0;
1416 1.24 ozaki if_percpuq_enqueue(ifp->if_percpuq, m);
1417 1.1 jdc } else
1418 1.38 thorpej if_statinc(ifp, if_ierrors);
1419 1.1 jdc }
1420 1.1 jdc
1421 1.1 jdc len = CAS_RC0_DATA_LEN(word[0]);
1422 1.1 jdc if (len > 0) {
1423 1.1 jdc off = CAS_RC0_DATA_OFF(word[0]);
1424 1.1 jdc idx = CAS_RC0_DATA_IDX(word[0]);
1425 1.1 jdc rxs = &sc->sc_rxsoft[idx];
1426 1.1 jdc
1427 1.1 jdc DPRINTF(sc, ("data at idx %d, off %d, len %d\n",
1428 1.1 jdc idx, off, len));
1429 1.1 jdc
1430 1.1 jdc bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
1431 1.1 jdc rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1432 1.1 jdc
1433 1.1 jdc /* XXX We should not be copying the packet here. */
1434 1.1 jdc cp = rxs->rxs_kva + off + ETHER_ALIGN;
1435 1.28 maxv m = m_devget(cp, len, 0, ifp);
1436 1.1 jdc
1437 1.1 jdc if (word[0] & CAS_RC0_RELEASE_DATA)
1438 1.1 jdc cas_add_rxbuf(sc, idx);
1439 1.1 jdc
1440 1.1 jdc if (m != NULL) {
1441 1.1 jdc /*
1442 1.1 jdc * Pass this up to any BPF listeners, but only
1443 1.1 jdc * pass it up the stack if its for us.
1444 1.1 jdc */
1445 1.1 jdc m->m_pkthdr.csum_flags = 0;
1446 1.24 ozaki if_percpuq_enqueue(ifp->if_percpuq, m);
1447 1.1 jdc } else
1448 1.38 thorpej if_statinc(ifp, if_ierrors);
1449 1.1 jdc }
1450 1.1 jdc
1451 1.1 jdc if (word[0] & CAS_RC0_SPLIT)
1452 1.1 jdc aprint_error_dev(sc->sc_dev, "split packet\n");
1453 1.1 jdc
1454 1.1 jdc skip = CAS_RC0_SKIP(word[0]);
1455 1.1 jdc }
1456 1.1 jdc
1457 1.1 jdc while (sc->sc_rxptr != i) {
1458 1.1 jdc sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0;
1459 1.1 jdc sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0;
1460 1.1 jdc sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0;
1461 1.1 jdc sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] =
1462 1.1 jdc CAS_DMA_WRITE(CAS_RC3_OWN);
1463 1.1 jdc CAS_CDRXCSYNC(sc, sc->sc_rxptr,
1464 1.33 msaitoh BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1465 1.1 jdc
1466 1.1 jdc sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr);
1467 1.1 jdc }
1468 1.1 jdc
1469 1.1 jdc bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr);
1470 1.1 jdc
1471 1.1 jdc DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n",
1472 1.1 jdc sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION)));
1473 1.1 jdc
1474 1.1 jdc return (1);
1475 1.1 jdc }
1476 1.1 jdc
1477 1.1 jdc /*
1478 1.1 jdc * cas_add_rxbuf:
1479 1.1 jdc *
1480 1.1 jdc * Add a receive buffer to the indicated descriptor.
1481 1.1 jdc */
1482 1.1 jdc int
1483 1.1 jdc cas_add_rxbuf(struct cas_softc *sc, int idx)
1484 1.1 jdc {
1485 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1486 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1487 1.1 jdc
1488 1.1 jdc CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx);
1489 1.1 jdc
1490 1.1 jdc if ((sc->sc_rxdptr % 4) == 0)
1491 1.1 jdc bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr);
1492 1.1 jdc
1493 1.1 jdc if (++sc->sc_rxdptr == CAS_NRXDESC)
1494 1.1 jdc sc->sc_rxdptr = 0;
1495 1.1 jdc
1496 1.1 jdc return (0);
1497 1.1 jdc }
1498 1.1 jdc
1499 1.1 jdc int
1500 1.1 jdc cas_eint(struct cas_softc *sc, u_int status)
1501 1.1 jdc {
1502 1.1 jdc char bits[128];
1503 1.1 jdc if ((status & CAS_INTR_MIF) != 0) {
1504 1.1 jdc DPRINTF(sc, ("%s: link status changed\n",
1505 1.1 jdc device_xname(sc->sc_dev)));
1506 1.1 jdc return (1);
1507 1.1 jdc }
1508 1.1 jdc
1509 1.1 jdc snprintb(bits, sizeof(bits), CAS_INTR_BITS, status);
1510 1.1 jdc printf("%s: status=%s\n", device_xname(sc->sc_dev), bits);
1511 1.1 jdc return (1);
1512 1.1 jdc }
1513 1.1 jdc
1514 1.1 jdc int
1515 1.1 jdc cas_pint(struct cas_softc *sc)
1516 1.1 jdc {
1517 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1518 1.1 jdc bus_space_handle_t seb = sc->sc_memh;
1519 1.33 msaitoh uint32_t status;
1520 1.1 jdc
1521 1.1 jdc status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS);
1522 1.1 jdc status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS);
1523 1.1 jdc #ifdef CAS_DEBUG
1524 1.1 jdc if (status)
1525 1.1 jdc printf("%s: link status changed\n", device_xname(sc->sc_dev));
1526 1.1 jdc #endif
1527 1.1 jdc return (1);
1528 1.1 jdc }
1529 1.1 jdc
1530 1.1 jdc int
1531 1.1 jdc cas_intr(void *v)
1532 1.1 jdc {
1533 1.1 jdc struct cas_softc *sc = (struct cas_softc *)v;
1534 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1535 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1536 1.1 jdc bus_space_handle_t seb = sc->sc_memh;
1537 1.33 msaitoh uint32_t status;
1538 1.1 jdc int r = 0;
1539 1.1 jdc #ifdef CAS_DEBUG
1540 1.1 jdc char bits[128];
1541 1.1 jdc #endif
1542 1.1 jdc
1543 1.1 jdc sc->sc_ev_intr.ev_count++;
1544 1.1 jdc
1545 1.1 jdc status = bus_space_read_4(t, seb, CAS_STATUS);
1546 1.1 jdc #ifdef CAS_DEBUG
1547 1.1 jdc snprintb(bits, sizeof(bits), CAS_INTR_BITS, status);
1548 1.1 jdc #endif
1549 1.1 jdc DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n",
1550 1.1 jdc device_xname(sc->sc_dev), (status>>19), bits));
1551 1.1 jdc
1552 1.1 jdc if ((status & CAS_INTR_PCS) != 0)
1553 1.1 jdc r |= cas_pint(sc);
1554 1.1 jdc
1555 1.1 jdc if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR |
1556 1.1 jdc CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0)
1557 1.1 jdc r |= cas_eint(sc, status);
1558 1.1 jdc
1559 1.1 jdc if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0)
1560 1.1 jdc r |= cas_tint(sc, status);
1561 1.1 jdc
1562 1.1 jdc if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0)
1563 1.1 jdc r |= cas_rint(sc);
1564 1.1 jdc
1565 1.1 jdc /* We should eventually do more than just print out error stats. */
1566 1.1 jdc if (status & CAS_INTR_TX_MAC) {
1567 1.1 jdc int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS);
1568 1.1 jdc #ifdef CAS_DEBUG
1569 1.1 jdc if (txstat & ~CAS_MAC_TX_XMIT_DONE)
1570 1.1 jdc printf("%s: MAC tx fault, status %x\n",
1571 1.1 jdc device_xname(sc->sc_dev), txstat);
1572 1.1 jdc #endif
1573 1.1 jdc if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG))
1574 1.1 jdc cas_init(ifp);
1575 1.1 jdc }
1576 1.1 jdc if (status & CAS_INTR_RX_MAC) {
1577 1.1 jdc int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS);
1578 1.1 jdc #ifdef CAS_DEBUG
1579 1.3 jdc if (rxstat & ~CAS_MAC_RX_DONE)
1580 1.3 jdc printf("%s: MAC rx fault, status %x\n",
1581 1.3 jdc device_xname(sc->sc_dev), rxstat);
1582 1.1 jdc #endif
1583 1.1 jdc /*
1584 1.1 jdc * On some chip revisions CAS_MAC_RX_OVERFLOW happen often
1585 1.1 jdc * due to a silicon bug so handle them silently.
1586 1.1 jdc */
1587 1.1 jdc if (rxstat & CAS_MAC_RX_OVERFLOW) {
1588 1.38 thorpej if_statinc(ifp, if_ierrors);
1589 1.1 jdc cas_init(ifp);
1590 1.1 jdc }
1591 1.1 jdc #ifdef CAS_DEBUG
1592 1.1 jdc else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT))
1593 1.1 jdc printf("%s: MAC rx fault, status %x\n",
1594 1.1 jdc device_xname(sc->sc_dev), rxstat);
1595 1.1 jdc #endif
1596 1.1 jdc }
1597 1.1 jdc rnd_add_uint32(&sc->rnd_source, status);
1598 1.1 jdc return (r);
1599 1.1 jdc }
1600 1.1 jdc
1601 1.1 jdc
1602 1.1 jdc void
1603 1.1 jdc cas_watchdog(struct ifnet *ifp)
1604 1.1 jdc {
1605 1.1 jdc struct cas_softc *sc = ifp->if_softc;
1606 1.1 jdc
1607 1.1 jdc DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x "
1608 1.1 jdc "CAS_MAC_RX_CONFIG %x\n",
1609 1.1 jdc bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG),
1610 1.1 jdc bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS),
1611 1.1 jdc bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG)));
1612 1.1 jdc
1613 1.1 jdc log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev));
1614 1.38 thorpej if_statinc(ifp, if_oerrors);
1615 1.1 jdc
1616 1.1 jdc /* Try to get more packets going. */
1617 1.1 jdc cas_init(ifp);
1618 1.1 jdc }
1619 1.1 jdc
1620 1.1 jdc /*
1621 1.1 jdc * Initialize the MII Management Interface
1622 1.1 jdc */
1623 1.1 jdc void
1624 1.1 jdc cas_mifinit(struct cas_softc *sc)
1625 1.1 jdc {
1626 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1627 1.1 jdc bus_space_handle_t mif = sc->sc_memh;
1628 1.1 jdc
1629 1.1 jdc /* Configure the MIF in frame mode */
1630 1.1 jdc sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG);
1631 1.1 jdc sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA;
1632 1.1 jdc bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config);
1633 1.1 jdc }
1634 1.1 jdc
1635 1.1 jdc /*
1636 1.1 jdc * MII interface
1637 1.1 jdc *
1638 1.1 jdc * The Cassini MII interface supports at least three different operating modes:
1639 1.1 jdc *
1640 1.1 jdc * Bitbang mode is implemented using data, clock and output enable registers.
1641 1.1 jdc *
1642 1.1 jdc * Frame mode is implemented by loading a complete frame into the frame
1643 1.1 jdc * register and polling the valid bit for completion.
1644 1.1 jdc *
1645 1.1 jdc * Polling mode uses the frame register but completion is indicated by
1646 1.1 jdc * an interrupt.
1647 1.1 jdc *
1648 1.1 jdc */
1649 1.1 jdc int
1650 1.30 msaitoh cas_mii_readreg(device_t self, int phy, int reg, uint16_t *val)
1651 1.1 jdc {
1652 1.1 jdc struct cas_softc *sc = device_private(self);
1653 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1654 1.1 jdc bus_space_handle_t mif = sc->sc_memh;
1655 1.1 jdc int n;
1656 1.33 msaitoh uint32_t v;
1657 1.1 jdc
1658 1.1 jdc #ifdef CAS_DEBUG
1659 1.1 jdc if (sc->sc_debug)
1660 1.1 jdc printf("cas_mii_readreg: phy %d reg %d\n", phy, reg);
1661 1.1 jdc #endif
1662 1.1 jdc
1663 1.1 jdc /* Construct the frame command */
1664 1.1 jdc v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) |
1665 1.1 jdc CAS_MIF_FRAME_READ;
1666 1.1 jdc
1667 1.1 jdc bus_space_write_4(t, mif, CAS_MIF_FRAME, v);
1668 1.1 jdc for (n = 0; n < 100; n++) {
1669 1.1 jdc DELAY(1);
1670 1.1 jdc v = bus_space_read_4(t, mif, CAS_MIF_FRAME);
1671 1.30 msaitoh if (v & CAS_MIF_FRAME_TA0) {
1672 1.30 msaitoh *val = v & CAS_MIF_FRAME_DATA;
1673 1.30 msaitoh return 0;
1674 1.30 msaitoh }
1675 1.1 jdc }
1676 1.1 jdc
1677 1.1 jdc printf("%s: mii_read timeout\n", device_xname(sc->sc_dev));
1678 1.30 msaitoh return ETIMEDOUT;
1679 1.1 jdc }
1680 1.1 jdc
1681 1.30 msaitoh int
1682 1.30 msaitoh cas_mii_writereg(device_t self, int phy, int reg, uint16_t val)
1683 1.1 jdc {
1684 1.1 jdc struct cas_softc *sc = device_private(self);
1685 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1686 1.1 jdc bus_space_handle_t mif = sc->sc_memh;
1687 1.1 jdc int n;
1688 1.33 msaitoh uint32_t v;
1689 1.1 jdc
1690 1.1 jdc #ifdef CAS_DEBUG
1691 1.1 jdc if (sc->sc_debug)
1692 1.1 jdc printf("cas_mii_writereg: phy %d reg %d val %x\n",
1693 1.1 jdc phy, reg, val);
1694 1.1 jdc #endif
1695 1.1 jdc
1696 1.1 jdc /* Construct the frame command */
1697 1.1 jdc v = CAS_MIF_FRAME_WRITE |
1698 1.1 jdc (phy << CAS_MIF_PHY_SHIFT) |
1699 1.1 jdc (reg << CAS_MIF_REG_SHIFT) |
1700 1.1 jdc (val & CAS_MIF_FRAME_DATA);
1701 1.1 jdc
1702 1.1 jdc bus_space_write_4(t, mif, CAS_MIF_FRAME, v);
1703 1.1 jdc for (n = 0; n < 100; n++) {
1704 1.1 jdc DELAY(1);
1705 1.1 jdc v = bus_space_read_4(t, mif, CAS_MIF_FRAME);
1706 1.1 jdc if (v & CAS_MIF_FRAME_TA0)
1707 1.30 msaitoh return 0;
1708 1.1 jdc }
1709 1.1 jdc
1710 1.1 jdc printf("%s: mii_write timeout\n", device_xname(sc->sc_dev));
1711 1.30 msaitoh return ETIMEDOUT;
1712 1.1 jdc }
1713 1.1 jdc
1714 1.1 jdc void
1715 1.18 matt cas_mii_statchg(struct ifnet *ifp)
1716 1.1 jdc {
1717 1.18 matt struct cas_softc *sc = ifp->if_softc;
1718 1.1 jdc #ifdef CAS_DEBUG
1719 1.1 jdc int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media);
1720 1.1 jdc #endif
1721 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1722 1.1 jdc bus_space_handle_t mac = sc->sc_memh;
1723 1.33 msaitoh uint32_t v;
1724 1.1 jdc
1725 1.1 jdc #ifdef CAS_DEBUG
1726 1.1 jdc if (sc->sc_debug)
1727 1.1 jdc printf("cas_mii_statchg: status change: phy = %d\n",
1728 1.1 jdc sc->sc_phys[instance]);
1729 1.1 jdc #endif
1730 1.1 jdc
1731 1.1 jdc /* Set tx full duplex options */
1732 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0);
1733 1.1 jdc delay(10000); /* reg must be cleared and delay before changing. */
1734 1.33 msaitoh v = CAS_MAC_TX_ENA_IPG0 | CAS_MAC_TX_NGU | CAS_MAC_TX_NGU_LIMIT |
1735 1.1 jdc CAS_MAC_TX_ENABLE;
1736 1.1 jdc if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
1737 1.33 msaitoh v |= CAS_MAC_TX_IGN_CARRIER | CAS_MAC_TX_IGN_COLLIS;
1738 1.1 jdc }
1739 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v);
1740 1.1 jdc
1741 1.1 jdc /* XIF Configuration */
1742 1.1 jdc v = CAS_MAC_XIF_TX_MII_ENA;
1743 1.1 jdc v |= CAS_MAC_XIF_LINK_LED;
1744 1.1 jdc
1745 1.1 jdc /* MII needs echo disable if half duplex. */
1746 1.1 jdc if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
1747 1.1 jdc /* turn on full duplex LED */
1748 1.1 jdc v |= CAS_MAC_XIF_FDPLX_LED;
1749 1.1 jdc else
1750 1.1 jdc /* half duplex -- disable echo */
1751 1.1 jdc v |= CAS_MAC_XIF_ECHO_DISABL;
1752 1.1 jdc
1753 1.1 jdc switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
1754 1.1 jdc case IFM_1000_T: /* Gigabit using GMII interface */
1755 1.1 jdc case IFM_1000_SX:
1756 1.1 jdc v |= CAS_MAC_XIF_GMII_MODE;
1757 1.1 jdc break;
1758 1.1 jdc default:
1759 1.1 jdc v &= ~CAS_MAC_XIF_GMII_MODE;
1760 1.1 jdc }
1761 1.1 jdc bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v);
1762 1.1 jdc }
1763 1.1 jdc
1764 1.1 jdc int
1765 1.30 msaitoh cas_pcs_readreg(device_t self, int phy, int reg, uint16_t *val)
1766 1.1 jdc {
1767 1.1 jdc struct cas_softc *sc = device_private(self);
1768 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1769 1.1 jdc bus_space_handle_t pcs = sc->sc_memh;
1770 1.1 jdc
1771 1.1 jdc #ifdef CAS_DEBUG
1772 1.1 jdc if (sc->sc_debug)
1773 1.1 jdc printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg);
1774 1.1 jdc #endif
1775 1.1 jdc
1776 1.1 jdc if (phy != CAS_PHYAD_EXTERNAL)
1777 1.30 msaitoh return -1;
1778 1.1 jdc
1779 1.1 jdc switch (reg) {
1780 1.1 jdc case MII_BMCR:
1781 1.1 jdc reg = CAS_MII_CONTROL;
1782 1.1 jdc break;
1783 1.1 jdc case MII_BMSR:
1784 1.1 jdc reg = CAS_MII_STATUS;
1785 1.1 jdc break;
1786 1.1 jdc case MII_ANAR:
1787 1.1 jdc reg = CAS_MII_ANAR;
1788 1.1 jdc break;
1789 1.1 jdc case MII_ANLPAR:
1790 1.1 jdc reg = CAS_MII_ANLPAR;
1791 1.1 jdc break;
1792 1.1 jdc case MII_EXTSR:
1793 1.30 msaitoh *val = EXTSR_1000XFDX | EXTSR_1000XHDX;
1794 1.30 msaitoh return 0;
1795 1.1 jdc default:
1796 1.1 jdc return (0);
1797 1.1 jdc }
1798 1.1 jdc
1799 1.30 msaitoh *val = bus_space_read_4(t, pcs, reg) & 0xffff;
1800 1.30 msaitoh return 0;
1801 1.1 jdc }
1802 1.1 jdc
1803 1.30 msaitoh int
1804 1.30 msaitoh cas_pcs_writereg(device_t self, int phy, int reg, uint16_t val)
1805 1.1 jdc {
1806 1.1 jdc struct cas_softc *sc = device_private(self);
1807 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1808 1.1 jdc bus_space_handle_t pcs = sc->sc_memh;
1809 1.1 jdc int reset = 0;
1810 1.1 jdc
1811 1.1 jdc #ifdef CAS_DEBUG
1812 1.1 jdc if (sc->sc_debug)
1813 1.1 jdc printf("cas_pcs_writereg: phy %d reg %d val %x\n",
1814 1.1 jdc phy, reg, val);
1815 1.1 jdc #endif
1816 1.1 jdc
1817 1.1 jdc if (phy != CAS_PHYAD_EXTERNAL)
1818 1.30 msaitoh return -1;
1819 1.1 jdc
1820 1.1 jdc if (reg == MII_ANAR)
1821 1.1 jdc bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0);
1822 1.1 jdc
1823 1.1 jdc switch (reg) {
1824 1.1 jdc case MII_BMCR:
1825 1.1 jdc reset = (val & CAS_MII_CONTROL_RESET);
1826 1.1 jdc reg = CAS_MII_CONTROL;
1827 1.1 jdc break;
1828 1.1 jdc case MII_BMSR:
1829 1.1 jdc reg = CAS_MII_STATUS;
1830 1.1 jdc break;
1831 1.1 jdc case MII_ANAR:
1832 1.1 jdc reg = CAS_MII_ANAR;
1833 1.1 jdc break;
1834 1.1 jdc case MII_ANLPAR:
1835 1.1 jdc reg = CAS_MII_ANLPAR;
1836 1.1 jdc break;
1837 1.1 jdc default:
1838 1.30 msaitoh return 0;
1839 1.1 jdc }
1840 1.1 jdc
1841 1.1 jdc bus_space_write_4(t, pcs, reg, val);
1842 1.1 jdc
1843 1.1 jdc if (reset)
1844 1.1 jdc cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0);
1845 1.1 jdc
1846 1.1 jdc if (reg == CAS_MII_ANAR || reset)
1847 1.1 jdc bus_space_write_4(t, pcs, CAS_MII_CONFIG,
1848 1.1 jdc CAS_MII_CONFIG_ENABLE);
1849 1.30 msaitoh
1850 1.30 msaitoh return 0;
1851 1.1 jdc }
1852 1.1 jdc
1853 1.1 jdc int
1854 1.1 jdc cas_mediachange(struct ifnet *ifp)
1855 1.1 jdc {
1856 1.1 jdc struct cas_softc *sc = ifp->if_softc;
1857 1.1 jdc struct mii_data *mii = &sc->sc_mii;
1858 1.1 jdc
1859 1.1 jdc if (mii->mii_instance) {
1860 1.1 jdc struct mii_softc *miisc;
1861 1.1 jdc LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1862 1.1 jdc mii_phy_reset(miisc);
1863 1.1 jdc }
1864 1.1 jdc
1865 1.1 jdc return (mii_mediachg(&sc->sc_mii));
1866 1.1 jdc }
1867 1.1 jdc
1868 1.1 jdc void
1869 1.1 jdc cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1870 1.1 jdc {
1871 1.1 jdc struct cas_softc *sc = ifp->if_softc;
1872 1.1 jdc
1873 1.1 jdc mii_pollstat(&sc->sc_mii);
1874 1.1 jdc ifmr->ifm_active = sc->sc_mii.mii_media_active;
1875 1.1 jdc ifmr->ifm_status = sc->sc_mii.mii_media_status;
1876 1.1 jdc }
1877 1.1 jdc
1878 1.1 jdc /*
1879 1.1 jdc * Process an ioctl request.
1880 1.1 jdc */
1881 1.1 jdc int
1882 1.1 jdc cas_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1883 1.1 jdc {
1884 1.1 jdc struct cas_softc *sc = ifp->if_softc;
1885 1.1 jdc int s, error = 0;
1886 1.1 jdc
1887 1.1 jdc s = splnet();
1888 1.1 jdc
1889 1.1 jdc if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
1890 1.1 jdc error = 0;
1891 1.1 jdc if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
1892 1.1 jdc ;
1893 1.1 jdc else if (ifp->if_flags & IFF_RUNNING) {
1894 1.1 jdc /*
1895 1.1 jdc * Multicast list has changed; set the hardware filter
1896 1.1 jdc * accordingly.
1897 1.1 jdc */
1898 1.1 jdc cas_iff(sc);
1899 1.1 jdc }
1900 1.1 jdc }
1901 1.1 jdc
1902 1.1 jdc splx(s);
1903 1.1 jdc return (error);
1904 1.1 jdc }
1905 1.1 jdc
1906 1.1 jdc static bool
1907 1.6 dyoung cas_suspend(device_t self, const pmf_qual_t *qual)
1908 1.1 jdc {
1909 1.1 jdc struct cas_softc *sc = device_private(self);
1910 1.3 jdc bus_space_tag_t t = sc->sc_memt;
1911 1.3 jdc bus_space_handle_t h = sc->sc_memh;
1912 1.1 jdc
1913 1.3 jdc bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0);
1914 1.1 jdc if (sc->sc_ih != NULL) {
1915 1.1 jdc pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
1916 1.1 jdc sc->sc_ih = NULL;
1917 1.1 jdc }
1918 1.1 jdc
1919 1.1 jdc return true;
1920 1.1 jdc }
1921 1.1 jdc
1922 1.1 jdc static bool
1923 1.6 dyoung cas_resume(device_t self, const pmf_qual_t *qual)
1924 1.1 jdc {
1925 1.1 jdc struct cas_softc *sc = device_private(self);
1926 1.1 jdc
1927 1.3 jdc return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG);
1928 1.1 jdc }
1929 1.1 jdc
1930 1.1 jdc static bool
1931 1.3 jdc cas_estintr(struct cas_softc *sc, int what)
1932 1.1 jdc {
1933 1.3 jdc bus_space_tag_t t = sc->sc_memt;
1934 1.3 jdc bus_space_handle_t h = sc->sc_memh;
1935 1.1 jdc const char *intrstr = NULL;
1936 1.21 christos char intrbuf[PCI_INTRSTR_LEN];
1937 1.1 jdc
1938 1.3 jdc /* PCI interrupts */
1939 1.3 jdc if (what & CAS_INTR_PCI) {
1940 1.33 msaitoh intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle, intrbuf,
1941 1.33 msaitoh sizeof(intrbuf));
1942 1.29 jdolecek sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_handle,
1943 1.29 jdolecek IPL_NET, cas_intr, sc, device_xname(sc->sc_dev));
1944 1.3 jdc if (sc->sc_ih == NULL) {
1945 1.3 jdc aprint_error_dev(sc->sc_dev,
1946 1.3 jdc "unable to establish interrupt");
1947 1.3 jdc if (intrstr != NULL)
1948 1.3 jdc aprint_error(" at %s", intrstr);
1949 1.3 jdc aprint_error("\n");
1950 1.3 jdc return false;
1951 1.3 jdc }
1952 1.3 jdc
1953 1.3 jdc aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
1954 1.1 jdc }
1955 1.1 jdc
1956 1.3 jdc /* Interrupt register */
1957 1.3 jdc if (what & CAS_INTR_REG) {
1958 1.3 jdc bus_space_write_4(t, h, CAS_INTMASK,
1959 1.33 msaitoh ~(CAS_INTR_TX_INTME | CAS_INTR_TX_EMPTY |
1960 1.33 msaitoh CAS_INTR_TX_TAG_ERR |
1961 1.33 msaitoh CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF |
1962 1.33 msaitoh CAS_INTR_RX_TAG_ERR |
1963 1.33 msaitoh CAS_INTR_RX_COMP_FULL | CAS_INTR_PCS |
1964 1.33 msaitoh CAS_INTR_MAC_CONTROL | CAS_INTR_MIF |
1965 1.3 jdc CAS_INTR_BERR));
1966 1.3 jdc bus_space_write_4(t, h, CAS_MAC_RX_MASK,
1967 1.33 msaitoh CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT);
1968 1.3 jdc bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE);
1969 1.3 jdc bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */
1970 1.3 jdc }
1971 1.1 jdc return true;
1972 1.1 jdc }
1973 1.1 jdc
1974 1.1 jdc bool
1975 1.1 jdc cas_shutdown(device_t self, int howto)
1976 1.1 jdc {
1977 1.1 jdc struct cas_softc *sc = device_private(self);
1978 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1979 1.1 jdc
1980 1.1 jdc cas_stop(ifp, 1);
1981 1.1 jdc
1982 1.1 jdc return true;
1983 1.1 jdc }
1984 1.1 jdc
1985 1.1 jdc void
1986 1.1 jdc cas_iff(struct cas_softc *sc)
1987 1.1 jdc {
1988 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1989 1.1 jdc struct ethercom *ec = &sc->sc_ethercom;
1990 1.1 jdc struct ether_multi *enm;
1991 1.1 jdc struct ether_multistep step;
1992 1.1 jdc bus_space_tag_t t = sc->sc_memt;
1993 1.1 jdc bus_space_handle_t h = sc->sc_memh;
1994 1.33 msaitoh uint32_t crc, hash[16], rxcfg;
1995 1.1 jdc int i;
1996 1.1 jdc
1997 1.1 jdc rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG);
1998 1.1 jdc rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS |
1999 1.1 jdc CAS_MAC_RX_PROMISC_GRP);
2000 1.1 jdc ifp->if_flags &= ~IFF_ALLMULTI;
2001 1.1 jdc
2002 1.36 msaitoh if ((ifp->if_flags & IFF_PROMISC) != 0)
2003 1.36 msaitoh goto update;
2004 1.36 msaitoh
2005 1.36 msaitoh /*
2006 1.36 msaitoh * Set up multicast address filter by passing all multicast
2007 1.36 msaitoh * addresses through a crc generator, and then using the
2008 1.36 msaitoh * high order 8 bits as an index into the 256 bit logical
2009 1.36 msaitoh * address filter. The high order 4 bits selects the word,
2010 1.36 msaitoh * while the other 4 bits select the bit within the word
2011 1.36 msaitoh * (where bit 0 is the MSB).
2012 1.36 msaitoh */
2013 1.36 msaitoh
2014 1.36 msaitoh /* Clear hash table */
2015 1.36 msaitoh for (i = 0; i < 16; i++)
2016 1.36 msaitoh hash[i] = 0;
2017 1.1 jdc
2018 1.36 msaitoh ETHER_LOCK(ec);
2019 1.36 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
2020 1.36 msaitoh while (enm != NULL) {
2021 1.36 msaitoh if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2022 1.36 msaitoh /* XXX Use ETHER_F_ALLMULTI in future. */
2023 1.36 msaitoh ifp->if_flags |= IFF_ALLMULTI;
2024 1.36 msaitoh ETHER_UNLOCK(ec);
2025 1.36 msaitoh goto update;
2026 1.36 msaitoh }
2027 1.1 jdc
2028 1.36 msaitoh crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
2029 1.1 jdc
2030 1.36 msaitoh /* Just want the 8 most significant bits. */
2031 1.36 msaitoh crc >>= 24;
2032 1.1 jdc
2033 1.36 msaitoh /* Set the corresponding bit in the filter. */
2034 1.36 msaitoh hash[crc >> 4] |= 1 << (15 - (crc & 15));
2035 1.1 jdc
2036 1.36 msaitoh ETHER_NEXT_MULTI(step, enm);
2037 1.36 msaitoh }
2038 1.36 msaitoh ETHER_UNLOCK(ec);
2039 1.1 jdc
2040 1.36 msaitoh rxcfg |= CAS_MAC_RX_HASH_FILTER;
2041 1.1 jdc
2042 1.36 msaitoh /* Now load the hash table into the chip (if we are using it) */
2043 1.36 msaitoh for (i = 0; i < 16; i++) {
2044 1.36 msaitoh bus_space_write_4(t, h,
2045 1.36 msaitoh CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
2046 1.36 msaitoh hash[i]);
2047 1.1 jdc }
2048 1.1 jdc
2049 1.36 msaitoh update:
2050 1.36 msaitoh if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2051 1.36 msaitoh if (ifp->if_flags & IFF_PROMISC) {
2052 1.36 msaitoh rxcfg |= CAS_MAC_RX_PROMISCUOUS;
2053 1.36 msaitoh /* XXX Use ETHER_F_ALLMULTI in future. */
2054 1.36 msaitoh ifp->if_flags |= IFF_ALLMULTI;
2055 1.36 msaitoh } else
2056 1.36 msaitoh rxcfg |= CAS_MAC_RX_PROMISC_GRP;
2057 1.36 msaitoh }
2058 1.1 jdc bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg);
2059 1.1 jdc }
2060 1.1 jdc
2061 1.1 jdc int
2062 1.33 msaitoh cas_encap(struct cas_softc *sc, struct mbuf *mhead, uint32_t *bixp)
2063 1.1 jdc {
2064 1.33 msaitoh uint64_t flags;
2065 1.33 msaitoh uint32_t cur, frag, i;
2066 1.1 jdc bus_dmamap_t map;
2067 1.1 jdc
2068 1.1 jdc cur = frag = *bixp;
2069 1.1 jdc map = sc->sc_txd[cur].sd_map;
2070 1.1 jdc
2071 1.1 jdc if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead,
2072 1.1 jdc BUS_DMA_NOWAIT) != 0) {
2073 1.1 jdc return (ENOBUFS);
2074 1.1 jdc }
2075 1.1 jdc
2076 1.1 jdc if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) {
2077 1.1 jdc bus_dmamap_unload(sc->sc_dmatag, map);
2078 1.1 jdc return (ENOBUFS);
2079 1.1 jdc }
2080 1.1 jdc
2081 1.1 jdc bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize,
2082 1.1 jdc BUS_DMASYNC_PREWRITE);
2083 1.1 jdc
2084 1.1 jdc for (i = 0; i < map->dm_nsegs; i++) {
2085 1.1 jdc sc->sc_txdescs[frag].cd_addr =
2086 1.1 jdc CAS_DMA_WRITE(map->dm_segs[i].ds_addr);
2087 1.1 jdc flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) |
2088 1.1 jdc (i == 0 ? CAS_TD_START_OF_PACKET : 0) |
2089 1.1 jdc ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0);
2090 1.1 jdc sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags);
2091 1.1 jdc bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap,
2092 1.1 jdc CAS_CDTXOFF(frag), sizeof(struct cas_desc),
2093 1.1 jdc BUS_DMASYNC_PREWRITE);
2094 1.1 jdc cur = frag;
2095 1.1 jdc if (++frag == CAS_NTXDESC)
2096 1.1 jdc frag = 0;
2097 1.1 jdc }
2098 1.1 jdc
2099 1.1 jdc sc->sc_tx_cnt += map->dm_nsegs;
2100 1.1 jdc sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map;
2101 1.1 jdc sc->sc_txd[cur].sd_map = map;
2102 1.1 jdc sc->sc_txd[cur].sd_mbuf = mhead;
2103 1.1 jdc
2104 1.1 jdc bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag);
2105 1.1 jdc
2106 1.1 jdc *bixp = frag;
2107 1.1 jdc
2108 1.1 jdc /* sync descriptors */
2109 1.1 jdc
2110 1.1 jdc return (0);
2111 1.1 jdc }
2112 1.1 jdc
2113 1.1 jdc /*
2114 1.1 jdc * Transmit interrupt.
2115 1.1 jdc */
2116 1.1 jdc int
2117 1.33 msaitoh cas_tint(struct cas_softc *sc, uint32_t status)
2118 1.1 jdc {
2119 1.1 jdc struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2120 1.1 jdc struct cas_sxd *sd;
2121 1.33 msaitoh uint32_t cons, comp;
2122 1.1 jdc
2123 1.1 jdc comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION);
2124 1.1 jdc cons = sc->sc_tx_cons;
2125 1.1 jdc while (cons != comp) {
2126 1.1 jdc sd = &sc->sc_txd[cons];
2127 1.1 jdc if (sd->sd_mbuf != NULL) {
2128 1.1 jdc bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
2129 1.1 jdc sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2130 1.1 jdc bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
2131 1.1 jdc m_freem(sd->sd_mbuf);
2132 1.1 jdc sd->sd_mbuf = NULL;
2133 1.38 thorpej if_statinc(ifp, if_opackets);
2134 1.1 jdc }
2135 1.1 jdc sc->sc_tx_cnt--;
2136 1.1 jdc if (++cons == CAS_NTXDESC)
2137 1.1 jdc cons = 0;
2138 1.1 jdc }
2139 1.1 jdc sc->sc_tx_cons = cons;
2140 1.1 jdc
2141 1.1 jdc if (sc->sc_tx_cnt < CAS_NTXDESC - 2)
2142 1.1 jdc ifp->if_flags &= ~IFF_OACTIVE;
2143 1.1 jdc if (sc->sc_tx_cnt == 0)
2144 1.1 jdc ifp->if_timer = 0;
2145 1.1 jdc
2146 1.25 ozaki if_schedule_deferred_start(ifp);
2147 1.1 jdc
2148 1.1 jdc return (1);
2149 1.1 jdc }
2150 1.1 jdc
2151 1.1 jdc void
2152 1.1 jdc cas_start(struct ifnet *ifp)
2153 1.1 jdc {
2154 1.1 jdc struct cas_softc *sc = ifp->if_softc;
2155 1.1 jdc struct mbuf *m;
2156 1.33 msaitoh uint32_t bix;
2157 1.1 jdc
2158 1.1 jdc if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2159 1.1 jdc return;
2160 1.1 jdc
2161 1.1 jdc bix = sc->sc_tx_prod;
2162 1.1 jdc while (sc->sc_txd[bix].sd_mbuf == NULL) {
2163 1.1 jdc IFQ_POLL(&ifp->if_snd, m);
2164 1.1 jdc if (m == NULL)
2165 1.1 jdc break;
2166 1.1 jdc
2167 1.1 jdc /*
2168 1.1 jdc * If BPF is listening on this interface, let it see the
2169 1.1 jdc * packet before we commit it to the wire.
2170 1.1 jdc */
2171 1.27 msaitoh bpf_mtap(ifp, m, BPF_D_OUT);
2172 1.1 jdc
2173 1.1 jdc /*
2174 1.1 jdc * Encapsulate this packet and start it going...
2175 1.1 jdc * or fail...
2176 1.1 jdc */
2177 1.1 jdc if (cas_encap(sc, m, &bix)) {
2178 1.1 jdc ifp->if_flags |= IFF_OACTIVE;
2179 1.1 jdc break;
2180 1.1 jdc }
2181 1.1 jdc
2182 1.1 jdc IFQ_DEQUEUE(&ifp->if_snd, m);
2183 1.1 jdc ifp->if_timer = 5;
2184 1.1 jdc }
2185 1.1 jdc
2186 1.1 jdc sc->sc_tx_prod = bix;
2187 1.1 jdc }
2188 1.13 jmcneill
2189 1.14 jmcneill MODULE(MODULE_CLASS_DRIVER, if_cas, "pci");
2190 1.13 jmcneill
2191 1.13 jmcneill #ifdef _MODULE
2192 1.13 jmcneill #include "ioconf.c"
2193 1.13 jmcneill #endif
2194 1.13 jmcneill
2195 1.13 jmcneill static int
2196 1.13 jmcneill if_cas_modcmd(modcmd_t cmd, void *opaque)
2197 1.13 jmcneill {
2198 1.13 jmcneill int error = 0;
2199 1.13 jmcneill
2200 1.13 jmcneill switch (cmd) {
2201 1.13 jmcneill case MODULE_CMD_INIT:
2202 1.13 jmcneill #ifdef _MODULE
2203 1.13 jmcneill error = config_init_component(cfdriver_ioconf_cas,
2204 1.13 jmcneill cfattach_ioconf_cas, cfdata_ioconf_cas);
2205 1.13 jmcneill #endif
2206 1.13 jmcneill return error;
2207 1.13 jmcneill case MODULE_CMD_FINI:
2208 1.13 jmcneill #ifdef _MODULE
2209 1.13 jmcneill error = config_fini_component(cfdriver_ioconf_cas,
2210 1.13 jmcneill cfattach_ioconf_cas, cfdata_ioconf_cas);
2211 1.13 jmcneill #endif
2212 1.13 jmcneill return error;
2213 1.13 jmcneill default:
2214 1.13 jmcneill return ENOTTY;
2215 1.13 jmcneill }
2216 1.13 jmcneill }
2217