if_cas.c revision 1.3
1 /* $NetBSD: if_cas.c,v 1.3 2010/01/17 11:57:29 jdc Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.3 2010/01/17 11:57:29 jdc Exp $"); 48 49 #include "opt_inet.h" 50 #include "bpfilter.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/callout.h> 55 #include <sys/mbuf.h> 56 #include <sys/syslog.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 64 #include <machine/endian.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #if NBPFILTER > 0 83 #include <net/bpf.h> 84 #endif 85 86 #include <sys/bus.h> 87 #include <sys/intr.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 #include <dev/mii/mii_bitbang.h> 92 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcidevs.h> 96 97 #include <dev/pci/if_casreg.h> 98 #include <dev/pci/if_casvar.h> 99 100 /* XXX Should use Properties when that's fleshed out. */ 101 #ifdef macppc 102 #include <dev/ofw/openfirm.h> 103 #endif /* macppc */ 104 #ifdef __sparc__ 105 #include <machine/promlib.h> 106 #endif 107 108 #ifndef CAS_USE_LOCAL_MAC_ADDRESS 109 #if defined (macppc) || defined (__sparc__) 110 #define CAS_USE_LOCAL_MAC_ADDRESS 0 /* use system-wide address */ 111 #else 112 #define CAS_USE_LOCAL_MAC_ADDRESS 1 113 #endif 114 #endif 115 116 #define TRIES 10000 117 118 static bool cas_estintr(struct cas_softc *sc, int); 119 bool cas_shutdown(device_t, int); 120 static bool cas_suspend(device_t, pmf_qual_t); 121 static bool cas_resume(device_t, pmf_qual_t); 122 static int cas_detach(device_t, int); 123 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 124 125 int cas_match(device_t, cfdata_t, void *); 126 void cas_attach(device_t, device_t, void *); 127 128 129 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 130 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 131 DVF_DETACH_SHUTDOWN); 132 133 #if CAS_USE_LOCAL_MAC_ADDRESS 134 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 135 #endif 136 137 void cas_config(struct cas_softc *, const uint8_t *); 138 void cas_start(struct ifnet *); 139 void cas_stop(struct ifnet *, int); 140 int cas_ioctl(struct ifnet *, u_long, void *); 141 void cas_tick(void *); 142 void cas_watchdog(struct ifnet *); 143 int cas_init(struct ifnet *); 144 void cas_init_regs(struct cas_softc *); 145 int cas_ringsize(int); 146 int cas_cringsize(int); 147 int cas_meminit(struct cas_softc *); 148 void cas_mifinit(struct cas_softc *); 149 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 150 u_int32_t, u_int32_t); 151 void cas_reset(struct cas_softc *); 152 int cas_reset_rx(struct cas_softc *); 153 int cas_reset_tx(struct cas_softc *); 154 int cas_disable_rx(struct cas_softc *); 155 int cas_disable_tx(struct cas_softc *); 156 void cas_rxdrain(struct cas_softc *); 157 int cas_add_rxbuf(struct cas_softc *, int idx); 158 void cas_iff(struct cas_softc *); 159 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 160 161 /* MII methods & callbacks */ 162 int cas_mii_readreg(device_t, int, int); 163 void cas_mii_writereg(device_t, int, int, int); 164 void cas_mii_statchg(device_t); 165 int cas_pcs_readreg(device_t, int, int); 166 void cas_pcs_writereg(device_t, int, int, int); 167 168 int cas_mediachange(struct ifnet *); 169 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 170 171 int cas_eint(struct cas_softc *, u_int); 172 int cas_rint(struct cas_softc *); 173 int cas_tint(struct cas_softc *, u_int32_t); 174 int cas_pint(struct cas_softc *); 175 int cas_intr(void *); 176 177 #ifdef CAS_DEBUG 178 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 179 printf x 180 #else 181 #define DPRINTF(sc, x) /* nothing */ 182 #endif 183 184 int 185 cas_match(device_t parent, cfdata_t cf, void *aux) 186 { 187 struct pci_attach_args *pa = aux; 188 189 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 190 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 191 return 1; 192 193 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 194 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 195 return 1; 196 197 return 0; 198 } 199 200 #if CAS_USE_LOCAL_MAC_ADDRESS 201 #define PROMHDR_PTR_DATA 0x18 202 #define PROMDATA_PTR_VPD 0x08 203 #define PROMDATA_DATA2 0x0a 204 205 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 206 static const u_int8_t cas_promdat[] = { 207 'P', 'C', 'I', 'R', 208 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 209 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 210 }; 211 212 static const u_int8_t cas_promdat2[] = { 213 0x18, 0x00, /* structure length */ 214 0x00, /* structure revision */ 215 0x00, /* interface revision */ 216 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 217 PCI_CLASS_NETWORK /* class code */ 218 }; 219 220 int 221 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 222 uint8_t *enaddr) 223 { 224 struct pci_vpd_largeres *res; 225 struct pci_vpd *vpd; 226 bus_space_handle_t romh; 227 bus_space_tag_t romt; 228 bus_size_t romsize = 0; 229 u_int8_t buf[32], *desc; 230 pcireg_t address; 231 int dataoff, vpdoff, len; 232 int rv = -1; 233 234 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 235 &romt, &romh, NULL, &romsize)) 236 return (-1); 237 238 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 239 address |= PCI_MAPREG_ROM_ENABLE; 240 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 241 242 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 243 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 244 goto fail; 245 246 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 247 if (dataoff < 0x1c) 248 goto fail; 249 250 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 251 if (bcmp(buf, cas_promdat, sizeof(cas_promdat)) || 252 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 253 goto fail; 254 255 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 256 if (vpdoff < 0x1c) 257 goto fail; 258 259 next: 260 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 261 if (!PCI_VPDRES_ISLARGE(buf[0])) 262 goto fail; 263 264 res = (struct pci_vpd_largeres *)buf; 265 vpdoff += sizeof(*res); 266 267 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 268 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 269 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 270 /* Skip identifier string. */ 271 vpdoff += len; 272 goto next; 273 274 case PCI_VPDRES_TYPE_VPD: 275 while (len > 0) { 276 bus_space_read_region_1(romt, romh, vpdoff, 277 buf, sizeof(buf)); 278 279 vpd = (struct pci_vpd *)buf; 280 vpdoff += sizeof(*vpd) + vpd->vpd_len; 281 len -= sizeof(*vpd) + vpd->vpd_len; 282 283 /* 284 * We're looking for an "Enhanced" VPD... 285 */ 286 if (vpd->vpd_key0 != 'Z') 287 continue; 288 289 desc = buf + sizeof(*vpd); 290 291 /* 292 * ...which is an instance property... 293 */ 294 if (desc[0] != 'I') 295 continue; 296 desc += 3; 297 298 /* 299 * ...that's a byte array with the proper 300 * length for a MAC address... 301 */ 302 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 303 continue; 304 desc += 2; 305 306 /* 307 * ...named "local-mac-address". 308 */ 309 if (strcmp(desc, "local-mac-address") != 0) 310 continue; 311 desc += strlen("local-mac-address") + 1; 312 313 memcpy(enaddr, enp, ETHER_ADDR_LEN); 314 rv = 0; 315 } 316 break; 317 318 default: 319 goto fail; 320 } 321 322 fail: 323 if (romsize != 0) 324 bus_space_unmap(romt, romh, romsize); 325 326 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 327 address &= ~PCI_MAPREG_ROM_ENABLE; 328 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 329 330 return (rv); 331 } 332 #endif /* CAS_USE_LOCAL_MAC_ADDRESS */ 333 334 void 335 cas_attach(device_t parent, device_t self, void *aux) 336 { 337 struct pci_attach_args *pa = aux; 338 struct cas_softc *sc = device_private(self); 339 char devinfo[256]; 340 uint8_t enaddr[ETHER_ADDR_LEN]; 341 342 sc->sc_dev = self; 343 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 344 sc->sc_rev = PCI_REVISION(pa->pa_class); 345 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, sc->sc_rev); 346 sc->sc_dmatag = pa->pa_dmat; 347 348 #define PCI_CAS_BASEADDR 0x10 349 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 350 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 351 aprint_error_dev(sc->sc_dev, 352 "unable to map device registers\n"); 353 return; 354 } 355 356 #if CAS_USE_LOCAL_MAC_ADDRESS 357 if (cas_pci_enaddr(sc, pa, enaddr) != 0) 358 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 359 #endif 360 #ifdef __sparc64__ 361 prom_getether(PCITAG_NODE(pa->pa_tag), enaddr); 362 #else 363 #ifdef macppc 364 { 365 int node; 366 367 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 368 if (node == 0) { 369 aprint_error_dev(sc->sc_dev, "unable to locate OpenFirmware node\n"); 370 return; 371 } 372 373 OF_getprop(node, "local-mac-address", enaddr, sizeof(enaddr)); 374 } 375 #endif /* macppc */ 376 #endif /* __sparc__ */ 377 378 sc->sc_burst = 16; /* XXX */ 379 380 sc->sc_att_stage = CAS_ATT_BACKEND_0; 381 382 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 383 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 384 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 385 return; 386 } 387 sc->sc_pc = pa->pa_pc; 388 if (!cas_estintr(sc, CAS_INTR_PCI)) { 389 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 390 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 391 return; 392 } 393 394 sc->sc_att_stage = CAS_ATT_BACKEND_1; 395 396 /* 397 * call the main configure 398 */ 399 cas_config(sc, enaddr); 400 401 if (pmf_device_register1(sc->sc_dev, 402 cas_suspend, cas_resume, cas_shutdown)) 403 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 404 else 405 aprint_error_dev(sc->sc_dev, 406 "could not establish power handlers\n"); 407 408 sc->sc_att_stage = CAS_ATT_FINISHED; 409 /*FALLTHROUGH*/ 410 } 411 412 /* 413 * cas_config: 414 * 415 * Attach a Cassini interface to the system. 416 */ 417 void 418 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 419 { 420 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 421 struct mii_data *mii = &sc->sc_mii; 422 struct mii_softc *child; 423 int i, error; 424 425 /* Make sure the chip is stopped. */ 426 ifp->if_softc = sc; 427 cas_reset(sc); 428 429 /* 430 * Allocate the control data structures, and create and load the 431 * DMA map for it. 432 */ 433 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 434 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 435 1, &sc->sc_cdnseg, 0)) != 0) { 436 aprint_error_dev(sc->sc_dev, 437 "unable to allocate control data, error = %d\n", 438 error); 439 cas_partial_detach(sc, CAS_ATT_0); 440 } 441 442 /* XXX should map this in with correct endianness */ 443 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 444 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 445 BUS_DMA_COHERENT)) != 0) { 446 aprint_error_dev(sc->sc_dev, 447 "unable to map control data, error = %d\n", error); 448 cas_partial_detach(sc, CAS_ATT_1); 449 } 450 451 if ((error = bus_dmamap_create(sc->sc_dmatag, 452 sizeof(struct cas_control_data), 1, 453 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 454 aprint_error_dev(sc->sc_dev, 455 "unable to create control data DMA map, error = %d\n", error); 456 cas_partial_detach(sc, CAS_ATT_2); 457 } 458 459 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 460 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 461 0)) != 0) { 462 aprint_error_dev(sc->sc_dev, 463 "unable to load control data DMA map, error = %d\n", 464 error); 465 cas_partial_detach(sc, CAS_ATT_3); 466 } 467 468 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 469 470 /* 471 * Create the receive buffer DMA maps. 472 */ 473 for (i = 0; i < CAS_NRXDESC; i++) { 474 bus_dma_segment_t seg; 475 char *kva; 476 int rseg; 477 478 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 479 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 480 aprint_error_dev(sc->sc_dev, 481 "unable to alloc rx DMA mem %d, error = %d\n", 482 i, error); 483 cas_partial_detach(sc, CAS_ATT_5); 484 } 485 sc->sc_rxsoft[i].rxs_dmaseg = seg; 486 487 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 488 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 489 aprint_error_dev(sc->sc_dev, 490 "unable to alloc rx DMA mem %d, error = %d\n", 491 i, error); 492 cas_partial_detach(sc, CAS_ATT_5); 493 } 494 sc->sc_rxsoft[i].rxs_kva = kva; 495 496 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 497 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 498 aprint_error_dev(sc->sc_dev, 499 "unable to create rx DMA map %d, error = %d\n", 500 i, error); 501 cas_partial_detach(sc, CAS_ATT_5); 502 } 503 504 if ((error = bus_dmamap_load(sc->sc_dmatag, 505 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 506 BUS_DMA_NOWAIT)) != 0) { 507 aprint_error_dev(sc->sc_dev, 508 "unable to load rx DMA map %d, error = %d\n", 509 i, error); 510 cas_partial_detach(sc, CAS_ATT_5); 511 } 512 } 513 514 /* 515 * Create the transmit buffer DMA maps. 516 */ 517 for (i = 0; i < CAS_NTXDESC; i++) { 518 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 519 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 520 &sc->sc_txd[i].sd_map)) != 0) { 521 aprint_error_dev(sc->sc_dev, 522 "unable to create tx DMA map %d, error = %d\n", 523 i, error); 524 cas_partial_detach(sc, CAS_ATT_6); 525 } 526 sc->sc_txd[i].sd_mbuf = NULL; 527 } 528 529 /* 530 * From this point forward, the attachment cannot fail. A failure 531 * before this point releases all resources that may have been 532 * allocated. 533 */ 534 535 /* Announce ourselves. */ 536 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 537 ether_sprintf(enaddr)); 538 539 /* Get RX FIFO size */ 540 sc->sc_rxfifosize = 16 * 1024; 541 542 /* Initialize ifnet structure. */ 543 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 544 ifp->if_softc = sc; 545 ifp->if_flags = 546 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 547 ifp->if_start = cas_start; 548 ifp->if_ioctl = cas_ioctl; 549 ifp->if_watchdog = cas_watchdog; 550 ifp->if_stop = cas_stop; 551 ifp->if_init = cas_init; 552 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 553 IFQ_SET_READY(&ifp->if_snd); 554 555 /* Initialize ifmedia structures and MII info */ 556 mii->mii_ifp = ifp; 557 mii->mii_readreg = cas_mii_readreg; 558 mii->mii_writereg = cas_mii_writereg; 559 mii->mii_statchg = cas_mii_statchg; 560 561 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 562 sc->sc_ethercom.ec_mii = mii; 563 564 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 565 566 cas_mifinit(sc); 567 568 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 569 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 570 bus_space_write_4(sc->sc_memt, sc->sc_memh, 571 CAS_MIF_CONFIG, sc->sc_mif_config); 572 } 573 574 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 575 MII_OFFSET_ANY, 0); 576 577 child = LIST_FIRST(&mii->mii_phys); 578 if (child == NULL && 579 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 580 /* 581 * Try the external PCS SERDES if we didn't find any 582 * MII devices. 583 */ 584 bus_space_write_4(sc->sc_memt, sc->sc_memh, 585 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 586 587 bus_space_write_4(sc->sc_memt, sc->sc_memh, 588 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 589 590 mii->mii_readreg = cas_pcs_readreg; 591 mii->mii_writereg = cas_pcs_writereg; 592 593 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 594 MII_OFFSET_ANY, MIIF_NOISOLATE); 595 } 596 597 child = LIST_FIRST(&mii->mii_phys); 598 if (child == NULL) { 599 /* No PHY attached */ 600 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 601 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 602 } else { 603 /* 604 * Walk along the list of attached MII devices and 605 * establish an `MII instance' to `phy number' 606 * mapping. We'll use this mapping in media change 607 * requests to determine which phy to use to program 608 * the MIF configuration register. 609 */ 610 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 611 /* 612 * Note: we support just two PHYs: the built-in 613 * internal device and an external on the MII 614 * connector. 615 */ 616 if (child->mii_phy > 1 || child->mii_inst > 1) { 617 aprint_error_dev(sc->sc_dev, 618 "cannot accommodate MII device %s" 619 " at phy %d, instance %d\n", 620 device_xname(child->mii_dev), 621 child->mii_phy, child->mii_inst); 622 continue; 623 } 624 625 sc->sc_phys[child->mii_inst] = child->mii_phy; 626 } 627 628 /* 629 * XXX - we can really do the following ONLY if the 630 * phy indeed has the auto negotiation capability!! 631 */ 632 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 633 } 634 635 /* claim 802.1q capability */ 636 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 637 638 /* Attach the interface. */ 639 if_attach(ifp); 640 ether_ifattach(ifp, enaddr); 641 642 #if NRND > 0 643 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 644 RND_TYPE_NET, 0); 645 #endif 646 647 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 648 NULL, device_xname(sc->sc_dev), "interrupts"); 649 650 callout_init(&sc->sc_tick_ch, 0); 651 652 return; 653 } 654 655 int 656 cas_detach(device_t self, int flags) 657 { 658 int i; 659 struct cas_softc *sc = device_private(self); 660 bus_space_tag_t t = sc->sc_memt; 661 bus_space_handle_t h = sc->sc_memh; 662 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 663 664 /* 665 * Free any resources we've allocated during the failed attach 666 * attempt. Do this in reverse order and fall through. 667 */ 668 switch (sc->sc_att_stage) { 669 case CAS_ATT_FINISHED: 670 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 671 pmf_device_deregister(self); 672 cas_stop(&sc->sc_ethercom.ec_if, 1); 673 evcnt_detach(&sc->sc_ev_intr); 674 675 #if NRND > 0 676 rnd_detach_source(&sc->rnd_source); 677 #endif 678 679 ether_ifdetach(ifp); 680 if_detach(ifp); 681 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 682 683 callout_destroy(&sc->sc_tick_ch); 684 685 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 686 687 /*FALLTHROUGH*/ 688 case CAS_ATT_MII: 689 case CAS_ATT_7: 690 case CAS_ATT_6: 691 for (i = 0; i < CAS_NTXDESC; i++) { 692 if (sc->sc_txd[i].sd_map != NULL) 693 bus_dmamap_destroy(sc->sc_dmatag, 694 sc->sc_txd[i].sd_map); 695 } 696 /*FALLTHROUGH*/ 697 case CAS_ATT_5: 698 for (i = 0; i < CAS_NRXDESC; i++) { 699 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 700 bus_dmamap_unload(sc->sc_dmatag, 701 sc->sc_rxsoft[i].rxs_dmamap); 702 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 703 bus_dmamap_destroy(sc->sc_dmatag, 704 sc->sc_rxsoft[i].rxs_dmamap); 705 if (sc->sc_rxsoft[i].rxs_kva != NULL) 706 bus_dmamem_unmap(sc->sc_dmatag, 707 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 708 /* XXX need to check that bus_dmamem_alloc suceeded 709 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 710 */ 711 bus_dmamem_free(sc->sc_dmatag, 712 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 713 } 714 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 715 /*FALLTHROUGH*/ 716 case CAS_ATT_4: 717 case CAS_ATT_3: 718 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 719 /*FALLTHROUGH*/ 720 case CAS_ATT_2: 721 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 722 sizeof(struct cas_control_data)); 723 /*FALLTHROUGH*/ 724 case CAS_ATT_1: 725 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 726 /*FALLTHROUGH*/ 727 case CAS_ATT_0: 728 sc->sc_att_stage = CAS_ATT_0; 729 /*FALLTHROUGH*/ 730 case CAS_ATT_BACKEND_2: 731 case CAS_ATT_BACKEND_1: 732 if (sc->sc_ih != NULL) { 733 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 734 sc->sc_ih = NULL; 735 } 736 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 737 /*FALLTHROUGH*/ 738 case CAS_ATT_BACKEND_0: 739 break; 740 } 741 return 0; 742 } 743 744 static void 745 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 746 { 747 cfattach_t ca = device_cfattach(sc->sc_dev); 748 749 sc->sc_att_stage = stage; 750 (*ca->ca_detach)(sc->sc_dev, 0); 751 } 752 753 void 754 cas_tick(void *arg) 755 { 756 struct cas_softc *sc = arg; 757 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 758 bus_space_tag_t t = sc->sc_memt; 759 bus_space_handle_t mac = sc->sc_memh; 760 int s; 761 u_int32_t v; 762 763 /* unload collisions counters */ 764 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 765 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 766 ifp->if_collisions += v + 767 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 768 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 769 ifp->if_oerrors += v; 770 771 /* read error counters */ 772 ifp->if_ierrors += 773 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 774 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 775 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 776 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 777 778 /* clear the hardware counters */ 779 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 780 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 781 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 782 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 783 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 784 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 785 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 786 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 787 788 s = splnet(); 789 mii_tick(&sc->sc_mii); 790 splx(s); 791 792 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 793 } 794 795 int 796 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 797 u_int32_t clr, u_int32_t set) 798 { 799 int i; 800 u_int32_t reg; 801 802 for (i = TRIES; i--; DELAY(100)) { 803 reg = bus_space_read_4(sc->sc_memt, h, r); 804 if ((reg & clr) == 0 && (reg & set) == set) 805 return (1); 806 } 807 808 return (0); 809 } 810 811 void 812 cas_reset(struct cas_softc *sc) 813 { 814 bus_space_tag_t t = sc->sc_memt; 815 bus_space_handle_t h = sc->sc_memh; 816 int s; 817 818 s = splnet(); 819 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 820 cas_reset_rx(sc); 821 cas_reset_tx(sc); 822 823 /* Do a full reset */ 824 bus_space_write_4(t, h, CAS_RESET, 825 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 826 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 827 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 828 splx(s); 829 } 830 831 832 /* 833 * cas_rxdrain: 834 * 835 * Drain the receive queue. 836 */ 837 void 838 cas_rxdrain(struct cas_softc *sc) 839 { 840 /* Nothing to do yet. */ 841 } 842 843 /* 844 * Reset the whole thing. 845 */ 846 void 847 cas_stop(struct ifnet *ifp, int disable) 848 { 849 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 850 struct cas_sxd *sd; 851 u_int32_t i; 852 853 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 854 855 callout_stop(&sc->sc_tick_ch); 856 857 /* 858 * Mark the interface down and cancel the watchdog timer. 859 */ 860 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 861 ifp->if_timer = 0; 862 863 mii_down(&sc->sc_mii); 864 865 cas_reset_rx(sc); 866 cas_reset_tx(sc); 867 868 /* 869 * Release any queued transmit buffers. 870 */ 871 for (i = 0; i < CAS_NTXDESC; i++) { 872 sd = &sc->sc_txd[i]; 873 if (sd->sd_mbuf != NULL) { 874 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 875 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 876 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 877 m_freem(sd->sd_mbuf); 878 sd->sd_mbuf = NULL; 879 } 880 } 881 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 882 883 if (disable) 884 cas_rxdrain(sc); 885 } 886 887 888 /* 889 * Reset the receiver 890 */ 891 int 892 cas_reset_rx(struct cas_softc *sc) 893 { 894 bus_space_tag_t t = sc->sc_memt; 895 bus_space_handle_t h = sc->sc_memh; 896 897 /* 898 * Resetting while DMA is in progress can cause a bus hang, so we 899 * disable DMA first. 900 */ 901 cas_disable_rx(sc); 902 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 903 /* Wait till it finishes */ 904 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 905 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 906 /* Wait 5ms extra. */ 907 delay(5000); 908 909 /* Finally, reset the ERX */ 910 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 911 /* Wait till it finishes */ 912 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 913 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 914 return (1); 915 } 916 return (0); 917 } 918 919 920 /* 921 * Reset the transmitter 922 */ 923 int 924 cas_reset_tx(struct cas_softc *sc) 925 { 926 bus_space_tag_t t = sc->sc_memt; 927 bus_space_handle_t h = sc->sc_memh; 928 929 /* 930 * Resetting while DMA is in progress can cause a bus hang, so we 931 * disable DMA first. 932 */ 933 cas_disable_tx(sc); 934 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 935 /* Wait till it finishes */ 936 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 937 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 938 /* Wait 5ms extra. */ 939 delay(5000); 940 941 /* Finally, reset the ETX */ 942 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 943 /* Wait till it finishes */ 944 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 945 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 946 return (1); 947 } 948 return (0); 949 } 950 951 /* 952 * Disable receiver. 953 */ 954 int 955 cas_disable_rx(struct cas_softc *sc) 956 { 957 bus_space_tag_t t = sc->sc_memt; 958 bus_space_handle_t h = sc->sc_memh; 959 u_int32_t cfg; 960 961 /* Flip the enable bit */ 962 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 963 cfg &= ~CAS_MAC_RX_ENABLE; 964 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 965 966 /* Wait for it to finish */ 967 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 968 } 969 970 /* 971 * Disable transmitter. 972 */ 973 int 974 cas_disable_tx(struct cas_softc *sc) 975 { 976 bus_space_tag_t t = sc->sc_memt; 977 bus_space_handle_t h = sc->sc_memh; 978 u_int32_t cfg; 979 980 /* Flip the enable bit */ 981 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 982 cfg &= ~CAS_MAC_TX_ENABLE; 983 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 984 985 /* Wait for it to finish */ 986 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 987 } 988 989 /* 990 * Initialize interface. 991 */ 992 int 993 cas_meminit(struct cas_softc *sc) 994 { 995 struct cas_rxsoft *rxs; 996 int i, error; 997 998 rxs = (void *)&error; 999 1000 /* 1001 * Initialize the transmit descriptor ring. 1002 */ 1003 for (i = 0; i < CAS_NTXDESC; i++) { 1004 sc->sc_txdescs[i].cd_flags = 0; 1005 sc->sc_txdescs[i].cd_addr = 0; 1006 } 1007 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 1008 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1009 1010 /* 1011 * Initialize the receive descriptor and receive job 1012 * descriptor rings. 1013 */ 1014 for (i = 0; i < CAS_NRXDESC; i++) 1015 CAS_INIT_RXDESC(sc, i, i); 1016 sc->sc_rxdptr = 0; 1017 sc->sc_rxptr = 0; 1018 1019 /* 1020 * Initialize the receive completion ring. 1021 */ 1022 for (i = 0; i < CAS_NRXCOMP; i++) { 1023 sc->sc_rxcomps[i].cc_word[0] = 0; 1024 sc->sc_rxcomps[i].cc_word[1] = 0; 1025 sc->sc_rxcomps[i].cc_word[2] = 0; 1026 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1027 CAS_CDRXCSYNC(sc, i, 1028 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1029 } 1030 1031 return (0); 1032 } 1033 1034 int 1035 cas_ringsize(int sz) 1036 { 1037 switch (sz) { 1038 case 32: 1039 return CAS_RING_SZ_32; 1040 case 64: 1041 return CAS_RING_SZ_64; 1042 case 128: 1043 return CAS_RING_SZ_128; 1044 case 256: 1045 return CAS_RING_SZ_256; 1046 case 512: 1047 return CAS_RING_SZ_512; 1048 case 1024: 1049 return CAS_RING_SZ_1024; 1050 case 2048: 1051 return CAS_RING_SZ_2048; 1052 case 4096: 1053 return CAS_RING_SZ_4096; 1054 case 8192: 1055 return CAS_RING_SZ_8192; 1056 default: 1057 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1058 sz); 1059 return CAS_RING_SZ_32; 1060 } 1061 } 1062 1063 int 1064 cas_cringsize(int sz) 1065 { 1066 int i; 1067 1068 for (i = 0; i < 9; i++) 1069 if (sz == (128 << i)) 1070 return i; 1071 1072 aprint_error("cas: invalid completion ring size %d\n", sz); 1073 return 128; 1074 } 1075 1076 /* 1077 * Initialization of interface; set up initialization block 1078 * and transmit/receive descriptor rings. 1079 */ 1080 int 1081 cas_init(struct ifnet *ifp) 1082 { 1083 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1084 bus_space_tag_t t = sc->sc_memt; 1085 bus_space_handle_t h = sc->sc_memh; 1086 int s; 1087 u_int max_frame_size; 1088 u_int32_t v; 1089 1090 s = splnet(); 1091 1092 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1093 /* 1094 * Initialization sequence. The numbered steps below correspond 1095 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1096 * Channel Engine manual (part of the PCIO manual). 1097 * See also the STP2002-STQ document from Sun Microsystems. 1098 */ 1099 1100 /* step 1 & 2. Reset the Ethernet Channel */ 1101 cas_stop(ifp, 0); 1102 cas_reset(sc); 1103 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1104 1105 /* Re-initialize the MIF */ 1106 cas_mifinit(sc); 1107 1108 /* step 3. Setup data structures in host memory */ 1109 cas_meminit(sc); 1110 1111 /* step 4. TX MAC registers & counters */ 1112 cas_init_regs(sc); 1113 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1114 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1115 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1116 1117 /* step 5. RX MAC registers & counters */ 1118 cas_iff(sc); 1119 1120 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1121 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1122 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1123 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1124 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1125 1126 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1127 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1128 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1129 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1130 1131 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1132 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1133 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1134 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1135 1136 if (CAS_PLUS(sc)) { 1137 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1138 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1139 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1140 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1141 CAS_CDRXADDR2(sc, 0)); 1142 } 1143 1144 /* step 8. Global Configuration & Interrupt Mask */ 1145 cas_estintr(sc, CAS_INTR_REG); 1146 1147 /* step 9. ETX Configuration: use mostly default values */ 1148 1149 /* Enable DMA */ 1150 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1151 bus_space_write_4(t, h, CAS_TX_CONFIG, 1152 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1153 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1154 1155 /* step 10. ERX Configuration */ 1156 1157 /* Encode Receive Descriptor ring size */ 1158 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1159 if (CAS_PLUS(sc)) 1160 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1161 1162 /* Encode Receive Completion ring size */ 1163 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1164 1165 /* Enable DMA */ 1166 bus_space_write_4(t, h, CAS_RX_CONFIG, 1167 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1168 1169 /* 1170 * The following value is for an OFF Threshold of about 3/4 full 1171 * and an ON Threshold of 1/4 full. 1172 */ 1173 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1174 (3 * sc->sc_rxfifosize / 256) | 1175 ((sc->sc_rxfifosize / 256) << 12)); 1176 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1177 1178 /* step 11. Configure Media */ 1179 mii_ifmedia_change(&sc->sc_mii); 1180 1181 /* step 12. RX_MAC Configuration Register */ 1182 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1183 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1184 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1185 1186 /* step 14. Issue Transmit Pending command */ 1187 1188 /* step 15. Give the receiver a swift kick */ 1189 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1190 if (CAS_PLUS(sc)) 1191 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1192 1193 /* Start the one second timer. */ 1194 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1195 1196 ifp->if_flags |= IFF_RUNNING; 1197 ifp->if_flags &= ~IFF_OACTIVE; 1198 ifp->if_timer = 0; 1199 splx(s); 1200 1201 return (0); 1202 } 1203 1204 void 1205 cas_init_regs(struct cas_softc *sc) 1206 { 1207 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1208 bus_space_tag_t t = sc->sc_memt; 1209 bus_space_handle_t h = sc->sc_memh; 1210 const u_char *laddr = CLLADDR(ifp->if_sadl); 1211 u_int32_t v, r; 1212 1213 /* These regs are not cleared on reset */ 1214 sc->sc_inited = 0; 1215 if (!sc->sc_inited) { 1216 /* Load recommended values */ 1217 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1218 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1219 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1220 1221 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1222 /* Max frame and max burst size */ 1223 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1224 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1225 1226 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1227 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1228 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1229 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1230 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1231 ((laddr[5]<<8)|laddr[4])&0x3ff); 1232 1233 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1234 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1235 bus_space_write_4(t, h, r, 0); 1236 1237 /* MAC control addr set to 0:1:c2:0:1:80 */ 1238 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1239 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1240 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1241 1242 /* MAC filter addr set to 0:0:0:0:0:0 */ 1243 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1244 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1245 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1246 1247 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1248 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1249 1250 /* Hash table initialized to 0 */ 1251 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1252 bus_space_write_4(t, h, r, 0); 1253 1254 sc->sc_inited = 1; 1255 } 1256 1257 /* Counters need to be zeroed */ 1258 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1259 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1260 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1261 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1262 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1263 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1264 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1265 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1266 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1267 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1268 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1269 1270 /* Un-pause stuff */ 1271 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1272 1273 /* 1274 * Set the station address. 1275 */ 1276 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1277 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1278 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1279 } 1280 1281 /* 1282 * Receive interrupt. 1283 */ 1284 int 1285 cas_rint(struct cas_softc *sc) 1286 { 1287 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1288 bus_space_tag_t t = sc->sc_memt; 1289 bus_space_handle_t h = sc->sc_memh; 1290 struct cas_rxsoft *rxs; 1291 struct mbuf *m; 1292 u_int64_t word[4]; 1293 int len, off, idx; 1294 int i, skip; 1295 void *cp; 1296 1297 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1298 CAS_CDRXCSYNC(sc, i, 1299 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1300 1301 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1302 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1303 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1304 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1305 1306 /* Stop if the hardware still owns the descriptor. */ 1307 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1308 break; 1309 1310 len = CAS_RC1_HDR_LEN(word[1]); 1311 if (len > 0) { 1312 off = CAS_RC1_HDR_OFF(word[1]); 1313 idx = CAS_RC1_HDR_IDX(word[1]); 1314 rxs = &sc->sc_rxsoft[idx]; 1315 1316 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1317 idx, off, len)); 1318 1319 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1320 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1321 1322 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1323 m = m_devget(cp, len, 0, ifp, NULL); 1324 1325 if (word[0] & CAS_RC0_RELEASE_HDR) 1326 cas_add_rxbuf(sc, idx); 1327 1328 if (m != NULL) { 1329 1330 #if NBPFILTER > 0 1331 /* 1332 * Pass this up to any BPF listeners, but only 1333 * pass it up the stack if its for us. 1334 */ 1335 if (ifp->if_bpf) 1336 bpf_mtap(ifp->if_bpf, m); 1337 #endif /* NBPFILTER > 0 */ 1338 1339 ifp->if_ipackets++; 1340 m->m_pkthdr.csum_flags = 0; 1341 (*ifp->if_input)(ifp, m); 1342 } else 1343 ifp->if_ierrors++; 1344 } 1345 1346 len = CAS_RC0_DATA_LEN(word[0]); 1347 if (len > 0) { 1348 off = CAS_RC0_DATA_OFF(word[0]); 1349 idx = CAS_RC0_DATA_IDX(word[0]); 1350 rxs = &sc->sc_rxsoft[idx]; 1351 1352 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1353 idx, off, len)); 1354 1355 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1356 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1357 1358 /* XXX We should not be copying the packet here. */ 1359 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1360 m = m_devget(cp, len, 0, ifp, NULL); 1361 1362 if (word[0] & CAS_RC0_RELEASE_DATA) 1363 cas_add_rxbuf(sc, idx); 1364 1365 if (m != NULL) { 1366 #if NBPFILTER > 0 1367 /* 1368 * Pass this up to any BPF listeners, but only 1369 * pass it up the stack if its for us. 1370 */ 1371 if (ifp->if_bpf) 1372 bpf_mtap(ifp->if_bpf, m); 1373 #endif /* NBPFILTER > 0 */ 1374 1375 ifp->if_ipackets++; 1376 m->m_pkthdr.csum_flags = 0; 1377 (*ifp->if_input)(ifp, m); 1378 } else 1379 ifp->if_ierrors++; 1380 } 1381 1382 if (word[0] & CAS_RC0_SPLIT) 1383 aprint_error_dev(sc->sc_dev, "split packet\n"); 1384 1385 skip = CAS_RC0_SKIP(word[0]); 1386 } 1387 1388 while (sc->sc_rxptr != i) { 1389 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1390 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1391 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1392 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1393 CAS_DMA_WRITE(CAS_RC3_OWN); 1394 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1395 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1396 1397 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1398 } 1399 1400 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1401 1402 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1403 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1404 1405 return (1); 1406 } 1407 1408 /* 1409 * cas_add_rxbuf: 1410 * 1411 * Add a receive buffer to the indicated descriptor. 1412 */ 1413 int 1414 cas_add_rxbuf(struct cas_softc *sc, int idx) 1415 { 1416 bus_space_tag_t t = sc->sc_memt; 1417 bus_space_handle_t h = sc->sc_memh; 1418 1419 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1420 1421 if ((sc->sc_rxdptr % 4) == 0) 1422 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1423 1424 if (++sc->sc_rxdptr == CAS_NRXDESC) 1425 sc->sc_rxdptr = 0; 1426 1427 return (0); 1428 } 1429 1430 int 1431 cas_eint(struct cas_softc *sc, u_int status) 1432 { 1433 char bits[128]; 1434 if ((status & CAS_INTR_MIF) != 0) { 1435 DPRINTF(sc, ("%s: link status changed\n", 1436 device_xname(sc->sc_dev))); 1437 return (1); 1438 } 1439 1440 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1441 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1442 return (1); 1443 } 1444 1445 int 1446 cas_pint(struct cas_softc *sc) 1447 { 1448 bus_space_tag_t t = sc->sc_memt; 1449 bus_space_handle_t seb = sc->sc_memh; 1450 u_int32_t status; 1451 1452 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1453 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1454 #ifdef CAS_DEBUG 1455 if (status) 1456 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1457 #endif 1458 return (1); 1459 } 1460 1461 int 1462 cas_intr(void *v) 1463 { 1464 struct cas_softc *sc = (struct cas_softc *)v; 1465 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1466 bus_space_tag_t t = sc->sc_memt; 1467 bus_space_handle_t seb = sc->sc_memh; 1468 u_int32_t status; 1469 int r = 0; 1470 #ifdef CAS_DEBUG 1471 char bits[128]; 1472 #endif 1473 1474 sc->sc_ev_intr.ev_count++; 1475 1476 status = bus_space_read_4(t, seb, CAS_STATUS); 1477 #ifdef CAS_DEBUG 1478 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1479 #endif 1480 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1481 device_xname(sc->sc_dev), (status>>19), bits)); 1482 1483 if ((status & CAS_INTR_PCS) != 0) 1484 r |= cas_pint(sc); 1485 1486 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1487 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1488 r |= cas_eint(sc, status); 1489 1490 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1491 r |= cas_tint(sc, status); 1492 1493 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1494 r |= cas_rint(sc); 1495 1496 /* We should eventually do more than just print out error stats. */ 1497 if (status & CAS_INTR_TX_MAC) { 1498 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1499 #ifdef CAS_DEBUG 1500 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1501 printf("%s: MAC tx fault, status %x\n", 1502 device_xname(sc->sc_dev), txstat); 1503 #endif 1504 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1505 cas_init(ifp); 1506 } 1507 if (status & CAS_INTR_RX_MAC) { 1508 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1509 #ifdef CAS_DEBUG 1510 if (rxstat & ~CAS_MAC_RX_DONE) 1511 printf("%s: MAC rx fault, status %x\n", 1512 device_xname(sc->sc_dev), rxstat); 1513 #endif 1514 /* 1515 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1516 * due to a silicon bug so handle them silently. 1517 */ 1518 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1519 ifp->if_ierrors++; 1520 cas_init(ifp); 1521 } 1522 #ifdef CAS_DEBUG 1523 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1524 printf("%s: MAC rx fault, status %x\n", 1525 device_xname(sc->sc_dev), rxstat); 1526 #endif 1527 } 1528 #if NRND > 0 1529 rnd_add_uint32(&sc->rnd_source, status); 1530 #endif 1531 return (r); 1532 } 1533 1534 1535 void 1536 cas_watchdog(struct ifnet *ifp) 1537 { 1538 struct cas_softc *sc = ifp->if_softc; 1539 1540 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1541 "CAS_MAC_RX_CONFIG %x\n", 1542 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1543 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1544 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1545 1546 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1547 ++ifp->if_oerrors; 1548 1549 /* Try to get more packets going. */ 1550 cas_init(ifp); 1551 } 1552 1553 /* 1554 * Initialize the MII Management Interface 1555 */ 1556 void 1557 cas_mifinit(struct cas_softc *sc) 1558 { 1559 bus_space_tag_t t = sc->sc_memt; 1560 bus_space_handle_t mif = sc->sc_memh; 1561 1562 /* Configure the MIF in frame mode */ 1563 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1564 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1565 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1566 } 1567 1568 /* 1569 * MII interface 1570 * 1571 * The Cassini MII interface supports at least three different operating modes: 1572 * 1573 * Bitbang mode is implemented using data, clock and output enable registers. 1574 * 1575 * Frame mode is implemented by loading a complete frame into the frame 1576 * register and polling the valid bit for completion. 1577 * 1578 * Polling mode uses the frame register but completion is indicated by 1579 * an interrupt. 1580 * 1581 */ 1582 int 1583 cas_mii_readreg(device_t self, int phy, int reg) 1584 { 1585 struct cas_softc *sc = device_private(self); 1586 bus_space_tag_t t = sc->sc_memt; 1587 bus_space_handle_t mif = sc->sc_memh; 1588 int n; 1589 u_int32_t v; 1590 1591 #ifdef CAS_DEBUG 1592 if (sc->sc_debug) 1593 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1594 #endif 1595 1596 /* Construct the frame command */ 1597 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1598 CAS_MIF_FRAME_READ; 1599 1600 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1601 for (n = 0; n < 100; n++) { 1602 DELAY(1); 1603 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1604 if (v & CAS_MIF_FRAME_TA0) 1605 return (v & CAS_MIF_FRAME_DATA); 1606 } 1607 1608 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1609 return (0); 1610 } 1611 1612 void 1613 cas_mii_writereg(device_t self, int phy, int reg, int val) 1614 { 1615 struct cas_softc *sc = device_private(self); 1616 bus_space_tag_t t = sc->sc_memt; 1617 bus_space_handle_t mif = sc->sc_memh; 1618 int n; 1619 u_int32_t v; 1620 1621 #ifdef CAS_DEBUG 1622 if (sc->sc_debug) 1623 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1624 phy, reg, val); 1625 #endif 1626 1627 /* Construct the frame command */ 1628 v = CAS_MIF_FRAME_WRITE | 1629 (phy << CAS_MIF_PHY_SHIFT) | 1630 (reg << CAS_MIF_REG_SHIFT) | 1631 (val & CAS_MIF_FRAME_DATA); 1632 1633 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1634 for (n = 0; n < 100; n++) { 1635 DELAY(1); 1636 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1637 if (v & CAS_MIF_FRAME_TA0) 1638 return; 1639 } 1640 1641 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1642 } 1643 1644 void 1645 cas_mii_statchg(device_t self) 1646 { 1647 struct cas_softc *sc = device_private(self); 1648 #ifdef CAS_DEBUG 1649 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1650 #endif 1651 bus_space_tag_t t = sc->sc_memt; 1652 bus_space_handle_t mac = sc->sc_memh; 1653 u_int32_t v; 1654 1655 #ifdef CAS_DEBUG 1656 if (sc->sc_debug) 1657 printf("cas_mii_statchg: status change: phy = %d\n", 1658 sc->sc_phys[instance]); 1659 #endif 1660 1661 /* Set tx full duplex options */ 1662 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1663 delay(10000); /* reg must be cleared and delay before changing. */ 1664 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1665 CAS_MAC_TX_ENABLE; 1666 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1667 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1668 } 1669 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1670 1671 /* XIF Configuration */ 1672 v = CAS_MAC_XIF_TX_MII_ENA; 1673 v |= CAS_MAC_XIF_LINK_LED; 1674 1675 /* MII needs echo disable if half duplex. */ 1676 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1677 /* turn on full duplex LED */ 1678 v |= CAS_MAC_XIF_FDPLX_LED; 1679 else 1680 /* half duplex -- disable echo */ 1681 v |= CAS_MAC_XIF_ECHO_DISABL; 1682 1683 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1684 case IFM_1000_T: /* Gigabit using GMII interface */ 1685 case IFM_1000_SX: 1686 v |= CAS_MAC_XIF_GMII_MODE; 1687 break; 1688 default: 1689 v &= ~CAS_MAC_XIF_GMII_MODE; 1690 } 1691 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1692 } 1693 1694 int 1695 cas_pcs_readreg(device_t self, int phy, int reg) 1696 { 1697 struct cas_softc *sc = device_private(self); 1698 bus_space_tag_t t = sc->sc_memt; 1699 bus_space_handle_t pcs = sc->sc_memh; 1700 1701 #ifdef CAS_DEBUG 1702 if (sc->sc_debug) 1703 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1704 #endif 1705 1706 if (phy != CAS_PHYAD_EXTERNAL) 1707 return (0); 1708 1709 switch (reg) { 1710 case MII_BMCR: 1711 reg = CAS_MII_CONTROL; 1712 break; 1713 case MII_BMSR: 1714 reg = CAS_MII_STATUS; 1715 break; 1716 case MII_ANAR: 1717 reg = CAS_MII_ANAR; 1718 break; 1719 case MII_ANLPAR: 1720 reg = CAS_MII_ANLPAR; 1721 break; 1722 case MII_EXTSR: 1723 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1724 default: 1725 return (0); 1726 } 1727 1728 return bus_space_read_4(t, pcs, reg); 1729 } 1730 1731 void 1732 cas_pcs_writereg(device_t self, int phy, int reg, int val) 1733 { 1734 struct cas_softc *sc = device_private(self); 1735 bus_space_tag_t t = sc->sc_memt; 1736 bus_space_handle_t pcs = sc->sc_memh; 1737 int reset = 0; 1738 1739 #ifdef CAS_DEBUG 1740 if (sc->sc_debug) 1741 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1742 phy, reg, val); 1743 #endif 1744 1745 if (phy != CAS_PHYAD_EXTERNAL) 1746 return; 1747 1748 if (reg == MII_ANAR) 1749 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1750 1751 switch (reg) { 1752 case MII_BMCR: 1753 reset = (val & CAS_MII_CONTROL_RESET); 1754 reg = CAS_MII_CONTROL; 1755 break; 1756 case MII_BMSR: 1757 reg = CAS_MII_STATUS; 1758 break; 1759 case MII_ANAR: 1760 reg = CAS_MII_ANAR; 1761 break; 1762 case MII_ANLPAR: 1763 reg = CAS_MII_ANLPAR; 1764 break; 1765 default: 1766 return; 1767 } 1768 1769 bus_space_write_4(t, pcs, reg, val); 1770 1771 if (reset) 1772 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1773 1774 if (reg == CAS_MII_ANAR || reset) 1775 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1776 CAS_MII_CONFIG_ENABLE); 1777 } 1778 1779 int 1780 cas_mediachange(struct ifnet *ifp) 1781 { 1782 struct cas_softc *sc = ifp->if_softc; 1783 struct mii_data *mii = &sc->sc_mii; 1784 1785 if (mii->mii_instance) { 1786 struct mii_softc *miisc; 1787 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1788 mii_phy_reset(miisc); 1789 } 1790 1791 return (mii_mediachg(&sc->sc_mii)); 1792 } 1793 1794 void 1795 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1796 { 1797 struct cas_softc *sc = ifp->if_softc; 1798 1799 mii_pollstat(&sc->sc_mii); 1800 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1801 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1802 } 1803 1804 /* 1805 * Process an ioctl request. 1806 */ 1807 int 1808 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1809 { 1810 struct cas_softc *sc = ifp->if_softc; 1811 int s, error = 0; 1812 1813 s = splnet(); 1814 1815 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1816 error = 0; 1817 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1818 ; 1819 else if (ifp->if_flags & IFF_RUNNING) { 1820 /* 1821 * Multicast list has changed; set the hardware filter 1822 * accordingly. 1823 */ 1824 cas_iff(sc); 1825 } 1826 } 1827 1828 splx(s); 1829 return (error); 1830 } 1831 1832 static bool 1833 cas_suspend(device_t self, pmf_qual_t qual) 1834 { 1835 struct cas_softc *sc = device_private(self); 1836 bus_space_tag_t t = sc->sc_memt; 1837 bus_space_handle_t h = sc->sc_memh; 1838 1839 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1840 if (sc->sc_ih != NULL) { 1841 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1842 sc->sc_ih = NULL; 1843 } 1844 1845 return true; 1846 } 1847 1848 static bool 1849 cas_resume(device_t self, pmf_qual_t qual) 1850 { 1851 struct cas_softc *sc = device_private(self); 1852 1853 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1854 } 1855 1856 static bool 1857 cas_estintr(struct cas_softc *sc, int what) 1858 { 1859 bus_space_tag_t t = sc->sc_memt; 1860 bus_space_handle_t h = sc->sc_memh; 1861 const char *intrstr = NULL; 1862 1863 /* PCI interrupts */ 1864 if (what & CAS_INTR_PCI) { 1865 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle); 1866 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1867 IPL_NET, cas_intr, sc); 1868 if (sc->sc_ih == NULL) { 1869 aprint_error_dev(sc->sc_dev, 1870 "unable to establish interrupt"); 1871 if (intrstr != NULL) 1872 aprint_error(" at %s", intrstr); 1873 aprint_error("\n"); 1874 return false; 1875 } 1876 1877 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1878 } 1879 1880 /* Interrupt register */ 1881 if (what & CAS_INTR_REG) { 1882 bus_space_write_4(t, h, CAS_INTMASK, 1883 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1884 CAS_INTR_TX_TAG_ERR| 1885 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1886 CAS_INTR_RX_TAG_ERR| 1887 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1888 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1889 CAS_INTR_BERR)); 1890 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1891 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1892 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1893 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1894 } 1895 return true; 1896 } 1897 1898 bool 1899 cas_shutdown(device_t self, int howto) 1900 { 1901 struct cas_softc *sc = device_private(self); 1902 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1903 1904 cas_stop(ifp, 1); 1905 1906 return true; 1907 } 1908 1909 void 1910 cas_iff(struct cas_softc *sc) 1911 { 1912 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1913 struct ethercom *ec = &sc->sc_ethercom; 1914 struct ether_multi *enm; 1915 struct ether_multistep step; 1916 bus_space_tag_t t = sc->sc_memt; 1917 bus_space_handle_t h = sc->sc_memh; 1918 u_int32_t crc, hash[16], rxcfg; 1919 int i; 1920 1921 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1922 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1923 CAS_MAC_RX_PROMISC_GRP); 1924 ifp->if_flags &= ~IFF_ALLMULTI; 1925 1926 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1927 ifp->if_flags |= IFF_ALLMULTI; 1928 if (ifp->if_flags & IFF_PROMISC) 1929 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1930 else 1931 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1932 } else { 1933 /* 1934 * Set up multicast address filter by passing all multicast 1935 * addresses through a crc generator, and then using the 1936 * high order 8 bits as an index into the 256 bit logical 1937 * address filter. The high order 4 bits selects the word, 1938 * while the other 4 bits select the bit within the word 1939 * (where bit 0 is the MSB). 1940 */ 1941 1942 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1943 1944 /* Clear hash table */ 1945 for (i = 0; i < 16; i++) 1946 hash[i] = 0; 1947 1948 ETHER_FIRST_MULTI(step, ec, enm); 1949 while (enm != NULL) { 1950 crc = ether_crc32_le(enm->enm_addrlo, 1951 ETHER_ADDR_LEN); 1952 1953 /* Just want the 8 most significant bits. */ 1954 crc >>= 24; 1955 1956 /* Set the corresponding bit in the filter. */ 1957 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1958 1959 ETHER_NEXT_MULTI(step, enm); 1960 } 1961 1962 /* Now load the hash table into the chip (if we are using it) */ 1963 for (i = 0; i < 16; i++) { 1964 bus_space_write_4(t, h, 1965 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1966 hash[i]); 1967 } 1968 } 1969 1970 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1971 } 1972 1973 int 1974 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1975 { 1976 u_int64_t flags; 1977 u_int32_t cur, frag, i; 1978 bus_dmamap_t map; 1979 1980 cur = frag = *bixp; 1981 map = sc->sc_txd[cur].sd_map; 1982 1983 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1984 BUS_DMA_NOWAIT) != 0) { 1985 return (ENOBUFS); 1986 } 1987 1988 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1989 bus_dmamap_unload(sc->sc_dmatag, map); 1990 return (ENOBUFS); 1991 } 1992 1993 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1994 BUS_DMASYNC_PREWRITE); 1995 1996 for (i = 0; i < map->dm_nsegs; i++) { 1997 sc->sc_txdescs[frag].cd_addr = 1998 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1999 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 2000 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 2001 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 2002 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 2003 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 2004 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 2005 BUS_DMASYNC_PREWRITE); 2006 cur = frag; 2007 if (++frag == CAS_NTXDESC) 2008 frag = 0; 2009 } 2010 2011 sc->sc_tx_cnt += map->dm_nsegs; 2012 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 2013 sc->sc_txd[cur].sd_map = map; 2014 sc->sc_txd[cur].sd_mbuf = mhead; 2015 2016 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 2017 2018 *bixp = frag; 2019 2020 /* sync descriptors */ 2021 2022 return (0); 2023 } 2024 2025 /* 2026 * Transmit interrupt. 2027 */ 2028 int 2029 cas_tint(struct cas_softc *sc, u_int32_t status) 2030 { 2031 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2032 struct cas_sxd *sd; 2033 u_int32_t cons, comp; 2034 2035 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2036 cons = sc->sc_tx_cons; 2037 while (cons != comp) { 2038 sd = &sc->sc_txd[cons]; 2039 if (sd->sd_mbuf != NULL) { 2040 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2041 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2042 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2043 m_freem(sd->sd_mbuf); 2044 sd->sd_mbuf = NULL; 2045 ifp->if_opackets++; 2046 } 2047 sc->sc_tx_cnt--; 2048 if (++cons == CAS_NTXDESC) 2049 cons = 0; 2050 } 2051 sc->sc_tx_cons = cons; 2052 2053 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2054 ifp->if_flags &= ~IFF_OACTIVE; 2055 if (sc->sc_tx_cnt == 0) 2056 ifp->if_timer = 0; 2057 2058 cas_start(ifp); 2059 2060 return (1); 2061 } 2062 2063 void 2064 cas_start(struct ifnet *ifp) 2065 { 2066 struct cas_softc *sc = ifp->if_softc; 2067 struct mbuf *m; 2068 u_int32_t bix; 2069 2070 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2071 return; 2072 2073 bix = sc->sc_tx_prod; 2074 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2075 IFQ_POLL(&ifp->if_snd, m); 2076 if (m == NULL) 2077 break; 2078 2079 #if NBPFILTER > 0 2080 /* 2081 * If BPF is listening on this interface, let it see the 2082 * packet before we commit it to the wire. 2083 */ 2084 if (ifp->if_bpf) 2085 bpf_mtap(ifp->if_bpf, m); 2086 #endif 2087 2088 /* 2089 * Encapsulate this packet and start it going... 2090 * or fail... 2091 */ 2092 if (cas_encap(sc, m, &bix)) { 2093 ifp->if_flags |= IFF_OACTIVE; 2094 break; 2095 } 2096 2097 IFQ_DEQUEUE(&ifp->if_snd, m); 2098 ifp->if_timer = 5; 2099 } 2100 2101 sc->sc_tx_prod = bix; 2102 } 2103
Indexes created Thu Oct 02 01:09:59 GMT 2025