if_cas.c revision 1.37.2.1
1 /* $NetBSD: if_cas.c,v 1.37.2.1 2020/02/29 20:19:10 ad Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.37.2.1 2020/02/29 20:19:10 ad Exp $"); 48 49 #ifndef _MODULE 50 #include "opt_inet.h" 51 #endif 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/module.h> 65 66 #include <machine/endian.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #include <net/bpf.h> 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 #include <sys/rndsource.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/mii_bitbang.h> 91 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcidevs.h> 95 #include <prop/proplib.h> 96 97 #include <dev/pci/if_casreg.h> 98 #include <dev/pci/if_casvar.h> 99 100 #define TRIES 10000 101 102 static bool cas_estintr(struct cas_softc *sc, int); 103 bool cas_shutdown(device_t, int); 104 static bool cas_suspend(device_t, const pmf_qual_t *); 105 static bool cas_resume(device_t, const pmf_qual_t *); 106 static int cas_detach(device_t, int); 107 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 108 109 int cas_match(device_t, cfdata_t, void *); 110 void cas_attach(device_t, device_t, void *); 111 112 113 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 114 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 115 DVF_DETACH_SHUTDOWN); 116 117 int cas_pci_readvpd(struct cas_softc *, struct pci_attach_args *, uint8_t *); 118 119 void cas_config(struct cas_softc *, const uint8_t *); 120 void cas_start(struct ifnet *); 121 void cas_stop(struct ifnet *, int); 122 int cas_ioctl(struct ifnet *, u_long, void *); 123 void cas_tick(void *); 124 void cas_watchdog(struct ifnet *); 125 int cas_init(struct ifnet *); 126 void cas_init_regs(struct cas_softc *); 127 int cas_ringsize(int); 128 int cas_cringsize(int); 129 int cas_meminit(struct cas_softc *); 130 void cas_mifinit(struct cas_softc *); 131 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 132 uint32_t, uint32_t); 133 void cas_reset(struct cas_softc *); 134 int cas_reset_rx(struct cas_softc *); 135 int cas_reset_tx(struct cas_softc *); 136 int cas_disable_rx(struct cas_softc *); 137 int cas_disable_tx(struct cas_softc *); 138 void cas_rxdrain(struct cas_softc *); 139 int cas_add_rxbuf(struct cas_softc *, int); 140 void cas_iff(struct cas_softc *); 141 int cas_encap(struct cas_softc *, struct mbuf *, uint32_t *); 142 143 /* MII methods & callbacks */ 144 int cas_mii_readreg(device_t, int, int, uint16_t*); 145 int cas_mii_writereg(device_t, int, int, uint16_t); 146 void cas_mii_statchg(struct ifnet *); 147 int cas_pcs_readreg(device_t, int, int, uint16_t *); 148 int cas_pcs_writereg(device_t, int, int, uint16_t); 149 150 int cas_mediachange(struct ifnet *); 151 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 152 153 int cas_eint(struct cas_softc *, u_int); 154 int cas_rint(struct cas_softc *); 155 int cas_tint(struct cas_softc *, uint32_t); 156 int cas_pint(struct cas_softc *); 157 int cas_intr(void *); 158 159 #ifdef CAS_DEBUG 160 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 161 printf x 162 #else 163 #define DPRINTF(sc, x) /* nothing */ 164 #endif 165 166 static const struct cas_pci_dev { 167 uint16_t cpd_vendor; 168 uint16_t cpd_device; 169 int cpd_variant; 170 } cas_pci_devlist[] = { 171 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_CASSINI, CAS_CAS }, 172 { PCI_VENDOR_NS, PCI_PRODUCT_NS_SATURN, CAS_SATURN }, 173 { 0, 0, 0 } 174 }; 175 176 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 177 #define CAS_PHY_INTERFACE "phy-interface" 178 #define CAS_PHY_TYPE "phy-type" 179 #define CAS_PHY_TYPE_PCS "pcs" 180 181 int 182 cas_match(device_t parent, cfdata_t cf, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 int i; 186 187 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 188 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 189 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) 190 return 1; 191 } 192 193 return 0; 194 } 195 196 #define PROMHDR_PTR_DATA 0x18 197 #define PROMDATA_PTR_VPD 0x08 198 #define PROMDATA_DATA2 0x0a 199 200 static const uint8_t cas_promhdr[] = { 0x55, 0xaa }; 201 static const uint8_t cas_promdat[] = { 202 'P', 'C', 'I', 'R', 203 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 204 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 205 }; 206 static const uint8_t cas_promdat_ns[] = { 207 'P', 'C', 'I', 'R', 208 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 209 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 210 }; 211 212 static const uint8_t cas_promdat2[] = { 213 0x18, 0x00, /* structure length */ 214 0x00, /* structure revision */ 215 0x00, /* interface revision */ 216 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 217 PCI_CLASS_NETWORK /* class code */ 218 }; 219 220 #define CAS_LMA_MAXNUM 4 221 int 222 cas_pci_readvpd(struct cas_softc *sc, struct pci_attach_args *pa, 223 uint8_t *enaddr) 224 { 225 struct pci_vpd_largeres *res; 226 struct pci_vpd *vpd; 227 bus_space_handle_t romh; 228 bus_space_tag_t romt; 229 bus_size_t romsize = 0; 230 uint8_t enaddrs[CAS_LMA_MAXNUM][ETHER_ADDR_LEN]; 231 bool pcs[4] = {false, false, false, false}; 232 uint8_t buf[32], *desc; 233 pcireg_t address; 234 int dataoff, vpdoff, len, lma = 0, phy = 0; 235 int i, rv = -1; 236 237 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 238 &romt, &romh, NULL, &romsize)) 239 return (-1); 240 241 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 242 address |= PCI_MAPREG_ROM_ENABLE; 243 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 244 245 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 246 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 247 goto fail; 248 249 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 250 if (dataoff < 0x1c) 251 goto fail; 252 253 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 254 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 255 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 256 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 257 goto fail; 258 259 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 260 if (vpdoff < 0x1c) 261 goto fail; 262 263 next: 264 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 265 if (!PCI_VPDRES_ISLARGE(buf[0])) 266 goto fail; 267 268 res = (struct pci_vpd_largeres *)buf; 269 vpdoff += sizeof(*res); 270 271 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 272 switch (PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 273 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 274 /* Skip identifier string. */ 275 vpdoff += len; 276 goto next; 277 278 case PCI_VPDRES_TYPE_VPD: 279 #ifdef CAS_DEBUG 280 printf("\n"); 281 for (i = 0; i < len; i++) { 282 uint8_t byte; 283 if (i % 16 == 0) 284 printf("%04x :", i); 285 byte = bus_space_read_1(romt, romh, vpdoff + i); 286 printf(" %02x", byte); 287 if (i % 16 == 15) 288 printf("\n"); 289 } 290 printf("\n"); 291 #endif 292 293 while (len > 0) { 294 bus_space_read_region_1(romt, romh, vpdoff, 295 buf, sizeof(buf)); 296 297 vpd = (struct pci_vpd *)buf; 298 vpdoff += sizeof(*vpd) + vpd->vpd_len; 299 len -= sizeof(*vpd) + vpd->vpd_len; 300 301 /* 302 * We're looking for an "Enhanced" VPD... 303 */ 304 if (vpd->vpd_key0 != 'Z') 305 continue; 306 307 desc = buf + sizeof(*vpd); 308 309 /* 310 * ...which is an instance property... 311 */ 312 if (desc[0] != 'I') 313 continue; 314 desc += 3; 315 316 if (desc[0] == 'B' || desc[1] == ETHER_ADDR_LEN) { 317 /* 318 * ...that's a byte array with the proper 319 * length for a MAC address... 320 */ 321 desc += 2; 322 323 /* 324 * ...named "local-mac-address". 325 */ 326 if (strcmp(desc, CAS_LOCAL_MAC_ADDRESS) != 0) 327 continue; 328 desc += sizeof(CAS_LOCAL_MAC_ADDRESS); 329 330 if (lma == CAS_LMA_MAXNUM) 331 continue; 332 333 memcpy(enaddrs[lma], desc, ETHER_ADDR_LEN); 334 lma++; 335 rv = 0; 336 continue; 337 } else if (desc[0] == 'S') { 338 size_t k; 339 340 /* String */ 341 desc += 2; 342 #ifdef CAS_DEBUG 343 /* ...named "pcs". */ 344 printf("STR: \"%s\"\n", desc); 345 if (strcmp(desc, CAS_PHY_TYPE_PCS) != 0) 346 continue; 347 desc += sizeof(CAS_PHY_TYPE_PCS); 348 printf("STR: \"%s\"\n", desc); 349 #endif 350 /* ...named "phy-interface" or "phy-type". */ 351 if (strcmp(desc, CAS_PHY_INTERFACE) == 0) 352 k = sizeof(CAS_PHY_INTERFACE); 353 else if (strcmp(desc, CAS_PHY_TYPE) == 0) 354 k = sizeof(CAS_PHY_TYPE); 355 else 356 continue; 357 358 desc += k; 359 #ifdef CAS_DEBUG 360 printf("STR: \"%s\"\n", desc); 361 #endif 362 if (strcmp(desc, CAS_PHY_TYPE_PCS) == 0) 363 pcs[phy] = true; 364 phy++; 365 continue; 366 } 367 } 368 break; 369 370 default: 371 goto fail; 372 } 373 374 /* 375 * Multi port card has bridge chip. The device number is fixed: 376 * e.g. 377 * p0: 005:00:0 378 * p1: 005:01:0 379 * p2: 006:02:0 380 * p3: 006:03:0 381 */ 382 if (enaddr != 0) { 383 i = 0; 384 if ((lma > 1) && (pa->pa_device < CAS_LMA_MAXNUM) 385 && (pa->pa_device < lma)) 386 i = pa->pa_device; 387 memcpy(enaddr, enaddrs[i], ETHER_ADDR_LEN); 388 } 389 if (pcs[pa->pa_device]) 390 sc->sc_flags |= CAS_SERDES; 391 fail: 392 if (romsize != 0) 393 bus_space_unmap(romt, romh, romsize); 394 395 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 396 address &= ~PCI_MAPREG_ROM_ENABLE; 397 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 398 399 return (rv); 400 } 401 402 void 403 cas_attach(device_t parent, device_t self, void *aux) 404 { 405 struct pci_attach_args *pa = aux; 406 struct cas_softc *sc = device_private(self); 407 int i; 408 prop_data_t data; 409 uint8_t enaddr[ETHER_ADDR_LEN]; 410 411 sc->sc_dev = self; 412 pci_aprint_devinfo(pa, NULL); 413 sc->sc_rev = PCI_REVISION(pa->pa_class); 414 sc->sc_dmatag = pa->pa_dmat; 415 416 sc->sc_variant = CAS_UNKNOWN; 417 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 418 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 419 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) { 420 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 421 break; 422 } 423 } 424 aprint_debug_dev(sc->sc_dev, "variant = %d\n", sc->sc_variant); 425 if (sc->sc_variant == CAS_UNKNOWN) { 426 aprint_error_dev(sc->sc_dev, "unknown adaptor\n"); 427 return; 428 } 429 430 #define PCI_CAS_BASEADDR 0x10 431 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 432 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 433 aprint_error_dev(sc->sc_dev, 434 "unable to map device registers\n"); 435 return; 436 } 437 438 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 439 "mac-address")) != NULL) 440 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 441 if (cas_pci_readvpd(sc, pa, (data == NULL) ? enaddr : 0) != 0) { 442 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 443 memset(enaddr, 0, sizeof(enaddr)); 444 } 445 446 sc->sc_burst = 16; /* XXX */ 447 448 sc->sc_att_stage = CAS_ATT_BACKEND_0; 449 450 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 451 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 452 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 453 return; 454 } 455 sc->sc_pc = pa->pa_pc; 456 if (!cas_estintr(sc, CAS_INTR_PCI)) { 457 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 458 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 459 return; 460 } 461 462 sc->sc_att_stage = CAS_ATT_BACKEND_1; 463 464 /* 465 * call the main configure 466 */ 467 cas_config(sc, enaddr); 468 469 if (pmf_device_register1(sc->sc_dev, 470 cas_suspend, cas_resume, cas_shutdown)) 471 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 472 else 473 aprint_error_dev(sc->sc_dev, 474 "could not establish power handlers\n"); 475 476 sc->sc_att_stage = CAS_ATT_FINISHED; 477 /*FALLTHROUGH*/ 478 } 479 480 /* 481 * cas_config: 482 * 483 * Attach a Cassini interface to the system. 484 */ 485 void 486 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 487 { 488 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 489 struct mii_data *mii = &sc->sc_mii; 490 struct mii_softc *child; 491 uint32_t reg; 492 int i, error; 493 494 /* Make sure the chip is stopped. */ 495 ifp->if_softc = sc; 496 cas_reset(sc); 497 498 /* 499 * Allocate the control data structures, and create and load the 500 * DMA map for it. 501 */ 502 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 503 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 504 1, &sc->sc_cdnseg, 0)) != 0) { 505 aprint_error_dev(sc->sc_dev, 506 "unable to allocate control data, error = %d\n", 507 error); 508 cas_partial_detach(sc, CAS_ATT_0); 509 } 510 511 /* XXX should map this in with correct endianness */ 512 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, 513 sc->sc_cdnseg, sizeof(struct cas_control_data), 514 (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) { 515 aprint_error_dev(sc->sc_dev, 516 "unable to map control data, error = %d\n", error); 517 cas_partial_detach(sc, CAS_ATT_1); 518 } 519 520 if ((error = bus_dmamap_create(sc->sc_dmatag, 521 sizeof(struct cas_control_data), 1, 522 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 523 aprint_error_dev(sc->sc_dev, 524 "unable to create control data DMA map, error = %d\n", 525 error); 526 cas_partial_detach(sc, CAS_ATT_2); 527 } 528 529 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 530 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 531 0)) != 0) { 532 aprint_error_dev(sc->sc_dev, 533 "unable to load control data DMA map, error = %d\n", 534 error); 535 cas_partial_detach(sc, CAS_ATT_3); 536 } 537 538 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 539 540 /* 541 * Create the receive buffer DMA maps. 542 */ 543 for (i = 0; i < CAS_NRXDESC; i++) { 544 bus_dma_segment_t seg; 545 char *kva; 546 int rseg; 547 548 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 549 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 550 aprint_error_dev(sc->sc_dev, 551 "unable to alloc rx DMA mem %d, error = %d\n", 552 i, error); 553 cas_partial_detach(sc, CAS_ATT_5); 554 } 555 sc->sc_rxsoft[i].rxs_dmaseg = seg; 556 557 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 558 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 559 aprint_error_dev(sc->sc_dev, 560 "unable to alloc rx DMA mem %d, error = %d\n", 561 i, error); 562 cas_partial_detach(sc, CAS_ATT_5); 563 } 564 sc->sc_rxsoft[i].rxs_kva = kva; 565 566 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 567 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 568 aprint_error_dev(sc->sc_dev, 569 "unable to create rx DMA map %d, error = %d\n", 570 i, error); 571 cas_partial_detach(sc, CAS_ATT_5); 572 } 573 574 if ((error = bus_dmamap_load(sc->sc_dmatag, 575 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 576 BUS_DMA_NOWAIT)) != 0) { 577 aprint_error_dev(sc->sc_dev, 578 "unable to load rx DMA map %d, error = %d\n", 579 i, error); 580 cas_partial_detach(sc, CAS_ATT_5); 581 } 582 } 583 584 /* 585 * Create the transmit buffer DMA maps. 586 */ 587 for (i = 0; i < CAS_NTXDESC; i++) { 588 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 589 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 590 &sc->sc_txd[i].sd_map)) != 0) { 591 aprint_error_dev(sc->sc_dev, 592 "unable to create tx DMA map %d, error = %d\n", 593 i, error); 594 cas_partial_detach(sc, CAS_ATT_6); 595 } 596 sc->sc_txd[i].sd_mbuf = NULL; 597 } 598 599 /* 600 * From this point forward, the attachment cannot fail. A failure 601 * before this point releases all resources that may have been 602 * allocated. 603 */ 604 605 /* Announce ourselves. */ 606 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 607 ether_sprintf(enaddr)); 608 aprint_naive(": Ethernet controller\n"); 609 610 /* Get RX FIFO size */ 611 sc->sc_rxfifosize = 16 * 1024; 612 613 /* Initialize ifnet structure. */ 614 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 615 ifp->if_softc = sc; 616 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 617 ifp->if_start = cas_start; 618 ifp->if_ioctl = cas_ioctl; 619 ifp->if_watchdog = cas_watchdog; 620 ifp->if_stop = cas_stop; 621 ifp->if_init = cas_init; 622 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 623 IFQ_SET_READY(&ifp->if_snd); 624 625 /* Initialize ifmedia structures and MII info */ 626 mii->mii_ifp = ifp; 627 mii->mii_readreg = cas_mii_readreg; 628 mii->mii_writereg = cas_mii_writereg; 629 mii->mii_statchg = cas_mii_statchg; 630 631 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 632 sc->sc_ethercom.ec_mii = mii; 633 634 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 635 636 cas_mifinit(sc); 637 638 if (sc->sc_mif_config & (CAS_MIF_CONFIG_MDI1 | CAS_MIF_CONFIG_MDI0)) { 639 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 640 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 641 bus_space_write_4(sc->sc_memt, sc->sc_memh, 642 CAS_MIF_CONFIG, sc->sc_mif_config); 643 } 644 /* Enable/unfreeze the GMII pins of Saturn. */ 645 if (sc->sc_variant == CAS_SATURN) { 646 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 647 CAS_SATURN_PCFG) & ~CAS_SATURN_PCFG_FSI; 648 if ((sc->sc_mif_config & CAS_MIF_CONFIG_MDI0) != 0) 649 reg |= CAS_SATURN_PCFG_FSI; 650 bus_space_write_4(sc->sc_memt, sc->sc_memh, 651 CAS_SATURN_PCFG, reg); 652 /* Read to flush */ 653 bus_space_read_4(sc->sc_memt, sc->sc_memh, 654 CAS_SATURN_PCFG); 655 DELAY(10000); 656 } 657 } 658 659 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 660 MII_OFFSET_ANY, 0); 661 662 child = LIST_FIRST(&mii->mii_phys); 663 if (child == NULL && 664 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0 | CAS_MIF_CONFIG_MDI1)) { 665 /* 666 * Try the external PCS SERDES if we didn't find any 667 * MII devices. 668 */ 669 bus_space_write_4(sc->sc_memt, sc->sc_memh, 670 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 671 672 bus_space_write_4(sc->sc_memt, sc->sc_memh, 673 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 674 675 mii->mii_readreg = cas_pcs_readreg; 676 mii->mii_writereg = cas_pcs_writereg; 677 678 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 679 MII_OFFSET_ANY, MIIF_NOISOLATE); 680 } 681 682 child = LIST_FIRST(&mii->mii_phys); 683 if (child == NULL) { 684 /* No PHY attached */ 685 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 686 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 687 } else { 688 /* 689 * Walk along the list of attached MII devices and 690 * establish an `MII instance' to `phy number' 691 * mapping. We'll use this mapping in media change 692 * requests to determine which phy to use to program 693 * the MIF configuration register. 694 */ 695 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 696 /* 697 * Note: we support just two PHYs: the built-in 698 * internal device and an external on the MII 699 * connector. 700 */ 701 if (child->mii_phy > 1 || child->mii_inst > 1) { 702 aprint_error_dev(sc->sc_dev, 703 "cannot accommodate MII device %s" 704 " at phy %d, instance %d\n", 705 device_xname(child->mii_dev), 706 child->mii_phy, child->mii_inst); 707 continue; 708 } 709 710 sc->sc_phys[child->mii_inst] = child->mii_phy; 711 } 712 713 /* 714 * XXX - we can really do the following ONLY if the 715 * phy indeed has the auto negotiation capability!! 716 */ 717 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 718 } 719 720 /* claim 802.1q capability */ 721 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 722 723 /* Attach the interface. */ 724 if_attach(ifp); 725 if_deferred_start_init(ifp, NULL); 726 ether_ifattach(ifp, enaddr); 727 728 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 729 RND_TYPE_NET, RND_FLAG_DEFAULT); 730 731 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 732 NULL, device_xname(sc->sc_dev), "interrupts"); 733 734 callout_init(&sc->sc_tick_ch, 0); 735 callout_setfunc(&sc->sc_tick_ch, cas_tick, sc); 736 737 return; 738 } 739 740 int 741 cas_detach(device_t self, int flags) 742 { 743 int i; 744 struct cas_softc *sc = device_private(self); 745 bus_space_tag_t t = sc->sc_memt; 746 bus_space_handle_t h = sc->sc_memh; 747 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 748 749 /* 750 * Free any resources we've allocated during the failed attach 751 * attempt. Do this in reverse order and fall through. 752 */ 753 switch (sc->sc_att_stage) { 754 case CAS_ATT_FINISHED: 755 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 756 pmf_device_deregister(self); 757 cas_stop(&sc->sc_ethercom.ec_if, 1); 758 evcnt_detach(&sc->sc_ev_intr); 759 760 rnd_detach_source(&sc->rnd_source); 761 762 ether_ifdetach(ifp); 763 if_detach(ifp); 764 ifmedia_fini(&sc->sc_mii.mii_media); 765 766 callout_destroy(&sc->sc_tick_ch); 767 768 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 769 770 /*FALLTHROUGH*/ 771 case CAS_ATT_MII: 772 case CAS_ATT_7: 773 case CAS_ATT_6: 774 for (i = 0; i < CAS_NTXDESC; i++) { 775 if (sc->sc_txd[i].sd_map != NULL) 776 bus_dmamap_destroy(sc->sc_dmatag, 777 sc->sc_txd[i].sd_map); 778 } 779 /*FALLTHROUGH*/ 780 case CAS_ATT_5: 781 for (i = 0; i < CAS_NRXDESC; i++) { 782 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 783 bus_dmamap_unload(sc->sc_dmatag, 784 sc->sc_rxsoft[i].rxs_dmamap); 785 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 786 bus_dmamap_destroy(sc->sc_dmatag, 787 sc->sc_rxsoft[i].rxs_dmamap); 788 if (sc->sc_rxsoft[i].rxs_kva != NULL) 789 bus_dmamem_unmap(sc->sc_dmatag, 790 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 791 /* XXX need to check that bus_dmamem_alloc suceeded 792 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 793 */ 794 bus_dmamem_free(sc->sc_dmatag, 795 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 796 } 797 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 798 /*FALLTHROUGH*/ 799 case CAS_ATT_4: 800 case CAS_ATT_3: 801 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 802 /*FALLTHROUGH*/ 803 case CAS_ATT_2: 804 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 805 sizeof(struct cas_control_data)); 806 /*FALLTHROUGH*/ 807 case CAS_ATT_1: 808 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 809 /*FALLTHROUGH*/ 810 case CAS_ATT_0: 811 sc->sc_att_stage = CAS_ATT_0; 812 /*FALLTHROUGH*/ 813 case CAS_ATT_BACKEND_2: 814 case CAS_ATT_BACKEND_1: 815 if (sc->sc_ih != NULL) { 816 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 817 sc->sc_ih = NULL; 818 } 819 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 820 /*FALLTHROUGH*/ 821 case CAS_ATT_BACKEND_0: 822 break; 823 } 824 return 0; 825 } 826 827 static void 828 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 829 { 830 cfattach_t ca = device_cfattach(sc->sc_dev); 831 832 sc->sc_att_stage = stage; 833 (*ca->ca_detach)(sc->sc_dev, 0); 834 } 835 836 void 837 cas_tick(void *arg) 838 { 839 struct cas_softc *sc = arg; 840 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 841 bus_space_tag_t t = sc->sc_memt; 842 bus_space_handle_t mac = sc->sc_memh; 843 int s; 844 uint32_t v; 845 846 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 847 848 /* unload collisions counters */ 849 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 850 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 851 if_statadd_ref(nsr, if_collisions, v + 852 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 853 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT)); 854 if_statadd_ref(nsr, if_oerrors, v); 855 856 /* read error counters */ 857 if_statadd_ref(nsr, if_ierrors, 858 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 859 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 860 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 861 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL)); 862 863 IF_STAT_PUTREF(ifp); 864 865 /* clear the hardware counters */ 866 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 867 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 868 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 869 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 870 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 871 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 872 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 873 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 874 875 s = splnet(); 876 mii_tick(&sc->sc_mii); 877 splx(s); 878 879 callout_schedule(&sc->sc_tick_ch, hz); 880 } 881 882 int 883 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 884 uint32_t clr, uint32_t set) 885 { 886 int i; 887 uint32_t reg; 888 889 for (i = TRIES; i--; DELAY(100)) { 890 reg = bus_space_read_4(sc->sc_memt, h, r); 891 if ((reg & clr) == 0 && (reg & set) == set) 892 return (1); 893 } 894 895 return (0); 896 } 897 898 void 899 cas_reset(struct cas_softc *sc) 900 { 901 bus_space_tag_t t = sc->sc_memt; 902 bus_space_handle_t h = sc->sc_memh; 903 int s; 904 905 s = splnet(); 906 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 907 cas_reset_rx(sc); 908 cas_reset_tx(sc); 909 910 /* Disable interrupts */ 911 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 912 913 /* Do a full reset */ 914 bus_space_write_4(t, h, CAS_RESET, 915 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 916 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 917 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 918 splx(s); 919 } 920 921 922 /* 923 * cas_rxdrain: 924 * 925 * Drain the receive queue. 926 */ 927 void 928 cas_rxdrain(struct cas_softc *sc) 929 { 930 /* Nothing to do yet. */ 931 } 932 933 /* 934 * Reset the whole thing. 935 */ 936 void 937 cas_stop(struct ifnet *ifp, int disable) 938 { 939 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 940 struct cas_sxd *sd; 941 uint32_t i; 942 943 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 944 945 callout_stop(&sc->sc_tick_ch); 946 947 /* 948 * Mark the interface down and cancel the watchdog timer. 949 */ 950 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 951 ifp->if_timer = 0; 952 953 mii_down(&sc->sc_mii); 954 955 cas_reset_rx(sc); 956 cas_reset_tx(sc); 957 958 /* 959 * Release any queued transmit buffers. 960 */ 961 for (i = 0; i < CAS_NTXDESC; i++) { 962 sd = &sc->sc_txd[i]; 963 if (sd->sd_mbuf != NULL) { 964 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 965 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 966 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 967 m_freem(sd->sd_mbuf); 968 sd->sd_mbuf = NULL; 969 } 970 } 971 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 972 973 if (disable) 974 cas_rxdrain(sc); 975 } 976 977 978 /* 979 * Reset the receiver 980 */ 981 int 982 cas_reset_rx(struct cas_softc *sc) 983 { 984 bus_space_tag_t t = sc->sc_memt; 985 bus_space_handle_t h = sc->sc_memh; 986 987 /* 988 * Resetting while DMA is in progress can cause a bus hang, so we 989 * disable DMA first. 990 */ 991 cas_disable_rx(sc); 992 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 993 /* Wait till it finishes */ 994 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 995 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 996 /* Wait 5ms extra. */ 997 delay(5000); 998 999 /* Finally, reset the ERX */ 1000 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 1001 /* Wait till it finishes */ 1002 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 1003 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 1004 return (1); 1005 } 1006 return (0); 1007 } 1008 1009 1010 /* 1011 * Reset the transmitter 1012 */ 1013 int 1014 cas_reset_tx(struct cas_softc *sc) 1015 { 1016 bus_space_tag_t t = sc->sc_memt; 1017 bus_space_handle_t h = sc->sc_memh; 1018 1019 /* 1020 * Resetting while DMA is in progress can cause a bus hang, so we 1021 * disable DMA first. 1022 */ 1023 cas_disable_tx(sc); 1024 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 1025 /* Wait till it finishes */ 1026 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 1027 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 1028 /* Wait 5ms extra. */ 1029 delay(5000); 1030 1031 /* Finally, reset the ETX */ 1032 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 1033 /* Wait till it finishes */ 1034 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 1035 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 1036 return (1); 1037 } 1038 return (0); 1039 } 1040 1041 /* 1042 * Disable receiver. 1043 */ 1044 int 1045 cas_disable_rx(struct cas_softc *sc) 1046 { 1047 bus_space_tag_t t = sc->sc_memt; 1048 bus_space_handle_t h = sc->sc_memh; 1049 uint32_t cfg; 1050 1051 /* Flip the enable bit */ 1052 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1053 cfg &= ~CAS_MAC_RX_ENABLE; 1054 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 1055 1056 /* Wait for it to finish */ 1057 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 1058 } 1059 1060 /* 1061 * Disable transmitter. 1062 */ 1063 int 1064 cas_disable_tx(struct cas_softc *sc) 1065 { 1066 bus_space_tag_t t = sc->sc_memt; 1067 bus_space_handle_t h = sc->sc_memh; 1068 uint32_t cfg; 1069 1070 /* Flip the enable bit */ 1071 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 1072 cfg &= ~CAS_MAC_TX_ENABLE; 1073 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 1074 1075 /* Wait for it to finish */ 1076 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 1077 } 1078 1079 /* 1080 * Initialize interface. 1081 */ 1082 int 1083 cas_meminit(struct cas_softc *sc) 1084 { 1085 int i; 1086 1087 /* 1088 * Initialize the transmit descriptor ring. 1089 */ 1090 for (i = 0; i < CAS_NTXDESC; i++) { 1091 sc->sc_txdescs[i].cd_flags = 0; 1092 sc->sc_txdescs[i].cd_addr = 0; 1093 } 1094 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 1095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1096 1097 /* 1098 * Initialize the receive descriptor and receive job 1099 * descriptor rings. 1100 */ 1101 for (i = 0; i < CAS_NRXDESC; i++) 1102 CAS_INIT_RXDESC(sc, i, i); 1103 sc->sc_rxdptr = 0; 1104 sc->sc_rxptr = 0; 1105 1106 /* 1107 * Initialize the receive completion ring. 1108 */ 1109 for (i = 0; i < CAS_NRXCOMP; i++) { 1110 sc->sc_rxcomps[i].cc_word[0] = 0; 1111 sc->sc_rxcomps[i].cc_word[1] = 0; 1112 sc->sc_rxcomps[i].cc_word[2] = 0; 1113 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1114 CAS_CDRXCSYNC(sc, i, 1115 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1116 } 1117 1118 return (0); 1119 } 1120 1121 int 1122 cas_ringsize(int sz) 1123 { 1124 switch (sz) { 1125 case 32: 1126 return CAS_RING_SZ_32; 1127 case 64: 1128 return CAS_RING_SZ_64; 1129 case 128: 1130 return CAS_RING_SZ_128; 1131 case 256: 1132 return CAS_RING_SZ_256; 1133 case 512: 1134 return CAS_RING_SZ_512; 1135 case 1024: 1136 return CAS_RING_SZ_1024; 1137 case 2048: 1138 return CAS_RING_SZ_2048; 1139 case 4096: 1140 return CAS_RING_SZ_4096; 1141 case 8192: 1142 return CAS_RING_SZ_8192; 1143 default: 1144 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1145 sz); 1146 return CAS_RING_SZ_32; 1147 } 1148 } 1149 1150 int 1151 cas_cringsize(int sz) 1152 { 1153 int i; 1154 1155 for (i = 0; i < 9; i++) 1156 if (sz == (128 << i)) 1157 return i; 1158 1159 aprint_error("cas: invalid completion ring size %d\n", sz); 1160 return 128; 1161 } 1162 1163 /* 1164 * Initialization of interface; set up initialization block 1165 * and transmit/receive descriptor rings. 1166 */ 1167 int 1168 cas_init(struct ifnet *ifp) 1169 { 1170 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1171 bus_space_tag_t t = sc->sc_memt; 1172 bus_space_handle_t h = sc->sc_memh; 1173 int s; 1174 u_int max_frame_size; 1175 uint32_t v; 1176 1177 s = splnet(); 1178 1179 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1180 /* 1181 * Initialization sequence. The numbered steps below correspond 1182 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1183 * Channel Engine manual (part of the PCIO manual). 1184 * See also the STP2002-STQ document from Sun Microsystems. 1185 */ 1186 1187 /* step 1 & 2. Reset the Ethernet Channel */ 1188 cas_stop(ifp, 0); 1189 cas_reset(sc); 1190 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1191 1192 /* Re-initialize the MIF */ 1193 cas_mifinit(sc); 1194 1195 /* step 3. Setup data structures in host memory */ 1196 cas_meminit(sc); 1197 1198 /* step 4. TX MAC registers & counters */ 1199 cas_init_regs(sc); 1200 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1201 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1202 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1203 1204 /* step 5. RX MAC registers & counters */ 1205 cas_iff(sc); 1206 1207 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1208 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1209 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1210 (((uint64_t)CAS_CDTXADDR(sc, 0)) >> 32)); 1211 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1212 1213 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1214 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1215 (((uint64_t)CAS_CDRXADDR(sc, 0)) >> 32)); 1216 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1217 1218 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1219 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1220 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1221 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1222 1223 if (CAS_PLUS(sc)) { 1224 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1225 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1226 (((uint64_t)CAS_CDRXADDR2(sc, 0)) >> 32)); 1227 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1228 CAS_CDRXADDR2(sc, 0)); 1229 } 1230 1231 /* step 8. Global Configuration & Interrupt Mask */ 1232 cas_estintr(sc, CAS_INTR_REG); 1233 1234 /* step 9. ETX Configuration: use mostly default values */ 1235 1236 /* Enable DMA */ 1237 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1238 bus_space_write_4(t, h, CAS_TX_CONFIG, 1239 v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29)); 1240 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1241 1242 /* step 10. ERX Configuration */ 1243 1244 /* Encode Receive Descriptor ring size */ 1245 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1246 if (CAS_PLUS(sc)) 1247 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1248 1249 /* Encode Receive Completion ring size */ 1250 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1251 1252 /* Enable DMA */ 1253 bus_space_write_4(t, h, CAS_RX_CONFIG, 1254 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT) | CAS_RX_CONFIG_RXDMA_EN); 1255 1256 /* 1257 * The following value is for an OFF Threshold of about 3/4 full 1258 * and an ON Threshold of 1/4 full. 1259 */ 1260 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1261 (3 * sc->sc_rxfifosize / 256) | 1262 ((sc->sc_rxfifosize / 256) << 12)); 1263 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1264 1265 /* step 11. Configure Media */ 1266 mii_ifmedia_change(&sc->sc_mii); 1267 1268 /* step 12. RX_MAC Configuration Register */ 1269 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1270 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1271 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1272 1273 /* step 14. Issue Transmit Pending command */ 1274 1275 /* step 15. Give the receiver a swift kick */ 1276 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1277 if (CAS_PLUS(sc)) 1278 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1279 1280 /* Start the one second timer. */ 1281 callout_schedule(&sc->sc_tick_ch, hz); 1282 1283 ifp->if_flags |= IFF_RUNNING; 1284 ifp->if_flags &= ~IFF_OACTIVE; 1285 ifp->if_timer = 0; 1286 splx(s); 1287 1288 return (0); 1289 } 1290 1291 void 1292 cas_init_regs(struct cas_softc *sc) 1293 { 1294 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1295 bus_space_tag_t t = sc->sc_memt; 1296 bus_space_handle_t h = sc->sc_memh; 1297 const u_char *laddr = CLLADDR(ifp->if_sadl); 1298 uint32_t v, r; 1299 1300 /* These regs are not cleared on reset */ 1301 sc->sc_inited = 0; 1302 if (!sc->sc_inited) { 1303 /* Load recommended values */ 1304 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1305 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1306 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1307 1308 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1309 /* Max frame and max burst size */ 1310 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1311 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1312 1313 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1314 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1315 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1316 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1317 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1318 ((laddr[5]<<8)|laddr[4])&0x3ff); 1319 1320 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1321 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1322 bus_space_write_4(t, h, r, 0); 1323 1324 /* MAC control addr set to 0:1:c2:0:1:80 */ 1325 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1326 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1327 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1328 1329 /* MAC filter addr set to 0:0:0:0:0:0 */ 1330 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1331 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1332 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1333 1334 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1335 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1336 1337 /* Hash table initialized to 0 */ 1338 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1339 bus_space_write_4(t, h, r, 0); 1340 1341 sc->sc_inited = 1; 1342 } 1343 1344 /* Counters need to be zeroed */ 1345 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1346 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1347 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1348 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1349 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1350 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1351 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1352 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1353 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1354 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1355 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1356 1357 /* Un-pause stuff */ 1358 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1359 1360 /* 1361 * Set the station address. 1362 */ 1363 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1364 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1365 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1366 } 1367 1368 /* 1369 * Receive interrupt. 1370 */ 1371 int 1372 cas_rint(struct cas_softc *sc) 1373 { 1374 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1375 bus_space_tag_t t = sc->sc_memt; 1376 bus_space_handle_t h = sc->sc_memh; 1377 struct cas_rxsoft *rxs; 1378 struct mbuf *m; 1379 uint64_t word[4]; 1380 int len, off, idx; 1381 int i, skip; 1382 void *cp; 1383 1384 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1385 CAS_CDRXCSYNC(sc, i, 1386 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1387 1388 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1389 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1390 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1391 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1392 1393 /* Stop if the hardware still owns the descriptor. */ 1394 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1395 break; 1396 1397 len = CAS_RC1_HDR_LEN(word[1]); 1398 if (len > 0) { 1399 off = CAS_RC1_HDR_OFF(word[1]); 1400 idx = CAS_RC1_HDR_IDX(word[1]); 1401 rxs = &sc->sc_rxsoft[idx]; 1402 1403 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1404 idx, off, len)); 1405 1406 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1407 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1408 1409 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1410 m = m_devget(cp, len, 0, ifp); 1411 1412 if (word[0] & CAS_RC0_RELEASE_HDR) 1413 cas_add_rxbuf(sc, idx); 1414 1415 if (m != NULL) { 1416 1417 /* 1418 * Pass this up to any BPF listeners, but only 1419 * pass it up the stack if its for us. 1420 */ 1421 m->m_pkthdr.csum_flags = 0; 1422 if_percpuq_enqueue(ifp->if_percpuq, m); 1423 } else 1424 if_statinc(ifp, if_ierrors); 1425 } 1426 1427 len = CAS_RC0_DATA_LEN(word[0]); 1428 if (len > 0) { 1429 off = CAS_RC0_DATA_OFF(word[0]); 1430 idx = CAS_RC0_DATA_IDX(word[0]); 1431 rxs = &sc->sc_rxsoft[idx]; 1432 1433 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1434 idx, off, len)); 1435 1436 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1437 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1438 1439 /* XXX We should not be copying the packet here. */ 1440 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1441 m = m_devget(cp, len, 0, ifp); 1442 1443 if (word[0] & CAS_RC0_RELEASE_DATA) 1444 cas_add_rxbuf(sc, idx); 1445 1446 if (m != NULL) { 1447 /* 1448 * Pass this up to any BPF listeners, but only 1449 * pass it up the stack if its for us. 1450 */ 1451 m->m_pkthdr.csum_flags = 0; 1452 if_percpuq_enqueue(ifp->if_percpuq, m); 1453 } else 1454 if_statinc(ifp, if_ierrors); 1455 } 1456 1457 if (word[0] & CAS_RC0_SPLIT) 1458 aprint_error_dev(sc->sc_dev, "split packet\n"); 1459 1460 skip = CAS_RC0_SKIP(word[0]); 1461 } 1462 1463 while (sc->sc_rxptr != i) { 1464 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1465 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1466 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1467 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1468 CAS_DMA_WRITE(CAS_RC3_OWN); 1469 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1470 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1471 1472 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1473 } 1474 1475 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1476 1477 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1478 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1479 1480 return (1); 1481 } 1482 1483 /* 1484 * cas_add_rxbuf: 1485 * 1486 * Add a receive buffer to the indicated descriptor. 1487 */ 1488 int 1489 cas_add_rxbuf(struct cas_softc *sc, int idx) 1490 { 1491 bus_space_tag_t t = sc->sc_memt; 1492 bus_space_handle_t h = sc->sc_memh; 1493 1494 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1495 1496 if ((sc->sc_rxdptr % 4) == 0) 1497 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1498 1499 if (++sc->sc_rxdptr == CAS_NRXDESC) 1500 sc->sc_rxdptr = 0; 1501 1502 return (0); 1503 } 1504 1505 int 1506 cas_eint(struct cas_softc *sc, u_int status) 1507 { 1508 char bits[128]; 1509 if ((status & CAS_INTR_MIF) != 0) { 1510 DPRINTF(sc, ("%s: link status changed\n", 1511 device_xname(sc->sc_dev))); 1512 return (1); 1513 } 1514 1515 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1516 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1517 return (1); 1518 } 1519 1520 int 1521 cas_pint(struct cas_softc *sc) 1522 { 1523 bus_space_tag_t t = sc->sc_memt; 1524 bus_space_handle_t seb = sc->sc_memh; 1525 uint32_t status; 1526 1527 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1528 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1529 #ifdef CAS_DEBUG 1530 if (status) 1531 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1532 #endif 1533 return (1); 1534 } 1535 1536 int 1537 cas_intr(void *v) 1538 { 1539 struct cas_softc *sc = (struct cas_softc *)v; 1540 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1541 bus_space_tag_t t = sc->sc_memt; 1542 bus_space_handle_t seb = sc->sc_memh; 1543 uint32_t status; 1544 int r = 0; 1545 #ifdef CAS_DEBUG 1546 char bits[128]; 1547 #endif 1548 1549 sc->sc_ev_intr.ev_count++; 1550 1551 status = bus_space_read_4(t, seb, CAS_STATUS); 1552 #ifdef CAS_DEBUG 1553 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1554 #endif 1555 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1556 device_xname(sc->sc_dev), (status>>19), bits)); 1557 1558 if ((status & CAS_INTR_PCS) != 0) 1559 r |= cas_pint(sc); 1560 1561 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1562 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1563 r |= cas_eint(sc, status); 1564 1565 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1566 r |= cas_tint(sc, status); 1567 1568 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1569 r |= cas_rint(sc); 1570 1571 /* We should eventually do more than just print out error stats. */ 1572 if (status & CAS_INTR_TX_MAC) { 1573 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1574 #ifdef CAS_DEBUG 1575 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1576 printf("%s: MAC tx fault, status %x\n", 1577 device_xname(sc->sc_dev), txstat); 1578 #endif 1579 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1580 cas_init(ifp); 1581 } 1582 if (status & CAS_INTR_RX_MAC) { 1583 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1584 #ifdef CAS_DEBUG 1585 if (rxstat & ~CAS_MAC_RX_DONE) 1586 printf("%s: MAC rx fault, status %x\n", 1587 device_xname(sc->sc_dev), rxstat); 1588 #endif 1589 /* 1590 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1591 * due to a silicon bug so handle them silently. 1592 */ 1593 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1594 if_statinc(ifp, if_ierrors); 1595 cas_init(ifp); 1596 } 1597 #ifdef CAS_DEBUG 1598 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1599 printf("%s: MAC rx fault, status %x\n", 1600 device_xname(sc->sc_dev), rxstat); 1601 #endif 1602 } 1603 rnd_add_uint32(&sc->rnd_source, status); 1604 return (r); 1605 } 1606 1607 1608 void 1609 cas_watchdog(struct ifnet *ifp) 1610 { 1611 struct cas_softc *sc = ifp->if_softc; 1612 1613 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1614 "CAS_MAC_RX_CONFIG %x\n", 1615 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1616 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1617 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1618 1619 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1620 if_statinc(ifp, if_oerrors); 1621 1622 /* Try to get more packets going. */ 1623 cas_init(ifp); 1624 } 1625 1626 /* 1627 * Initialize the MII Management Interface 1628 */ 1629 void 1630 cas_mifinit(struct cas_softc *sc) 1631 { 1632 bus_space_tag_t t = sc->sc_memt; 1633 bus_space_handle_t mif = sc->sc_memh; 1634 1635 /* Configure the MIF in frame mode */ 1636 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1637 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1638 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1639 } 1640 1641 /* 1642 * MII interface 1643 * 1644 * The Cassini MII interface supports at least three different operating modes: 1645 * 1646 * Bitbang mode is implemented using data, clock and output enable registers. 1647 * 1648 * Frame mode is implemented by loading a complete frame into the frame 1649 * register and polling the valid bit for completion. 1650 * 1651 * Polling mode uses the frame register but completion is indicated by 1652 * an interrupt. 1653 * 1654 */ 1655 int 1656 cas_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1657 { 1658 struct cas_softc *sc = device_private(self); 1659 bus_space_tag_t t = sc->sc_memt; 1660 bus_space_handle_t mif = sc->sc_memh; 1661 int n; 1662 uint32_t v; 1663 1664 #ifdef CAS_DEBUG 1665 if (sc->sc_debug) 1666 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1667 #endif 1668 1669 /* Construct the frame command */ 1670 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1671 CAS_MIF_FRAME_READ; 1672 1673 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1674 for (n = 0; n < 100; n++) { 1675 DELAY(1); 1676 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1677 if (v & CAS_MIF_FRAME_TA0) { 1678 *val = v & CAS_MIF_FRAME_DATA; 1679 return 0; 1680 } 1681 } 1682 1683 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1684 return ETIMEDOUT; 1685 } 1686 1687 int 1688 cas_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1689 { 1690 struct cas_softc *sc = device_private(self); 1691 bus_space_tag_t t = sc->sc_memt; 1692 bus_space_handle_t mif = sc->sc_memh; 1693 int n; 1694 uint32_t v; 1695 1696 #ifdef CAS_DEBUG 1697 if (sc->sc_debug) 1698 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1699 phy, reg, val); 1700 #endif 1701 1702 /* Construct the frame command */ 1703 v = CAS_MIF_FRAME_WRITE | 1704 (phy << CAS_MIF_PHY_SHIFT) | 1705 (reg << CAS_MIF_REG_SHIFT) | 1706 (val & CAS_MIF_FRAME_DATA); 1707 1708 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1709 for (n = 0; n < 100; n++) { 1710 DELAY(1); 1711 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1712 if (v & CAS_MIF_FRAME_TA0) 1713 return 0; 1714 } 1715 1716 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1717 return ETIMEDOUT; 1718 } 1719 1720 void 1721 cas_mii_statchg(struct ifnet *ifp) 1722 { 1723 struct cas_softc *sc = ifp->if_softc; 1724 #ifdef CAS_DEBUG 1725 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1726 #endif 1727 bus_space_tag_t t = sc->sc_memt; 1728 bus_space_handle_t mac = sc->sc_memh; 1729 uint32_t v; 1730 1731 #ifdef CAS_DEBUG 1732 if (sc->sc_debug) 1733 printf("cas_mii_statchg: status change: phy = %d\n", 1734 sc->sc_phys[instance]); 1735 #endif 1736 1737 /* Set tx full duplex options */ 1738 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1739 delay(10000); /* reg must be cleared and delay before changing. */ 1740 v = CAS_MAC_TX_ENA_IPG0 | CAS_MAC_TX_NGU | CAS_MAC_TX_NGU_LIMIT | 1741 CAS_MAC_TX_ENABLE; 1742 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1743 v |= CAS_MAC_TX_IGN_CARRIER | CAS_MAC_TX_IGN_COLLIS; 1744 } 1745 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1746 1747 /* XIF Configuration */ 1748 v = CAS_MAC_XIF_TX_MII_ENA; 1749 v |= CAS_MAC_XIF_LINK_LED; 1750 1751 /* MII needs echo disable if half duplex. */ 1752 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1753 /* turn on full duplex LED */ 1754 v |= CAS_MAC_XIF_FDPLX_LED; 1755 else 1756 /* half duplex -- disable echo */ 1757 v |= CAS_MAC_XIF_ECHO_DISABL; 1758 1759 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1760 case IFM_1000_T: /* Gigabit using GMII interface */ 1761 case IFM_1000_SX: 1762 v |= CAS_MAC_XIF_GMII_MODE; 1763 break; 1764 default: 1765 v &= ~CAS_MAC_XIF_GMII_MODE; 1766 } 1767 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1768 } 1769 1770 int 1771 cas_pcs_readreg(device_t self, int phy, int reg, uint16_t *val) 1772 { 1773 struct cas_softc *sc = device_private(self); 1774 bus_space_tag_t t = sc->sc_memt; 1775 bus_space_handle_t pcs = sc->sc_memh; 1776 1777 #ifdef CAS_DEBUG 1778 if (sc->sc_debug) 1779 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1780 #endif 1781 1782 if (phy != CAS_PHYAD_EXTERNAL) 1783 return -1; 1784 1785 switch (reg) { 1786 case MII_BMCR: 1787 reg = CAS_MII_CONTROL; 1788 break; 1789 case MII_BMSR: 1790 reg = CAS_MII_STATUS; 1791 break; 1792 case MII_ANAR: 1793 reg = CAS_MII_ANAR; 1794 break; 1795 case MII_ANLPAR: 1796 reg = CAS_MII_ANLPAR; 1797 break; 1798 case MII_EXTSR: 1799 *val = EXTSR_1000XFDX | EXTSR_1000XHDX; 1800 return 0; 1801 default: 1802 return (0); 1803 } 1804 1805 *val = bus_space_read_4(t, pcs, reg) & 0xffff; 1806 return 0; 1807 } 1808 1809 int 1810 cas_pcs_writereg(device_t self, int phy, int reg, uint16_t val) 1811 { 1812 struct cas_softc *sc = device_private(self); 1813 bus_space_tag_t t = sc->sc_memt; 1814 bus_space_handle_t pcs = sc->sc_memh; 1815 int reset = 0; 1816 1817 #ifdef CAS_DEBUG 1818 if (sc->sc_debug) 1819 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1820 phy, reg, val); 1821 #endif 1822 1823 if (phy != CAS_PHYAD_EXTERNAL) 1824 return -1; 1825 1826 if (reg == MII_ANAR) 1827 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1828 1829 switch (reg) { 1830 case MII_BMCR: 1831 reset = (val & CAS_MII_CONTROL_RESET); 1832 reg = CAS_MII_CONTROL; 1833 break; 1834 case MII_BMSR: 1835 reg = CAS_MII_STATUS; 1836 break; 1837 case MII_ANAR: 1838 reg = CAS_MII_ANAR; 1839 break; 1840 case MII_ANLPAR: 1841 reg = CAS_MII_ANLPAR; 1842 break; 1843 default: 1844 return 0; 1845 } 1846 1847 bus_space_write_4(t, pcs, reg, val); 1848 1849 if (reset) 1850 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1851 1852 if (reg == CAS_MII_ANAR || reset) 1853 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1854 CAS_MII_CONFIG_ENABLE); 1855 1856 return 0; 1857 } 1858 1859 int 1860 cas_mediachange(struct ifnet *ifp) 1861 { 1862 struct cas_softc *sc = ifp->if_softc; 1863 struct mii_data *mii = &sc->sc_mii; 1864 1865 if (mii->mii_instance) { 1866 struct mii_softc *miisc; 1867 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1868 mii_phy_reset(miisc); 1869 } 1870 1871 return (mii_mediachg(&sc->sc_mii)); 1872 } 1873 1874 void 1875 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1876 { 1877 struct cas_softc *sc = ifp->if_softc; 1878 1879 mii_pollstat(&sc->sc_mii); 1880 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1881 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1882 } 1883 1884 /* 1885 * Process an ioctl request. 1886 */ 1887 int 1888 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1889 { 1890 struct cas_softc *sc = ifp->if_softc; 1891 int s, error = 0; 1892 1893 s = splnet(); 1894 1895 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1896 error = 0; 1897 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1898 ; 1899 else if (ifp->if_flags & IFF_RUNNING) { 1900 /* 1901 * Multicast list has changed; set the hardware filter 1902 * accordingly. 1903 */ 1904 cas_iff(sc); 1905 } 1906 } 1907 1908 splx(s); 1909 return (error); 1910 } 1911 1912 static bool 1913 cas_suspend(device_t self, const pmf_qual_t *qual) 1914 { 1915 struct cas_softc *sc = device_private(self); 1916 bus_space_tag_t t = sc->sc_memt; 1917 bus_space_handle_t h = sc->sc_memh; 1918 1919 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1920 if (sc->sc_ih != NULL) { 1921 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1922 sc->sc_ih = NULL; 1923 } 1924 1925 return true; 1926 } 1927 1928 static bool 1929 cas_resume(device_t self, const pmf_qual_t *qual) 1930 { 1931 struct cas_softc *sc = device_private(self); 1932 1933 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1934 } 1935 1936 static bool 1937 cas_estintr(struct cas_softc *sc, int what) 1938 { 1939 bus_space_tag_t t = sc->sc_memt; 1940 bus_space_handle_t h = sc->sc_memh; 1941 const char *intrstr = NULL; 1942 char intrbuf[PCI_INTRSTR_LEN]; 1943 1944 /* PCI interrupts */ 1945 if (what & CAS_INTR_PCI) { 1946 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle, intrbuf, 1947 sizeof(intrbuf)); 1948 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_handle, 1949 IPL_NET, cas_intr, sc, device_xname(sc->sc_dev)); 1950 if (sc->sc_ih == NULL) { 1951 aprint_error_dev(sc->sc_dev, 1952 "unable to establish interrupt"); 1953 if (intrstr != NULL) 1954 aprint_error(" at %s", intrstr); 1955 aprint_error("\n"); 1956 return false; 1957 } 1958 1959 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1960 } 1961 1962 /* Interrupt register */ 1963 if (what & CAS_INTR_REG) { 1964 bus_space_write_4(t, h, CAS_INTMASK, 1965 ~(CAS_INTR_TX_INTME | CAS_INTR_TX_EMPTY | 1966 CAS_INTR_TX_TAG_ERR | 1967 CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF | 1968 CAS_INTR_RX_TAG_ERR | 1969 CAS_INTR_RX_COMP_FULL | CAS_INTR_PCS | 1970 CAS_INTR_MAC_CONTROL | CAS_INTR_MIF | 1971 CAS_INTR_BERR)); 1972 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1973 CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT); 1974 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1975 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1976 } 1977 return true; 1978 } 1979 1980 bool 1981 cas_shutdown(device_t self, int howto) 1982 { 1983 struct cas_softc *sc = device_private(self); 1984 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1985 1986 cas_stop(ifp, 1); 1987 1988 return true; 1989 } 1990 1991 void 1992 cas_iff(struct cas_softc *sc) 1993 { 1994 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1995 struct ethercom *ec = &sc->sc_ethercom; 1996 struct ether_multi *enm; 1997 struct ether_multistep step; 1998 bus_space_tag_t t = sc->sc_memt; 1999 bus_space_handle_t h = sc->sc_memh; 2000 uint32_t crc, hash[16], rxcfg; 2001 int i; 2002 2003 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 2004 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 2005 CAS_MAC_RX_PROMISC_GRP); 2006 ifp->if_flags &= ~IFF_ALLMULTI; 2007 2008 if ((ifp->if_flags & IFF_PROMISC) != 0) 2009 goto update; 2010 2011 /* 2012 * Set up multicast address filter by passing all multicast 2013 * addresses through a crc generator, and then using the 2014 * high order 8 bits as an index into the 256 bit logical 2015 * address filter. The high order 4 bits selects the word, 2016 * while the other 4 bits select the bit within the word 2017 * (where bit 0 is the MSB). 2018 */ 2019 2020 /* Clear hash table */ 2021 for (i = 0; i < 16; i++) 2022 hash[i] = 0; 2023 2024 ETHER_LOCK(ec); 2025 ETHER_FIRST_MULTI(step, ec, enm); 2026 while (enm != NULL) { 2027 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2028 /* XXX Use ETHER_F_ALLMULTI in future. */ 2029 ifp->if_flags |= IFF_ALLMULTI; 2030 ETHER_UNLOCK(ec); 2031 goto update; 2032 } 2033 2034 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2035 2036 /* Just want the 8 most significant bits. */ 2037 crc >>= 24; 2038 2039 /* Set the corresponding bit in the filter. */ 2040 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2041 2042 ETHER_NEXT_MULTI(step, enm); 2043 } 2044 ETHER_UNLOCK(ec); 2045 2046 rxcfg |= CAS_MAC_RX_HASH_FILTER; 2047 2048 /* Now load the hash table into the chip (if we are using it) */ 2049 for (i = 0; i < 16; i++) { 2050 bus_space_write_4(t, h, 2051 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2052 hash[i]); 2053 } 2054 2055 update: 2056 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2057 if (ifp->if_flags & IFF_PROMISC) { 2058 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 2059 /* XXX Use ETHER_F_ALLMULTI in future. */ 2060 ifp->if_flags |= IFF_ALLMULTI; 2061 } else 2062 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 2063 } 2064 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 2065 } 2066 2067 int 2068 cas_encap(struct cas_softc *sc, struct mbuf *mhead, uint32_t *bixp) 2069 { 2070 uint64_t flags; 2071 uint32_t cur, frag, i; 2072 bus_dmamap_t map; 2073 2074 cur = frag = *bixp; 2075 map = sc->sc_txd[cur].sd_map; 2076 2077 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 2078 BUS_DMA_NOWAIT) != 0) { 2079 return (ENOBUFS); 2080 } 2081 2082 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 2083 bus_dmamap_unload(sc->sc_dmatag, map); 2084 return (ENOBUFS); 2085 } 2086 2087 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 2088 BUS_DMASYNC_PREWRITE); 2089 2090 for (i = 0; i < map->dm_nsegs; i++) { 2091 sc->sc_txdescs[frag].cd_addr = 2092 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 2093 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 2094 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 2095 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 2096 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 2097 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 2098 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 2099 BUS_DMASYNC_PREWRITE); 2100 cur = frag; 2101 if (++frag == CAS_NTXDESC) 2102 frag = 0; 2103 } 2104 2105 sc->sc_tx_cnt += map->dm_nsegs; 2106 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 2107 sc->sc_txd[cur].sd_map = map; 2108 sc->sc_txd[cur].sd_mbuf = mhead; 2109 2110 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 2111 2112 *bixp = frag; 2113 2114 /* sync descriptors */ 2115 2116 return (0); 2117 } 2118 2119 /* 2120 * Transmit interrupt. 2121 */ 2122 int 2123 cas_tint(struct cas_softc *sc, uint32_t status) 2124 { 2125 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2126 struct cas_sxd *sd; 2127 uint32_t cons, comp; 2128 2129 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2130 cons = sc->sc_tx_cons; 2131 while (cons != comp) { 2132 sd = &sc->sc_txd[cons]; 2133 if (sd->sd_mbuf != NULL) { 2134 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2135 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2136 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2137 m_freem(sd->sd_mbuf); 2138 sd->sd_mbuf = NULL; 2139 if_statinc(ifp, if_opackets); 2140 } 2141 sc->sc_tx_cnt--; 2142 if (++cons == CAS_NTXDESC) 2143 cons = 0; 2144 } 2145 sc->sc_tx_cons = cons; 2146 2147 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2148 ifp->if_flags &= ~IFF_OACTIVE; 2149 if (sc->sc_tx_cnt == 0) 2150 ifp->if_timer = 0; 2151 2152 if_schedule_deferred_start(ifp); 2153 2154 return (1); 2155 } 2156 2157 void 2158 cas_start(struct ifnet *ifp) 2159 { 2160 struct cas_softc *sc = ifp->if_softc; 2161 struct mbuf *m; 2162 uint32_t bix; 2163 2164 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2165 return; 2166 2167 bix = sc->sc_tx_prod; 2168 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2169 IFQ_POLL(&ifp->if_snd, m); 2170 if (m == NULL) 2171 break; 2172 2173 /* 2174 * If BPF is listening on this interface, let it see the 2175 * packet before we commit it to the wire. 2176 */ 2177 bpf_mtap(ifp, m, BPF_D_OUT); 2178 2179 /* 2180 * Encapsulate this packet and start it going... 2181 * or fail... 2182 */ 2183 if (cas_encap(sc, m, &bix)) { 2184 ifp->if_flags |= IFF_OACTIVE; 2185 break; 2186 } 2187 2188 IFQ_DEQUEUE(&ifp->if_snd, m); 2189 ifp->if_timer = 5; 2190 } 2191 2192 sc->sc_tx_prod = bix; 2193 } 2194 2195 MODULE(MODULE_CLASS_DRIVER, if_cas, "pci"); 2196 2197 #ifdef _MODULE 2198 #include "ioconf.c" 2199 #endif 2200 2201 static int 2202 if_cas_modcmd(modcmd_t cmd, void *opaque) 2203 { 2204 int error = 0; 2205 2206 switch (cmd) { 2207 case MODULE_CMD_INIT: 2208 #ifdef _MODULE 2209 error = config_init_component(cfdriver_ioconf_cas, 2210 cfattach_ioconf_cas, cfdata_ioconf_cas); 2211 #endif 2212 return error; 2213 case MODULE_CMD_FINI: 2214 #ifdef _MODULE 2215 error = config_fini_component(cfdriver_ioconf_cas, 2216 cfattach_ioconf_cas, cfdata_ioconf_cas); 2217 #endif 2218 return error; 2219 default: 2220 return ENOTTY; 2221 } 2222 } 2223
Indexes created Thu Oct 02 01:09:59 GMT 2025