if_cas.c revision 1.45.2.1
1 /* $NetBSD: if_cas.c,v 1.45.2.1 2021/05/31 22:15:18 cjep Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.45.2.1 2021/05/31 22:15:18 cjep Exp $"); 48 49 #ifndef _MODULE 50 #include "opt_inet.h" 51 #endif 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/module.h> 65 66 #include <machine/endian.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #include <net/bpf.h> 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 #include <sys/rndsource.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/mii_bitbang.h> 91 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcidevs.h> 95 #include <prop/proplib.h> 96 97 #include <dev/pci/if_casreg.h> 98 #include <dev/pci/if_casvar.h> 99 100 #define TRIES 10000 101 102 static bool cas_estintr(struct cas_softc *sc, int); 103 bool cas_shutdown(device_t, int); 104 static bool cas_suspend(device_t, const pmf_qual_t *); 105 static bool cas_resume(device_t, const pmf_qual_t *); 106 static int cas_detach(device_t, int); 107 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 108 109 int cas_match(device_t, cfdata_t, void *); 110 void cas_attach(device_t, device_t, void *); 111 112 113 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 114 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 115 DVF_DETACH_SHUTDOWN); 116 117 int cas_pci_readvpd(struct cas_softc *, struct pci_attach_args *, uint8_t *); 118 119 void cas_config(struct cas_softc *, const uint8_t *); 120 void cas_start(struct ifnet *); 121 void cas_stop(struct ifnet *, int); 122 int cas_ioctl(struct ifnet *, u_long, void *); 123 void cas_tick(void *); 124 void cas_watchdog(struct ifnet *); 125 int cas_init(struct ifnet *); 126 void cas_init_regs(struct cas_softc *); 127 int cas_ringsize(int); 128 int cas_cringsize(int); 129 int cas_meminit(struct cas_softc *); 130 void cas_mifinit(struct cas_softc *); 131 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 132 uint32_t, uint32_t); 133 void cas_reset(struct cas_softc *); 134 int cas_reset_rx(struct cas_softc *); 135 int cas_reset_tx(struct cas_softc *); 136 int cas_disable_rx(struct cas_softc *); 137 int cas_disable_tx(struct cas_softc *); 138 void cas_rxdrain(struct cas_softc *); 139 int cas_add_rxbuf(struct cas_softc *, int); 140 void cas_iff(struct cas_softc *); 141 int cas_encap(struct cas_softc *, struct mbuf *, uint32_t *); 142 143 /* MII methods & callbacks */ 144 int cas_mii_readreg(device_t, int, int, uint16_t*); 145 int cas_mii_writereg(device_t, int, int, uint16_t); 146 void cas_mii_statchg(struct ifnet *); 147 int cas_pcs_readreg(device_t, int, int, uint16_t *); 148 int cas_pcs_writereg(device_t, int, int, uint16_t); 149 150 int cas_mediachange(struct ifnet *); 151 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 152 153 int cas_eint(struct cas_softc *, u_int); 154 int cas_rint(struct cas_softc *); 155 int cas_tint(struct cas_softc *, uint32_t); 156 int cas_pint(struct cas_softc *); 157 int cas_intr(void *); 158 159 #ifdef CAS_DEBUG 160 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 161 printf x 162 #else 163 #define DPRINTF(sc, x) /* nothing */ 164 #endif 165 166 static const struct device_compatible_entry compat_data[] = { 167 { .id = PCI_ID_CODE(PCI_VENDOR_SUN, 168 PCI_PRODUCT_SUN_CASSINI), 169 .value = CAS_CAS }, 170 171 { .id = PCI_ID_CODE(PCI_VENDOR_NS, 172 PCI_PRODUCT_NS_SATURN), 173 .value = CAS_SATURN }, 174 175 PCI_COMPAT_EOL 176 }; 177 178 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 179 #define CAS_PHY_INTERFACE "phy-interface" 180 #define CAS_PHY_TYPE "phy-type" 181 #define CAS_PHY_TYPE_PCS "pcs" 182 183 int 184 cas_match(device_t parent, cfdata_t cf, void *aux) 185 { 186 struct pci_attach_args *pa = aux; 187 188 return pci_compatible_match(pa, compat_data); 189 } 190 191 #define PROMHDR_PTR_DATA 0x18 192 #define PROMDATA_PTR_VPD 0x08 193 #define PROMDATA_DATA2 0x0a 194 195 static const uint8_t cas_promhdr[] = { 0x55, 0xaa }; 196 static const uint8_t cas_promdat[] = { 197 'P', 'C', 'I', 'R', 198 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 199 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 200 }; 201 static const uint8_t cas_promdat_ns[] = { 202 'P', 'C', 'I', 'R', 203 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 204 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 205 }; 206 207 static const uint8_t cas_promdat2[] = { 208 0x18, 0x00, /* structure length */ 209 0x00, /* structure revision */ 210 0x00, /* interface revision */ 211 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 212 PCI_CLASS_NETWORK /* class code */ 213 }; 214 215 #define CAS_LMA_MAXNUM 4 216 int 217 cas_pci_readvpd(struct cas_softc *sc, struct pci_attach_args *pa, 218 uint8_t *enaddr) 219 { 220 struct pci_vpd_largeres *res; 221 struct pci_vpd *vpd; 222 bus_space_handle_t romh; 223 bus_space_tag_t romt; 224 bus_size_t romsize = 0; 225 uint8_t enaddrs[CAS_LMA_MAXNUM][ETHER_ADDR_LEN]; 226 bool pcs[4] = {false, false, false, false}; 227 uint8_t buf[32], *desc; 228 pcireg_t address; 229 int dataoff, vpdoff, len, lma = 0, phy = 0; 230 int i, rv = -1; 231 232 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 233 &romt, &romh, NULL, &romsize)) 234 return (-1); 235 236 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 237 address |= PCI_MAPREG_ROM_ENABLE; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 239 240 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 241 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 242 goto fail; 243 244 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 245 if (dataoff < 0x1c) 246 goto fail; 247 248 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 249 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 250 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 251 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 252 goto fail; 253 254 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 255 if (vpdoff < 0x1c) 256 goto fail; 257 258 next: 259 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 260 if (!PCI_VPDRES_ISLARGE(buf[0])) 261 goto fail; 262 263 res = (struct pci_vpd_largeres *)buf; 264 vpdoff += sizeof(*res); 265 266 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 267 switch (PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 268 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 269 /* Skip identifier string. */ 270 vpdoff += len; 271 goto next; 272 273 case PCI_VPDRES_TYPE_VPD: 274 #ifdef CAS_DEBUG 275 printf("\n"); 276 for (i = 0; i < len; i++) { 277 uint8_t byte; 278 if (i % 16 == 0) 279 printf("%04x :", i); 280 byte = bus_space_read_1(romt, romh, vpdoff + i); 281 printf(" %02x", byte); 282 if (i % 16 == 15) 283 printf("\n"); 284 } 285 printf("\n"); 286 #endif 287 288 while (len > 0) { 289 bus_space_read_region_1(romt, romh, vpdoff, 290 buf, sizeof(buf)); 291 292 vpd = (struct pci_vpd *)buf; 293 vpdoff += sizeof(*vpd) + vpd->vpd_len; 294 len -= sizeof(*vpd) + vpd->vpd_len; 295 296 /* 297 * We're looking for an "Enhanced" VPD... 298 */ 299 if (vpd->vpd_key0 != 'Z') 300 continue; 301 302 desc = buf + sizeof(*vpd); 303 304 /* 305 * ...which is an instance property... 306 */ 307 if (desc[0] != 'I') 308 continue; 309 desc += 3; 310 311 if (desc[0] == 'B' || desc[1] == ETHER_ADDR_LEN) { 312 /* 313 * ...that's a byte array with the proper 314 * length for a MAC address... 315 */ 316 desc += 2; 317 318 /* 319 * ...named "local-mac-address". 320 */ 321 if (strcmp(desc, CAS_LOCAL_MAC_ADDRESS) != 0) 322 continue; 323 desc += sizeof(CAS_LOCAL_MAC_ADDRESS); 324 325 if (lma == CAS_LMA_MAXNUM) 326 continue; 327 328 memcpy(enaddrs[lma], desc, ETHER_ADDR_LEN); 329 lma++; 330 rv = 0; 331 continue; 332 } else if (desc[0] == 'S') { 333 size_t k; 334 335 /* String */ 336 desc += 2; 337 #ifdef CAS_DEBUG 338 /* ...named "pcs". */ 339 printf("STR: \"%s\"\n", desc); 340 if (strcmp(desc, CAS_PHY_TYPE_PCS) != 0) 341 continue; 342 desc += sizeof(CAS_PHY_TYPE_PCS); 343 printf("STR: \"%s\"\n", desc); 344 #endif 345 /* ...named "phy-interface" or "phy-type". */ 346 if (strcmp(desc, CAS_PHY_INTERFACE) == 0) 347 k = sizeof(CAS_PHY_INTERFACE); 348 else if (strcmp(desc, CAS_PHY_TYPE) == 0) 349 k = sizeof(CAS_PHY_TYPE); 350 else 351 continue; 352 353 desc += k; 354 #ifdef CAS_DEBUG 355 printf("STR: \"%s\"\n", desc); 356 #endif 357 if (strcmp(desc, CAS_PHY_TYPE_PCS) == 0) 358 pcs[phy] = true; 359 phy++; 360 continue; 361 } 362 } 363 break; 364 365 default: 366 goto fail; 367 } 368 369 /* 370 * Multi port card has bridge chip. The device number is fixed: 371 * e.g. 372 * p0: 005:00:0 373 * p1: 005:01:0 374 * p2: 006:02:0 375 * p3: 006:03:0 376 */ 377 if (enaddr != 0) { 378 i = 0; 379 if ((lma > 1) && (pa->pa_device < CAS_LMA_MAXNUM) 380 && (pa->pa_device < lma)) 381 i = pa->pa_device; 382 memcpy(enaddr, enaddrs[i], ETHER_ADDR_LEN); 383 } 384 if (pcs[pa->pa_device]) 385 sc->sc_flags |= CAS_SERDES; 386 fail: 387 if (romsize != 0) 388 bus_space_unmap(romt, romh, romsize); 389 390 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 391 address &= ~PCI_MAPREG_ROM_ENABLE; 392 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 393 394 return (rv); 395 } 396 397 void 398 cas_attach(device_t parent, device_t self, void *aux) 399 { 400 struct pci_attach_args *pa = aux; 401 const struct device_compatible_entry *dce; 402 struct cas_softc *sc = device_private(self); 403 prop_data_t data; 404 uint8_t enaddr[ETHER_ADDR_LEN]; 405 406 sc->sc_dev = self; 407 pci_aprint_devinfo(pa, NULL); 408 sc->sc_rev = PCI_REVISION(pa->pa_class); 409 410 if (pci_dma64_available(pa)) 411 sc->sc_dmatag = pa->pa_dmat64; 412 else 413 sc->sc_dmatag = pa->pa_dmat; 414 415 dce = pci_compatible_lookup(pa, compat_data); 416 KASSERT(dce != NULL); 417 sc->sc_variant = (u_int)dce->value; 418 419 aprint_debug_dev(sc->sc_dev, "variant = %d\n", sc->sc_variant); 420 421 #define PCI_CAS_BASEADDR 0x10 422 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 423 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 424 aprint_error_dev(sc->sc_dev, 425 "unable to map device registers\n"); 426 return; 427 } 428 429 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 430 "mac-address")) != NULL) 431 memcpy(enaddr, prop_data_value(data), ETHER_ADDR_LEN); 432 if (cas_pci_readvpd(sc, pa, (data == NULL) ? enaddr : 0) != 0) { 433 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 434 memset(enaddr, 0, sizeof(enaddr)); 435 } 436 437 sc->sc_burst = 16; /* XXX */ 438 439 sc->sc_att_stage = CAS_ATT_BACKEND_0; 440 441 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 442 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 443 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 444 return; 445 } 446 sc->sc_pc = pa->pa_pc; 447 if (!cas_estintr(sc, CAS_INTR_PCI)) { 448 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 449 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 450 return; 451 } 452 453 sc->sc_att_stage = CAS_ATT_BACKEND_1; 454 455 /* 456 * call the main configure 457 */ 458 cas_config(sc, enaddr); 459 460 if (pmf_device_register1(sc->sc_dev, 461 cas_suspend, cas_resume, cas_shutdown)) 462 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 463 else 464 aprint_error_dev(sc->sc_dev, 465 "could not establish power handlers\n"); 466 467 sc->sc_att_stage = CAS_ATT_FINISHED; 468 /*FALLTHROUGH*/ 469 } 470 471 /* 472 * cas_config: 473 * 474 * Attach a Cassini interface to the system. 475 */ 476 void 477 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 478 { 479 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 480 struct mii_data *mii = &sc->sc_mii; 481 struct mii_softc *child; 482 uint32_t reg; 483 int i, error; 484 485 /* Make sure the chip is stopped. */ 486 ifp->if_softc = sc; 487 cas_reset(sc); 488 489 /* 490 * Allocate the control data structures, and create and load the 491 * DMA map for it. 492 */ 493 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 494 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 495 1, &sc->sc_cdnseg, 0)) != 0) { 496 aprint_error_dev(sc->sc_dev, 497 "unable to allocate control data, error = %d\n", 498 error); 499 cas_partial_detach(sc, CAS_ATT_0); 500 } 501 502 /* XXX should map this in with correct endianness */ 503 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, 504 sc->sc_cdnseg, sizeof(struct cas_control_data), 505 (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) { 506 aprint_error_dev(sc->sc_dev, 507 "unable to map control data, error = %d\n", error); 508 cas_partial_detach(sc, CAS_ATT_1); 509 } 510 511 if ((error = bus_dmamap_create(sc->sc_dmatag, 512 sizeof(struct cas_control_data), 1, 513 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 514 aprint_error_dev(sc->sc_dev, 515 "unable to create control data DMA map, error = %d\n", 516 error); 517 cas_partial_detach(sc, CAS_ATT_2); 518 } 519 520 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 521 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 522 0)) != 0) { 523 aprint_error_dev(sc->sc_dev, 524 "unable to load control data DMA map, error = %d\n", 525 error); 526 cas_partial_detach(sc, CAS_ATT_3); 527 } 528 529 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 530 531 /* 532 * Create the receive buffer DMA maps. 533 */ 534 for (i = 0; i < CAS_NRXDESC; i++) { 535 bus_dma_segment_t seg; 536 char *kva; 537 int rseg; 538 539 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 540 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 541 aprint_error_dev(sc->sc_dev, 542 "unable to alloc rx DMA mem %d, error = %d\n", 543 i, error); 544 cas_partial_detach(sc, CAS_ATT_5); 545 } 546 sc->sc_rxsoft[i].rxs_dmaseg = seg; 547 548 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 549 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 550 aprint_error_dev(sc->sc_dev, 551 "unable to alloc rx DMA mem %d, error = %d\n", 552 i, error); 553 cas_partial_detach(sc, CAS_ATT_5); 554 } 555 sc->sc_rxsoft[i].rxs_kva = kva; 556 557 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 558 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 559 aprint_error_dev(sc->sc_dev, 560 "unable to create rx DMA map %d, error = %d\n", 561 i, error); 562 cas_partial_detach(sc, CAS_ATT_5); 563 } 564 565 if ((error = bus_dmamap_load(sc->sc_dmatag, 566 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 567 BUS_DMA_NOWAIT)) != 0) { 568 aprint_error_dev(sc->sc_dev, 569 "unable to load rx DMA map %d, error = %d\n", 570 i, error); 571 cas_partial_detach(sc, CAS_ATT_5); 572 } 573 } 574 575 /* 576 * Create the transmit buffer DMA maps. 577 */ 578 for (i = 0; i < CAS_NTXDESC; i++) { 579 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 580 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 581 &sc->sc_txd[i].sd_map)) != 0) { 582 aprint_error_dev(sc->sc_dev, 583 "unable to create tx DMA map %d, error = %d\n", 584 i, error); 585 cas_partial_detach(sc, CAS_ATT_6); 586 } 587 sc->sc_txd[i].sd_mbuf = NULL; 588 } 589 590 /* 591 * From this point forward, the attachment cannot fail. A failure 592 * before this point releases all resources that may have been 593 * allocated. 594 */ 595 596 /* Announce ourselves. */ 597 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 598 ether_sprintf(enaddr)); 599 aprint_naive(": Ethernet controller\n"); 600 601 /* Get RX FIFO size */ 602 sc->sc_rxfifosize = 16 * 1024; 603 604 /* Initialize ifnet structure. */ 605 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 606 ifp->if_softc = sc; 607 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 608 ifp->if_start = cas_start; 609 ifp->if_ioctl = cas_ioctl; 610 ifp->if_watchdog = cas_watchdog; 611 ifp->if_stop = cas_stop; 612 ifp->if_init = cas_init; 613 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 614 IFQ_SET_READY(&ifp->if_snd); 615 616 /* Initialize ifmedia structures and MII info */ 617 mii->mii_ifp = ifp; 618 mii->mii_readreg = cas_mii_readreg; 619 mii->mii_writereg = cas_mii_writereg; 620 mii->mii_statchg = cas_mii_statchg; 621 622 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 623 sc->sc_ethercom.ec_mii = mii; 624 625 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 626 627 cas_mifinit(sc); 628 629 if (sc->sc_mif_config & (CAS_MIF_CONFIG_MDI1 | CAS_MIF_CONFIG_MDI0)) { 630 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 631 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 632 bus_space_write_4(sc->sc_memt, sc->sc_memh, 633 CAS_MIF_CONFIG, sc->sc_mif_config); 634 } 635 /* Enable/unfreeze the GMII pins of Saturn. */ 636 if (sc->sc_variant == CAS_SATURN) { 637 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 638 CAS_SATURN_PCFG) & ~CAS_SATURN_PCFG_FSI; 639 if ((sc->sc_mif_config & CAS_MIF_CONFIG_MDI0) != 0) 640 reg |= CAS_SATURN_PCFG_FSI; 641 bus_space_write_4(sc->sc_memt, sc->sc_memh, 642 CAS_SATURN_PCFG, reg); 643 /* Read to flush */ 644 bus_space_read_4(sc->sc_memt, sc->sc_memh, 645 CAS_SATURN_PCFG); 646 DELAY(10000); 647 } 648 } 649 650 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 651 MII_OFFSET_ANY, 0); 652 653 child = LIST_FIRST(&mii->mii_phys); 654 if (child == NULL && 655 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0 | CAS_MIF_CONFIG_MDI1)) { 656 /* 657 * Try the external PCS SERDES if we didn't find any 658 * MII devices. 659 */ 660 bus_space_write_4(sc->sc_memt, sc->sc_memh, 661 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 662 663 bus_space_write_4(sc->sc_memt, sc->sc_memh, 664 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 665 666 mii->mii_readreg = cas_pcs_readreg; 667 mii->mii_writereg = cas_pcs_writereg; 668 669 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 670 MII_OFFSET_ANY, MIIF_NOISOLATE); 671 } 672 673 child = LIST_FIRST(&mii->mii_phys); 674 if (child == NULL) { 675 /* No PHY attached */ 676 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 677 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 678 } else { 679 /* 680 * Walk along the list of attached MII devices and 681 * establish an `MII instance' to `phy number' 682 * mapping. We'll use this mapping in media change 683 * requests to determine which phy to use to program 684 * the MIF configuration register. 685 */ 686 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 687 /* 688 * Note: we support just two PHYs: the built-in 689 * internal device and an external on the MII 690 * connector. 691 */ 692 if (child->mii_phy > 1 || child->mii_inst > 1) { 693 aprint_error_dev(sc->sc_dev, 694 "cannot accommodate MII device %s" 695 " at phy %d, instance %d\n", 696 device_xname(child->mii_dev), 697 child->mii_phy, child->mii_inst); 698 continue; 699 } 700 701 sc->sc_phys[child->mii_inst] = child->mii_phy; 702 } 703 704 /* 705 * XXX - we can really do the following ONLY if the 706 * phy indeed has the auto negotiation capability!! 707 */ 708 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 709 } 710 711 /* claim 802.1q capability */ 712 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 713 714 /* Attach the interface. */ 715 if_attach(ifp); 716 if_deferred_start_init(ifp, NULL); 717 ether_ifattach(ifp, enaddr); 718 719 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 720 RND_TYPE_NET, RND_FLAG_DEFAULT); 721 722 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 723 NULL, device_xname(sc->sc_dev), "interrupts"); 724 725 callout_init(&sc->sc_tick_ch, 0); 726 callout_setfunc(&sc->sc_tick_ch, cas_tick, sc); 727 728 return; 729 } 730 731 int 732 cas_detach(device_t self, int flags) 733 { 734 int i; 735 struct cas_softc *sc = device_private(self); 736 bus_space_tag_t t = sc->sc_memt; 737 bus_space_handle_t h = sc->sc_memh; 738 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 739 740 /* 741 * Free any resources we've allocated during the failed attach 742 * attempt. Do this in reverse order and fall through. 743 */ 744 switch (sc->sc_att_stage) { 745 case CAS_ATT_FINISHED: 746 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 747 pmf_device_deregister(self); 748 cas_stop(&sc->sc_ethercom.ec_if, 1); 749 evcnt_detach(&sc->sc_ev_intr); 750 751 rnd_detach_source(&sc->rnd_source); 752 753 ether_ifdetach(ifp); 754 if_detach(ifp); 755 756 callout_destroy(&sc->sc_tick_ch); 757 758 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 759 760 ifmedia_fini(&sc->sc_mii.mii_media); 761 762 /*FALLTHROUGH*/ 763 case CAS_ATT_MII: 764 case CAS_ATT_7: 765 case CAS_ATT_6: 766 for (i = 0; i < CAS_NTXDESC; i++) { 767 if (sc->sc_txd[i].sd_map != NULL) 768 bus_dmamap_destroy(sc->sc_dmatag, 769 sc->sc_txd[i].sd_map); 770 } 771 /*FALLTHROUGH*/ 772 case CAS_ATT_5: 773 for (i = 0; i < CAS_NRXDESC; i++) { 774 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 775 bus_dmamap_unload(sc->sc_dmatag, 776 sc->sc_rxsoft[i].rxs_dmamap); 777 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 778 bus_dmamap_destroy(sc->sc_dmatag, 779 sc->sc_rxsoft[i].rxs_dmamap); 780 if (sc->sc_rxsoft[i].rxs_kva != NULL) 781 bus_dmamem_unmap(sc->sc_dmatag, 782 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 783 /* XXX need to check that bus_dmamem_alloc suceeded 784 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 785 */ 786 bus_dmamem_free(sc->sc_dmatag, 787 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 788 } 789 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 790 /*FALLTHROUGH*/ 791 case CAS_ATT_4: 792 case CAS_ATT_3: 793 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 794 /*FALLTHROUGH*/ 795 case CAS_ATT_2: 796 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 797 sizeof(struct cas_control_data)); 798 /*FALLTHROUGH*/ 799 case CAS_ATT_1: 800 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 801 /*FALLTHROUGH*/ 802 case CAS_ATT_0: 803 sc->sc_att_stage = CAS_ATT_0; 804 /*FALLTHROUGH*/ 805 case CAS_ATT_BACKEND_2: 806 case CAS_ATT_BACKEND_1: 807 if (sc->sc_ih != NULL) { 808 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 809 sc->sc_ih = NULL; 810 } 811 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 812 /*FALLTHROUGH*/ 813 case CAS_ATT_BACKEND_0: 814 break; 815 } 816 return 0; 817 } 818 819 static void 820 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 821 { 822 cfattach_t ca = device_cfattach(sc->sc_dev); 823 824 sc->sc_att_stage = stage; 825 (*ca->ca_detach)(sc->sc_dev, 0); 826 } 827 828 void 829 cas_tick(void *arg) 830 { 831 struct cas_softc *sc = arg; 832 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 833 bus_space_tag_t t = sc->sc_memt; 834 bus_space_handle_t mac = sc->sc_memh; 835 int s; 836 uint32_t v; 837 838 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 839 840 /* unload collisions counters */ 841 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 842 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 843 if_statadd_ref(nsr, if_collisions, v + 844 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 845 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT)); 846 if_statadd_ref(nsr, if_oerrors, v); 847 848 /* read error counters */ 849 if_statadd_ref(nsr, if_ierrors, 850 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 851 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 852 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 853 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL)); 854 855 IF_STAT_PUTREF(ifp); 856 857 /* clear the hardware counters */ 858 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 859 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 860 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 861 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 862 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 863 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 864 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 865 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 866 867 s = splnet(); 868 mii_tick(&sc->sc_mii); 869 splx(s); 870 871 callout_schedule(&sc->sc_tick_ch, hz); 872 } 873 874 int 875 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 876 uint32_t clr, uint32_t set) 877 { 878 int i; 879 uint32_t reg; 880 881 for (i = TRIES; i--; DELAY(100)) { 882 reg = bus_space_read_4(sc->sc_memt, h, r); 883 if ((reg & clr) == 0 && (reg & set) == set) 884 return (1); 885 } 886 887 return (0); 888 } 889 890 void 891 cas_reset(struct cas_softc *sc) 892 { 893 bus_space_tag_t t = sc->sc_memt; 894 bus_space_handle_t h = sc->sc_memh; 895 int s; 896 897 s = splnet(); 898 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 899 cas_reset_rx(sc); 900 cas_reset_tx(sc); 901 902 /* Disable interrupts */ 903 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 904 905 /* Do a full reset */ 906 bus_space_write_4(t, h, CAS_RESET, 907 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 908 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 909 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 910 splx(s); 911 } 912 913 914 /* 915 * cas_rxdrain: 916 * 917 * Drain the receive queue. 918 */ 919 void 920 cas_rxdrain(struct cas_softc *sc) 921 { 922 /* Nothing to do yet. */ 923 } 924 925 /* 926 * Reset the whole thing. 927 */ 928 void 929 cas_stop(struct ifnet *ifp, int disable) 930 { 931 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 932 struct cas_sxd *sd; 933 uint32_t i; 934 935 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 936 937 callout_stop(&sc->sc_tick_ch); 938 939 /* 940 * Mark the interface down and cancel the watchdog timer. 941 */ 942 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 943 ifp->if_timer = 0; 944 945 mii_down(&sc->sc_mii); 946 947 cas_reset_rx(sc); 948 cas_reset_tx(sc); 949 950 /* 951 * Release any queued transmit buffers. 952 */ 953 for (i = 0; i < CAS_NTXDESC; i++) { 954 sd = &sc->sc_txd[i]; 955 if (sd->sd_mbuf != NULL) { 956 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 957 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 958 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 959 m_freem(sd->sd_mbuf); 960 sd->sd_mbuf = NULL; 961 } 962 } 963 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 964 965 if (disable) 966 cas_rxdrain(sc); 967 } 968 969 970 /* 971 * Reset the receiver 972 */ 973 int 974 cas_reset_rx(struct cas_softc *sc) 975 { 976 bus_space_tag_t t = sc->sc_memt; 977 bus_space_handle_t h = sc->sc_memh; 978 979 /* 980 * Resetting while DMA is in progress can cause a bus hang, so we 981 * disable DMA first. 982 */ 983 cas_disable_rx(sc); 984 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 985 /* Wait till it finishes */ 986 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 987 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 988 /* Wait 5ms extra. */ 989 delay(5000); 990 991 /* Finally, reset the ERX */ 992 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 993 /* Wait till it finishes */ 994 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 995 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 996 return (1); 997 } 998 return (0); 999 } 1000 1001 1002 /* 1003 * Reset the transmitter 1004 */ 1005 int 1006 cas_reset_tx(struct cas_softc *sc) 1007 { 1008 bus_space_tag_t t = sc->sc_memt; 1009 bus_space_handle_t h = sc->sc_memh; 1010 1011 /* 1012 * Resetting while DMA is in progress can cause a bus hang, so we 1013 * disable DMA first. 1014 */ 1015 cas_disable_tx(sc); 1016 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 1017 /* Wait till it finishes */ 1018 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 1019 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 1020 /* Wait 5ms extra. */ 1021 delay(5000); 1022 1023 /* Finally, reset the ETX */ 1024 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 1025 /* Wait till it finishes */ 1026 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 1027 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 1028 return (1); 1029 } 1030 return (0); 1031 } 1032 1033 /* 1034 * Disable receiver. 1035 */ 1036 int 1037 cas_disable_rx(struct cas_softc *sc) 1038 { 1039 bus_space_tag_t t = sc->sc_memt; 1040 bus_space_handle_t h = sc->sc_memh; 1041 uint32_t cfg; 1042 1043 /* Flip the enable bit */ 1044 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1045 cfg &= ~CAS_MAC_RX_ENABLE; 1046 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 1047 1048 /* Wait for it to finish */ 1049 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 1050 } 1051 1052 /* 1053 * Disable transmitter. 1054 */ 1055 int 1056 cas_disable_tx(struct cas_softc *sc) 1057 { 1058 bus_space_tag_t t = sc->sc_memt; 1059 bus_space_handle_t h = sc->sc_memh; 1060 uint32_t cfg; 1061 1062 /* Flip the enable bit */ 1063 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 1064 cfg &= ~CAS_MAC_TX_ENABLE; 1065 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 1066 1067 /* Wait for it to finish */ 1068 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 1069 } 1070 1071 /* 1072 * Initialize interface. 1073 */ 1074 int 1075 cas_meminit(struct cas_softc *sc) 1076 { 1077 int i; 1078 1079 /* 1080 * Initialize the transmit descriptor ring. 1081 */ 1082 for (i = 0; i < CAS_NTXDESC; i++) { 1083 sc->sc_txdescs[i].cd_flags = 0; 1084 sc->sc_txdescs[i].cd_addr = 0; 1085 } 1086 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 1087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1088 1089 /* 1090 * Initialize the receive descriptor and receive job 1091 * descriptor rings. 1092 */ 1093 for (i = 0; i < CAS_NRXDESC; i++) 1094 CAS_INIT_RXDESC(sc, i, i); 1095 sc->sc_rxdptr = 0; 1096 sc->sc_rxptr = 0; 1097 1098 /* 1099 * Initialize the receive completion ring. 1100 */ 1101 for (i = 0; i < CAS_NRXCOMP; i++) { 1102 sc->sc_rxcomps[i].cc_word[0] = 0; 1103 sc->sc_rxcomps[i].cc_word[1] = 0; 1104 sc->sc_rxcomps[i].cc_word[2] = 0; 1105 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1106 CAS_CDRXCSYNC(sc, i, 1107 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1108 } 1109 1110 return (0); 1111 } 1112 1113 int 1114 cas_ringsize(int sz) 1115 { 1116 switch (sz) { 1117 case 32: 1118 return CAS_RING_SZ_32; 1119 case 64: 1120 return CAS_RING_SZ_64; 1121 case 128: 1122 return CAS_RING_SZ_128; 1123 case 256: 1124 return CAS_RING_SZ_256; 1125 case 512: 1126 return CAS_RING_SZ_512; 1127 case 1024: 1128 return CAS_RING_SZ_1024; 1129 case 2048: 1130 return CAS_RING_SZ_2048; 1131 case 4096: 1132 return CAS_RING_SZ_4096; 1133 case 8192: 1134 return CAS_RING_SZ_8192; 1135 default: 1136 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1137 sz); 1138 return CAS_RING_SZ_32; 1139 } 1140 } 1141 1142 int 1143 cas_cringsize(int sz) 1144 { 1145 int i; 1146 1147 for (i = 0; i < 9; i++) 1148 if (sz == (128 << i)) 1149 return i; 1150 1151 aprint_error("cas: invalid completion ring size %d\n", sz); 1152 return 128; 1153 } 1154 1155 /* 1156 * Initialization of interface; set up initialization block 1157 * and transmit/receive descriptor rings. 1158 */ 1159 int 1160 cas_init(struct ifnet *ifp) 1161 { 1162 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1163 bus_space_tag_t t = sc->sc_memt; 1164 bus_space_handle_t h = sc->sc_memh; 1165 int s; 1166 u_int max_frame_size; 1167 uint32_t v; 1168 1169 s = splnet(); 1170 1171 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1172 /* 1173 * Initialization sequence. The numbered steps below correspond 1174 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1175 * Channel Engine manual (part of the PCIO manual). 1176 * See also the STP2002-STQ document from Sun Microsystems. 1177 */ 1178 1179 /* step 1 & 2. Reset the Ethernet Channel */ 1180 cas_stop(ifp, 0); 1181 cas_reset(sc); 1182 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1183 1184 /* Re-initialize the MIF */ 1185 cas_mifinit(sc); 1186 1187 /* step 3. Setup data structures in host memory */ 1188 cas_meminit(sc); 1189 1190 /* step 4. TX MAC registers & counters */ 1191 cas_init_regs(sc); 1192 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1193 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1194 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1195 1196 /* step 5. RX MAC registers & counters */ 1197 cas_iff(sc); 1198 1199 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1200 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1201 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1202 BUS_ADDR_HI32(CAS_CDTXADDR(sc, 0))); 1203 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, 1204 BUS_ADDR_LO32(CAS_CDTXADDR(sc, 0))); 1205 1206 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1207 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1208 BUS_ADDR_HI32(CAS_CDRXADDR(sc, 0))); 1209 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, 1210 BUS_ADDR_LO32(CAS_CDRXADDR(sc, 0))); 1211 1212 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1213 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1214 BUS_ADDR_HI32(CAS_CDRXCADDR(sc, 0))); 1215 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, 1216 BUS_ADDR_LO32(CAS_CDRXCADDR(sc, 0))); 1217 1218 if (CAS_PLUS(sc)) { 1219 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1220 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1221 BUS_ADDR_HI32(CAS_CDRXADDR2(sc, 0))); 1222 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1223 BUS_ADDR_LO32(CAS_CDRXADDR2(sc, 0))); 1224 } 1225 1226 /* step 8. Global Configuration & Interrupt Mask */ 1227 cas_estintr(sc, CAS_INTR_REG); 1228 1229 /* step 9. ETX Configuration: use mostly default values */ 1230 1231 /* Enable DMA */ 1232 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1233 bus_space_write_4(t, h, CAS_TX_CONFIG, 1234 v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29)); 1235 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1236 1237 /* step 10. ERX Configuration */ 1238 1239 /* Encode Receive Descriptor ring size */ 1240 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1241 if (CAS_PLUS(sc)) 1242 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1243 1244 /* Encode Receive Completion ring size */ 1245 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1246 1247 /* Enable DMA */ 1248 bus_space_write_4(t, h, CAS_RX_CONFIG, 1249 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT) | CAS_RX_CONFIG_RXDMA_EN); 1250 1251 /* 1252 * The following value is for an OFF Threshold of about 3/4 full 1253 * and an ON Threshold of 1/4 full. 1254 */ 1255 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1256 (3 * sc->sc_rxfifosize / 256) | 1257 ((sc->sc_rxfifosize / 256) << 12)); 1258 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1259 1260 /* step 11. Configure Media */ 1261 mii_ifmedia_change(&sc->sc_mii); 1262 1263 /* step 12. RX_MAC Configuration Register */ 1264 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1265 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1266 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1267 1268 /* step 14. Issue Transmit Pending command */ 1269 1270 /* step 15. Give the receiver a swift kick */ 1271 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1272 if (CAS_PLUS(sc)) 1273 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1274 1275 /* Start the one second timer. */ 1276 callout_schedule(&sc->sc_tick_ch, hz); 1277 1278 ifp->if_flags |= IFF_RUNNING; 1279 ifp->if_flags &= ~IFF_OACTIVE; 1280 ifp->if_timer = 0; 1281 splx(s); 1282 1283 return (0); 1284 } 1285 1286 void 1287 cas_init_regs(struct cas_softc *sc) 1288 { 1289 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1290 bus_space_tag_t t = sc->sc_memt; 1291 bus_space_handle_t h = sc->sc_memh; 1292 const u_char *laddr = CLLADDR(ifp->if_sadl); 1293 uint32_t v, r; 1294 1295 /* These regs are not cleared on reset */ 1296 sc->sc_inited = 0; 1297 if (!sc->sc_inited) { 1298 /* Load recommended values */ 1299 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1300 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1301 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1302 1303 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1304 /* Max frame and max burst size */ 1305 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1306 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1307 1308 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1309 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1310 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1311 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1312 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1313 ((laddr[5]<<8)|laddr[4])&0x3ff); 1314 1315 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1316 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1317 bus_space_write_4(t, h, r, 0); 1318 1319 /* MAC control addr set to 0:1:c2:0:1:80 */ 1320 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1321 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1322 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1323 1324 /* MAC filter addr set to 0:0:0:0:0:0 */ 1325 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1326 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1327 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1328 1329 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1330 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1331 1332 /* Hash table initialized to 0 */ 1333 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1334 bus_space_write_4(t, h, r, 0); 1335 1336 sc->sc_inited = 1; 1337 } 1338 1339 /* Counters need to be zeroed */ 1340 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1341 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1342 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1343 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1344 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1345 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1346 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1347 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1348 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1349 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1350 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1351 1352 /* Un-pause stuff */ 1353 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1354 1355 /* 1356 * Set the station address. 1357 */ 1358 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1359 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1360 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1361 } 1362 1363 /* 1364 * Receive interrupt. 1365 */ 1366 int 1367 cas_rint(struct cas_softc *sc) 1368 { 1369 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1370 bus_space_tag_t t = sc->sc_memt; 1371 bus_space_handle_t h = sc->sc_memh; 1372 struct cas_rxsoft *rxs; 1373 struct mbuf *m; 1374 uint64_t word[4]; 1375 int len, off, idx; 1376 int i, skip; 1377 void *cp; 1378 1379 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1380 CAS_CDRXCSYNC(sc, i, 1381 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1382 1383 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1384 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1385 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1386 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1387 1388 /* Stop if the hardware still owns the descriptor. */ 1389 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1390 break; 1391 1392 len = CAS_RC1_HDR_LEN(word[1]); 1393 if (len > 0) { 1394 off = CAS_RC1_HDR_OFF(word[1]); 1395 idx = CAS_RC1_HDR_IDX(word[1]); 1396 rxs = &sc->sc_rxsoft[idx]; 1397 1398 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1399 idx, off, len)); 1400 1401 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1402 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1403 1404 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1405 m = m_devget(cp, len, 0, ifp); 1406 1407 if (word[0] & CAS_RC0_RELEASE_HDR) 1408 cas_add_rxbuf(sc, idx); 1409 1410 if (m != NULL) { 1411 1412 /* 1413 * Pass this up to any BPF listeners, but only 1414 * pass it up the stack if its for us. 1415 */ 1416 m->m_pkthdr.csum_flags = 0; 1417 if_percpuq_enqueue(ifp->if_percpuq, m); 1418 } else 1419 if_statinc(ifp, if_ierrors); 1420 } 1421 1422 len = CAS_RC0_DATA_LEN(word[0]); 1423 if (len > 0) { 1424 off = CAS_RC0_DATA_OFF(word[0]); 1425 idx = CAS_RC0_DATA_IDX(word[0]); 1426 rxs = &sc->sc_rxsoft[idx]; 1427 1428 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1429 idx, off, len)); 1430 1431 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1432 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1433 1434 /* XXX We should not be copying the packet here. */ 1435 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1436 m = m_devget(cp, len, 0, ifp); 1437 1438 if (word[0] & CAS_RC0_RELEASE_DATA) 1439 cas_add_rxbuf(sc, idx); 1440 1441 if (m != NULL) { 1442 /* 1443 * Pass this up to any BPF listeners, but only 1444 * pass it up the stack if its for us. 1445 */ 1446 m->m_pkthdr.csum_flags = 0; 1447 if_percpuq_enqueue(ifp->if_percpuq, m); 1448 } else 1449 if_statinc(ifp, if_ierrors); 1450 } 1451 1452 if (word[0] & CAS_RC0_SPLIT) 1453 aprint_error_dev(sc->sc_dev, "split packet\n"); 1454 1455 skip = CAS_RC0_SKIP(word[0]); 1456 } 1457 1458 while (sc->sc_rxptr != i) { 1459 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1460 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1461 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1462 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1463 CAS_DMA_WRITE(CAS_RC3_OWN); 1464 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1465 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1466 1467 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1468 } 1469 1470 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1471 1472 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1473 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1474 1475 return (1); 1476 } 1477 1478 /* 1479 * cas_add_rxbuf: 1480 * 1481 * Add a receive buffer to the indicated descriptor. 1482 */ 1483 int 1484 cas_add_rxbuf(struct cas_softc *sc, int idx) 1485 { 1486 bus_space_tag_t t = sc->sc_memt; 1487 bus_space_handle_t h = sc->sc_memh; 1488 1489 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1490 1491 if ((sc->sc_rxdptr % 4) == 0) 1492 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1493 1494 if (++sc->sc_rxdptr == CAS_NRXDESC) 1495 sc->sc_rxdptr = 0; 1496 1497 return (0); 1498 } 1499 1500 int 1501 cas_eint(struct cas_softc *sc, u_int status) 1502 { 1503 char bits[128]; 1504 if ((status & CAS_INTR_MIF) != 0) { 1505 DPRINTF(sc, ("%s: link status changed\n", 1506 device_xname(sc->sc_dev))); 1507 return (1); 1508 } 1509 1510 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1511 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1512 return (1); 1513 } 1514 1515 int 1516 cas_pint(struct cas_softc *sc) 1517 { 1518 bus_space_tag_t t = sc->sc_memt; 1519 bus_space_handle_t seb = sc->sc_memh; 1520 uint32_t status; 1521 1522 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1523 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1524 #ifdef CAS_DEBUG 1525 if (status) 1526 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1527 #endif 1528 return (1); 1529 } 1530 1531 int 1532 cas_intr(void *v) 1533 { 1534 struct cas_softc *sc = (struct cas_softc *)v; 1535 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1536 bus_space_tag_t t = sc->sc_memt; 1537 bus_space_handle_t seb = sc->sc_memh; 1538 uint32_t status; 1539 int r = 0; 1540 #ifdef CAS_DEBUG 1541 char bits[128]; 1542 #endif 1543 1544 sc->sc_ev_intr.ev_count++; 1545 1546 status = bus_space_read_4(t, seb, CAS_STATUS); 1547 #ifdef CAS_DEBUG 1548 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1549 #endif 1550 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1551 device_xname(sc->sc_dev), (status>>19), bits)); 1552 1553 if ((status & CAS_INTR_PCS) != 0) 1554 r |= cas_pint(sc); 1555 1556 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1557 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1558 r |= cas_eint(sc, status); 1559 1560 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1561 r |= cas_tint(sc, status); 1562 1563 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1564 r |= cas_rint(sc); 1565 1566 /* We should eventually do more than just print out error stats. */ 1567 if (status & CAS_INTR_TX_MAC) { 1568 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1569 #ifdef CAS_DEBUG 1570 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1571 printf("%s: MAC tx fault, status %x\n", 1572 device_xname(sc->sc_dev), txstat); 1573 #endif 1574 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1575 cas_init(ifp); 1576 } 1577 if (status & CAS_INTR_RX_MAC) { 1578 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1579 #ifdef CAS_DEBUG 1580 if (rxstat & ~CAS_MAC_RX_DONE) 1581 printf("%s: MAC rx fault, status %x\n", 1582 device_xname(sc->sc_dev), rxstat); 1583 #endif 1584 /* 1585 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1586 * due to a silicon bug so handle them silently. 1587 */ 1588 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1589 if_statinc(ifp, if_ierrors); 1590 cas_init(ifp); 1591 } 1592 #ifdef CAS_DEBUG 1593 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1594 printf("%s: MAC rx fault, status %x\n", 1595 device_xname(sc->sc_dev), rxstat); 1596 #endif 1597 } 1598 rnd_add_uint32(&sc->rnd_source, status); 1599 return (r); 1600 } 1601 1602 1603 void 1604 cas_watchdog(struct ifnet *ifp) 1605 { 1606 struct cas_softc *sc = ifp->if_softc; 1607 1608 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1609 "CAS_MAC_RX_CONFIG %x\n", 1610 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1611 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1612 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1613 1614 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1615 if_statinc(ifp, if_oerrors); 1616 1617 /* Try to get more packets going. */ 1618 cas_init(ifp); 1619 } 1620 1621 /* 1622 * Initialize the MII Management Interface 1623 */ 1624 void 1625 cas_mifinit(struct cas_softc *sc) 1626 { 1627 bus_space_tag_t t = sc->sc_memt; 1628 bus_space_handle_t mif = sc->sc_memh; 1629 1630 /* Configure the MIF in frame mode */ 1631 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1632 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1633 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1634 } 1635 1636 /* 1637 * MII interface 1638 * 1639 * The Cassini MII interface supports at least three different operating modes: 1640 * 1641 * Bitbang mode is implemented using data, clock and output enable registers. 1642 * 1643 * Frame mode is implemented by loading a complete frame into the frame 1644 * register and polling the valid bit for completion. 1645 * 1646 * Polling mode uses the frame register but completion is indicated by 1647 * an interrupt. 1648 * 1649 */ 1650 int 1651 cas_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1652 { 1653 struct cas_softc *sc = device_private(self); 1654 bus_space_tag_t t = sc->sc_memt; 1655 bus_space_handle_t mif = sc->sc_memh; 1656 int n; 1657 uint32_t v; 1658 1659 #ifdef CAS_DEBUG 1660 if (sc->sc_debug) 1661 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1662 #endif 1663 1664 /* Construct the frame command */ 1665 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1666 CAS_MIF_FRAME_READ; 1667 1668 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1669 for (n = 0; n < 100; n++) { 1670 DELAY(1); 1671 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1672 if (v & CAS_MIF_FRAME_TA0) { 1673 *val = v & CAS_MIF_FRAME_DATA; 1674 return 0; 1675 } 1676 } 1677 1678 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1679 return ETIMEDOUT; 1680 } 1681 1682 int 1683 cas_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1684 { 1685 struct cas_softc *sc = device_private(self); 1686 bus_space_tag_t t = sc->sc_memt; 1687 bus_space_handle_t mif = sc->sc_memh; 1688 int n; 1689 uint32_t v; 1690 1691 #ifdef CAS_DEBUG 1692 if (sc->sc_debug) 1693 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1694 phy, reg, val); 1695 #endif 1696 1697 /* Construct the frame command */ 1698 v = CAS_MIF_FRAME_WRITE | 1699 (phy << CAS_MIF_PHY_SHIFT) | 1700 (reg << CAS_MIF_REG_SHIFT) | 1701 (val & CAS_MIF_FRAME_DATA); 1702 1703 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1704 for (n = 0; n < 100; n++) { 1705 DELAY(1); 1706 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1707 if (v & CAS_MIF_FRAME_TA0) 1708 return 0; 1709 } 1710 1711 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1712 return ETIMEDOUT; 1713 } 1714 1715 void 1716 cas_mii_statchg(struct ifnet *ifp) 1717 { 1718 struct cas_softc *sc = ifp->if_softc; 1719 #ifdef CAS_DEBUG 1720 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1721 #endif 1722 bus_space_tag_t t = sc->sc_memt; 1723 bus_space_handle_t mac = sc->sc_memh; 1724 uint32_t v; 1725 1726 #ifdef CAS_DEBUG 1727 if (sc->sc_debug) 1728 printf("cas_mii_statchg: status change: phy = %d\n", 1729 sc->sc_phys[instance]); 1730 #endif 1731 1732 /* Set tx full duplex options */ 1733 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1734 delay(10000); /* reg must be cleared and delay before changing. */ 1735 v = CAS_MAC_TX_ENA_IPG0 | CAS_MAC_TX_NGU | CAS_MAC_TX_NGU_LIMIT | 1736 CAS_MAC_TX_ENABLE; 1737 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1738 v |= CAS_MAC_TX_IGN_CARRIER | CAS_MAC_TX_IGN_COLLIS; 1739 } 1740 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1741 1742 /* XIF Configuration */ 1743 v = CAS_MAC_XIF_TX_MII_ENA; 1744 v |= CAS_MAC_XIF_LINK_LED; 1745 1746 /* MII needs echo disable if half duplex. */ 1747 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1748 /* turn on full duplex LED */ 1749 v |= CAS_MAC_XIF_FDPLX_LED; 1750 else 1751 /* half duplex -- disable echo */ 1752 v |= CAS_MAC_XIF_ECHO_DISABL; 1753 1754 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1755 case IFM_1000_T: /* Gigabit using GMII interface */ 1756 case IFM_1000_SX: 1757 v |= CAS_MAC_XIF_GMII_MODE; 1758 break; 1759 default: 1760 v &= ~CAS_MAC_XIF_GMII_MODE; 1761 } 1762 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1763 } 1764 1765 int 1766 cas_pcs_readreg(device_t self, int phy, int reg, uint16_t *val) 1767 { 1768 struct cas_softc *sc = device_private(self); 1769 bus_space_tag_t t = sc->sc_memt; 1770 bus_space_handle_t pcs = sc->sc_memh; 1771 1772 #ifdef CAS_DEBUG 1773 if (sc->sc_debug) 1774 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1775 #endif 1776 1777 if (phy != CAS_PHYAD_EXTERNAL) 1778 return -1; 1779 1780 switch (reg) { 1781 case MII_BMCR: 1782 reg = CAS_MII_CONTROL; 1783 break; 1784 case MII_BMSR: 1785 reg = CAS_MII_STATUS; 1786 break; 1787 case MII_ANAR: 1788 reg = CAS_MII_ANAR; 1789 break; 1790 case MII_ANLPAR: 1791 reg = CAS_MII_ANLPAR; 1792 break; 1793 case MII_EXTSR: 1794 *val = EXTSR_1000XFDX | EXTSR_1000XHDX; 1795 return 0; 1796 default: 1797 return (0); 1798 } 1799 1800 *val = bus_space_read_4(t, pcs, reg) & 0xffff; 1801 return 0; 1802 } 1803 1804 int 1805 cas_pcs_writereg(device_t self, int phy, int reg, uint16_t val) 1806 { 1807 struct cas_softc *sc = device_private(self); 1808 bus_space_tag_t t = sc->sc_memt; 1809 bus_space_handle_t pcs = sc->sc_memh; 1810 int reset = 0; 1811 1812 #ifdef CAS_DEBUG 1813 if (sc->sc_debug) 1814 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1815 phy, reg, val); 1816 #endif 1817 1818 if (phy != CAS_PHYAD_EXTERNAL) 1819 return -1; 1820 1821 if (reg == MII_ANAR) 1822 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1823 1824 switch (reg) { 1825 case MII_BMCR: 1826 reset = (val & CAS_MII_CONTROL_RESET); 1827 reg = CAS_MII_CONTROL; 1828 break; 1829 case MII_BMSR: 1830 reg = CAS_MII_STATUS; 1831 break; 1832 case MII_ANAR: 1833 reg = CAS_MII_ANAR; 1834 break; 1835 case MII_ANLPAR: 1836 reg = CAS_MII_ANLPAR; 1837 break; 1838 default: 1839 return 0; 1840 } 1841 1842 bus_space_write_4(t, pcs, reg, val); 1843 1844 if (reset) 1845 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1846 1847 if (reg == CAS_MII_ANAR || reset) 1848 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1849 CAS_MII_CONFIG_ENABLE); 1850 1851 return 0; 1852 } 1853 1854 int 1855 cas_mediachange(struct ifnet *ifp) 1856 { 1857 struct cas_softc *sc = ifp->if_softc; 1858 struct mii_data *mii = &sc->sc_mii; 1859 1860 if (mii->mii_instance) { 1861 struct mii_softc *miisc; 1862 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1863 mii_phy_reset(miisc); 1864 } 1865 1866 return (mii_mediachg(&sc->sc_mii)); 1867 } 1868 1869 void 1870 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1871 { 1872 struct cas_softc *sc = ifp->if_softc; 1873 1874 mii_pollstat(&sc->sc_mii); 1875 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1876 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1877 } 1878 1879 /* 1880 * Process an ioctl request. 1881 */ 1882 int 1883 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1884 { 1885 struct cas_softc *sc = ifp->if_softc; 1886 int s, error = 0; 1887 1888 s = splnet(); 1889 1890 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1891 error = 0; 1892 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1893 ; 1894 else if (ifp->if_flags & IFF_RUNNING) { 1895 /* 1896 * Multicast list has changed; set the hardware filter 1897 * accordingly. 1898 */ 1899 cas_iff(sc); 1900 } 1901 } 1902 1903 splx(s); 1904 return (error); 1905 } 1906 1907 static bool 1908 cas_suspend(device_t self, const pmf_qual_t *qual) 1909 { 1910 struct cas_softc *sc = device_private(self); 1911 bus_space_tag_t t = sc->sc_memt; 1912 bus_space_handle_t h = sc->sc_memh; 1913 1914 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1915 if (sc->sc_ih != NULL) { 1916 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1917 sc->sc_ih = NULL; 1918 } 1919 1920 return true; 1921 } 1922 1923 static bool 1924 cas_resume(device_t self, const pmf_qual_t *qual) 1925 { 1926 struct cas_softc *sc = device_private(self); 1927 1928 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1929 } 1930 1931 static bool 1932 cas_estintr(struct cas_softc *sc, int what) 1933 { 1934 bus_space_tag_t t = sc->sc_memt; 1935 bus_space_handle_t h = sc->sc_memh; 1936 const char *intrstr = NULL; 1937 char intrbuf[PCI_INTRSTR_LEN]; 1938 1939 /* PCI interrupts */ 1940 if (what & CAS_INTR_PCI) { 1941 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle, intrbuf, 1942 sizeof(intrbuf)); 1943 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_handle, 1944 IPL_NET, cas_intr, sc, device_xname(sc->sc_dev)); 1945 if (sc->sc_ih == NULL) { 1946 aprint_error_dev(sc->sc_dev, 1947 "unable to establish interrupt"); 1948 if (intrstr != NULL) 1949 aprint_error(" at %s", intrstr); 1950 aprint_error("\n"); 1951 return false; 1952 } 1953 1954 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1955 } 1956 1957 /* Interrupt register */ 1958 if (what & CAS_INTR_REG) { 1959 bus_space_write_4(t, h, CAS_INTMASK, 1960 ~(CAS_INTR_TX_INTME | CAS_INTR_TX_EMPTY | 1961 CAS_INTR_TX_TAG_ERR | 1962 CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF | 1963 CAS_INTR_RX_TAG_ERR | 1964 CAS_INTR_RX_COMP_FULL | CAS_INTR_PCS | 1965 CAS_INTR_MAC_CONTROL | CAS_INTR_MIF | 1966 CAS_INTR_BERR)); 1967 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1968 CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT); 1969 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1970 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1971 } 1972 return true; 1973 } 1974 1975 bool 1976 cas_shutdown(device_t self, int howto) 1977 { 1978 struct cas_softc *sc = device_private(self); 1979 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1980 1981 cas_stop(ifp, 1); 1982 1983 return true; 1984 } 1985 1986 void 1987 cas_iff(struct cas_softc *sc) 1988 { 1989 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1990 struct ethercom *ec = &sc->sc_ethercom; 1991 struct ether_multi *enm; 1992 struct ether_multistep step; 1993 bus_space_tag_t t = sc->sc_memt; 1994 bus_space_handle_t h = sc->sc_memh; 1995 uint32_t crc, hash[16], rxcfg; 1996 int i; 1997 1998 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1999 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 2000 CAS_MAC_RX_PROMISC_GRP); 2001 ifp->if_flags &= ~IFF_ALLMULTI; 2002 2003 if ((ifp->if_flags & IFF_PROMISC) != 0) 2004 goto update; 2005 2006 /* 2007 * Set up multicast address filter by passing all multicast 2008 * addresses through a crc generator, and then using the 2009 * high order 8 bits as an index into the 256 bit logical 2010 * address filter. The high order 4 bits selects the word, 2011 * while the other 4 bits select the bit within the word 2012 * (where bit 0 is the MSB). 2013 */ 2014 2015 /* Clear hash table */ 2016 for (i = 0; i < 16; i++) 2017 hash[i] = 0; 2018 2019 ETHER_LOCK(ec); 2020 ETHER_FIRST_MULTI(step, ec, enm); 2021 while (enm != NULL) { 2022 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2023 /* XXX Use ETHER_F_ALLMULTI in future. */ 2024 ifp->if_flags |= IFF_ALLMULTI; 2025 ETHER_UNLOCK(ec); 2026 goto update; 2027 } 2028 2029 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2030 2031 /* Just want the 8 most significant bits. */ 2032 crc >>= 24; 2033 2034 /* Set the corresponding bit in the filter. */ 2035 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2036 2037 ETHER_NEXT_MULTI(step, enm); 2038 } 2039 ETHER_UNLOCK(ec); 2040 2041 rxcfg |= CAS_MAC_RX_HASH_FILTER; 2042 2043 /* Now load the hash table into the chip (if we are using it) */ 2044 for (i = 0; i < 16; i++) { 2045 bus_space_write_4(t, h, 2046 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2047 hash[i]); 2048 } 2049 2050 update: 2051 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2052 if (ifp->if_flags & IFF_PROMISC) { 2053 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 2054 /* XXX Use ETHER_F_ALLMULTI in future. */ 2055 ifp->if_flags |= IFF_ALLMULTI; 2056 } else 2057 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 2058 } 2059 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 2060 } 2061 2062 int 2063 cas_encap(struct cas_softc *sc, struct mbuf *mhead, uint32_t *bixp) 2064 { 2065 uint64_t flags; 2066 uint32_t cur, frag, i; 2067 bus_dmamap_t map; 2068 2069 cur = frag = *bixp; 2070 map = sc->sc_txd[cur].sd_map; 2071 2072 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 2073 BUS_DMA_NOWAIT) != 0) { 2074 return (ENOBUFS); 2075 } 2076 2077 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 2078 bus_dmamap_unload(sc->sc_dmatag, map); 2079 return (ENOBUFS); 2080 } 2081 2082 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 2083 BUS_DMASYNC_PREWRITE); 2084 2085 for (i = 0; i < map->dm_nsegs; i++) { 2086 sc->sc_txdescs[frag].cd_addr = 2087 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 2088 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 2089 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 2090 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 2091 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 2092 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 2093 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 2094 BUS_DMASYNC_PREWRITE); 2095 cur = frag; 2096 if (++frag == CAS_NTXDESC) 2097 frag = 0; 2098 } 2099 2100 sc->sc_tx_cnt += map->dm_nsegs; 2101 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 2102 sc->sc_txd[cur].sd_map = map; 2103 sc->sc_txd[cur].sd_mbuf = mhead; 2104 2105 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 2106 2107 *bixp = frag; 2108 2109 /* sync descriptors */ 2110 2111 return (0); 2112 } 2113 2114 /* 2115 * Transmit interrupt. 2116 */ 2117 int 2118 cas_tint(struct cas_softc *sc, uint32_t status) 2119 { 2120 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2121 struct cas_sxd *sd; 2122 uint32_t cons, comp; 2123 2124 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2125 cons = sc->sc_tx_cons; 2126 while (cons != comp) { 2127 sd = &sc->sc_txd[cons]; 2128 if (sd->sd_mbuf != NULL) { 2129 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2130 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2131 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2132 m_freem(sd->sd_mbuf); 2133 sd->sd_mbuf = NULL; 2134 if_statinc(ifp, if_opackets); 2135 } 2136 sc->sc_tx_cnt--; 2137 if (++cons == CAS_NTXDESC) 2138 cons = 0; 2139 } 2140 sc->sc_tx_cons = cons; 2141 2142 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2143 ifp->if_flags &= ~IFF_OACTIVE; 2144 if (sc->sc_tx_cnt == 0) 2145 ifp->if_timer = 0; 2146 2147 if_schedule_deferred_start(ifp); 2148 2149 return (1); 2150 } 2151 2152 void 2153 cas_start(struct ifnet *ifp) 2154 { 2155 struct cas_softc *sc = ifp->if_softc; 2156 struct mbuf *m; 2157 uint32_t bix; 2158 2159 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2160 return; 2161 2162 bix = sc->sc_tx_prod; 2163 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2164 IFQ_POLL(&ifp->if_snd, m); 2165 if (m == NULL) 2166 break; 2167 2168 /* 2169 * If BPF is listening on this interface, let it see the 2170 * packet before we commit it to the wire. 2171 */ 2172 bpf_mtap(ifp, m, BPF_D_OUT); 2173 2174 /* 2175 * Encapsulate this packet and start it going... 2176 * or fail... 2177 */ 2178 if (cas_encap(sc, m, &bix)) { 2179 ifp->if_flags |= IFF_OACTIVE; 2180 break; 2181 } 2182 2183 IFQ_DEQUEUE(&ifp->if_snd, m); 2184 ifp->if_timer = 5; 2185 } 2186 2187 sc->sc_tx_prod = bix; 2188 } 2189 2190 MODULE(MODULE_CLASS_DRIVER, if_cas, "pci"); 2191 2192 #ifdef _MODULE 2193 #include "ioconf.c" 2194 #endif 2195 2196 static int 2197 if_cas_modcmd(modcmd_t cmd, void *opaque) 2198 { 2199 int error = 0; 2200 2201 switch (cmd) { 2202 case MODULE_CMD_INIT: 2203 #ifdef _MODULE 2204 error = config_init_component(cfdriver_ioconf_cas, 2205 cfattach_ioconf_cas, cfdata_ioconf_cas); 2206 #endif 2207 return error; 2208 case MODULE_CMD_FINI: 2209 #ifdef _MODULE 2210 error = config_fini_component(cfdriver_ioconf_cas, 2211 cfattach_ioconf_cas, cfdata_ioconf_cas); 2212 #endif 2213 return error; 2214 default: 2215 return ENOTTY; 2216 } 2217 } 2218
Indexes created Thu Oct 02 01:09:59 GMT 2025