if_cas.c revision 1.7.2.2
1 /* $NetBSD: if_cas.c,v 1.7.2.2 2010/03/11 15:03:45 yamt Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.7.2.2 2010/03/11 15:03:45 yamt Exp $"); 48 49 #include "opt_inet.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/syslog.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/socket.h> 59 #include <sys/ioctl.h> 60 #include <sys/errno.h> 61 #include <sys/device.h> 62 63 #include <machine/endian.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/in_systm.h> 75 #include <netinet/in_var.h> 76 #include <netinet/ip.h> 77 #include <netinet/tcp.h> 78 #include <netinet/udp.h> 79 #endif 80 81 #include <net/bpf.h> 82 83 #include <sys/bus.h> 84 #include <sys/intr.h> 85 86 #include <dev/mii/mii.h> 87 #include <dev/mii/miivar.h> 88 #include <dev/mii/mii_bitbang.h> 89 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcidevs.h> 93 #include <prop/proplib.h> 94 95 #include <dev/pci/if_casreg.h> 96 #include <dev/pci/if_casvar.h> 97 98 #define TRIES 10000 99 100 static bool cas_estintr(struct cas_softc *sc, int); 101 bool cas_shutdown(device_t, int); 102 static bool cas_suspend(device_t, const pmf_qual_t *); 103 static bool cas_resume(device_t, const pmf_qual_t *); 104 static int cas_detach(device_t, int); 105 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 106 107 int cas_match(device_t, cfdata_t, void *); 108 void cas_attach(device_t, device_t, void *); 109 110 111 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 112 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 113 DVF_DETACH_SHUTDOWN); 114 115 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 116 117 void cas_config(struct cas_softc *, const uint8_t *); 118 void cas_start(struct ifnet *); 119 void cas_stop(struct ifnet *, int); 120 int cas_ioctl(struct ifnet *, u_long, void *); 121 void cas_tick(void *); 122 void cas_watchdog(struct ifnet *); 123 int cas_init(struct ifnet *); 124 void cas_init_regs(struct cas_softc *); 125 int cas_ringsize(int); 126 int cas_cringsize(int); 127 int cas_meminit(struct cas_softc *); 128 void cas_mifinit(struct cas_softc *); 129 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 130 u_int32_t, u_int32_t); 131 void cas_reset(struct cas_softc *); 132 int cas_reset_rx(struct cas_softc *); 133 int cas_reset_tx(struct cas_softc *); 134 int cas_disable_rx(struct cas_softc *); 135 int cas_disable_tx(struct cas_softc *); 136 void cas_rxdrain(struct cas_softc *); 137 int cas_add_rxbuf(struct cas_softc *, int idx); 138 void cas_iff(struct cas_softc *); 139 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 140 141 /* MII methods & callbacks */ 142 int cas_mii_readreg(device_t, int, int); 143 void cas_mii_writereg(device_t, int, int, int); 144 void cas_mii_statchg(device_t); 145 int cas_pcs_readreg(device_t, int, int); 146 void cas_pcs_writereg(device_t, int, int, int); 147 148 int cas_mediachange(struct ifnet *); 149 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 150 151 int cas_eint(struct cas_softc *, u_int); 152 int cas_rint(struct cas_softc *); 153 int cas_tint(struct cas_softc *, u_int32_t); 154 int cas_pint(struct cas_softc *); 155 int cas_intr(void *); 156 157 #ifdef CAS_DEBUG 158 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 159 printf x 160 #else 161 #define DPRINTF(sc, x) /* nothing */ 162 #endif 163 164 int 165 cas_match(device_t parent, cfdata_t cf, void *aux) 166 { 167 struct pci_attach_args *pa = aux; 168 169 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 170 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 171 return 1; 172 173 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 174 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 175 return 1; 176 177 return 0; 178 } 179 180 #define PROMHDR_PTR_DATA 0x18 181 #define PROMDATA_PTR_VPD 0x08 182 #define PROMDATA_DATA2 0x0a 183 184 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 185 static const u_int8_t cas_promdat[] = { 186 'P', 'C', 'I', 'R', 187 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 188 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 189 }; 190 191 static const u_int8_t cas_promdat2[] = { 192 0x18, 0x00, /* structure length */ 193 0x00, /* structure revision */ 194 0x00, /* interface revision */ 195 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 196 PCI_CLASS_NETWORK /* class code */ 197 }; 198 199 int 200 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 201 uint8_t *enaddr) 202 { 203 struct pci_vpd_largeres *res; 204 struct pci_vpd *vpd; 205 bus_space_handle_t romh; 206 bus_space_tag_t romt; 207 bus_size_t romsize = 0; 208 u_int8_t buf[32], *desc; 209 pcireg_t address; 210 int dataoff, vpdoff, len; 211 int rv = -1; 212 213 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 214 &romt, &romh, NULL, &romsize)) 215 return (-1); 216 217 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 218 address |= PCI_MAPREG_ROM_ENABLE; 219 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 220 221 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 222 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 223 goto fail; 224 225 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 226 if (dataoff < 0x1c) 227 goto fail; 228 229 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 230 if (bcmp(buf, cas_promdat, sizeof(cas_promdat)) || 231 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 232 goto fail; 233 234 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 235 if (vpdoff < 0x1c) 236 goto fail; 237 238 next: 239 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 240 if (!PCI_VPDRES_ISLARGE(buf[0])) 241 goto fail; 242 243 res = (struct pci_vpd_largeres *)buf; 244 vpdoff += sizeof(*res); 245 246 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 247 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 248 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 249 /* Skip identifier string. */ 250 vpdoff += len; 251 goto next; 252 253 case PCI_VPDRES_TYPE_VPD: 254 while (len > 0) { 255 bus_space_read_region_1(romt, romh, vpdoff, 256 buf, sizeof(buf)); 257 258 vpd = (struct pci_vpd *)buf; 259 vpdoff += sizeof(*vpd) + vpd->vpd_len; 260 len -= sizeof(*vpd) + vpd->vpd_len; 261 262 /* 263 * We're looking for an "Enhanced" VPD... 264 */ 265 if (vpd->vpd_key0 != 'Z') 266 continue; 267 268 desc = buf + sizeof(*vpd); 269 270 /* 271 * ...which is an instance property... 272 */ 273 if (desc[0] != 'I') 274 continue; 275 desc += 3; 276 277 /* 278 * ...that's a byte array with the proper 279 * length for a MAC address... 280 */ 281 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 282 continue; 283 desc += 2; 284 285 /* 286 * ...named "local-mac-address". 287 */ 288 if (strcmp(desc, "local-mac-address") != 0) 289 continue; 290 desc += strlen("local-mac-address") + 1; 291 292 memcpy(enaddr, desc, ETHER_ADDR_LEN); 293 rv = 0; 294 } 295 break; 296 297 default: 298 goto fail; 299 } 300 301 fail: 302 if (romsize != 0) 303 bus_space_unmap(romt, romh, romsize); 304 305 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 306 address &= ~PCI_MAPREG_ROM_ENABLE; 307 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 308 309 return (rv); 310 } 311 312 void 313 cas_attach(device_t parent, device_t self, void *aux) 314 { 315 struct pci_attach_args *pa = aux; 316 struct cas_softc *sc = device_private(self); 317 char devinfo[256]; 318 prop_data_t data; 319 uint8_t enaddr[ETHER_ADDR_LEN]; 320 321 sc->sc_dev = self; 322 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 323 sc->sc_rev = PCI_REVISION(pa->pa_class); 324 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, sc->sc_rev); 325 sc->sc_dmatag = pa->pa_dmat; 326 327 #define PCI_CAS_BASEADDR 0x10 328 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 329 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 330 aprint_error_dev(sc->sc_dev, 331 "unable to map device registers\n"); 332 return; 333 } 334 335 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 336 "mac-address")) != NULL) 337 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 338 else if (cas_pci_enaddr(sc, pa, enaddr) != 0) 339 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 340 341 sc->sc_burst = 16; /* XXX */ 342 343 sc->sc_att_stage = CAS_ATT_BACKEND_0; 344 345 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 346 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 347 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 348 return; 349 } 350 sc->sc_pc = pa->pa_pc; 351 if (!cas_estintr(sc, CAS_INTR_PCI)) { 352 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 353 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 354 return; 355 } 356 357 sc->sc_att_stage = CAS_ATT_BACKEND_1; 358 359 /* 360 * call the main configure 361 */ 362 cas_config(sc, enaddr); 363 364 if (pmf_device_register1(sc->sc_dev, 365 cas_suspend, cas_resume, cas_shutdown)) 366 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 367 else 368 aprint_error_dev(sc->sc_dev, 369 "could not establish power handlers\n"); 370 371 sc->sc_att_stage = CAS_ATT_FINISHED; 372 /*FALLTHROUGH*/ 373 } 374 375 /* 376 * cas_config: 377 * 378 * Attach a Cassini interface to the system. 379 */ 380 void 381 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 382 { 383 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 384 struct mii_data *mii = &sc->sc_mii; 385 struct mii_softc *child; 386 int i, error; 387 388 /* Make sure the chip is stopped. */ 389 ifp->if_softc = sc; 390 cas_reset(sc); 391 392 /* 393 * Allocate the control data structures, and create and load the 394 * DMA map for it. 395 */ 396 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 397 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 398 1, &sc->sc_cdnseg, 0)) != 0) { 399 aprint_error_dev(sc->sc_dev, 400 "unable to allocate control data, error = %d\n", 401 error); 402 cas_partial_detach(sc, CAS_ATT_0); 403 } 404 405 /* XXX should map this in with correct endianness */ 406 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 407 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 408 BUS_DMA_COHERENT)) != 0) { 409 aprint_error_dev(sc->sc_dev, 410 "unable to map control data, error = %d\n", error); 411 cas_partial_detach(sc, CAS_ATT_1); 412 } 413 414 if ((error = bus_dmamap_create(sc->sc_dmatag, 415 sizeof(struct cas_control_data), 1, 416 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 417 aprint_error_dev(sc->sc_dev, 418 "unable to create control data DMA map, error = %d\n", error); 419 cas_partial_detach(sc, CAS_ATT_2); 420 } 421 422 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 423 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 424 0)) != 0) { 425 aprint_error_dev(sc->sc_dev, 426 "unable to load control data DMA map, error = %d\n", 427 error); 428 cas_partial_detach(sc, CAS_ATT_3); 429 } 430 431 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 432 433 /* 434 * Create the receive buffer DMA maps. 435 */ 436 for (i = 0; i < CAS_NRXDESC; i++) { 437 bus_dma_segment_t seg; 438 char *kva; 439 int rseg; 440 441 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 442 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 443 aprint_error_dev(sc->sc_dev, 444 "unable to alloc rx DMA mem %d, error = %d\n", 445 i, error); 446 cas_partial_detach(sc, CAS_ATT_5); 447 } 448 sc->sc_rxsoft[i].rxs_dmaseg = seg; 449 450 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 451 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 452 aprint_error_dev(sc->sc_dev, 453 "unable to alloc rx DMA mem %d, error = %d\n", 454 i, error); 455 cas_partial_detach(sc, CAS_ATT_5); 456 } 457 sc->sc_rxsoft[i].rxs_kva = kva; 458 459 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 460 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 461 aprint_error_dev(sc->sc_dev, 462 "unable to create rx DMA map %d, error = %d\n", 463 i, error); 464 cas_partial_detach(sc, CAS_ATT_5); 465 } 466 467 if ((error = bus_dmamap_load(sc->sc_dmatag, 468 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 469 BUS_DMA_NOWAIT)) != 0) { 470 aprint_error_dev(sc->sc_dev, 471 "unable to load rx DMA map %d, error = %d\n", 472 i, error); 473 cas_partial_detach(sc, CAS_ATT_5); 474 } 475 } 476 477 /* 478 * Create the transmit buffer DMA maps. 479 */ 480 for (i = 0; i < CAS_NTXDESC; i++) { 481 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 482 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 483 &sc->sc_txd[i].sd_map)) != 0) { 484 aprint_error_dev(sc->sc_dev, 485 "unable to create tx DMA map %d, error = %d\n", 486 i, error); 487 cas_partial_detach(sc, CAS_ATT_6); 488 } 489 sc->sc_txd[i].sd_mbuf = NULL; 490 } 491 492 /* 493 * From this point forward, the attachment cannot fail. A failure 494 * before this point releases all resources that may have been 495 * allocated. 496 */ 497 498 /* Announce ourselves. */ 499 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 500 ether_sprintf(enaddr)); 501 502 /* Get RX FIFO size */ 503 sc->sc_rxfifosize = 16 * 1024; 504 505 /* Initialize ifnet structure. */ 506 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 507 ifp->if_softc = sc; 508 ifp->if_flags = 509 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 510 ifp->if_start = cas_start; 511 ifp->if_ioctl = cas_ioctl; 512 ifp->if_watchdog = cas_watchdog; 513 ifp->if_stop = cas_stop; 514 ifp->if_init = cas_init; 515 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 516 IFQ_SET_READY(&ifp->if_snd); 517 518 /* Initialize ifmedia structures and MII info */ 519 mii->mii_ifp = ifp; 520 mii->mii_readreg = cas_mii_readreg; 521 mii->mii_writereg = cas_mii_writereg; 522 mii->mii_statchg = cas_mii_statchg; 523 524 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 525 sc->sc_ethercom.ec_mii = mii; 526 527 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 528 529 cas_mifinit(sc); 530 531 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 532 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 533 bus_space_write_4(sc->sc_memt, sc->sc_memh, 534 CAS_MIF_CONFIG, sc->sc_mif_config); 535 } 536 537 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 538 MII_OFFSET_ANY, 0); 539 540 child = LIST_FIRST(&mii->mii_phys); 541 if (child == NULL && 542 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 543 /* 544 * Try the external PCS SERDES if we didn't find any 545 * MII devices. 546 */ 547 bus_space_write_4(sc->sc_memt, sc->sc_memh, 548 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 549 550 bus_space_write_4(sc->sc_memt, sc->sc_memh, 551 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 552 553 mii->mii_readreg = cas_pcs_readreg; 554 mii->mii_writereg = cas_pcs_writereg; 555 556 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 557 MII_OFFSET_ANY, MIIF_NOISOLATE); 558 } 559 560 child = LIST_FIRST(&mii->mii_phys); 561 if (child == NULL) { 562 /* No PHY attached */ 563 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 564 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 565 } else { 566 /* 567 * Walk along the list of attached MII devices and 568 * establish an `MII instance' to `phy number' 569 * mapping. We'll use this mapping in media change 570 * requests to determine which phy to use to program 571 * the MIF configuration register. 572 */ 573 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 574 /* 575 * Note: we support just two PHYs: the built-in 576 * internal device and an external on the MII 577 * connector. 578 */ 579 if (child->mii_phy > 1 || child->mii_inst > 1) { 580 aprint_error_dev(sc->sc_dev, 581 "cannot accommodate MII device %s" 582 " at phy %d, instance %d\n", 583 device_xname(child->mii_dev), 584 child->mii_phy, child->mii_inst); 585 continue; 586 } 587 588 sc->sc_phys[child->mii_inst] = child->mii_phy; 589 } 590 591 /* 592 * XXX - we can really do the following ONLY if the 593 * phy indeed has the auto negotiation capability!! 594 */ 595 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 596 } 597 598 /* claim 802.1q capability */ 599 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 600 601 /* Attach the interface. */ 602 if_attach(ifp); 603 ether_ifattach(ifp, enaddr); 604 605 #if NRND > 0 606 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 607 RND_TYPE_NET, 0); 608 #endif 609 610 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 611 NULL, device_xname(sc->sc_dev), "interrupts"); 612 613 callout_init(&sc->sc_tick_ch, 0); 614 615 return; 616 } 617 618 int 619 cas_detach(device_t self, int flags) 620 { 621 int i; 622 struct cas_softc *sc = device_private(self); 623 bus_space_tag_t t = sc->sc_memt; 624 bus_space_handle_t h = sc->sc_memh; 625 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 626 627 /* 628 * Free any resources we've allocated during the failed attach 629 * attempt. Do this in reverse order and fall through. 630 */ 631 switch (sc->sc_att_stage) { 632 case CAS_ATT_FINISHED: 633 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 634 pmf_device_deregister(self); 635 cas_stop(&sc->sc_ethercom.ec_if, 1); 636 evcnt_detach(&sc->sc_ev_intr); 637 638 #if NRND > 0 639 rnd_detach_source(&sc->rnd_source); 640 #endif 641 642 ether_ifdetach(ifp); 643 if_detach(ifp); 644 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 645 646 callout_destroy(&sc->sc_tick_ch); 647 648 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 649 650 /*FALLTHROUGH*/ 651 case CAS_ATT_MII: 652 case CAS_ATT_7: 653 case CAS_ATT_6: 654 for (i = 0; i < CAS_NTXDESC; i++) { 655 if (sc->sc_txd[i].sd_map != NULL) 656 bus_dmamap_destroy(sc->sc_dmatag, 657 sc->sc_txd[i].sd_map); 658 } 659 /*FALLTHROUGH*/ 660 case CAS_ATT_5: 661 for (i = 0; i < CAS_NRXDESC; i++) { 662 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 663 bus_dmamap_unload(sc->sc_dmatag, 664 sc->sc_rxsoft[i].rxs_dmamap); 665 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 666 bus_dmamap_destroy(sc->sc_dmatag, 667 sc->sc_rxsoft[i].rxs_dmamap); 668 if (sc->sc_rxsoft[i].rxs_kva != NULL) 669 bus_dmamem_unmap(sc->sc_dmatag, 670 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 671 /* XXX need to check that bus_dmamem_alloc suceeded 672 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 673 */ 674 bus_dmamem_free(sc->sc_dmatag, 675 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 676 } 677 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 678 /*FALLTHROUGH*/ 679 case CAS_ATT_4: 680 case CAS_ATT_3: 681 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 682 /*FALLTHROUGH*/ 683 case CAS_ATT_2: 684 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 685 sizeof(struct cas_control_data)); 686 /*FALLTHROUGH*/ 687 case CAS_ATT_1: 688 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 689 /*FALLTHROUGH*/ 690 case CAS_ATT_0: 691 sc->sc_att_stage = CAS_ATT_0; 692 /*FALLTHROUGH*/ 693 case CAS_ATT_BACKEND_2: 694 case CAS_ATT_BACKEND_1: 695 if (sc->sc_ih != NULL) { 696 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 697 sc->sc_ih = NULL; 698 } 699 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 700 /*FALLTHROUGH*/ 701 case CAS_ATT_BACKEND_0: 702 break; 703 } 704 return 0; 705 } 706 707 static void 708 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 709 { 710 cfattach_t ca = device_cfattach(sc->sc_dev); 711 712 sc->sc_att_stage = stage; 713 (*ca->ca_detach)(sc->sc_dev, 0); 714 } 715 716 void 717 cas_tick(void *arg) 718 { 719 struct cas_softc *sc = arg; 720 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 721 bus_space_tag_t t = sc->sc_memt; 722 bus_space_handle_t mac = sc->sc_memh; 723 int s; 724 u_int32_t v; 725 726 /* unload collisions counters */ 727 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 728 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 729 ifp->if_collisions += v + 730 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 731 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 732 ifp->if_oerrors += v; 733 734 /* read error counters */ 735 ifp->if_ierrors += 736 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 737 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 738 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 739 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 740 741 /* clear the hardware counters */ 742 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 743 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 744 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 745 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 746 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 747 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 748 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 749 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 750 751 s = splnet(); 752 mii_tick(&sc->sc_mii); 753 splx(s); 754 755 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 756 } 757 758 int 759 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 760 u_int32_t clr, u_int32_t set) 761 { 762 int i; 763 u_int32_t reg; 764 765 for (i = TRIES; i--; DELAY(100)) { 766 reg = bus_space_read_4(sc->sc_memt, h, r); 767 if ((reg & clr) == 0 && (reg & set) == set) 768 return (1); 769 } 770 771 return (0); 772 } 773 774 void 775 cas_reset(struct cas_softc *sc) 776 { 777 bus_space_tag_t t = sc->sc_memt; 778 bus_space_handle_t h = sc->sc_memh; 779 int s; 780 781 s = splnet(); 782 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 783 cas_reset_rx(sc); 784 cas_reset_tx(sc); 785 786 /* Do a full reset */ 787 bus_space_write_4(t, h, CAS_RESET, 788 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 789 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 790 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 791 splx(s); 792 } 793 794 795 /* 796 * cas_rxdrain: 797 * 798 * Drain the receive queue. 799 */ 800 void 801 cas_rxdrain(struct cas_softc *sc) 802 { 803 /* Nothing to do yet. */ 804 } 805 806 /* 807 * Reset the whole thing. 808 */ 809 void 810 cas_stop(struct ifnet *ifp, int disable) 811 { 812 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 813 struct cas_sxd *sd; 814 u_int32_t i; 815 816 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 817 818 callout_stop(&sc->sc_tick_ch); 819 820 /* 821 * Mark the interface down and cancel the watchdog timer. 822 */ 823 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 824 ifp->if_timer = 0; 825 826 mii_down(&sc->sc_mii); 827 828 cas_reset_rx(sc); 829 cas_reset_tx(sc); 830 831 /* 832 * Release any queued transmit buffers. 833 */ 834 for (i = 0; i < CAS_NTXDESC; i++) { 835 sd = &sc->sc_txd[i]; 836 if (sd->sd_mbuf != NULL) { 837 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 838 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 839 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 840 m_freem(sd->sd_mbuf); 841 sd->sd_mbuf = NULL; 842 } 843 } 844 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 845 846 if (disable) 847 cas_rxdrain(sc); 848 } 849 850 851 /* 852 * Reset the receiver 853 */ 854 int 855 cas_reset_rx(struct cas_softc *sc) 856 { 857 bus_space_tag_t t = sc->sc_memt; 858 bus_space_handle_t h = sc->sc_memh; 859 860 /* 861 * Resetting while DMA is in progress can cause a bus hang, so we 862 * disable DMA first. 863 */ 864 cas_disable_rx(sc); 865 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 866 /* Wait till it finishes */ 867 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 868 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 869 /* Wait 5ms extra. */ 870 delay(5000); 871 872 /* Finally, reset the ERX */ 873 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 874 /* Wait till it finishes */ 875 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 876 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 877 return (1); 878 } 879 return (0); 880 } 881 882 883 /* 884 * Reset the transmitter 885 */ 886 int 887 cas_reset_tx(struct cas_softc *sc) 888 { 889 bus_space_tag_t t = sc->sc_memt; 890 bus_space_handle_t h = sc->sc_memh; 891 892 /* 893 * Resetting while DMA is in progress can cause a bus hang, so we 894 * disable DMA first. 895 */ 896 cas_disable_tx(sc); 897 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 898 /* Wait till it finishes */ 899 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 900 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 901 /* Wait 5ms extra. */ 902 delay(5000); 903 904 /* Finally, reset the ETX */ 905 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 906 /* Wait till it finishes */ 907 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 908 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 909 return (1); 910 } 911 return (0); 912 } 913 914 /* 915 * Disable receiver. 916 */ 917 int 918 cas_disable_rx(struct cas_softc *sc) 919 { 920 bus_space_tag_t t = sc->sc_memt; 921 bus_space_handle_t h = sc->sc_memh; 922 u_int32_t cfg; 923 924 /* Flip the enable bit */ 925 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 926 cfg &= ~CAS_MAC_RX_ENABLE; 927 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 928 929 /* Wait for it to finish */ 930 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 931 } 932 933 /* 934 * Disable transmitter. 935 */ 936 int 937 cas_disable_tx(struct cas_softc *sc) 938 { 939 bus_space_tag_t t = sc->sc_memt; 940 bus_space_handle_t h = sc->sc_memh; 941 u_int32_t cfg; 942 943 /* Flip the enable bit */ 944 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 945 cfg &= ~CAS_MAC_TX_ENABLE; 946 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 947 948 /* Wait for it to finish */ 949 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 950 } 951 952 /* 953 * Initialize interface. 954 */ 955 int 956 cas_meminit(struct cas_softc *sc) 957 { 958 struct cas_rxsoft *rxs; 959 int i, error; 960 961 rxs = (void *)&error; 962 963 /* 964 * Initialize the transmit descriptor ring. 965 */ 966 for (i = 0; i < CAS_NTXDESC; i++) { 967 sc->sc_txdescs[i].cd_flags = 0; 968 sc->sc_txdescs[i].cd_addr = 0; 969 } 970 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 971 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 972 973 /* 974 * Initialize the receive descriptor and receive job 975 * descriptor rings. 976 */ 977 for (i = 0; i < CAS_NRXDESC; i++) 978 CAS_INIT_RXDESC(sc, i, i); 979 sc->sc_rxdptr = 0; 980 sc->sc_rxptr = 0; 981 982 /* 983 * Initialize the receive completion ring. 984 */ 985 for (i = 0; i < CAS_NRXCOMP; i++) { 986 sc->sc_rxcomps[i].cc_word[0] = 0; 987 sc->sc_rxcomps[i].cc_word[1] = 0; 988 sc->sc_rxcomps[i].cc_word[2] = 0; 989 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 990 CAS_CDRXCSYNC(sc, i, 991 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 992 } 993 994 return (0); 995 } 996 997 int 998 cas_ringsize(int sz) 999 { 1000 switch (sz) { 1001 case 32: 1002 return CAS_RING_SZ_32; 1003 case 64: 1004 return CAS_RING_SZ_64; 1005 case 128: 1006 return CAS_RING_SZ_128; 1007 case 256: 1008 return CAS_RING_SZ_256; 1009 case 512: 1010 return CAS_RING_SZ_512; 1011 case 1024: 1012 return CAS_RING_SZ_1024; 1013 case 2048: 1014 return CAS_RING_SZ_2048; 1015 case 4096: 1016 return CAS_RING_SZ_4096; 1017 case 8192: 1018 return CAS_RING_SZ_8192; 1019 default: 1020 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1021 sz); 1022 return CAS_RING_SZ_32; 1023 } 1024 } 1025 1026 int 1027 cas_cringsize(int sz) 1028 { 1029 int i; 1030 1031 for (i = 0; i < 9; i++) 1032 if (sz == (128 << i)) 1033 return i; 1034 1035 aprint_error("cas: invalid completion ring size %d\n", sz); 1036 return 128; 1037 } 1038 1039 /* 1040 * Initialization of interface; set up initialization block 1041 * and transmit/receive descriptor rings. 1042 */ 1043 int 1044 cas_init(struct ifnet *ifp) 1045 { 1046 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1047 bus_space_tag_t t = sc->sc_memt; 1048 bus_space_handle_t h = sc->sc_memh; 1049 int s; 1050 u_int max_frame_size; 1051 u_int32_t v; 1052 1053 s = splnet(); 1054 1055 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1056 /* 1057 * Initialization sequence. The numbered steps below correspond 1058 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1059 * Channel Engine manual (part of the PCIO manual). 1060 * See also the STP2002-STQ document from Sun Microsystems. 1061 */ 1062 1063 /* step 1 & 2. Reset the Ethernet Channel */ 1064 cas_stop(ifp, 0); 1065 cas_reset(sc); 1066 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1067 1068 /* Re-initialize the MIF */ 1069 cas_mifinit(sc); 1070 1071 /* step 3. Setup data structures in host memory */ 1072 cas_meminit(sc); 1073 1074 /* step 4. TX MAC registers & counters */ 1075 cas_init_regs(sc); 1076 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1077 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1078 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1079 1080 /* step 5. RX MAC registers & counters */ 1081 cas_iff(sc); 1082 1083 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1084 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1085 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1086 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1087 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1088 1089 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1090 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1091 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1092 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1093 1094 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1095 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1096 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1097 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1098 1099 if (CAS_PLUS(sc)) { 1100 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1101 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1102 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1103 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1104 CAS_CDRXADDR2(sc, 0)); 1105 } 1106 1107 /* step 8. Global Configuration & Interrupt Mask */ 1108 cas_estintr(sc, CAS_INTR_REG); 1109 1110 /* step 9. ETX Configuration: use mostly default values */ 1111 1112 /* Enable DMA */ 1113 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1114 bus_space_write_4(t, h, CAS_TX_CONFIG, 1115 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1116 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1117 1118 /* step 10. ERX Configuration */ 1119 1120 /* Encode Receive Descriptor ring size */ 1121 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1122 if (CAS_PLUS(sc)) 1123 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1124 1125 /* Encode Receive Completion ring size */ 1126 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1127 1128 /* Enable DMA */ 1129 bus_space_write_4(t, h, CAS_RX_CONFIG, 1130 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1131 1132 /* 1133 * The following value is for an OFF Threshold of about 3/4 full 1134 * and an ON Threshold of 1/4 full. 1135 */ 1136 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1137 (3 * sc->sc_rxfifosize / 256) | 1138 ((sc->sc_rxfifosize / 256) << 12)); 1139 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1140 1141 /* step 11. Configure Media */ 1142 mii_ifmedia_change(&sc->sc_mii); 1143 1144 /* step 12. RX_MAC Configuration Register */ 1145 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1146 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1147 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1148 1149 /* step 14. Issue Transmit Pending command */ 1150 1151 /* step 15. Give the receiver a swift kick */ 1152 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1153 if (CAS_PLUS(sc)) 1154 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1155 1156 /* Start the one second timer. */ 1157 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1158 1159 ifp->if_flags |= IFF_RUNNING; 1160 ifp->if_flags &= ~IFF_OACTIVE; 1161 ifp->if_timer = 0; 1162 splx(s); 1163 1164 return (0); 1165 } 1166 1167 void 1168 cas_init_regs(struct cas_softc *sc) 1169 { 1170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1171 bus_space_tag_t t = sc->sc_memt; 1172 bus_space_handle_t h = sc->sc_memh; 1173 const u_char *laddr = CLLADDR(ifp->if_sadl); 1174 u_int32_t v, r; 1175 1176 /* These regs are not cleared on reset */ 1177 sc->sc_inited = 0; 1178 if (!sc->sc_inited) { 1179 /* Load recommended values */ 1180 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1181 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1182 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1183 1184 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1185 /* Max frame and max burst size */ 1186 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1187 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1188 1189 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1190 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1191 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1192 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1193 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1194 ((laddr[5]<<8)|laddr[4])&0x3ff); 1195 1196 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1197 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1198 bus_space_write_4(t, h, r, 0); 1199 1200 /* MAC control addr set to 0:1:c2:0:1:80 */ 1201 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1202 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1203 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1204 1205 /* MAC filter addr set to 0:0:0:0:0:0 */ 1206 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1207 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1208 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1209 1210 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1211 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1212 1213 /* Hash table initialized to 0 */ 1214 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1215 bus_space_write_4(t, h, r, 0); 1216 1217 sc->sc_inited = 1; 1218 } 1219 1220 /* Counters need to be zeroed */ 1221 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1222 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1223 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1224 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1225 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1226 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1227 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1228 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1229 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1230 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1231 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1232 1233 /* Un-pause stuff */ 1234 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1235 1236 /* 1237 * Set the station address. 1238 */ 1239 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1240 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1241 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1242 } 1243 1244 /* 1245 * Receive interrupt. 1246 */ 1247 int 1248 cas_rint(struct cas_softc *sc) 1249 { 1250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1251 bus_space_tag_t t = sc->sc_memt; 1252 bus_space_handle_t h = sc->sc_memh; 1253 struct cas_rxsoft *rxs; 1254 struct mbuf *m; 1255 u_int64_t word[4]; 1256 int len, off, idx; 1257 int i, skip; 1258 void *cp; 1259 1260 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1261 CAS_CDRXCSYNC(sc, i, 1262 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1263 1264 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1265 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1266 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1267 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1268 1269 /* Stop if the hardware still owns the descriptor. */ 1270 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1271 break; 1272 1273 len = CAS_RC1_HDR_LEN(word[1]); 1274 if (len > 0) { 1275 off = CAS_RC1_HDR_OFF(word[1]); 1276 idx = CAS_RC1_HDR_IDX(word[1]); 1277 rxs = &sc->sc_rxsoft[idx]; 1278 1279 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1280 idx, off, len)); 1281 1282 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1283 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1284 1285 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1286 m = m_devget(cp, len, 0, ifp, NULL); 1287 1288 if (word[0] & CAS_RC0_RELEASE_HDR) 1289 cas_add_rxbuf(sc, idx); 1290 1291 if (m != NULL) { 1292 1293 /* 1294 * Pass this up to any BPF listeners, but only 1295 * pass it up the stack if its for us. 1296 */ 1297 if (ifp->if_bpf) 1298 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1299 1300 ifp->if_ipackets++; 1301 m->m_pkthdr.csum_flags = 0; 1302 (*ifp->if_input)(ifp, m); 1303 } else 1304 ifp->if_ierrors++; 1305 } 1306 1307 len = CAS_RC0_DATA_LEN(word[0]); 1308 if (len > 0) { 1309 off = CAS_RC0_DATA_OFF(word[0]); 1310 idx = CAS_RC0_DATA_IDX(word[0]); 1311 rxs = &sc->sc_rxsoft[idx]; 1312 1313 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1314 idx, off, len)); 1315 1316 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1317 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1318 1319 /* XXX We should not be copying the packet here. */ 1320 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1321 m = m_devget(cp, len, 0, ifp, NULL); 1322 1323 if (word[0] & CAS_RC0_RELEASE_DATA) 1324 cas_add_rxbuf(sc, idx); 1325 1326 if (m != NULL) { 1327 /* 1328 * Pass this up to any BPF listeners, but only 1329 * pass it up the stack if its for us. 1330 */ 1331 if (ifp->if_bpf) 1332 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1333 1334 ifp->if_ipackets++; 1335 m->m_pkthdr.csum_flags = 0; 1336 (*ifp->if_input)(ifp, m); 1337 } else 1338 ifp->if_ierrors++; 1339 } 1340 1341 if (word[0] & CAS_RC0_SPLIT) 1342 aprint_error_dev(sc->sc_dev, "split packet\n"); 1343 1344 skip = CAS_RC0_SKIP(word[0]); 1345 } 1346 1347 while (sc->sc_rxptr != i) { 1348 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1349 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1350 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1351 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1352 CAS_DMA_WRITE(CAS_RC3_OWN); 1353 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1354 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1355 1356 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1357 } 1358 1359 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1360 1361 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1362 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1363 1364 return (1); 1365 } 1366 1367 /* 1368 * cas_add_rxbuf: 1369 * 1370 * Add a receive buffer to the indicated descriptor. 1371 */ 1372 int 1373 cas_add_rxbuf(struct cas_softc *sc, int idx) 1374 { 1375 bus_space_tag_t t = sc->sc_memt; 1376 bus_space_handle_t h = sc->sc_memh; 1377 1378 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1379 1380 if ((sc->sc_rxdptr % 4) == 0) 1381 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1382 1383 if (++sc->sc_rxdptr == CAS_NRXDESC) 1384 sc->sc_rxdptr = 0; 1385 1386 return (0); 1387 } 1388 1389 int 1390 cas_eint(struct cas_softc *sc, u_int status) 1391 { 1392 char bits[128]; 1393 if ((status & CAS_INTR_MIF) != 0) { 1394 DPRINTF(sc, ("%s: link status changed\n", 1395 device_xname(sc->sc_dev))); 1396 return (1); 1397 } 1398 1399 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1400 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1401 return (1); 1402 } 1403 1404 int 1405 cas_pint(struct cas_softc *sc) 1406 { 1407 bus_space_tag_t t = sc->sc_memt; 1408 bus_space_handle_t seb = sc->sc_memh; 1409 u_int32_t status; 1410 1411 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1412 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1413 #ifdef CAS_DEBUG 1414 if (status) 1415 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1416 #endif 1417 return (1); 1418 } 1419 1420 int 1421 cas_intr(void *v) 1422 { 1423 struct cas_softc *sc = (struct cas_softc *)v; 1424 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1425 bus_space_tag_t t = sc->sc_memt; 1426 bus_space_handle_t seb = sc->sc_memh; 1427 u_int32_t status; 1428 int r = 0; 1429 #ifdef CAS_DEBUG 1430 char bits[128]; 1431 #endif 1432 1433 sc->sc_ev_intr.ev_count++; 1434 1435 status = bus_space_read_4(t, seb, CAS_STATUS); 1436 #ifdef CAS_DEBUG 1437 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1438 #endif 1439 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1440 device_xname(sc->sc_dev), (status>>19), bits)); 1441 1442 if ((status & CAS_INTR_PCS) != 0) 1443 r |= cas_pint(sc); 1444 1445 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1446 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1447 r |= cas_eint(sc, status); 1448 1449 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1450 r |= cas_tint(sc, status); 1451 1452 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1453 r |= cas_rint(sc); 1454 1455 /* We should eventually do more than just print out error stats. */ 1456 if (status & CAS_INTR_TX_MAC) { 1457 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1458 #ifdef CAS_DEBUG 1459 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1460 printf("%s: MAC tx fault, status %x\n", 1461 device_xname(sc->sc_dev), txstat); 1462 #endif 1463 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1464 cas_init(ifp); 1465 } 1466 if (status & CAS_INTR_RX_MAC) { 1467 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1468 #ifdef CAS_DEBUG 1469 if (rxstat & ~CAS_MAC_RX_DONE) 1470 printf("%s: MAC rx fault, status %x\n", 1471 device_xname(sc->sc_dev), rxstat); 1472 #endif 1473 /* 1474 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1475 * due to a silicon bug so handle them silently. 1476 */ 1477 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1478 ifp->if_ierrors++; 1479 cas_init(ifp); 1480 } 1481 #ifdef CAS_DEBUG 1482 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1483 printf("%s: MAC rx fault, status %x\n", 1484 device_xname(sc->sc_dev), rxstat); 1485 #endif 1486 } 1487 #if NRND > 0 1488 rnd_add_uint32(&sc->rnd_source, status); 1489 #endif 1490 return (r); 1491 } 1492 1493 1494 void 1495 cas_watchdog(struct ifnet *ifp) 1496 { 1497 struct cas_softc *sc = ifp->if_softc; 1498 1499 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1500 "CAS_MAC_RX_CONFIG %x\n", 1501 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1502 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1503 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1504 1505 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1506 ++ifp->if_oerrors; 1507 1508 /* Try to get more packets going. */ 1509 cas_init(ifp); 1510 } 1511 1512 /* 1513 * Initialize the MII Management Interface 1514 */ 1515 void 1516 cas_mifinit(struct cas_softc *sc) 1517 { 1518 bus_space_tag_t t = sc->sc_memt; 1519 bus_space_handle_t mif = sc->sc_memh; 1520 1521 /* Configure the MIF in frame mode */ 1522 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1523 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1524 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1525 } 1526 1527 /* 1528 * MII interface 1529 * 1530 * The Cassini MII interface supports at least three different operating modes: 1531 * 1532 * Bitbang mode is implemented using data, clock and output enable registers. 1533 * 1534 * Frame mode is implemented by loading a complete frame into the frame 1535 * register and polling the valid bit for completion. 1536 * 1537 * Polling mode uses the frame register but completion is indicated by 1538 * an interrupt. 1539 * 1540 */ 1541 int 1542 cas_mii_readreg(device_t self, int phy, int reg) 1543 { 1544 struct cas_softc *sc = device_private(self); 1545 bus_space_tag_t t = sc->sc_memt; 1546 bus_space_handle_t mif = sc->sc_memh; 1547 int n; 1548 u_int32_t v; 1549 1550 #ifdef CAS_DEBUG 1551 if (sc->sc_debug) 1552 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1553 #endif 1554 1555 /* Construct the frame command */ 1556 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1557 CAS_MIF_FRAME_READ; 1558 1559 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1560 for (n = 0; n < 100; n++) { 1561 DELAY(1); 1562 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1563 if (v & CAS_MIF_FRAME_TA0) 1564 return (v & CAS_MIF_FRAME_DATA); 1565 } 1566 1567 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1568 return (0); 1569 } 1570 1571 void 1572 cas_mii_writereg(device_t self, int phy, int reg, int val) 1573 { 1574 struct cas_softc *sc = device_private(self); 1575 bus_space_tag_t t = sc->sc_memt; 1576 bus_space_handle_t mif = sc->sc_memh; 1577 int n; 1578 u_int32_t v; 1579 1580 #ifdef CAS_DEBUG 1581 if (sc->sc_debug) 1582 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1583 phy, reg, val); 1584 #endif 1585 1586 /* Construct the frame command */ 1587 v = CAS_MIF_FRAME_WRITE | 1588 (phy << CAS_MIF_PHY_SHIFT) | 1589 (reg << CAS_MIF_REG_SHIFT) | 1590 (val & CAS_MIF_FRAME_DATA); 1591 1592 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1593 for (n = 0; n < 100; n++) { 1594 DELAY(1); 1595 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1596 if (v & CAS_MIF_FRAME_TA0) 1597 return; 1598 } 1599 1600 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1601 } 1602 1603 void 1604 cas_mii_statchg(device_t self) 1605 { 1606 struct cas_softc *sc = device_private(self); 1607 #ifdef CAS_DEBUG 1608 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1609 #endif 1610 bus_space_tag_t t = sc->sc_memt; 1611 bus_space_handle_t mac = sc->sc_memh; 1612 u_int32_t v; 1613 1614 #ifdef CAS_DEBUG 1615 if (sc->sc_debug) 1616 printf("cas_mii_statchg: status change: phy = %d\n", 1617 sc->sc_phys[instance]); 1618 #endif 1619 1620 /* Set tx full duplex options */ 1621 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1622 delay(10000); /* reg must be cleared and delay before changing. */ 1623 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1624 CAS_MAC_TX_ENABLE; 1625 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1626 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1627 } 1628 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1629 1630 /* XIF Configuration */ 1631 v = CAS_MAC_XIF_TX_MII_ENA; 1632 v |= CAS_MAC_XIF_LINK_LED; 1633 1634 /* MII needs echo disable if half duplex. */ 1635 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1636 /* turn on full duplex LED */ 1637 v |= CAS_MAC_XIF_FDPLX_LED; 1638 else 1639 /* half duplex -- disable echo */ 1640 v |= CAS_MAC_XIF_ECHO_DISABL; 1641 1642 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1643 case IFM_1000_T: /* Gigabit using GMII interface */ 1644 case IFM_1000_SX: 1645 v |= CAS_MAC_XIF_GMII_MODE; 1646 break; 1647 default: 1648 v &= ~CAS_MAC_XIF_GMII_MODE; 1649 } 1650 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1651 } 1652 1653 int 1654 cas_pcs_readreg(device_t self, int phy, int reg) 1655 { 1656 struct cas_softc *sc = device_private(self); 1657 bus_space_tag_t t = sc->sc_memt; 1658 bus_space_handle_t pcs = sc->sc_memh; 1659 1660 #ifdef CAS_DEBUG 1661 if (sc->sc_debug) 1662 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1663 #endif 1664 1665 if (phy != CAS_PHYAD_EXTERNAL) 1666 return (0); 1667 1668 switch (reg) { 1669 case MII_BMCR: 1670 reg = CAS_MII_CONTROL; 1671 break; 1672 case MII_BMSR: 1673 reg = CAS_MII_STATUS; 1674 break; 1675 case MII_ANAR: 1676 reg = CAS_MII_ANAR; 1677 break; 1678 case MII_ANLPAR: 1679 reg = CAS_MII_ANLPAR; 1680 break; 1681 case MII_EXTSR: 1682 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1683 default: 1684 return (0); 1685 } 1686 1687 return bus_space_read_4(t, pcs, reg); 1688 } 1689 1690 void 1691 cas_pcs_writereg(device_t self, int phy, int reg, int val) 1692 { 1693 struct cas_softc *sc = device_private(self); 1694 bus_space_tag_t t = sc->sc_memt; 1695 bus_space_handle_t pcs = sc->sc_memh; 1696 int reset = 0; 1697 1698 #ifdef CAS_DEBUG 1699 if (sc->sc_debug) 1700 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1701 phy, reg, val); 1702 #endif 1703 1704 if (phy != CAS_PHYAD_EXTERNAL) 1705 return; 1706 1707 if (reg == MII_ANAR) 1708 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1709 1710 switch (reg) { 1711 case MII_BMCR: 1712 reset = (val & CAS_MII_CONTROL_RESET); 1713 reg = CAS_MII_CONTROL; 1714 break; 1715 case MII_BMSR: 1716 reg = CAS_MII_STATUS; 1717 break; 1718 case MII_ANAR: 1719 reg = CAS_MII_ANAR; 1720 break; 1721 case MII_ANLPAR: 1722 reg = CAS_MII_ANLPAR; 1723 break; 1724 default: 1725 return; 1726 } 1727 1728 bus_space_write_4(t, pcs, reg, val); 1729 1730 if (reset) 1731 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1732 1733 if (reg == CAS_MII_ANAR || reset) 1734 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1735 CAS_MII_CONFIG_ENABLE); 1736 } 1737 1738 int 1739 cas_mediachange(struct ifnet *ifp) 1740 { 1741 struct cas_softc *sc = ifp->if_softc; 1742 struct mii_data *mii = &sc->sc_mii; 1743 1744 if (mii->mii_instance) { 1745 struct mii_softc *miisc; 1746 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1747 mii_phy_reset(miisc); 1748 } 1749 1750 return (mii_mediachg(&sc->sc_mii)); 1751 } 1752 1753 void 1754 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1755 { 1756 struct cas_softc *sc = ifp->if_softc; 1757 1758 mii_pollstat(&sc->sc_mii); 1759 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1760 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1761 } 1762 1763 /* 1764 * Process an ioctl request. 1765 */ 1766 int 1767 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1768 { 1769 struct cas_softc *sc = ifp->if_softc; 1770 int s, error = 0; 1771 1772 s = splnet(); 1773 1774 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1775 error = 0; 1776 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1777 ; 1778 else if (ifp->if_flags & IFF_RUNNING) { 1779 /* 1780 * Multicast list has changed; set the hardware filter 1781 * accordingly. 1782 */ 1783 cas_iff(sc); 1784 } 1785 } 1786 1787 splx(s); 1788 return (error); 1789 } 1790 1791 static bool 1792 cas_suspend(device_t self, const pmf_qual_t *qual) 1793 { 1794 struct cas_softc *sc = device_private(self); 1795 bus_space_tag_t t = sc->sc_memt; 1796 bus_space_handle_t h = sc->sc_memh; 1797 1798 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1799 if (sc->sc_ih != NULL) { 1800 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1801 sc->sc_ih = NULL; 1802 } 1803 1804 return true; 1805 } 1806 1807 static bool 1808 cas_resume(device_t self, const pmf_qual_t *qual) 1809 { 1810 struct cas_softc *sc = device_private(self); 1811 1812 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1813 } 1814 1815 static bool 1816 cas_estintr(struct cas_softc *sc, int what) 1817 { 1818 bus_space_tag_t t = sc->sc_memt; 1819 bus_space_handle_t h = sc->sc_memh; 1820 const char *intrstr = NULL; 1821 1822 /* PCI interrupts */ 1823 if (what & CAS_INTR_PCI) { 1824 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle); 1825 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1826 IPL_NET, cas_intr, sc); 1827 if (sc->sc_ih == NULL) { 1828 aprint_error_dev(sc->sc_dev, 1829 "unable to establish interrupt"); 1830 if (intrstr != NULL) 1831 aprint_error(" at %s", intrstr); 1832 aprint_error("\n"); 1833 return false; 1834 } 1835 1836 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1837 } 1838 1839 /* Interrupt register */ 1840 if (what & CAS_INTR_REG) { 1841 bus_space_write_4(t, h, CAS_INTMASK, 1842 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1843 CAS_INTR_TX_TAG_ERR| 1844 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1845 CAS_INTR_RX_TAG_ERR| 1846 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1847 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1848 CAS_INTR_BERR)); 1849 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1850 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1851 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1852 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1853 } 1854 return true; 1855 } 1856 1857 bool 1858 cas_shutdown(device_t self, int howto) 1859 { 1860 struct cas_softc *sc = device_private(self); 1861 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1862 1863 cas_stop(ifp, 1); 1864 1865 return true; 1866 } 1867 1868 void 1869 cas_iff(struct cas_softc *sc) 1870 { 1871 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1872 struct ethercom *ec = &sc->sc_ethercom; 1873 struct ether_multi *enm; 1874 struct ether_multistep step; 1875 bus_space_tag_t t = sc->sc_memt; 1876 bus_space_handle_t h = sc->sc_memh; 1877 u_int32_t crc, hash[16], rxcfg; 1878 int i; 1879 1880 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1881 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1882 CAS_MAC_RX_PROMISC_GRP); 1883 ifp->if_flags &= ~IFF_ALLMULTI; 1884 1885 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1886 ifp->if_flags |= IFF_ALLMULTI; 1887 if (ifp->if_flags & IFF_PROMISC) 1888 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1889 else 1890 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1891 } else { 1892 /* 1893 * Set up multicast address filter by passing all multicast 1894 * addresses through a crc generator, and then using the 1895 * high order 8 bits as an index into the 256 bit logical 1896 * address filter. The high order 4 bits selects the word, 1897 * while the other 4 bits select the bit within the word 1898 * (where bit 0 is the MSB). 1899 */ 1900 1901 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1902 1903 /* Clear hash table */ 1904 for (i = 0; i < 16; i++) 1905 hash[i] = 0; 1906 1907 ETHER_FIRST_MULTI(step, ec, enm); 1908 while (enm != NULL) { 1909 crc = ether_crc32_le(enm->enm_addrlo, 1910 ETHER_ADDR_LEN); 1911 1912 /* Just want the 8 most significant bits. */ 1913 crc >>= 24; 1914 1915 /* Set the corresponding bit in the filter. */ 1916 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1917 1918 ETHER_NEXT_MULTI(step, enm); 1919 } 1920 1921 /* Now load the hash table into the chip (if we are using it) */ 1922 for (i = 0; i < 16; i++) { 1923 bus_space_write_4(t, h, 1924 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1925 hash[i]); 1926 } 1927 } 1928 1929 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1930 } 1931 1932 int 1933 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1934 { 1935 u_int64_t flags; 1936 u_int32_t cur, frag, i; 1937 bus_dmamap_t map; 1938 1939 cur = frag = *bixp; 1940 map = sc->sc_txd[cur].sd_map; 1941 1942 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1943 BUS_DMA_NOWAIT) != 0) { 1944 return (ENOBUFS); 1945 } 1946 1947 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1948 bus_dmamap_unload(sc->sc_dmatag, map); 1949 return (ENOBUFS); 1950 } 1951 1952 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1953 BUS_DMASYNC_PREWRITE); 1954 1955 for (i = 0; i < map->dm_nsegs; i++) { 1956 sc->sc_txdescs[frag].cd_addr = 1957 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1958 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1959 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1960 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1961 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1962 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1963 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1964 BUS_DMASYNC_PREWRITE); 1965 cur = frag; 1966 if (++frag == CAS_NTXDESC) 1967 frag = 0; 1968 } 1969 1970 sc->sc_tx_cnt += map->dm_nsegs; 1971 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1972 sc->sc_txd[cur].sd_map = map; 1973 sc->sc_txd[cur].sd_mbuf = mhead; 1974 1975 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1976 1977 *bixp = frag; 1978 1979 /* sync descriptors */ 1980 1981 return (0); 1982 } 1983 1984 /* 1985 * Transmit interrupt. 1986 */ 1987 int 1988 cas_tint(struct cas_softc *sc, u_int32_t status) 1989 { 1990 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1991 struct cas_sxd *sd; 1992 u_int32_t cons, comp; 1993 1994 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 1995 cons = sc->sc_tx_cons; 1996 while (cons != comp) { 1997 sd = &sc->sc_txd[cons]; 1998 if (sd->sd_mbuf != NULL) { 1999 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2000 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2001 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2002 m_freem(sd->sd_mbuf); 2003 sd->sd_mbuf = NULL; 2004 ifp->if_opackets++; 2005 } 2006 sc->sc_tx_cnt--; 2007 if (++cons == CAS_NTXDESC) 2008 cons = 0; 2009 } 2010 sc->sc_tx_cons = cons; 2011 2012 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2013 ifp->if_flags &= ~IFF_OACTIVE; 2014 if (sc->sc_tx_cnt == 0) 2015 ifp->if_timer = 0; 2016 2017 cas_start(ifp); 2018 2019 return (1); 2020 } 2021 2022 void 2023 cas_start(struct ifnet *ifp) 2024 { 2025 struct cas_softc *sc = ifp->if_softc; 2026 struct mbuf *m; 2027 u_int32_t bix; 2028 2029 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2030 return; 2031 2032 bix = sc->sc_tx_prod; 2033 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2034 IFQ_POLL(&ifp->if_snd, m); 2035 if (m == NULL) 2036 break; 2037 2038 /* 2039 * If BPF is listening on this interface, let it see the 2040 * packet before we commit it to the wire. 2041 */ 2042 if (ifp->if_bpf) 2043 bpf_ops->bpf_mtap(ifp->if_bpf, m); 2044 2045 /* 2046 * Encapsulate this packet and start it going... 2047 * or fail... 2048 */ 2049 if (cas_encap(sc, m, &bix)) { 2050 ifp->if_flags |= IFF_OACTIVE; 2051 break; 2052 } 2053 2054 IFQ_DEQUEUE(&ifp->if_snd, m); 2055 ifp->if_timer = 5; 2056 } 2057 2058 sc->sc_tx_prod = bix; 2059 } 2060
Indexes created Thu Oct 02 01:09:59 GMT 2025