if_casvar.h revision 1.4
1 /* $NetBSD: if_casvar.h,v 1.4 2012/02/02 19:43:05 tls Exp $ */ 2 /* $OpenBSD: if_casvar.h,v 1.6 2009/06/13 12:18:58 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef _IF_CASVAR_H 35 #define _IF_CASVAR_H 36 37 #include <sys/queue.h> 38 #include <sys/callout.h> 39 40 /* 41 * Misc. definitions for Sun Cassini ethernet controllers. 42 */ 43 44 /* 45 * Preferred page size. Cassini has a configurable page size, but 46 * needs at least 8k to handle jumbo frames. This happens to be the 47 * default anyway. 48 */ 49 #define CAS_PAGE_SIZE 8192 50 51 /* 52 * Transmit descriptor ring size. This is arbitrary, but allocate 53 * enough descriptors for 64 pending transmissions and 16 segments 54 * per packet. 55 */ 56 #define CAS_NTXSEGS 16 57 58 #define CAS_TXQUEUELEN 64 59 #define CAS_NTXDESC (CAS_TXQUEUELEN * CAS_NTXSEGS) 60 #define CAS_NTXDESC_MASK (CAS_NTXDESC - 1) 61 #define CAS_NEXTTX(x) ((x + 1) & CAS_NTXDESC_MASK) 62 63 struct cas_sxd { 64 struct mbuf *sd_mbuf; 65 bus_dmamap_t sd_map; 66 }; 67 68 /* 69 * Receive descriptor ring size. We have one Rx buffer per incoming 70 * packet, so this logic is a little simpler. 71 */ 72 #define CAS_NRXDESC 128 73 #define CAS_NRXDESC_MASK (CAS_NRXDESC - 1) 74 75 /* 76 * Receive completion ring size. 77 */ 78 #define CAS_NRXCOMP 256 79 #define CAS_NRXCOMP_MASK (CAS_NRXCOMP - 1) 80 #define CAS_NEXTRX(x) ((x + 1) & CAS_NRXCOMP_MASK) 81 82 /* 83 * Control structures are DMA'd to the Cassini chip. We allocate them in 84 * a single clump that maps to a single DMA segment to make several things 85 * easier. 86 */ 87 struct cas_control_data { 88 /* 89 * The transmit descriptors. 90 */ 91 struct cas_desc ccd_txdescs[CAS_NTXDESC]; 92 93 /* 94 * The receive completions. 95 */ 96 struct cas_comp ccd_rxcomps[CAS_NRXCOMP]; 97 98 /* 99 * The receive descriptors. 100 */ 101 struct cas_desc ccd_rxdescs[CAS_NRXDESC]; 102 char ccd_unused[CAS_PAGE_SIZE - CAS_NRXDESC * 16]; 103 struct cas_desc ccd_rxdescs2[CAS_NRXDESC]; 104 }; 105 106 #define CAS_CDOFF(x) offsetof(struct cas_control_data, x) 107 #define CAS_CDTXOFF(x) CAS_CDOFF(ccd_txdescs[(x)]) 108 #define CAS_CDRXOFF(x) CAS_CDOFF(ccd_rxdescs[(x)]) 109 #define CAS_CDRXOFF2(x) CAS_CDOFF(ccd_rxdescs2[(x)]) 110 #define CAS_CDRXCOFF(x) CAS_CDOFF(ccd_rxcomps[(x)]) 111 112 /* 113 * Software state for receive jobs. 114 */ 115 struct cas_rxsoft { 116 bus_dmamap_t rxs_dmamap; /* our DMA map */ 117 bus_dma_segment_t rxs_dmaseg; /* our DMA segment */ 118 char *rxs_kva; 119 }; 120 121 enum cas_attach_stage { 122 CAS_ATT_BACKEND_2 = 0 123 , CAS_ATT_BACKEND_1 124 , CAS_ATT_FINISHED 125 , CAS_ATT_MII 126 , CAS_ATT_7 127 , CAS_ATT_6 128 , CAS_ATT_5 129 , CAS_ATT_4 130 , CAS_ATT_3 131 , CAS_ATT_2 132 , CAS_ATT_1 133 , CAS_ATT_0 134 , CAS_ATT_BACKEND_0 135 }; 136 137 /* 138 * Software state per device. 139 */ 140 struct cas_softc { 141 device_t sc_dev; /* generic device information */ 142 struct ethercom sc_ethercom; /* ethernet common data */ 143 struct mii_data sc_mii; /* MII media control */ 144 #define sc_media sc_mii.mii_media/* shorthand */ 145 struct callout sc_tick_ch; /* tick callout */ 146 147 bus_space_tag_t sc_memt; 148 bus_space_handle_t sc_memh; 149 bus_size_t sc_size; 150 151 void *sc_ih; 152 pci_chipset_tag_t sc_pc; 153 pci_intr_handle_t sc_handle; 154 155 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 156 bus_dmamap_t sc_dmamap; /* bus dma handle */ 157 int sc_burst; /* DVMA burst size in effect */ 158 int sc_phys[2]; /* MII instance -> PHY map */ 159 160 int sc_mif_config; /* Selected MII reg setting */ 161 162 /* 163 * Ring buffer DMA stuff. 164 */ 165 bus_dma_segment_t sc_cdseg; /* control data memory */ 166 int sc_cdnseg; /* number of segments */ 167 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 168 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 169 170 /* 171 * Software state for transmit and receive descriptors. 172 */ 173 struct cas_sxd sc_txd[CAS_NTXDESC]; 174 u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons; 175 176 struct cas_rxsoft sc_rxsoft[CAS_NRXDESC]; 177 struct cas_rxsoft sc_rxsoft2[CAS_NRXDESC]; 178 179 /* 180 * Control data structures. 181 */ 182 struct cas_control_data *sc_control_data; 183 #define sc_txdescs sc_control_data->ccd_txdescs 184 #define sc_rxdescs sc_control_data->ccd_rxdescs 185 #define sc_rxdescs2 sc_control_data->ccd_rxdescs2 186 #define sc_rxcomps sc_control_data->ccd_rxcomps 187 188 int sc_rxptr; /* next ready RX descriptor/descsoft */ 189 int sc_rxfifosize; 190 int sc_rxdptr; 191 192 int sc_rev; 193 int sc_inited; 194 int sc_debug; 195 void *sc_sh; /* shutdownhook cookie */ 196 197 krndsource_t rnd_source; 198 199 struct evcnt sc_ev_intr; 200 enum cas_attach_stage sc_att_stage; 201 }; 202 203 /* 204 * This maccro determines whether we have a Cassini+. 205 */ 206 #define CAS_PLUS(sc) (sc->sc_rev > 0x10) 207 208 #define CAS_DMA_READ(v) le64toh(v) 209 #define CAS_DMA_WRITE(v) htole64(v) 210 211 #define CAS_CDTXADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXOFF((x))) 212 #define CAS_CDRXADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF((x))) 213 #define CAS_CDRXADDR2(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF2((x))) 214 #define CAS_CDRXCADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXCOFF((x))) 215 216 #define CAS_CDTXSYNC(sc, x, n, ops) \ 217 do { \ 218 int __x, __n; \ 219 \ 220 __x = (x); \ 221 __n = (n); \ 222 \ 223 /* If it will wrap around, sync to the end of the ring. */ \ 224 if ((__x + __n) > CAS_NTXDESC) { \ 225 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 226 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * \ 227 (CAS_NTXDESC - __x), (ops)); \ 228 __n -= (CAS_NTXDESC - __x); \ 229 __x = 0; \ 230 } \ 231 \ 232 /* Now sync whatever is left. */ \ 233 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 234 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * __n, (ops)); \ 235 } while (0) 236 237 #define CAS_CDRXSYNC(sc, x, ops) \ 238 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 239 CAS_CDRXOFF((x)), sizeof(struct cas_desc), (ops)) 240 241 #define CAS_CDRXCSYNC(sc, x, ops) \ 242 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 243 CAS_CDRXCOFF((x)), sizeof(struct cas_desc), (ops)) 244 245 #define CAS_INIT_RXDESC(sc, d, s) \ 246 do { \ 247 struct cas_rxsoft *__rxs = &sc->sc_rxsoft[(s)]; \ 248 struct cas_desc *__rxd = &sc->sc_rxdescs[(d)]; \ 249 \ 250 __rxd->cd_addr = \ 251 CAS_DMA_WRITE(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 252 __rxd->cd_flags = \ 253 CAS_DMA_WRITE((s)); \ 254 CAS_CDRXSYNC((sc), (d), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 255 } while (0) 256 257 #define CAS_INTR_PCI 1 258 #define CAS_INTR_REG 2 259 260 #define ETHER_ALIGN 2 261 262 #endif 263
Indexes created Mon Oct 20 20:10:13 GMT 2025