if_dge.c revision 1.5.2.5
1 1.5.2.5 skrll /* $NetBSD: if_dge.c,v 1.5.2.5 2004/09/24 10:53:28 skrll Exp $ */ 2 1.5.2.2 skrll 3 1.5.2.2 skrll /* 4 1.5.2.2 skrll * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 1.5.2.2 skrll * All rights reserved. 6 1.5.2.2 skrll * 7 1.5.2.2 skrll * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 1.5.2.2 skrll * 9 1.5.2.2 skrll * Redistribution and use in source and binary forms, with or without 10 1.5.2.2 skrll * modification, are permitted provided that the following conditions 11 1.5.2.2 skrll * are met: 12 1.5.2.2 skrll * 1. Redistributions of source code must retain the above copyright 13 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer. 14 1.5.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 15 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer in the 16 1.5.2.2 skrll * documentation and/or other materials provided with the distribution. 17 1.5.2.2 skrll * 3. All advertising materials mentioning features or use of this software 18 1.5.2.2 skrll * must display the following acknowledgement: 19 1.5.2.2 skrll * This product includes software developed for the NetBSD Project by 20 1.5.2.2 skrll * SUNET, Swedish University Computer Network. 21 1.5.2.2 skrll * 4. The name of SUNET may not be used to endorse or promote products 22 1.5.2.2 skrll * derived from this software without specific prior written permission. 23 1.5.2.2 skrll * 24 1.5.2.2 skrll * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 1.5.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 1.5.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 1.5.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 1.5.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 1.5.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 1.5.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 1.5.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 1.5.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 1.5.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 1.5.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 35 1.5.2.2 skrll */ 36 1.5.2.2 skrll 37 1.5.2.2 skrll /* 38 1.5.2.2 skrll * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 1.5.2.2 skrll * All rights reserved. 40 1.5.2.2 skrll * 41 1.5.2.2 skrll * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 1.5.2.2 skrll * 43 1.5.2.2 skrll * Redistribution and use in source and binary forms, with or without 44 1.5.2.2 skrll * modification, are permitted provided that the following conditions 45 1.5.2.2 skrll * are met: 46 1.5.2.2 skrll * 1. Redistributions of source code must retain the above copyright 47 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer. 48 1.5.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 49 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer in the 50 1.5.2.2 skrll * documentation and/or other materials provided with the distribution. 51 1.5.2.2 skrll * 3. All advertising materials mentioning features or use of this software 52 1.5.2.2 skrll * must display the following acknowledgement: 53 1.5.2.2 skrll * This product includes software developed for the NetBSD Project by 54 1.5.2.2 skrll * Wasabi Systems, Inc. 55 1.5.2.2 skrll * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 1.5.2.2 skrll * or promote products derived from this software without specific prior 57 1.5.2.2 skrll * written permission. 58 1.5.2.2 skrll * 59 1.5.2.2 skrll * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 1.5.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 1.5.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 1.5.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 1.5.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 1.5.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 1.5.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 1.5.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 1.5.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 1.5.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 1.5.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 70 1.5.2.2 skrll */ 71 1.5.2.2 skrll 72 1.5.2.2 skrll /* 73 1.5.2.2 skrll * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 1.5.2.2 skrll * 75 1.5.2.2 skrll * TODO (in no specific order): 76 1.5.2.2 skrll * HW VLAN support. 77 1.5.2.2 skrll * TSE offloading (needs kernel changes...) 78 1.5.2.2 skrll * RAIDC (receive interrupt delay adaptation) 79 1.5.2.2 skrll * Use memory > 4GB. 80 1.5.2.2 skrll */ 81 1.5.2.2 skrll 82 1.5.2.2 skrll #include <sys/cdefs.h> 83 1.5.2.5 skrll __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.5.2.5 2004/09/24 10:53:28 skrll Exp $"); 84 1.5.2.2 skrll 85 1.5.2.2 skrll #include "bpfilter.h" 86 1.5.2.2 skrll #include "rnd.h" 87 1.5.2.2 skrll 88 1.5.2.2 skrll #include <sys/param.h> 89 1.5.2.2 skrll #include <sys/systm.h> 90 1.5.2.2 skrll #include <sys/callout.h> 91 1.5.2.2 skrll #include <sys/mbuf.h> 92 1.5.2.2 skrll #include <sys/malloc.h> 93 1.5.2.2 skrll #include <sys/kernel.h> 94 1.5.2.2 skrll #include <sys/socket.h> 95 1.5.2.2 skrll #include <sys/ioctl.h> 96 1.5.2.2 skrll #include <sys/errno.h> 97 1.5.2.2 skrll #include <sys/device.h> 98 1.5.2.2 skrll #include <sys/queue.h> 99 1.5.2.2 skrll 100 1.5.2.2 skrll #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 1.5.2.2 skrll 102 1.5.2.2 skrll #if NRND > 0 103 1.5.2.2 skrll #include <sys/rnd.h> 104 1.5.2.2 skrll #endif 105 1.5.2.2 skrll 106 1.5.2.2 skrll #include <net/if.h> 107 1.5.2.2 skrll #include <net/if_dl.h> 108 1.5.2.2 skrll #include <net/if_media.h> 109 1.5.2.2 skrll #include <net/if_ether.h> 110 1.5.2.2 skrll 111 1.5.2.2 skrll #if NBPFILTER > 0 112 1.5.2.2 skrll #include <net/bpf.h> 113 1.5.2.2 skrll #endif 114 1.5.2.2 skrll 115 1.5.2.2 skrll #include <netinet/in.h> /* XXX for struct ip */ 116 1.5.2.2 skrll #include <netinet/in_systm.h> /* XXX for struct ip */ 117 1.5.2.2 skrll #include <netinet/ip.h> /* XXX for struct ip */ 118 1.5.2.2 skrll #include <netinet/tcp.h> /* XXX for struct tcphdr */ 119 1.5.2.2 skrll 120 1.5.2.2 skrll #include <machine/bus.h> 121 1.5.2.2 skrll #include <machine/intr.h> 122 1.5.2.2 skrll #include <machine/endian.h> 123 1.5.2.2 skrll 124 1.5.2.2 skrll #include <dev/mii/mii.h> 125 1.5.2.2 skrll #include <dev/mii/miivar.h> 126 1.5.2.2 skrll #include <dev/mii/mii_bitbang.h> 127 1.5.2.2 skrll 128 1.5.2.2 skrll #include <dev/pci/pcireg.h> 129 1.5.2.2 skrll #include <dev/pci/pcivar.h> 130 1.5.2.2 skrll #include <dev/pci/pcidevs.h> 131 1.5.2.2 skrll 132 1.5.2.2 skrll #include <dev/pci/if_dgereg.h> 133 1.5.2.2 skrll 134 1.5.2.2 skrll /* 135 1.5.2.2 skrll * The receive engine may sometimes become off-by-one when writing back 136 1.5.2.2 skrll * chained descriptors. Avoid this by allocating a large chunk of 137 1.5.2.2 skrll * memory and use if instead (to avoid chained descriptors). 138 1.5.2.2 skrll * This only happens with chained descriptors under heavy load. 139 1.5.2.2 skrll */ 140 1.5.2.2 skrll #define DGE_OFFBYONE_RXBUG 141 1.5.2.2 skrll 142 1.5.2.2 skrll #define DGE_EVENT_COUNTERS 143 1.5.2.2 skrll #define DGE_DEBUG 144 1.5.2.2 skrll 145 1.5.2.2 skrll #ifdef DGE_DEBUG 146 1.5.2.2 skrll #define DGE_DEBUG_LINK 0x01 147 1.5.2.2 skrll #define DGE_DEBUG_TX 0x02 148 1.5.2.2 skrll #define DGE_DEBUG_RX 0x04 149 1.5.2.2 skrll #define DGE_DEBUG_CKSUM 0x08 150 1.5.2.2 skrll int dge_debug = 0; 151 1.5.2.2 skrll 152 1.5.2.2 skrll #define DPRINTF(x, y) if (dge_debug & (x)) printf y 153 1.5.2.2 skrll #else 154 1.5.2.2 skrll #define DPRINTF(x, y) /* nothing */ 155 1.5.2.2 skrll #endif /* DGE_DEBUG */ 156 1.5.2.2 skrll 157 1.5.2.2 skrll /* 158 1.5.2.2 skrll * Transmit descriptor list size. We allow up to 100 DMA segments per 159 1.5.2.2 skrll * packet (Intel reports of jumbo frame packets with as 160 1.5.2.2 skrll * many as 80 DMA segments when using 16k buffers). 161 1.5.2.2 skrll */ 162 1.5.2.2 skrll #define DGE_NTXSEGS 100 163 1.5.2.2 skrll #define DGE_IFQUEUELEN 20000 164 1.5.2.2 skrll #define DGE_TXQUEUELEN 2048 165 1.5.2.2 skrll #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 166 1.5.2.2 skrll #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 167 1.5.2.2 skrll #define DGE_NTXDESC 1024 168 1.5.2.2 skrll #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 169 1.5.2.2 skrll #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 170 1.5.2.2 skrll #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 171 1.5.2.2 skrll 172 1.5.2.2 skrll /* 173 1.5.2.2 skrll * Receive descriptor list size. 174 1.5.2.2 skrll * Packet is of size MCLBYTES, and for jumbo packets buffers may 175 1.5.2.2 skrll * be chained. Due to the nature of the card (high-speed), keep this 176 1.5.2.2 skrll * ring large. With 2k buffers the ring can store 400 jumbo packets, 177 1.5.2.2 skrll * which at full speed will be received in just under 3ms. 178 1.5.2.2 skrll */ 179 1.5.2.2 skrll #define DGE_NRXDESC 2048 180 1.5.2.2 skrll #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 181 1.5.2.2 skrll #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 182 1.5.2.2 skrll /* 183 1.5.2.2 skrll * # of descriptors between head and written descriptors. 184 1.5.2.2 skrll * This is to work-around two erratas. 185 1.5.2.2 skrll */ 186 1.5.2.2 skrll #define DGE_RXSPACE 10 187 1.5.2.2 skrll #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 188 1.5.2.2 skrll /* 189 1.5.2.2 skrll * Receive descriptor fetch threshholds. These are values recommended 190 1.5.2.2 skrll * by Intel, do not touch them unless you know what you are doing. 191 1.5.2.2 skrll */ 192 1.5.2.2 skrll #define RXDCTL_PTHRESH_VAL 128 193 1.5.2.2 skrll #define RXDCTL_HTHRESH_VAL 16 194 1.5.2.2 skrll #define RXDCTL_WTHRESH_VAL 16 195 1.5.2.2 skrll 196 1.5.2.2 skrll 197 1.5.2.2 skrll /* 198 1.5.2.2 skrll * Tweakable parameters; default values. 199 1.5.2.2 skrll */ 200 1.5.2.2 skrll #define FCRTH 0x30000 /* Send XOFF water mark */ 201 1.5.2.2 skrll #define FCRTL 0x28000 /* Send XON water mark */ 202 1.5.2.2 skrll #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 203 1.5.2.2 skrll #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 204 1.5.2.2 skrll 205 1.5.2.2 skrll /* 206 1.5.2.2 skrll * Control structures are DMA'd to the i82597 chip. We allocate them in 207 1.5.2.2 skrll * a single clump that maps to a single DMA segment to make serveral things 208 1.5.2.2 skrll * easier. 209 1.5.2.2 skrll */ 210 1.5.2.2 skrll struct dge_control_data { 211 1.5.2.2 skrll /* 212 1.5.2.2 skrll * The transmit descriptors. 213 1.5.2.2 skrll */ 214 1.5.2.2 skrll struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 215 1.5.2.2 skrll 216 1.5.2.2 skrll /* 217 1.5.2.2 skrll * The receive descriptors. 218 1.5.2.2 skrll */ 219 1.5.2.2 skrll struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 220 1.5.2.2 skrll }; 221 1.5.2.2 skrll 222 1.5.2.2 skrll #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 223 1.5.2.2 skrll #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 224 1.5.2.2 skrll #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 225 1.5.2.2 skrll 226 1.5.2.2 skrll /* 227 1.5.2.2 skrll * The DGE interface have a higher max MTU size than normal jumbo frames. 228 1.5.2.2 skrll */ 229 1.5.2.2 skrll #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 230 1.5.2.2 skrll 231 1.5.2.2 skrll /* 232 1.5.2.2 skrll * Software state for transmit jobs. 233 1.5.2.2 skrll */ 234 1.5.2.2 skrll struct dge_txsoft { 235 1.5.2.2 skrll struct mbuf *txs_mbuf; /* head of our mbuf chain */ 236 1.5.2.2 skrll bus_dmamap_t txs_dmamap; /* our DMA map */ 237 1.5.2.2 skrll int txs_firstdesc; /* first descriptor in packet */ 238 1.5.2.2 skrll int txs_lastdesc; /* last descriptor in packet */ 239 1.5.2.2 skrll int txs_ndesc; /* # of descriptors used */ 240 1.5.2.2 skrll }; 241 1.5.2.2 skrll 242 1.5.2.2 skrll /* 243 1.5.2.2 skrll * Software state for receive buffers. Each descriptor gets a 244 1.5.2.2 skrll * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 245 1.5.2.2 skrll * more than one buffer, we chain them together. 246 1.5.2.2 skrll */ 247 1.5.2.2 skrll struct dge_rxsoft { 248 1.5.2.2 skrll struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 249 1.5.2.2 skrll bus_dmamap_t rxs_dmamap; /* our DMA map */ 250 1.5.2.2 skrll }; 251 1.5.2.2 skrll 252 1.5.2.2 skrll /* 253 1.5.2.2 skrll * Software state per device. 254 1.5.2.2 skrll */ 255 1.5.2.2 skrll struct dge_softc { 256 1.5.2.2 skrll struct device sc_dev; /* generic device information */ 257 1.5.2.2 skrll bus_space_tag_t sc_st; /* bus space tag */ 258 1.5.2.2 skrll bus_space_handle_t sc_sh; /* bus space handle */ 259 1.5.2.2 skrll bus_dma_tag_t sc_dmat; /* bus DMA tag */ 260 1.5.2.2 skrll struct ethercom sc_ethercom; /* ethernet common data */ 261 1.5.2.2 skrll void *sc_sdhook; /* shutdown hook */ 262 1.5.2.2 skrll 263 1.5.2.2 skrll int sc_flags; /* flags; see below */ 264 1.5.2.2 skrll int sc_bus_speed; /* PCI/PCIX bus speed */ 265 1.5.2.2 skrll int sc_pcix_offset; /* PCIX capability register offset */ 266 1.5.2.2 skrll 267 1.5.2.2 skrll pci_chipset_tag_t sc_pc; 268 1.5.2.2 skrll pcitag_t sc_pt; 269 1.5.2.2 skrll int sc_mmrbc; /* Max PCIX memory read byte count */ 270 1.5.2.2 skrll 271 1.5.2.2 skrll void *sc_ih; /* interrupt cookie */ 272 1.5.2.2 skrll 273 1.5.2.2 skrll struct ifmedia sc_media; 274 1.5.2.2 skrll 275 1.5.2.2 skrll bus_dmamap_t sc_cddmamap; /* control data DMA map */ 276 1.5.2.2 skrll #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 277 1.5.2.2 skrll 278 1.5.2.2 skrll int sc_align_tweak; 279 1.5.2.2 skrll 280 1.5.2.2 skrll /* 281 1.5.2.2 skrll * Software state for the transmit and receive descriptors. 282 1.5.2.2 skrll */ 283 1.5.2.2 skrll struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 284 1.5.2.2 skrll struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 285 1.5.2.2 skrll 286 1.5.2.2 skrll /* 287 1.5.2.2 skrll * Control data structures. 288 1.5.2.2 skrll */ 289 1.5.2.2 skrll struct dge_control_data *sc_control_data; 290 1.5.2.2 skrll #define sc_txdescs sc_control_data->wcd_txdescs 291 1.5.2.2 skrll #define sc_rxdescs sc_control_data->wcd_rxdescs 292 1.5.2.2 skrll 293 1.5.2.2 skrll #ifdef DGE_EVENT_COUNTERS 294 1.5.2.2 skrll /* Event counters. */ 295 1.5.2.2 skrll struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 296 1.5.2.2 skrll struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 297 1.5.2.2 skrll struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 298 1.5.2.2 skrll struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 299 1.5.2.2 skrll struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 300 1.5.2.2 skrll struct evcnt sc_ev_rxintr; /* Rx interrupts */ 301 1.5.2.2 skrll struct evcnt sc_ev_linkintr; /* Link interrupts */ 302 1.5.2.2 skrll 303 1.5.2.2 skrll struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 304 1.5.2.2 skrll struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 305 1.5.2.2 skrll struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 306 1.5.2.2 skrll struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 307 1.5.2.2 skrll 308 1.5.2.2 skrll struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 309 1.5.2.2 skrll struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 310 1.5.2.2 skrll struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 311 1.5.2.2 skrll 312 1.5.2.2 skrll struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 313 1.5.2.2 skrll struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 314 1.5.2.2 skrll #endif /* DGE_EVENT_COUNTERS */ 315 1.5.2.2 skrll 316 1.5.2.2 skrll int sc_txfree; /* number of free Tx descriptors */ 317 1.5.2.2 skrll int sc_txnext; /* next ready Tx descriptor */ 318 1.5.2.2 skrll 319 1.5.2.2 skrll int sc_txsfree; /* number of free Tx jobs */ 320 1.5.2.2 skrll int sc_txsnext; /* next free Tx job */ 321 1.5.2.2 skrll int sc_txsdirty; /* dirty Tx jobs */ 322 1.5.2.2 skrll 323 1.5.2.2 skrll uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 324 1.5.2.2 skrll uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 325 1.5.2.2 skrll 326 1.5.2.2 skrll int sc_rxptr; /* next ready Rx descriptor/queue ent */ 327 1.5.2.2 skrll int sc_rxdiscard; 328 1.5.2.2 skrll int sc_rxlen; 329 1.5.2.2 skrll struct mbuf *sc_rxhead; 330 1.5.2.2 skrll struct mbuf *sc_rxtail; 331 1.5.2.2 skrll struct mbuf **sc_rxtailp; 332 1.5.2.2 skrll 333 1.5.2.2 skrll uint32_t sc_ctrl0; /* prototype CTRL0 register */ 334 1.5.2.2 skrll uint32_t sc_icr; /* prototype interrupt bits */ 335 1.5.2.2 skrll uint32_t sc_tctl; /* prototype TCTL register */ 336 1.5.2.2 skrll uint32_t sc_rctl; /* prototype RCTL register */ 337 1.5.2.2 skrll 338 1.5.2.2 skrll int sc_mchash_type; /* multicast filter offset */ 339 1.5.2.2 skrll 340 1.5.2.2 skrll uint16_t sc_eeprom[EEPROM_SIZE]; 341 1.5.2.2 skrll 342 1.5.2.2 skrll #if NRND > 0 343 1.5.2.2 skrll rndsource_element_t rnd_source; /* random source */ 344 1.5.2.2 skrll #endif 345 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 346 1.5.2.2 skrll caddr_t sc_bugbuf; 347 1.5.2.2 skrll SLIST_HEAD(, rxbugentry) sc_buglist; 348 1.5.2.2 skrll bus_dmamap_t sc_bugmap; 349 1.5.2.2 skrll struct rxbugentry *sc_entry; 350 1.5.2.2 skrll #endif 351 1.5.2.2 skrll }; 352 1.5.2.2 skrll 353 1.5.2.2 skrll #define DGE_RXCHAIN_RESET(sc) \ 354 1.5.2.2 skrll do { \ 355 1.5.2.2 skrll (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 356 1.5.2.2 skrll *(sc)->sc_rxtailp = NULL; \ 357 1.5.2.2 skrll (sc)->sc_rxlen = 0; \ 358 1.5.2.2 skrll } while (/*CONSTCOND*/0) 359 1.5.2.2 skrll 360 1.5.2.2 skrll #define DGE_RXCHAIN_LINK(sc, m) \ 361 1.5.2.2 skrll do { \ 362 1.5.2.2 skrll *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 363 1.5.2.2 skrll (sc)->sc_rxtailp = &(m)->m_next; \ 364 1.5.2.2 skrll } while (/*CONSTCOND*/0) 365 1.5.2.2 skrll 366 1.5.2.2 skrll /* sc_flags */ 367 1.5.2.2 skrll #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 368 1.5.2.2 skrll #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 369 1.5.2.2 skrll 370 1.5.2.2 skrll #ifdef DGE_EVENT_COUNTERS 371 1.5.2.2 skrll #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 372 1.5.2.2 skrll #else 373 1.5.2.2 skrll #define DGE_EVCNT_INCR(ev) /* nothing */ 374 1.5.2.2 skrll #endif 375 1.5.2.2 skrll 376 1.5.2.2 skrll #define CSR_READ(sc, reg) \ 377 1.5.2.2 skrll bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 1.5.2.2 skrll #define CSR_WRITE(sc, reg, val) \ 379 1.5.2.2 skrll bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 1.5.2.2 skrll 381 1.5.2.2 skrll #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 382 1.5.2.2 skrll #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 383 1.5.2.2 skrll 384 1.5.2.2 skrll #define DGE_CDTXSYNC(sc, x, n, ops) \ 385 1.5.2.2 skrll do { \ 386 1.5.2.2 skrll int __x, __n; \ 387 1.5.2.2 skrll \ 388 1.5.2.2 skrll __x = (x); \ 389 1.5.2.2 skrll __n = (n); \ 390 1.5.2.2 skrll \ 391 1.5.2.2 skrll /* If it will wrap around, sync to the end of the ring. */ \ 392 1.5.2.2 skrll if ((__x + __n) > DGE_NTXDESC) { \ 393 1.5.2.2 skrll bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 394 1.5.2.2 skrll DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 395 1.5.2.2 skrll (DGE_NTXDESC - __x), (ops)); \ 396 1.5.2.2 skrll __n -= (DGE_NTXDESC - __x); \ 397 1.5.2.2 skrll __x = 0; \ 398 1.5.2.2 skrll } \ 399 1.5.2.2 skrll \ 400 1.5.2.2 skrll /* Now sync whatever is left. */ \ 401 1.5.2.2 skrll bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 1.5.2.2 skrll DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 403 1.5.2.2 skrll } while (/*CONSTCOND*/0) 404 1.5.2.2 skrll 405 1.5.2.2 skrll #define DGE_CDRXSYNC(sc, x, ops) \ 406 1.5.2.2 skrll do { \ 407 1.5.2.2 skrll bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 408 1.5.2.2 skrll DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 409 1.5.2.2 skrll } while (/*CONSTCOND*/0) 410 1.5.2.2 skrll 411 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 412 1.5.2.2 skrll #define DGE_INIT_RXDESC(sc, x) \ 413 1.5.2.2 skrll do { \ 414 1.5.2.2 skrll struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 415 1.5.2.2 skrll struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 416 1.5.2.2 skrll struct mbuf *__m = __rxs->rxs_mbuf; \ 417 1.5.2.2 skrll \ 418 1.5.2.2 skrll __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 419 1.5.2.2 skrll (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 420 1.5.2.2 skrll __rxd->dr_baddrh = 0; \ 421 1.5.2.2 skrll __rxd->dr_len = 0; \ 422 1.5.2.2 skrll __rxd->dr_cksum = 0; \ 423 1.5.2.2 skrll __rxd->dr_status = 0; \ 424 1.5.2.2 skrll __rxd->dr_errors = 0; \ 425 1.5.2.2 skrll __rxd->dr_special = 0; \ 426 1.5.2.2 skrll DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 427 1.5.2.2 skrll \ 428 1.5.2.2 skrll CSR_WRITE((sc), DGE_RDT, (x)); \ 429 1.5.2.2 skrll } while (/*CONSTCOND*/0) 430 1.5.2.2 skrll #else 431 1.5.2.2 skrll #define DGE_INIT_RXDESC(sc, x) \ 432 1.5.2.2 skrll do { \ 433 1.5.2.2 skrll struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 434 1.5.2.2 skrll struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 435 1.5.2.2 skrll struct mbuf *__m = __rxs->rxs_mbuf; \ 436 1.5.2.2 skrll \ 437 1.5.2.2 skrll /* \ 438 1.5.2.2 skrll * Note: We scoot the packet forward 2 bytes in the buffer \ 439 1.5.2.2 skrll * so that the payload after the Ethernet header is aligned \ 440 1.5.2.2 skrll * to a 4-byte boundary. \ 441 1.5.2.2 skrll * \ 442 1.5.2.2 skrll * XXX BRAINDAMAGE ALERT! \ 443 1.5.2.2 skrll * The stupid chip uses the same size for every buffer, which \ 444 1.5.2.2 skrll * is set in the Receive Control register. We are using the 2K \ 445 1.5.2.2 skrll * size option, but what we REALLY want is (2K - 2)! For this \ 446 1.5.2.2 skrll * reason, we can't "scoot" packets longer than the standard \ 447 1.5.2.2 skrll * Ethernet MTU. On strict-alignment platforms, if the total \ 448 1.5.2.2 skrll * size exceeds (2K - 2) we set align_tweak to 0 and let \ 449 1.5.2.2 skrll * the upper layer copy the headers. \ 450 1.5.2.2 skrll */ \ 451 1.5.2.2 skrll __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 452 1.5.2.2 skrll \ 453 1.5.2.2 skrll __rxd->dr_baddrl = \ 454 1.5.2.2 skrll htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 455 1.5.2.2 skrll (sc)->sc_align_tweak); \ 456 1.5.2.2 skrll __rxd->dr_baddrh = 0; \ 457 1.5.2.2 skrll __rxd->dr_len = 0; \ 458 1.5.2.2 skrll __rxd->dr_cksum = 0; \ 459 1.5.2.2 skrll __rxd->dr_status = 0; \ 460 1.5.2.2 skrll __rxd->dr_errors = 0; \ 461 1.5.2.2 skrll __rxd->dr_special = 0; \ 462 1.5.2.2 skrll DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 463 1.5.2.2 skrll \ 464 1.5.2.2 skrll CSR_WRITE((sc), DGE_RDT, (x)); \ 465 1.5.2.2 skrll } while (/*CONSTCOND*/0) 466 1.5.2.2 skrll #endif 467 1.5.2.2 skrll 468 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 469 1.5.2.2 skrll /* 470 1.5.2.2 skrll * Allocation constants. Much memory may be used for this. 471 1.5.2.2 skrll */ 472 1.5.2.2 skrll #ifndef DGE_BUFFER_SIZE 473 1.5.2.2 skrll #define DGE_BUFFER_SIZE DGE_MAX_MTU 474 1.5.2.2 skrll #endif 475 1.5.2.2 skrll #define DGE_NBUFFERS (4*DGE_NRXDESC) 476 1.5.2.2 skrll #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 477 1.5.2.2 skrll 478 1.5.2.2 skrll struct rxbugentry { 479 1.5.2.2 skrll SLIST_ENTRY(rxbugentry) rb_entry; 480 1.5.2.2 skrll int rb_slot; 481 1.5.2.2 skrll }; 482 1.5.2.2 skrll 483 1.5.2.2 skrll static int 484 1.5.2.2 skrll dge_alloc_rcvmem(struct dge_softc *sc) 485 1.5.2.2 skrll { 486 1.5.2.2 skrll caddr_t ptr, kva; 487 1.5.2.2 skrll bus_dma_segment_t seg; 488 1.5.2.2 skrll int i, rseg, state, error; 489 1.5.2.2 skrll struct rxbugentry *entry; 490 1.5.2.2 skrll 491 1.5.2.2 skrll state = error = 0; 492 1.5.2.2 skrll 493 1.5.2.2 skrll if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 494 1.5.2.2 skrll &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 495 1.5.2.2 skrll printf("%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname); 496 1.5.2.2 skrll return ENOBUFS; 497 1.5.2.2 skrll } 498 1.5.2.2 skrll 499 1.5.2.2 skrll state = 1; 500 1.5.2.2 skrll if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, &kva, 501 1.5.2.2 skrll BUS_DMA_NOWAIT)) { 502 1.5.2.2 skrll printf("%s: can't map DMA buffers (%d bytes)\n", 503 1.5.2.2 skrll sc->sc_dev.dv_xname, (int)DGE_RXMEM); 504 1.5.2.2 skrll error = ENOBUFS; 505 1.5.2.2 skrll goto out; 506 1.5.2.2 skrll } 507 1.5.2.2 skrll 508 1.5.2.2 skrll state = 2; 509 1.5.2.2 skrll if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 510 1.5.2.2 skrll BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 511 1.5.2.2 skrll printf("%s: can't create DMA map\n", sc->sc_dev.dv_xname); 512 1.5.2.2 skrll error = ENOBUFS; 513 1.5.2.2 skrll goto out; 514 1.5.2.2 skrll } 515 1.5.2.2 skrll 516 1.5.2.2 skrll state = 3; 517 1.5.2.2 skrll if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 518 1.5.2.2 skrll kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 519 1.5.2.2 skrll printf("%s: can't load DMA map\n", sc->sc_dev.dv_xname); 520 1.5.2.2 skrll error = ENOBUFS; 521 1.5.2.2 skrll goto out; 522 1.5.2.2 skrll } 523 1.5.2.2 skrll 524 1.5.2.2 skrll state = 4; 525 1.5.2.2 skrll sc->sc_bugbuf = (caddr_t)kva; 526 1.5.2.2 skrll SLIST_INIT(&sc->sc_buglist); 527 1.5.2.2 skrll 528 1.5.2.2 skrll /* 529 1.5.2.2 skrll * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 530 1.5.2.2 skrll * in an array. 531 1.5.2.2 skrll */ 532 1.5.2.2 skrll ptr = sc->sc_bugbuf; 533 1.5.2.2 skrll if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 534 1.5.2.2 skrll M_DEVBUF, M_NOWAIT)) == NULL) { 535 1.5.2.2 skrll error = ENOBUFS; 536 1.5.2.2 skrll goto out; 537 1.5.2.2 skrll } 538 1.5.2.2 skrll sc->sc_entry = entry; 539 1.5.2.2 skrll for (i = 0; i < DGE_NBUFFERS; i++) { 540 1.5.2.2 skrll entry[i].rb_slot = i; 541 1.5.2.2 skrll SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 542 1.5.2.2 skrll } 543 1.5.2.2 skrll out: 544 1.5.2.2 skrll if (error != 0) { 545 1.5.2.2 skrll switch (state) { 546 1.5.2.2 skrll case 4: 547 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 548 1.5.2.2 skrll case 3: 549 1.5.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 550 1.5.2.2 skrll case 2: 551 1.5.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 552 1.5.2.2 skrll case 1: 553 1.5.2.2 skrll bus_dmamem_free(sc->sc_dmat, &seg, rseg); 554 1.5.2.2 skrll break; 555 1.5.2.2 skrll default: 556 1.5.2.2 skrll break; 557 1.5.2.2 skrll } 558 1.5.2.2 skrll } 559 1.5.2.2 skrll 560 1.5.2.2 skrll return error; 561 1.5.2.2 skrll } 562 1.5.2.2 skrll 563 1.5.2.2 skrll /* 564 1.5.2.2 skrll * Allocate a jumbo buffer. 565 1.5.2.2 skrll */ 566 1.5.2.2 skrll static void * 567 1.5.2.2 skrll dge_getbuf(struct dge_softc *sc) 568 1.5.2.2 skrll { 569 1.5.2.2 skrll struct rxbugentry *entry; 570 1.5.2.2 skrll 571 1.5.2.2 skrll entry = SLIST_FIRST(&sc->sc_buglist); 572 1.5.2.2 skrll 573 1.5.2.2 skrll if (entry == NULL) { 574 1.5.2.2 skrll printf("%s: no free RX buffers\n", sc->sc_dev.dv_xname); 575 1.5.2.2 skrll return(NULL); 576 1.5.2.2 skrll } 577 1.5.2.2 skrll 578 1.5.2.2 skrll SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 579 1.5.2.2 skrll return sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 580 1.5.2.2 skrll } 581 1.5.2.2 skrll 582 1.5.2.2 skrll /* 583 1.5.2.2 skrll * Release a jumbo buffer. 584 1.5.2.2 skrll */ 585 1.5.2.2 skrll static void 586 1.5.2.2 skrll dge_freebuf(struct mbuf *m, caddr_t buf, size_t size, void *arg) 587 1.5.2.2 skrll { 588 1.5.2.2 skrll struct rxbugentry *entry; 589 1.5.2.2 skrll struct dge_softc *sc; 590 1.5.2.2 skrll int i, s; 591 1.5.2.2 skrll 592 1.5.2.2 skrll /* Extract the softc struct pointer. */ 593 1.5.2.2 skrll sc = (struct dge_softc *)arg; 594 1.5.2.2 skrll 595 1.5.2.2 skrll if (sc == NULL) 596 1.5.2.2 skrll panic("dge_freebuf: can't find softc pointer!"); 597 1.5.2.2 skrll 598 1.5.2.2 skrll /* calculate the slot this buffer belongs to */ 599 1.5.2.2 skrll 600 1.5.2.2 skrll i = (buf - sc->sc_bugbuf) / DGE_BUFFER_SIZE; 601 1.5.2.2 skrll 602 1.5.2.2 skrll if ((i < 0) || (i >= DGE_NBUFFERS)) 603 1.5.2.2 skrll panic("dge_freebuf: asked to free buffer %d!", i); 604 1.5.2.2 skrll 605 1.5.2.2 skrll s = splvm(); 606 1.5.2.2 skrll entry = sc->sc_entry + i; 607 1.5.2.2 skrll SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 608 1.5.2.2 skrll 609 1.5.2.2 skrll if (__predict_true(m != NULL)) 610 1.5.2.2 skrll pool_cache_put(&mbpool_cache, m); 611 1.5.2.2 skrll splx(s); 612 1.5.2.2 skrll } 613 1.5.2.2 skrll #endif 614 1.5.2.2 skrll 615 1.5.2.2 skrll static void dge_start(struct ifnet *); 616 1.5.2.2 skrll static void dge_watchdog(struct ifnet *); 617 1.5.2.2 skrll static int dge_ioctl(struct ifnet *, u_long, caddr_t); 618 1.5.2.2 skrll static int dge_init(struct ifnet *); 619 1.5.2.2 skrll static void dge_stop(struct ifnet *, int); 620 1.5.2.2 skrll 621 1.5.2.2 skrll static void dge_shutdown(void *); 622 1.5.2.2 skrll 623 1.5.2.2 skrll static void dge_reset(struct dge_softc *); 624 1.5.2.2 skrll static void dge_rxdrain(struct dge_softc *); 625 1.5.2.2 skrll static int dge_add_rxbuf(struct dge_softc *, int); 626 1.5.2.2 skrll 627 1.5.2.2 skrll static void dge_set_filter(struct dge_softc *); 628 1.5.2.2 skrll 629 1.5.2.2 skrll static int dge_intr(void *); 630 1.5.2.2 skrll static void dge_txintr(struct dge_softc *); 631 1.5.2.2 skrll static void dge_rxintr(struct dge_softc *); 632 1.5.2.2 skrll static void dge_linkintr(struct dge_softc *, uint32_t); 633 1.5.2.2 skrll 634 1.5.2.2 skrll static int dge_match(struct device *, struct cfdata *, void *); 635 1.5.2.2 skrll static void dge_attach(struct device *, struct device *, void *); 636 1.5.2.2 skrll 637 1.5.2.2 skrll static int dge_read_eeprom(struct dge_softc *sc); 638 1.5.2.2 skrll static int dge_eeprom_clockin(struct dge_softc *sc); 639 1.5.2.2 skrll static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 640 1.5.2.2 skrll static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 641 1.5.2.2 skrll static int dge_xgmii_mediachange(struct ifnet *); 642 1.5.2.2 skrll static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 643 1.5.2.2 skrll static void dge_xgmii_reset(struct dge_softc *); 644 1.5.2.2 skrll static void dge_xgmii_writereg(struct device *, int, int, int); 645 1.5.2.2 skrll 646 1.5.2.2 skrll 647 1.5.2.2 skrll CFATTACH_DECL(dge, sizeof(struct dge_softc), 648 1.5.2.2 skrll dge_match, dge_attach, NULL, NULL); 649 1.5.2.2 skrll 650 1.5.2.2 skrll #ifdef DGE_EVENT_COUNTERS 651 1.5.2.2 skrll #if DGE_NTXSEGS > 100 652 1.5.2.2 skrll #error Update dge_txseg_evcnt_names 653 1.5.2.2 skrll #endif 654 1.5.2.2 skrll static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 655 1.5.2.2 skrll #endif /* DGE_EVENT_COUNTERS */ 656 1.5.2.2 skrll 657 1.5.2.2 skrll static int 658 1.5.2.2 skrll dge_match(struct device *parent, struct cfdata *cf, void *aux) 659 1.5.2.2 skrll { 660 1.5.2.2 skrll struct pci_attach_args *pa = aux; 661 1.5.2.2 skrll 662 1.5.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 663 1.5.2.2 skrll PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82597EX) 664 1.5.2.2 skrll return (1); 665 1.5.2.2 skrll 666 1.5.2.2 skrll return (0); 667 1.5.2.2 skrll } 668 1.5.2.2 skrll 669 1.5.2.2 skrll static void 670 1.5.2.2 skrll dge_attach(struct device *parent, struct device *self, void *aux) 671 1.5.2.2 skrll { 672 1.5.2.2 skrll struct dge_softc *sc = (void *) self; 673 1.5.2.2 skrll struct pci_attach_args *pa = aux; 674 1.5.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 675 1.5.2.2 skrll pci_chipset_tag_t pc = pa->pa_pc; 676 1.5.2.2 skrll pci_intr_handle_t ih; 677 1.5.2.2 skrll const char *intrstr = NULL; 678 1.5.2.2 skrll bus_dma_segment_t seg; 679 1.5.2.2 skrll int i, rseg, error; 680 1.5.2.2 skrll uint8_t enaddr[ETHER_ADDR_LEN]; 681 1.5.2.2 skrll pcireg_t preg, memtype; 682 1.5.2.2 skrll uint32_t reg; 683 1.5.2.2 skrll 684 1.5.2.2 skrll sc->sc_dmat = pa->pa_dmat; 685 1.5.2.2 skrll sc->sc_pc = pa->pa_pc; 686 1.5.2.2 skrll sc->sc_pt = pa->pa_tag; 687 1.5.2.2 skrll 688 1.5.2.2 skrll preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 689 1.5.2.2 skrll aprint_naive(": Ethernet controller\n"); 690 1.5.2.2 skrll aprint_normal(": Intel i82597EX 10GbE-LR Ethernet, rev. %d\n", preg); 691 1.5.2.2 skrll 692 1.5.2.2 skrll memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 693 1.5.2.2 skrll if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 694 1.5.2.2 skrll &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 695 1.5.2.2 skrll aprint_error("%s: unable to map device registers\n", 696 1.5.2.2 skrll sc->sc_dev.dv_xname); 697 1.5.2.2 skrll return; 698 1.5.2.2 skrll } 699 1.5.2.2 skrll 700 1.5.2.2 skrll /* Enable bus mastering */ 701 1.5.2.2 skrll preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 702 1.5.2.2 skrll preg |= PCI_COMMAND_MASTER_ENABLE; 703 1.5.2.2 skrll pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 704 1.5.2.2 skrll 705 1.5.2.2 skrll /* 706 1.5.2.2 skrll * Map and establish our interrupt. 707 1.5.2.2 skrll */ 708 1.5.2.2 skrll if (pci_intr_map(pa, &ih)) { 709 1.5.2.2 skrll aprint_error("%s: unable to map interrupt\n", 710 1.5.2.2 skrll sc->sc_dev.dv_xname); 711 1.5.2.2 skrll return; 712 1.5.2.2 skrll } 713 1.5.2.2 skrll intrstr = pci_intr_string(pc, ih); 714 1.5.2.2 skrll sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 715 1.5.2.2 skrll if (sc->sc_ih == NULL) { 716 1.5.2.2 skrll aprint_error("%s: unable to establish interrupt", 717 1.5.2.2 skrll sc->sc_dev.dv_xname); 718 1.5.2.2 skrll if (intrstr != NULL) 719 1.5.2.2 skrll aprint_normal(" at %s", intrstr); 720 1.5.2.2 skrll aprint_normal("\n"); 721 1.5.2.2 skrll return; 722 1.5.2.2 skrll } 723 1.5.2.2 skrll aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 724 1.5.2.2 skrll 725 1.5.2.2 skrll /* 726 1.5.2.2 skrll * Determine a few things about the bus we're connected to. 727 1.5.2.2 skrll */ 728 1.5.2.2 skrll reg = CSR_READ(sc, DGE_STATUS); 729 1.5.2.2 skrll if (reg & STATUS_BUS64) 730 1.5.2.2 skrll sc->sc_flags |= DGE_F_BUS64; 731 1.5.2.2 skrll 732 1.5.2.2 skrll sc->sc_flags |= DGE_F_PCIX; 733 1.5.2.2 skrll if (pci_get_capability(pa->pa_pc, pa->pa_tag, 734 1.5.2.2 skrll PCI_CAP_PCIX, 735 1.5.2.2 skrll &sc->sc_pcix_offset, NULL) == 0) 736 1.5.2.2 skrll aprint_error("%s: unable to find PCIX " 737 1.5.2.2 skrll "capability\n", sc->sc_dev.dv_xname); 738 1.5.2.2 skrll 739 1.5.2.2 skrll if (sc->sc_flags & DGE_F_PCIX) { 740 1.5.2.2 skrll switch (reg & STATUS_PCIX_MSK) { 741 1.5.2.2 skrll case STATUS_PCIX_66: 742 1.5.2.2 skrll sc->sc_bus_speed = 66; 743 1.5.2.2 skrll break; 744 1.5.2.2 skrll case STATUS_PCIX_100: 745 1.5.2.2 skrll sc->sc_bus_speed = 100; 746 1.5.2.2 skrll break; 747 1.5.2.2 skrll case STATUS_PCIX_133: 748 1.5.2.2 skrll sc->sc_bus_speed = 133; 749 1.5.2.2 skrll break; 750 1.5.2.2 skrll default: 751 1.5.2.2 skrll aprint_error( 752 1.5.2.2 skrll "%s: unknown PCIXSPD %d; assuming 66MHz\n", 753 1.5.2.2 skrll sc->sc_dev.dv_xname, 754 1.5.2.2 skrll reg & STATUS_PCIX_MSK); 755 1.5.2.2 skrll sc->sc_bus_speed = 66; 756 1.5.2.2 skrll } 757 1.5.2.2 skrll } else 758 1.5.2.2 skrll sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 759 1.5.2.2 skrll aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 760 1.5.2.2 skrll (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 761 1.5.2.2 skrll (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 762 1.5.2.2 skrll 763 1.5.2.2 skrll /* 764 1.5.2.2 skrll * Allocate the control data structures, and create and load the 765 1.5.2.2 skrll * DMA map for it. 766 1.5.2.2 skrll */ 767 1.5.2.2 skrll if ((error = bus_dmamem_alloc(sc->sc_dmat, 768 1.5.2.2 skrll sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 769 1.5.2.2 skrll 0)) != 0) { 770 1.5.2.2 skrll aprint_error( 771 1.5.2.2 skrll "%s: unable to allocate control data, error = %d\n", 772 1.5.2.2 skrll sc->sc_dev.dv_xname, error); 773 1.5.2.2 skrll goto fail_0; 774 1.5.2.2 skrll } 775 1.5.2.2 skrll 776 1.5.2.2 skrll if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 777 1.5.2.2 skrll sizeof(struct dge_control_data), (caddr_t *)&sc->sc_control_data, 778 1.5.2.2 skrll 0)) != 0) { 779 1.5.2.2 skrll aprint_error("%s: unable to map control data, error = %d\n", 780 1.5.2.2 skrll sc->sc_dev.dv_xname, error); 781 1.5.2.2 skrll goto fail_1; 782 1.5.2.2 skrll } 783 1.5.2.2 skrll 784 1.5.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, 785 1.5.2.2 skrll sizeof(struct dge_control_data), 1, 786 1.5.2.2 skrll sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 787 1.5.2.2 skrll aprint_error("%s: unable to create control data DMA map, " 788 1.5.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, error); 789 1.5.2.2 skrll goto fail_2; 790 1.5.2.2 skrll } 791 1.5.2.2 skrll 792 1.5.2.2 skrll if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 793 1.5.2.2 skrll sc->sc_control_data, sizeof(struct dge_control_data), NULL, 794 1.5.2.2 skrll 0)) != 0) { 795 1.5.2.2 skrll aprint_error( 796 1.5.2.2 skrll "%s: unable to load control data DMA map, error = %d\n", 797 1.5.2.2 skrll sc->sc_dev.dv_xname, error); 798 1.5.2.2 skrll goto fail_3; 799 1.5.2.2 skrll } 800 1.5.2.2 skrll 801 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 802 1.5.2.2 skrll if (dge_alloc_rcvmem(sc) != 0) 803 1.5.2.2 skrll return; /* Already complained */ 804 1.5.2.2 skrll #endif 805 1.5.2.2 skrll /* 806 1.5.2.2 skrll * Create the transmit buffer DMA maps. 807 1.5.2.2 skrll */ 808 1.5.2.2 skrll for (i = 0; i < DGE_TXQUEUELEN; i++) { 809 1.5.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 810 1.5.2.2 skrll DGE_NTXSEGS, MCLBYTES, 0, 0, 811 1.5.2.2 skrll &sc->sc_txsoft[i].txs_dmamap)) != 0) { 812 1.5.2.2 skrll aprint_error("%s: unable to create Tx DMA map %d, " 813 1.5.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, i, error); 814 1.5.2.2 skrll goto fail_4; 815 1.5.2.2 skrll } 816 1.5.2.2 skrll } 817 1.5.2.2 skrll 818 1.5.2.2 skrll /* 819 1.5.2.2 skrll * Create the receive buffer DMA maps. 820 1.5.2.2 skrll */ 821 1.5.2.2 skrll for (i = 0; i < DGE_NRXDESC; i++) { 822 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 823 1.5.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 824 1.5.2.2 skrll DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 825 1.5.2.2 skrll #else 826 1.5.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 827 1.5.2.2 skrll MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 828 1.5.2.2 skrll #endif 829 1.5.2.2 skrll aprint_error("%s: unable to create Rx DMA map %d, " 830 1.5.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, i, error); 831 1.5.2.2 skrll goto fail_5; 832 1.5.2.2 skrll } 833 1.5.2.2 skrll sc->sc_rxsoft[i].rxs_mbuf = NULL; 834 1.5.2.2 skrll } 835 1.5.2.2 skrll 836 1.5.2.2 skrll /* 837 1.5.2.2 skrll * Set bits in ctrl0 register. 838 1.5.2.2 skrll * Should get the software defined pins out of EEPROM? 839 1.5.2.2 skrll */ 840 1.5.2.2 skrll sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 841 1.5.2.2 skrll sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 842 1.5.2.2 skrll CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 843 1.5.2.2 skrll 844 1.5.2.2 skrll /* 845 1.5.2.2 skrll * Reset the chip to a known state. 846 1.5.2.2 skrll */ 847 1.5.2.2 skrll dge_reset(sc); 848 1.5.2.2 skrll 849 1.5.2.2 skrll /* 850 1.5.2.2 skrll * Reset the PHY. 851 1.5.2.2 skrll */ 852 1.5.2.2 skrll dge_xgmii_reset(sc); 853 1.5.2.2 skrll 854 1.5.2.2 skrll /* 855 1.5.2.2 skrll * Read in EEPROM data. 856 1.5.2.2 skrll */ 857 1.5.2.2 skrll if (dge_read_eeprom(sc)) { 858 1.5.2.2 skrll aprint_error("%s: couldn't read EEPROM\n", sc->sc_dev.dv_xname); 859 1.5.2.2 skrll return; 860 1.5.2.2 skrll } 861 1.5.2.2 skrll 862 1.5.2.2 skrll /* 863 1.5.2.2 skrll * Get the ethernet address. 864 1.5.2.2 skrll */ 865 1.5.2.2 skrll enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 866 1.5.2.2 skrll enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 867 1.5.2.2 skrll enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 868 1.5.2.2 skrll enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 869 1.5.2.2 skrll enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 870 1.5.2.2 skrll enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 871 1.5.2.2 skrll 872 1.5.2.2 skrll aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 873 1.5.2.2 skrll ether_sprintf(enaddr)); 874 1.5.2.2 skrll 875 1.5.2.2 skrll /* 876 1.5.2.2 skrll * Setup media stuff. 877 1.5.2.2 skrll */ 878 1.5.2.2 skrll ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 879 1.5.2.2 skrll dge_xgmii_mediastatus); 880 1.5.2.2 skrll ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 881 1.5.2.2 skrll ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 882 1.5.2.2 skrll 883 1.5.2.2 skrll ifp = &sc->sc_ethercom.ec_if; 884 1.5.2.2 skrll strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 885 1.5.2.2 skrll ifp->if_softc = sc; 886 1.5.2.2 skrll ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 887 1.5.2.2 skrll ifp->if_ioctl = dge_ioctl; 888 1.5.2.2 skrll ifp->if_start = dge_start; 889 1.5.2.2 skrll ifp->if_watchdog = dge_watchdog; 890 1.5.2.2 skrll ifp->if_init = dge_init; 891 1.5.2.2 skrll ifp->if_stop = dge_stop; 892 1.5.2.2 skrll IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 893 1.5.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 894 1.5.2.2 skrll 895 1.5.2.2 skrll sc->sc_ethercom.ec_capabilities |= 896 1.5.2.2 skrll ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 897 1.5.2.2 skrll 898 1.5.2.2 skrll /* 899 1.5.2.2 skrll * We can perform TCPv4 and UDPv4 checkums in-bound. 900 1.5.2.2 skrll */ 901 1.5.2.2 skrll ifp->if_capabilities |= 902 1.5.2.2 skrll IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 903 1.5.2.2 skrll 904 1.5.2.2 skrll /* 905 1.5.2.2 skrll * Attach the interface. 906 1.5.2.2 skrll */ 907 1.5.2.2 skrll if_attach(ifp); 908 1.5.2.2 skrll ether_ifattach(ifp, enaddr); 909 1.5.2.2 skrll #if NRND > 0 910 1.5.2.2 skrll rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 911 1.5.2.2 skrll RND_TYPE_NET, 0); 912 1.5.2.2 skrll #endif 913 1.5.2.2 skrll 914 1.5.2.2 skrll #ifdef DGE_EVENT_COUNTERS 915 1.5.2.2 skrll /* Fix segment event naming */ 916 1.5.2.2 skrll if (dge_txseg_evcnt_names == NULL) { 917 1.5.2.2 skrll dge_txseg_evcnt_names = 918 1.5.2.2 skrll malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 919 1.5.2.2 skrll for (i = 0; i < DGE_NTXSEGS; i++) 920 1.5.2.2 skrll snprintf((*dge_txseg_evcnt_names)[i], 921 1.5.2.2 skrll sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 922 1.5.2.2 skrll } 923 1.5.2.2 skrll 924 1.5.2.2 skrll /* Attach event counters. */ 925 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 926 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txsstall"); 927 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 928 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txdstall"); 929 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 930 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txforceintr"); 931 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 932 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txdw"); 933 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 934 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txqe"); 935 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 936 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "rxintr"); 937 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 938 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "linkintr"); 939 1.5.2.2 skrll 940 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 941 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "rxipsum"); 942 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 943 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "rxtusum"); 944 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 945 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txipsum"); 946 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 947 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txtusum"); 948 1.5.2.2 skrll 949 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 950 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txctx init"); 951 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 952 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txctx hit"); 953 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 954 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txctx miss"); 955 1.5.2.2 skrll 956 1.5.2.2 skrll for (i = 0; i < DGE_NTXSEGS; i++) 957 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 958 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, (*dge_txseg_evcnt_names)[i]); 959 1.5.2.2 skrll 960 1.5.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 961 1.5.2.2 skrll NULL, sc->sc_dev.dv_xname, "txdrop"); 962 1.5.2.2 skrll 963 1.5.2.2 skrll #endif /* DGE_EVENT_COUNTERS */ 964 1.5.2.2 skrll 965 1.5.2.2 skrll /* 966 1.5.2.2 skrll * Make sure the interface is shutdown during reboot. 967 1.5.2.2 skrll */ 968 1.5.2.2 skrll sc->sc_sdhook = shutdownhook_establish(dge_shutdown, sc); 969 1.5.2.2 skrll if (sc->sc_sdhook == NULL) 970 1.5.2.2 skrll aprint_error("%s: WARNING: unable to establish shutdown hook\n", 971 1.5.2.2 skrll sc->sc_dev.dv_xname); 972 1.5.2.2 skrll return; 973 1.5.2.2 skrll 974 1.5.2.2 skrll /* 975 1.5.2.2 skrll * Free any resources we've allocated during the failed attach 976 1.5.2.2 skrll * attempt. Do this in reverse order and fall through. 977 1.5.2.2 skrll */ 978 1.5.2.2 skrll fail_5: 979 1.5.2.2 skrll for (i = 0; i < DGE_NRXDESC; i++) { 980 1.5.2.2 skrll if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 981 1.5.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, 982 1.5.2.2 skrll sc->sc_rxsoft[i].rxs_dmamap); 983 1.5.2.2 skrll } 984 1.5.2.2 skrll fail_4: 985 1.5.2.2 skrll for (i = 0; i < DGE_TXQUEUELEN; i++) { 986 1.5.2.2 skrll if (sc->sc_txsoft[i].txs_dmamap != NULL) 987 1.5.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, 988 1.5.2.2 skrll sc->sc_txsoft[i].txs_dmamap); 989 1.5.2.2 skrll } 990 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 991 1.5.2.2 skrll fail_3: 992 1.5.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 993 1.5.2.2 skrll fail_2: 994 1.5.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 995 1.5.2.2 skrll sizeof(struct dge_control_data)); 996 1.5.2.2 skrll fail_1: 997 1.5.2.2 skrll bus_dmamem_free(sc->sc_dmat, &seg, rseg); 998 1.5.2.2 skrll fail_0: 999 1.5.2.2 skrll return; 1000 1.5.2.2 skrll } 1001 1.5.2.2 skrll 1002 1.5.2.2 skrll /* 1003 1.5.2.2 skrll * dge_shutdown: 1004 1.5.2.2 skrll * 1005 1.5.2.2 skrll * Make sure the interface is stopped at reboot time. 1006 1.5.2.2 skrll */ 1007 1.5.2.2 skrll static void 1008 1.5.2.2 skrll dge_shutdown(void *arg) 1009 1.5.2.2 skrll { 1010 1.5.2.2 skrll struct dge_softc *sc = arg; 1011 1.5.2.2 skrll 1012 1.5.2.2 skrll dge_stop(&sc->sc_ethercom.ec_if, 1); 1013 1.5.2.2 skrll } 1014 1.5.2.2 skrll 1015 1.5.2.2 skrll /* 1016 1.5.2.2 skrll * dge_tx_cksum: 1017 1.5.2.2 skrll * 1018 1.5.2.2 skrll * Set up TCP/IP checksumming parameters for the 1019 1.5.2.2 skrll * specified packet. 1020 1.5.2.2 skrll */ 1021 1.5.2.2 skrll static int 1022 1.5.2.2 skrll dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1023 1.5.2.2 skrll { 1024 1.5.2.2 skrll struct mbuf *m0 = txs->txs_mbuf; 1025 1.5.2.2 skrll struct dge_ctdes *t; 1026 1.5.2.2 skrll uint32_t ipcs, tucs; 1027 1.5.2.2 skrll struct ip *ip; 1028 1.5.2.2 skrll struct ether_header *eh; 1029 1.5.2.2 skrll int offset, iphl; 1030 1.5.2.2 skrll uint8_t fields = 0; 1031 1.5.2.2 skrll 1032 1.5.2.2 skrll /* 1033 1.5.2.2 skrll * XXX It would be nice if the mbuf pkthdr had offset 1034 1.5.2.2 skrll * fields for the protocol headers. 1035 1.5.2.2 skrll */ 1036 1.5.2.2 skrll 1037 1.5.2.2 skrll eh = mtod(m0, struct ether_header *); 1038 1.5.2.2 skrll switch (htons(eh->ether_type)) { 1039 1.5.2.2 skrll case ETHERTYPE_IP: 1040 1.5.2.2 skrll iphl = sizeof(struct ip); 1041 1.5.2.2 skrll offset = ETHER_HDR_LEN; 1042 1.5.2.2 skrll break; 1043 1.5.2.2 skrll 1044 1.5.2.2 skrll case ETHERTYPE_VLAN: 1045 1.5.2.2 skrll iphl = sizeof(struct ip); 1046 1.5.2.2 skrll offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1047 1.5.2.2 skrll break; 1048 1.5.2.2 skrll 1049 1.5.2.2 skrll default: 1050 1.5.2.2 skrll /* 1051 1.5.2.2 skrll * Don't support this protocol or encapsulation. 1052 1.5.2.2 skrll */ 1053 1.5.2.2 skrll *fieldsp = 0; 1054 1.5.2.2 skrll return (0); 1055 1.5.2.2 skrll } 1056 1.5.2.2 skrll 1057 1.5.2.2 skrll if (m0->m_len < (offset + iphl)) { 1058 1.5.2.2 skrll if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1059 1.5.2.2 skrll printf("%s: dge_tx_cksum: mbuf allocation failed, " 1060 1.5.2.2 skrll "packet dropped\n", sc->sc_dev.dv_xname); 1061 1.5.2.2 skrll return (ENOMEM); 1062 1.5.2.2 skrll } 1063 1.5.2.2 skrll m0 = txs->txs_mbuf; 1064 1.5.2.2 skrll } 1065 1.5.2.2 skrll 1066 1.5.2.2 skrll ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1067 1.5.2.2 skrll iphl = ip->ip_hl << 2; 1068 1.5.2.2 skrll 1069 1.5.2.2 skrll /* 1070 1.5.2.2 skrll * NOTE: Even if we're not using the IP or TCP/UDP checksum 1071 1.5.2.2 skrll * offload feature, if we load the context descriptor, we 1072 1.5.2.2 skrll * MUST provide valid values for IPCSS and TUCSS fields. 1073 1.5.2.2 skrll */ 1074 1.5.2.2 skrll 1075 1.5.2.2 skrll if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1076 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1077 1.5.2.2 skrll fields |= TDESC_POPTS_IXSM; 1078 1.5.2.2 skrll ipcs = DGE_TCPIP_IPCSS(offset) | 1079 1.5.2.2 skrll DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1080 1.5.2.2 skrll DGE_TCPIP_IPCSE(offset + iphl - 1); 1081 1.5.2.2 skrll } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1082 1.5.2.2 skrll /* Use the cached value. */ 1083 1.5.2.2 skrll ipcs = sc->sc_txctx_ipcs; 1084 1.5.2.2 skrll } else { 1085 1.5.2.2 skrll /* Just initialize it to the likely value anyway. */ 1086 1.5.2.2 skrll ipcs = DGE_TCPIP_IPCSS(offset) | 1087 1.5.2.2 skrll DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1088 1.5.2.2 skrll DGE_TCPIP_IPCSE(offset + iphl - 1); 1089 1.5.2.2 skrll } 1090 1.5.2.2 skrll DPRINTF(DGE_DEBUG_CKSUM, 1091 1.5.2.2 skrll ("%s: CKSUM: offset %d ipcs 0x%x\n", 1092 1.5.2.2 skrll sc->sc_dev.dv_xname, offset, ipcs)); 1093 1.5.2.2 skrll 1094 1.5.2.2 skrll offset += iphl; 1095 1.5.2.2 skrll 1096 1.5.2.2 skrll if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1097 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1098 1.5.2.2 skrll fields |= TDESC_POPTS_TXSM; 1099 1.5.2.2 skrll tucs = DGE_TCPIP_TUCSS(offset) | 1100 1.5.2.2 skrll DGE_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1101 1.5.2.2 skrll DGE_TCPIP_TUCSE(0) /* rest of packet */; 1102 1.5.2.2 skrll } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1103 1.5.2.2 skrll /* Use the cached value. */ 1104 1.5.2.2 skrll tucs = sc->sc_txctx_tucs; 1105 1.5.2.2 skrll } else { 1106 1.5.2.2 skrll /* Just initialize it to a valid TCP context. */ 1107 1.5.2.2 skrll tucs = DGE_TCPIP_TUCSS(offset) | 1108 1.5.2.2 skrll DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1109 1.5.2.2 skrll DGE_TCPIP_TUCSE(0) /* rest of packet */; 1110 1.5.2.2 skrll } 1111 1.5.2.2 skrll 1112 1.5.2.2 skrll DPRINTF(DGE_DEBUG_CKSUM, 1113 1.5.2.2 skrll ("%s: CKSUM: offset %d tucs 0x%x\n", 1114 1.5.2.2 skrll sc->sc_dev.dv_xname, offset, tucs)); 1115 1.5.2.2 skrll 1116 1.5.2.2 skrll if (sc->sc_txctx_ipcs == ipcs && 1117 1.5.2.2 skrll sc->sc_txctx_tucs == tucs) { 1118 1.5.2.2 skrll /* Cached context is fine. */ 1119 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1120 1.5.2.2 skrll } else { 1121 1.5.2.2 skrll /* Fill in the context descriptor. */ 1122 1.5.2.2 skrll #ifdef DGE_EVENT_COUNTERS 1123 1.5.2.2 skrll if (sc->sc_txctx_ipcs == 0xffffffff && 1124 1.5.2.2 skrll sc->sc_txctx_tucs == 0xffffffff) 1125 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1126 1.5.2.2 skrll else 1127 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1128 1.5.2.2 skrll #endif 1129 1.5.2.2 skrll t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1130 1.5.2.2 skrll t->dc_tcpip_ipcs = htole32(ipcs); 1131 1.5.2.2 skrll t->dc_tcpip_tucs = htole32(tucs); 1132 1.5.2.2 skrll t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1133 1.5.2.2 skrll t->dc_tcpip_seg = 0; 1134 1.5.2.2 skrll DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1135 1.5.2.2 skrll 1136 1.5.2.2 skrll sc->sc_txctx_ipcs = ipcs; 1137 1.5.2.2 skrll sc->sc_txctx_tucs = tucs; 1138 1.5.2.2 skrll 1139 1.5.2.2 skrll sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1140 1.5.2.2 skrll txs->txs_ndesc++; 1141 1.5.2.2 skrll } 1142 1.5.2.2 skrll 1143 1.5.2.2 skrll *fieldsp = fields; 1144 1.5.2.2 skrll 1145 1.5.2.2 skrll return (0); 1146 1.5.2.2 skrll } 1147 1.5.2.2 skrll 1148 1.5.2.2 skrll /* 1149 1.5.2.2 skrll * dge_start: [ifnet interface function] 1150 1.5.2.2 skrll * 1151 1.5.2.2 skrll * Start packet transmission on the interface. 1152 1.5.2.2 skrll */ 1153 1.5.2.2 skrll static void 1154 1.5.2.2 skrll dge_start(struct ifnet *ifp) 1155 1.5.2.2 skrll { 1156 1.5.2.2 skrll struct dge_softc *sc = ifp->if_softc; 1157 1.5.2.2 skrll struct mbuf *m0; 1158 1.5.2.2 skrll struct dge_txsoft *txs; 1159 1.5.2.2 skrll bus_dmamap_t dmamap; 1160 1.5.2.2 skrll int error, nexttx, lasttx = -1, ofree, seg; 1161 1.5.2.2 skrll uint32_t cksumcmd; 1162 1.5.2.2 skrll uint8_t cksumfields; 1163 1.5.2.2 skrll 1164 1.5.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1165 1.5.2.2 skrll return; 1166 1.5.2.2 skrll 1167 1.5.2.2 skrll /* 1168 1.5.2.2 skrll * Remember the previous number of free descriptors. 1169 1.5.2.2 skrll */ 1170 1.5.2.2 skrll ofree = sc->sc_txfree; 1171 1.5.2.2 skrll 1172 1.5.2.2 skrll /* 1173 1.5.2.2 skrll * Loop through the send queue, setting up transmit descriptors 1174 1.5.2.2 skrll * until we drain the queue, or use up all available transmit 1175 1.5.2.2 skrll * descriptors. 1176 1.5.2.2 skrll */ 1177 1.5.2.2 skrll for (;;) { 1178 1.5.2.2 skrll /* Grab a packet off the queue. */ 1179 1.5.2.2 skrll IFQ_POLL(&ifp->if_snd, m0); 1180 1.5.2.2 skrll if (m0 == NULL) 1181 1.5.2.2 skrll break; 1182 1.5.2.2 skrll 1183 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1184 1.5.2.2 skrll ("%s: TX: have packet to transmit: %p\n", 1185 1.5.2.2 skrll sc->sc_dev.dv_xname, m0)); 1186 1.5.2.2 skrll 1187 1.5.2.2 skrll /* Get a work queue entry. */ 1188 1.5.2.2 skrll if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1189 1.5.2.2 skrll dge_txintr(sc); 1190 1.5.2.2 skrll if (sc->sc_txsfree == 0) { 1191 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1192 1.5.2.2 skrll ("%s: TX: no free job descriptors\n", 1193 1.5.2.2 skrll sc->sc_dev.dv_xname)); 1194 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1195 1.5.2.2 skrll break; 1196 1.5.2.2 skrll } 1197 1.5.2.2 skrll } 1198 1.5.2.2 skrll 1199 1.5.2.2 skrll txs = &sc->sc_txsoft[sc->sc_txsnext]; 1200 1.5.2.2 skrll dmamap = txs->txs_dmamap; 1201 1.5.2.2 skrll 1202 1.5.2.2 skrll /* 1203 1.5.2.2 skrll * Load the DMA map. If this fails, the packet either 1204 1.5.2.2 skrll * didn't fit in the allotted number of segments, or we 1205 1.5.2.2 skrll * were short on resources. For the too-many-segments 1206 1.5.2.2 skrll * case, we simply report an error and drop the packet, 1207 1.5.2.2 skrll * since we can't sanely copy a jumbo packet to a single 1208 1.5.2.2 skrll * buffer. 1209 1.5.2.2 skrll */ 1210 1.5.2.2 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1211 1.5.2.2 skrll BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1212 1.5.2.2 skrll if (error) { 1213 1.5.2.2 skrll if (error == EFBIG) { 1214 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1215 1.5.2.2 skrll printf("%s: Tx packet consumes too many " 1216 1.5.2.2 skrll "DMA segments, dropping...\n", 1217 1.5.2.2 skrll sc->sc_dev.dv_xname); 1218 1.5.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m0); 1219 1.5.2.2 skrll m_freem(m0); 1220 1.5.2.2 skrll continue; 1221 1.5.2.2 skrll } 1222 1.5.2.2 skrll /* 1223 1.5.2.2 skrll * Short on resources, just stop for now. 1224 1.5.2.2 skrll */ 1225 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1226 1.5.2.2 skrll ("%s: TX: dmamap load failed: %d\n", 1227 1.5.2.2 skrll sc->sc_dev.dv_xname, error)); 1228 1.5.2.2 skrll break; 1229 1.5.2.2 skrll } 1230 1.5.2.2 skrll 1231 1.5.2.2 skrll /* 1232 1.5.2.2 skrll * Ensure we have enough descriptors free to describe 1233 1.5.2.2 skrll * the packet. Note, we always reserve one descriptor 1234 1.5.2.2 skrll * at the end of the ring due to the semantics of the 1235 1.5.2.2 skrll * TDT register, plus one more in the event we need 1236 1.5.2.2 skrll * to re-load checksum offload context. 1237 1.5.2.2 skrll */ 1238 1.5.2.2 skrll if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1239 1.5.2.2 skrll /* 1240 1.5.2.2 skrll * Not enough free descriptors to transmit this 1241 1.5.2.2 skrll * packet. We haven't committed anything yet, 1242 1.5.2.2 skrll * so just unload the DMA map, put the packet 1243 1.5.2.2 skrll * pack on the queue, and punt. Notify the upper 1244 1.5.2.2 skrll * layer that there are no more slots left. 1245 1.5.2.2 skrll */ 1246 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1247 1.5.2.2 skrll ("%s: TX: need %d descriptors, have %d\n", 1248 1.5.2.2 skrll sc->sc_dev.dv_xname, dmamap->dm_nsegs, 1249 1.5.2.2 skrll sc->sc_txfree - 1)); 1250 1.5.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 1251 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, dmamap); 1252 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1253 1.5.2.2 skrll break; 1254 1.5.2.2 skrll } 1255 1.5.2.2 skrll 1256 1.5.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m0); 1257 1.5.2.2 skrll 1258 1.5.2.2 skrll /* 1259 1.5.2.2 skrll * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1260 1.5.2.2 skrll */ 1261 1.5.2.2 skrll 1262 1.5.2.2 skrll /* Sync the DMA map. */ 1263 1.5.2.2 skrll bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1264 1.5.2.2 skrll BUS_DMASYNC_PREWRITE); 1265 1.5.2.2 skrll 1266 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1267 1.5.2.2 skrll ("%s: TX: packet has %d DMA segments\n", 1268 1.5.2.2 skrll sc->sc_dev.dv_xname, dmamap->dm_nsegs)); 1269 1.5.2.2 skrll 1270 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1271 1.5.2.2 skrll 1272 1.5.2.2 skrll /* 1273 1.5.2.2 skrll * Store a pointer to the packet so that we can free it 1274 1.5.2.2 skrll * later. 1275 1.5.2.2 skrll * 1276 1.5.2.2 skrll * Initially, we consider the number of descriptors the 1277 1.5.2.2 skrll * packet uses the number of DMA segments. This may be 1278 1.5.2.2 skrll * incremented by 1 if we do checksum offload (a descriptor 1279 1.5.2.2 skrll * is used to set the checksum context). 1280 1.5.2.2 skrll */ 1281 1.5.2.2 skrll txs->txs_mbuf = m0; 1282 1.5.2.2 skrll txs->txs_firstdesc = sc->sc_txnext; 1283 1.5.2.2 skrll txs->txs_ndesc = dmamap->dm_nsegs; 1284 1.5.2.2 skrll 1285 1.5.2.2 skrll /* 1286 1.5.2.2 skrll * Set up checksum offload parameters for 1287 1.5.2.2 skrll * this packet. 1288 1.5.2.2 skrll */ 1289 1.5.2.2 skrll if (m0->m_pkthdr.csum_flags & 1290 1.5.2.2 skrll (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1291 1.5.2.2 skrll if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1292 1.5.2.2 skrll /* Error message already displayed. */ 1293 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, dmamap); 1294 1.5.2.2 skrll continue; 1295 1.5.2.2 skrll } 1296 1.5.2.2 skrll } else { 1297 1.5.2.2 skrll cksumfields = 0; 1298 1.5.2.2 skrll } 1299 1.5.2.2 skrll 1300 1.5.2.2 skrll cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1301 1.5.2.2 skrll 1302 1.5.2.2 skrll /* 1303 1.5.2.2 skrll * Initialize the transmit descriptor. 1304 1.5.2.2 skrll */ 1305 1.5.2.2 skrll for (nexttx = sc->sc_txnext, seg = 0; 1306 1.5.2.2 skrll seg < dmamap->dm_nsegs; 1307 1.5.2.2 skrll seg++, nexttx = DGE_NEXTTX(nexttx)) { 1308 1.5.2.2 skrll /* 1309 1.5.2.2 skrll * Note: we currently only use 32-bit DMA 1310 1.5.2.2 skrll * addresses. 1311 1.5.2.2 skrll */ 1312 1.5.2.2 skrll sc->sc_txdescs[nexttx].dt_baddrh = 0; 1313 1.5.2.2 skrll sc->sc_txdescs[nexttx].dt_baddrl = 1314 1.5.2.2 skrll htole32(dmamap->dm_segs[seg].ds_addr); 1315 1.5.2.2 skrll sc->sc_txdescs[nexttx].dt_ctl = 1316 1.5.2.2 skrll htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1317 1.5.2.2 skrll sc->sc_txdescs[nexttx].dt_status = 0; 1318 1.5.2.2 skrll sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1319 1.5.2.2 skrll sc->sc_txdescs[nexttx].dt_vlan = 0; 1320 1.5.2.2 skrll lasttx = nexttx; 1321 1.5.2.2 skrll 1322 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1323 1.5.2.2 skrll ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1324 1.5.2.2 skrll sc->sc_dev.dv_xname, nexttx, 1325 1.5.2.2 skrll le32toh(dmamap->dm_segs[seg].ds_addr), 1326 1.5.2.2 skrll le32toh(dmamap->dm_segs[seg].ds_len))); 1327 1.5.2.2 skrll } 1328 1.5.2.2 skrll 1329 1.5.2.2 skrll KASSERT(lasttx != -1); 1330 1.5.2.2 skrll 1331 1.5.2.2 skrll /* 1332 1.5.2.2 skrll * Set up the command byte on the last descriptor of 1333 1.5.2.2 skrll * the packet. If we're in the interrupt delay window, 1334 1.5.2.2 skrll * delay the interrupt. 1335 1.5.2.2 skrll */ 1336 1.5.2.2 skrll sc->sc_txdescs[lasttx].dt_ctl |= 1337 1.5.2.2 skrll htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1338 1.5.2.2 skrll 1339 1.5.2.2 skrll txs->txs_lastdesc = lasttx; 1340 1.5.2.2 skrll 1341 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1342 1.5.2.2 skrll ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1343 1.5.2.2 skrll lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1344 1.5.2.2 skrll 1345 1.5.2.2 skrll /* Sync the descriptors we're using. */ 1346 1.5.2.2 skrll DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1347 1.5.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1348 1.5.2.2 skrll 1349 1.5.2.2 skrll /* Give the packet to the chip. */ 1350 1.5.2.2 skrll CSR_WRITE(sc, DGE_TDT, nexttx); 1351 1.5.2.2 skrll 1352 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1353 1.5.2.2 skrll ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1354 1.5.2.2 skrll 1355 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1356 1.5.2.2 skrll ("%s: TX: finished transmitting packet, job %d\n", 1357 1.5.2.2 skrll sc->sc_dev.dv_xname, sc->sc_txsnext)); 1358 1.5.2.2 skrll 1359 1.5.2.2 skrll /* Advance the tx pointer. */ 1360 1.5.2.2 skrll sc->sc_txfree -= txs->txs_ndesc; 1361 1.5.2.2 skrll sc->sc_txnext = nexttx; 1362 1.5.2.2 skrll 1363 1.5.2.2 skrll sc->sc_txsfree--; 1364 1.5.2.2 skrll sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1365 1.5.2.2 skrll 1366 1.5.2.2 skrll #if NBPFILTER > 0 1367 1.5.2.2 skrll /* Pass the packet to any BPF listeners. */ 1368 1.5.2.2 skrll if (ifp->if_bpf) 1369 1.5.2.2 skrll bpf_mtap(ifp->if_bpf, m0); 1370 1.5.2.2 skrll #endif /* NBPFILTER > 0 */ 1371 1.5.2.2 skrll } 1372 1.5.2.2 skrll 1373 1.5.2.2 skrll if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1374 1.5.2.2 skrll /* No more slots; notify upper layer. */ 1375 1.5.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 1376 1.5.2.2 skrll } 1377 1.5.2.2 skrll 1378 1.5.2.2 skrll if (sc->sc_txfree != ofree) { 1379 1.5.2.2 skrll /* Set a watchdog timer in case the chip flakes out. */ 1380 1.5.2.2 skrll ifp->if_timer = 5; 1381 1.5.2.2 skrll } 1382 1.5.2.2 skrll } 1383 1.5.2.2 skrll 1384 1.5.2.2 skrll /* 1385 1.5.2.2 skrll * dge_watchdog: [ifnet interface function] 1386 1.5.2.2 skrll * 1387 1.5.2.2 skrll * Watchdog timer handler. 1388 1.5.2.2 skrll */ 1389 1.5.2.2 skrll static void 1390 1.5.2.2 skrll dge_watchdog(struct ifnet *ifp) 1391 1.5.2.2 skrll { 1392 1.5.2.2 skrll struct dge_softc *sc = ifp->if_softc; 1393 1.5.2.2 skrll 1394 1.5.2.2 skrll /* 1395 1.5.2.2 skrll * Since we're using delayed interrupts, sweep up 1396 1.5.2.2 skrll * before we report an error. 1397 1.5.2.2 skrll */ 1398 1.5.2.2 skrll dge_txintr(sc); 1399 1.5.2.2 skrll 1400 1.5.2.2 skrll if (sc->sc_txfree != DGE_NTXDESC) { 1401 1.5.2.2 skrll printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1402 1.5.2.2 skrll sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1403 1.5.2.2 skrll sc->sc_txnext); 1404 1.5.2.2 skrll ifp->if_oerrors++; 1405 1.5.2.2 skrll 1406 1.5.2.2 skrll /* Reset the interface. */ 1407 1.5.2.2 skrll (void) dge_init(ifp); 1408 1.5.2.2 skrll } 1409 1.5.2.2 skrll 1410 1.5.2.2 skrll /* Try to get more packets going. */ 1411 1.5.2.2 skrll dge_start(ifp); 1412 1.5.2.2 skrll } 1413 1.5.2.2 skrll 1414 1.5.2.2 skrll /* 1415 1.5.2.2 skrll * dge_ioctl: [ifnet interface function] 1416 1.5.2.2 skrll * 1417 1.5.2.2 skrll * Handle control requests from the operator. 1418 1.5.2.2 skrll */ 1419 1.5.2.2 skrll static int 1420 1.5.2.2 skrll dge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1421 1.5.2.2 skrll { 1422 1.5.2.2 skrll struct dge_softc *sc = ifp->if_softc; 1423 1.5.2.2 skrll struct ifreq *ifr = (struct ifreq *) data; 1424 1.5.2.2 skrll pcireg_t preg; 1425 1.5.2.2 skrll int s, error, mmrbc; 1426 1.5.2.2 skrll 1427 1.5.2.2 skrll s = splnet(); 1428 1.5.2.2 skrll 1429 1.5.2.2 skrll switch (cmd) { 1430 1.5.2.2 skrll case SIOCSIFMEDIA: 1431 1.5.2.2 skrll case SIOCGIFMEDIA: 1432 1.5.2.2 skrll error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1433 1.5.2.2 skrll break; 1434 1.5.2.2 skrll 1435 1.5.2.2 skrll case SIOCSIFMTU: 1436 1.5.2.2 skrll if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) { 1437 1.5.2.2 skrll error = EINVAL; 1438 1.5.2.2 skrll } else { 1439 1.5.2.2 skrll error = 0; 1440 1.5.2.2 skrll ifp->if_mtu = ifr->ifr_mtu; 1441 1.5.2.2 skrll if (ifp->if_flags & IFF_UP) 1442 1.5.2.2 skrll error = (*ifp->if_init)(ifp); 1443 1.5.2.2 skrll } 1444 1.5.2.2 skrll break; 1445 1.5.2.2 skrll 1446 1.5.2.2 skrll case SIOCSIFFLAGS: 1447 1.5.2.2 skrll /* extract link flags */ 1448 1.5.2.2 skrll if ((ifp->if_flags & IFF_LINK0) == 0 && 1449 1.5.2.2 skrll (ifp->if_flags & IFF_LINK1) == 0) 1450 1.5.2.2 skrll mmrbc = PCIX_MMRBC_512; 1451 1.5.2.2 skrll else if ((ifp->if_flags & IFF_LINK0) == 0 && 1452 1.5.2.2 skrll (ifp->if_flags & IFF_LINK1) != 0) 1453 1.5.2.2 skrll mmrbc = PCIX_MMRBC_1024; 1454 1.5.2.2 skrll else if ((ifp->if_flags & IFF_LINK0) != 0 && 1455 1.5.2.2 skrll (ifp->if_flags & IFF_LINK1) == 0) 1456 1.5.2.2 skrll mmrbc = PCIX_MMRBC_2048; 1457 1.5.2.2 skrll else 1458 1.5.2.2 skrll mmrbc = PCIX_MMRBC_4096; 1459 1.5.2.2 skrll if (mmrbc != sc->sc_mmrbc) { 1460 1.5.2.2 skrll preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1461 1.5.2.2 skrll preg &= ~PCIX_MMRBC_MSK; 1462 1.5.2.2 skrll preg |= mmrbc; 1463 1.5.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1464 1.5.2.2 skrll sc->sc_mmrbc = mmrbc; 1465 1.5.2.2 skrll } 1466 1.5.2.2 skrll /* FALLTHROUGH */ 1467 1.5.2.2 skrll default: 1468 1.5.2.2 skrll error = ether_ioctl(ifp, cmd, data); 1469 1.5.2.2 skrll if (error == ENETRESET) { 1470 1.5.2.2 skrll /* 1471 1.5.2.2 skrll * Multicast list has changed; set the hardware filter 1472 1.5.2.2 skrll * accordingly. 1473 1.5.2.2 skrll */ 1474 1.5.2.2 skrll dge_set_filter(sc); 1475 1.5.2.2 skrll error = 0; 1476 1.5.2.2 skrll } 1477 1.5.2.2 skrll break; 1478 1.5.2.2 skrll } 1479 1.5.2.2 skrll 1480 1.5.2.2 skrll /* Try to get more packets going. */ 1481 1.5.2.2 skrll dge_start(ifp); 1482 1.5.2.2 skrll 1483 1.5.2.2 skrll splx(s); 1484 1.5.2.2 skrll return (error); 1485 1.5.2.2 skrll } 1486 1.5.2.2 skrll 1487 1.5.2.2 skrll /* 1488 1.5.2.2 skrll * dge_intr: 1489 1.5.2.2 skrll * 1490 1.5.2.2 skrll * Interrupt service routine. 1491 1.5.2.2 skrll */ 1492 1.5.2.2 skrll static int 1493 1.5.2.2 skrll dge_intr(void *arg) 1494 1.5.2.2 skrll { 1495 1.5.2.2 skrll struct dge_softc *sc = arg; 1496 1.5.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1497 1.5.2.2 skrll uint32_t icr; 1498 1.5.2.2 skrll int wantinit, handled = 0; 1499 1.5.2.2 skrll 1500 1.5.2.2 skrll for (wantinit = 0; wantinit == 0;) { 1501 1.5.2.2 skrll icr = CSR_READ(sc, DGE_ICR); 1502 1.5.2.2 skrll if ((icr & sc->sc_icr) == 0) 1503 1.5.2.2 skrll break; 1504 1.5.2.2 skrll 1505 1.5.2.2 skrll #if 0 /*NRND > 0*/ 1506 1.5.2.2 skrll if (RND_ENABLED(&sc->rnd_source)) 1507 1.5.2.2 skrll rnd_add_uint32(&sc->rnd_source, icr); 1508 1.5.2.2 skrll #endif 1509 1.5.2.2 skrll 1510 1.5.2.2 skrll handled = 1; 1511 1.5.2.2 skrll 1512 1.5.2.2 skrll #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1513 1.5.2.2 skrll if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1514 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1515 1.5.2.2 skrll ("%s: RX: got Rx intr 0x%08x\n", 1516 1.5.2.2 skrll sc->sc_dev.dv_xname, 1517 1.5.2.2 skrll icr & (ICR_RXDMT0|ICR_RXT0))); 1518 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1519 1.5.2.2 skrll } 1520 1.5.2.2 skrll #endif 1521 1.5.2.2 skrll dge_rxintr(sc); 1522 1.5.2.2 skrll 1523 1.5.2.2 skrll #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1524 1.5.2.2 skrll if (icr & ICR_TXDW) { 1525 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1526 1.5.2.2 skrll ("%s: TX: got TXDW interrupt\n", 1527 1.5.2.2 skrll sc->sc_dev.dv_xname)); 1528 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1529 1.5.2.2 skrll } 1530 1.5.2.2 skrll if (icr & ICR_TXQE) 1531 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1532 1.5.2.2 skrll #endif 1533 1.5.2.2 skrll dge_txintr(sc); 1534 1.5.2.2 skrll 1535 1.5.2.2 skrll if (icr & (ICR_LSC|ICR_RXSEQ)) { 1536 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1537 1.5.2.2 skrll dge_linkintr(sc, icr); 1538 1.5.2.2 skrll } 1539 1.5.2.2 skrll 1540 1.5.2.2 skrll if (icr & ICR_RXO) { 1541 1.5.2.2 skrll printf("%s: Receive overrun\n", sc->sc_dev.dv_xname); 1542 1.5.2.2 skrll wantinit = 1; 1543 1.5.2.2 skrll } 1544 1.5.2.2 skrll } 1545 1.5.2.2 skrll 1546 1.5.2.2 skrll if (handled) { 1547 1.5.2.2 skrll if (wantinit) 1548 1.5.2.2 skrll dge_init(ifp); 1549 1.5.2.2 skrll 1550 1.5.2.2 skrll /* Try to get more packets going. */ 1551 1.5.2.2 skrll dge_start(ifp); 1552 1.5.2.2 skrll } 1553 1.5.2.2 skrll 1554 1.5.2.2 skrll return (handled); 1555 1.5.2.2 skrll } 1556 1.5.2.2 skrll 1557 1.5.2.2 skrll /* 1558 1.5.2.2 skrll * dge_txintr: 1559 1.5.2.2 skrll * 1560 1.5.2.2 skrll * Helper; handle transmit interrupts. 1561 1.5.2.2 skrll */ 1562 1.5.2.2 skrll static void 1563 1.5.2.2 skrll dge_txintr(struct dge_softc *sc) 1564 1.5.2.2 skrll { 1565 1.5.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1566 1.5.2.2 skrll struct dge_txsoft *txs; 1567 1.5.2.2 skrll uint8_t status; 1568 1.5.2.2 skrll int i; 1569 1.5.2.2 skrll 1570 1.5.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 1571 1.5.2.2 skrll 1572 1.5.2.2 skrll /* 1573 1.5.2.2 skrll * Go through the Tx list and free mbufs for those 1574 1.5.2.2 skrll * frames which have been transmitted. 1575 1.5.2.2 skrll */ 1576 1.5.2.2 skrll for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1577 1.5.2.2 skrll i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1578 1.5.2.2 skrll txs = &sc->sc_txsoft[i]; 1579 1.5.2.2 skrll 1580 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1581 1.5.2.2 skrll ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 1582 1.5.2.2 skrll 1583 1.5.2.2 skrll DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1584 1.5.2.2 skrll BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1585 1.5.2.2 skrll 1586 1.5.2.2 skrll status = 1587 1.5.2.2 skrll sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1588 1.5.2.2 skrll if ((status & TDESC_STA_DD) == 0) { 1589 1.5.2.2 skrll DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1590 1.5.2.2 skrll BUS_DMASYNC_PREREAD); 1591 1.5.2.2 skrll break; 1592 1.5.2.2 skrll } 1593 1.5.2.2 skrll 1594 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1595 1.5.2.2 skrll ("%s: TX: job %d done: descs %d..%d\n", 1596 1.5.2.2 skrll sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 1597 1.5.2.2 skrll txs->txs_lastdesc)); 1598 1.5.2.2 skrll 1599 1.5.2.2 skrll ifp->if_opackets++; 1600 1.5.2.2 skrll sc->sc_txfree += txs->txs_ndesc; 1601 1.5.2.2 skrll bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1602 1.5.2.2 skrll 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1603 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1604 1.5.2.2 skrll m_freem(txs->txs_mbuf); 1605 1.5.2.2 skrll txs->txs_mbuf = NULL; 1606 1.5.2.2 skrll } 1607 1.5.2.2 skrll 1608 1.5.2.2 skrll /* Update the dirty transmit buffer pointer. */ 1609 1.5.2.2 skrll sc->sc_txsdirty = i; 1610 1.5.2.2 skrll DPRINTF(DGE_DEBUG_TX, 1611 1.5.2.2 skrll ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 1612 1.5.2.2 skrll 1613 1.5.2.2 skrll /* 1614 1.5.2.2 skrll * If there are no more pending transmissions, cancel the watchdog 1615 1.5.2.2 skrll * timer. 1616 1.5.2.2 skrll */ 1617 1.5.2.2 skrll if (sc->sc_txsfree == DGE_TXQUEUELEN) 1618 1.5.2.2 skrll ifp->if_timer = 0; 1619 1.5.2.2 skrll } 1620 1.5.2.2 skrll 1621 1.5.2.2 skrll /* 1622 1.5.2.2 skrll * dge_rxintr: 1623 1.5.2.2 skrll * 1624 1.5.2.2 skrll * Helper; handle receive interrupts. 1625 1.5.2.2 skrll */ 1626 1.5.2.2 skrll static void 1627 1.5.2.2 skrll dge_rxintr(struct dge_softc *sc) 1628 1.5.2.2 skrll { 1629 1.5.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1630 1.5.2.2 skrll struct dge_rxsoft *rxs; 1631 1.5.2.2 skrll struct mbuf *m; 1632 1.5.2.2 skrll int i, len; 1633 1.5.2.2 skrll uint8_t status, errors; 1634 1.5.2.2 skrll 1635 1.5.2.2 skrll for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1636 1.5.2.2 skrll rxs = &sc->sc_rxsoft[i]; 1637 1.5.2.2 skrll 1638 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1639 1.5.2.2 skrll ("%s: RX: checking descriptor %d\n", 1640 1.5.2.2 skrll sc->sc_dev.dv_xname, i)); 1641 1.5.2.2 skrll 1642 1.5.2.2 skrll DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1643 1.5.2.2 skrll 1644 1.5.2.2 skrll status = sc->sc_rxdescs[i].dr_status; 1645 1.5.2.2 skrll errors = sc->sc_rxdescs[i].dr_errors; 1646 1.5.2.2 skrll len = le16toh(sc->sc_rxdescs[i].dr_len); 1647 1.5.2.2 skrll 1648 1.5.2.2 skrll if ((status & RDESC_STS_DD) == 0) { 1649 1.5.2.2 skrll /* 1650 1.5.2.2 skrll * We have processed all of the receive descriptors. 1651 1.5.2.2 skrll */ 1652 1.5.2.2 skrll DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1653 1.5.2.2 skrll break; 1654 1.5.2.2 skrll } 1655 1.5.2.2 skrll 1656 1.5.2.2 skrll if (__predict_false(sc->sc_rxdiscard)) { 1657 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1658 1.5.2.2 skrll ("%s: RX: discarding contents of descriptor %d\n", 1659 1.5.2.2 skrll sc->sc_dev.dv_xname, i)); 1660 1.5.2.2 skrll DGE_INIT_RXDESC(sc, i); 1661 1.5.2.2 skrll if (status & RDESC_STS_EOP) { 1662 1.5.2.2 skrll /* Reset our state. */ 1663 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1664 1.5.2.2 skrll ("%s: RX: resetting rxdiscard -> 0\n", 1665 1.5.2.2 skrll sc->sc_dev.dv_xname)); 1666 1.5.2.2 skrll sc->sc_rxdiscard = 0; 1667 1.5.2.2 skrll } 1668 1.5.2.2 skrll continue; 1669 1.5.2.2 skrll } 1670 1.5.2.2 skrll 1671 1.5.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1672 1.5.2.2 skrll rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1673 1.5.2.2 skrll 1674 1.5.2.2 skrll m = rxs->rxs_mbuf; 1675 1.5.2.2 skrll 1676 1.5.2.2 skrll /* 1677 1.5.2.2 skrll * Add a new receive buffer to the ring. 1678 1.5.2.2 skrll */ 1679 1.5.2.2 skrll if (dge_add_rxbuf(sc, i) != 0) { 1680 1.5.2.2 skrll /* 1681 1.5.2.2 skrll * Failed, throw away what we've done so 1682 1.5.2.2 skrll * far, and discard the rest of the packet. 1683 1.5.2.2 skrll */ 1684 1.5.2.2 skrll ifp->if_ierrors++; 1685 1.5.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1686 1.5.2.2 skrll rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1687 1.5.2.2 skrll DGE_INIT_RXDESC(sc, i); 1688 1.5.2.2 skrll if ((status & RDESC_STS_EOP) == 0) 1689 1.5.2.2 skrll sc->sc_rxdiscard = 1; 1690 1.5.2.2 skrll if (sc->sc_rxhead != NULL) 1691 1.5.2.2 skrll m_freem(sc->sc_rxhead); 1692 1.5.2.2 skrll DGE_RXCHAIN_RESET(sc); 1693 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1694 1.5.2.2 skrll ("%s: RX: Rx buffer allocation failed, " 1695 1.5.2.2 skrll "dropping packet%s\n", sc->sc_dev.dv_xname, 1696 1.5.2.2 skrll sc->sc_rxdiscard ? " (discard)" : "")); 1697 1.5.2.2 skrll continue; 1698 1.5.2.2 skrll } 1699 1.5.2.2 skrll DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1700 1.5.2.2 skrll 1701 1.5.2.2 skrll DGE_RXCHAIN_LINK(sc, m); 1702 1.5.2.2 skrll 1703 1.5.2.2 skrll m->m_len = len; 1704 1.5.2.2 skrll 1705 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1706 1.5.2.2 skrll ("%s: RX: buffer at %p len %d\n", 1707 1.5.2.2 skrll sc->sc_dev.dv_xname, m->m_data, len)); 1708 1.5.2.2 skrll 1709 1.5.2.2 skrll /* 1710 1.5.2.2 skrll * If this is not the end of the packet, keep 1711 1.5.2.2 skrll * looking. 1712 1.5.2.2 skrll */ 1713 1.5.2.2 skrll if ((status & RDESC_STS_EOP) == 0) { 1714 1.5.2.2 skrll sc->sc_rxlen += len; 1715 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1716 1.5.2.2 skrll ("%s: RX: not yet EOP, rxlen -> %d\n", 1717 1.5.2.2 skrll sc->sc_dev.dv_xname, sc->sc_rxlen)); 1718 1.5.2.2 skrll continue; 1719 1.5.2.2 skrll } 1720 1.5.2.2 skrll 1721 1.5.2.2 skrll /* 1722 1.5.2.2 skrll * Okay, we have the entire packet now... 1723 1.5.2.2 skrll */ 1724 1.5.2.2 skrll *sc->sc_rxtailp = NULL; 1725 1.5.2.2 skrll m = sc->sc_rxhead; 1726 1.5.2.2 skrll len += sc->sc_rxlen; 1727 1.5.2.2 skrll 1728 1.5.2.2 skrll DGE_RXCHAIN_RESET(sc); 1729 1.5.2.2 skrll 1730 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1731 1.5.2.2 skrll ("%s: RX: have entire packet, len -> %d\n", 1732 1.5.2.2 skrll sc->sc_dev.dv_xname, len)); 1733 1.5.2.2 skrll 1734 1.5.2.2 skrll /* 1735 1.5.2.2 skrll * If an error occurred, update stats and drop the packet. 1736 1.5.2.2 skrll */ 1737 1.5.2.2 skrll if (errors & 1738 1.5.2.2 skrll (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1739 1.5.2.2 skrll ifp->if_ierrors++; 1740 1.5.2.2 skrll if (errors & RDESC_ERR_SE) 1741 1.5.2.2 skrll printf("%s: symbol error\n", 1742 1.5.2.2 skrll sc->sc_dev.dv_xname); 1743 1.5.2.2 skrll else if (errors & RDESC_ERR_P) 1744 1.5.2.2 skrll printf("%s: parity error\n", 1745 1.5.2.2 skrll sc->sc_dev.dv_xname); 1746 1.5.2.2 skrll else if (errors & RDESC_ERR_CE) 1747 1.5.2.2 skrll printf("%s: CRC error\n", 1748 1.5.2.2 skrll sc->sc_dev.dv_xname); 1749 1.5.2.2 skrll m_freem(m); 1750 1.5.2.2 skrll continue; 1751 1.5.2.2 skrll } 1752 1.5.2.2 skrll 1753 1.5.2.2 skrll /* 1754 1.5.2.2 skrll * No errors. Receive the packet. 1755 1.5.2.2 skrll */ 1756 1.5.2.2 skrll m->m_pkthdr.rcvif = ifp; 1757 1.5.2.2 skrll m->m_pkthdr.len = len; 1758 1.5.2.2 skrll 1759 1.5.2.2 skrll /* 1760 1.5.2.2 skrll * Set up checksum info for this packet. 1761 1.5.2.2 skrll */ 1762 1.5.2.2 skrll if (status & RDESC_STS_IPCS) { 1763 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1764 1.5.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1765 1.5.2.2 skrll if (errors & RDESC_ERR_IPE) 1766 1.5.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1767 1.5.2.2 skrll } 1768 1.5.2.2 skrll if (status & RDESC_STS_TCPCS) { 1769 1.5.2.2 skrll /* 1770 1.5.2.2 skrll * Note: we don't know if this was TCP or UDP, 1771 1.5.2.2 skrll * so we just set both bits, and expect the 1772 1.5.2.2 skrll * upper layers to deal. 1773 1.5.2.2 skrll */ 1774 1.5.2.2 skrll DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1775 1.5.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1776 1.5.2.2 skrll if (errors & RDESC_ERR_TCPE) 1777 1.5.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1778 1.5.2.2 skrll } 1779 1.5.2.2 skrll 1780 1.5.2.2 skrll ifp->if_ipackets++; 1781 1.5.2.2 skrll 1782 1.5.2.2 skrll #if NBPFILTER > 0 1783 1.5.2.2 skrll /* Pass this up to any BPF listeners. */ 1784 1.5.2.2 skrll if (ifp->if_bpf) 1785 1.5.2.2 skrll bpf_mtap(ifp->if_bpf, m); 1786 1.5.2.2 skrll #endif /* NBPFILTER > 0 */ 1787 1.5.2.2 skrll 1788 1.5.2.2 skrll /* Pass it on. */ 1789 1.5.2.2 skrll (*ifp->if_input)(ifp, m); 1790 1.5.2.2 skrll } 1791 1.5.2.2 skrll 1792 1.5.2.2 skrll /* Update the receive pointer. */ 1793 1.5.2.2 skrll sc->sc_rxptr = i; 1794 1.5.2.2 skrll 1795 1.5.2.2 skrll DPRINTF(DGE_DEBUG_RX, 1796 1.5.2.2 skrll ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 1797 1.5.2.2 skrll } 1798 1.5.2.2 skrll 1799 1.5.2.2 skrll /* 1800 1.5.2.2 skrll * dge_linkintr: 1801 1.5.2.2 skrll * 1802 1.5.2.2 skrll * Helper; handle link interrupts. 1803 1.5.2.2 skrll */ 1804 1.5.2.2 skrll static void 1805 1.5.2.2 skrll dge_linkintr(struct dge_softc *sc, uint32_t icr) 1806 1.5.2.2 skrll { 1807 1.5.2.2 skrll uint32_t status; 1808 1.5.2.2 skrll 1809 1.5.2.2 skrll if (icr & ICR_LSC) { 1810 1.5.2.2 skrll status = CSR_READ(sc, DGE_STATUS); 1811 1.5.2.2 skrll if (status & STATUS_LINKUP) { 1812 1.5.2.2 skrll DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1813 1.5.2.2 skrll sc->sc_dev.dv_xname)); 1814 1.5.2.2 skrll } else { 1815 1.5.2.2 skrll DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1816 1.5.2.2 skrll sc->sc_dev.dv_xname)); 1817 1.5.2.2 skrll } 1818 1.5.2.2 skrll } else if (icr & ICR_RXSEQ) { 1819 1.5.2.2 skrll DPRINTF(DGE_DEBUG_LINK, 1820 1.5.2.2 skrll ("%s: LINK: Receive sequence error\n", 1821 1.5.2.2 skrll sc->sc_dev.dv_xname)); 1822 1.5.2.2 skrll } 1823 1.5.2.2 skrll /* XXX - fix errata */ 1824 1.5.2.2 skrll } 1825 1.5.2.2 skrll 1826 1.5.2.2 skrll /* 1827 1.5.2.2 skrll * dge_reset: 1828 1.5.2.2 skrll * 1829 1.5.2.2 skrll * Reset the i82597 chip. 1830 1.5.2.2 skrll */ 1831 1.5.2.2 skrll static void 1832 1.5.2.2 skrll dge_reset(struct dge_softc *sc) 1833 1.5.2.2 skrll { 1834 1.5.2.2 skrll int i; 1835 1.5.2.2 skrll 1836 1.5.2.2 skrll /* 1837 1.5.2.2 skrll * Do a chip reset. 1838 1.5.2.2 skrll */ 1839 1.5.2.2 skrll CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1840 1.5.2.2 skrll 1841 1.5.2.2 skrll delay(10000); 1842 1.5.2.2 skrll 1843 1.5.2.2 skrll for (i = 0; i < 1000; i++) { 1844 1.5.2.2 skrll if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1845 1.5.2.2 skrll break; 1846 1.5.2.2 skrll delay(20); 1847 1.5.2.2 skrll } 1848 1.5.2.2 skrll 1849 1.5.2.2 skrll if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1850 1.5.2.2 skrll printf("%s: WARNING: reset failed to complete\n", 1851 1.5.2.2 skrll sc->sc_dev.dv_xname); 1852 1.5.2.2 skrll /* 1853 1.5.2.2 skrll * Reset the EEPROM logic. 1854 1.5.2.2 skrll * This will cause the chip to reread its default values, 1855 1.5.2.2 skrll * which doesn't happen otherwise (errata). 1856 1.5.2.2 skrll */ 1857 1.5.2.2 skrll CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1858 1.5.2.2 skrll delay(10000); 1859 1.5.2.2 skrll } 1860 1.5.2.2 skrll 1861 1.5.2.2 skrll /* 1862 1.5.2.2 skrll * dge_init: [ifnet interface function] 1863 1.5.2.2 skrll * 1864 1.5.2.2 skrll * Initialize the interface. Must be called at splnet(). 1865 1.5.2.2 skrll */ 1866 1.5.2.2 skrll static int 1867 1.5.2.2 skrll dge_init(struct ifnet *ifp) 1868 1.5.2.2 skrll { 1869 1.5.2.2 skrll struct dge_softc *sc = ifp->if_softc; 1870 1.5.2.2 skrll struct dge_rxsoft *rxs; 1871 1.5.2.2 skrll int i, error = 0; 1872 1.5.2.2 skrll uint32_t reg; 1873 1.5.2.2 skrll 1874 1.5.2.2 skrll /* 1875 1.5.2.2 skrll * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1876 1.5.2.2 skrll * There is a small but measurable benefit to avoiding the adjusment 1877 1.5.2.2 skrll * of the descriptor so that the headers are aligned, for normal mtu, 1878 1.5.2.2 skrll * on such platforms. One possibility is that the DMA itself is 1879 1.5.2.2 skrll * slightly more efficient if the front of the entire packet (instead 1880 1.5.2.2 skrll * of the front of the headers) is aligned. 1881 1.5.2.2 skrll * 1882 1.5.2.2 skrll * Note we must always set align_tweak to 0 if we are using 1883 1.5.2.2 skrll * jumbo frames. 1884 1.5.2.2 skrll */ 1885 1.5.2.2 skrll #ifdef __NO_STRICT_ALIGNMENT 1886 1.5.2.2 skrll sc->sc_align_tweak = 0; 1887 1.5.2.2 skrll #else 1888 1.5.2.2 skrll if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1889 1.5.2.2 skrll sc->sc_align_tweak = 0; 1890 1.5.2.2 skrll else 1891 1.5.2.2 skrll sc->sc_align_tweak = 2; 1892 1.5.2.2 skrll #endif /* __NO_STRICT_ALIGNMENT */ 1893 1.5.2.2 skrll 1894 1.5.2.2 skrll /* Cancel any pending I/O. */ 1895 1.5.2.2 skrll dge_stop(ifp, 0); 1896 1.5.2.2 skrll 1897 1.5.2.2 skrll /* Reset the chip to a known state. */ 1898 1.5.2.2 skrll dge_reset(sc); 1899 1.5.2.2 skrll 1900 1.5.2.2 skrll /* Initialize the transmit descriptor ring. */ 1901 1.5.2.2 skrll memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1902 1.5.2.2 skrll DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1903 1.5.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1904 1.5.2.2 skrll sc->sc_txfree = DGE_NTXDESC; 1905 1.5.2.2 skrll sc->sc_txnext = 0; 1906 1.5.2.2 skrll 1907 1.5.2.2 skrll sc->sc_txctx_ipcs = 0xffffffff; 1908 1.5.2.2 skrll sc->sc_txctx_tucs = 0xffffffff; 1909 1.5.2.2 skrll 1910 1.5.2.2 skrll CSR_WRITE(sc, DGE_TDBAH, 0); 1911 1.5.2.2 skrll CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1912 1.5.2.2 skrll CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1913 1.5.2.2 skrll CSR_WRITE(sc, DGE_TDH, 0); 1914 1.5.2.2 skrll CSR_WRITE(sc, DGE_TDT, 0); 1915 1.5.2.2 skrll CSR_WRITE(sc, DGE_TIDV, TIDV); 1916 1.5.2.2 skrll 1917 1.5.2.2 skrll #if 0 1918 1.5.2.2 skrll CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1919 1.5.2.2 skrll TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1920 1.5.2.2 skrll #endif 1921 1.5.2.2 skrll CSR_WRITE(sc, DGE_RXDCTL, 1922 1.5.2.2 skrll RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1923 1.5.2.2 skrll RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1924 1.5.2.2 skrll RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1925 1.5.2.2 skrll 1926 1.5.2.2 skrll /* Initialize the transmit job descriptors. */ 1927 1.5.2.2 skrll for (i = 0; i < DGE_TXQUEUELEN; i++) 1928 1.5.2.2 skrll sc->sc_txsoft[i].txs_mbuf = NULL; 1929 1.5.2.2 skrll sc->sc_txsfree = DGE_TXQUEUELEN; 1930 1.5.2.2 skrll sc->sc_txsnext = 0; 1931 1.5.2.2 skrll sc->sc_txsdirty = 0; 1932 1.5.2.2 skrll 1933 1.5.2.2 skrll /* 1934 1.5.2.2 skrll * Initialize the receive descriptor and receive job 1935 1.5.2.2 skrll * descriptor rings. 1936 1.5.2.2 skrll */ 1937 1.5.2.2 skrll CSR_WRITE(sc, DGE_RDBAH, 0); 1938 1.5.2.2 skrll CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1939 1.5.2.2 skrll CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1940 1.5.2.2 skrll CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1941 1.5.2.2 skrll CSR_WRITE(sc, DGE_RDT, 0); 1942 1.5.2.2 skrll CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1943 1.5.2.2 skrll CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1944 1.5.2.2 skrll CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1945 1.5.2.2 skrll 1946 1.5.2.2 skrll for (i = 0; i < DGE_NRXDESC; i++) { 1947 1.5.2.2 skrll rxs = &sc->sc_rxsoft[i]; 1948 1.5.2.2 skrll if (rxs->rxs_mbuf == NULL) { 1949 1.5.2.2 skrll if ((error = dge_add_rxbuf(sc, i)) != 0) { 1950 1.5.2.2 skrll printf("%s: unable to allocate or map rx " 1951 1.5.2.2 skrll "buffer %d, error = %d\n", 1952 1.5.2.2 skrll sc->sc_dev.dv_xname, i, error); 1953 1.5.2.2 skrll /* 1954 1.5.2.2 skrll * XXX Should attempt to run with fewer receive 1955 1.5.2.2 skrll * XXX buffers instead of just failing. 1956 1.5.2.2 skrll */ 1957 1.5.2.2 skrll dge_rxdrain(sc); 1958 1.5.2.2 skrll goto out; 1959 1.5.2.2 skrll } 1960 1.5.2.2 skrll } 1961 1.5.2.2 skrll DGE_INIT_RXDESC(sc, i); 1962 1.5.2.2 skrll } 1963 1.5.2.2 skrll sc->sc_rxptr = DGE_RXSPACE; 1964 1.5.2.2 skrll sc->sc_rxdiscard = 0; 1965 1.5.2.2 skrll DGE_RXCHAIN_RESET(sc); 1966 1.5.2.2 skrll 1967 1.5.2.2 skrll if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1968 1.5.2.2 skrll sc->sc_ctrl0 |= CTRL0_JFE; 1969 1.5.2.2 skrll CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1970 1.5.2.2 skrll } 1971 1.5.2.2 skrll 1972 1.5.2.2 skrll /* Write the control registers. */ 1973 1.5.2.2 skrll CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1974 1.5.2.2 skrll 1975 1.5.2.2 skrll /* 1976 1.5.2.2 skrll * Set up checksum offload parameters. 1977 1.5.2.2 skrll */ 1978 1.5.2.2 skrll reg = CSR_READ(sc, DGE_RXCSUM); 1979 1.5.2.2 skrll if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1980 1.5.2.2 skrll reg |= RXCSUM_IPOFL; 1981 1.5.2.2 skrll else 1982 1.5.2.2 skrll reg &= ~RXCSUM_IPOFL; 1983 1.5.2.2 skrll if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 1984 1.5.2.2 skrll reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1985 1.5.2.2 skrll else { 1986 1.5.2.2 skrll reg &= ~RXCSUM_TUOFL; 1987 1.5.2.2 skrll if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 1988 1.5.2.2 skrll reg &= ~RXCSUM_IPOFL; 1989 1.5.2.2 skrll } 1990 1.5.2.2 skrll CSR_WRITE(sc, DGE_RXCSUM, reg); 1991 1.5.2.2 skrll 1992 1.5.2.2 skrll /* 1993 1.5.2.2 skrll * Set up the interrupt registers. 1994 1.5.2.2 skrll */ 1995 1.5.2.2 skrll CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 1996 1.5.2.2 skrll sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 1997 1.5.2.2 skrll ICR_RXO | ICR_RXT0; 1998 1.5.2.2 skrll 1999 1.5.2.2 skrll CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 2000 1.5.2.2 skrll 2001 1.5.2.2 skrll /* 2002 1.5.2.2 skrll * Set up the transmit control register. 2003 1.5.2.2 skrll */ 2004 1.5.2.2 skrll sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 2005 1.5.2.2 skrll CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 2006 1.5.2.2 skrll 2007 1.5.2.2 skrll /* 2008 1.5.2.2 skrll * Set up the receive control register; we actually program 2009 1.5.2.2 skrll * the register when we set the receive filter. Use multicast 2010 1.5.2.2 skrll * address offset type 0. 2011 1.5.2.2 skrll */ 2012 1.5.2.2 skrll sc->sc_mchash_type = 0; 2013 1.5.2.2 skrll 2014 1.5.2.2 skrll sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2015 1.5.2.2 skrll RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2016 1.5.2.2 skrll 2017 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 2018 1.5.2.2 skrll sc->sc_rctl |= RCTL_BSIZE_16k; 2019 1.5.2.2 skrll #else 2020 1.5.2.2 skrll switch(MCLBYTES) { 2021 1.5.2.2 skrll case 2048: 2022 1.5.2.2 skrll sc->sc_rctl |= RCTL_BSIZE_2k; 2023 1.5.2.2 skrll break; 2024 1.5.2.2 skrll case 4096: 2025 1.5.2.2 skrll sc->sc_rctl |= RCTL_BSIZE_4k; 2026 1.5.2.2 skrll break; 2027 1.5.2.2 skrll case 8192: 2028 1.5.2.2 skrll sc->sc_rctl |= RCTL_BSIZE_8k; 2029 1.5.2.2 skrll break; 2030 1.5.2.2 skrll case 16384: 2031 1.5.2.2 skrll sc->sc_rctl |= RCTL_BSIZE_16k; 2032 1.5.2.2 skrll break; 2033 1.5.2.2 skrll default: 2034 1.5.2.2 skrll panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2035 1.5.2.2 skrll } 2036 1.5.2.2 skrll #endif 2037 1.5.2.2 skrll 2038 1.5.2.2 skrll /* Set the receive filter. */ 2039 1.5.2.2 skrll /* Also sets RCTL */ 2040 1.5.2.2 skrll dge_set_filter(sc); 2041 1.5.2.2 skrll 2042 1.5.2.2 skrll /* ...all done! */ 2043 1.5.2.2 skrll ifp->if_flags |= IFF_RUNNING; 2044 1.5.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 2045 1.5.2.2 skrll 2046 1.5.2.2 skrll out: 2047 1.5.2.2 skrll if (error) 2048 1.5.2.2 skrll printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2049 1.5.2.2 skrll return (error); 2050 1.5.2.2 skrll } 2051 1.5.2.2 skrll 2052 1.5.2.2 skrll /* 2053 1.5.2.2 skrll * dge_rxdrain: 2054 1.5.2.2 skrll * 2055 1.5.2.2 skrll * Drain the receive queue. 2056 1.5.2.2 skrll */ 2057 1.5.2.2 skrll static void 2058 1.5.2.2 skrll dge_rxdrain(struct dge_softc *sc) 2059 1.5.2.2 skrll { 2060 1.5.2.2 skrll struct dge_rxsoft *rxs; 2061 1.5.2.2 skrll int i; 2062 1.5.2.2 skrll 2063 1.5.2.2 skrll for (i = 0; i < DGE_NRXDESC; i++) { 2064 1.5.2.2 skrll rxs = &sc->sc_rxsoft[i]; 2065 1.5.2.2 skrll if (rxs->rxs_mbuf != NULL) { 2066 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2067 1.5.2.2 skrll m_freem(rxs->rxs_mbuf); 2068 1.5.2.2 skrll rxs->rxs_mbuf = NULL; 2069 1.5.2.2 skrll } 2070 1.5.2.2 skrll } 2071 1.5.2.2 skrll } 2072 1.5.2.2 skrll 2073 1.5.2.2 skrll /* 2074 1.5.2.2 skrll * dge_stop: [ifnet interface function] 2075 1.5.2.2 skrll * 2076 1.5.2.2 skrll * Stop transmission on the interface. 2077 1.5.2.2 skrll */ 2078 1.5.2.2 skrll static void 2079 1.5.2.2 skrll dge_stop(struct ifnet *ifp, int disable) 2080 1.5.2.2 skrll { 2081 1.5.2.2 skrll struct dge_softc *sc = ifp->if_softc; 2082 1.5.2.2 skrll struct dge_txsoft *txs; 2083 1.5.2.2 skrll int i; 2084 1.5.2.2 skrll 2085 1.5.2.2 skrll /* Stop the transmit and receive processes. */ 2086 1.5.2.2 skrll CSR_WRITE(sc, DGE_TCTL, 0); 2087 1.5.2.2 skrll CSR_WRITE(sc, DGE_RCTL, 0); 2088 1.5.2.2 skrll 2089 1.5.2.2 skrll /* Release any queued transmit buffers. */ 2090 1.5.2.2 skrll for (i = 0; i < DGE_TXQUEUELEN; i++) { 2091 1.5.2.2 skrll txs = &sc->sc_txsoft[i]; 2092 1.5.2.2 skrll if (txs->txs_mbuf != NULL) { 2093 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2094 1.5.2.2 skrll m_freem(txs->txs_mbuf); 2095 1.5.2.2 skrll txs->txs_mbuf = NULL; 2096 1.5.2.2 skrll } 2097 1.5.2.2 skrll } 2098 1.5.2.2 skrll 2099 1.5.2.2 skrll if (disable) 2100 1.5.2.2 skrll dge_rxdrain(sc); 2101 1.5.2.2 skrll 2102 1.5.2.2 skrll /* Mark the interface as down and cancel the watchdog timer. */ 2103 1.5.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2104 1.5.2.2 skrll ifp->if_timer = 0; 2105 1.5.2.2 skrll } 2106 1.5.2.2 skrll 2107 1.5.2.2 skrll /* 2108 1.5.2.2 skrll * dge_add_rxbuf: 2109 1.5.2.2 skrll * 2110 1.5.2.2 skrll * Add a receive buffer to the indiciated descriptor. 2111 1.5.2.2 skrll */ 2112 1.5.2.2 skrll static int 2113 1.5.2.2 skrll dge_add_rxbuf(struct dge_softc *sc, int idx) 2114 1.5.2.2 skrll { 2115 1.5.2.2 skrll struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2116 1.5.2.2 skrll struct mbuf *m; 2117 1.5.2.2 skrll int error; 2118 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 2119 1.5.2.2 skrll caddr_t buf; 2120 1.5.2.2 skrll #endif 2121 1.5.2.2 skrll 2122 1.5.2.2 skrll MGETHDR(m, M_DONTWAIT, MT_DATA); 2123 1.5.2.2 skrll if (m == NULL) 2124 1.5.2.2 skrll return (ENOBUFS); 2125 1.5.2.2 skrll 2126 1.5.2.2 skrll #ifdef DGE_OFFBYONE_RXBUG 2127 1.5.2.2 skrll if ((buf = dge_getbuf(sc)) == NULL) 2128 1.5.2.2 skrll return ENOBUFS; 2129 1.5.2.2 skrll 2130 1.5.2.2 skrll m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2131 1.5.2.2 skrll MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2132 1.5.2.5 skrll m->m_flags |= M_EXT_RW; 2133 1.5.2.2 skrll 2134 1.5.2.2 skrll if (rxs->rxs_mbuf != NULL) 2135 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2136 1.5.2.2 skrll rxs->rxs_mbuf = m; 2137 1.5.2.2 skrll 2138 1.5.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2139 1.5.2.2 skrll DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2140 1.5.2.2 skrll #else 2141 1.5.2.2 skrll MCLGET(m, M_DONTWAIT); 2142 1.5.2.2 skrll if ((m->m_flags & M_EXT) == 0) { 2143 1.5.2.2 skrll m_freem(m); 2144 1.5.2.2 skrll return (ENOBUFS); 2145 1.5.2.2 skrll } 2146 1.5.2.2 skrll 2147 1.5.2.2 skrll if (rxs->rxs_mbuf != NULL) 2148 1.5.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2149 1.5.2.2 skrll 2150 1.5.2.2 skrll rxs->rxs_mbuf = m; 2151 1.5.2.2 skrll 2152 1.5.2.2 skrll m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2153 1.5.2.2 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2154 1.5.2.2 skrll BUS_DMA_READ|BUS_DMA_NOWAIT); 2155 1.5.2.2 skrll #endif 2156 1.5.2.2 skrll if (error) { 2157 1.5.2.2 skrll printf("%s: unable to load rx DMA map %d, error = %d\n", 2158 1.5.2.2 skrll sc->sc_dev.dv_xname, idx, error); 2159 1.5.2.2 skrll panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2160 1.5.2.2 skrll } 2161 1.5.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2162 1.5.2.2 skrll rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2163 1.5.2.2 skrll 2164 1.5.2.2 skrll return (0); 2165 1.5.2.2 skrll } 2166 1.5.2.2 skrll 2167 1.5.2.2 skrll /* 2168 1.5.2.2 skrll * dge_set_ral: 2169 1.5.2.2 skrll * 2170 1.5.2.2 skrll * Set an entry in the receive address list. 2171 1.5.2.2 skrll */ 2172 1.5.2.2 skrll static void 2173 1.5.2.2 skrll dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2174 1.5.2.2 skrll { 2175 1.5.2.2 skrll uint32_t ral_lo, ral_hi; 2176 1.5.2.2 skrll 2177 1.5.2.2 skrll if (enaddr != NULL) { 2178 1.5.2.2 skrll ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2179 1.5.2.2 skrll (enaddr[3] << 24); 2180 1.5.2.2 skrll ral_hi = enaddr[4] | (enaddr[5] << 8); 2181 1.5.2.2 skrll ral_hi |= RAH_AV; 2182 1.5.2.2 skrll } else { 2183 1.5.2.2 skrll ral_lo = 0; 2184 1.5.2.2 skrll ral_hi = 0; 2185 1.5.2.2 skrll } 2186 1.5.2.2 skrll CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2187 1.5.2.2 skrll CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2188 1.5.2.2 skrll } 2189 1.5.2.2 skrll 2190 1.5.2.2 skrll /* 2191 1.5.2.2 skrll * dge_mchash: 2192 1.5.2.2 skrll * 2193 1.5.2.2 skrll * Compute the hash of the multicast address for the 4096-bit 2194 1.5.2.2 skrll * multicast filter. 2195 1.5.2.2 skrll */ 2196 1.5.2.2 skrll static uint32_t 2197 1.5.2.2 skrll dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2198 1.5.2.2 skrll { 2199 1.5.2.2 skrll static const int lo_shift[4] = { 4, 3, 2, 0 }; 2200 1.5.2.2 skrll static const int hi_shift[4] = { 4, 5, 6, 8 }; 2201 1.5.2.2 skrll uint32_t hash; 2202 1.5.2.2 skrll 2203 1.5.2.2 skrll hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2204 1.5.2.2 skrll (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2205 1.5.2.2 skrll 2206 1.5.2.2 skrll return (hash & 0xfff); 2207 1.5.2.2 skrll } 2208 1.5.2.2 skrll 2209 1.5.2.2 skrll /* 2210 1.5.2.2 skrll * dge_set_filter: 2211 1.5.2.2 skrll * 2212 1.5.2.2 skrll * Set up the receive filter. 2213 1.5.2.2 skrll */ 2214 1.5.2.2 skrll static void 2215 1.5.2.2 skrll dge_set_filter(struct dge_softc *sc) 2216 1.5.2.2 skrll { 2217 1.5.2.2 skrll struct ethercom *ec = &sc->sc_ethercom; 2218 1.5.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2219 1.5.2.2 skrll struct ether_multi *enm; 2220 1.5.2.2 skrll struct ether_multistep step; 2221 1.5.2.2 skrll uint32_t hash, reg, bit; 2222 1.5.2.2 skrll int i; 2223 1.5.2.2 skrll 2224 1.5.2.2 skrll sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2225 1.5.2.2 skrll 2226 1.5.2.2 skrll if (ifp->if_flags & IFF_BROADCAST) 2227 1.5.2.2 skrll sc->sc_rctl |= RCTL_BAM; 2228 1.5.2.2 skrll if (ifp->if_flags & IFF_PROMISC) { 2229 1.5.2.2 skrll sc->sc_rctl |= RCTL_UPE; 2230 1.5.2.2 skrll goto allmulti; 2231 1.5.2.2 skrll } 2232 1.5.2.2 skrll 2233 1.5.2.2 skrll /* 2234 1.5.2.2 skrll * Set the station address in the first RAL slot, and 2235 1.5.2.2 skrll * clear the remaining slots. 2236 1.5.2.2 skrll */ 2237 1.5.2.2 skrll dge_set_ral(sc, LLADDR(ifp->if_sadl), 0); 2238 1.5.2.2 skrll for (i = 1; i < RA_TABSIZE; i++) 2239 1.5.2.2 skrll dge_set_ral(sc, NULL, i); 2240 1.5.2.2 skrll 2241 1.5.2.2 skrll /* Clear out the multicast table. */ 2242 1.5.2.2 skrll for (i = 0; i < MC_TABSIZE; i++) 2243 1.5.2.2 skrll CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2244 1.5.2.2 skrll 2245 1.5.2.2 skrll ETHER_FIRST_MULTI(step, ec, enm); 2246 1.5.2.2 skrll while (enm != NULL) { 2247 1.5.2.2 skrll if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2248 1.5.2.2 skrll /* 2249 1.5.2.2 skrll * We must listen to a range of multicast addresses. 2250 1.5.2.2 skrll * For now, just accept all multicasts, rather than 2251 1.5.2.2 skrll * trying to set only those filter bits needed to match 2252 1.5.2.2 skrll * the range. (At this time, the only use of address 2253 1.5.2.2 skrll * ranges is for IP multicast routing, for which the 2254 1.5.2.2 skrll * range is big enough to require all bits set.) 2255 1.5.2.2 skrll */ 2256 1.5.2.2 skrll goto allmulti; 2257 1.5.2.2 skrll } 2258 1.5.2.2 skrll 2259 1.5.2.2 skrll hash = dge_mchash(sc, enm->enm_addrlo); 2260 1.5.2.2 skrll 2261 1.5.2.2 skrll reg = (hash >> 5) & 0x7f; 2262 1.5.2.2 skrll bit = hash & 0x1f; 2263 1.5.2.2 skrll 2264 1.5.2.2 skrll hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2265 1.5.2.2 skrll hash |= 1U << bit; 2266 1.5.2.2 skrll 2267 1.5.2.2 skrll CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2268 1.5.2.2 skrll 2269 1.5.2.2 skrll ETHER_NEXT_MULTI(step, enm); 2270 1.5.2.2 skrll } 2271 1.5.2.2 skrll 2272 1.5.2.2 skrll ifp->if_flags &= ~IFF_ALLMULTI; 2273 1.5.2.2 skrll goto setit; 2274 1.5.2.2 skrll 2275 1.5.2.2 skrll allmulti: 2276 1.5.2.2 skrll ifp->if_flags |= IFF_ALLMULTI; 2277 1.5.2.2 skrll sc->sc_rctl |= RCTL_MPE; 2278 1.5.2.2 skrll 2279 1.5.2.2 skrll setit: 2280 1.5.2.2 skrll CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2281 1.5.2.2 skrll } 2282 1.5.2.2 skrll 2283 1.5.2.2 skrll /* 2284 1.5.2.2 skrll * Read in the EEPROM info and verify checksum. 2285 1.5.2.2 skrll */ 2286 1.5.2.2 skrll int 2287 1.5.2.2 skrll dge_read_eeprom(struct dge_softc *sc) 2288 1.5.2.2 skrll { 2289 1.5.2.2 skrll uint16_t cksum; 2290 1.5.2.2 skrll int i; 2291 1.5.2.2 skrll 2292 1.5.2.2 skrll cksum = 0; 2293 1.5.2.2 skrll for (i = 0; i < EEPROM_SIZE; i++) { 2294 1.5.2.2 skrll sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2295 1.5.2.2 skrll cksum += sc->sc_eeprom[i]; 2296 1.5.2.2 skrll } 2297 1.5.2.2 skrll return cksum != EEPROM_CKSUM; 2298 1.5.2.2 skrll } 2299 1.5.2.2 skrll 2300 1.5.2.2 skrll 2301 1.5.2.2 skrll /* 2302 1.5.2.2 skrll * Read a 16-bit word from address addr in the serial EEPROM. 2303 1.5.2.2 skrll */ 2304 1.5.2.2 skrll uint16_t 2305 1.5.2.2 skrll dge_eeprom_word(struct dge_softc *sc, int addr) 2306 1.5.2.2 skrll { 2307 1.5.2.2 skrll uint32_t reg; 2308 1.5.2.2 skrll uint16_t rval = 0; 2309 1.5.2.2 skrll int i; 2310 1.5.2.2 skrll 2311 1.5.2.2 skrll reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2312 1.5.2.2 skrll 2313 1.5.2.2 skrll /* Lower clock pulse (and data in to chip) */ 2314 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg); 2315 1.5.2.2 skrll /* Select chip */ 2316 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2317 1.5.2.2 skrll 2318 1.5.2.2 skrll /* Send read command */ 2319 1.5.2.2 skrll dge_eeprom_clockout(sc, 1); 2320 1.5.2.2 skrll dge_eeprom_clockout(sc, 1); 2321 1.5.2.2 skrll dge_eeprom_clockout(sc, 0); 2322 1.5.2.2 skrll 2323 1.5.2.2 skrll /* Send address */ 2324 1.5.2.2 skrll for (i = 5; i >= 0; i--) 2325 1.5.2.2 skrll dge_eeprom_clockout(sc, (addr >> i) & 1); 2326 1.5.2.2 skrll 2327 1.5.2.2 skrll /* Read data */ 2328 1.5.2.2 skrll for (i = 0; i < 16; i++) { 2329 1.5.2.2 skrll rval <<= 1; 2330 1.5.2.2 skrll rval |= dge_eeprom_clockin(sc); 2331 1.5.2.2 skrll } 2332 1.5.2.2 skrll 2333 1.5.2.2 skrll /* Deselect chip */ 2334 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg); 2335 1.5.2.2 skrll 2336 1.5.2.2 skrll return rval; 2337 1.5.2.2 skrll } 2338 1.5.2.2 skrll 2339 1.5.2.2 skrll /* 2340 1.5.2.2 skrll * Clock out a single bit to the EEPROM. 2341 1.5.2.2 skrll */ 2342 1.5.2.2 skrll void 2343 1.5.2.2 skrll dge_eeprom_clockout(struct dge_softc *sc, int bit) 2344 1.5.2.2 skrll { 2345 1.5.2.2 skrll int reg; 2346 1.5.2.2 skrll 2347 1.5.2.2 skrll reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2348 1.5.2.2 skrll if (bit) 2349 1.5.2.2 skrll reg |= EECD_DI; 2350 1.5.2.2 skrll 2351 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg); 2352 1.5.2.2 skrll delay(2); 2353 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2354 1.5.2.2 skrll delay(2); 2355 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg); 2356 1.5.2.2 skrll delay(2); 2357 1.5.2.2 skrll } 2358 1.5.2.2 skrll 2359 1.5.2.2 skrll /* 2360 1.5.2.2 skrll * Clock in a single bit from EEPROM. 2361 1.5.2.2 skrll */ 2362 1.5.2.2 skrll int 2363 1.5.2.2 skrll dge_eeprom_clockin(struct dge_softc *sc) 2364 1.5.2.2 skrll { 2365 1.5.2.2 skrll int reg, rv; 2366 1.5.2.2 skrll 2367 1.5.2.2 skrll reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2368 1.5.2.2 skrll 2369 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2370 1.5.2.2 skrll delay(2); 2371 1.5.2.2 skrll rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2372 1.5.2.2 skrll CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2373 1.5.2.2 skrll delay(2); 2374 1.5.2.2 skrll 2375 1.5.2.2 skrll return rv; 2376 1.5.2.2 skrll } 2377 1.5.2.2 skrll 2378 1.5.2.2 skrll static void 2379 1.5.2.2 skrll dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2380 1.5.2.2 skrll { 2381 1.5.2.2 skrll struct dge_softc *sc = ifp->if_softc; 2382 1.5.2.2 skrll 2383 1.5.2.2 skrll ifmr->ifm_status = IFM_AVALID; 2384 1.5.2.2 skrll ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2385 1.5.2.2 skrll 2386 1.5.2.2 skrll if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2387 1.5.2.2 skrll ifmr->ifm_status |= IFM_ACTIVE; 2388 1.5.2.2 skrll } 2389 1.5.2.2 skrll 2390 1.5.2.2 skrll static inline int 2391 1.5.2.2 skrll phwait(struct dge_softc *sc, int p, int r, int d, int type) 2392 1.5.2.2 skrll { 2393 1.5.2.2 skrll int i, mdic; 2394 1.5.2.2 skrll 2395 1.5.2.2 skrll CSR_WRITE(sc, DGE_MDIO, 2396 1.5.2.2 skrll MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2397 1.5.2.2 skrll for (i = 0; i < 10; i++) { 2398 1.5.2.2 skrll delay(10); 2399 1.5.2.2 skrll if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2400 1.5.2.2 skrll break; 2401 1.5.2.2 skrll } 2402 1.5.2.2 skrll return mdic; 2403 1.5.2.2 skrll } 2404 1.5.2.2 skrll 2405 1.5.2.2 skrll 2406 1.5.2.2 skrll static void 2407 1.5.2.2 skrll dge_xgmii_writereg(struct device *self, int phy, int reg, int val) 2408 1.5.2.2 skrll { 2409 1.5.2.2 skrll struct dge_softc *sc = (void *) self; 2410 1.5.2.2 skrll int mdic; 2411 1.5.2.2 skrll 2412 1.5.2.2 skrll CSR_WRITE(sc, DGE_MDIRW, val); 2413 1.5.2.2 skrll if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2414 1.5.2.2 skrll printf("%s: address cycle timeout; phy %d reg %d\n", 2415 1.5.2.2 skrll sc->sc_dev.dv_xname, phy, reg); 2416 1.5.2.2 skrll return; 2417 1.5.2.2 skrll } 2418 1.5.2.2 skrll if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2419 1.5.2.2 skrll printf("%s: read cycle timeout; phy %d reg %d\n", 2420 1.5.2.2 skrll sc->sc_dev.dv_xname, phy, reg); 2421 1.5.2.2 skrll return; 2422 1.5.2.2 skrll } 2423 1.5.2.2 skrll } 2424 1.5.2.2 skrll 2425 1.5.2.2 skrll static void 2426 1.5.2.2 skrll dge_xgmii_reset(struct dge_softc *sc) 2427 1.5.2.2 skrll { 2428 1.5.2.2 skrll dge_xgmii_writereg((void *)sc, 0, 0, BMCR_RESET); 2429 1.5.2.2 skrll } 2430 1.5.2.2 skrll 2431 1.5.2.2 skrll static int 2432 1.5.2.2 skrll dge_xgmii_mediachange(struct ifnet *ifp) 2433 1.5.2.2 skrll { 2434 1.5.2.2 skrll return 0; 2435 1.5.2.2 skrll } 2436
Indexes created Thu Oct 02 01:09:59 GMT 2025