if_dge.c revision 1.7
1 /* $NetBSD: if_dge.c,v 1.7 2004/10/30 18:09:22 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.7 2004/10/30 18:09:22 thorpej Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <netinet/in.h> /* XXX for struct ip */ 116 #include <netinet/in_systm.h> /* XXX for struct ip */ 117 #include <netinet/ip.h> /* XXX for struct ip */ 118 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 #include <machine/endian.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/mii_bitbang.h> 127 128 #include <dev/pci/pcireg.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/pcidevs.h> 131 132 #include <dev/pci/if_dgereg.h> 133 134 /* 135 * The receive engine may sometimes become off-by-one when writing back 136 * chained descriptors. Avoid this by allocating a large chunk of 137 * memory and use if instead (to avoid chained descriptors). 138 * This only happens with chained descriptors under heavy load. 139 */ 140 #define DGE_OFFBYONE_RXBUG 141 142 #define DGE_EVENT_COUNTERS 143 #define DGE_DEBUG 144 145 #ifdef DGE_DEBUG 146 #define DGE_DEBUG_LINK 0x01 147 #define DGE_DEBUG_TX 0x02 148 #define DGE_DEBUG_RX 0x04 149 #define DGE_DEBUG_CKSUM 0x08 150 int dge_debug = 0; 151 152 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 153 #else 154 #define DPRINTF(x, y) /* nothing */ 155 #endif /* DGE_DEBUG */ 156 157 /* 158 * Transmit descriptor list size. We allow up to 100 DMA segments per 159 * packet (Intel reports of jumbo frame packets with as 160 * many as 80 DMA segments when using 16k buffers). 161 */ 162 #define DGE_NTXSEGS 100 163 #define DGE_IFQUEUELEN 20000 164 #define DGE_TXQUEUELEN 2048 165 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 166 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 167 #define DGE_NTXDESC 1024 168 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 169 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 170 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 171 172 /* 173 * Receive descriptor list size. 174 * Packet is of size MCLBYTES, and for jumbo packets buffers may 175 * be chained. Due to the nature of the card (high-speed), keep this 176 * ring large. With 2k buffers the ring can store 400 jumbo packets, 177 * which at full speed will be received in just under 3ms. 178 */ 179 #define DGE_NRXDESC 2048 180 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 181 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 182 /* 183 * # of descriptors between head and written descriptors. 184 * This is to work-around two erratas. 185 */ 186 #define DGE_RXSPACE 10 187 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 188 /* 189 * Receive descriptor fetch threshholds. These are values recommended 190 * by Intel, do not touch them unless you know what you are doing. 191 */ 192 #define RXDCTL_PTHRESH_VAL 128 193 #define RXDCTL_HTHRESH_VAL 16 194 #define RXDCTL_WTHRESH_VAL 16 195 196 197 /* 198 * Tweakable parameters; default values. 199 */ 200 #define FCRTH 0x30000 /* Send XOFF water mark */ 201 #define FCRTL 0x28000 /* Send XON water mark */ 202 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 203 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 204 205 /* 206 * Control structures are DMA'd to the i82597 chip. We allocate them in 207 * a single clump that maps to a single DMA segment to make serveral things 208 * easier. 209 */ 210 struct dge_control_data { 211 /* 212 * The transmit descriptors. 213 */ 214 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 215 216 /* 217 * The receive descriptors. 218 */ 219 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 220 }; 221 222 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 223 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 224 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 225 226 /* 227 * The DGE interface have a higher max MTU size than normal jumbo frames. 228 */ 229 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 230 231 /* 232 * Software state for transmit jobs. 233 */ 234 struct dge_txsoft { 235 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 236 bus_dmamap_t txs_dmamap; /* our DMA map */ 237 int txs_firstdesc; /* first descriptor in packet */ 238 int txs_lastdesc; /* last descriptor in packet */ 239 int txs_ndesc; /* # of descriptors used */ 240 }; 241 242 /* 243 * Software state for receive buffers. Each descriptor gets a 244 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 245 * more than one buffer, we chain them together. 246 */ 247 struct dge_rxsoft { 248 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 249 bus_dmamap_t rxs_dmamap; /* our DMA map */ 250 }; 251 252 /* 253 * Software state per device. 254 */ 255 struct dge_softc { 256 struct device sc_dev; /* generic device information */ 257 bus_space_tag_t sc_st; /* bus space tag */ 258 bus_space_handle_t sc_sh; /* bus space handle */ 259 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 260 struct ethercom sc_ethercom; /* ethernet common data */ 261 void *sc_sdhook; /* shutdown hook */ 262 263 int sc_flags; /* flags; see below */ 264 int sc_bus_speed; /* PCI/PCIX bus speed */ 265 int sc_pcix_offset; /* PCIX capability register offset */ 266 267 pci_chipset_tag_t sc_pc; 268 pcitag_t sc_pt; 269 int sc_mmrbc; /* Max PCIX memory read byte count */ 270 271 void *sc_ih; /* interrupt cookie */ 272 273 struct ifmedia sc_media; 274 275 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 276 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 277 278 int sc_align_tweak; 279 280 /* 281 * Software state for the transmit and receive descriptors. 282 */ 283 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 284 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 285 286 /* 287 * Control data structures. 288 */ 289 struct dge_control_data *sc_control_data; 290 #define sc_txdescs sc_control_data->wcd_txdescs 291 #define sc_rxdescs sc_control_data->wcd_rxdescs 292 293 #ifdef DGE_EVENT_COUNTERS 294 /* Event counters. */ 295 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 296 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 297 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 298 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 299 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 300 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 301 struct evcnt sc_ev_linkintr; /* Link interrupts */ 302 303 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 304 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 305 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 306 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 307 308 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 309 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 310 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 311 312 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 313 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 314 #endif /* DGE_EVENT_COUNTERS */ 315 316 int sc_txfree; /* number of free Tx descriptors */ 317 int sc_txnext; /* next ready Tx descriptor */ 318 319 int sc_txsfree; /* number of free Tx jobs */ 320 int sc_txsnext; /* next free Tx job */ 321 int sc_txsdirty; /* dirty Tx jobs */ 322 323 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 324 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 325 326 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 327 int sc_rxdiscard; 328 int sc_rxlen; 329 struct mbuf *sc_rxhead; 330 struct mbuf *sc_rxtail; 331 struct mbuf **sc_rxtailp; 332 333 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 334 uint32_t sc_icr; /* prototype interrupt bits */ 335 uint32_t sc_tctl; /* prototype TCTL register */ 336 uint32_t sc_rctl; /* prototype RCTL register */ 337 338 int sc_mchash_type; /* multicast filter offset */ 339 340 uint16_t sc_eeprom[EEPROM_SIZE]; 341 342 #if NRND > 0 343 rndsource_element_t rnd_source; /* random source */ 344 #endif 345 #ifdef DGE_OFFBYONE_RXBUG 346 caddr_t sc_bugbuf; 347 SLIST_HEAD(, rxbugentry) sc_buglist; 348 bus_dmamap_t sc_bugmap; 349 struct rxbugentry *sc_entry; 350 #endif 351 }; 352 353 #define DGE_RXCHAIN_RESET(sc) \ 354 do { \ 355 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 356 *(sc)->sc_rxtailp = NULL; \ 357 (sc)->sc_rxlen = 0; \ 358 } while (/*CONSTCOND*/0) 359 360 #define DGE_RXCHAIN_LINK(sc, m) \ 361 do { \ 362 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 363 (sc)->sc_rxtailp = &(m)->m_next; \ 364 } while (/*CONSTCOND*/0) 365 366 /* sc_flags */ 367 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 368 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 369 370 #ifdef DGE_EVENT_COUNTERS 371 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 372 #else 373 #define DGE_EVCNT_INCR(ev) /* nothing */ 374 #endif 375 376 #define CSR_READ(sc, reg) \ 377 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 #define CSR_WRITE(sc, reg, val) \ 379 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 381 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 382 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 383 384 #define DGE_CDTXSYNC(sc, x, n, ops) \ 385 do { \ 386 int __x, __n; \ 387 \ 388 __x = (x); \ 389 __n = (n); \ 390 \ 391 /* If it will wrap around, sync to the end of the ring. */ \ 392 if ((__x + __n) > DGE_NTXDESC) { \ 393 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 394 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 395 (DGE_NTXDESC - __x), (ops)); \ 396 __n -= (DGE_NTXDESC - __x); \ 397 __x = 0; \ 398 } \ 399 \ 400 /* Now sync whatever is left. */ \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 403 } while (/*CONSTCOND*/0) 404 405 #define DGE_CDRXSYNC(sc, x, ops) \ 406 do { \ 407 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 408 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 409 } while (/*CONSTCOND*/0) 410 411 #ifdef DGE_OFFBYONE_RXBUG 412 #define DGE_INIT_RXDESC(sc, x) \ 413 do { \ 414 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 415 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 416 struct mbuf *__m = __rxs->rxs_mbuf; \ 417 \ 418 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 419 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 420 __rxd->dr_baddrh = 0; \ 421 __rxd->dr_len = 0; \ 422 __rxd->dr_cksum = 0; \ 423 __rxd->dr_status = 0; \ 424 __rxd->dr_errors = 0; \ 425 __rxd->dr_special = 0; \ 426 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 427 \ 428 CSR_WRITE((sc), DGE_RDT, (x)); \ 429 } while (/*CONSTCOND*/0) 430 #else 431 #define DGE_INIT_RXDESC(sc, x) \ 432 do { \ 433 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 434 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 435 struct mbuf *__m = __rxs->rxs_mbuf; \ 436 \ 437 /* \ 438 * Note: We scoot the packet forward 2 bytes in the buffer \ 439 * so that the payload after the Ethernet header is aligned \ 440 * to a 4-byte boundary. \ 441 * \ 442 * XXX BRAINDAMAGE ALERT! \ 443 * The stupid chip uses the same size for every buffer, which \ 444 * is set in the Receive Control register. We are using the 2K \ 445 * size option, but what we REALLY want is (2K - 2)! For this \ 446 * reason, we can't "scoot" packets longer than the standard \ 447 * Ethernet MTU. On strict-alignment platforms, if the total \ 448 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 449 * the upper layer copy the headers. \ 450 */ \ 451 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 452 \ 453 __rxd->dr_baddrl = \ 454 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 455 (sc)->sc_align_tweak); \ 456 __rxd->dr_baddrh = 0; \ 457 __rxd->dr_len = 0; \ 458 __rxd->dr_cksum = 0; \ 459 __rxd->dr_status = 0; \ 460 __rxd->dr_errors = 0; \ 461 __rxd->dr_special = 0; \ 462 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 463 \ 464 CSR_WRITE((sc), DGE_RDT, (x)); \ 465 } while (/*CONSTCOND*/0) 466 #endif 467 468 #ifdef DGE_OFFBYONE_RXBUG 469 /* 470 * Allocation constants. Much memory may be used for this. 471 */ 472 #ifndef DGE_BUFFER_SIZE 473 #define DGE_BUFFER_SIZE DGE_MAX_MTU 474 #endif 475 #define DGE_NBUFFERS (4*DGE_NRXDESC) 476 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 477 478 struct rxbugentry { 479 SLIST_ENTRY(rxbugentry) rb_entry; 480 int rb_slot; 481 }; 482 483 static int 484 dge_alloc_rcvmem(struct dge_softc *sc) 485 { 486 caddr_t ptr, kva; 487 bus_dma_segment_t seg; 488 int i, rseg, state, error; 489 struct rxbugentry *entry; 490 491 state = error = 0; 492 493 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 494 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 495 printf("%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname); 496 return ENOBUFS; 497 } 498 499 state = 1; 500 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, &kva, 501 BUS_DMA_NOWAIT)) { 502 printf("%s: can't map DMA buffers (%d bytes)\n", 503 sc->sc_dev.dv_xname, (int)DGE_RXMEM); 504 error = ENOBUFS; 505 goto out; 506 } 507 508 state = 2; 509 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 510 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 511 printf("%s: can't create DMA map\n", sc->sc_dev.dv_xname); 512 error = ENOBUFS; 513 goto out; 514 } 515 516 state = 3; 517 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 518 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 519 printf("%s: can't load DMA map\n", sc->sc_dev.dv_xname); 520 error = ENOBUFS; 521 goto out; 522 } 523 524 state = 4; 525 sc->sc_bugbuf = (caddr_t)kva; 526 SLIST_INIT(&sc->sc_buglist); 527 528 /* 529 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 530 * in an array. 531 */ 532 ptr = sc->sc_bugbuf; 533 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 534 M_DEVBUF, M_NOWAIT)) == NULL) { 535 error = ENOBUFS; 536 goto out; 537 } 538 sc->sc_entry = entry; 539 for (i = 0; i < DGE_NBUFFERS; i++) { 540 entry[i].rb_slot = i; 541 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 542 } 543 out: 544 if (error != 0) { 545 switch (state) { 546 case 4: 547 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 548 case 3: 549 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 550 case 2: 551 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 552 case 1: 553 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 554 break; 555 default: 556 break; 557 } 558 } 559 560 return error; 561 } 562 563 /* 564 * Allocate a jumbo buffer. 565 */ 566 static void * 567 dge_getbuf(struct dge_softc *sc) 568 { 569 struct rxbugentry *entry; 570 571 entry = SLIST_FIRST(&sc->sc_buglist); 572 573 if (entry == NULL) { 574 printf("%s: no free RX buffers\n", sc->sc_dev.dv_xname); 575 return(NULL); 576 } 577 578 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 579 return sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 580 } 581 582 /* 583 * Release a jumbo buffer. 584 */ 585 static void 586 dge_freebuf(struct mbuf *m, caddr_t buf, size_t size, void *arg) 587 { 588 struct rxbugentry *entry; 589 struct dge_softc *sc; 590 int i, s; 591 592 /* Extract the softc struct pointer. */ 593 sc = (struct dge_softc *)arg; 594 595 if (sc == NULL) 596 panic("dge_freebuf: can't find softc pointer!"); 597 598 /* calculate the slot this buffer belongs to */ 599 600 i = (buf - sc->sc_bugbuf) / DGE_BUFFER_SIZE; 601 602 if ((i < 0) || (i >= DGE_NBUFFERS)) 603 panic("dge_freebuf: asked to free buffer %d!", i); 604 605 s = splvm(); 606 entry = sc->sc_entry + i; 607 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 608 609 if (__predict_true(m != NULL)) 610 pool_cache_put(&mbpool_cache, m); 611 splx(s); 612 } 613 #endif 614 615 static void dge_start(struct ifnet *); 616 static void dge_watchdog(struct ifnet *); 617 static int dge_ioctl(struct ifnet *, u_long, caddr_t); 618 static int dge_init(struct ifnet *); 619 static void dge_stop(struct ifnet *, int); 620 621 static void dge_shutdown(void *); 622 623 static void dge_reset(struct dge_softc *); 624 static void dge_rxdrain(struct dge_softc *); 625 static int dge_add_rxbuf(struct dge_softc *, int); 626 627 static void dge_set_filter(struct dge_softc *); 628 629 static int dge_intr(void *); 630 static void dge_txintr(struct dge_softc *); 631 static void dge_rxintr(struct dge_softc *); 632 static void dge_linkintr(struct dge_softc *, uint32_t); 633 634 static int dge_match(struct device *, struct cfdata *, void *); 635 static void dge_attach(struct device *, struct device *, void *); 636 637 static int dge_read_eeprom(struct dge_softc *sc); 638 static int dge_eeprom_clockin(struct dge_softc *sc); 639 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 640 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 641 static int dge_xgmii_mediachange(struct ifnet *); 642 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 643 static void dge_xgmii_reset(struct dge_softc *); 644 static void dge_xgmii_writereg(struct device *, int, int, int); 645 646 647 CFATTACH_DECL(dge, sizeof(struct dge_softc), 648 dge_match, dge_attach, NULL, NULL); 649 650 #ifdef DGE_EVENT_COUNTERS 651 #if DGE_NTXSEGS > 100 652 #error Update dge_txseg_evcnt_names 653 #endif 654 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 655 #endif /* DGE_EVENT_COUNTERS */ 656 657 static int 658 dge_match(struct device *parent, struct cfdata *cf, void *aux) 659 { 660 struct pci_attach_args *pa = aux; 661 662 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 663 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82597EX) 664 return (1); 665 666 return (0); 667 } 668 669 static void 670 dge_attach(struct device *parent, struct device *self, void *aux) 671 { 672 struct dge_softc *sc = (void *) self; 673 struct pci_attach_args *pa = aux; 674 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 675 pci_chipset_tag_t pc = pa->pa_pc; 676 pci_intr_handle_t ih; 677 const char *intrstr = NULL; 678 bus_dma_segment_t seg; 679 int i, rseg, error; 680 uint8_t enaddr[ETHER_ADDR_LEN]; 681 pcireg_t preg, memtype; 682 uint32_t reg; 683 684 sc->sc_dmat = pa->pa_dmat; 685 sc->sc_pc = pa->pa_pc; 686 sc->sc_pt = pa->pa_tag; 687 688 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 689 aprint_naive(": Ethernet controller\n"); 690 aprint_normal(": Intel i82597EX 10GbE-LR Ethernet, rev. %d\n", preg); 691 692 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 693 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 694 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 695 aprint_error("%s: unable to map device registers\n", 696 sc->sc_dev.dv_xname); 697 return; 698 } 699 700 /* Enable bus mastering */ 701 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 702 preg |= PCI_COMMAND_MASTER_ENABLE; 703 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 704 705 /* 706 * Map and establish our interrupt. 707 */ 708 if (pci_intr_map(pa, &ih)) { 709 aprint_error("%s: unable to map interrupt\n", 710 sc->sc_dev.dv_xname); 711 return; 712 } 713 intrstr = pci_intr_string(pc, ih); 714 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 715 if (sc->sc_ih == NULL) { 716 aprint_error("%s: unable to establish interrupt", 717 sc->sc_dev.dv_xname); 718 if (intrstr != NULL) 719 aprint_normal(" at %s", intrstr); 720 aprint_normal("\n"); 721 return; 722 } 723 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 724 725 /* 726 * Determine a few things about the bus we're connected to. 727 */ 728 reg = CSR_READ(sc, DGE_STATUS); 729 if (reg & STATUS_BUS64) 730 sc->sc_flags |= DGE_F_BUS64; 731 732 sc->sc_flags |= DGE_F_PCIX; 733 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 734 PCI_CAP_PCIX, 735 &sc->sc_pcix_offset, NULL) == 0) 736 aprint_error("%s: unable to find PCIX " 737 "capability\n", sc->sc_dev.dv_xname); 738 739 if (sc->sc_flags & DGE_F_PCIX) { 740 switch (reg & STATUS_PCIX_MSK) { 741 case STATUS_PCIX_66: 742 sc->sc_bus_speed = 66; 743 break; 744 case STATUS_PCIX_100: 745 sc->sc_bus_speed = 100; 746 break; 747 case STATUS_PCIX_133: 748 sc->sc_bus_speed = 133; 749 break; 750 default: 751 aprint_error( 752 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 753 sc->sc_dev.dv_xname, 754 reg & STATUS_PCIX_MSK); 755 sc->sc_bus_speed = 66; 756 } 757 } else 758 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 759 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 760 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 761 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 762 763 /* 764 * Allocate the control data structures, and create and load the 765 * DMA map for it. 766 */ 767 if ((error = bus_dmamem_alloc(sc->sc_dmat, 768 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 769 0)) != 0) { 770 aprint_error( 771 "%s: unable to allocate control data, error = %d\n", 772 sc->sc_dev.dv_xname, error); 773 goto fail_0; 774 } 775 776 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 777 sizeof(struct dge_control_data), (caddr_t *)&sc->sc_control_data, 778 0)) != 0) { 779 aprint_error("%s: unable to map control data, error = %d\n", 780 sc->sc_dev.dv_xname, error); 781 goto fail_1; 782 } 783 784 if ((error = bus_dmamap_create(sc->sc_dmat, 785 sizeof(struct dge_control_data), 1, 786 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 787 aprint_error("%s: unable to create control data DMA map, " 788 "error = %d\n", sc->sc_dev.dv_xname, error); 789 goto fail_2; 790 } 791 792 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 793 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 794 0)) != 0) { 795 aprint_error( 796 "%s: unable to load control data DMA map, error = %d\n", 797 sc->sc_dev.dv_xname, error); 798 goto fail_3; 799 } 800 801 #ifdef DGE_OFFBYONE_RXBUG 802 if (dge_alloc_rcvmem(sc) != 0) 803 return; /* Already complained */ 804 #endif 805 /* 806 * Create the transmit buffer DMA maps. 807 */ 808 for (i = 0; i < DGE_TXQUEUELEN; i++) { 809 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 810 DGE_NTXSEGS, MCLBYTES, 0, 0, 811 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 812 aprint_error("%s: unable to create Tx DMA map %d, " 813 "error = %d\n", sc->sc_dev.dv_xname, i, error); 814 goto fail_4; 815 } 816 } 817 818 /* 819 * Create the receive buffer DMA maps. 820 */ 821 for (i = 0; i < DGE_NRXDESC; i++) { 822 #ifdef DGE_OFFBYONE_RXBUG 823 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 824 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 825 #else 826 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 827 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 828 #endif 829 aprint_error("%s: unable to create Rx DMA map %d, " 830 "error = %d\n", sc->sc_dev.dv_xname, i, error); 831 goto fail_5; 832 } 833 sc->sc_rxsoft[i].rxs_mbuf = NULL; 834 } 835 836 /* 837 * Set bits in ctrl0 register. 838 * Should get the software defined pins out of EEPROM? 839 */ 840 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 841 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 842 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 843 844 /* 845 * Reset the chip to a known state. 846 */ 847 dge_reset(sc); 848 849 /* 850 * Reset the PHY. 851 */ 852 dge_xgmii_reset(sc); 853 854 /* 855 * Read in EEPROM data. 856 */ 857 if (dge_read_eeprom(sc)) { 858 aprint_error("%s: couldn't read EEPROM\n", sc->sc_dev.dv_xname); 859 return; 860 } 861 862 /* 863 * Get the ethernet address. 864 */ 865 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 866 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 867 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 868 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 869 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 870 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 871 872 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 873 ether_sprintf(enaddr)); 874 875 /* 876 * Setup media stuff. 877 */ 878 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 879 dge_xgmii_mediastatus); 880 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 881 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 882 883 ifp = &sc->sc_ethercom.ec_if; 884 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 885 ifp->if_softc = sc; 886 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 887 ifp->if_ioctl = dge_ioctl; 888 ifp->if_start = dge_start; 889 ifp->if_watchdog = dge_watchdog; 890 ifp->if_init = dge_init; 891 ifp->if_stop = dge_stop; 892 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 893 IFQ_SET_READY(&ifp->if_snd); 894 895 sc->sc_ethercom.ec_capabilities |= 896 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 897 898 /* 899 * We can perform TCPv4 and UDPv4 checkums in-bound. 900 */ 901 ifp->if_capabilities |= 902 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 903 904 /* 905 * Attach the interface. 906 */ 907 if_attach(ifp); 908 ether_ifattach(ifp, enaddr); 909 #if NRND > 0 910 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 911 RND_TYPE_NET, 0); 912 #endif 913 914 #ifdef DGE_EVENT_COUNTERS 915 /* Fix segment event naming */ 916 if (dge_txseg_evcnt_names == NULL) { 917 dge_txseg_evcnt_names = 918 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 919 for (i = 0; i < DGE_NTXSEGS; i++) 920 snprintf((*dge_txseg_evcnt_names)[i], 921 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 922 } 923 924 /* Attach event counters. */ 925 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 926 NULL, sc->sc_dev.dv_xname, "txsstall"); 927 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 928 NULL, sc->sc_dev.dv_xname, "txdstall"); 929 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 930 NULL, sc->sc_dev.dv_xname, "txforceintr"); 931 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 932 NULL, sc->sc_dev.dv_xname, "txdw"); 933 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 934 NULL, sc->sc_dev.dv_xname, "txqe"); 935 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 936 NULL, sc->sc_dev.dv_xname, "rxintr"); 937 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 938 NULL, sc->sc_dev.dv_xname, "linkintr"); 939 940 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 941 NULL, sc->sc_dev.dv_xname, "rxipsum"); 942 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 943 NULL, sc->sc_dev.dv_xname, "rxtusum"); 944 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 945 NULL, sc->sc_dev.dv_xname, "txipsum"); 946 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 947 NULL, sc->sc_dev.dv_xname, "txtusum"); 948 949 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 950 NULL, sc->sc_dev.dv_xname, "txctx init"); 951 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 952 NULL, sc->sc_dev.dv_xname, "txctx hit"); 953 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 954 NULL, sc->sc_dev.dv_xname, "txctx miss"); 955 956 for (i = 0; i < DGE_NTXSEGS; i++) 957 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 958 NULL, sc->sc_dev.dv_xname, (*dge_txseg_evcnt_names)[i]); 959 960 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 961 NULL, sc->sc_dev.dv_xname, "txdrop"); 962 963 #endif /* DGE_EVENT_COUNTERS */ 964 965 /* 966 * Make sure the interface is shutdown during reboot. 967 */ 968 sc->sc_sdhook = shutdownhook_establish(dge_shutdown, sc); 969 if (sc->sc_sdhook == NULL) 970 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 971 sc->sc_dev.dv_xname); 972 return; 973 974 /* 975 * Free any resources we've allocated during the failed attach 976 * attempt. Do this in reverse order and fall through. 977 */ 978 fail_5: 979 for (i = 0; i < DGE_NRXDESC; i++) { 980 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 981 bus_dmamap_destroy(sc->sc_dmat, 982 sc->sc_rxsoft[i].rxs_dmamap); 983 } 984 fail_4: 985 for (i = 0; i < DGE_TXQUEUELEN; i++) { 986 if (sc->sc_txsoft[i].txs_dmamap != NULL) 987 bus_dmamap_destroy(sc->sc_dmat, 988 sc->sc_txsoft[i].txs_dmamap); 989 } 990 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 991 fail_3: 992 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 993 fail_2: 994 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 995 sizeof(struct dge_control_data)); 996 fail_1: 997 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 998 fail_0: 999 return; 1000 } 1001 1002 /* 1003 * dge_shutdown: 1004 * 1005 * Make sure the interface is stopped at reboot time. 1006 */ 1007 static void 1008 dge_shutdown(void *arg) 1009 { 1010 struct dge_softc *sc = arg; 1011 1012 dge_stop(&sc->sc_ethercom.ec_if, 1); 1013 } 1014 1015 /* 1016 * dge_tx_cksum: 1017 * 1018 * Set up TCP/IP checksumming parameters for the 1019 * specified packet. 1020 */ 1021 static int 1022 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1023 { 1024 struct mbuf *m0 = txs->txs_mbuf; 1025 struct dge_ctdes *t; 1026 uint32_t ipcs, tucs; 1027 struct ip *ip; 1028 struct ether_header *eh; 1029 int offset, iphl; 1030 uint8_t fields = 0; 1031 1032 /* 1033 * XXX It would be nice if the mbuf pkthdr had offset 1034 * fields for the protocol headers. 1035 */ 1036 1037 eh = mtod(m0, struct ether_header *); 1038 switch (htons(eh->ether_type)) { 1039 case ETHERTYPE_IP: 1040 iphl = sizeof(struct ip); 1041 offset = ETHER_HDR_LEN; 1042 break; 1043 1044 case ETHERTYPE_VLAN: 1045 iphl = sizeof(struct ip); 1046 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1047 break; 1048 1049 default: 1050 /* 1051 * Don't support this protocol or encapsulation. 1052 */ 1053 *fieldsp = 0; 1054 return (0); 1055 } 1056 1057 if (m0->m_len < (offset + iphl)) { 1058 if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1059 printf("%s: dge_tx_cksum: mbuf allocation failed, " 1060 "packet dropped\n", sc->sc_dev.dv_xname); 1061 return (ENOMEM); 1062 } 1063 m0 = txs->txs_mbuf; 1064 } 1065 1066 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1067 iphl = ip->ip_hl << 2; 1068 1069 /* 1070 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1071 * offload feature, if we load the context descriptor, we 1072 * MUST provide valid values for IPCSS and TUCSS fields. 1073 */ 1074 1075 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1076 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1077 fields |= TDESC_POPTS_IXSM; 1078 ipcs = DGE_TCPIP_IPCSS(offset) | 1079 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1080 DGE_TCPIP_IPCSE(offset + iphl - 1); 1081 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1082 /* Use the cached value. */ 1083 ipcs = sc->sc_txctx_ipcs; 1084 } else { 1085 /* Just initialize it to the likely value anyway. */ 1086 ipcs = DGE_TCPIP_IPCSS(offset) | 1087 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1088 DGE_TCPIP_IPCSE(offset + iphl - 1); 1089 } 1090 DPRINTF(DGE_DEBUG_CKSUM, 1091 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1092 sc->sc_dev.dv_xname, offset, ipcs)); 1093 1094 offset += iphl; 1095 1096 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1097 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1098 fields |= TDESC_POPTS_TXSM; 1099 tucs = DGE_TCPIP_TUCSS(offset) | 1100 DGE_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1101 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1102 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1103 /* Use the cached value. */ 1104 tucs = sc->sc_txctx_tucs; 1105 } else { 1106 /* Just initialize it to a valid TCP context. */ 1107 tucs = DGE_TCPIP_TUCSS(offset) | 1108 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1109 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1110 } 1111 1112 DPRINTF(DGE_DEBUG_CKSUM, 1113 ("%s: CKSUM: offset %d tucs 0x%x\n", 1114 sc->sc_dev.dv_xname, offset, tucs)); 1115 1116 if (sc->sc_txctx_ipcs == ipcs && 1117 sc->sc_txctx_tucs == tucs) { 1118 /* Cached context is fine. */ 1119 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1120 } else { 1121 /* Fill in the context descriptor. */ 1122 #ifdef DGE_EVENT_COUNTERS 1123 if (sc->sc_txctx_ipcs == 0xffffffff && 1124 sc->sc_txctx_tucs == 0xffffffff) 1125 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1126 else 1127 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1128 #endif 1129 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1130 t->dc_tcpip_ipcs = htole32(ipcs); 1131 t->dc_tcpip_tucs = htole32(tucs); 1132 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1133 t->dc_tcpip_seg = 0; 1134 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1135 1136 sc->sc_txctx_ipcs = ipcs; 1137 sc->sc_txctx_tucs = tucs; 1138 1139 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1140 txs->txs_ndesc++; 1141 } 1142 1143 *fieldsp = fields; 1144 1145 return (0); 1146 } 1147 1148 /* 1149 * dge_start: [ifnet interface function] 1150 * 1151 * Start packet transmission on the interface. 1152 */ 1153 static void 1154 dge_start(struct ifnet *ifp) 1155 { 1156 struct dge_softc *sc = ifp->if_softc; 1157 struct mbuf *m0; 1158 struct dge_txsoft *txs; 1159 bus_dmamap_t dmamap; 1160 int error, nexttx, lasttx = -1, ofree, seg; 1161 uint32_t cksumcmd; 1162 uint8_t cksumfields; 1163 1164 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1165 return; 1166 1167 /* 1168 * Remember the previous number of free descriptors. 1169 */ 1170 ofree = sc->sc_txfree; 1171 1172 /* 1173 * Loop through the send queue, setting up transmit descriptors 1174 * until we drain the queue, or use up all available transmit 1175 * descriptors. 1176 */ 1177 for (;;) { 1178 /* Grab a packet off the queue. */ 1179 IFQ_POLL(&ifp->if_snd, m0); 1180 if (m0 == NULL) 1181 break; 1182 1183 DPRINTF(DGE_DEBUG_TX, 1184 ("%s: TX: have packet to transmit: %p\n", 1185 sc->sc_dev.dv_xname, m0)); 1186 1187 /* Get a work queue entry. */ 1188 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1189 dge_txintr(sc); 1190 if (sc->sc_txsfree == 0) { 1191 DPRINTF(DGE_DEBUG_TX, 1192 ("%s: TX: no free job descriptors\n", 1193 sc->sc_dev.dv_xname)); 1194 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1195 break; 1196 } 1197 } 1198 1199 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1200 dmamap = txs->txs_dmamap; 1201 1202 /* 1203 * Load the DMA map. If this fails, the packet either 1204 * didn't fit in the allotted number of segments, or we 1205 * were short on resources. For the too-many-segments 1206 * case, we simply report an error and drop the packet, 1207 * since we can't sanely copy a jumbo packet to a single 1208 * buffer. 1209 */ 1210 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1211 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1212 if (error) { 1213 if (error == EFBIG) { 1214 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1215 printf("%s: Tx packet consumes too many " 1216 "DMA segments, dropping...\n", 1217 sc->sc_dev.dv_xname); 1218 IFQ_DEQUEUE(&ifp->if_snd, m0); 1219 m_freem(m0); 1220 continue; 1221 } 1222 /* 1223 * Short on resources, just stop for now. 1224 */ 1225 DPRINTF(DGE_DEBUG_TX, 1226 ("%s: TX: dmamap load failed: %d\n", 1227 sc->sc_dev.dv_xname, error)); 1228 break; 1229 } 1230 1231 /* 1232 * Ensure we have enough descriptors free to describe 1233 * the packet. Note, we always reserve one descriptor 1234 * at the end of the ring due to the semantics of the 1235 * TDT register, plus one more in the event we need 1236 * to re-load checksum offload context. 1237 */ 1238 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1239 /* 1240 * Not enough free descriptors to transmit this 1241 * packet. We haven't committed anything yet, 1242 * so just unload the DMA map, put the packet 1243 * pack on the queue, and punt. Notify the upper 1244 * layer that there are no more slots left. 1245 */ 1246 DPRINTF(DGE_DEBUG_TX, 1247 ("%s: TX: need %d descriptors, have %d\n", 1248 sc->sc_dev.dv_xname, dmamap->dm_nsegs, 1249 sc->sc_txfree - 1)); 1250 ifp->if_flags |= IFF_OACTIVE; 1251 bus_dmamap_unload(sc->sc_dmat, dmamap); 1252 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1253 break; 1254 } 1255 1256 IFQ_DEQUEUE(&ifp->if_snd, m0); 1257 1258 /* 1259 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1260 */ 1261 1262 /* Sync the DMA map. */ 1263 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1264 BUS_DMASYNC_PREWRITE); 1265 1266 DPRINTF(DGE_DEBUG_TX, 1267 ("%s: TX: packet has %d DMA segments\n", 1268 sc->sc_dev.dv_xname, dmamap->dm_nsegs)); 1269 1270 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1271 1272 /* 1273 * Store a pointer to the packet so that we can free it 1274 * later. 1275 * 1276 * Initially, we consider the number of descriptors the 1277 * packet uses the number of DMA segments. This may be 1278 * incremented by 1 if we do checksum offload (a descriptor 1279 * is used to set the checksum context). 1280 */ 1281 txs->txs_mbuf = m0; 1282 txs->txs_firstdesc = sc->sc_txnext; 1283 txs->txs_ndesc = dmamap->dm_nsegs; 1284 1285 /* 1286 * Set up checksum offload parameters for 1287 * this packet. 1288 */ 1289 if (m0->m_pkthdr.csum_flags & 1290 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1291 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1292 /* Error message already displayed. */ 1293 bus_dmamap_unload(sc->sc_dmat, dmamap); 1294 continue; 1295 } 1296 } else { 1297 cksumfields = 0; 1298 } 1299 1300 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1301 1302 /* 1303 * Initialize the transmit descriptor. 1304 */ 1305 for (nexttx = sc->sc_txnext, seg = 0; 1306 seg < dmamap->dm_nsegs; 1307 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1308 /* 1309 * Note: we currently only use 32-bit DMA 1310 * addresses. 1311 */ 1312 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1313 sc->sc_txdescs[nexttx].dt_baddrl = 1314 htole32(dmamap->dm_segs[seg].ds_addr); 1315 sc->sc_txdescs[nexttx].dt_ctl = 1316 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1317 sc->sc_txdescs[nexttx].dt_status = 0; 1318 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1319 sc->sc_txdescs[nexttx].dt_vlan = 0; 1320 lasttx = nexttx; 1321 1322 DPRINTF(DGE_DEBUG_TX, 1323 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1324 sc->sc_dev.dv_xname, nexttx, 1325 le32toh(dmamap->dm_segs[seg].ds_addr), 1326 le32toh(dmamap->dm_segs[seg].ds_len))); 1327 } 1328 1329 KASSERT(lasttx != -1); 1330 1331 /* 1332 * Set up the command byte on the last descriptor of 1333 * the packet. If we're in the interrupt delay window, 1334 * delay the interrupt. 1335 */ 1336 sc->sc_txdescs[lasttx].dt_ctl |= 1337 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1338 1339 txs->txs_lastdesc = lasttx; 1340 1341 DPRINTF(DGE_DEBUG_TX, 1342 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1343 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1344 1345 /* Sync the descriptors we're using. */ 1346 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1347 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1348 1349 /* Give the packet to the chip. */ 1350 CSR_WRITE(sc, DGE_TDT, nexttx); 1351 1352 DPRINTF(DGE_DEBUG_TX, 1353 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1354 1355 DPRINTF(DGE_DEBUG_TX, 1356 ("%s: TX: finished transmitting packet, job %d\n", 1357 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1358 1359 /* Advance the tx pointer. */ 1360 sc->sc_txfree -= txs->txs_ndesc; 1361 sc->sc_txnext = nexttx; 1362 1363 sc->sc_txsfree--; 1364 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1365 1366 #if NBPFILTER > 0 1367 /* Pass the packet to any BPF listeners. */ 1368 if (ifp->if_bpf) 1369 bpf_mtap(ifp->if_bpf, m0); 1370 #endif /* NBPFILTER > 0 */ 1371 } 1372 1373 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1374 /* No more slots; notify upper layer. */ 1375 ifp->if_flags |= IFF_OACTIVE; 1376 } 1377 1378 if (sc->sc_txfree != ofree) { 1379 /* Set a watchdog timer in case the chip flakes out. */ 1380 ifp->if_timer = 5; 1381 } 1382 } 1383 1384 /* 1385 * dge_watchdog: [ifnet interface function] 1386 * 1387 * Watchdog timer handler. 1388 */ 1389 static void 1390 dge_watchdog(struct ifnet *ifp) 1391 { 1392 struct dge_softc *sc = ifp->if_softc; 1393 1394 /* 1395 * Since we're using delayed interrupts, sweep up 1396 * before we report an error. 1397 */ 1398 dge_txintr(sc); 1399 1400 if (sc->sc_txfree != DGE_NTXDESC) { 1401 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1402 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1403 sc->sc_txnext); 1404 ifp->if_oerrors++; 1405 1406 /* Reset the interface. */ 1407 (void) dge_init(ifp); 1408 } 1409 1410 /* Try to get more packets going. */ 1411 dge_start(ifp); 1412 } 1413 1414 /* 1415 * dge_ioctl: [ifnet interface function] 1416 * 1417 * Handle control requests from the operator. 1418 */ 1419 static int 1420 dge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1421 { 1422 struct dge_softc *sc = ifp->if_softc; 1423 struct ifreq *ifr = (struct ifreq *) data; 1424 pcireg_t preg; 1425 int s, error, mmrbc; 1426 1427 s = splnet(); 1428 1429 switch (cmd) { 1430 case SIOCSIFMEDIA: 1431 case SIOCGIFMEDIA: 1432 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1433 break; 1434 1435 case SIOCSIFMTU: 1436 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) { 1437 error = EINVAL; 1438 } else { 1439 error = 0; 1440 ifp->if_mtu = ifr->ifr_mtu; 1441 if (ifp->if_flags & IFF_UP) 1442 error = (*ifp->if_init)(ifp); 1443 } 1444 break; 1445 1446 case SIOCSIFFLAGS: 1447 /* extract link flags */ 1448 if ((ifp->if_flags & IFF_LINK0) == 0 && 1449 (ifp->if_flags & IFF_LINK1) == 0) 1450 mmrbc = PCIX_MMRBC_512; 1451 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1452 (ifp->if_flags & IFF_LINK1) != 0) 1453 mmrbc = PCIX_MMRBC_1024; 1454 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1455 (ifp->if_flags & IFF_LINK1) == 0) 1456 mmrbc = PCIX_MMRBC_2048; 1457 else 1458 mmrbc = PCIX_MMRBC_4096; 1459 if (mmrbc != sc->sc_mmrbc) { 1460 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1461 preg &= ~PCIX_MMRBC_MSK; 1462 preg |= mmrbc; 1463 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1464 sc->sc_mmrbc = mmrbc; 1465 } 1466 /* FALLTHROUGH */ 1467 default: 1468 error = ether_ioctl(ifp, cmd, data); 1469 if (error == ENETRESET) { 1470 /* 1471 * Multicast list has changed; set the hardware filter 1472 * accordingly. 1473 */ 1474 if (ifp->if_flags & IFF_RUNNING) 1475 dge_set_filter(sc); 1476 error = 0; 1477 } 1478 break; 1479 } 1480 1481 /* Try to get more packets going. */ 1482 dge_start(ifp); 1483 1484 splx(s); 1485 return (error); 1486 } 1487 1488 /* 1489 * dge_intr: 1490 * 1491 * Interrupt service routine. 1492 */ 1493 static int 1494 dge_intr(void *arg) 1495 { 1496 struct dge_softc *sc = arg; 1497 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1498 uint32_t icr; 1499 int wantinit, handled = 0; 1500 1501 for (wantinit = 0; wantinit == 0;) { 1502 icr = CSR_READ(sc, DGE_ICR); 1503 if ((icr & sc->sc_icr) == 0) 1504 break; 1505 1506 #if 0 /*NRND > 0*/ 1507 if (RND_ENABLED(&sc->rnd_source)) 1508 rnd_add_uint32(&sc->rnd_source, icr); 1509 #endif 1510 1511 handled = 1; 1512 1513 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1514 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1515 DPRINTF(DGE_DEBUG_RX, 1516 ("%s: RX: got Rx intr 0x%08x\n", 1517 sc->sc_dev.dv_xname, 1518 icr & (ICR_RXDMT0|ICR_RXT0))); 1519 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1520 } 1521 #endif 1522 dge_rxintr(sc); 1523 1524 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1525 if (icr & ICR_TXDW) { 1526 DPRINTF(DGE_DEBUG_TX, 1527 ("%s: TX: got TXDW interrupt\n", 1528 sc->sc_dev.dv_xname)); 1529 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1530 } 1531 if (icr & ICR_TXQE) 1532 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1533 #endif 1534 dge_txintr(sc); 1535 1536 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1537 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1538 dge_linkintr(sc, icr); 1539 } 1540 1541 if (icr & ICR_RXO) { 1542 printf("%s: Receive overrun\n", sc->sc_dev.dv_xname); 1543 wantinit = 1; 1544 } 1545 } 1546 1547 if (handled) { 1548 if (wantinit) 1549 dge_init(ifp); 1550 1551 /* Try to get more packets going. */ 1552 dge_start(ifp); 1553 } 1554 1555 return (handled); 1556 } 1557 1558 /* 1559 * dge_txintr: 1560 * 1561 * Helper; handle transmit interrupts. 1562 */ 1563 static void 1564 dge_txintr(struct dge_softc *sc) 1565 { 1566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1567 struct dge_txsoft *txs; 1568 uint8_t status; 1569 int i; 1570 1571 ifp->if_flags &= ~IFF_OACTIVE; 1572 1573 /* 1574 * Go through the Tx list and free mbufs for those 1575 * frames which have been transmitted. 1576 */ 1577 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1578 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1579 txs = &sc->sc_txsoft[i]; 1580 1581 DPRINTF(DGE_DEBUG_TX, 1582 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 1583 1584 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1585 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1586 1587 status = 1588 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1589 if ((status & TDESC_STA_DD) == 0) { 1590 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1591 BUS_DMASYNC_PREREAD); 1592 break; 1593 } 1594 1595 DPRINTF(DGE_DEBUG_TX, 1596 ("%s: TX: job %d done: descs %d..%d\n", 1597 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 1598 txs->txs_lastdesc)); 1599 1600 ifp->if_opackets++; 1601 sc->sc_txfree += txs->txs_ndesc; 1602 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1603 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1604 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1605 m_freem(txs->txs_mbuf); 1606 txs->txs_mbuf = NULL; 1607 } 1608 1609 /* Update the dirty transmit buffer pointer. */ 1610 sc->sc_txsdirty = i; 1611 DPRINTF(DGE_DEBUG_TX, 1612 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 1613 1614 /* 1615 * If there are no more pending transmissions, cancel the watchdog 1616 * timer. 1617 */ 1618 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1619 ifp->if_timer = 0; 1620 } 1621 1622 /* 1623 * dge_rxintr: 1624 * 1625 * Helper; handle receive interrupts. 1626 */ 1627 static void 1628 dge_rxintr(struct dge_softc *sc) 1629 { 1630 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1631 struct dge_rxsoft *rxs; 1632 struct mbuf *m; 1633 int i, len; 1634 uint8_t status, errors; 1635 1636 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1637 rxs = &sc->sc_rxsoft[i]; 1638 1639 DPRINTF(DGE_DEBUG_RX, 1640 ("%s: RX: checking descriptor %d\n", 1641 sc->sc_dev.dv_xname, i)); 1642 1643 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1644 1645 status = sc->sc_rxdescs[i].dr_status; 1646 errors = sc->sc_rxdescs[i].dr_errors; 1647 len = le16toh(sc->sc_rxdescs[i].dr_len); 1648 1649 if ((status & RDESC_STS_DD) == 0) { 1650 /* 1651 * We have processed all of the receive descriptors. 1652 */ 1653 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1654 break; 1655 } 1656 1657 if (__predict_false(sc->sc_rxdiscard)) { 1658 DPRINTF(DGE_DEBUG_RX, 1659 ("%s: RX: discarding contents of descriptor %d\n", 1660 sc->sc_dev.dv_xname, i)); 1661 DGE_INIT_RXDESC(sc, i); 1662 if (status & RDESC_STS_EOP) { 1663 /* Reset our state. */ 1664 DPRINTF(DGE_DEBUG_RX, 1665 ("%s: RX: resetting rxdiscard -> 0\n", 1666 sc->sc_dev.dv_xname)); 1667 sc->sc_rxdiscard = 0; 1668 } 1669 continue; 1670 } 1671 1672 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1673 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1674 1675 m = rxs->rxs_mbuf; 1676 1677 /* 1678 * Add a new receive buffer to the ring. 1679 */ 1680 if (dge_add_rxbuf(sc, i) != 0) { 1681 /* 1682 * Failed, throw away what we've done so 1683 * far, and discard the rest of the packet. 1684 */ 1685 ifp->if_ierrors++; 1686 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1687 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1688 DGE_INIT_RXDESC(sc, i); 1689 if ((status & RDESC_STS_EOP) == 0) 1690 sc->sc_rxdiscard = 1; 1691 if (sc->sc_rxhead != NULL) 1692 m_freem(sc->sc_rxhead); 1693 DGE_RXCHAIN_RESET(sc); 1694 DPRINTF(DGE_DEBUG_RX, 1695 ("%s: RX: Rx buffer allocation failed, " 1696 "dropping packet%s\n", sc->sc_dev.dv_xname, 1697 sc->sc_rxdiscard ? " (discard)" : "")); 1698 continue; 1699 } 1700 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1701 1702 DGE_RXCHAIN_LINK(sc, m); 1703 1704 m->m_len = len; 1705 1706 DPRINTF(DGE_DEBUG_RX, 1707 ("%s: RX: buffer at %p len %d\n", 1708 sc->sc_dev.dv_xname, m->m_data, len)); 1709 1710 /* 1711 * If this is not the end of the packet, keep 1712 * looking. 1713 */ 1714 if ((status & RDESC_STS_EOP) == 0) { 1715 sc->sc_rxlen += len; 1716 DPRINTF(DGE_DEBUG_RX, 1717 ("%s: RX: not yet EOP, rxlen -> %d\n", 1718 sc->sc_dev.dv_xname, sc->sc_rxlen)); 1719 continue; 1720 } 1721 1722 /* 1723 * Okay, we have the entire packet now... 1724 */ 1725 *sc->sc_rxtailp = NULL; 1726 m = sc->sc_rxhead; 1727 len += sc->sc_rxlen; 1728 1729 DGE_RXCHAIN_RESET(sc); 1730 1731 DPRINTF(DGE_DEBUG_RX, 1732 ("%s: RX: have entire packet, len -> %d\n", 1733 sc->sc_dev.dv_xname, len)); 1734 1735 /* 1736 * If an error occurred, update stats and drop the packet. 1737 */ 1738 if (errors & 1739 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1740 ifp->if_ierrors++; 1741 if (errors & RDESC_ERR_SE) 1742 printf("%s: symbol error\n", 1743 sc->sc_dev.dv_xname); 1744 else if (errors & RDESC_ERR_P) 1745 printf("%s: parity error\n", 1746 sc->sc_dev.dv_xname); 1747 else if (errors & RDESC_ERR_CE) 1748 printf("%s: CRC error\n", 1749 sc->sc_dev.dv_xname); 1750 m_freem(m); 1751 continue; 1752 } 1753 1754 /* 1755 * No errors. Receive the packet. 1756 */ 1757 m->m_pkthdr.rcvif = ifp; 1758 m->m_pkthdr.len = len; 1759 1760 /* 1761 * Set up checksum info for this packet. 1762 */ 1763 if (status & RDESC_STS_IPCS) { 1764 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1765 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1766 if (errors & RDESC_ERR_IPE) 1767 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1768 } 1769 if (status & RDESC_STS_TCPCS) { 1770 /* 1771 * Note: we don't know if this was TCP or UDP, 1772 * so we just set both bits, and expect the 1773 * upper layers to deal. 1774 */ 1775 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1776 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1777 if (errors & RDESC_ERR_TCPE) 1778 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1779 } 1780 1781 ifp->if_ipackets++; 1782 1783 #if NBPFILTER > 0 1784 /* Pass this up to any BPF listeners. */ 1785 if (ifp->if_bpf) 1786 bpf_mtap(ifp->if_bpf, m); 1787 #endif /* NBPFILTER > 0 */ 1788 1789 /* Pass it on. */ 1790 (*ifp->if_input)(ifp, m); 1791 } 1792 1793 /* Update the receive pointer. */ 1794 sc->sc_rxptr = i; 1795 1796 DPRINTF(DGE_DEBUG_RX, 1797 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 1798 } 1799 1800 /* 1801 * dge_linkintr: 1802 * 1803 * Helper; handle link interrupts. 1804 */ 1805 static void 1806 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1807 { 1808 uint32_t status; 1809 1810 if (icr & ICR_LSC) { 1811 status = CSR_READ(sc, DGE_STATUS); 1812 if (status & STATUS_LINKUP) { 1813 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1814 sc->sc_dev.dv_xname)); 1815 } else { 1816 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1817 sc->sc_dev.dv_xname)); 1818 } 1819 } else if (icr & ICR_RXSEQ) { 1820 DPRINTF(DGE_DEBUG_LINK, 1821 ("%s: LINK: Receive sequence error\n", 1822 sc->sc_dev.dv_xname)); 1823 } 1824 /* XXX - fix errata */ 1825 } 1826 1827 /* 1828 * dge_reset: 1829 * 1830 * Reset the i82597 chip. 1831 */ 1832 static void 1833 dge_reset(struct dge_softc *sc) 1834 { 1835 int i; 1836 1837 /* 1838 * Do a chip reset. 1839 */ 1840 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1841 1842 delay(10000); 1843 1844 for (i = 0; i < 1000; i++) { 1845 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1846 break; 1847 delay(20); 1848 } 1849 1850 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1851 printf("%s: WARNING: reset failed to complete\n", 1852 sc->sc_dev.dv_xname); 1853 /* 1854 * Reset the EEPROM logic. 1855 * This will cause the chip to reread its default values, 1856 * which doesn't happen otherwise (errata). 1857 */ 1858 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1859 delay(10000); 1860 } 1861 1862 /* 1863 * dge_init: [ifnet interface function] 1864 * 1865 * Initialize the interface. Must be called at splnet(). 1866 */ 1867 static int 1868 dge_init(struct ifnet *ifp) 1869 { 1870 struct dge_softc *sc = ifp->if_softc; 1871 struct dge_rxsoft *rxs; 1872 int i, error = 0; 1873 uint32_t reg; 1874 1875 /* 1876 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1877 * There is a small but measurable benefit to avoiding the adjusment 1878 * of the descriptor so that the headers are aligned, for normal mtu, 1879 * on such platforms. One possibility is that the DMA itself is 1880 * slightly more efficient if the front of the entire packet (instead 1881 * of the front of the headers) is aligned. 1882 * 1883 * Note we must always set align_tweak to 0 if we are using 1884 * jumbo frames. 1885 */ 1886 #ifdef __NO_STRICT_ALIGNMENT 1887 sc->sc_align_tweak = 0; 1888 #else 1889 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1890 sc->sc_align_tweak = 0; 1891 else 1892 sc->sc_align_tweak = 2; 1893 #endif /* __NO_STRICT_ALIGNMENT */ 1894 1895 /* Cancel any pending I/O. */ 1896 dge_stop(ifp, 0); 1897 1898 /* Reset the chip to a known state. */ 1899 dge_reset(sc); 1900 1901 /* Initialize the transmit descriptor ring. */ 1902 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1903 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1904 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1905 sc->sc_txfree = DGE_NTXDESC; 1906 sc->sc_txnext = 0; 1907 1908 sc->sc_txctx_ipcs = 0xffffffff; 1909 sc->sc_txctx_tucs = 0xffffffff; 1910 1911 CSR_WRITE(sc, DGE_TDBAH, 0); 1912 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1913 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1914 CSR_WRITE(sc, DGE_TDH, 0); 1915 CSR_WRITE(sc, DGE_TDT, 0); 1916 CSR_WRITE(sc, DGE_TIDV, TIDV); 1917 1918 #if 0 1919 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1920 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1921 #endif 1922 CSR_WRITE(sc, DGE_RXDCTL, 1923 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1924 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1925 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1926 1927 /* Initialize the transmit job descriptors. */ 1928 for (i = 0; i < DGE_TXQUEUELEN; i++) 1929 sc->sc_txsoft[i].txs_mbuf = NULL; 1930 sc->sc_txsfree = DGE_TXQUEUELEN; 1931 sc->sc_txsnext = 0; 1932 sc->sc_txsdirty = 0; 1933 1934 /* 1935 * Initialize the receive descriptor and receive job 1936 * descriptor rings. 1937 */ 1938 CSR_WRITE(sc, DGE_RDBAH, 0); 1939 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1940 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1941 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1942 CSR_WRITE(sc, DGE_RDT, 0); 1943 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1944 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1945 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1946 1947 for (i = 0; i < DGE_NRXDESC; i++) { 1948 rxs = &sc->sc_rxsoft[i]; 1949 if (rxs->rxs_mbuf == NULL) { 1950 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1951 printf("%s: unable to allocate or map rx " 1952 "buffer %d, error = %d\n", 1953 sc->sc_dev.dv_xname, i, error); 1954 /* 1955 * XXX Should attempt to run with fewer receive 1956 * XXX buffers instead of just failing. 1957 */ 1958 dge_rxdrain(sc); 1959 goto out; 1960 } 1961 } 1962 DGE_INIT_RXDESC(sc, i); 1963 } 1964 sc->sc_rxptr = DGE_RXSPACE; 1965 sc->sc_rxdiscard = 0; 1966 DGE_RXCHAIN_RESET(sc); 1967 1968 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1969 sc->sc_ctrl0 |= CTRL0_JFE; 1970 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1971 } 1972 1973 /* Write the control registers. */ 1974 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1975 1976 /* 1977 * Set up checksum offload parameters. 1978 */ 1979 reg = CSR_READ(sc, DGE_RXCSUM); 1980 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1981 reg |= RXCSUM_IPOFL; 1982 else 1983 reg &= ~RXCSUM_IPOFL; 1984 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 1985 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1986 else { 1987 reg &= ~RXCSUM_TUOFL; 1988 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 1989 reg &= ~RXCSUM_IPOFL; 1990 } 1991 CSR_WRITE(sc, DGE_RXCSUM, reg); 1992 1993 /* 1994 * Set up the interrupt registers. 1995 */ 1996 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 1997 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 1998 ICR_RXO | ICR_RXT0; 1999 2000 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 2001 2002 /* 2003 * Set up the transmit control register. 2004 */ 2005 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 2006 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 2007 2008 /* 2009 * Set up the receive control register; we actually program 2010 * the register when we set the receive filter. Use multicast 2011 * address offset type 0. 2012 */ 2013 sc->sc_mchash_type = 0; 2014 2015 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2016 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2017 2018 #ifdef DGE_OFFBYONE_RXBUG 2019 sc->sc_rctl |= RCTL_BSIZE_16k; 2020 #else 2021 switch(MCLBYTES) { 2022 case 2048: 2023 sc->sc_rctl |= RCTL_BSIZE_2k; 2024 break; 2025 case 4096: 2026 sc->sc_rctl |= RCTL_BSIZE_4k; 2027 break; 2028 case 8192: 2029 sc->sc_rctl |= RCTL_BSIZE_8k; 2030 break; 2031 case 16384: 2032 sc->sc_rctl |= RCTL_BSIZE_16k; 2033 break; 2034 default: 2035 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2036 } 2037 #endif 2038 2039 /* Set the receive filter. */ 2040 /* Also sets RCTL */ 2041 dge_set_filter(sc); 2042 2043 /* ...all done! */ 2044 ifp->if_flags |= IFF_RUNNING; 2045 ifp->if_flags &= ~IFF_OACTIVE; 2046 2047 out: 2048 if (error) 2049 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2050 return (error); 2051 } 2052 2053 /* 2054 * dge_rxdrain: 2055 * 2056 * Drain the receive queue. 2057 */ 2058 static void 2059 dge_rxdrain(struct dge_softc *sc) 2060 { 2061 struct dge_rxsoft *rxs; 2062 int i; 2063 2064 for (i = 0; i < DGE_NRXDESC; i++) { 2065 rxs = &sc->sc_rxsoft[i]; 2066 if (rxs->rxs_mbuf != NULL) { 2067 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2068 m_freem(rxs->rxs_mbuf); 2069 rxs->rxs_mbuf = NULL; 2070 } 2071 } 2072 } 2073 2074 /* 2075 * dge_stop: [ifnet interface function] 2076 * 2077 * Stop transmission on the interface. 2078 */ 2079 static void 2080 dge_stop(struct ifnet *ifp, int disable) 2081 { 2082 struct dge_softc *sc = ifp->if_softc; 2083 struct dge_txsoft *txs; 2084 int i; 2085 2086 /* Stop the transmit and receive processes. */ 2087 CSR_WRITE(sc, DGE_TCTL, 0); 2088 CSR_WRITE(sc, DGE_RCTL, 0); 2089 2090 /* Release any queued transmit buffers. */ 2091 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2092 txs = &sc->sc_txsoft[i]; 2093 if (txs->txs_mbuf != NULL) { 2094 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2095 m_freem(txs->txs_mbuf); 2096 txs->txs_mbuf = NULL; 2097 } 2098 } 2099 2100 if (disable) 2101 dge_rxdrain(sc); 2102 2103 /* Mark the interface as down and cancel the watchdog timer. */ 2104 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2105 ifp->if_timer = 0; 2106 } 2107 2108 /* 2109 * dge_add_rxbuf: 2110 * 2111 * Add a receive buffer to the indiciated descriptor. 2112 */ 2113 static int 2114 dge_add_rxbuf(struct dge_softc *sc, int idx) 2115 { 2116 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2117 struct mbuf *m; 2118 int error; 2119 #ifdef DGE_OFFBYONE_RXBUG 2120 caddr_t buf; 2121 #endif 2122 2123 MGETHDR(m, M_DONTWAIT, MT_DATA); 2124 if (m == NULL) 2125 return (ENOBUFS); 2126 2127 #ifdef DGE_OFFBYONE_RXBUG 2128 if ((buf = dge_getbuf(sc)) == NULL) 2129 return ENOBUFS; 2130 2131 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2132 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2133 m->m_flags |= M_EXT_RW; 2134 2135 if (rxs->rxs_mbuf != NULL) 2136 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2137 rxs->rxs_mbuf = m; 2138 2139 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2140 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2141 #else 2142 MCLGET(m, M_DONTWAIT); 2143 if ((m->m_flags & M_EXT) == 0) { 2144 m_freem(m); 2145 return (ENOBUFS); 2146 } 2147 2148 if (rxs->rxs_mbuf != NULL) 2149 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2150 2151 rxs->rxs_mbuf = m; 2152 2153 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2154 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2155 BUS_DMA_READ|BUS_DMA_NOWAIT); 2156 #endif 2157 if (error) { 2158 printf("%s: unable to load rx DMA map %d, error = %d\n", 2159 sc->sc_dev.dv_xname, idx, error); 2160 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2161 } 2162 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2163 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2164 2165 return (0); 2166 } 2167 2168 /* 2169 * dge_set_ral: 2170 * 2171 * Set an entry in the receive address list. 2172 */ 2173 static void 2174 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2175 { 2176 uint32_t ral_lo, ral_hi; 2177 2178 if (enaddr != NULL) { 2179 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2180 (enaddr[3] << 24); 2181 ral_hi = enaddr[4] | (enaddr[5] << 8); 2182 ral_hi |= RAH_AV; 2183 } else { 2184 ral_lo = 0; 2185 ral_hi = 0; 2186 } 2187 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2188 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2189 } 2190 2191 /* 2192 * dge_mchash: 2193 * 2194 * Compute the hash of the multicast address for the 4096-bit 2195 * multicast filter. 2196 */ 2197 static uint32_t 2198 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2199 { 2200 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2201 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2202 uint32_t hash; 2203 2204 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2205 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2206 2207 return (hash & 0xfff); 2208 } 2209 2210 /* 2211 * dge_set_filter: 2212 * 2213 * Set up the receive filter. 2214 */ 2215 static void 2216 dge_set_filter(struct dge_softc *sc) 2217 { 2218 struct ethercom *ec = &sc->sc_ethercom; 2219 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2220 struct ether_multi *enm; 2221 struct ether_multistep step; 2222 uint32_t hash, reg, bit; 2223 int i; 2224 2225 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2226 2227 if (ifp->if_flags & IFF_BROADCAST) 2228 sc->sc_rctl |= RCTL_BAM; 2229 if (ifp->if_flags & IFF_PROMISC) { 2230 sc->sc_rctl |= RCTL_UPE; 2231 goto allmulti; 2232 } 2233 2234 /* 2235 * Set the station address in the first RAL slot, and 2236 * clear the remaining slots. 2237 */ 2238 dge_set_ral(sc, LLADDR(ifp->if_sadl), 0); 2239 for (i = 1; i < RA_TABSIZE; i++) 2240 dge_set_ral(sc, NULL, i); 2241 2242 /* Clear out the multicast table. */ 2243 for (i = 0; i < MC_TABSIZE; i++) 2244 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2245 2246 ETHER_FIRST_MULTI(step, ec, enm); 2247 while (enm != NULL) { 2248 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2249 /* 2250 * We must listen to a range of multicast addresses. 2251 * For now, just accept all multicasts, rather than 2252 * trying to set only those filter bits needed to match 2253 * the range. (At this time, the only use of address 2254 * ranges is for IP multicast routing, for which the 2255 * range is big enough to require all bits set.) 2256 */ 2257 goto allmulti; 2258 } 2259 2260 hash = dge_mchash(sc, enm->enm_addrlo); 2261 2262 reg = (hash >> 5) & 0x7f; 2263 bit = hash & 0x1f; 2264 2265 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2266 hash |= 1U << bit; 2267 2268 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2269 2270 ETHER_NEXT_MULTI(step, enm); 2271 } 2272 2273 ifp->if_flags &= ~IFF_ALLMULTI; 2274 goto setit; 2275 2276 allmulti: 2277 ifp->if_flags |= IFF_ALLMULTI; 2278 sc->sc_rctl |= RCTL_MPE; 2279 2280 setit: 2281 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2282 } 2283 2284 /* 2285 * Read in the EEPROM info and verify checksum. 2286 */ 2287 int 2288 dge_read_eeprom(struct dge_softc *sc) 2289 { 2290 uint16_t cksum; 2291 int i; 2292 2293 cksum = 0; 2294 for (i = 0; i < EEPROM_SIZE; i++) { 2295 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2296 cksum += sc->sc_eeprom[i]; 2297 } 2298 return cksum != EEPROM_CKSUM; 2299 } 2300 2301 2302 /* 2303 * Read a 16-bit word from address addr in the serial EEPROM. 2304 */ 2305 uint16_t 2306 dge_eeprom_word(struct dge_softc *sc, int addr) 2307 { 2308 uint32_t reg; 2309 uint16_t rval = 0; 2310 int i; 2311 2312 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2313 2314 /* Lower clock pulse (and data in to chip) */ 2315 CSR_WRITE(sc, DGE_EECD, reg); 2316 /* Select chip */ 2317 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2318 2319 /* Send read command */ 2320 dge_eeprom_clockout(sc, 1); 2321 dge_eeprom_clockout(sc, 1); 2322 dge_eeprom_clockout(sc, 0); 2323 2324 /* Send address */ 2325 for (i = 5; i >= 0; i--) 2326 dge_eeprom_clockout(sc, (addr >> i) & 1); 2327 2328 /* Read data */ 2329 for (i = 0; i < 16; i++) { 2330 rval <<= 1; 2331 rval |= dge_eeprom_clockin(sc); 2332 } 2333 2334 /* Deselect chip */ 2335 CSR_WRITE(sc, DGE_EECD, reg); 2336 2337 return rval; 2338 } 2339 2340 /* 2341 * Clock out a single bit to the EEPROM. 2342 */ 2343 void 2344 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2345 { 2346 int reg; 2347 2348 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2349 if (bit) 2350 reg |= EECD_DI; 2351 2352 CSR_WRITE(sc, DGE_EECD, reg); 2353 delay(2); 2354 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2355 delay(2); 2356 CSR_WRITE(sc, DGE_EECD, reg); 2357 delay(2); 2358 } 2359 2360 /* 2361 * Clock in a single bit from EEPROM. 2362 */ 2363 int 2364 dge_eeprom_clockin(struct dge_softc *sc) 2365 { 2366 int reg, rv; 2367 2368 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2369 2370 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2371 delay(2); 2372 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2373 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2374 delay(2); 2375 2376 return rv; 2377 } 2378 2379 static void 2380 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2381 { 2382 struct dge_softc *sc = ifp->if_softc; 2383 2384 ifmr->ifm_status = IFM_AVALID; 2385 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2386 2387 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2388 ifmr->ifm_status |= IFM_ACTIVE; 2389 } 2390 2391 static inline int 2392 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2393 { 2394 int i, mdic; 2395 2396 CSR_WRITE(sc, DGE_MDIO, 2397 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2398 for (i = 0; i < 10; i++) { 2399 delay(10); 2400 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2401 break; 2402 } 2403 return mdic; 2404 } 2405 2406 2407 static void 2408 dge_xgmii_writereg(struct device *self, int phy, int reg, int val) 2409 { 2410 struct dge_softc *sc = (void *) self; 2411 int mdic; 2412 2413 CSR_WRITE(sc, DGE_MDIRW, val); 2414 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2415 printf("%s: address cycle timeout; phy %d reg %d\n", 2416 sc->sc_dev.dv_xname, phy, reg); 2417 return; 2418 } 2419 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2420 printf("%s: read cycle timeout; phy %d reg %d\n", 2421 sc->sc_dev.dv_xname, phy, reg); 2422 return; 2423 } 2424 } 2425 2426 static void 2427 dge_xgmii_reset(struct dge_softc *sc) 2428 { 2429 dge_xgmii_writereg((void *)sc, 0, 0, BMCR_RESET); 2430 } 2431 2432 static int 2433 dge_xgmii_mediachange(struct ifnet *ifp) 2434 { 2435 return 0; 2436 } 2437
Indexes created Thu Sep 25 16:09:42 GMT 2025