if_ena.c revision 1.15.2.3
1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifdef _KERNEL_OPT 32 #include "opt_net_mpsafe.h" 33 #endif 34 35 #include <sys/cdefs.h> 36 #if 0 37 __FBSDID("$FreeBSD: head/sys/dev/ena/ena.c 333456 2018-05-10 09:37:54Z mw $"); 38 #endif 39 __KERNEL_RCSID(0, "$NetBSD: if_ena.c,v 1.15.2.3 2020/08/05 14:59:41 martin Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/time.h> 54 #include <sys/workqueue.h> 55 #include <sys/callout.h> 56 #include <sys/interrupt.h> 57 #include <sys/cpu.h> 58 59 #include <net/if_ether.h> 60 #include <net/if_vlanvar.h> 61 62 #include <dev/pci/if_enavar.h> 63 64 #ifdef NET_MPSAFE 65 #define WQ_FLAGS WQ_MPSAFE 66 #define CALLOUT_FLAGS CALLOUT_MPSAFE 67 #else 68 #define WQ_FLAGS 0 69 #define CALLOUT_FLAGS 0 70 #endif 71 72 /********************************************************* 73 * Function prototypes 74 *********************************************************/ 75 static int ena_probe(device_t, cfdata_t, void *); 76 static int ena_intr_msix_mgmnt(void *); 77 static int ena_allocate_pci_resources(struct pci_attach_args *, 78 struct ena_adapter *); 79 static void ena_free_pci_resources(struct ena_adapter *); 80 static int ena_change_mtu(struct ifnet *, int); 81 static void ena_init_io_rings_common(struct ena_adapter *, 82 struct ena_ring *, uint16_t); 83 static void ena_init_io_rings(struct ena_adapter *); 84 static void ena_free_io_ring_resources(struct ena_adapter *, unsigned int); 85 static void ena_free_all_io_rings_resources(struct ena_adapter *); 86 #if 0 87 static int ena_setup_tx_dma_tag(struct ena_adapter *); 88 static int ena_free_tx_dma_tag(struct ena_adapter *); 89 static int ena_setup_rx_dma_tag(struct ena_adapter *); 90 static int ena_free_rx_dma_tag(struct ena_adapter *); 91 #endif 92 static int ena_setup_tx_resources(struct ena_adapter *, int); 93 static void ena_free_tx_resources(struct ena_adapter *, int); 94 static int ena_setup_all_tx_resources(struct ena_adapter *); 95 static void ena_free_all_tx_resources(struct ena_adapter *); 96 static inline int validate_rx_req_id(struct ena_ring *, uint16_t); 97 static int ena_setup_rx_resources(struct ena_adapter *, unsigned int); 98 static void ena_free_rx_resources(struct ena_adapter *, unsigned int); 99 static int ena_setup_all_rx_resources(struct ena_adapter *); 100 static void ena_free_all_rx_resources(struct ena_adapter *); 101 static inline int ena_alloc_rx_mbuf(struct ena_adapter *, struct ena_ring *, 102 struct ena_rx_buffer *); 103 static void ena_free_rx_mbuf(struct ena_adapter *, struct ena_ring *, 104 struct ena_rx_buffer *); 105 static int ena_refill_rx_bufs(struct ena_ring *, uint32_t); 106 static void ena_free_rx_bufs(struct ena_adapter *, unsigned int); 107 static void ena_refill_all_rx_bufs(struct ena_adapter *); 108 static void ena_free_all_rx_bufs(struct ena_adapter *); 109 static void ena_free_tx_bufs(struct ena_adapter *, unsigned int); 110 static void ena_free_all_tx_bufs(struct ena_adapter *); 111 static void ena_destroy_all_tx_queues(struct ena_adapter *); 112 static void ena_destroy_all_rx_queues(struct ena_adapter *); 113 static void ena_destroy_all_io_queues(struct ena_adapter *); 114 static int ena_create_io_queues(struct ena_adapter *); 115 static int ena_tx_cleanup(struct ena_ring *); 116 static void ena_deferred_rx_cleanup(struct work *, void *); 117 static int ena_rx_cleanup(struct ena_ring *); 118 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 119 #if 0 120 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 121 struct mbuf *); 122 #endif 123 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 124 struct ena_com_rx_ctx *, uint16_t *); 125 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 126 struct mbuf *); 127 static int ena_handle_msix(void *); 128 static int ena_enable_msix(struct ena_adapter *); 129 static int ena_request_mgmnt_irq(struct ena_adapter *); 130 static int ena_request_io_irq(struct ena_adapter *); 131 static void ena_free_mgmnt_irq(struct ena_adapter *); 132 static void ena_free_io_irq(struct ena_adapter *); 133 static void ena_free_irqs(struct ena_adapter*); 134 static void ena_disable_msix(struct ena_adapter *); 135 static void ena_unmask_all_io_irqs(struct ena_adapter *); 136 static int ena_rss_configure(struct ena_adapter *); 137 static int ena_up_complete(struct ena_adapter *); 138 static int ena_up(struct ena_adapter *); 139 static void ena_down(struct ena_adapter *); 140 #if 0 141 static uint64_t ena_get_counter(struct ifnet *, ift_counter); 142 #endif 143 static int ena_media_change(struct ifnet *); 144 static void ena_media_status(struct ifnet *, struct ifmediareq *); 145 static int ena_init(struct ifnet *); 146 static int ena_ioctl(struct ifnet *, u_long, void *); 147 static int ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *); 148 static void ena_update_host_info(struct ena_admin_host_info *, struct ifnet *); 149 static void ena_update_hwassist(struct ena_adapter *); 150 static int ena_setup_ifnet(device_t, struct ena_adapter *, 151 struct ena_com_dev_get_features_ctx *); 152 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *); 153 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 154 struct mbuf **mbuf); 155 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 156 static void ena_start_xmit(struct ena_ring *); 157 static int ena_mq_start(struct ifnet *, struct mbuf *); 158 static void ena_deferred_mq_start(struct work *, void *); 159 #if 0 160 static void ena_qflush(struct ifnet *); 161 #endif 162 static int ena_calc_io_queue_num(struct pci_attach_args *, 163 struct ena_adapter *, struct ena_com_dev_get_features_ctx *); 164 static int ena_calc_queue_size(struct ena_adapter *, uint16_t *, 165 uint16_t *, struct ena_com_dev_get_features_ctx *); 166 #if 0 167 static int ena_rss_init_default(struct ena_adapter *); 168 static void ena_rss_init_default_deferred(void *); 169 #endif 170 static void ena_config_host_info(struct ena_com_dev *); 171 static void ena_attach(device_t, device_t, void *); 172 static int ena_detach(device_t, int); 173 static int ena_device_init(struct ena_adapter *, device_t, 174 struct ena_com_dev_get_features_ctx *, int *); 175 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *, 176 int); 177 static void ena_update_on_link_change(void *, struct ena_admin_aenq_entry *); 178 static void unimplemented_aenq_handler(void *, 179 struct ena_admin_aenq_entry *); 180 static void ena_timer_service(void *); 181 182 static const char ena_version[] = 183 DEVICE_NAME DRV_MODULE_NAME " v" DRV_MODULE_VERSION; 184 185 #if 0 186 static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD, 0, "ENA driver parameters"); 187 #endif 188 189 /* 190 * Tuneable number of buffers in the buf-ring (drbr) 191 */ 192 static int ena_buf_ring_size = 4096; 193 #if 0 194 SYSCTL_INT(_hw_ena, OID_AUTO, buf_ring_size, CTLFLAG_RWTUN, 195 &ena_buf_ring_size, 0, "Size of the bufring"); 196 #endif 197 198 /* 199 * Logging level for changing verbosity of the output 200 */ 201 int ena_log_level = ENA_ALERT | ENA_WARNING; 202 #if 0 203 SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, 204 &ena_log_level, 0, "Logging level indicating verbosity of the logs"); 205 #endif 206 207 static const ena_vendor_info_t ena_vendor_info_array[] = { 208 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_PF, 0}, 209 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_PF, 0}, 210 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_VF, 0}, 211 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_VF, 0}, 212 /* Last entry */ 213 { 0, 0, 0 } 214 }; 215 216 /* 217 * Contains pointers to event handlers, e.g. link state chage. 218 */ 219 static struct ena_aenq_handlers aenq_handlers; 220 221 int 222 ena_dma_alloc(device_t dmadev, bus_size_t size, 223 ena_mem_handle_t *dma , int mapflags) 224 { 225 struct ena_adapter *adapter = device_private(dmadev); 226 uint32_t maxsize; 227 bus_dma_segment_t seg; 228 int error, nsegs; 229 230 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; 231 232 #if 0 233 /* XXX what is this needed for ? */ 234 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); 235 if (unlikely(dma_space_addr == 0)) 236 dma_space_addr = BUS_SPACE_MAXADDR; 237 #endif 238 239 dma->tag = adapter->sc_dmat; 240 241 if ((error = bus_dmamap_create(dma->tag, maxsize, 1, maxsize, 0, 242 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->map)) != 0) { 243 ena_trace(ENA_ALERT, "bus_dmamap_create(%ju) failed: %d\n", 244 (uintmax_t)maxsize, error); 245 goto fail_create; 246 } 247 248 error = bus_dmamem_alloc(dma->tag, maxsize, 8, 0, &seg, 1, &nsegs, 249 BUS_DMA_ALLOCNOW); 250 if (error) { 251 ena_trace(ENA_ALERT, "bus_dmamem_alloc(%ju) failed: %d\n", 252 (uintmax_t)maxsize, error); 253 goto fail_alloc; 254 } 255 256 error = bus_dmamem_map(dma->tag, &seg, nsegs, maxsize, 257 &dma->vaddr, BUS_DMA_COHERENT); 258 if (error) { 259 ena_trace(ENA_ALERT, "bus_dmamem_map(%ju) failed: %d\n", 260 (uintmax_t)maxsize, error); 261 goto fail_map; 262 } 263 memset(dma->vaddr, 0, maxsize); 264 265 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 266 maxsize, NULL, mapflags); 267 if (error) { 268 ena_trace(ENA_ALERT, ": bus_dmamap_load failed: %d\n", error); 269 goto fail_load; 270 } 271 dma->paddr = dma->map->dm_segs[0].ds_addr; 272 273 return (0); 274 275 fail_load: 276 bus_dmamem_unmap(dma->tag, dma->vaddr, maxsize); 277 fail_map: 278 bus_dmamem_free(dma->tag, &seg, nsegs); 279 fail_alloc: 280 bus_dmamap_destroy(adapter->sc_dmat, dma->map); 281 fail_create: 282 return (error); 283 } 284 285 static int 286 ena_allocate_pci_resources(struct pci_attach_args *pa, 287 struct ena_adapter *adapter) 288 { 289 pcireg_t memtype, reg; 290 bus_addr_t memaddr; 291 bus_size_t mapsize; 292 int flags, error; 293 int msixoff; 294 295 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ENA_REG_BAR); 296 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 297 aprint_error_dev(adapter->pdev, "invalid type (type=0x%x)\n", 298 memtype); 299 return ENXIO; 300 } 301 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 302 if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) || 303 ((reg & PCI_COMMAND_MEM_ENABLE) == 0)) { 304 /* 305 * Enable address decoding for memory range in case BIOS or 306 * UEFI didn't set it. 307 */ 308 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 309 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 310 reg); 311 } 312 313 adapter->sc_btag = pa->pa_memt; 314 error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, ENA_REG_BAR, 315 memtype, &memaddr, &mapsize, &flags); 316 if (error) { 317 aprint_error_dev(adapter->pdev, "can't get map info\n"); 318 return ENXIO; 319 } 320 321 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 322 NULL)) { 323 pcireg_t msixtbl; 324 uint32_t table_offset; 325 int bir; 326 327 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 328 msixoff + PCI_MSIX_TBLOFFSET); 329 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 330 bir = msixtbl & PCI_MSIX_PBABIR_MASK; 331 if (bir == PCI_MAPREG_NUM(ENA_REG_BAR)) 332 mapsize = table_offset; 333 } 334 335 error = bus_space_map(adapter->sc_btag, memaddr, mapsize, flags, 336 &adapter->sc_bhandle); 337 if (error != 0) { 338 aprint_error_dev(adapter->pdev, 339 "can't map mem space (error=%d)\n", error); 340 return ENXIO; 341 } 342 343 return (0); 344 } 345 346 static void 347 ena_free_pci_resources(struct ena_adapter *adapter) 348 { 349 /* Nothing to do */ 350 } 351 352 static int 353 ena_probe(device_t parent, cfdata_t match, void *aux) 354 { 355 struct pci_attach_args *pa = aux; 356 const ena_vendor_info_t *ent; 357 358 for (int i = 0; i < __arraycount(ena_vendor_info_array); i++) { 359 ent = &ena_vendor_info_array[i]; 360 361 if ((PCI_VENDOR(pa->pa_id) == ent->vendor_id) && 362 (PCI_PRODUCT(pa->pa_id) == ent->device_id)) { 363 return 1; 364 } 365 } 366 367 return 0; 368 } 369 370 static int 371 ena_change_mtu(struct ifnet *ifp, int new_mtu) 372 { 373 struct ena_adapter *adapter = if_getsoftc(ifp); 374 int rc; 375 376 if ((new_mtu > adapter->max_mtu) || (new_mtu < ENA_MIN_MTU)) { 377 device_printf(adapter->pdev, "Invalid MTU setting. " 378 "new_mtu: %d max mtu: %d min mtu: %d\n", 379 new_mtu, adapter->max_mtu, ENA_MIN_MTU); 380 return (EINVAL); 381 } 382 383 rc = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 384 if (likely(rc == 0)) { 385 ena_trace(ENA_DBG, "set MTU to %d\n", new_mtu); 386 if_setmtu(ifp, new_mtu); 387 } else { 388 device_printf(adapter->pdev, "Failed to set MTU to %d\n", 389 new_mtu); 390 } 391 392 return (rc); 393 } 394 395 #define EVCNT_INIT(st, f) \ 396 do { \ 397 evcnt_attach_dynamic(&st->f, EVCNT_TYPE_MISC, NULL, \ 398 st->name, #f); \ 399 } while (0) 400 401 static inline void 402 ena_alloc_counters_rx(struct ena_stats_rx *st, int queue) 403 { 404 snprintf(st->name, sizeof(st->name), "ena rxq%d", queue); 405 406 EVCNT_INIT(st, cnt); 407 EVCNT_INIT(st, bytes); 408 EVCNT_INIT(st, refil_partial); 409 EVCNT_INIT(st, bad_csum); 410 EVCNT_INIT(st, mjum_alloc_fail); 411 EVCNT_INIT(st, mbuf_alloc_fail); 412 EVCNT_INIT(st, dma_mapping_err); 413 EVCNT_INIT(st, bad_desc_num); 414 EVCNT_INIT(st, bad_req_id); 415 EVCNT_INIT(st, empty_rx_ring); 416 417 /* Make sure all code is updated when new fields added */ 418 CTASSERT(offsetof(struct ena_stats_rx, empty_rx_ring) 419 + sizeof(st->empty_rx_ring) == sizeof(*st)); 420 } 421 422 static inline void 423 ena_alloc_counters_tx(struct ena_stats_tx *st, int queue) 424 { 425 snprintf(st->name, sizeof(st->name), "ena txq%d", queue); 426 427 EVCNT_INIT(st, cnt); 428 EVCNT_INIT(st, bytes); 429 EVCNT_INIT(st, prepare_ctx_err); 430 EVCNT_INIT(st, dma_mapping_err); 431 EVCNT_INIT(st, doorbells); 432 EVCNT_INIT(st, missing_tx_comp); 433 EVCNT_INIT(st, bad_req_id); 434 EVCNT_INIT(st, collapse); 435 EVCNT_INIT(st, collapse_err); 436 437 /* Make sure all code is updated when new fields added */ 438 CTASSERT(offsetof(struct ena_stats_tx, collapse_err) 439 + sizeof(st->collapse_err) == sizeof(*st)); 440 } 441 442 static inline void 443 ena_alloc_counters_dev(struct ena_stats_dev *st, int queue) 444 { 445 snprintf(st->name, sizeof(st->name), "ena dev ioq%d", queue); 446 447 EVCNT_INIT(st, wd_expired); 448 EVCNT_INIT(st, interface_up); 449 EVCNT_INIT(st, interface_down); 450 EVCNT_INIT(st, admin_q_pause); 451 452 /* Make sure all code is updated when new fields added */ 453 CTASSERT(offsetof(struct ena_stats_dev, admin_q_pause) 454 + sizeof(st->admin_q_pause) == sizeof(*st)); 455 } 456 457 static inline void 458 ena_alloc_counters_hwstats(struct ena_hw_stats *st, int queue) 459 { 460 snprintf(st->name, sizeof(st->name), "ena hw ioq%d", queue); 461 462 EVCNT_INIT(st, rx_packets); 463 EVCNT_INIT(st, tx_packets); 464 EVCNT_INIT(st, rx_bytes); 465 EVCNT_INIT(st, tx_bytes); 466 EVCNT_INIT(st, rx_drops); 467 468 /* Make sure all code is updated when new fields added */ 469 CTASSERT(offsetof(struct ena_hw_stats, rx_drops) 470 + sizeof(st->rx_drops) == sizeof(*st)); 471 } 472 static inline void 473 ena_free_counters(struct evcnt *begin, int size) 474 { 475 struct evcnt *end = (struct evcnt *)((char *)begin + size); 476 477 for (; begin < end; ++begin) 478 counter_u64_free(*begin); 479 } 480 481 static inline void 482 ena_reset_counters(struct evcnt *begin, int size) 483 { 484 struct evcnt *end = (struct evcnt *)((char *)begin + size); 485 486 for (; begin < end; ++begin) 487 counter_u64_zero(*begin); 488 } 489 490 static void 491 ena_init_io_rings_common(struct ena_adapter *adapter, struct ena_ring *ring, 492 uint16_t qid) 493 { 494 495 ring->qid = qid; 496 ring->adapter = adapter; 497 ring->ena_dev = adapter->ena_dev; 498 } 499 500 static void 501 ena_init_io_rings(struct ena_adapter *adapter) 502 { 503 struct ena_com_dev *ena_dev; 504 struct ena_ring *txr, *rxr; 505 struct ena_que *que; 506 int i; 507 508 ena_dev = adapter->ena_dev; 509 510 for (i = 0; i < adapter->num_queues; i++) { 511 txr = &adapter->tx_ring[i]; 512 rxr = &adapter->rx_ring[i]; 513 514 /* TX/RX common ring state */ 515 ena_init_io_rings_common(adapter, txr, i); 516 ena_init_io_rings_common(adapter, rxr, i); 517 518 /* TX specific ring state */ 519 txr->ring_size = adapter->tx_ring_size; 520 txr->tx_max_header_size = ena_dev->tx_max_header_size; 521 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 522 txr->smoothed_interval = 523 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 524 525 /* Allocate a buf ring */ 526 txr->br = buf_ring_alloc(ena_buf_ring_size, M_DEVBUF, 527 M_WAITOK, &txr->ring_mtx); 528 529 /* Alloc TX statistics. */ 530 ena_alloc_counters_tx(&txr->tx_stats, i); 531 532 /* RX specific ring state */ 533 rxr->ring_size = adapter->rx_ring_size; 534 rxr->smoothed_interval = 535 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 536 537 /* Alloc RX statistics. */ 538 ena_alloc_counters_rx(&rxr->rx_stats, i); 539 540 /* Initialize locks */ 541 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 542 device_xname(adapter->pdev), i); 543 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 544 device_xname(adapter->pdev), i); 545 546 mutex_init(&txr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 547 mutex_init(&rxr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 548 549 que = &adapter->que[i]; 550 que->adapter = adapter; 551 que->id = i; 552 que->tx_ring = txr; 553 que->rx_ring = rxr; 554 555 txr->que = que; 556 rxr->que = que; 557 558 rxr->empty_rx_queue = 0; 559 } 560 } 561 562 static void 563 ena_free_io_ring_resources(struct ena_adapter *adapter, unsigned int qid) 564 { 565 struct ena_ring *txr = &adapter->tx_ring[qid]; 566 struct ena_ring *rxr = &adapter->rx_ring[qid]; 567 568 ena_free_counters((struct evcnt *)&txr->tx_stats, 569 sizeof(txr->tx_stats)); 570 ena_free_counters((struct evcnt *)&rxr->rx_stats, 571 sizeof(rxr->rx_stats)); 572 573 ENA_RING_MTX_LOCK(txr); 574 drbr_free(txr->br, M_DEVBUF); 575 ENA_RING_MTX_UNLOCK(txr); 576 577 mutex_destroy(&txr->ring_mtx); 578 mutex_destroy(&rxr->ring_mtx); 579 } 580 581 static void 582 ena_free_all_io_rings_resources(struct ena_adapter *adapter) 583 { 584 int i; 585 586 for (i = 0; i < adapter->num_queues; i++) 587 ena_free_io_ring_resources(adapter, i); 588 589 } 590 591 #if 0 592 static int 593 ena_setup_tx_dma_tag(struct ena_adapter *adapter) 594 { 595 int ret; 596 597 /* Create DMA tag for Tx buffers */ 598 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), 599 1, 0, /* alignment, bounds */ 600 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 601 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 602 NULL, NULL, /* filter, filterarg */ 603 ENA_TSO_MAXSIZE, /* maxsize */ 604 adapter->max_tx_sgl_size - 1, /* nsegments */ 605 ENA_TSO_MAXSIZE, /* maxsegsize */ 606 0, /* flags */ 607 NULL, /* lockfunc */ 608 NULL, /* lockfuncarg */ 609 &adapter->tx_buf_tag); 610 611 return (ret); 612 } 613 #endif 614 615 #if 0 616 static int 617 ena_setup_rx_dma_tag(struct ena_adapter *adapter) 618 { 619 int ret; 620 621 /* Create DMA tag for Rx buffers*/ 622 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */ 623 1, 0, /* alignment, bounds */ 624 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 625 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 626 NULL, NULL, /* filter, filterarg */ 627 MJUM16BYTES, /* maxsize */ 628 adapter->max_rx_sgl_size, /* nsegments */ 629 MJUM16BYTES, /* maxsegsize */ 630 0, /* flags */ 631 NULL, /* lockfunc */ 632 NULL, /* lockarg */ 633 &adapter->rx_buf_tag); 634 635 return (ret); 636 } 637 #endif 638 639 /** 640 * ena_setup_tx_resources - allocate Tx resources (Descriptors) 641 * @adapter: network interface device structure 642 * @qid: queue index 643 * 644 * Returns 0 on success, otherwise on failure. 645 **/ 646 static int 647 ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 648 { 649 struct ena_que *que = &adapter->que[qid]; 650 struct ena_ring *tx_ring = que->tx_ring; 651 int size, i, err; 652 #ifdef RSS 653 cpuset_t cpu_mask; 654 #endif 655 656 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 657 658 tx_ring->tx_buffer_info = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 659 if (unlikely(tx_ring->tx_buffer_info == NULL)) 660 return (ENOMEM); 661 662 size = sizeof(uint16_t) * tx_ring->ring_size; 663 tx_ring->free_tx_ids = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 664 if (unlikely(tx_ring->free_tx_ids == NULL)) 665 goto err_buf_info_free; 666 667 /* Req id stack for TX OOO completions */ 668 for (i = 0; i < tx_ring->ring_size; i++) 669 tx_ring->free_tx_ids[i] = i; 670 671 /* Reset TX statistics. */ 672 ena_reset_counters((struct evcnt *)&tx_ring->tx_stats, 673 sizeof(tx_ring->tx_stats)); 674 675 tx_ring->next_to_use = 0; 676 tx_ring->next_to_clean = 0; 677 678 /* Make sure that drbr is empty */ 679 ENA_RING_MTX_LOCK(tx_ring); 680 drbr_flush(adapter->ifp, tx_ring->br); 681 ENA_RING_MTX_UNLOCK(tx_ring); 682 683 /* ... and create the buffer DMA maps */ 684 for (i = 0; i < tx_ring->ring_size; i++) { 685 err = bus_dmamap_create(adapter->sc_dmat, 686 ENA_TSO_MAXSIZE, adapter->max_tx_sgl_size - 1, 687 ENA_TSO_MAXSIZE, 0, 0, 688 &tx_ring->tx_buffer_info[i].map); 689 if (unlikely(err != 0)) { 690 ena_trace(ENA_ALERT, 691 "Unable to create Tx DMA map for buffer %d\n", i); 692 goto err_buf_info_unmap; 693 } 694 } 695 696 /* Allocate workqueues */ 697 int rc = workqueue_create(&tx_ring->enqueue_tq, "ena_tx_enq", 698 ena_deferred_mq_start, tx_ring, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 699 if (unlikely(rc != 0)) { 700 ena_trace(ENA_ALERT, 701 "Unable to create workqueue for enqueue task\n"); 702 i = tx_ring->ring_size; 703 goto err_buf_info_unmap; 704 } 705 706 #if 0 707 /* RSS set cpu for thread */ 708 #ifdef RSS 709 CPU_SETOF(que->cpu, &cpu_mask); 710 taskqueue_start_threads_cpuset(&tx_ring->enqueue_tq, 1, IPL_NET, 711 &cpu_mask, "%s tx_ring enq (bucket %d)", 712 device_xname(adapter->pdev), que->cpu); 713 #else /* RSS */ 714 taskqueue_start_threads(&tx_ring->enqueue_tq, 1, IPL_NET, 715 "%s txeq %d", device_xname(adapter->pdev), que->cpu); 716 #endif /* RSS */ 717 #endif 718 719 return (0); 720 721 err_buf_info_unmap: 722 while (i--) { 723 bus_dmamap_destroy(adapter->sc_dmat, 724 tx_ring->tx_buffer_info[i].map); 725 } 726 free(tx_ring->free_tx_ids, M_DEVBUF); 727 tx_ring->free_tx_ids = NULL; 728 err_buf_info_free: 729 free(tx_ring->tx_buffer_info, M_DEVBUF); 730 tx_ring->tx_buffer_info = NULL; 731 732 return (ENOMEM); 733 } 734 735 /** 736 * ena_free_tx_resources - Free Tx Resources per Queue 737 * @adapter: network interface device structure 738 * @qid: queue index 739 * 740 * Free all transmit software resources 741 **/ 742 static void 743 ena_free_tx_resources(struct ena_adapter *adapter, int qid) 744 { 745 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 746 747 workqueue_wait(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 748 workqueue_destroy(tx_ring->enqueue_tq); 749 tx_ring->enqueue_tq = NULL; 750 751 ENA_RING_MTX_LOCK(tx_ring); 752 /* Flush buffer ring, */ 753 drbr_flush(adapter->ifp, tx_ring->br); 754 755 /* Free buffer DMA maps, */ 756 for (int i = 0; i < tx_ring->ring_size; i++) { 757 m_freem(tx_ring->tx_buffer_info[i].mbuf); 758 tx_ring->tx_buffer_info[i].mbuf = NULL; 759 bus_dmamap_unload(adapter->sc_dmat, 760 tx_ring->tx_buffer_info[i].map); 761 bus_dmamap_destroy(adapter->sc_dmat, 762 tx_ring->tx_buffer_info[i].map); 763 } 764 ENA_RING_MTX_UNLOCK(tx_ring); 765 766 /* And free allocated memory. */ 767 free(tx_ring->tx_buffer_info, M_DEVBUF); 768 tx_ring->tx_buffer_info = NULL; 769 770 free(tx_ring->free_tx_ids, M_DEVBUF); 771 tx_ring->free_tx_ids = NULL; 772 } 773 774 /** 775 * ena_setup_all_tx_resources - allocate all queues Tx resources 776 * @adapter: network interface device structure 777 * 778 * Returns 0 on success, otherwise on failure. 779 **/ 780 static int 781 ena_setup_all_tx_resources(struct ena_adapter *adapter) 782 { 783 int i, rc; 784 785 for (i = 0; i < adapter->num_queues; i++) { 786 rc = ena_setup_tx_resources(adapter, i); 787 if (rc != 0) { 788 device_printf(adapter->pdev, 789 "Allocation for Tx Queue %u failed\n", i); 790 goto err_setup_tx; 791 } 792 } 793 794 return (0); 795 796 err_setup_tx: 797 /* Rewind the index freeing the rings as we go */ 798 while (i--) 799 ena_free_tx_resources(adapter, i); 800 return (rc); 801 } 802 803 /** 804 * ena_free_all_tx_resources - Free Tx Resources for All Queues 805 * @adapter: network interface device structure 806 * 807 * Free all transmit software resources 808 **/ 809 static void 810 ena_free_all_tx_resources(struct ena_adapter *adapter) 811 { 812 int i; 813 814 for (i = 0; i < adapter->num_queues; i++) 815 ena_free_tx_resources(adapter, i); 816 } 817 818 static inline int 819 validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 820 { 821 if (likely(req_id < rx_ring->ring_size)) 822 return (0); 823 824 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 825 req_id); 826 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 827 828 /* Trigger device reset */ 829 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 830 rx_ring->adapter->trigger_reset = true; 831 832 return (EFAULT); 833 } 834 835 /** 836 * ena_setup_rx_resources - allocate Rx resources (Descriptors) 837 * @adapter: network interface device structure 838 * @qid: queue index 839 * 840 * Returns 0 on success, otherwise on failure. 841 **/ 842 static int 843 ena_setup_rx_resources(struct ena_adapter *adapter, unsigned int qid) 844 { 845 struct ena_que *que = &adapter->que[qid]; 846 struct ena_ring *rx_ring = que->rx_ring; 847 int size, err, i; 848 #ifdef RSS 849 cpuset_t cpu_mask; 850 #endif 851 852 size = sizeof(struct ena_rx_buffer) * rx_ring->ring_size; 853 854 /* 855 * Alloc extra element so in rx path 856 * we can always prefetch rx_info + 1 857 */ 858 size += sizeof(struct ena_rx_buffer); 859 860 rx_ring->rx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 861 862 size = sizeof(uint16_t) * rx_ring->ring_size; 863 rx_ring->free_rx_ids = malloc(size, M_DEVBUF, M_WAITOK); 864 865 for (i = 0; i < rx_ring->ring_size; i++) 866 rx_ring->free_rx_ids[i] = i; 867 868 /* Reset RX statistics. */ 869 ena_reset_counters((struct evcnt *)&rx_ring->rx_stats, 870 sizeof(rx_ring->rx_stats)); 871 872 rx_ring->next_to_clean = 0; 873 rx_ring->next_to_use = 0; 874 875 /* ... and create the buffer DMA maps */ 876 for (i = 0; i < rx_ring->ring_size; i++) { 877 err = bus_dmamap_create(adapter->sc_dmat, 878 MJUM16BYTES, adapter->max_rx_sgl_size, MJUM16BYTES, 879 0, 0, 880 &(rx_ring->rx_buffer_info[i].map)); 881 if (err != 0) { 882 ena_trace(ENA_ALERT, 883 "Unable to create Rx DMA map for buffer %d\n", i); 884 goto err_buf_info_unmap; 885 } 886 } 887 888 #ifdef LRO 889 /* Create LRO for the ring */ 890 if ((adapter->ifp->if_capenable & IFCAP_LRO) != 0) { 891 int err = tcp_lro_init(&rx_ring->lro); 892 if (err != 0) { 893 device_printf(adapter->pdev, 894 "LRO[%d] Initialization failed!\n", qid); 895 } else { 896 ena_trace(ENA_INFO, 897 "RX Soft LRO[%d] Initialized\n", qid); 898 rx_ring->lro.ifp = adapter->ifp; 899 } 900 } 901 #endif 902 903 /* Allocate workqueues */ 904 int rc = workqueue_create(&rx_ring->cmpl_tq, "ena_rx_comp", 905 ena_deferred_rx_cleanup, rx_ring, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 906 if (unlikely(rc != 0)) { 907 ena_trace(ENA_ALERT, 908 "Unable to create workqueue for RX completion task\n"); 909 goto err_buf_info_unmap; 910 } 911 912 #if 0 913 /* RSS set cpu for thread */ 914 #ifdef RSS 915 CPU_SETOF(que->cpu, &cpu_mask); 916 taskqueue_start_threads_cpuset(&rx_ring->cmpl_tq, 1, IPL_NET, &cpu_mask, 917 "%s rx_ring cmpl (bucket %d)", 918 device_xname(adapter->pdev), que->cpu); 919 #else 920 taskqueue_start_threads(&rx_ring->cmpl_tq, 1, IPL_NET, 921 "%s rx_ring cmpl %d", device_xname(adapter->pdev), que->cpu); 922 #endif 923 #endif 924 925 return (0); 926 927 err_buf_info_unmap: 928 while (i--) { 929 bus_dmamap_destroy(adapter->sc_dmat, 930 rx_ring->rx_buffer_info[i].map); 931 } 932 933 free(rx_ring->free_rx_ids, M_DEVBUF); 934 rx_ring->free_rx_ids = NULL; 935 free(rx_ring->rx_buffer_info, M_DEVBUF); 936 rx_ring->rx_buffer_info = NULL; 937 return (ENOMEM); 938 } 939 940 /** 941 * ena_free_rx_resources - Free Rx Resources 942 * @adapter: network interface device structure 943 * @qid: queue index 944 * 945 * Free all receive software resources 946 **/ 947 static void 948 ena_free_rx_resources(struct ena_adapter *adapter, unsigned int qid) 949 { 950 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 951 952 workqueue_wait(rx_ring->cmpl_tq, &rx_ring->cmpl_task); 953 workqueue_destroy(rx_ring->cmpl_tq); 954 rx_ring->cmpl_tq = NULL; 955 956 /* Free buffer DMA maps, */ 957 for (int i = 0; i < rx_ring->ring_size; i++) { 958 m_freem(rx_ring->rx_buffer_info[i].mbuf); 959 rx_ring->rx_buffer_info[i].mbuf = NULL; 960 bus_dmamap_unload(adapter->sc_dmat, 961 rx_ring->rx_buffer_info[i].map); 962 bus_dmamap_destroy(adapter->sc_dmat, 963 rx_ring->rx_buffer_info[i].map); 964 } 965 966 #ifdef LRO 967 /* free LRO resources, */ 968 tcp_lro_free(&rx_ring->lro); 969 #endif 970 971 /* free allocated memory */ 972 free(rx_ring->rx_buffer_info, M_DEVBUF); 973 rx_ring->rx_buffer_info = NULL; 974 975 free(rx_ring->free_rx_ids, M_DEVBUF); 976 rx_ring->free_rx_ids = NULL; 977 } 978 979 /** 980 * ena_setup_all_rx_resources - allocate all queues Rx resources 981 * @adapter: network interface device structure 982 * 983 * Returns 0 on success, otherwise on failure. 984 **/ 985 static int 986 ena_setup_all_rx_resources(struct ena_adapter *adapter) 987 { 988 int i, rc = 0; 989 990 for (i = 0; i < adapter->num_queues; i++) { 991 rc = ena_setup_rx_resources(adapter, i); 992 if (rc != 0) { 993 device_printf(adapter->pdev, 994 "Allocation for Rx Queue %u failed\n", i); 995 goto err_setup_rx; 996 } 997 } 998 return (0); 999 1000 err_setup_rx: 1001 /* rewind the index freeing the rings as we go */ 1002 while (i--) 1003 ena_free_rx_resources(adapter, i); 1004 return (rc); 1005 } 1006 1007 /** 1008 * ena_free_all_rx_resources - Free Rx resources for all queues 1009 * @adapter: network interface device structure 1010 * 1011 * Free all receive software resources 1012 **/ 1013 static void 1014 ena_free_all_rx_resources(struct ena_adapter *adapter) 1015 { 1016 int i; 1017 1018 for (i = 0; i < adapter->num_queues; i++) 1019 ena_free_rx_resources(adapter, i); 1020 } 1021 1022 static inline int 1023 ena_alloc_rx_mbuf(struct ena_adapter *adapter, 1024 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 1025 { 1026 struct ena_com_buf *ena_buf; 1027 int error; 1028 int mlen; 1029 1030 /* if previous allocated frag is not used */ 1031 if (unlikely(rx_info->mbuf != NULL)) 1032 return (0); 1033 1034 /* Get mbuf using UMA allocator */ 1035 rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); 1036 1037 if (unlikely(rx_info->mbuf == NULL)) { 1038 counter_u64_add(rx_ring->rx_stats.mjum_alloc_fail, 1); 1039 rx_info->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1040 if (unlikely(rx_info->mbuf == NULL)) { 1041 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1042 return (ENOMEM); 1043 } 1044 mlen = MCLBYTES; 1045 } else { 1046 mlen = MJUM16BYTES; 1047 } 1048 /* Set mbuf length*/ 1049 rx_info->mbuf->m_pkthdr.len = rx_info->mbuf->m_len = mlen; 1050 1051 /* Map packets for DMA */ 1052 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1053 "Using tag %p for buffers' DMA mapping, mbuf %p len: %d", 1054 adapter->sc_dmat,rx_info->mbuf, rx_info->mbuf->m_len); 1055 error = bus_dmamap_load_mbuf(adapter->sc_dmat, rx_info->map, 1056 rx_info->mbuf, BUS_DMA_NOWAIT); 1057 if (unlikely((error != 0) || (rx_info->map->dm_nsegs != 1))) { 1058 ena_trace(ENA_WARNING, "failed to map mbuf, error: %d, " 1059 "nsegs: %d\n", error, rx_info->map->dm_nsegs); 1060 counter_u64_add(rx_ring->rx_stats.dma_mapping_err, 1); 1061 goto exit; 1062 1063 } 1064 1065 bus_dmamap_sync(adapter->sc_dmat, rx_info->map, 0, 1066 rx_info->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1067 1068 ena_buf = &rx_info->ena_buf; 1069 ena_buf->paddr = rx_info->map->dm_segs[0].ds_addr; 1070 ena_buf->len = mlen; 1071 1072 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1073 "ALLOC RX BUF: mbuf %p, rx_info %p, len %d, paddr %#jx\n", 1074 rx_info->mbuf, rx_info,ena_buf->len, (uintmax_t)ena_buf->paddr); 1075 1076 return (0); 1077 1078 exit: 1079 m_freem(rx_info->mbuf); 1080 rx_info->mbuf = NULL; 1081 return (EFAULT); 1082 } 1083 1084 static void 1085 ena_free_rx_mbuf(struct ena_adapter *adapter, struct ena_ring *rx_ring, 1086 struct ena_rx_buffer *rx_info) 1087 { 1088 1089 if (rx_info->mbuf == NULL) { 1090 ena_trace(ENA_WARNING, "Trying to free unallocated buffer\n"); 1091 return; 1092 } 1093 1094 bus_dmamap_unload(adapter->sc_dmat, rx_info->map); 1095 m_freem(rx_info->mbuf); 1096 rx_info->mbuf = NULL; 1097 } 1098 1099 /** 1100 * ena_refill_rx_bufs - Refills ring with descriptors 1101 * @rx_ring: the ring which we want to feed with free descriptors 1102 * @num: number of descriptors to refill 1103 * Refills the ring with newly allocated DMA-mapped mbufs for receiving 1104 **/ 1105 static int 1106 ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num) 1107 { 1108 struct ena_adapter *adapter = rx_ring->adapter; 1109 uint16_t next_to_use, req_id; 1110 uint32_t i; 1111 int rc; 1112 1113 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, "refill qid: %d", 1114 rx_ring->qid); 1115 1116 next_to_use = rx_ring->next_to_use; 1117 1118 for (i = 0; i < num; i++) { 1119 struct ena_rx_buffer *rx_info; 1120 1121 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, 1122 "RX buffer - next to use: %d", next_to_use); 1123 1124 req_id = rx_ring->free_rx_ids[next_to_use]; 1125 rc = validate_rx_req_id(rx_ring, req_id); 1126 if (unlikely(rc != 0)) 1127 break; 1128 1129 rx_info = &rx_ring->rx_buffer_info[req_id]; 1130 1131 rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info); 1132 if (unlikely(rc != 0)) { 1133 ena_trace(ENA_WARNING, 1134 "failed to alloc buffer for rx queue %d\n", 1135 rx_ring->qid); 1136 break; 1137 } 1138 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 1139 &rx_info->ena_buf, req_id); 1140 if (unlikely(rc != 0)) { 1141 ena_trace(ENA_WARNING, 1142 "failed to add buffer for rx queue %d\n", 1143 rx_ring->qid); 1144 break; 1145 } 1146 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 1147 rx_ring->ring_size); 1148 } 1149 1150 if (unlikely(i < num)) { 1151 counter_u64_add(rx_ring->rx_stats.refil_partial, 1); 1152 ena_trace(ENA_WARNING, 1153 "refilled rx qid %d with only %d mbufs (from %d)\n", 1154 rx_ring->qid, i, num); 1155 } 1156 1157 if (likely(i != 0)) { 1158 wmb(); 1159 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 1160 } 1161 rx_ring->next_to_use = next_to_use; 1162 return (i); 1163 } 1164 1165 static void 1166 ena_free_rx_bufs(struct ena_adapter *adapter, unsigned int qid) 1167 { 1168 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 1169 unsigned int i; 1170 1171 for (i = 0; i < rx_ring->ring_size; i++) { 1172 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 1173 1174 if (rx_info->mbuf != NULL) 1175 ena_free_rx_mbuf(adapter, rx_ring, rx_info); 1176 } 1177 } 1178 1179 /** 1180 * ena_refill_all_rx_bufs - allocate all queues Rx buffers 1181 * @adapter: network interface device structure 1182 * 1183 */ 1184 static void 1185 ena_refill_all_rx_bufs(struct ena_adapter *adapter) 1186 { 1187 struct ena_ring *rx_ring; 1188 int i, rc, bufs_num; 1189 1190 for (i = 0; i < adapter->num_queues; i++) { 1191 rx_ring = &adapter->rx_ring[i]; 1192 bufs_num = rx_ring->ring_size - 1; 1193 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 1194 1195 if (unlikely(rc != bufs_num)) 1196 ena_trace(ENA_WARNING, "refilling Queue %d failed. " 1197 "Allocated %d buffers from: %d\n", i, rc, bufs_num); 1198 } 1199 } 1200 1201 static void 1202 ena_free_all_rx_bufs(struct ena_adapter *adapter) 1203 { 1204 int i; 1205 1206 for (i = 0; i < adapter->num_queues; i++) 1207 ena_free_rx_bufs(adapter, i); 1208 } 1209 1210 /** 1211 * ena_free_tx_bufs - Free Tx Buffers per Queue 1212 * @adapter: network interface device structure 1213 * @qid: queue index 1214 **/ 1215 static void 1216 ena_free_tx_bufs(struct ena_adapter *adapter, unsigned int qid) 1217 { 1218 bool print_once = true; 1219 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 1220 1221 ENA_RING_MTX_LOCK(tx_ring); 1222 for (int i = 0; i < tx_ring->ring_size; i++) { 1223 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 1224 1225 if (tx_info->mbuf == NULL) 1226 continue; 1227 1228 if (print_once) { 1229 device_printf(adapter->pdev, 1230 "free uncompleted tx mbuf qid %d idx 0x%x", 1231 qid, i); 1232 print_once = false; 1233 } else { 1234 ena_trace(ENA_DBG, 1235 "free uncompleted tx mbuf qid %d idx 0x%x", 1236 qid, i); 1237 } 1238 1239 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1240 m_free(tx_info->mbuf); 1241 tx_info->mbuf = NULL; 1242 } 1243 ENA_RING_MTX_UNLOCK(tx_ring); 1244 } 1245 1246 static void 1247 ena_free_all_tx_bufs(struct ena_adapter *adapter) 1248 { 1249 1250 for (int i = 0; i < adapter->num_queues; i++) 1251 ena_free_tx_bufs(adapter, i); 1252 } 1253 1254 static void 1255 ena_destroy_all_tx_queues(struct ena_adapter *adapter) 1256 { 1257 uint16_t ena_qid; 1258 int i; 1259 1260 for (i = 0; i < adapter->num_queues; i++) { 1261 ena_qid = ENA_IO_TXQ_IDX(i); 1262 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1263 } 1264 } 1265 1266 static void 1267 ena_destroy_all_rx_queues(struct ena_adapter *adapter) 1268 { 1269 uint16_t ena_qid; 1270 int i; 1271 1272 for (i = 0; i < adapter->num_queues; i++) { 1273 ena_qid = ENA_IO_RXQ_IDX(i); 1274 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1275 } 1276 } 1277 1278 static void 1279 ena_destroy_all_io_queues(struct ena_adapter *adapter) 1280 { 1281 ena_destroy_all_tx_queues(adapter); 1282 ena_destroy_all_rx_queues(adapter); 1283 } 1284 1285 static inline int 1286 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 1287 { 1288 struct ena_adapter *adapter = tx_ring->adapter; 1289 struct ena_tx_buffer *tx_info = NULL; 1290 1291 if (likely(req_id < tx_ring->ring_size)) { 1292 tx_info = &tx_ring->tx_buffer_info[req_id]; 1293 if (tx_info->mbuf != NULL) 1294 return (0); 1295 } 1296 1297 if (tx_info->mbuf == NULL) 1298 device_printf(adapter->pdev, 1299 "tx_info doesn't have valid mbuf\n"); 1300 else 1301 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 1302 1303 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 1304 1305 return (EFAULT); 1306 } 1307 1308 static int 1309 ena_create_io_queues(struct ena_adapter *adapter) 1310 { 1311 struct ena_com_dev *ena_dev = adapter->ena_dev; 1312 struct ena_com_create_io_ctx ctx; 1313 struct ena_ring *ring; 1314 uint16_t ena_qid; 1315 uint32_t msix_vector; 1316 int rc, i; 1317 1318 /* Create TX queues */ 1319 for (i = 0; i < adapter->num_queues; i++) { 1320 msix_vector = ENA_IO_IRQ_IDX(i); 1321 ena_qid = ENA_IO_TXQ_IDX(i); 1322 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1323 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1324 ctx.queue_size = adapter->tx_ring_size; 1325 ctx.msix_vector = msix_vector; 1326 ctx.qid = ena_qid; 1327 rc = ena_com_create_io_queue(ena_dev, &ctx); 1328 if (rc != 0) { 1329 device_printf(adapter->pdev, 1330 "Failed to create io TX queue #%d rc: %d\n", i, rc); 1331 goto err_tx; 1332 } 1333 ring = &adapter->tx_ring[i]; 1334 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1335 &ring->ena_com_io_sq, 1336 &ring->ena_com_io_cq); 1337 if (rc != 0) { 1338 device_printf(adapter->pdev, 1339 "Failed to get TX queue handlers. TX queue num" 1340 " %d rc: %d\n", i, rc); 1341 ena_com_destroy_io_queue(ena_dev, ena_qid); 1342 goto err_tx; 1343 } 1344 } 1345 1346 /* Create RX queues */ 1347 for (i = 0; i < adapter->num_queues; i++) { 1348 msix_vector = ENA_IO_IRQ_IDX(i); 1349 ena_qid = ENA_IO_RXQ_IDX(i); 1350 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1351 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1352 ctx.queue_size = adapter->rx_ring_size; 1353 ctx.msix_vector = msix_vector; 1354 ctx.qid = ena_qid; 1355 rc = ena_com_create_io_queue(ena_dev, &ctx); 1356 if (unlikely(rc != 0)) { 1357 device_printf(adapter->pdev, 1358 "Failed to create io RX queue[%d] rc: %d\n", i, rc); 1359 goto err_rx; 1360 } 1361 1362 ring = &adapter->rx_ring[i]; 1363 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1364 &ring->ena_com_io_sq, 1365 &ring->ena_com_io_cq); 1366 if (unlikely(rc != 0)) { 1367 device_printf(adapter->pdev, 1368 "Failed to get RX queue handlers. RX queue num" 1369 " %d rc: %d\n", i, rc); 1370 ena_com_destroy_io_queue(ena_dev, ena_qid); 1371 goto err_rx; 1372 } 1373 } 1374 1375 return (0); 1376 1377 err_rx: 1378 while (i--) 1379 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1380 i = adapter->num_queues; 1381 err_tx: 1382 while (i--) 1383 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1384 1385 return (ENXIO); 1386 } 1387 1388 /** 1389 * ena_tx_cleanup - clear sent packets and corresponding descriptors 1390 * @tx_ring: ring for which we want to clean packets 1391 * 1392 * Once packets are sent, we ask the device in a loop for no longer used 1393 * descriptors. We find the related mbuf chain in a map (index in an array) 1394 * and free it, then update ring state. 1395 * This is performed in "endless" loop, updating ring pointers every 1396 * TX_COMMIT. The first check of free descriptor is performed before the actual 1397 * loop, then repeated at the loop end. 1398 **/ 1399 static int 1400 ena_tx_cleanup(struct ena_ring *tx_ring) 1401 { 1402 struct ena_adapter *adapter; 1403 struct ena_com_io_cq* io_cq; 1404 uint16_t next_to_clean; 1405 uint16_t req_id; 1406 uint16_t ena_qid; 1407 unsigned int total_done = 0; 1408 int rc; 1409 int commit = TX_COMMIT; 1410 int budget = TX_BUDGET; 1411 int work_done; 1412 1413 adapter = tx_ring->que->adapter; 1414 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1415 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1416 next_to_clean = tx_ring->next_to_clean; 1417 1418 do { 1419 struct ena_tx_buffer *tx_info; 1420 struct mbuf *mbuf; 1421 1422 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 1423 if (unlikely(rc != 0)) 1424 break; 1425 1426 rc = validate_tx_req_id(tx_ring, req_id); 1427 if (unlikely(rc != 0)) 1428 break; 1429 1430 tx_info = &tx_ring->tx_buffer_info[req_id]; 1431 1432 mbuf = tx_info->mbuf; 1433 1434 tx_info->mbuf = NULL; 1435 bintime_clear(&tx_info->timestamp); 1436 1437 if (likely(tx_info->num_of_bufs != 0)) { 1438 /* Map is no longer required */ 1439 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1440 } 1441 1442 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed", 1443 tx_ring->qid, mbuf); 1444 1445 m_freem(mbuf); 1446 1447 total_done += tx_info->tx_descs; 1448 1449 tx_ring->free_tx_ids[next_to_clean] = req_id; 1450 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 1451 tx_ring->ring_size); 1452 1453 if (unlikely(--commit == 0)) { 1454 commit = TX_COMMIT; 1455 /* update ring state every TX_COMMIT descriptor */ 1456 tx_ring->next_to_clean = next_to_clean; 1457 ena_com_comp_ack( 1458 &adapter->ena_dev->io_sq_queues[ena_qid], 1459 total_done); 1460 ena_com_update_dev_comp_head(io_cq); 1461 total_done = 0; 1462 } 1463 } while (likely(--budget)); 1464 1465 work_done = TX_BUDGET - budget; 1466 1467 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d", 1468 tx_ring->qid, work_done); 1469 1470 /* If there is still something to commit update ring state */ 1471 if (likely(commit != TX_COMMIT)) { 1472 tx_ring->next_to_clean = next_to_clean; 1473 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 1474 total_done); 1475 ena_com_update_dev_comp_head(io_cq); 1476 } 1477 1478 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 1479 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, NULL); 1480 1481 return (work_done); 1482 } 1483 1484 #if 0 1485 static void 1486 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1487 struct mbuf *mbuf) 1488 { 1489 struct ena_adapter *adapter = rx_ring->adapter; 1490 1491 if (likely(adapter->rss_support)) { 1492 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 1493 1494 if (ena_rx_ctx->frag && 1495 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 1496 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1497 return; 1498 } 1499 1500 switch (ena_rx_ctx->l3_proto) { 1501 case ENA_ETH_IO_L3_PROTO_IPV4: 1502 switch (ena_rx_ctx->l4_proto) { 1503 case ENA_ETH_IO_L4_PROTO_TCP: 1504 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 1505 break; 1506 case ENA_ETH_IO_L4_PROTO_UDP: 1507 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 1508 break; 1509 default: 1510 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 1511 } 1512 break; 1513 case ENA_ETH_IO_L3_PROTO_IPV6: 1514 switch (ena_rx_ctx->l4_proto) { 1515 case ENA_ETH_IO_L4_PROTO_TCP: 1516 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 1517 break; 1518 case ENA_ETH_IO_L4_PROTO_UDP: 1519 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 1520 break; 1521 default: 1522 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 1523 } 1524 break; 1525 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 1526 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1527 break; 1528 default: 1529 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1530 } 1531 } else { 1532 mbuf->m_pkthdr.flowid = rx_ring->qid; 1533 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1534 } 1535 } 1536 #endif 1537 1538 /** 1539 * ena_rx_mbuf - assemble mbuf from descriptors 1540 * @rx_ring: ring for which we want to clean packets 1541 * @ena_bufs: buffer info 1542 * @ena_rx_ctx: metadata for this packet(s) 1543 * @next_to_clean: ring pointer, will be updated only upon success 1544 * 1545 **/ 1546 static struct mbuf* 1547 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 1548 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 1549 { 1550 struct mbuf *mbuf; 1551 struct ena_rx_buffer *rx_info; 1552 struct ena_adapter *adapter; 1553 unsigned int descs = ena_rx_ctx->descs; 1554 uint16_t ntc, len, req_id, buf = 0; 1555 1556 ntc = *next_to_clean; 1557 adapter = rx_ring->adapter; 1558 rx_info = &rx_ring->rx_buffer_info[ntc]; 1559 1560 if (unlikely(rx_info->mbuf == NULL)) { 1561 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1562 return (NULL); 1563 } 1564 1565 len = ena_bufs[buf].len; 1566 req_id = ena_bufs[buf].req_id; 1567 rx_info = &rx_ring->rx_buffer_info[req_id]; 1568 1569 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx", 1570 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 1571 1572 mbuf = rx_info->mbuf; 1573 KASSERT(mbuf->m_flags & M_PKTHDR); 1574 mbuf->m_pkthdr.len = len; 1575 mbuf->m_len = len; 1576 m_set_rcvif(mbuf, rx_ring->que->adapter->ifp); 1577 1578 /* Fill mbuf with hash key and it's interpretation for optimization */ 1579 #if 0 1580 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 1581 #endif 1582 1583 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf 0x%p, flags=0x%x, len: %d", 1584 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 1585 1586 /* DMA address is not needed anymore, unmap it */ 1587 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1588 1589 rx_info->mbuf = NULL; 1590 rx_ring->free_rx_ids[ntc] = req_id; 1591 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1592 1593 /* 1594 * While we have more than 1 descriptors for one rcvd packet, append 1595 * other mbufs to the main one 1596 */ 1597 while (--descs) { 1598 ++buf; 1599 len = ena_bufs[buf].len; 1600 req_id = ena_bufs[buf].req_id; 1601 rx_info = &rx_ring->rx_buffer_info[req_id]; 1602 1603 if (unlikely(rx_info->mbuf == NULL)) { 1604 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1605 /* 1606 * If one of the required mbufs was not allocated yet, 1607 * we can break there. 1608 * All earlier used descriptors will be reallocated 1609 * later and not used mbufs can be reused. 1610 * The next_to_clean pointer will not be updated in case 1611 * of an error, so caller should advance it manually 1612 * in error handling routine to keep it up to date 1613 * with hw ring. 1614 */ 1615 m_freem(mbuf); 1616 return (NULL); 1617 } 1618 1619 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 1620 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1621 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p", 1622 mbuf); 1623 } 1624 1625 ena_trace(ENA_DBG | ENA_RXPTH, 1626 "rx mbuf updated. len %d", mbuf->m_pkthdr.len); 1627 1628 /* Free already appended mbuf, it won't be useful anymore */ 1629 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1630 m_freem(rx_info->mbuf); 1631 rx_info->mbuf = NULL; 1632 1633 rx_ring->free_rx_ids[ntc] = req_id; 1634 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1635 } 1636 1637 *next_to_clean = ntc; 1638 1639 return (mbuf); 1640 } 1641 1642 /** 1643 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 1644 **/ 1645 static inline void 1646 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1647 struct mbuf *mbuf) 1648 { 1649 1650 /* IPv4 */ 1651 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { 1652 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1653 if (ena_rx_ctx->l3_csum_err) { 1654 /* ipv4 checksum error */ 1655 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1656 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1657 ena_trace(ENA_DBG, "RX IPv4 header checksum error"); 1658 return; 1659 } 1660 1661 /* TCP/UDP */ 1662 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1663 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1664 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv4 : M_CSUM_UDPv4; 1665 if (ena_rx_ctx->l4_csum_err) { 1666 /* TCP/UDP checksum error */ 1667 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1668 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1669 ena_trace(ENA_DBG, "RX L4 checksum error"); 1670 } 1671 } 1672 } 1673 /* IPv6 */ 1674 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { 1675 /* TCP/UDP */ 1676 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1677 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1678 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv6 : M_CSUM_UDPv6; 1679 if (ena_rx_ctx->l4_csum_err) { 1680 /* TCP/UDP checksum error */ 1681 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1682 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1683 ena_trace(ENA_DBG, "RX L4 checksum error"); 1684 } 1685 } 1686 } 1687 } 1688 1689 static void 1690 ena_deferred_rx_cleanup(struct work *wk, void *arg) 1691 { 1692 struct ena_ring *rx_ring = arg; 1693 int budget = CLEAN_BUDGET; 1694 1695 atomic_swap_uint(&rx_ring->task_pending, 0); 1696 1697 ENA_RING_MTX_LOCK(rx_ring); 1698 /* 1699 * If deferred task was executed, perform cleanup of all awaiting 1700 * descs (or until given budget is depleted to avoid infinite loop). 1701 */ 1702 while (likely(budget--)) { 1703 if (ena_rx_cleanup(rx_ring) == 0) 1704 break; 1705 } 1706 ENA_RING_MTX_UNLOCK(rx_ring); 1707 } 1708 1709 /** 1710 * ena_rx_cleanup - handle rx irq 1711 * @arg: ring for which irq is being handled 1712 **/ 1713 static int 1714 ena_rx_cleanup(struct ena_ring *rx_ring) 1715 { 1716 struct ena_adapter *adapter; 1717 struct mbuf *mbuf; 1718 struct ena_com_rx_ctx ena_rx_ctx; 1719 struct ena_com_io_cq* io_cq; 1720 struct ena_com_io_sq* io_sq; 1721 struct ifnet *ifp; 1722 uint16_t ena_qid; 1723 uint16_t next_to_clean; 1724 uint32_t refill_required; 1725 uint32_t refill_threshold; 1726 uint32_t do_if_input = 0; 1727 unsigned int qid; 1728 int rc, i; 1729 int budget = RX_BUDGET; 1730 1731 adapter = rx_ring->que->adapter; 1732 ifp = adapter->ifp; 1733 qid = rx_ring->que->id; 1734 ena_qid = ENA_IO_RXQ_IDX(qid); 1735 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1736 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1737 next_to_clean = rx_ring->next_to_clean; 1738 1739 ena_trace(ENA_DBG, "rx: qid %d", qid); 1740 1741 do { 1742 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1743 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 1744 ena_rx_ctx.descs = 0; 1745 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 1746 1747 if (unlikely(rc != 0)) 1748 goto error; 1749 1750 if (unlikely(ena_rx_ctx.descs == 0)) 1751 break; 1752 1753 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 1754 "descs #: %d l3 proto %d l4 proto %d hash: %x", 1755 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1756 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1757 1758 /* Receive mbuf from the ring */ 1759 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 1760 &ena_rx_ctx, &next_to_clean); 1761 1762 /* Exit if we failed to retrieve a buffer */ 1763 if (unlikely(mbuf == NULL)) { 1764 for (i = 0; i < ena_rx_ctx.descs; ++i) { 1765 rx_ring->free_rx_ids[next_to_clean] = 1766 rx_ring->ena_bufs[i].req_id; 1767 next_to_clean = 1768 ENA_RX_RING_IDX_NEXT(next_to_clean, 1769 rx_ring->ring_size); 1770 1771 } 1772 break; 1773 } 1774 1775 if (((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) || 1776 ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) || 1777 ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) || 1778 ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) || 1779 ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0)) { 1780 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 1781 } 1782 1783 counter_enter(); 1784 counter_u64_add_protected(rx_ring->rx_stats.bytes, 1785 mbuf->m_pkthdr.len); 1786 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 1787 mbuf->m_pkthdr.len); 1788 counter_exit(); 1789 /* 1790 * LRO is only for IP/TCP packets and TCP checksum of the packet 1791 * should be computed by hardware. 1792 */ 1793 do_if_input = 1; 1794 #ifdef LRO 1795 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 1796 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 1797 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 1798 /* 1799 * Send to the stack if: 1800 * - LRO not enabled, or 1801 * - no LRO resources, or 1802 * - lro enqueue fails 1803 */ 1804 if ((rx_ring->lro.lro_cnt != 0) && 1805 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 1806 do_if_input = 0; 1807 } 1808 #endif 1809 if (do_if_input != 0) { 1810 ena_trace(ENA_DBG | ENA_RXPTH, 1811 "calling if_input() with mbuf %p", mbuf); 1812 if_percpuq_enqueue(ifp->if_percpuq, mbuf); 1813 } 1814 1815 counter_enter(); 1816 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 1817 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 1818 counter_exit(); 1819 } while (--budget); 1820 1821 rx_ring->next_to_clean = next_to_clean; 1822 1823 refill_required = ena_com_free_desc(io_sq); 1824 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1825 1826 if (refill_required > refill_threshold) { 1827 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1828 ena_refill_rx_bufs(rx_ring, refill_required); 1829 } 1830 1831 #ifdef LRO 1832 tcp_lro_flush_all(&rx_ring->lro); 1833 #endif 1834 1835 return (RX_BUDGET - budget); 1836 1837 error: 1838 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 1839 return (RX_BUDGET - budget); 1840 } 1841 1842 /********************************************************************* 1843 * 1844 * MSIX & Interrupt Service routine 1845 * 1846 **********************************************************************/ 1847 1848 /** 1849 * ena_handle_msix - MSIX Interrupt Handler for admin/async queue 1850 * @arg: interrupt number 1851 **/ 1852 static int 1853 ena_intr_msix_mgmnt(void *arg) 1854 { 1855 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1856 1857 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1858 if (likely(adapter->running)) 1859 ena_com_aenq_intr_handler(adapter->ena_dev, arg); 1860 1861 return 1; 1862 } 1863 1864 /** 1865 * ena_handle_msix - MSIX Interrupt Handler for Tx/Rx 1866 * @arg: interrupt number 1867 **/ 1868 static int 1869 ena_handle_msix(void *arg) 1870 { 1871 struct ena_que *que = arg; 1872 struct ena_adapter *adapter = que->adapter; 1873 struct ifnet *ifp = adapter->ifp; 1874 struct ena_ring *tx_ring; 1875 struct ena_ring *rx_ring; 1876 struct ena_com_io_cq* io_cq; 1877 struct ena_eth_io_intr_reg intr_reg; 1878 int qid, ena_qid; 1879 int txc, rxc, i; 1880 1881 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1882 return 0; 1883 1884 ena_trace(ENA_DBG, "MSI-X TX/RX routine"); 1885 1886 tx_ring = que->tx_ring; 1887 rx_ring = que->rx_ring; 1888 qid = que->id; 1889 ena_qid = ENA_IO_TXQ_IDX(qid); 1890 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1891 1892 for (i = 0; i < CLEAN_BUDGET; ++i) { 1893 /* 1894 * If lock cannot be acquired, then deferred cleanup task was 1895 * being executed and rx ring is being cleaned up in 1896 * another thread. 1897 */ 1898 if (likely(ENA_RING_MTX_TRYLOCK(rx_ring) != 0)) { 1899 rxc = ena_rx_cleanup(rx_ring); 1900 ENA_RING_MTX_UNLOCK(rx_ring); 1901 } else { 1902 rxc = 0; 1903 } 1904 1905 /* Protection from calling ena_tx_cleanup from ena_start_xmit */ 1906 ENA_RING_MTX_LOCK(tx_ring); 1907 txc = ena_tx_cleanup(tx_ring); 1908 ENA_RING_MTX_UNLOCK(tx_ring); 1909 1910 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1911 return 0; 1912 1913 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 1914 break; 1915 } 1916 1917 /* Signal that work is done and unmask interrupt */ 1918 ena_com_update_intr_reg(&intr_reg, 1919 RX_IRQ_INTERVAL, 1920 TX_IRQ_INTERVAL, 1921 true); 1922 ena_com_unmask_intr(io_cq, &intr_reg); 1923 1924 return 1; 1925 } 1926 1927 static int 1928 ena_enable_msix(struct ena_adapter *adapter) 1929 { 1930 int msix_req; 1931 int counts[PCI_INTR_TYPE_SIZE]; 1932 int max_type; 1933 1934 /* Reserved the max msix vectors we might need */ 1935 msix_req = ENA_MAX_MSIX_VEC(adapter->num_queues); 1936 1937 counts[PCI_INTR_TYPE_INTX] = 0; 1938 counts[PCI_INTR_TYPE_MSI] = 0; 1939 counts[PCI_INTR_TYPE_MSIX] = msix_req; 1940 max_type = PCI_INTR_TYPE_MSIX; 1941 1942 if (pci_intr_alloc(&adapter->sc_pa, &adapter->sc_intrs, counts, 1943 max_type) != 0) { 1944 aprint_error_dev(adapter->pdev, 1945 "failed to allocate interrupt\n"); 1946 return ENOSPC; 1947 } 1948 1949 adapter->sc_nintrs = counts[PCI_INTR_TYPE_MSIX]; 1950 1951 if (counts[PCI_INTR_TYPE_MSIX] != msix_req) { 1952 device_printf(adapter->pdev, 1953 "Enable only %d MSI-x (out of %d), reduce " 1954 "the number of queues\n", adapter->sc_nintrs, msix_req); 1955 adapter->num_queues = adapter->sc_nintrs - ENA_ADMIN_MSIX_VEC; 1956 } 1957 1958 return 0; 1959 } 1960 1961 #if 0 1962 static void 1963 ena_setup_io_intr(struct ena_adapter *adapter) 1964 { 1965 static int last_bind_cpu = -1; 1966 int irq_idx; 1967 1968 for (int i = 0; i < adapter->num_queues; i++) { 1969 irq_idx = ENA_IO_IRQ_IDX(i); 1970 1971 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1972 "%s-TxRx-%d", device_xname(adapter->pdev), i); 1973 adapter->irq_tbl[irq_idx].handler = ena_handle_msix; 1974 adapter->irq_tbl[irq_idx].data = &adapter->que[i]; 1975 adapter->irq_tbl[irq_idx].vector = 1976 adapter->msix_entries[irq_idx].vector; 1977 ena_trace(ENA_INFO | ENA_IOQ, "ena_setup_io_intr vector: %d\n", 1978 adapter->msix_entries[irq_idx].vector); 1979 #ifdef RSS 1980 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1981 rss_getcpu(i % rss_getnumbuckets()); 1982 #else 1983 /* 1984 * We still want to bind rings to the corresponding cpu 1985 * using something similar to the RSS round-robin technique. 1986 */ 1987 if (unlikely(last_bind_cpu < 0)) 1988 last_bind_cpu = CPU_FIRST(); 1989 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1990 last_bind_cpu; 1991 last_bind_cpu = CPU_NEXT(last_bind_cpu); 1992 #endif 1993 } 1994 } 1995 #endif 1996 1997 static int 1998 ena_request_mgmnt_irq(struct ena_adapter *adapter) 1999 { 2000 const char *intrstr; 2001 char intrbuf[PCI_INTRSTR_LEN]; 2002 char intr_xname[INTRDEVNAMEBUF]; 2003 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 2004 const int irq_slot = ENA_MGMNT_IRQ_IDX; 2005 2006 KASSERT(adapter->sc_intrs != NULL); 2007 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 2008 2009 snprintf(intr_xname, sizeof(intr_xname), "%s mgmnt", 2010 device_xname(adapter->pdev)); 2011 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 2012 intrbuf, sizeof(intrbuf)); 2013 2014 adapter->sc_ihs[irq_slot] = pci_intr_establish_xname( 2015 pc, adapter->sc_intrs[irq_slot], 2016 IPL_NET, ena_intr_msix_mgmnt, adapter, intr_xname); 2017 2018 if (adapter->sc_ihs[irq_slot] == NULL) { 2019 device_printf(adapter->pdev, "failed to register " 2020 "interrupt handler for MGMNT irq %s\n", 2021 intrstr); 2022 return ENOMEM; 2023 } 2024 2025 aprint_normal_dev(adapter->pdev, 2026 "for MGMNT interrupting at %s\n", intrstr); 2027 2028 return 0; 2029 } 2030 2031 static int 2032 ena_request_io_irq(struct ena_adapter *adapter) 2033 { 2034 const char *intrstr; 2035 char intrbuf[PCI_INTRSTR_LEN]; 2036 char intr_xname[INTRDEVNAMEBUF]; 2037 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 2038 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2039 void *vih; 2040 kcpuset_t *affinity; 2041 int i; 2042 2043 KASSERT(adapter->sc_intrs != NULL); 2044 2045 kcpuset_create(&affinity, false); 2046 2047 for (i = 0; i < adapter->num_queues; i++) { 2048 int irq_slot = i + irq_off; 2049 int affinity_to = (irq_slot) % ncpu; 2050 2051 KASSERT((void *)adapter->sc_intrs[irq_slot] != NULL); 2052 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 2053 2054 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 2055 device_xname(adapter->pdev), i); 2056 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 2057 intrbuf, sizeof(intrbuf)); 2058 2059 vih = pci_intr_establish_xname(adapter->sc_pa.pa_pc, 2060 adapter->sc_intrs[irq_slot], IPL_NET, 2061 ena_handle_msix, &adapter->que[i], intr_xname); 2062 2063 if (adapter->sc_ihs[ENA_MGMNT_IRQ_IDX] == NULL) { 2064 device_printf(adapter->pdev, "failed to register " 2065 "interrupt handler for IO queue %d irq %s\n", 2066 i, intrstr); 2067 goto err; 2068 } 2069 2070 kcpuset_zero(affinity); 2071 /* Round-robin affinity */ 2072 kcpuset_set(affinity, affinity_to); 2073 int error = interrupt_distribute(vih, affinity, NULL); 2074 if (error == 0) { 2075 aprint_normal_dev(adapter->pdev, 2076 "for IO queue %d interrupting at %s" 2077 " affinity to %u\n", i, intrstr, affinity_to); 2078 } else { 2079 aprint_normal_dev(adapter->pdev, 2080 "for IO queue %d interrupting at %s\n", i, intrstr); 2081 } 2082 2083 adapter->sc_ihs[irq_slot] = vih; 2084 2085 #ifdef RSS 2086 ena_trace(ENA_INFO, "queue %d - RSS bucket %d\n", 2087 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2088 #else 2089 ena_trace(ENA_INFO, "queue %d - cpu %d\n", 2090 i - ENA_IO_IRQ_FIRST_IDX, affinity_to); 2091 #endif 2092 } 2093 2094 kcpuset_destroy(affinity); 2095 return 0; 2096 2097 err: 2098 kcpuset_destroy(affinity); 2099 2100 for (i--; i >= 0; i--) { 2101 int irq_slot __diagused = i + irq_off; 2102 KASSERT(adapter->sc_ihs[irq_slot] != NULL); 2103 pci_intr_disestablish(adapter->sc_pa.pa_pc, adapter->sc_ihs[i]); 2104 adapter->sc_ihs[i] = NULL; 2105 } 2106 2107 return ENOSPC; 2108 } 2109 2110 static void 2111 ena_free_mgmnt_irq(struct ena_adapter *adapter) 2112 { 2113 const int irq_slot = ENA_MGMNT_IRQ_IDX; 2114 2115 if (adapter->sc_ihs[irq_slot]) { 2116 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2117 adapter->sc_ihs[irq_slot]); 2118 adapter->sc_ihs[irq_slot] = NULL; 2119 } 2120 } 2121 2122 static void 2123 ena_free_io_irq(struct ena_adapter *adapter) 2124 { 2125 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2126 2127 for (int i = 0; i < adapter->num_queues; i++) { 2128 int irq_slot = i + irq_off; 2129 2130 if (adapter->sc_ihs[irq_slot]) { 2131 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2132 adapter->sc_ihs[i]); 2133 adapter->sc_ihs[i] = NULL; 2134 } 2135 } 2136 } 2137 2138 static void 2139 ena_free_irqs(struct ena_adapter* adapter) 2140 { 2141 2142 ena_free_io_irq(adapter); 2143 ena_free_mgmnt_irq(adapter); 2144 ena_disable_msix(adapter); 2145 } 2146 2147 static void 2148 ena_disable_msix(struct ena_adapter *adapter) 2149 { 2150 pci_intr_release(adapter->sc_pa.pa_pc, adapter->sc_intrs, 2151 adapter->sc_nintrs); 2152 } 2153 2154 static void 2155 ena_unmask_all_io_irqs(struct ena_adapter *adapter) 2156 { 2157 struct ena_com_io_cq* io_cq; 2158 struct ena_eth_io_intr_reg intr_reg; 2159 uint16_t ena_qid; 2160 int i; 2161 2162 /* Unmask interrupts for all queues */ 2163 for (i = 0; i < adapter->num_queues; i++) { 2164 ena_qid = ENA_IO_TXQ_IDX(i); 2165 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 2166 ena_com_update_intr_reg(&intr_reg, 0, 0, true); 2167 ena_com_unmask_intr(io_cq, &intr_reg); 2168 } 2169 } 2170 2171 /* Configure the Rx forwarding */ 2172 static int 2173 ena_rss_configure(struct ena_adapter *adapter) 2174 { 2175 struct ena_com_dev *ena_dev = adapter->ena_dev; 2176 int rc; 2177 2178 /* Set indirect table */ 2179 rc = ena_com_indirect_table_set(ena_dev); 2180 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2181 return (rc); 2182 2183 /* Configure hash function (if supported) */ 2184 rc = ena_com_set_hash_function(ena_dev); 2185 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2186 return (rc); 2187 2188 /* Configure hash inputs (if supported) */ 2189 rc = ena_com_set_hash_ctrl(ena_dev); 2190 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2191 return (rc); 2192 2193 return (0); 2194 } 2195 2196 static int 2197 ena_up_complete(struct ena_adapter *adapter) 2198 { 2199 int rc; 2200 2201 if (likely(adapter->rss_support)) { 2202 rc = ena_rss_configure(adapter); 2203 if (rc != 0) 2204 return (rc); 2205 } 2206 2207 rc = ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu); 2208 if (unlikely(rc != 0)) 2209 return (rc); 2210 2211 ena_refill_all_rx_bufs(adapter); 2212 ena_reset_counters((struct evcnt *)&adapter->hw_stats, 2213 sizeof(adapter->hw_stats)); 2214 2215 return (0); 2216 } 2217 2218 static int 2219 ena_up(struct ena_adapter *adapter) 2220 { 2221 int rc = 0; 2222 2223 #if 0 2224 if (unlikely(device_is_attached(adapter->pdev) == 0)) { 2225 device_printf(adapter->pdev, "device is not attached!\n"); 2226 return (ENXIO); 2227 } 2228 #endif 2229 2230 if (unlikely(!adapter->running)) { 2231 device_printf(adapter->pdev, "device is not running!\n"); 2232 return (ENXIO); 2233 } 2234 2235 if (!adapter->up) { 2236 device_printf(adapter->pdev, "device is going UP\n"); 2237 2238 /* setup interrupts for IO queues */ 2239 rc = ena_request_io_irq(adapter); 2240 if (unlikely(rc != 0)) { 2241 ena_trace(ENA_ALERT, "err_req_irq"); 2242 goto err_req_irq; 2243 } 2244 2245 /* allocate transmit descriptors */ 2246 rc = ena_setup_all_tx_resources(adapter); 2247 if (unlikely(rc != 0)) { 2248 ena_trace(ENA_ALERT, "err_setup_tx"); 2249 goto err_setup_tx; 2250 } 2251 2252 /* allocate receive descriptors */ 2253 rc = ena_setup_all_rx_resources(adapter); 2254 if (unlikely(rc != 0)) { 2255 ena_trace(ENA_ALERT, "err_setup_rx"); 2256 goto err_setup_rx; 2257 } 2258 2259 /* create IO queues for Rx & Tx */ 2260 rc = ena_create_io_queues(adapter); 2261 if (unlikely(rc != 0)) { 2262 ena_trace(ENA_ALERT, 2263 "create IO queues failed"); 2264 goto err_io_que; 2265 } 2266 2267 if (unlikely(adapter->link_status)) 2268 if_link_state_change(adapter->ifp, LINK_STATE_UP); 2269 2270 rc = ena_up_complete(adapter); 2271 if (unlikely(rc != 0)) 2272 goto err_up_complete; 2273 2274 counter_u64_add(adapter->dev_stats.interface_up, 1); 2275 2276 ena_update_hwassist(adapter); 2277 2278 if_setdrvflagbits(adapter->ifp, IFF_RUNNING, 2279 IFF_OACTIVE); 2280 2281 callout_reset(&adapter->timer_service, hz, 2282 ena_timer_service, (void *)adapter); 2283 2284 adapter->up = true; 2285 2286 ena_unmask_all_io_irqs(adapter); 2287 } 2288 2289 return (0); 2290 2291 err_up_complete: 2292 ena_destroy_all_io_queues(adapter); 2293 err_io_que: 2294 ena_free_all_rx_resources(adapter); 2295 err_setup_rx: 2296 ena_free_all_tx_resources(adapter); 2297 err_setup_tx: 2298 ena_free_io_irq(adapter); 2299 err_req_irq: 2300 return (rc); 2301 } 2302 2303 #if 0 2304 static uint64_t 2305 ena_get_counter(struct ifnet *ifp, ift_counter cnt) 2306 { 2307 struct ena_adapter *adapter; 2308 struct ena_hw_stats *stats; 2309 2310 adapter = if_getsoftc(ifp); 2311 stats = &adapter->hw_stats; 2312 2313 switch (cnt) { 2314 case IFCOUNTER_IPACKETS: 2315 return (counter_u64_fetch(stats->rx_packets)); 2316 case IFCOUNTER_OPACKETS: 2317 return (counter_u64_fetch(stats->tx_packets)); 2318 case IFCOUNTER_IBYTES: 2319 return (counter_u64_fetch(stats->rx_bytes)); 2320 case IFCOUNTER_OBYTES: 2321 return (counter_u64_fetch(stats->tx_bytes)); 2322 case IFCOUNTER_IQDROPS: 2323 return (counter_u64_fetch(stats->rx_drops)); 2324 default: 2325 return (if_get_counter_default(ifp, cnt)); 2326 } 2327 } 2328 #endif 2329 2330 static int 2331 ena_media_change(struct ifnet *ifp) 2332 { 2333 /* Media Change is not supported by firmware */ 2334 return (0); 2335 } 2336 2337 static void 2338 ena_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2339 { 2340 struct ena_adapter *adapter = if_getsoftc(ifp); 2341 ena_trace(ENA_DBG, "enter"); 2342 2343 mutex_enter(&adapter->global_mtx); 2344 2345 ifmr->ifm_status = IFM_AVALID; 2346 ifmr->ifm_active = IFM_ETHER; 2347 2348 if (!adapter->link_status) { 2349 mutex_exit(&adapter->global_mtx); 2350 ena_trace(ENA_INFO, "link_status = false"); 2351 return; 2352 } 2353 2354 ifmr->ifm_status |= IFM_ACTIVE; 2355 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2356 2357 mutex_exit(&adapter->global_mtx); 2358 } 2359 2360 static int 2361 ena_init(struct ifnet *ifp) 2362 { 2363 struct ena_adapter *adapter = if_getsoftc(ifp); 2364 2365 if (!adapter->up) { 2366 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2367 ena_up(adapter); 2368 rw_exit(&adapter->ioctl_sx); 2369 } 2370 2371 return 0; 2372 } 2373 2374 static int 2375 ena_ioctl(struct ifnet *ifp, u_long command, void *data) 2376 { 2377 struct ena_adapter *adapter; 2378 struct ifreq *ifr; 2379 int rc; 2380 2381 adapter = ifp->if_softc; 2382 ifr = (struct ifreq *)data; 2383 2384 /* 2385 * Acquiring lock to prevent from running up and down routines parallel. 2386 */ 2387 rc = 0; 2388 switch (command) { 2389 case SIOCSIFMTU: 2390 if (ifp->if_mtu == ifr->ifr_mtu) 2391 break; 2392 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2393 ena_down(adapter); 2394 2395 ena_change_mtu(ifp, ifr->ifr_mtu); 2396 2397 rc = ena_up(adapter); 2398 rw_exit(&adapter->ioctl_sx); 2399 break; 2400 2401 case SIOCSIFFLAGS: 2402 if ((ifp->if_flags & IFF_UP) != 0) { 2403 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2404 if ((ifp->if_flags & (IFF_PROMISC | 2405 IFF_ALLMULTI)) != 0) { 2406 device_printf(adapter->pdev, 2407 "ioctl promisc/allmulti\n"); 2408 } 2409 } else { 2410 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2411 rc = ena_up(adapter); 2412 rw_exit(&adapter->ioctl_sx); 2413 } 2414 } else { 2415 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2416 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2417 ena_down(adapter); 2418 rw_exit(&adapter->ioctl_sx); 2419 } 2420 } 2421 break; 2422 2423 case SIOCADDMULTI: 2424 case SIOCDELMULTI: 2425 break; 2426 2427 case SIOCSIFCAP: 2428 { 2429 struct ifcapreq *ifcr = data; 2430 int reinit = 0; 2431 2432 if (ifcr->ifcr_capenable != ifp->if_capenable) { 2433 ifp->if_capenable = ifcr->ifcr_capenable; 2434 reinit = 1; 2435 } 2436 2437 if ((reinit != 0) && 2438 ((if_getdrvflags(ifp) & IFF_RUNNING) != 0)) { 2439 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2440 ena_down(adapter); 2441 rc = ena_up(adapter); 2442 rw_exit(&adapter->ioctl_sx); 2443 } 2444 } 2445 2446 break; 2447 default: 2448 rc = ether_ioctl(ifp, command, data); 2449 break; 2450 } 2451 2452 return (rc); 2453 } 2454 2455 static int 2456 ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *feat) 2457 { 2458 int caps = 0; 2459 2460 if ((feat->offload.tx & 2461 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2462 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK | 2463 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)) != 0) 2464 caps |= IFCAP_CSUM_IPv4_Tx; 2465 2466 if ((feat->offload.tx & 2467 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK | 2468 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)) != 0) 2469 caps |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 2470 2471 if ((feat->offload.tx & 2472 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0) 2473 caps |= IFCAP_TSOv4; 2474 2475 if ((feat->offload.tx & 2476 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) != 0) 2477 caps |= IFCAP_TSOv6; 2478 2479 if ((feat->offload.rx_supported & 2480 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK | 2481 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)) != 0) 2482 caps |= IFCAP_CSUM_IPv4_Rx; 2483 2484 if ((feat->offload.rx_supported & 2485 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) != 0) 2486 caps |= IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 2487 2488 caps |= IFCAP_LRO; 2489 2490 return (caps); 2491 } 2492 2493 static void 2494 ena_update_host_info(struct ena_admin_host_info *host_info, struct ifnet *ifp) 2495 { 2496 2497 host_info->supported_network_features[0] = 2498 (uint32_t)if_getcapabilities(ifp); 2499 } 2500 2501 static void 2502 ena_update_hwassist(struct ena_adapter *adapter) 2503 { 2504 struct ifnet *ifp = adapter->ifp; 2505 uint32_t feat = adapter->tx_offload_cap; 2506 int cap = if_getcapenable(ifp); 2507 int flags = 0; 2508 2509 if_clearhwassist(ifp); 2510 2511 if ((cap & (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2512 != 0) { 2513 if ((feat & 2514 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) != 0) 2515 flags |= M_CSUM_IPv4; 2516 if ((feat & 2517 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2518 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)) != 0) 2519 flags |= M_CSUM_TCPv4 | M_CSUM_UDPv4; 2520 } 2521 2522 if ((cap & IFCAP_CSUM_TCPv6_Tx) != 0) 2523 flags |= M_CSUM_TCPv6; 2524 2525 if ((cap & IFCAP_CSUM_UDPv6_Tx) != 0) 2526 flags |= M_CSUM_UDPv6; 2527 2528 if ((cap & IFCAP_TSOv4) != 0) 2529 flags |= M_CSUM_TSOv4; 2530 2531 if ((cap & IFCAP_TSOv6) != 0) 2532 flags |= M_CSUM_TSOv6; 2533 2534 if_sethwassistbits(ifp, flags, 0); 2535 } 2536 2537 static int 2538 ena_setup_ifnet(device_t pdev, struct ena_adapter *adapter, 2539 struct ena_com_dev_get_features_ctx *feat) 2540 { 2541 struct ifnet *ifp; 2542 int caps = 0; 2543 2544 ifp = adapter->ifp = &adapter->sc_ec.ec_if; 2545 if (unlikely(ifp == NULL)) { 2546 ena_trace(ENA_ALERT, "can not allocate ifnet structure\n"); 2547 return (ENXIO); 2548 } 2549 if_initname(ifp, "ena", device_unit(pdev)); 2550 if_setdev(ifp, pdev); 2551 if_setsoftc(ifp, adapter); 2552 2553 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2554 if_setinitfn(ifp, ena_init); 2555 if_settransmitfn(ifp, ena_mq_start); 2556 #if 0 2557 if_setqflushfn(ifp, ena_qflush); 2558 #endif 2559 if_setioctlfn(ifp, ena_ioctl); 2560 #if 0 2561 if_setgetcounterfn(ifp, ena_get_counter); 2562 #endif 2563 2564 if_setsendqlen(ifp, adapter->tx_ring_size); 2565 if_setsendqready(ifp); 2566 if_setmtu(ifp, ETHERMTU); 2567 if_setbaudrate(ifp, 0); 2568 /* Zeroize capabilities... */ 2569 if_setcapabilities(ifp, 0); 2570 if_setcapenable(ifp, 0); 2571 /* check hardware support */ 2572 caps = ena_get_dev_offloads(feat); 2573 /* ... and set them */ 2574 if_setcapabilitiesbit(ifp, caps, 0); 2575 adapter->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2576 2577 #if 0 2578 /* TSO parameters */ 2579 /* XXX no limits on NetBSD, guarded by virtue of dmamap load failing */ 2580 ifp->if_hw_tsomax = ENA_TSO_MAXSIZE - 2581 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2582 ifp->if_hw_tsomaxsegcount = adapter->max_tx_sgl_size - 1; 2583 ifp->if_hw_tsomaxsegsize = ENA_TSO_MAXSIZE; 2584 #endif 2585 2586 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2587 if_setcapenable(ifp, if_getcapabilities(ifp)); 2588 2589 /* 2590 * Specify the media types supported by this adapter and register 2591 * callbacks to update media and link information 2592 */ 2593 adapter->sc_ec.ec_ifmedia = &adapter->media; 2594 ifmedia_init(&adapter->media, IFM_IMASK, 2595 ena_media_change, ena_media_status); 2596 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2597 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2598 2599 if_attach(ifp); 2600 if_deferred_start_init(ifp, NULL); 2601 2602 ether_ifattach(ifp, adapter->mac_addr); 2603 2604 return (0); 2605 } 2606 2607 static void 2608 ena_down(struct ena_adapter *adapter) 2609 { 2610 int rc; 2611 2612 if (adapter->up) { 2613 device_printf(adapter->pdev, "device is going DOWN\n"); 2614 2615 callout_halt(&adapter->timer_service, &adapter->global_mtx); 2616 2617 adapter->up = false; 2618 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, 2619 IFF_RUNNING); 2620 2621 ena_free_io_irq(adapter); 2622 2623 if (adapter->trigger_reset) { 2624 rc = ena_com_dev_reset(adapter->ena_dev, 2625 adapter->reset_reason); 2626 if (unlikely(rc != 0)) 2627 device_printf(adapter->pdev, 2628 "Device reset failed\n"); 2629 } 2630 2631 ena_destroy_all_io_queues(adapter); 2632 2633 ena_free_all_tx_bufs(adapter); 2634 ena_free_all_rx_bufs(adapter); 2635 ena_free_all_tx_resources(adapter); 2636 ena_free_all_rx_resources(adapter); 2637 2638 counter_u64_add(adapter->dev_stats.interface_down, 1); 2639 } 2640 } 2641 2642 static void 2643 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf) 2644 { 2645 struct ena_com_tx_meta *ena_meta; 2646 struct ether_vlan_header *eh; 2647 u32 mss; 2648 bool offload; 2649 uint16_t etype; 2650 int ehdrlen; 2651 struct ip *ip; 2652 int iphlen; 2653 struct tcphdr *th; 2654 2655 offload = false; 2656 ena_meta = &ena_tx_ctx->ena_meta; 2657 2658 #if 0 2659 u32 mss = mbuf->m_pkthdr.tso_segsz; 2660 2661 if (mss != 0) 2662 offload = true; 2663 #else 2664 mss = mbuf->m_pkthdr.len; /* XXX don't have tso_segsz */ 2665 #endif 2666 2667 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) 2668 offload = true; 2669 2670 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 2671 offload = true; 2672 2673 if (!offload) { 2674 ena_tx_ctx->meta_valid = 0; 2675 return; 2676 } 2677 2678 /* Determine where frame payload starts. */ 2679 eh = mtod(mbuf, struct ether_vlan_header *); 2680 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2681 etype = ntohs(eh->evl_proto); 2682 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2683 } else { 2684 etype = htons(eh->evl_encap_proto); 2685 ehdrlen = ETHER_HDR_LEN; 2686 } 2687 2688 ip = (struct ip *)(mbuf->m_data + ehdrlen); 2689 iphlen = ip->ip_hl << 2; 2690 th = (struct tcphdr *)((vaddr_t)ip + iphlen); 2691 2692 if ((mbuf->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 2693 ena_tx_ctx->l3_csum_enable = 1; 2694 } 2695 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 2696 ena_tx_ctx->tso_enable = 1; 2697 ena_meta->l4_hdr_len = (th->th_off); 2698 } 2699 2700 switch (etype) { 2701 case ETHERTYPE_IP: 2702 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 2703 if ((ip->ip_off & htons(IP_DF)) != 0) 2704 ena_tx_ctx->df = 1; 2705 break; 2706 case ETHERTYPE_IPV6: 2707 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 2708 2709 default: 2710 break; 2711 } 2712 2713 if (ip->ip_p == IPPROTO_TCP) { 2714 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 2715 if ((mbuf->m_pkthdr.csum_flags & 2716 (M_CSUM_TCPv4 | M_CSUM_TCPv6)) != 0) 2717 ena_tx_ctx->l4_csum_enable = 1; 2718 else 2719 ena_tx_ctx->l4_csum_enable = 0; 2720 } else if (ip->ip_p == IPPROTO_UDP) { 2721 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 2722 if ((mbuf->m_pkthdr.csum_flags & 2723 (M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2724 ena_tx_ctx->l4_csum_enable = 1; 2725 else 2726 ena_tx_ctx->l4_csum_enable = 0; 2727 } else { 2728 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 2729 ena_tx_ctx->l4_csum_enable = 0; 2730 } 2731 2732 ena_meta->mss = mss; 2733 ena_meta->l3_hdr_len = iphlen; 2734 ena_meta->l3_hdr_offset = ehdrlen; 2735 ena_tx_ctx->meta_valid = 1; 2736 } 2737 2738 static int 2739 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2740 { 2741 struct ena_adapter *adapter; 2742 struct mbuf *collapsed_mbuf; 2743 int num_frags; 2744 2745 adapter = tx_ring->adapter; 2746 num_frags = ena_mbuf_count(*mbuf); 2747 2748 /* One segment must be reserved for configuration descriptor. */ 2749 if (num_frags < adapter->max_tx_sgl_size) 2750 return (0); 2751 counter_u64_add(tx_ring->tx_stats.collapse, 1); 2752 2753 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 2754 adapter->max_tx_sgl_size - 1); 2755 if (unlikely(collapsed_mbuf == NULL)) { 2756 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 2757 return (ENOMEM); 2758 } 2759 2760 /* If mbuf was collapsed succesfully, original mbuf is released. */ 2761 *mbuf = collapsed_mbuf; 2762 2763 return (0); 2764 } 2765 2766 static int 2767 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2768 { 2769 struct ena_adapter *adapter; 2770 struct ena_tx_buffer *tx_info; 2771 struct ena_com_tx_ctx ena_tx_ctx; 2772 struct ena_com_dev *ena_dev; 2773 struct ena_com_buf *ena_buf; 2774 struct ena_com_io_sq* io_sq; 2775 void *push_hdr; 2776 uint16_t next_to_use; 2777 uint16_t req_id; 2778 uint16_t ena_qid; 2779 uint32_t header_len; 2780 int i, rc; 2781 int nb_hw_desc; 2782 2783 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2784 adapter = tx_ring->que->adapter; 2785 ena_dev = adapter->ena_dev; 2786 io_sq = &ena_dev->io_sq_queues[ena_qid]; 2787 2788 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 2789 if (unlikely(rc != 0)) { 2790 ena_trace(ENA_WARNING, 2791 "Failed to collapse mbuf! err: %d", rc); 2792 return (rc); 2793 } 2794 2795 next_to_use = tx_ring->next_to_use; 2796 req_id = tx_ring->free_tx_ids[next_to_use]; 2797 tx_info = &tx_ring->tx_buffer_info[req_id]; 2798 2799 tx_info->mbuf = *mbuf; 2800 tx_info->num_of_bufs = 0; 2801 2802 ena_buf = tx_info->bufs; 2803 2804 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes", (*mbuf)->m_pkthdr.len); 2805 2806 /* 2807 * header_len is just a hint for the device. Because FreeBSD is not 2808 * giving us information about packet header length and it is not 2809 * guaranteed that all packet headers will be in the 1st mbuf, setting 2810 * header_len to 0 is making the device ignore this value and resolve 2811 * header on it's own. 2812 */ 2813 header_len = 0; 2814 push_hdr = NULL; 2815 2816 rc = bus_dmamap_load_mbuf(adapter->sc_dmat, tx_info->map, 2817 *mbuf, BUS_DMA_NOWAIT); 2818 2819 if (unlikely((rc != 0) || (tx_info->map->dm_nsegs == 0))) { 2820 ena_trace(ENA_WARNING, 2821 "dmamap load failed! err: %d nsegs: %d", rc, 2822 tx_info->map->dm_nsegs); 2823 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 2824 tx_info->mbuf = NULL; 2825 if (rc == ENOMEM) 2826 return (ENA_COM_NO_MEM); 2827 else 2828 return (ENA_COM_INVAL); 2829 } 2830 2831 for (i = 0; i < tx_info->map->dm_nsegs; i++) { 2832 ena_buf->len = tx_info->map->dm_segs[i].ds_len; 2833 ena_buf->paddr = tx_info->map->dm_segs[i].ds_addr; 2834 ena_buf++; 2835 } 2836 tx_info->num_of_bufs = tx_info->map->dm_nsegs; 2837 2838 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2839 ena_tx_ctx.ena_bufs = tx_info->bufs; 2840 ena_tx_ctx.push_header = push_hdr; 2841 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2842 ena_tx_ctx.req_id = req_id; 2843 ena_tx_ctx.header_len = header_len; 2844 2845 /* Set flags and meta data */ 2846 ena_tx_csum(&ena_tx_ctx, *mbuf); 2847 /* Prepare the packet's descriptors and send them to device */ 2848 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 2849 if (unlikely(rc != 0)) { 2850 device_printf(adapter->pdev, "failed to prepare tx bufs\n"); 2851 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 2852 goto dma_error; 2853 } 2854 2855 counter_enter(); 2856 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 2857 counter_u64_add_protected(tx_ring->tx_stats.bytes, 2858 (*mbuf)->m_pkthdr.len); 2859 2860 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 2861 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 2862 (*mbuf)->m_pkthdr.len); 2863 counter_exit(); 2864 2865 tx_info->tx_descs = nb_hw_desc; 2866 getbinuptime(&tx_info->timestamp); 2867 tx_info->print_once = true; 2868 2869 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2870 tx_ring->ring_size); 2871 2872 bus_dmamap_sync(adapter->sc_dmat, tx_info->map, 0, 2873 tx_info->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2874 2875 return (0); 2876 2877 dma_error: 2878 tx_info->mbuf = NULL; 2879 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 2880 2881 return (rc); 2882 } 2883 2884 static void 2885 ena_start_xmit(struct ena_ring *tx_ring) 2886 { 2887 struct mbuf *mbuf; 2888 struct ena_adapter *adapter = tx_ring->adapter; 2889 struct ena_com_io_sq* io_sq; 2890 int ena_qid; 2891 int acum_pkts = 0; 2892 int ret = 0; 2893 2894 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2895 return; 2896 2897 if (unlikely(!adapter->link_status)) 2898 return; 2899 2900 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2901 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 2902 2903 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 2904 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 2905 " header csum flags %#jx", 2906 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 2907 2908 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 2909 ENA_TX_CLEANUP_THRESHOLD))) 2910 ena_tx_cleanup(tx_ring); 2911 2912 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 2913 if (ret == ENA_COM_NO_MEM) { 2914 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2915 } else if (ret == ENA_COM_NO_SPACE) { 2916 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2917 } else { 2918 m_freem(mbuf); 2919 drbr_advance(adapter->ifp, tx_ring->br); 2920 } 2921 2922 break; 2923 } 2924 2925 drbr_advance(adapter->ifp, tx_ring->br); 2926 2927 if (unlikely((if_getdrvflags(adapter->ifp) & 2928 IFF_RUNNING) == 0)) 2929 return; 2930 2931 acum_pkts++; 2932 2933 /* 2934 * If there's a BPF listener, bounce a copy of this frame 2935 * to him. 2936 */ 2937 bpf_mtap(adapter->ifp, mbuf, BPF_D_OUT); 2938 2939 if (unlikely(acum_pkts == DB_THRESHOLD)) { 2940 acum_pkts = 0; 2941 wmb(); 2942 /* Trigger the dma engine */ 2943 ena_com_write_sq_doorbell(io_sq); 2944 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2945 } 2946 2947 } 2948 2949 if (likely(acum_pkts != 0)) { 2950 wmb(); 2951 /* Trigger the dma engine */ 2952 ena_com_write_sq_doorbell(io_sq); 2953 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2954 } 2955 2956 if (!ena_com_sq_have_enough_space(io_sq, ENA_TX_CLEANUP_THRESHOLD)) 2957 ena_tx_cleanup(tx_ring); 2958 } 2959 2960 static void 2961 ena_deferred_mq_start(struct work *wk, void *arg) 2962 { 2963 struct ena_ring *tx_ring = (struct ena_ring *)arg; 2964 struct ifnet *ifp = tx_ring->adapter->ifp; 2965 2966 atomic_swap_uint(&tx_ring->task_pending, 0); 2967 2968 while (!drbr_empty(ifp, tx_ring->br) && 2969 (if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2970 ENA_RING_MTX_LOCK(tx_ring); 2971 ena_start_xmit(tx_ring); 2972 ENA_RING_MTX_UNLOCK(tx_ring); 2973 } 2974 } 2975 2976 static int 2977 ena_mq_start(struct ifnet *ifp, struct mbuf *m) 2978 { 2979 struct ena_adapter *adapter = ifp->if_softc; 2980 struct ena_ring *tx_ring; 2981 int ret, is_drbr_empty; 2982 uint32_t i; 2983 2984 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2985 return (ENODEV); 2986 2987 /* Which queue to use */ 2988 /* 2989 * If everything is setup correctly, it should be the 2990 * same bucket that the current CPU we're on is. 2991 * It should improve performance. 2992 */ 2993 #if 0 2994 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 2995 #ifdef RSS 2996 if (rss_hash2bucket(m->m_pkthdr.flowid, 2997 M_HASHTYPE_GET(m), &i) == 0) { 2998 i = i % adapter->num_queues; 2999 3000 } else 3001 #endif 3002 { 3003 i = m->m_pkthdr.flowid % adapter->num_queues; 3004 } 3005 } else { 3006 #endif 3007 i = cpu_index(curcpu()) % adapter->num_queues; 3008 #if 0 3009 } 3010 #endif 3011 tx_ring = &adapter->tx_ring[i]; 3012 3013 /* Check if drbr is empty before putting packet */ 3014 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 3015 ret = drbr_enqueue(ifp, tx_ring->br, m); 3016 if (unlikely(ret != 0)) { 3017 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 3018 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 3019 curcpu()); 3020 return (ret); 3021 } 3022 3023 if ((is_drbr_empty != 0) && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 3024 ena_start_xmit(tx_ring); 3025 ENA_RING_MTX_UNLOCK(tx_ring); 3026 } else { 3027 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 3028 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 3029 curcpu()); 3030 } 3031 3032 return (0); 3033 } 3034 3035 #if 0 3036 static void 3037 ena_qflush(struct ifnet *ifp) 3038 { 3039 struct ena_adapter *adapter = ifp->if_softc; 3040 struct ena_ring *tx_ring = adapter->tx_ring; 3041 int i; 3042 3043 for(i = 0; i < adapter->num_queues; ++i, ++tx_ring) 3044 if (!drbr_empty(ifp, tx_ring->br)) { 3045 ENA_RING_MTX_LOCK(tx_ring); 3046 drbr_flush(ifp, tx_ring->br); 3047 ENA_RING_MTX_UNLOCK(tx_ring); 3048 } 3049 3050 if_qflush(ifp); 3051 } 3052 #endif 3053 3054 static int 3055 ena_calc_io_queue_num(struct pci_attach_args *pa, 3056 struct ena_adapter *adapter, 3057 struct ena_com_dev_get_features_ctx *get_feat_ctx) 3058 { 3059 int io_sq_num, io_cq_num, io_queue_num; 3060 3061 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 3062 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 3063 3064 io_queue_num = min_t(int, mp_ncpus, ENA_MAX_NUM_IO_QUEUES); 3065 io_queue_num = min_t(int, io_queue_num, io_sq_num); 3066 io_queue_num = min_t(int, io_queue_num, io_cq_num); 3067 /* 1 IRQ for for mgmnt and 1 IRQ for each TX/RX pair */ 3068 io_queue_num = min_t(int, io_queue_num, 3069 pci_msix_count(pa->pa_pc, pa->pa_tag) - 1); 3070 #ifdef RSS 3071 io_queue_num = min_t(int, io_queue_num, rss_getnumbuckets()); 3072 #endif 3073 3074 return (io_queue_num); 3075 } 3076 3077 static int 3078 ena_calc_queue_size(struct ena_adapter *adapter, uint16_t *max_tx_sgl_size, 3079 uint16_t *max_rx_sgl_size, struct ena_com_dev_get_features_ctx *feat) 3080 { 3081 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 3082 uint32_t v; 3083 uint32_t q; 3084 3085 queue_size = min_t(uint32_t, queue_size, 3086 feat->max_queues.max_cq_depth); 3087 queue_size = min_t(uint32_t, queue_size, 3088 feat->max_queues.max_sq_depth); 3089 3090 /* round down to the nearest power of 2 */ 3091 v = queue_size; 3092 while (v != 0) { 3093 if (powerof2(queue_size) != 0) 3094 break; 3095 v /= 2; 3096 q = rounddown2(queue_size, v); 3097 if (q != 0) { 3098 queue_size = q; 3099 break; 3100 } 3101 } 3102 3103 if (unlikely(queue_size == 0)) { 3104 device_printf(adapter->pdev, "Invalid queue size\n"); 3105 return (ENA_COM_FAULT); 3106 } 3107 3108 *max_tx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3109 feat->max_queues.max_packet_tx_descs); 3110 *max_rx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3111 feat->max_queues.max_packet_rx_descs); 3112 3113 return (queue_size); 3114 } 3115 3116 #if 0 3117 static int 3118 ena_rss_init_default(struct ena_adapter *adapter) 3119 { 3120 struct ena_com_dev *ena_dev = adapter->ena_dev; 3121 device_t dev = adapter->pdev; 3122 int qid, rc, i; 3123 3124 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3125 if (unlikely(rc != 0)) { 3126 device_printf(dev, "Cannot init indirect table\n"); 3127 return (rc); 3128 } 3129 3130 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3131 #ifdef RSS 3132 qid = rss_get_indirection_to_bucket(i); 3133 qid = qid % adapter->num_queues; 3134 #else 3135 qid = i % adapter->num_queues; 3136 #endif 3137 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3138 ENA_IO_RXQ_IDX(qid)); 3139 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3140 device_printf(dev, "Cannot fill indirect table\n"); 3141 goto err_rss_destroy; 3142 } 3143 } 3144 3145 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3146 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3147 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3148 device_printf(dev, "Cannot fill hash function\n"); 3149 goto err_rss_destroy; 3150 } 3151 3152 rc = ena_com_set_default_hash_ctrl(ena_dev); 3153 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3154 device_printf(dev, "Cannot fill hash control\n"); 3155 goto err_rss_destroy; 3156 } 3157 3158 return (0); 3159 3160 err_rss_destroy: 3161 ena_com_rss_destroy(ena_dev); 3162 return (rc); 3163 } 3164 3165 static void 3166 ena_rss_init_default_deferred(void *arg) 3167 { 3168 struct ena_adapter *adapter; 3169 devclass_t dc; 3170 int max; 3171 int rc; 3172 3173 dc = devclass_find("ena"); 3174 if (unlikely(dc == NULL)) { 3175 ena_trace(ENA_ALERT, "No devclass ena\n"); 3176 return; 3177 } 3178 3179 max = devclass_get_maxunit(dc); 3180 while (max-- >= 0) { 3181 adapter = devclass_get_softc(dc, max); 3182 if (adapter != NULL) { 3183 rc = ena_rss_init_default(adapter); 3184 adapter->rss_support = true; 3185 if (unlikely(rc != 0)) { 3186 device_printf(adapter->pdev, 3187 "WARNING: RSS was not properly initialized," 3188 " it will affect bandwidth\n"); 3189 adapter->rss_support = false; 3190 } 3191 } 3192 } 3193 } 3194 SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL); 3195 #endif 3196 3197 static void 3198 ena_config_host_info(struct ena_com_dev *ena_dev) 3199 { 3200 struct ena_admin_host_info *host_info; 3201 int rc; 3202 3203 /* Allocate only the host info */ 3204 rc = ena_com_allocate_host_info(ena_dev); 3205 if (unlikely(rc != 0)) { 3206 ena_trace(ENA_ALERT, "Cannot allocate host info\n"); 3207 return; 3208 } 3209 3210 host_info = ena_dev->host_attr.host_info; 3211 3212 host_info->os_type = ENA_ADMIN_OS_FREEBSD; 3213 host_info->kernel_ver = osreldate; 3214 3215 snprintf(host_info->kernel_ver_str, sizeof(host_info->kernel_ver_str), 3216 "%d", osreldate); 3217 host_info->os_dist = 0; 3218 strncpy(host_info->os_dist_str, osrelease, 3219 sizeof(host_info->os_dist_str) - 1); 3220 3221 host_info->driver_version = 3222 (DRV_MODULE_VER_MAJOR) | 3223 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 3224 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 3225 3226 rc = ena_com_set_host_attributes(ena_dev); 3227 if (unlikely(rc != 0)) { 3228 if (rc == EOPNOTSUPP) 3229 ena_trace(ENA_WARNING, "Cannot set host attributes\n"); 3230 else 3231 ena_trace(ENA_ALERT, "Cannot set host attributes\n"); 3232 3233 goto err; 3234 } 3235 3236 return; 3237 3238 err: 3239 ena_com_delete_host_info(ena_dev); 3240 } 3241 3242 static int 3243 ena_device_init(struct ena_adapter *adapter, device_t pdev, 3244 struct ena_com_dev_get_features_ctx *get_feat_ctx, int *wd_active) 3245 { 3246 struct ena_com_dev* ena_dev = adapter->ena_dev; 3247 bool readless_supported; 3248 uint32_t aenq_groups; 3249 int dma_width; 3250 int rc; 3251 3252 rc = ena_com_mmio_reg_read_request_init(ena_dev); 3253 if (unlikely(rc != 0)) { 3254 device_printf(pdev, "failed to init mmio read less\n"); 3255 return (rc); 3256 } 3257 3258 /* 3259 * The PCIe configuration space revision id indicate if mmio reg 3260 * read is disabled 3261 */ 3262 const int rev = PCI_REVISION(adapter->sc_pa.pa_class); 3263 readless_supported = ((rev & ENA_MMIO_DISABLE_REG_READ) == 0); 3264 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 3265 3266 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 3267 if (unlikely(rc != 0)) { 3268 device_printf(pdev, "Can not reset device\n"); 3269 goto err_mmio_read_less; 3270 } 3271 3272 rc = ena_com_validate_version(ena_dev); 3273 if (unlikely(rc != 0)) { 3274 device_printf(pdev, "device version is too low\n"); 3275 goto err_mmio_read_less; 3276 } 3277 3278 dma_width = ena_com_get_dma_width(ena_dev); 3279 if (unlikely(dma_width < 0)) { 3280 device_printf(pdev, "Invalid dma width value %d", dma_width); 3281 rc = dma_width; 3282 goto err_mmio_read_less; 3283 } 3284 adapter->dma_width = dma_width; 3285 3286 /* ENA admin level init */ 3287 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 3288 if (unlikely(rc != 0)) { 3289 device_printf(pdev, 3290 "Can not initialize ena admin queue with device\n"); 3291 goto err_mmio_read_less; 3292 } 3293 3294 /* 3295 * To enable the msix interrupts the driver needs to know the number 3296 * of queues. So the driver uses polling mode to retrieve this 3297 * information 3298 */ 3299 ena_com_set_admin_polling_mode(ena_dev, true); 3300 3301 ena_config_host_info(ena_dev); 3302 3303 /* Get Device Attributes */ 3304 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 3305 if (unlikely(rc != 0)) { 3306 device_printf(pdev, 3307 "Cannot get attribute for ena device rc: %d\n", rc); 3308 goto err_admin_init; 3309 } 3310 3311 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT(ENA_ADMIN_KEEP_ALIVE); 3312 3313 aenq_groups &= get_feat_ctx->aenq.supported_groups; 3314 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 3315 if (unlikely(rc != 0)) { 3316 device_printf(pdev, "Cannot configure aenq groups rc: %d\n", rc); 3317 goto err_admin_init; 3318 } 3319 3320 *wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 3321 3322 return (0); 3323 3324 err_admin_init: 3325 ena_com_delete_host_info(ena_dev); 3326 ena_com_admin_destroy(ena_dev); 3327 err_mmio_read_less: 3328 ena_com_mmio_reg_read_request_destroy(ena_dev); 3329 3330 return (rc); 3331 } 3332 3333 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 3334 int io_vectors) 3335 { 3336 struct ena_com_dev *ena_dev = adapter->ena_dev; 3337 int rc; 3338 3339 rc = ena_enable_msix(adapter); 3340 if (unlikely(rc != 0)) { 3341 device_printf(adapter->pdev, "Error with MSI-X enablement\n"); 3342 return (rc); 3343 } 3344 3345 rc = ena_request_mgmnt_irq(adapter); 3346 if (unlikely(rc != 0)) { 3347 device_printf(adapter->pdev, "Cannot setup mgmnt queue intr\n"); 3348 goto err_disable_msix; 3349 } 3350 3351 ena_com_set_admin_polling_mode(ena_dev, false); 3352 3353 ena_com_admin_aenq_enable(ena_dev); 3354 3355 return (0); 3356 3357 err_disable_msix: 3358 ena_disable_msix(adapter); 3359 3360 return (rc); 3361 } 3362 3363 /* Function called on ENA_ADMIN_KEEP_ALIVE event */ 3364 static void ena_keep_alive_wd(void *adapter_data, 3365 struct ena_admin_aenq_entry *aenq_e) 3366 { 3367 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3368 struct ena_admin_aenq_keep_alive_desc *desc; 3369 sbintime_t stime; 3370 uint64_t rx_drops; 3371 3372 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3373 3374 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3375 counter_u64_zero(adapter->hw_stats.rx_drops); 3376 counter_u64_add(adapter->hw_stats.rx_drops, rx_drops); 3377 3378 stime = getsbinuptime(); 3379 (void) atomic_swap_64(&adapter->keep_alive_timestamp, stime); 3380 } 3381 3382 /* Check for keep alive expiration */ 3383 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 3384 { 3385 sbintime_t timestamp, time; 3386 3387 if (adapter->wd_active == 0) 3388 return; 3389 3390 if (likely(adapter->keep_alive_timeout == 0)) 3391 return; 3392 3393 /* FreeBSD uses atomic_load_acq_64() in place of the membar + read */ 3394 membar_sync(); 3395 timestamp = adapter->keep_alive_timestamp; 3396 3397 time = getsbinuptime() - timestamp; 3398 if (unlikely(time > adapter->keep_alive_timeout)) { 3399 device_printf(adapter->pdev, 3400 "Keep alive watchdog timeout.\n"); 3401 counter_u64_add(adapter->dev_stats.wd_expired, 1); 3402 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 3403 adapter->trigger_reset = true; 3404 } 3405 } 3406 3407 /* Check if admin queue is enabled */ 3408 static void check_for_admin_com_state(struct ena_adapter *adapter) 3409 { 3410 if (unlikely(ena_com_get_admin_running_state(adapter->ena_dev) == 3411 false)) { 3412 device_printf(adapter->pdev, 3413 "ENA admin queue is not in running state!\n"); 3414 counter_u64_add(adapter->dev_stats.admin_q_pause, 1); 3415 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 3416 adapter->trigger_reset = true; 3417 } 3418 } 3419 3420 static int 3421 check_missing_comp_in_queue(struct ena_adapter *adapter, 3422 struct ena_ring *tx_ring) 3423 { 3424 struct bintime curtime, time; 3425 struct ena_tx_buffer *tx_buf; 3426 uint32_t missed_tx = 0; 3427 int i; 3428 3429 getbinuptime(&curtime); 3430 3431 for (i = 0; i < tx_ring->ring_size; i++) { 3432 tx_buf = &tx_ring->tx_buffer_info[i]; 3433 3434 if (bintime_isset(&tx_buf->timestamp) == 0) 3435 continue; 3436 3437 time = curtime; 3438 bintime_sub(&time, &tx_buf->timestamp); 3439 3440 /* Check again if packet is still waiting */ 3441 if (unlikely(bttosbt(time) > adapter->missing_tx_timeout)) { 3442 3443 if (!tx_buf->print_once) 3444 ena_trace(ENA_WARNING, "Found a Tx that wasn't " 3445 "completed on time, qid %d, index %d.\n", 3446 tx_ring->qid, i); 3447 3448 tx_buf->print_once = true; 3449 missed_tx++; 3450 counter_u64_add(tx_ring->tx_stats.missing_tx_comp, 1); 3451 3452 if (unlikely(missed_tx > 3453 adapter->missing_tx_threshold)) { 3454 device_printf(adapter->pdev, 3455 "The number of lost tx completion " 3456 "is above the threshold (%d > %d). " 3457 "Reset the device\n", 3458 missed_tx, adapter->missing_tx_threshold); 3459 adapter->reset_reason = 3460 ENA_REGS_RESET_MISS_TX_CMPL; 3461 adapter->trigger_reset = true; 3462 return (EIO); 3463 } 3464 } 3465 } 3466 3467 return (0); 3468 } 3469 3470 /* 3471 * Check for TX which were not completed on time. 3472 * Timeout is defined by "missing_tx_timeout". 3473 * Reset will be performed if number of incompleted 3474 * transactions exceeds "missing_tx_threshold". 3475 */ 3476 static void 3477 check_for_missing_tx_completions(struct ena_adapter *adapter) 3478 { 3479 struct ena_ring *tx_ring; 3480 int i, budget, rc; 3481 3482 /* Make sure the driver doesn't turn the device in other process */ 3483 rmb(); 3484 3485 if (!adapter->up) 3486 return; 3487 3488 if (adapter->trigger_reset) 3489 return; 3490 3491 if (adapter->missing_tx_timeout == 0) 3492 return; 3493 3494 budget = adapter->missing_tx_max_queues; 3495 3496 for (i = adapter->next_monitored_tx_qid; i < adapter->num_queues; i++) { 3497 tx_ring = &adapter->tx_ring[i]; 3498 3499 rc = check_missing_comp_in_queue(adapter, tx_ring); 3500 if (unlikely(rc != 0)) 3501 return; 3502 3503 budget--; 3504 if (budget == 0) { 3505 i++; 3506 break; 3507 } 3508 } 3509 3510 adapter->next_monitored_tx_qid = i % adapter->num_queues; 3511 } 3512 3513 /* trigger deferred rx cleanup after 2 consecutive detections */ 3514 #define EMPTY_RX_REFILL 2 3515 /* For the rare case where the device runs out of Rx descriptors and the 3516 * msix handler failed to refill new Rx descriptors (due to a lack of memory 3517 * for example). 3518 * This case will lead to a deadlock: 3519 * The device won't send interrupts since all the new Rx packets will be dropped 3520 * The msix handler won't allocate new Rx descriptors so the device won't be 3521 * able to send new packets. 3522 * 3523 * When such a situation is detected - execute rx cleanup task in another thread 3524 */ 3525 static void 3526 check_for_empty_rx_ring(struct ena_adapter *adapter) 3527 { 3528 struct ena_ring *rx_ring; 3529 int i, refill_required; 3530 3531 if (!adapter->up) 3532 return; 3533 3534 if (adapter->trigger_reset) 3535 return; 3536 3537 for (i = 0; i < adapter->num_queues; i++) { 3538 rx_ring = &adapter->rx_ring[i]; 3539 3540 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 3541 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 3542 rx_ring->empty_rx_queue++; 3543 3544 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 3545 counter_u64_add(rx_ring->rx_stats.empty_rx_ring, 3546 1); 3547 3548 device_printf(adapter->pdev, 3549 "trigger refill for ring %d\n", i); 3550 3551 if (atomic_cas_uint(&rx_ring->task_pending, 0, 1) == 0) 3552 workqueue_enqueue(rx_ring->cmpl_tq, 3553 &rx_ring->cmpl_task, curcpu()); 3554 rx_ring->empty_rx_queue = 0; 3555 } 3556 } else { 3557 rx_ring->empty_rx_queue = 0; 3558 } 3559 } 3560 } 3561 3562 static void 3563 ena_timer_service(void *data) 3564 { 3565 struct ena_adapter *adapter = (struct ena_adapter *)data; 3566 struct ena_admin_host_info *host_info = 3567 adapter->ena_dev->host_attr.host_info; 3568 3569 check_for_missing_keep_alive(adapter); 3570 3571 check_for_admin_com_state(adapter); 3572 3573 check_for_missing_tx_completions(adapter); 3574 3575 check_for_empty_rx_ring(adapter); 3576 3577 if (host_info != NULL) 3578 ena_update_host_info(host_info, adapter->ifp); 3579 3580 if (unlikely(adapter->trigger_reset)) { 3581 device_printf(adapter->pdev, "Trigger reset is on\n"); 3582 workqueue_enqueue(adapter->reset_tq, &adapter->reset_task, 3583 curcpu()); 3584 return; 3585 } 3586 3587 /* 3588 * Schedule another timeout one second from now. 3589 */ 3590 callout_schedule(&adapter->timer_service, hz); 3591 } 3592 3593 static void 3594 ena_reset_task(struct work *wk, void *arg) 3595 { 3596 struct ena_com_dev_get_features_ctx get_feat_ctx; 3597 struct ena_adapter *adapter = (struct ena_adapter *)arg; 3598 struct ena_com_dev *ena_dev = adapter->ena_dev; 3599 bool dev_up; 3600 int rc; 3601 3602 if (unlikely(!adapter->trigger_reset)) { 3603 device_printf(adapter->pdev, 3604 "device reset scheduled but trigger_reset is off\n"); 3605 return; 3606 } 3607 3608 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3609 3610 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3611 3612 dev_up = adapter->up; 3613 3614 ena_com_set_admin_running_state(ena_dev, false); 3615 ena_down(adapter); 3616 ena_free_mgmnt_irq(adapter); 3617 ena_disable_msix(adapter); 3618 ena_com_abort_admin_commands(ena_dev); 3619 ena_com_wait_for_abort_completion(ena_dev); 3620 ena_com_admin_destroy(ena_dev); 3621 ena_com_mmio_reg_read_request_destroy(ena_dev); 3622 3623 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3624 adapter->trigger_reset = false; 3625 3626 /* Finished destroy part. Restart the device */ 3627 rc = ena_device_init(adapter, adapter->pdev, &get_feat_ctx, 3628 &adapter->wd_active); 3629 if (unlikely(rc != 0)) { 3630 device_printf(adapter->pdev, 3631 "ENA device init failed! (err: %d)\n", rc); 3632 goto err_dev_free; 3633 } 3634 3635 /* XXX dealloc and realloc MSI-X, probably a waste */ 3636 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 3637 adapter->num_queues); 3638 if (unlikely(rc != 0)) { 3639 device_printf(adapter->pdev, "Enable MSI-X failed\n"); 3640 goto err_com_free; 3641 } 3642 3643 /* If the interface was up before the reset bring it up */ 3644 if (dev_up) { 3645 rc = ena_up(adapter); 3646 if (unlikely(rc != 0)) { 3647 device_printf(adapter->pdev, 3648 "Failed to create I/O queues\n"); 3649 goto err_msix_free; 3650 } 3651 } 3652 3653 callout_reset(&adapter->timer_service, hz, 3654 ena_timer_service, (void *)adapter); 3655 3656 rw_exit(&adapter->ioctl_sx); 3657 3658 return; 3659 3660 err_msix_free: 3661 ena_free_mgmnt_irq(adapter); 3662 ena_disable_msix(adapter); 3663 err_com_free: 3664 ena_com_admin_destroy(ena_dev); 3665 err_dev_free: 3666 device_printf(adapter->pdev, "ENA reset failed!\n"); 3667 adapter->running = false; 3668 rw_exit(&adapter->ioctl_sx); 3669 } 3670 3671 /** 3672 * ena_attach - Device Initialization Routine 3673 * @pdev: device information struct 3674 * 3675 * Returns 0 on success, otherwise on failure. 3676 * 3677 * ena_attach initializes an adapter identified by a device structure. 3678 * The OS initialization, configuring of the adapter private structure, 3679 * and a hardware reset occur. 3680 **/ 3681 static void 3682 ena_attach(device_t parent, device_t self, void *aux) 3683 { 3684 struct pci_attach_args *pa = aux; 3685 struct ena_com_dev_get_features_ctx get_feat_ctx; 3686 static int version_printed; 3687 struct ena_adapter *adapter = device_private(self); 3688 struct ena_com_dev *ena_dev = NULL; 3689 uint16_t tx_sgl_size = 0; 3690 uint16_t rx_sgl_size = 0; 3691 pcireg_t reg; 3692 int io_queue_num; 3693 int queue_size; 3694 int rc; 3695 3696 adapter->pdev = self; 3697 adapter->ifp = &adapter->sc_ec.ec_if; 3698 adapter->sc_pa = *pa; /* used after attach for adapter reset too */ 3699 3700 if (pci_dma64_available(pa)) 3701 adapter->sc_dmat = pa->pa_dmat64; 3702 else 3703 adapter->sc_dmat = pa->pa_dmat; 3704 3705 pci_aprint_devinfo(pa, NULL); 3706 3707 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3708 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) { 3709 reg |= PCI_COMMAND_MASTER_ENABLE; 3710 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 3711 } 3712 3713 mutex_init(&adapter->global_mtx, MUTEX_DEFAULT, IPL_NET); 3714 rw_init(&adapter->ioctl_sx); 3715 3716 /* Set up the timer service */ 3717 adapter->keep_alive_timeout = DEFAULT_KEEP_ALIVE_TO; 3718 adapter->missing_tx_timeout = DEFAULT_TX_CMP_TO; 3719 adapter->missing_tx_max_queues = DEFAULT_TX_MONITORED_QUEUES; 3720 adapter->missing_tx_threshold = DEFAULT_TX_CMP_THRESHOLD; 3721 3722 if (version_printed++ == 0) 3723 device_printf(parent, "%s\n", ena_version); 3724 3725 rc = ena_allocate_pci_resources(pa, adapter); 3726 if (unlikely(rc != 0)) { 3727 device_printf(parent, "PCI resource allocation failed!\n"); 3728 ena_free_pci_resources(adapter); 3729 return; 3730 } 3731 3732 /* Allocate memory for ena_dev structure */ 3733 ena_dev = malloc(sizeof(struct ena_com_dev), M_DEVBUF, 3734 M_WAITOK | M_ZERO); 3735 3736 adapter->ena_dev = ena_dev; 3737 ena_dev->dmadev = self; 3738 ena_dev->bus = malloc(sizeof(struct ena_bus), M_DEVBUF, 3739 M_WAITOK | M_ZERO); 3740 3741 /* Store register resources */ 3742 ((struct ena_bus*)(ena_dev->bus))->reg_bar_t = adapter->sc_btag; 3743 ((struct ena_bus*)(ena_dev->bus))->reg_bar_h = adapter->sc_bhandle; 3744 3745 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3746 3747 /* Device initialization */ 3748 rc = ena_device_init(adapter, self, &get_feat_ctx, &adapter->wd_active); 3749 if (unlikely(rc != 0)) { 3750 device_printf(self, "ENA device init failed! (err: %d)\n", rc); 3751 rc = ENXIO; 3752 goto err_bus_free; 3753 } 3754 3755 adapter->keep_alive_timestamp = getsbinuptime(); 3756 3757 adapter->tx_offload_cap = get_feat_ctx.offload.tx; 3758 3759 /* Set for sure that interface is not up */ 3760 adapter->up = false; 3761 3762 memcpy(adapter->mac_addr, get_feat_ctx.dev_attr.mac_addr, 3763 ETHER_ADDR_LEN); 3764 3765 /* calculate IO queue number to create */ 3766 io_queue_num = ena_calc_io_queue_num(pa, adapter, &get_feat_ctx); 3767 3768 ENA_ASSERT(io_queue_num > 0, "Invalid queue number: %d\n", 3769 io_queue_num); 3770 adapter->num_queues = io_queue_num; 3771 3772 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 3773 3774 /* calculatre ring sizes */ 3775 queue_size = ena_calc_queue_size(adapter,&tx_sgl_size, 3776 &rx_sgl_size, &get_feat_ctx); 3777 if (unlikely((queue_size <= 0) || (io_queue_num <= 0))) { 3778 rc = ENA_COM_FAULT; 3779 goto err_com_free; 3780 } 3781 3782 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3783 3784 adapter->tx_ring_size = queue_size; 3785 adapter->rx_ring_size = queue_size; 3786 3787 adapter->max_tx_sgl_size = tx_sgl_size; 3788 adapter->max_rx_sgl_size = rx_sgl_size; 3789 3790 #if 0 3791 /* set up dma tags for rx and tx buffers */ 3792 rc = ena_setup_tx_dma_tag(adapter); 3793 if (unlikely(rc != 0)) { 3794 device_printf(self, "Failed to create TX DMA tag\n"); 3795 goto err_com_free; 3796 } 3797 3798 rc = ena_setup_rx_dma_tag(adapter); 3799 if (unlikely(rc != 0)) { 3800 device_printf(self, "Failed to create RX DMA tag\n"); 3801 goto err_tx_tag_free; 3802 } 3803 #endif 3804 3805 /* initialize rings basic information */ 3806 device_printf(self, "initalize %d io queues\n", io_queue_num); 3807 ena_init_io_rings(adapter); 3808 3809 /* setup network interface */ 3810 rc = ena_setup_ifnet(self, adapter, &get_feat_ctx); 3811 if (unlikely(rc != 0)) { 3812 device_printf(self, "Error with network interface setup\n"); 3813 goto err_io_free; 3814 } 3815 3816 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3817 if (unlikely(rc != 0)) { 3818 device_printf(self, 3819 "Failed to enable and set the admin interrupts\n"); 3820 goto err_ifp_free; 3821 } 3822 3823 callout_init(&adapter->timer_service, CALLOUT_FLAGS); 3824 3825 /* Initialize reset task queue */ 3826 rc = workqueue_create(&adapter->reset_tq, "ena_reset_enq", 3827 ena_reset_task, adapter, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 3828 if (unlikely(rc != 0)) { 3829 ena_trace(ENA_ALERT, 3830 "Unable to create workqueue for reset task\n"); 3831 goto err_ifp_free; 3832 } 3833 3834 /* Initialize statistics */ 3835 ena_alloc_counters_dev(&adapter->dev_stats, io_queue_num); 3836 ena_alloc_counters_hwstats(&adapter->hw_stats, io_queue_num); 3837 #if 0 3838 ena_sysctl_add_nodes(adapter); 3839 #endif 3840 3841 /* Tell the stack that the interface is not active */ 3842 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, IFF_RUNNING); 3843 3844 adapter->running = true; 3845 return; 3846 3847 err_ifp_free: 3848 if_detach(adapter->ifp); 3849 if_free(adapter->ifp); 3850 err_io_free: 3851 ena_free_all_io_rings_resources(adapter); 3852 #if 0 3853 ena_free_rx_dma_tag(adapter); 3854 err_tx_tag_free: 3855 ena_free_tx_dma_tag(adapter); 3856 #endif 3857 err_com_free: 3858 ena_com_admin_destroy(ena_dev); 3859 ena_com_delete_host_info(ena_dev); 3860 ena_com_mmio_reg_read_request_destroy(ena_dev); 3861 err_bus_free: 3862 free(ena_dev->bus, M_DEVBUF); 3863 free(ena_dev, M_DEVBUF); 3864 ena_free_pci_resources(adapter); 3865 } 3866 3867 /** 3868 * ena_detach - Device Removal Routine 3869 * @pdev: device information struct 3870 * 3871 * ena_detach is called by the device subsystem to alert the driver 3872 * that it should release a PCI device. 3873 **/ 3874 static int 3875 ena_detach(device_t pdev, int flags) 3876 { 3877 struct ena_adapter *adapter = device_private(pdev); 3878 struct ena_com_dev *ena_dev = adapter->ena_dev; 3879 #if 0 3880 int rc; 3881 #endif 3882 3883 /* Make sure VLANS are not using driver */ 3884 if (VLAN_ATTACHED(&adapter->sc_ec)) { 3885 device_printf(adapter->pdev ,"VLAN is in use, detach first\n"); 3886 return (EBUSY); 3887 } 3888 3889 /* Free reset task and callout */ 3890 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3891 callout_destroy(&adapter->timer_service); 3892 workqueue_wait(adapter->reset_tq, &adapter->reset_task); 3893 workqueue_destroy(adapter->reset_tq); 3894 adapter->reset_tq = NULL; 3895 3896 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3897 ena_down(adapter); 3898 rw_exit(&adapter->ioctl_sx); 3899 3900 if (adapter->ifp != NULL) { 3901 ether_ifdetach(adapter->ifp); 3902 if_free(adapter->ifp); 3903 } 3904 3905 ena_free_all_io_rings_resources(adapter); 3906 3907 ena_free_counters((struct evcnt *)&adapter->hw_stats, 3908 sizeof(struct ena_hw_stats)); 3909 ena_free_counters((struct evcnt *)&adapter->dev_stats, 3910 sizeof(struct ena_stats_dev)); 3911 3912 if (likely(adapter->rss_support)) 3913 ena_com_rss_destroy(ena_dev); 3914 3915 #if 0 3916 rc = ena_free_rx_dma_tag(adapter); 3917 if (unlikely(rc != 0)) 3918 device_printf(adapter->pdev, 3919 "Unmapped RX DMA tag associations\n"); 3920 3921 rc = ena_free_tx_dma_tag(adapter); 3922 if (unlikely(rc != 0)) 3923 device_printf(adapter->pdev, 3924 "Unmapped TX DMA tag associations\n"); 3925 #endif 3926 3927 /* Reset the device only if the device is running. */ 3928 if (adapter->running) 3929 ena_com_dev_reset(ena_dev, adapter->reset_reason); 3930 3931 ena_com_delete_host_info(ena_dev); 3932 3933 ena_free_irqs(adapter); 3934 3935 ena_com_abort_admin_commands(ena_dev); 3936 3937 ena_com_wait_for_abort_completion(ena_dev); 3938 3939 ena_com_admin_destroy(ena_dev); 3940 3941 ena_com_mmio_reg_read_request_destroy(ena_dev); 3942 3943 ena_free_pci_resources(adapter); 3944 3945 mutex_destroy(&adapter->global_mtx); 3946 rw_destroy(&adapter->ioctl_sx); 3947 3948 if (ena_dev->bus != NULL) 3949 free(ena_dev->bus, M_DEVBUF); 3950 3951 if (ena_dev != NULL) 3952 free(ena_dev, M_DEVBUF); 3953 3954 return 0; 3955 } 3956 3957 /****************************************************************************** 3958 ******************************** AENQ Handlers ******************************* 3959 *****************************************************************************/ 3960 /** 3961 * ena_update_on_link_change: 3962 * Notify the network interface about the change in link status 3963 **/ 3964 static void 3965 ena_update_on_link_change(void *adapter_data, 3966 struct ena_admin_aenq_entry *aenq_e) 3967 { 3968 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3969 struct ena_admin_aenq_link_change_desc *aenq_desc; 3970 int status; 3971 struct ifnet *ifp; 3972 3973 aenq_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3974 ifp = adapter->ifp; 3975 status = aenq_desc->flags & 3976 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3977 3978 if (status != 0) { 3979 device_printf(adapter->pdev, "link is UP\n"); 3980 if_link_state_change(ifp, LINK_STATE_UP); 3981 } else if (status == 0) { 3982 device_printf(adapter->pdev, "link is DOWN\n"); 3983 if_link_state_change(ifp, LINK_STATE_DOWN); 3984 } else { 3985 device_printf(adapter->pdev, "invalid value recvd\n"); 3986 BUG(); 3987 } 3988 3989 adapter->link_status = status; 3990 } 3991 3992 /** 3993 * This handler will called for unknown event group or unimplemented handlers 3994 **/ 3995 static void 3996 unimplemented_aenq_handler(void *data, 3997 struct ena_admin_aenq_entry *aenq_e) 3998 { 3999 return; 4000 } 4001 4002 static struct ena_aenq_handlers aenq_handlers = { 4003 .handlers = { 4004 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 4005 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 4006 }, 4007 .unimplemented_handler = unimplemented_aenq_handler 4008 }; 4009 4010 #ifdef __FreeBSD__ 4011 /********************************************************************* 4012 * FreeBSD Device Interface Entry Points 4013 *********************************************************************/ 4014 4015 static device_method_t ena_methods[] = { 4016 /* Device interface */ 4017 DEVMETHOD(device_probe, ena_probe), 4018 DEVMETHOD(device_attach, ena_attach), 4019 DEVMETHOD(device_detach, ena_detach), 4020 DEVMETHOD_END 4021 }; 4022 4023 static driver_t ena_driver = { 4024 "ena", ena_methods, sizeof(struct ena_adapter), 4025 }; 4026 4027 devclass_t ena_devclass; 4028 DRIVER_MODULE(ena, pci, ena_driver, ena_devclass, 0, 0); 4029 MODULE_DEPEND(ena, pci, 1, 1, 1); 4030 MODULE_DEPEND(ena, ether, 1, 1, 1); 4031 4032 /*********************************************************************/ 4033 #endif /* __FreeBSD__ */ 4034 4035 #ifdef __NetBSD__ 4036 CFATTACH_DECL_NEW(ena, sizeof(struct ena_adapter), ena_probe, ena_attach, 4037 ena_detach, NULL); 4038 #endif /* __NetBSD */ 4039
Indexes created Wed Oct 15 16:09:53 GMT 2025