if_enavar.h revision 1.2.2.2
1 1.2.2.2 pgoyette /* $NetBSD: if_enavar.h,v 1.2.2.2 2018/05/21 04:36:06 pgoyette Exp $ */ 2 1.2.2.2 pgoyette 3 1.2.2.2 pgoyette /*- 4 1.2.2.2 pgoyette * BSD LICENSE 5 1.2.2.2 pgoyette * 6 1.2.2.2 pgoyette * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 7 1.2.2.2 pgoyette * All rights reserved. 8 1.2.2.2 pgoyette * 9 1.2.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 10 1.2.2.2 pgoyette * modification, are permitted provided that the following conditions 11 1.2.2.2 pgoyette * are met: 12 1.2.2.2 pgoyette * 13 1.2.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 pgoyette * 16 1.2.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 17 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 18 1.2.2.2 pgoyette * documentation and/or other materials provided with the distribution. 19 1.2.2.2 pgoyette * 20 1.2.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 1.2.2.2 pgoyette * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 1.2.2.2 pgoyette * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 1.2.2.2 pgoyette * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 1.2.2.2 pgoyette * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 1.2.2.2 pgoyette * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 1.2.2.2 pgoyette * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.2.2.2 pgoyette * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.2.2.2 pgoyette * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.2.2.2 pgoyette * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 1.2.2.2 pgoyette * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.2.2.2 pgoyette * 32 1.2.2.2 pgoyette * $FreeBSD: head/sys/dev/ena/ena.h 333450 2018-05-10 09:06:21Z mw $ 33 1.2.2.2 pgoyette * 34 1.2.2.2 pgoyette */ 35 1.2.2.2 pgoyette 36 1.2.2.2 pgoyette #ifndef ENA_H 37 1.2.2.2 pgoyette #define ENA_H 38 1.2.2.2 pgoyette 39 1.2.2.2 pgoyette #include <sys/types.h> 40 1.2.2.2 pgoyette 41 1.2.2.2 pgoyette #include "external/bsd/ena-com/ena_com.h" 42 1.2.2.2 pgoyette #include "external/bsd/ena-com/ena_eth_com.h" 43 1.2.2.2 pgoyette 44 1.2.2.2 pgoyette #define DRV_MODULE_VER_MAJOR 0 45 1.2.2.2 pgoyette #define DRV_MODULE_VER_MINOR 8 46 1.2.2.2 pgoyette #define DRV_MODULE_VER_SUBMINOR 1 47 1.2.2.2 pgoyette 48 1.2.2.2 pgoyette #define DRV_MODULE_NAME "ena" 49 1.2.2.2 pgoyette 50 1.2.2.2 pgoyette #ifndef DRV_MODULE_VERSION 51 1.2.2.2 pgoyette #define DRV_MODULE_VERSION \ 52 1.2.2.2 pgoyette __STRING(DRV_MODULE_VER_MAJOR) "." \ 53 1.2.2.2 pgoyette __STRING(DRV_MODULE_VER_MINOR) "." \ 54 1.2.2.2 pgoyette __STRING(DRV_MODULE_VER_SUBMINOR) 55 1.2.2.2 pgoyette #endif 56 1.2.2.2 pgoyette #define DEVICE_NAME "Elastic Network Adapter (ENA)" 57 1.2.2.2 pgoyette #define DEVICE_DESC "ENA adapter" 58 1.2.2.2 pgoyette 59 1.2.2.2 pgoyette /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */ 60 1.2.2.2 pgoyette #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL) 61 1.2.2.2 pgoyette 62 1.2.2.2 pgoyette /* 1 for AENQ + ADMIN */ 63 1.2.2.2 pgoyette #define ENA_ADMIN_MSIX_VEC 1 64 1.2.2.2 pgoyette #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 65 1.2.2.2 pgoyette 66 1.2.2.2 pgoyette #define ENA_REG_BAR 0 67 1.2.2.2 pgoyette #define ENA_MEM_BAR 2 68 1.2.2.2 pgoyette 69 1.2.2.2 pgoyette #define ENA_BUS_DMA_SEGS 32 70 1.2.2.2 pgoyette 71 1.2.2.2 pgoyette #define ENA_DEFAULT_RING_SIZE 1024 72 1.2.2.2 pgoyette 73 1.2.2.2 pgoyette #define ENA_RX_REFILL_THRESH_DIVIDER 8 74 1.2.2.2 pgoyette 75 1.2.2.2 pgoyette #define ENA_IRQNAME_SIZE 40 76 1.2.2.2 pgoyette 77 1.2.2.2 pgoyette #define ENA_PKT_MAX_BUFS 19 78 1.2.2.2 pgoyette 79 1.2.2.2 pgoyette #define ENA_RX_RSS_TABLE_LOG_SIZE 7 80 1.2.2.2 pgoyette #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 81 1.2.2.2 pgoyette 82 1.2.2.2 pgoyette #define ENA_HASH_KEY_SIZE 40 83 1.2.2.2 pgoyette 84 1.2.2.2 pgoyette #define ENA_MAX_FRAME_LEN 10000 85 1.2.2.2 pgoyette #define ENA_MIN_FRAME_LEN 60 86 1.2.2.2 pgoyette 87 1.2.2.2 pgoyette #define ENA_TX_CLEANUP_THRESHOLD 128 88 1.2.2.2 pgoyette 89 1.2.2.2 pgoyette #define DB_THRESHOLD 64 90 1.2.2.2 pgoyette 91 1.2.2.2 pgoyette #define TX_COMMIT 32 92 1.2.2.2 pgoyette /* 93 1.2.2.2 pgoyette * TX budget for cleaning. It should be half of the RX budget to reduce amount 94 1.2.2.2 pgoyette * of TCP retransmissions. 95 1.2.2.2 pgoyette */ 96 1.2.2.2 pgoyette #define TX_BUDGET 128 97 1.2.2.2 pgoyette /* RX cleanup budget. -1 stands for infinity. */ 98 1.2.2.2 pgoyette #define RX_BUDGET 256 99 1.2.2.2 pgoyette /* 100 1.2.2.2 pgoyette * How many times we can repeat cleanup in the io irq handling routine if the 101 1.2.2.2 pgoyette * RX or TX budget was depleted. 102 1.2.2.2 pgoyette */ 103 1.2.2.2 pgoyette #define CLEAN_BUDGET 8 104 1.2.2.2 pgoyette 105 1.2.2.2 pgoyette #define RX_IRQ_INTERVAL 20 106 1.2.2.2 pgoyette #define TX_IRQ_INTERVAL 50 107 1.2.2.2 pgoyette 108 1.2.2.2 pgoyette #define ENA_MIN_MTU 128 109 1.2.2.2 pgoyette 110 1.2.2.2 pgoyette #define ENA_TSO_MAXSIZE 65536 111 1.2.2.2 pgoyette 112 1.2.2.2 pgoyette #define ENA_MMIO_DISABLE_REG_READ BIT(0) 113 1.2.2.2 pgoyette 114 1.2.2.2 pgoyette #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 115 1.2.2.2 pgoyette 116 1.2.2.2 pgoyette #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 117 1.2.2.2 pgoyette 118 1.2.2.2 pgoyette #define ENA_IO_TXQ_IDX(q) (2 * (q)) 119 1.2.2.2 pgoyette #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 120 1.2.2.2 pgoyette 121 1.2.2.2 pgoyette #define ENA_MGMNT_IRQ_IDX 0 122 1.2.2.2 pgoyette #define ENA_IO_IRQ_FIRST_IDX 1 123 1.2.2.2 pgoyette #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 124 1.2.2.2 pgoyette 125 1.2.2.2 pgoyette /* 126 1.2.2.2 pgoyette * ENA device should send keep alive msg every 1 sec. 127 1.2.2.2 pgoyette * We wait for 6 sec just to be on the safe side. 128 1.2.2.2 pgoyette */ 129 1.2.2.2 pgoyette #define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6) 130 1.2.2.2 pgoyette 131 1.2.2.2 pgoyette /* Time in jiffies before concluding the transmitter is hung. */ 132 1.2.2.2 pgoyette #define DEFAULT_TX_CMP_TO (SBT_1S * 5) 133 1.2.2.2 pgoyette 134 1.2.2.2 pgoyette /* Number of queues to check for missing queues per timer tick */ 135 1.2.2.2 pgoyette #define DEFAULT_TX_MONITORED_QUEUES (4) 136 1.2.2.2 pgoyette 137 1.2.2.2 pgoyette /* Max number of timeouted packets before device reset */ 138 1.2.2.2 pgoyette #define DEFAULT_TX_CMP_THRESHOLD (128) 139 1.2.2.2 pgoyette 140 1.2.2.2 pgoyette /* 141 1.2.2.2 pgoyette * Supported PCI vendor and devices IDs 142 1.2.2.2 pgoyette */ 143 1.2.2.2 pgoyette #define PCI_VENDOR_ID_AMAZON 0x1d0f 144 1.2.2.2 pgoyette 145 1.2.2.2 pgoyette #define PCI_DEV_ID_ENA_PF 0x0ec2 146 1.2.2.2 pgoyette #define PCI_DEV_ID_ENA_LLQ_PF 0x1ec2 147 1.2.2.2 pgoyette #define PCI_DEV_ID_ENA_VF 0xec20 148 1.2.2.2 pgoyette #define PCI_DEV_ID_ENA_LLQ_VF 0xec21 149 1.2.2.2 pgoyette 150 1.2.2.2 pgoyette struct msix_entry { 151 1.2.2.2 pgoyette int entry; 152 1.2.2.2 pgoyette int vector; 153 1.2.2.2 pgoyette }; 154 1.2.2.2 pgoyette 155 1.2.2.2 pgoyette typedef struct _ena_vendor_info_t { 156 1.2.2.2 pgoyette unsigned int vendor_id; 157 1.2.2.2 pgoyette unsigned int device_id; 158 1.2.2.2 pgoyette unsigned int index; 159 1.2.2.2 pgoyette } ena_vendor_info_t; 160 1.2.2.2 pgoyette 161 1.2.2.2 pgoyette struct ena_irq { 162 1.2.2.2 pgoyette /* Interrupt resources */ 163 1.2.2.2 pgoyette struct resource *res; 164 1.2.2.2 pgoyette void *handler; 165 1.2.2.2 pgoyette void *data; 166 1.2.2.2 pgoyette void *cookie; 167 1.2.2.2 pgoyette unsigned int vector; 168 1.2.2.2 pgoyette bool requested; 169 1.2.2.2 pgoyette int cpu; 170 1.2.2.2 pgoyette char name[ENA_IRQNAME_SIZE]; 171 1.2.2.2 pgoyette }; 172 1.2.2.2 pgoyette 173 1.2.2.2 pgoyette struct ena_que { 174 1.2.2.2 pgoyette struct ena_adapter *adapter; 175 1.2.2.2 pgoyette struct ena_ring *tx_ring; 176 1.2.2.2 pgoyette struct ena_ring *rx_ring; 177 1.2.2.2 pgoyette uint32_t id; 178 1.2.2.2 pgoyette int cpu; 179 1.2.2.2 pgoyette }; 180 1.2.2.2 pgoyette 181 1.2.2.2 pgoyette struct ena_tx_buffer { 182 1.2.2.2 pgoyette struct mbuf *mbuf; 183 1.2.2.2 pgoyette /* # of ena desc for this specific mbuf 184 1.2.2.2 pgoyette * (includes data desc and metadata desc) */ 185 1.2.2.2 pgoyette unsigned int tx_descs; 186 1.2.2.2 pgoyette /* # of buffers used by this mbuf */ 187 1.2.2.2 pgoyette unsigned int num_of_bufs; 188 1.2.2.2 pgoyette bus_dmamap_t map; 189 1.2.2.2 pgoyette 190 1.2.2.2 pgoyette /* Used to detect missing tx packets */ 191 1.2.2.2 pgoyette struct bintime timestamp; 192 1.2.2.2 pgoyette bool print_once; 193 1.2.2.2 pgoyette 194 1.2.2.2 pgoyette struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 195 1.2.2.2 pgoyette } __aligned(CACHE_LINE_SIZE); 196 1.2.2.2 pgoyette 197 1.2.2.2 pgoyette struct ena_rx_buffer { 198 1.2.2.2 pgoyette struct mbuf *mbuf; 199 1.2.2.2 pgoyette bus_dmamap_t map; 200 1.2.2.2 pgoyette struct ena_com_buf ena_buf; 201 1.2.2.2 pgoyette } __aligned(CACHE_LINE_SIZE); 202 1.2.2.2 pgoyette 203 1.2.2.2 pgoyette struct ena_stats_tx { 204 1.2.2.2 pgoyette struct evcnt cnt; 205 1.2.2.2 pgoyette struct evcnt bytes; 206 1.2.2.2 pgoyette struct evcnt prepare_ctx_err; 207 1.2.2.2 pgoyette struct evcnt dma_mapping_err; 208 1.2.2.2 pgoyette struct evcnt doorbells; 209 1.2.2.2 pgoyette struct evcnt missing_tx_comp; 210 1.2.2.2 pgoyette struct evcnt bad_req_id; 211 1.2.2.2 pgoyette struct evcnt collapse; 212 1.2.2.2 pgoyette struct evcnt collapse_err; 213 1.2.2.2 pgoyette }; 214 1.2.2.2 pgoyette 215 1.2.2.2 pgoyette struct ena_stats_rx { 216 1.2.2.2 pgoyette struct evcnt cnt; 217 1.2.2.2 pgoyette struct evcnt bytes; 218 1.2.2.2 pgoyette struct evcnt refil_partial; 219 1.2.2.2 pgoyette struct evcnt bad_csum; 220 1.2.2.2 pgoyette struct evcnt mjum_alloc_fail; 221 1.2.2.2 pgoyette struct evcnt mbuf_alloc_fail; 222 1.2.2.2 pgoyette struct evcnt dma_mapping_err; 223 1.2.2.2 pgoyette struct evcnt bad_desc_num; 224 1.2.2.2 pgoyette struct evcnt bad_req_id; 225 1.2.2.2 pgoyette struct evcnt empty_rx_ring; 226 1.2.2.2 pgoyette }; 227 1.2.2.2 pgoyette 228 1.2.2.2 pgoyette struct ena_ring { 229 1.2.2.2 pgoyette /* Holds the empty requests for TX/RX out of order completions */ 230 1.2.2.2 pgoyette union { 231 1.2.2.2 pgoyette uint16_t *free_tx_ids; 232 1.2.2.2 pgoyette uint16_t *free_rx_ids; 233 1.2.2.2 pgoyette }; 234 1.2.2.2 pgoyette struct ena_com_dev *ena_dev; 235 1.2.2.2 pgoyette struct ena_adapter *adapter; 236 1.2.2.2 pgoyette struct ena_com_io_cq *ena_com_io_cq; 237 1.2.2.2 pgoyette struct ena_com_io_sq *ena_com_io_sq; 238 1.2.2.2 pgoyette 239 1.2.2.2 pgoyette uint16_t qid; 240 1.2.2.2 pgoyette 241 1.2.2.2 pgoyette /* Determines if device will use LLQ or normal mode for TX */ 242 1.2.2.2 pgoyette enum ena_admin_placement_policy_type tx_mem_queue_type; 243 1.2.2.2 pgoyette /* The maximum length the driver can push to the device (For LLQ) */ 244 1.2.2.2 pgoyette uint8_t tx_max_header_size; 245 1.2.2.2 pgoyette 246 1.2.2.2 pgoyette struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 247 1.2.2.2 pgoyette 248 1.2.2.2 pgoyette /* 249 1.2.2.2 pgoyette * Fields used for Adaptive Interrupt Modulation - to be implemented in 250 1.2.2.2 pgoyette * the future releases 251 1.2.2.2 pgoyette */ 252 1.2.2.2 pgoyette uint32_t smoothed_interval; 253 1.2.2.2 pgoyette enum ena_intr_moder_level moder_tbl_idx; 254 1.2.2.2 pgoyette 255 1.2.2.2 pgoyette struct ena_que *que; 256 1.2.2.2 pgoyette #ifdef LRO 257 1.2.2.2 pgoyette struct lro_ctrl lro; 258 1.2.2.2 pgoyette #endif 259 1.2.2.2 pgoyette 260 1.2.2.2 pgoyette uint16_t next_to_use; 261 1.2.2.2 pgoyette uint16_t next_to_clean; 262 1.2.2.2 pgoyette 263 1.2.2.2 pgoyette union { 264 1.2.2.2 pgoyette struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 265 1.2.2.2 pgoyette struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */ 266 1.2.2.2 pgoyette }; 267 1.2.2.2 pgoyette int ring_size; /* number of tx/rx_buffer_info's entries */ 268 1.2.2.2 pgoyette 269 1.2.2.2 pgoyette struct buf_ring *br; /* only for TX */ 270 1.2.2.2 pgoyette 271 1.2.2.2 pgoyette kmutex_t ring_mtx; 272 1.2.2.2 pgoyette char mtx_name[16]; 273 1.2.2.2 pgoyette 274 1.2.2.2 pgoyette union { 275 1.2.2.2 pgoyette struct { 276 1.2.2.2 pgoyette struct work enqueue_task; 277 1.2.2.2 pgoyette struct workqueue *enqueue_tq; 278 1.2.2.2 pgoyette }; 279 1.2.2.2 pgoyette struct { 280 1.2.2.2 pgoyette struct work cmpl_task; 281 1.2.2.2 pgoyette struct workqueue *cmpl_tq; 282 1.2.2.2 pgoyette }; 283 1.2.2.2 pgoyette }; 284 1.2.2.2 pgoyette 285 1.2.2.2 pgoyette union { 286 1.2.2.2 pgoyette struct ena_stats_tx tx_stats; 287 1.2.2.2 pgoyette struct ena_stats_rx rx_stats; 288 1.2.2.2 pgoyette }; 289 1.2.2.2 pgoyette 290 1.2.2.2 pgoyette int empty_rx_queue; 291 1.2.2.2 pgoyette } __aligned(CACHE_LINE_SIZE); 292 1.2.2.2 pgoyette 293 1.2.2.2 pgoyette struct ena_stats_dev { 294 1.2.2.2 pgoyette struct evcnt wd_expired; 295 1.2.2.2 pgoyette struct evcnt interface_up; 296 1.2.2.2 pgoyette struct evcnt interface_down; 297 1.2.2.2 pgoyette struct evcnt admin_q_pause; 298 1.2.2.2 pgoyette }; 299 1.2.2.2 pgoyette 300 1.2.2.2 pgoyette struct ena_hw_stats { 301 1.2.2.2 pgoyette struct evcnt rx_packets; 302 1.2.2.2 pgoyette struct evcnt tx_packets; 303 1.2.2.2 pgoyette 304 1.2.2.2 pgoyette struct evcnt rx_bytes; 305 1.2.2.2 pgoyette struct evcnt tx_bytes; 306 1.2.2.2 pgoyette 307 1.2.2.2 pgoyette struct evcnt rx_drops; 308 1.2.2.2 pgoyette }; 309 1.2.2.2 pgoyette 310 1.2.2.2 pgoyette /* Board specific private data structure */ 311 1.2.2.2 pgoyette struct ena_adapter { 312 1.2.2.2 pgoyette struct ena_com_dev *ena_dev; 313 1.2.2.2 pgoyette 314 1.2.2.2 pgoyette /* OS defined structs */ 315 1.2.2.2 pgoyette device_t pdev; 316 1.2.2.2 pgoyette struct ethercom sc_ec; 317 1.2.2.2 pgoyette struct ifnet *ifp; /* set to point to sc_ec */ 318 1.2.2.2 pgoyette struct ifmedia media; 319 1.2.2.2 pgoyette 320 1.2.2.2 pgoyette /* OS resources */ 321 1.2.2.2 pgoyette struct resource *memory; 322 1.2.2.2 pgoyette struct resource *registers; 323 1.2.2.2 pgoyette 324 1.2.2.2 pgoyette kmutex_t global_mtx; 325 1.2.2.2 pgoyette krwlock_t ioctl_sx; 326 1.2.2.2 pgoyette 327 1.2.2.2 pgoyette /* MSI-X */ 328 1.2.2.2 pgoyette uint32_t msix_enabled; 329 1.2.2.2 pgoyette struct msix_entry *msix_entries; 330 1.2.2.2 pgoyette int msix_vecs; 331 1.2.2.2 pgoyette 332 1.2.2.2 pgoyette /* DMA tag used throughout the driver adapter for Tx and Rx */ 333 1.2.2.2 pgoyette bus_dma_tag_t sc_dmat; 334 1.2.2.2 pgoyette int dma_width; 335 1.2.2.2 pgoyette 336 1.2.2.2 pgoyette uint32_t max_mtu; 337 1.2.2.2 pgoyette 338 1.2.2.2 pgoyette uint16_t max_tx_sgl_size; 339 1.2.2.2 pgoyette uint16_t max_rx_sgl_size; 340 1.2.2.2 pgoyette 341 1.2.2.2 pgoyette uint32_t tx_offload_cap; 342 1.2.2.2 pgoyette 343 1.2.2.2 pgoyette /* Tx fast path data */ 344 1.2.2.2 pgoyette int num_queues; 345 1.2.2.2 pgoyette 346 1.2.2.2 pgoyette unsigned int tx_ring_size; 347 1.2.2.2 pgoyette unsigned int rx_ring_size; 348 1.2.2.2 pgoyette 349 1.2.2.2 pgoyette /* RSS*/ 350 1.2.2.2 pgoyette uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE]; 351 1.2.2.2 pgoyette bool rss_support; 352 1.2.2.2 pgoyette 353 1.2.2.2 pgoyette uint8_t mac_addr[ETHER_ADDR_LEN]; 354 1.2.2.2 pgoyette /* mdio and phy*/ 355 1.2.2.2 pgoyette 356 1.2.2.2 pgoyette bool link_status; 357 1.2.2.2 pgoyette bool trigger_reset; 358 1.2.2.2 pgoyette bool up; 359 1.2.2.2 pgoyette bool running; 360 1.2.2.2 pgoyette 361 1.2.2.2 pgoyette /* Queue will represent one TX and one RX ring */ 362 1.2.2.2 pgoyette struct ena_que que[ENA_MAX_NUM_IO_QUEUES] 363 1.2.2.2 pgoyette __aligned(CACHE_LINE_SIZE); 364 1.2.2.2 pgoyette 365 1.2.2.2 pgoyette /* TX */ 366 1.2.2.2 pgoyette struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 367 1.2.2.2 pgoyette __aligned(CACHE_LINE_SIZE); 368 1.2.2.2 pgoyette 369 1.2.2.2 pgoyette /* RX */ 370 1.2.2.2 pgoyette struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 371 1.2.2.2 pgoyette __aligned(CACHE_LINE_SIZE); 372 1.2.2.2 pgoyette 373 1.2.2.2 pgoyette struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 374 1.2.2.2 pgoyette 375 1.2.2.2 pgoyette /* Timer service */ 376 1.2.2.2 pgoyette struct callout timer_service; 377 1.2.2.2 pgoyette struct bintime keep_alive_timestamp; 378 1.2.2.2 pgoyette uint32_t next_monitored_tx_qid; 379 1.2.2.2 pgoyette struct work reset_task; 380 1.2.2.2 pgoyette struct workqueue *reset_tq; 381 1.2.2.2 pgoyette int wd_active; 382 1.2.2.2 pgoyette struct bintime keep_alive_timeout; 383 1.2.2.2 pgoyette struct bintime missing_tx_timeout; 384 1.2.2.2 pgoyette uint32_t missing_tx_max_queues; 385 1.2.2.2 pgoyette uint32_t missing_tx_threshold; 386 1.2.2.2 pgoyette 387 1.2.2.2 pgoyette /* Statistics */ 388 1.2.2.2 pgoyette struct ena_stats_dev dev_stats; 389 1.2.2.2 pgoyette struct ena_hw_stats hw_stats; 390 1.2.2.2 pgoyette 391 1.2.2.2 pgoyette enum ena_regs_reset_reason_types reset_reason; 392 1.2.2.2 pgoyette }; 393 1.2.2.2 pgoyette 394 1.2.2.2 pgoyette #define ENA_RING_MTX_LOCK(_ring) mutex_enter(&(_ring)->ring_mtx) 395 1.2.2.2 pgoyette #define ENA_RING_MTX_TRYLOCK(_ring) mutex_tryenter(&(_ring)->ring_mtx) 396 1.2.2.2 pgoyette #define ENA_RING_MTX_UNLOCK(_ring) mutex_exit(&(_ring)->ring_mtx) 397 1.2.2.2 pgoyette 398 1.2.2.2 pgoyette static inline int ena_mbuf_count(struct mbuf *mbuf) 399 1.2.2.2 pgoyette { 400 1.2.2.2 pgoyette int count = 1; 401 1.2.2.2 pgoyette 402 1.2.2.2 pgoyette while ((mbuf = mbuf->m_next) != NULL) 403 1.2.2.2 pgoyette ++count; 404 1.2.2.2 pgoyette 405 1.2.2.2 pgoyette return count; 406 1.2.2.2 pgoyette } 407 1.2.2.2 pgoyette 408 1.2.2.2 pgoyette #endif /* !(ENA_H) */ 409
Indexes created Tue Sep 30 20:09:53 GMT 2025