Home | History | Annotate | Line # | Download | only in pci
if_enavar.h revision 1.2 
      1 /*	$NetBSD: if_enavar.h,v 1.2 2018/05/19 09:32:55 jdolecek Exp $	*/
      2 
      3 /*-
      4  * BSD LICENSE
      5  *
      6  * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
      7  * All rights reserved.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  *
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  *
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  *
     32  * $FreeBSD: head/sys/dev/ena/ena.h 333450 2018-05-10 09:06:21Z mw $
     33  *
     34  */
     35 
     36 #ifndef ENA_H
     37 #define ENA_H
     38 
     39 #include <sys/types.h>
     40 
     41 #include "external/bsd/ena-com/ena_com.h"
     42 #include "external/bsd/ena-com/ena_eth_com.h"
     43 
     44 #define DRV_MODULE_VER_MAJOR	0
     45 #define DRV_MODULE_VER_MINOR	8
     46 #define DRV_MODULE_VER_SUBMINOR 1
     47 
     48 #define DRV_MODULE_NAME		"ena"
     49 
     50 #ifndef DRV_MODULE_VERSION
     51 #define DRV_MODULE_VERSION				\
     52 	__STRING(DRV_MODULE_VER_MAJOR) "."		\
     53 	__STRING(DRV_MODULE_VER_MINOR) "."		\
     54 	__STRING(DRV_MODULE_VER_SUBMINOR)
     55 #endif
     56 #define DEVICE_NAME	"Elastic Network Adapter (ENA)"
     57 #define DEVICE_DESC	"ENA adapter"
     58 
     59 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
     60 #define ENA_DMA_BIT_MASK(x)		((1ULL << (x)) - 1ULL)
     61 
     62 /* 1 for AENQ + ADMIN */
     63 #define	ENA_ADMIN_MSIX_VEC		1
     64 #define	ENA_MAX_MSIX_VEC(io_queues)	(ENA_ADMIN_MSIX_VEC + (io_queues))
     65 
     66 #define	ENA_REG_BAR			0
     67 #define	ENA_MEM_BAR			2
     68 
     69 #define	ENA_BUS_DMA_SEGS		32
     70 
     71 #define	ENA_DEFAULT_RING_SIZE		1024
     72 
     73 #define	ENA_RX_REFILL_THRESH_DIVIDER	8
     74 
     75 #define	ENA_IRQNAME_SIZE		40
     76 
     77 #define	ENA_PKT_MAX_BUFS 		19
     78 
     79 #define	ENA_RX_RSS_TABLE_LOG_SIZE	7
     80 #define	ENA_RX_RSS_TABLE_SIZE		(1 << ENA_RX_RSS_TABLE_LOG_SIZE)
     81 
     82 #define	ENA_HASH_KEY_SIZE		40
     83 
     84 #define	ENA_MAX_FRAME_LEN		10000
     85 #define	ENA_MIN_FRAME_LEN 		60
     86 
     87 #define ENA_TX_CLEANUP_THRESHOLD	128
     88 
     89 #define DB_THRESHOLD	64
     90 
     91 #define TX_COMMIT	32
     92  /*
     93  * TX budget for cleaning. It should be half of the RX budget to reduce amount
     94  *  of TCP retransmissions.
     95  */
     96 #define TX_BUDGET	128
     97 /* RX cleanup budget. -1 stands for infinity. */
     98 #define RX_BUDGET	256
     99 /*
    100  * How many times we can repeat cleanup in the io irq handling routine if the
    101  * RX or TX budget was depleted.
    102  */
    103 #define CLEAN_BUDGET	8
    104 
    105 #define RX_IRQ_INTERVAL 20
    106 #define TX_IRQ_INTERVAL 50
    107 
    108 #define	ENA_MIN_MTU		128
    109 
    110 #define	ENA_TSO_MAXSIZE		65536
    111 
    112 #define	ENA_MMIO_DISABLE_REG_READ	BIT(0)
    113 
    114 #define	ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
    115 
    116 #define	ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
    117 
    118 #define	ENA_IO_TXQ_IDX(q)		(2 * (q))
    119 #define	ENA_IO_RXQ_IDX(q)		(2 * (q) + 1)
    120 
    121 #define	ENA_MGMNT_IRQ_IDX		0
    122 #define	ENA_IO_IRQ_FIRST_IDX		1
    123 #define	ENA_IO_IRQ_IDX(q)		(ENA_IO_IRQ_FIRST_IDX + (q))
    124 
    125 /*
    126  * ENA device should send keep alive msg every 1 sec.
    127  * We wait for 6 sec just to be on the safe side.
    128  */
    129 #define DEFAULT_KEEP_ALIVE_TO		(SBT_1S * 6)
    130 
    131 /* Time in jiffies before concluding the transmitter is hung. */
    132 #define DEFAULT_TX_CMP_TO		(SBT_1S * 5)
    133 
    134 /* Number of queues to check for missing queues per timer tick */
    135 #define DEFAULT_TX_MONITORED_QUEUES	(4)
    136 
    137 /* Max number of timeouted packets before device reset */
    138 #define DEFAULT_TX_CMP_THRESHOLD	(128)
    139 
    140 /*
    141  * Supported PCI vendor and devices IDs
    142  */
    143 #define	PCI_VENDOR_ID_AMAZON	0x1d0f
    144 
    145 #define	PCI_DEV_ID_ENA_PF	0x0ec2
    146 #define	PCI_DEV_ID_ENA_LLQ_PF	0x1ec2
    147 #define	PCI_DEV_ID_ENA_VF	0xec20
    148 #define	PCI_DEV_ID_ENA_LLQ_VF	0xec21
    149 
    150 struct msix_entry {
    151 	int entry;
    152 	int vector;
    153 };
    154 
    155 typedef struct _ena_vendor_info_t {
    156 	unsigned int vendor_id;
    157 	unsigned int device_id;
    158 	unsigned int index;
    159 } ena_vendor_info_t;
    160 
    161 struct ena_irq {
    162 	/* Interrupt resources */
    163 	struct resource *res;
    164 	void *handler;
    165 	void *data;
    166 	void *cookie;
    167 	unsigned int vector;
    168 	bool requested;
    169 	int cpu;
    170 	char name[ENA_IRQNAME_SIZE];
    171 };
    172 
    173 struct ena_que {
    174 	struct ena_adapter *adapter;
    175 	struct ena_ring *tx_ring;
    176 	struct ena_ring *rx_ring;
    177 	uint32_t id;
    178 	int cpu;
    179 };
    180 
    181 struct ena_tx_buffer {
    182 	struct mbuf *mbuf;
    183 	/* # of ena desc for this specific mbuf
    184 	 * (includes data desc and metadata desc) */
    185 	unsigned int tx_descs;
    186 	/* # of buffers used by this mbuf */
    187 	unsigned int num_of_bufs;
    188 	bus_dmamap_t map;
    189 
    190 	/* Used to detect missing tx packets */
    191 	struct bintime timestamp;
    192 	bool print_once;
    193 
    194 	struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
    195 } __aligned(CACHE_LINE_SIZE);
    196 
    197 struct ena_rx_buffer {
    198 	struct mbuf *mbuf;
    199 	bus_dmamap_t map;
    200 	struct ena_com_buf ena_buf;
    201 } __aligned(CACHE_LINE_SIZE);
    202 
    203 struct ena_stats_tx {
    204 	struct evcnt cnt;
    205 	struct evcnt bytes;
    206 	struct evcnt prepare_ctx_err;
    207 	struct evcnt dma_mapping_err;
    208 	struct evcnt doorbells;
    209 	struct evcnt missing_tx_comp;
    210 	struct evcnt bad_req_id;
    211 	struct evcnt collapse;
    212 	struct evcnt collapse_err;
    213 };
    214 
    215 struct ena_stats_rx {
    216 	struct evcnt cnt;
    217 	struct evcnt bytes;
    218 	struct evcnt refil_partial;
    219 	struct evcnt bad_csum;
    220 	struct evcnt mjum_alloc_fail;
    221 	struct evcnt mbuf_alloc_fail;
    222 	struct evcnt dma_mapping_err;
    223 	struct evcnt bad_desc_num;
    224 	struct evcnt bad_req_id;
    225 	struct evcnt empty_rx_ring;
    226 };
    227 
    228 struct ena_ring {
    229 	/* Holds the empty requests for TX/RX out of order completions */
    230 	union {
    231 		uint16_t *free_tx_ids;
    232 		uint16_t *free_rx_ids;
    233 	};
    234 	struct ena_com_dev *ena_dev;
    235 	struct ena_adapter *adapter;
    236 	struct ena_com_io_cq *ena_com_io_cq;
    237 	struct ena_com_io_sq *ena_com_io_sq;
    238 
    239 	uint16_t qid;
    240 
    241 	/* Determines if device will use LLQ or normal mode for TX */
    242 	enum ena_admin_placement_policy_type tx_mem_queue_type;
    243 	/* The maximum length the driver can push to the device (For LLQ) */
    244 	uint8_t tx_max_header_size;
    245 
    246 	struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
    247 
    248 	/*
    249 	 * Fields used for Adaptive Interrupt Modulation - to be implemented in
    250 	 * the future releases
    251 	 */
    252 	uint32_t  smoothed_interval;
    253 	enum ena_intr_moder_level moder_tbl_idx;
    254 
    255 	struct ena_que *que;
    256 #ifdef LRO
    257 	struct lro_ctrl lro;
    258 #endif
    259 
    260 	uint16_t next_to_use;
    261 	uint16_t next_to_clean;
    262 
    263 	union {
    264 		struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
    265 		struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
    266 	};
    267 	int ring_size; /* number of tx/rx_buffer_info's entries */
    268 
    269 	struct buf_ring *br; /* only for TX */
    270 
    271 	kmutex_t ring_mtx;
    272 	char mtx_name[16];
    273 
    274 	union {
    275 		struct {
    276 			struct work enqueue_task;
    277 			struct workqueue *enqueue_tq;
    278 		};
    279 		struct {
    280 			struct work cmpl_task;
    281 			struct workqueue *cmpl_tq;
    282 		};
    283 	};
    284 
    285 	union {
    286 		struct ena_stats_tx tx_stats;
    287 		struct ena_stats_rx rx_stats;
    288 	};
    289 
    290 	int empty_rx_queue;
    291 } __aligned(CACHE_LINE_SIZE);
    292 
    293 struct ena_stats_dev {
    294 	struct evcnt wd_expired;
    295 	struct evcnt interface_up;
    296 	struct evcnt interface_down;
    297 	struct evcnt admin_q_pause;
    298 };
    299 
    300 struct ena_hw_stats {
    301 	struct evcnt rx_packets;
    302 	struct evcnt tx_packets;
    303 
    304 	struct evcnt rx_bytes;
    305 	struct evcnt tx_bytes;
    306 
    307 	struct evcnt rx_drops;
    308 };
    309 
    310 /* Board specific private data structure */
    311 struct ena_adapter {
    312 	struct ena_com_dev *ena_dev;
    313 
    314 	/* OS defined structs */
    315 	device_t pdev;
    316         struct ethercom sc_ec;
    317 	struct ifnet *ifp;		/* set to point to sc_ec */
    318 	struct ifmedia	media;
    319 
    320 	/* OS resources */
    321 	struct resource *memory;
    322 	struct resource *registers;
    323 
    324 	kmutex_t global_mtx;
    325 	krwlock_t ioctl_sx;
    326 
    327 	/* MSI-X */
    328 	uint32_t msix_enabled;
    329 	struct msix_entry *msix_entries;
    330 	int msix_vecs;
    331 
    332 	/* DMA tag used throughout the driver adapter for Tx and Rx */
    333 	bus_dma_tag_t sc_dmat;
    334 	int dma_width;
    335 
    336 	uint32_t max_mtu;
    337 
    338 	uint16_t max_tx_sgl_size;
    339 	uint16_t max_rx_sgl_size;
    340 
    341 	uint32_t tx_offload_cap;
    342 
    343 	/* Tx fast path data */
    344 	int num_queues;
    345 
    346 	unsigned int tx_ring_size;
    347 	unsigned int rx_ring_size;
    348 
    349 	/* RSS*/
    350 	uint8_t	rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE];
    351 	bool rss_support;
    352 
    353 	uint8_t mac_addr[ETHER_ADDR_LEN];
    354 	/* mdio and phy*/
    355 
    356 	bool link_status;
    357 	bool trigger_reset;
    358 	bool up;
    359 	bool running;
    360 
    361 	/* Queue will represent one TX and one RX ring */
    362 	struct ena_que que[ENA_MAX_NUM_IO_QUEUES]
    363 	    __aligned(CACHE_LINE_SIZE);
    364 
    365 	/* TX */
    366 	struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
    367 	    __aligned(CACHE_LINE_SIZE);
    368 
    369 	/* RX */
    370 	struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
    371 	    __aligned(CACHE_LINE_SIZE);
    372 
    373 	struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
    374 
    375 	/* Timer service */
    376 	struct callout timer_service;
    377 	struct bintime keep_alive_timestamp;
    378 	uint32_t next_monitored_tx_qid;
    379 	struct work reset_task;
    380 	struct workqueue *reset_tq;
    381 	int wd_active;
    382 	struct bintime keep_alive_timeout;
    383 	struct bintime missing_tx_timeout;
    384 	uint32_t missing_tx_max_queues;
    385 	uint32_t missing_tx_threshold;
    386 
    387 	/* Statistics */
    388 	struct ena_stats_dev dev_stats;
    389 	struct ena_hw_stats hw_stats;
    390 
    391 	enum ena_regs_reset_reason_types reset_reason;
    392 };
    393 
    394 #define	ENA_RING_MTX_LOCK(_ring)	mutex_enter(&(_ring)->ring_mtx)
    395 #define	ENA_RING_MTX_TRYLOCK(_ring)	mutex_tryenter(&(_ring)->ring_mtx)
    396 #define	ENA_RING_MTX_UNLOCK(_ring)	mutex_exit(&(_ring)->ring_mtx)
    397 
    398 static inline int ena_mbuf_count(struct mbuf *mbuf)
    399 {
    400 	int count = 1;
    401 
    402 	while ((mbuf = mbuf->m_next) != NULL)
    403 		++count;
    404 
    405 	return count;
    406 }
    407 
    408 #endif /* !(ENA_H) */
    409