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if_enavar.h revision 1.5 
      1 /*	$NetBSD: if_enavar.h,v 1.5 2018/11/28 19:06:54 jmcneill Exp $	*/
      2 
      3 /*-
      4  * BSD LICENSE
      5  *
      6  * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
      7  * All rights reserved.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  *
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  *
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  *
     32  * $FreeBSD: head/sys/dev/ena/ena.h 333450 2018-05-10 09:06:21Z mw $
     33  *
     34  */
     35 
     36 #ifndef ENA_H
     37 #define ENA_H
     38 
     39 #include <sys/types.h>
     40 
     41 #include "external/bsd/ena-com/ena_com.h"
     42 #include "external/bsd/ena-com/ena_eth_com.h"
     43 
     44 #define DRV_MODULE_VER_MAJOR	0
     45 #define DRV_MODULE_VER_MINOR	8
     46 #define DRV_MODULE_VER_SUBMINOR 1
     47 
     48 #define DRV_MODULE_NAME		"ena"
     49 
     50 #ifndef DRV_MODULE_VERSION
     51 #define DRV_MODULE_VERSION				\
     52 	__STRING(DRV_MODULE_VER_MAJOR) "."		\
     53 	__STRING(DRV_MODULE_VER_MINOR) "."		\
     54 	__STRING(DRV_MODULE_VER_SUBMINOR)
     55 #endif
     56 #define DEVICE_NAME	"Elastic Network Adapter (ENA)"
     57 #define DEVICE_DESC	"ENA adapter"
     58 
     59 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
     60 #define ENA_DMA_BIT_MASK(x)		((1ULL << (x)) - 1ULL)
     61 
     62 /* 1 for AENQ + ADMIN */
     63 #define	ENA_ADMIN_MSIX_VEC		1
     64 #define	ENA_MAX_MSIX_VEC(io_queues)	(ENA_ADMIN_MSIX_VEC + (io_queues))
     65 
     66 #define	ENA_REG_BAR			PCI_BAR(0)
     67 #define	ENA_MEM_BAR			PCI_BAR(2)
     68 
     69 #define	ENA_BUS_DMA_SEGS		32
     70 
     71 #define	ENA_DEFAULT_RING_SIZE		1024
     72 
     73 #define	ENA_RX_REFILL_THRESH_DIVIDER	8
     74 
     75 #define	ENA_IRQNAME_SIZE		40
     76 
     77 #define	ENA_PKT_MAX_BUFS 		19
     78 
     79 #define	ENA_RX_RSS_TABLE_LOG_SIZE	7
     80 #define	ENA_RX_RSS_TABLE_SIZE		(1 << ENA_RX_RSS_TABLE_LOG_SIZE)
     81 
     82 #define	ENA_HASH_KEY_SIZE		40
     83 
     84 #define	ENA_MAX_FRAME_LEN		10000
     85 #define	ENA_MIN_FRAME_LEN 		60
     86 
     87 #define ENA_TX_CLEANUP_THRESHOLD	128
     88 
     89 #define DB_THRESHOLD	64
     90 
     91 #define TX_COMMIT	32
     92  /*
     93  * TX budget for cleaning. It should be half of the RX budget to reduce amount
     94  *  of TCP retransmissions.
     95  */
     96 #define TX_BUDGET	128
     97 /* RX cleanup budget. -1 stands for infinity. */
     98 #define RX_BUDGET	256
     99 /*
    100  * How many times we can repeat cleanup in the io irq handling routine if the
    101  * RX or TX budget was depleted.
    102  */
    103 #define CLEAN_BUDGET	8
    104 
    105 #define RX_IRQ_INTERVAL 20
    106 #define TX_IRQ_INTERVAL 50
    107 
    108 #define	ENA_MIN_MTU		128
    109 
    110 #define	ENA_TSO_MAXSIZE		65536
    111 
    112 #define	ENA_MMIO_DISABLE_REG_READ	BIT(0)
    113 
    114 #define	ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
    115 
    116 #define	ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
    117 
    118 #define	ENA_IO_TXQ_IDX(q)		(2 * (q))
    119 #define	ENA_IO_RXQ_IDX(q)		(2 * (q) + 1)
    120 
    121 #define	ENA_MGMNT_IRQ_IDX		0
    122 #define	ENA_IO_IRQ_FIRST_IDX		1
    123 #define	ENA_IO_IRQ_IDX(q)		(ENA_IO_IRQ_FIRST_IDX + (q))
    124 
    125 /*
    126  * ENA device should send keep alive msg every 1 sec.
    127  * We wait for 6 sec just to be on the safe side.
    128  */
    129 #define DEFAULT_KEEP_ALIVE_TO		(SBT_1S * 6)
    130 
    131 /* Time in jiffies before concluding the transmitter is hung. */
    132 #define DEFAULT_TX_CMP_TO		(SBT_1S * 5)
    133 
    134 /* Number of queues to check for missing queues per timer tick */
    135 #define DEFAULT_TX_MONITORED_QUEUES	(4)
    136 
    137 /* Max number of timeouted packets before device reset */
    138 #define DEFAULT_TX_CMP_THRESHOLD	(128)
    139 
    140 /*
    141  * Supported PCI vendor and devices IDs
    142  */
    143 #define	PCI_VENDOR_ID_AMAZON	0x1d0f
    144 
    145 #define	PCI_DEV_ID_ENA_PF	0x0ec2
    146 #define	PCI_DEV_ID_ENA_LLQ_PF	0x1ec2
    147 #define	PCI_DEV_ID_ENA_VF	0xec20
    148 #define	PCI_DEV_ID_ENA_LLQ_VF	0xec21
    149 
    150 typedef __int64_t sbintime_t;
    151 
    152 struct msix_entry {
    153 	int entry;
    154 	int vector;
    155 };
    156 
    157 typedef struct _ena_vendor_info_t {
    158 	unsigned int vendor_id;
    159 	unsigned int device_id;
    160 	unsigned int index;
    161 } ena_vendor_info_t;
    162 
    163 struct ena_que {
    164 	struct ena_adapter *adapter;
    165 	struct ena_ring *tx_ring;
    166 	struct ena_ring *rx_ring;
    167 	uint32_t id;
    168 	int cpu;
    169 };
    170 
    171 struct ena_tx_buffer {
    172 	struct mbuf *mbuf;
    173 	/* # of ena desc for this specific mbuf
    174 	 * (includes data desc and metadata desc) */
    175 	unsigned int tx_descs;
    176 	/* # of buffers used by this mbuf */
    177 	unsigned int num_of_bufs;
    178 	bus_dmamap_t map;
    179 
    180 	/* Used to detect missing tx packets */
    181 	struct bintime timestamp;
    182 	bool print_once;
    183 
    184 	struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
    185 } __aligned(CACHE_LINE_SIZE);
    186 
    187 struct ena_rx_buffer {
    188 	struct mbuf *mbuf;
    189 	bus_dmamap_t map;
    190 	struct ena_com_buf ena_buf;
    191 } __aligned(CACHE_LINE_SIZE);
    192 
    193 struct ena_stats_tx {
    194 	char name[16];
    195 	struct evcnt cnt;
    196 	struct evcnt bytes;
    197 	struct evcnt prepare_ctx_err;
    198 	struct evcnt dma_mapping_err;
    199 	struct evcnt doorbells;
    200 	struct evcnt missing_tx_comp;
    201 	struct evcnt bad_req_id;
    202 	struct evcnt collapse;
    203 	struct evcnt collapse_err;
    204 };
    205 
    206 struct ena_stats_rx {
    207 	char name[16];
    208 	struct evcnt cnt;
    209 	struct evcnt bytes;
    210 	struct evcnt refil_partial;
    211 	struct evcnt bad_csum;
    212 	struct evcnt mjum_alloc_fail;
    213 	struct evcnt mbuf_alloc_fail;
    214 	struct evcnt dma_mapping_err;
    215 	struct evcnt bad_desc_num;
    216 	struct evcnt bad_req_id;
    217 	struct evcnt empty_rx_ring;
    218 };
    219 
    220 struct ena_ring {
    221 	/* Holds the empty requests for TX/RX out of order completions */
    222 	union {
    223 		uint16_t *free_tx_ids;
    224 		uint16_t *free_rx_ids;
    225 	};
    226 	struct ena_com_dev *ena_dev;
    227 	struct ena_adapter *adapter;
    228 	struct ena_com_io_cq *ena_com_io_cq;
    229 	struct ena_com_io_sq *ena_com_io_sq;
    230 
    231 	uint16_t qid;
    232 
    233 	/* Determines if device will use LLQ or normal mode for TX */
    234 	enum ena_admin_placement_policy_type tx_mem_queue_type;
    235 	/* The maximum length the driver can push to the device (For LLQ) */
    236 	uint8_t tx_max_header_size;
    237 
    238 	struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
    239 
    240 	/*
    241 	 * Fields used for Adaptive Interrupt Modulation - to be implemented in
    242 	 * the future releases
    243 	 */
    244 	uint32_t  smoothed_interval;
    245 	enum ena_intr_moder_level moder_tbl_idx;
    246 
    247 	struct ena_que *que;
    248 #ifdef LRO
    249 	struct lro_ctrl lro;
    250 #endif
    251 
    252 	uint16_t next_to_use;
    253 	uint16_t next_to_clean;
    254 
    255 	union {
    256 		struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
    257 		struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
    258 	};
    259 	int ring_size; /* number of tx/rx_buffer_info's entries */
    260 
    261 	struct buf_ring *br; /* only for TX */
    262 
    263 	kmutex_t ring_mtx;
    264 	char mtx_name[16];
    265 
    266 	union {
    267 		struct {
    268 			struct work enqueue_task;
    269 			struct workqueue *enqueue_tq;
    270 		};
    271 		struct {
    272 			struct work cmpl_task;
    273 			struct workqueue *cmpl_tq;
    274 		};
    275 	};
    276 
    277 	union {
    278 		struct ena_stats_tx tx_stats;
    279 		struct ena_stats_rx rx_stats;
    280 	};
    281 
    282 	int empty_rx_queue;
    283 } __aligned(CACHE_LINE_SIZE);
    284 
    285 struct ena_stats_dev {
    286 	char name[16];
    287 	struct evcnt wd_expired;
    288 	struct evcnt interface_up;
    289 	struct evcnt interface_down;
    290 	struct evcnt admin_q_pause;
    291 };
    292 
    293 struct ena_hw_stats {
    294 	char name[16];
    295 	struct evcnt rx_packets;
    296 	struct evcnt tx_packets;
    297 
    298 	struct evcnt rx_bytes;
    299 	struct evcnt tx_bytes;
    300 
    301 	struct evcnt rx_drops;
    302 };
    303 
    304 /* Board specific private data structure */
    305 struct ena_adapter {
    306 	struct ena_com_dev *ena_dev;
    307 
    308 	/* OS defined structs */
    309 	device_t pdev;
    310         struct ethercom sc_ec;
    311 	struct ifnet *ifp;		/* set to point to sc_ec */
    312 	struct ifmedia	media;
    313 
    314 	/* OS resources */
    315 	kmutex_t global_mtx;
    316 	krwlock_t ioctl_sx;
    317 
    318 	void *sc_ihs[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
    319 	pci_intr_handle_t *sc_intrs;
    320 	int sc_nintrs;
    321 	struct pci_attach_args sc_pa;
    322 
    323 	/* Registers */
    324 	bus_space_handle_t sc_bhandle;
    325 	bus_space_tag_t	sc_btag;
    326 
    327 	/* DMA tag used throughout the driver adapter for Tx and Rx */
    328 	bus_dma_tag_t sc_dmat;
    329 	int dma_width;
    330 
    331 	uint32_t max_mtu;
    332 
    333 	uint16_t max_tx_sgl_size;
    334 	uint16_t max_rx_sgl_size;
    335 
    336 	uint32_t tx_offload_cap;
    337 
    338 	/* Tx fast path data */
    339 	int num_queues;
    340 
    341 	unsigned int tx_ring_size;
    342 	unsigned int rx_ring_size;
    343 
    344 	/* RSS*/
    345 	uint8_t	rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE];
    346 	bool rss_support;
    347 
    348 	uint8_t mac_addr[ETHER_ADDR_LEN];
    349 	/* mdio and phy*/
    350 
    351 	bool link_status;
    352 	bool trigger_reset;
    353 	bool up;
    354 	bool running;
    355 
    356 	/* Queue will represent one TX and one RX ring */
    357 	struct ena_que que[ENA_MAX_NUM_IO_QUEUES]
    358 	    __aligned(CACHE_LINE_SIZE);
    359 
    360 	/* TX */
    361 	struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
    362 	    __aligned(CACHE_LINE_SIZE);
    363 
    364 	/* RX */
    365 	struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
    366 	    __aligned(CACHE_LINE_SIZE);
    367 
    368 	/* Timer service */
    369 	struct callout timer_service;
    370 	sbintime_t keep_alive_timestamp;
    371 	uint32_t next_monitored_tx_qid;
    372 	struct work reset_task;
    373 	struct workqueue *reset_tq;
    374 	int wd_active;
    375 	sbintime_t keep_alive_timeout;
    376 	sbintime_t missing_tx_timeout;
    377 	uint32_t missing_tx_max_queues;
    378 	uint32_t missing_tx_threshold;
    379 
    380 	/* Statistics */
    381 	struct ena_stats_dev dev_stats;
    382 	struct ena_hw_stats hw_stats;
    383 
    384 	enum ena_regs_reset_reason_types reset_reason;
    385 };
    386 
    387 #define	ENA_RING_MTX_LOCK(_ring)	mutex_enter(&(_ring)->ring_mtx)
    388 #define	ENA_RING_MTX_TRYLOCK(_ring)	mutex_tryenter(&(_ring)->ring_mtx)
    389 #define	ENA_RING_MTX_UNLOCK(_ring)	mutex_exit(&(_ring)->ring_mtx)
    390 
    391 static inline int ena_mbuf_count(struct mbuf *mbuf)
    392 {
    393 	int count = 1;
    394 
    395 	while ((mbuf = mbuf->m_next) != NULL)
    396 		++count;
    397 
    398 	return count;
    399 }
    400 
    401 /* provide FreeBSD-compatible macros */
    402 #define	if_getcapenable(ifp)		(ifp)->if_capenable
    403 #define	if_setcapenable(ifp, s)		SET((ifp)->if_capenable, s)
    404 #define if_getcapabilities(ifp)		(ifp)->if_capabilities
    405 #define if_setcapabilities(ifp, s)	SET((ifp)->if_capabilities, s)
    406 #define if_setcapabilitiesbit(ifp, s, c) do {	\
    407 		CLR((ifp)->if_capabilities, c);	\
    408 		SET((ifp)->if_capabilities, s);	\
    409 	} while (0)
    410 #define	if_getsoftc(ifp)		(ifp)->if_softc
    411 #define if_setmtu(ifp, new_mtu)		(ifp)->if_mtu = (new_mtu)
    412 #define if_getdrvflags(ifp)		(ifp)->if_flags
    413 #define if_setdrvflagbits(ifp, s, c)	do {	\
    414 		CLR((ifp)->if_flags, c);	\
    415 		SET((ifp)->if_flags, s);	\
    416 	} while (0)
    417 #define	if_setflags(ifp, s)		SET((ifp)->if_flags, s)
    418 #define if_sethwassistbits(ifp, s, c)	do {		\
    419 		CLR((ifp)->if_csum_flags_rx, c);	\
    420 		SET((ifp)->if_csum_flags_rx, s);	\
    421 	} while (0)
    422 #define if_clearhwassist(ifp)		(ifp)->if_csum_flags_rx = 0
    423 #define if_setbaudrate(ifp, r)		(ifp)->if_baudrate = (r)
    424 #define if_setdev(ifp, dev)		do { } while (0)
    425 #define if_setsoftc(ifp, softc)		(ifp)->if_softc = (softc)
    426 #define if_setinitfn(ifp, initfn)	(ifp)->if_init = (initfn)
    427 #define if_settransmitfn(ifp, txfn)	(ifp)->if_transmit = (txfn)
    428 #define if_setioctlfn(ifp, ioctlfn)	(ifp)->if_ioctl = (ioctlfn)
    429 #define if_setsendqlen(ifp, sqlen)	\
    430 	IFQ_SET_MAXLEN(&(ifp)->if_snd, uimax(sqlen, IFQ_MAXLEN))
    431 #define if_setsendqready(ifp)		IFQ_SET_READY(&(ifp)->if_snd)
    432 #define if_setifheaderlen(ifp, len)	(ifp)->if_hdrlen = (len)
    433 
    434 #define	SBT_1S	((sbintime_t)1 << 32)
    435 #define bintime_clear(a)	((a)->sec = (a)->frac = 0)
    436 #define	bintime_isset(a)	((a)->sec || (a)->frac)
    437 
    438 static __inline sbintime_t
    439 bttosbt(const struct bintime _bt)
    440 {
    441 	return (((sbintime_t)_bt.sec << 32) + (_bt.frac >> 32));
    442 }
    443 
    444 static __inline sbintime_t
    445 getsbinuptime(void)
    446 {
    447 	struct bintime _bt;
    448 
    449 	getbinuptime(&_bt);
    450 	return (bttosbt(_bt));
    451 }
    452 
    453 /* Intentionally non-atomic, it's just unnecessary overhead */
    454 #define counter_u64_add(x, cnt)			(x).ev_count += (cnt)
    455 #define counter_u64_zero(x)			(x).ev_count = 0
    456 #define counter_u64_free(x)			evcnt_detach(&(x))
    457 
    458 #define counter_u64_add_protected(x, cnt)	(x).ev_count += (cnt)
    459 #define counter_enter()				do {} while (0)
    460 #define counter_exit()				do {} while (0)
    461 
    462 /* Misc other constants */
    463 #define	mp_ncpus			ncpu
    464 #define osreldate			__NetBSD_Version__
    465 
    466 /*
    467  * XXX XXX XXX just to make compile, must provide replacement XXX XXX XXX
    468  * Other than that, TODO:
    469  * - decide whether to import <sys/buf_ring.h>
    470  * - recheck the M_CSUM/IPCAP mapping
    471  * - recheck workqueue use - FreeBSD taskqueues might have different semantics
    472  */
    473 #define buf_ring_alloc(a, b, c, d)	(void *)&a
    474 #define drbr_free(ifp, b)		do { } while (0)
    475 #define drbr_flush(ifp, b)		do { } while (0)
    476 #define drbr_advance(ifp, b)		do { } while (0)
    477 #define drbr_putback(ifp, b, m)		do { } while (0)
    478 #define drbr_empty(ifp, b)		false
    479 #define drbr_peek(ifp, b)		NULL
    480 #define drbr_enqueue(ifp, b, m)		0
    481 #define m_getjcl(a, b, c, d)		NULL
    482 #define MJUM16BYTES			MCLBYTES
    483 #define m_append(m, len, cp)		0
    484 #define m_collapse(m, how, maxfrags)	NULL
    485 /* XXX XXX XXX */
    486 
    487 #endif /* !(ENA_H) */
    488