if_epic_pci.c revision 1.32.24.2
1 /* if_epic_pci.c,v 1.32.24.1 2007/11/06 23:28:57 matt Exp */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100) driver. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "if_epic_pci.c,v 1.32.24.1 2007/11/06 23:28:57 matt Exp"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 66 #include <dev/mii/miivar.h> 67 68 #include <dev/ic/smc83c170reg.h> 69 #include <dev/ic/smc83c170var.h> 70 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcidevs.h> 74 75 /* 76 * PCI configuration space registers used by the EPIC. 77 */ 78 #define EPIC_PCI_IOBA 0x10 /* i/o mapped base */ 79 #define EPIC_PCI_MMBA 0x14 /* memory mapped base */ 80 81 struct epic_pci_softc { 82 struct epic_softc sc_epic; /* real EPIC softc */ 83 84 /* PCI-specific goo. */ 85 void *sc_ih; /* interrupt handle */ 86 }; 87 88 static int epic_pci_match(struct device *, struct cfdata *, void *); 89 static void epic_pci_attach(struct device *, struct device *, void *); 90 91 CFATTACH_DECL(epic_pci, sizeof(struct epic_pci_softc), 92 epic_pci_match, epic_pci_attach, NULL, NULL); 93 94 static const struct epic_pci_product { 95 u_int32_t epp_prodid; /* PCI product ID */ 96 const char *epp_name; /* device name */ 97 } epic_pci_products[] = { 98 { PCI_PRODUCT_SMC_83C170, "SMC 83c170 Fast Ethernet" }, 99 { PCI_PRODUCT_SMC_83C175, "SMC 83c175 Fast Ethernet" }, 100 { 0, NULL }, 101 }; 102 103 static const struct epic_pci_product * 104 epic_pci_lookup(const struct pci_attach_args *pa) 105 { 106 const struct epic_pci_product *epp; 107 108 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SMC) 109 return (NULL); 110 111 for (epp = epic_pci_products; epp->epp_name != NULL; epp++) 112 if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid) 113 return (epp); 114 115 return (NULL); 116 } 117 118 static const struct epic_pci_subsys_info { 119 pcireg_t subsysid; 120 int flags; 121 } epic_pci_subsys_info[] = { 122 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa015), /* SMC9432BTX */ 123 EPIC_HAS_BNC }, 124 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa024), /* SMC9432BTX1 */ 125 EPIC_HAS_BNC }, 126 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa016), /* SMC9432FTX */ 127 EPIC_HAS_MII_FIBER | EPIC_DUPLEXLED_ON_694 }, 128 { 0xffffffff, 129 0 } 130 }; 131 132 static const struct epic_pci_subsys_info * 133 epic_pci_subsys_lookup(const struct pci_attach_args *pa) 134 { 135 pci_chipset_tag_t pc = pa->pa_pc; 136 pcireg_t reg; 137 const struct epic_pci_subsys_info *esp; 138 139 reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 140 141 for (esp = epic_pci_subsys_info; esp->subsysid != 0xffffffff; esp++) 142 if (esp->subsysid == reg) 143 return (esp); 144 145 return (NULL); 146 } 147 148 static int 149 epic_pci_match(device_t parent, struct cfdata *match, void *aux) 150 { 151 struct pci_attach_args *pa = aux; 152 153 if (epic_pci_lookup(pa) != NULL) 154 return (1); 155 156 return (0); 157 } 158 159 static void 160 epic_pci_attach(device_t parent, device_t self, void *aux) 161 { 162 struct epic_pci_softc *psc = device_private(self); 163 struct epic_softc *sc = &psc->sc_epic; 164 struct pci_attach_args *pa = aux; 165 pci_chipset_tag_t pc = pa->pa_pc; 166 pci_intr_handle_t ih; 167 const char *intrstr = NULL; 168 const struct epic_pci_product *epp; 169 const struct epic_pci_subsys_info *esp; 170 bus_space_tag_t iot, memt; 171 bus_space_handle_t ioh, memh; 172 int ioh_valid, memh_valid; 173 int error; 174 175 aprint_naive(": Ethernet controller\n"); 176 177 epp = epic_pci_lookup(pa); 178 if (epp == NULL) { 179 printf("\n"); 180 panic("epic_pci_attach: impossible"); 181 } 182 183 aprint_normal(": %s, rev. %d\n", epp->epp_name, 184 PCI_REVISION(pa->pa_class)); 185 186 /* power up chip */ 187 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 188 NULL)) && error != EOPNOTSUPP) { 189 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 190 return; 191 } 192 193 /* 194 * Map the device. 195 */ 196 ioh_valid = (pci_mapreg_map(pa, EPIC_PCI_IOBA, 197 PCI_MAPREG_TYPE_IO, 0, 198 &iot, &ioh, NULL, NULL) == 0); 199 memh_valid = (pci_mapreg_map(pa, EPIC_PCI_MMBA, 200 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 201 &memt, &memh, NULL, NULL) == 0); 202 203 if (memh_valid) { 204 sc->sc_st = memt; 205 sc->sc_sh = memh; 206 } else if (ioh_valid) { 207 sc->sc_st = iot; 208 sc->sc_sh = ioh; 209 } else { 210 aprint_error_dev(&sc->sc_dev, 211 "unable to map device registers\n"); 212 return; 213 } 214 215 sc->sc_dmat = pa->pa_dmat; 216 217 /* Make sure bus mastering is enabled. */ 218 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 219 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 220 PCI_COMMAND_MASTER_ENABLE); 221 222 /* 223 * Map and establish our interrupt. 224 */ 225 if (pci_intr_map(pa, &ih)) { 226 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 227 return; 228 } 229 intrstr = pci_intr_string(pc, ih); 230 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, epic_intr, sc); 231 if (psc->sc_ih == NULL) { 232 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 233 if (intrstr != NULL) 234 aprint_normal(" at %s", intrstr); 235 aprint_normal("\n"); 236 return; 237 } 238 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 239 240 esp = epic_pci_subsys_lookup(pa); 241 if (esp) 242 sc->sc_hwflags = esp->flags; 243 244 /* 245 * Finish off the attach. 246 */ 247 epic_attach(sc); 248 } 249
Indexes created Fri Oct 03 02:09:57 GMT 2025