if_epic_pci.c revision 1.7.12.4
1 /* $NetBSD: if_epic_pci.c,v 1.7.12.4 2000/07/16 20:29:08 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100) driver. 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #ifdef NS 74 #include <netns/ns.h> 75 #include <netns/ns_if.h> 76 #endif 77 78 #include <machine/bus.h> 79 #include <machine/intr.h> 80 81 #include <dev/mii/miivar.h> 82 83 #include <dev/ic/smc83c170reg.h> 84 #include <dev/ic/smc83c170var.h> 85 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcidevs.h> 89 90 /* 91 * PCI configuration space registers used by the EPIC. 92 */ 93 #define EPIC_PCI_IOBA 0x10 /* i/o mapped base */ 94 #define EPIC_PCI_MMBA 0x14 /* memory mapped base */ 95 96 struct epic_pci_softc { 97 struct epic_softc sc_epic; /* real EPIC softc */ 98 99 /* PCI-specific goo. */ 100 void *sc_ih; /* interrupt handle */ 101 }; 102 103 int epic_pci_match __P((struct device *, struct cfdata *, void *)); 104 void epic_pci_attach __P((struct device *, struct device *, void *)); 105 106 struct cfattach epic_pci_ca = { 107 sizeof(struct epic_pci_softc), epic_pci_match, epic_pci_attach, 108 }; 109 110 const struct epic_pci_product { 111 u_int32_t epp_prodid; /* PCI product ID */ 112 const char *epp_name; /* device name */ 113 } epic_pci_products[] = { 114 { PCI_PRODUCT_SMC_83C170, "SMC 83c170 Fast Ethernet" }, 115 { PCI_PRODUCT_SMC_83C175, "SMC 83c175 Fast Ethernet" }, 116 { 0, NULL }, 117 }; 118 119 const struct epic_pci_product *epic_pci_lookup 120 __P((const struct pci_attach_args *)); 121 122 const struct epic_pci_product * 123 epic_pci_lookup(pa) 124 const struct pci_attach_args *pa; 125 { 126 const struct epic_pci_product *epp; 127 128 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SMC) 129 return (NULL); 130 131 for (epp = epic_pci_products; epp->epp_name != NULL; epp++) 132 if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid) 133 return (epp); 134 135 return (NULL); 136 } 137 138 int 139 epic_pci_match(parent, match, aux) 140 struct device *parent; 141 struct cfdata *match; 142 void *aux; 143 { 144 struct pci_attach_args *pa = aux; 145 146 if (epic_pci_lookup(pa) != NULL) 147 return (1); 148 149 return (0); 150 } 151 152 void 153 epic_pci_attach(parent, self, aux) 154 struct device *parent, *self; 155 void *aux; 156 { 157 struct epic_pci_softc *psc = (struct epic_pci_softc *)self; 158 struct epic_softc *sc = &psc->sc_epic; 159 struct pci_attach_args *pa = aux; 160 pci_chipset_tag_t pc = pa->pa_pc; 161 pci_intr_handle_t ih; 162 const char *intrstr = NULL; 163 const struct epic_pci_product *epp; 164 bus_space_tag_t iot, memt; 165 bus_space_handle_t ioh, memh; 166 pcireg_t reg; 167 int pmreg, ioh_valid, memh_valid; 168 169 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 170 reg = pci_conf_read(pc, pa->pa_tag, pmreg + 4); 171 switch (reg & PCI_PMCSR_STATE_MASK) { 172 case PCI_PMCSR_STATE_D1: 173 case PCI_PMCSR_STATE_D2: 174 printf(": waking up from power state D%d\n%s", 175 reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname); 176 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 177 break; 178 case PCI_PMCSR_STATE_D3: 179 /* 180 * IO and MEM are disabled. We can't enable 181 * the card because the BARs might be invalid. 182 */ 183 printf(": unable to wake up from power state D3, " 184 "reboot required.\n"); 185 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 186 return; 187 } 188 } 189 190 /* 191 * Map the device. 192 */ 193 ioh_valid = (pci_mapreg_map(pa, EPIC_PCI_IOBA, 194 PCI_MAPREG_TYPE_IO, 0, 195 &iot, &ioh, NULL, NULL) == 0); 196 memh_valid = (pci_mapreg_map(pa, EPIC_PCI_MMBA, 197 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 198 &memt, &memh, NULL, NULL) == 0); 199 200 if (memh_valid) { 201 sc->sc_st = memt; 202 sc->sc_sh = memh; 203 } else if (ioh_valid) { 204 sc->sc_st = iot; 205 sc->sc_sh = ioh; 206 } else { 207 printf(": unable to map device registers\n"); 208 return; 209 } 210 211 sc->sc_dmat = pa->pa_dmat; 212 213 epp = epic_pci_lookup(pa); 214 if (epp == NULL) { 215 printf("\n"); 216 panic("epic_pci_attach: impossible"); 217 } 218 219 printf(": %s, rev. %d\n", epp->epp_name, PCI_REVISION(pa->pa_class)); 220 221 /* Make sure bus mastering is enabled. */ 222 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 223 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 224 PCI_COMMAND_MASTER_ENABLE); 225 226 /* 227 * Map and establish our interrupt. 228 */ 229 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 230 pa->pa_intrline, &ih)) { 231 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 232 return; 233 } 234 intrstr = pci_intr_string(pc, ih); 235 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, epic_intr, sc); 236 if (psc->sc_ih == NULL) { 237 printf("%s: unable to establish interrupt", 238 sc->sc_dev.dv_xname); 239 if (intrstr != NULL) 240 printf(" at %s", intrstr); 241 printf("\n"); 242 return; 243 } 244 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 245 246 /* 247 * Finish off the attach. 248 */ 249 epic_attach(sc); 250 } 251
Indexes created Fri Oct 03 02:09:57 GMT 2025