if_et.c revision 1.16.2.3
1 /* $NetBSD: if_et.c,v 1.16.2.3 2019/01/26 22:00:07 pgoyette Exp $ */ 2 /* $OpenBSD: if_et.c,v 1.11 2008/06/08 06:18:07 jsg Exp $ */ 3 /* 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa (at) gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: if_et.c,v 1.16.2.3 2019/01/26 22:00:07 pgoyette Exp $"); 41 42 #include "opt_inet.h" 43 #include "vlan.h" 44 45 #include <sys/param.h> 46 #include <sys/endian.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/sockio.h> 50 #include <sys/mbuf.h> 51 #include <sys/queue.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/socket.h> 56 57 #include <sys/bus.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 #include <net/if_arp.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #include <net/bpf.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcidevs.h> 81 82 #include <dev/pci/if_etreg.h> 83 84 int et_match(device_t, cfdata_t, void *); 85 void et_attach(device_t, device_t, void *); 86 int et_detach(device_t, int flags); 87 int et_shutdown(device_t); 88 89 int et_miibus_readreg(device_t, int, int, uint16_t *); 90 int et_miibus_writereg(device_t, int, int, uint16_t); 91 void et_miibus_statchg(struct ifnet *); 92 93 int et_init(struct ifnet *ifp); 94 int et_ioctl(struct ifnet *, u_long, void *); 95 void et_start(struct ifnet *); 96 void et_watchdog(struct ifnet *); 97 98 int et_intr(void *); 99 void et_enable_intrs(struct et_softc *, uint32_t); 100 void et_disable_intrs(struct et_softc *); 101 void et_rxeof(struct et_softc *); 102 void et_txeof(struct et_softc *); 103 void et_txtick(void *); 104 105 int et_dma_alloc(struct et_softc *); 106 void et_dma_free(struct et_softc *); 107 int et_dma_mem_create(struct et_softc *, bus_size_t, 108 void **, bus_addr_t *, bus_dmamap_t *, bus_dma_segment_t *); 109 void et_dma_mem_destroy(struct et_softc *, void *, bus_dmamap_t); 110 int et_dma_mbuf_create(struct et_softc *); 111 void et_dma_mbuf_destroy(struct et_softc *, int, const int[]); 112 113 int et_init_tx_ring(struct et_softc *); 114 int et_init_rx_ring(struct et_softc *); 115 void et_free_tx_ring(struct et_softc *); 116 void et_free_rx_ring(struct et_softc *); 117 int et_encap(struct et_softc *, struct mbuf **); 118 int et_newbuf(struct et_rxbuf_data *, int, int, int); 119 int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 120 int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 121 122 void et_stop(struct et_softc *); 123 int et_chip_init(struct et_softc *); 124 void et_chip_attach(struct et_softc *); 125 void et_init_mac(struct et_softc *); 126 void et_init_rxmac(struct et_softc *); 127 void et_init_txmac(struct et_softc *); 128 int et_init_rxdma(struct et_softc *); 129 int et_init_txdma(struct et_softc *); 130 int et_start_rxdma(struct et_softc *); 131 int et_start_txdma(struct et_softc *); 132 int et_stop_rxdma(struct et_softc *); 133 int et_stop_txdma(struct et_softc *); 134 int et_enable_txrx(struct et_softc *); 135 void et_reset(struct et_softc *); 136 int et_bus_config(struct et_softc *); 137 void et_get_eaddr(struct et_softc *, uint8_t[]); 138 void et_setmulti(struct et_softc *); 139 void et_tick(void *); 140 141 static int et_rx_intr_npkts = 32; 142 static int et_rx_intr_delay = 20; /* x10 usec */ 143 static int et_tx_intr_nsegs = 128; 144 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 145 146 struct et_bsize { 147 int bufsize; 148 et_newbuf_t newbuf; 149 }; 150 151 static const struct et_bsize et_bufsize[ET_RX_NRING] = { 152 { .bufsize = 0, .newbuf = et_newbuf_hdr }, 153 { .bufsize = 0, .newbuf = et_newbuf_cluster }, 154 }; 155 156 const struct et_product { 157 pci_vendor_id_t vendor; 158 pci_product_id_t product; 159 } et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310 }, 161 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1301 } 162 }; 163 164 CFATTACH_DECL_NEW(et, sizeof(struct et_softc), et_match, et_attach, et_detach, 165 NULL); 166 167 int 168 et_match(device_t dev, cfdata_t match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 const struct et_product *ep; 172 int i; 173 174 for (i = 0; i < __arraycount(et_devices); i++) { 175 ep = &et_devices[i]; 176 if (PCI_VENDOR(pa->pa_id) == ep->vendor && 177 PCI_PRODUCT(pa->pa_id) == ep->product) 178 return 1; 179 } 180 return 0; 181 } 182 183 void 184 et_attach(device_t parent, device_t self, void *aux) 185 { 186 struct et_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 pci_intr_handle_t ih; 190 const char *intrstr; 191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 192 pcireg_t memtype; 193 int error; 194 char intrbuf[PCI_INTRSTR_LEN]; 195 196 pci_aprint_devinfo(pa, "Ethernet controller"); 197 198 sc->sc_dev = self; 199 200 /* 201 * Initialize tunables 202 */ 203 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 204 sc->sc_rx_intr_delay = et_rx_intr_delay; 205 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 206 sc->sc_timer = et_timer; 207 208 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ET_PCIR_BAR); 209 if (pci_mapreg_map(pa, ET_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 210 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 211 aprint_error_dev(self, "could not map mem space\n"); 212 return; 213 } 214 215 if (pci_intr_map(pa, &ih) != 0) { 216 aprint_error_dev(self, "could not map interrupt\n"); 217 goto fail; 218 } 219 220 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 221 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, et_intr, 222 sc, device_xname(self)); 223 if (sc->sc_irq_handle == NULL) { 224 aprint_error_dev(self, "could not establish interrupt"); 225 if (intrstr != NULL) 226 aprint_error(" at %s", intrstr); 227 aprint_error("\n"); 228 goto fail; 229 } 230 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 231 232 sc->sc_dmat = pa->pa_dmat; 233 sc->sc_pct = pa->pa_pc; 234 sc->sc_pcitag = pa->pa_tag; 235 236 error = et_bus_config(sc); 237 if (error) 238 goto fail; 239 240 et_get_eaddr(sc, sc->sc_enaddr); 241 242 aprint_normal_dev(self, "Ethernet address %s\n", 243 ether_sprintf(sc->sc_enaddr)); 244 245 CSR_WRITE_4(sc, ET_PM, 246 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 247 248 et_reset(sc); 249 250 et_disable_intrs(sc); 251 252 error = et_dma_alloc(sc); 253 if (error) 254 goto fail; 255 256 ifp->if_softc = sc; 257 ifp->if_mtu = ETHERMTU; 258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 259 ifp->if_init = et_init; 260 ifp->if_ioctl = et_ioctl; 261 ifp->if_start = et_start; 262 ifp->if_watchdog = et_watchdog; 263 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 264 IFQ_SET_READY(&ifp->if_snd); 265 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 266 267 et_chip_attach(sc); 268 269 sc->sc_miibus.mii_ifp = ifp; 270 sc->sc_miibus.mii_readreg = et_miibus_readreg; 271 sc->sc_miibus.mii_writereg = et_miibus_writereg; 272 sc->sc_miibus.mii_statchg = et_miibus_statchg; 273 274 sc->sc_ethercom.ec_mii = &sc->sc_miibus; 275 ifmedia_init(&sc->sc_miibus.mii_media, 0, ether_mediachange, 276 ether_mediastatus); 277 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 278 MII_OFFSET_ANY, 0); 279 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 280 aprint_error_dev(self, "no PHY found!\n"); 281 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 282 0, NULL); 283 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 284 } else 285 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 286 287 if_attach(ifp); 288 if_deferred_start_init(ifp, NULL); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 callout_init(&sc->sc_tick, 0); 292 callout_setfunc(&sc->sc_tick, et_tick, sc); 293 callout_init(&sc->sc_txtick, 0); 294 callout_setfunc(&sc->sc_txtick, et_txtick, sc); 295 296 if (pmf_device_register(self, NULL, NULL)) 297 pmf_class_network_register(self, ifp); 298 else 299 aprint_error_dev(self, "couldn't establish power handler\n"); 300 301 return; 302 303 fail: 304 et_dma_free(sc); 305 if (sc->sc_irq_handle != NULL) { 306 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 307 sc->sc_irq_handle = NULL; 308 } 309 if (sc->sc_mem_size) { 310 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 311 sc->sc_mem_size = 0; 312 } 313 } 314 315 int 316 et_detach(device_t self, int flags) 317 { 318 struct et_softc *sc = device_private(self); 319 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 320 int s; 321 322 pmf_device_deregister(self); 323 s = splnet(); 324 et_stop(sc); 325 splx(s); 326 327 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 328 329 /* Delete all remaining media. */ 330 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 331 332 ether_ifdetach(ifp); 333 if_detach(ifp); 334 et_dma_free(sc); 335 336 if (sc->sc_irq_handle != NULL) { 337 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 338 sc->sc_irq_handle = NULL; 339 } 340 341 if (sc->sc_mem_size) { 342 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 343 sc->sc_mem_size = 0; 344 } 345 346 return 0; 347 } 348 349 int 350 et_shutdown(device_t self) 351 { 352 struct et_softc *sc = device_private(self); 353 int s; 354 355 s = splnet(); 356 et_stop(sc); 357 splx(s); 358 359 return 0; 360 } 361 362 int 363 et_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 364 { 365 struct et_softc *sc = device_private(dev); 366 uint32_t data; 367 int i, ret; 368 369 /* Stop any pending operations */ 370 CSR_WRITE_4(sc, ET_MII_CMD, 0); 371 372 data = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 373 __SHIFTIN(reg, ET_MII_ADDR_REG); 374 CSR_WRITE_4(sc, ET_MII_ADDR, data); 375 376 /* Start reading */ 377 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 378 379 #define NRETRY 50 380 381 for (i = 0; i < NRETRY; ++i) { 382 data = CSR_READ_4(sc, ET_MII_IND); 383 if ((data & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 384 break; 385 DELAY(50); 386 } 387 if (i == NRETRY) { 388 aprint_error_dev(sc->sc_dev, "read phy %d, reg %d timed out\n", 389 phy, reg); 390 ret = ETIMEDOUT; 391 goto back; 392 } 393 394 #undef NRETRY 395 396 data = CSR_READ_4(sc, ET_MII_STAT); 397 *val = __SHIFTOUT(data, ET_MII_STAT_VALUE); 398 ret = 0; 399 400 back: 401 /* Make sure that the current operation is stopped */ 402 CSR_WRITE_4(sc, ET_MII_CMD, 0); 403 return ret; 404 } 405 406 int 407 et_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 408 { 409 struct et_softc *sc = device_private(dev); 410 uint32_t data; 411 uint16_t tmp; 412 int rv = 0; 413 int i; 414 415 /* Stop any pending operations */ 416 CSR_WRITE_4(sc, ET_MII_CMD, 0); 417 418 data = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 419 __SHIFTIN(reg, ET_MII_ADDR_REG); 420 CSR_WRITE_4(sc, ET_MII_ADDR, data); 421 422 /* Start writing */ 423 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val, ET_MII_CTRL_VALUE)); 424 425 #define NRETRY 100 426 427 for (i = 0; i < NRETRY; ++i) { 428 data = CSR_READ_4(sc, ET_MII_IND); 429 if ((data & ET_MII_IND_BUSY) == 0) 430 break; 431 DELAY(50); 432 } 433 if (i == NRETRY) { 434 aprint_error_dev(sc->sc_dev, "write phy %d, reg %d timed out\n", 435 phy, reg); 436 et_miibus_readreg(dev, phy, reg, &tmp); 437 rv = ETIMEDOUT; 438 } 439 440 #undef NRETRY 441 442 /* Make sure that the current operation is stopped */ 443 CSR_WRITE_4(sc, ET_MII_CMD, 0); 444 445 return rv; 446 } 447 448 void 449 et_miibus_statchg(struct ifnet *ifp) 450 { 451 struct et_softc *sc = ifp->if_softc; 452 struct mii_data *mii = &sc->sc_miibus; 453 uint32_t cfg2, ctrl; 454 455 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 456 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 457 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 458 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 459 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 460 461 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 462 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 463 464 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 465 cfg2 |= ET_MAC_CFG2_MODE_GMII; 466 } else { 467 cfg2 |= ET_MAC_CFG2_MODE_MII; 468 ctrl |= ET_MAC_CTRL_MODE_MII; 469 } 470 471 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 472 cfg2 |= ET_MAC_CFG2_FDX; 473 else 474 ctrl |= ET_MAC_CTRL_GHDX; 475 476 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 477 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 478 } 479 480 void 481 et_stop(struct et_softc *sc) 482 { 483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 484 485 callout_stop(&sc->sc_tick); 486 callout_stop(&sc->sc_txtick); 487 488 et_stop_rxdma(sc); 489 et_stop_txdma(sc); 490 491 et_disable_intrs(sc); 492 493 et_free_tx_ring(sc); 494 et_free_rx_ring(sc); 495 496 et_reset(sc); 497 498 sc->sc_tx = 0; 499 sc->sc_tx_intr = 0; 500 501 ifp->if_timer = 0; 502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 503 } 504 505 int 506 et_bus_config(struct et_softc *sc) 507 { 508 uint32_t val; //, max_plsz; 509 // uint16_t ack_latency, replay_timer; 510 511 /* 512 * Test whether EEPROM is valid 513 * NOTE: Read twice to get the correct value 514 */ 515 pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 516 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 517 518 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 519 aprint_error_dev(sc->sc_dev, "EEPROM status error 0x%02x\n", val); 520 return ENXIO; 521 } 522 523 /* TODO: LED */ 524 #if 0 525 /* 526 * Configure ACK latency and replay timer according to 527 * max playload size 528 */ 529 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CAPS); 530 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 531 532 switch (max_plsz) { 533 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 534 ack_latency = ET_PCIV_ACK_LATENCY_128; 535 replay_timer = ET_PCIV_REPLAY_TIMER_128; 536 break; 537 538 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 539 ack_latency = ET_PCIV_ACK_LATENCY_256; 540 replay_timer = ET_PCIV_REPLAY_TIMER_256; 541 break; 542 543 default: 544 ack_latency = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 545 ET_PCIR_ACK_LATENCY) >> 16; 546 replay_timer = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 547 ET_PCIR_REPLAY_TIMER) >> 16; 548 aprint_normal_dev(sc->sc_dev, "ack latency %u, replay timer %u\n", 549 ack_latency, replay_timer); 550 break; 551 } 552 if (ack_latency != 0) { 553 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 554 ET_PCIR_ACK_LATENCY, ack_latency << 16); 555 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 556 ET_PCIR_REPLAY_TIMER, replay_timer << 16); 557 } 558 559 /* 560 * Set L0s and L1 latency timer to 2us 561 */ 562 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 563 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_L0S_L1_LATENCY, 564 val << 24); 565 566 /* 567 * Set max read request size to 2048 bytes 568 */ 569 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 570 ET_PCIR_DEVICE_CTRL) >> 16; 571 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 572 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 573 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CTRL, 574 val << 16); 575 #endif 576 577 return 0; 578 } 579 580 void 581 et_get_eaddr(struct et_softc *sc, uint8_t eaddr[]) 582 { 583 uint32_t r; 584 585 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_LO); 586 eaddr[0] = r & 0xff; 587 eaddr[1] = (r >> 8) & 0xff; 588 eaddr[2] = (r >> 16) & 0xff; 589 eaddr[3] = (r >> 24) & 0xff; 590 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_HI); 591 eaddr[4] = r & 0xff; 592 eaddr[5] = (r >> 8) & 0xff; 593 } 594 595 void 596 et_reset(struct et_softc *sc) 597 { 598 CSR_WRITE_4(sc, ET_MAC_CFG1, 599 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 600 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 601 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 602 603 CSR_WRITE_4(sc, ET_SWRST, 604 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 605 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 606 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 607 608 CSR_WRITE_4(sc, ET_MAC_CFG1, 609 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 610 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 611 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 612 } 613 614 void 615 et_disable_intrs(struct et_softc *sc) 616 { 617 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 618 } 619 620 void 621 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 622 { 623 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 624 } 625 626 int 627 et_dma_alloc(struct et_softc *sc) 628 { 629 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 630 struct et_txstatus_data *txsd = &sc->sc_tx_status; 631 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 632 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 633 int i, error; 634 635 /* 636 * Create TX ring DMA stuffs 637 */ 638 error = et_dma_mem_create(sc, ET_TX_RING_SIZE, 639 (void **)&tx_ring->tr_desc, &tx_ring->tr_paddr, &tx_ring->tr_dmap, 640 &tx_ring->tr_seg); 641 if (error) { 642 aprint_error_dev(sc->sc_dev, "can't create TX ring DMA stuffs\n"); 643 return error; 644 } 645 646 /* 647 * Create TX status DMA stuffs 648 */ 649 error = et_dma_mem_create(sc, sizeof(uint32_t), 650 (void **)&txsd->txsd_status, 651 &txsd->txsd_paddr, &txsd->txsd_dmap, &txsd->txsd_seg); 652 if (error) { 653 aprint_error_dev(sc->sc_dev, "can't create TX status DMA stuffs\n"); 654 return error; 655 } 656 657 /* 658 * Create DMA stuffs for RX rings 659 */ 660 for (i = 0; i < ET_RX_NRING; ++i) { 661 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 662 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 663 664 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 665 666 error = et_dma_mem_create(sc, ET_RX_RING_SIZE, 667 (void **)&rx_ring->rr_desc, 668 &rx_ring->rr_paddr, &rx_ring->rr_dmap, &rx_ring->rr_seg); 669 if (error) { 670 aprint_error_dev(sc->sc_dev, "can't create DMA stuffs for " 671 "the %d RX ring\n", i); 672 return error; 673 } 674 rx_ring->rr_posreg = rx_ring_posreg[i]; 675 } 676 677 /* 678 * Create RX stat ring DMA stuffs 679 */ 680 error = et_dma_mem_create(sc, ET_RXSTAT_RING_SIZE, 681 (void **)&rxst_ring->rsr_stat, 682 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap, &rxst_ring->rsr_seg); 683 if (error) { 684 aprint_error_dev(sc->sc_dev, "can't create RX stat ring DMA stuffs\n"); 685 return error; 686 } 687 688 /* 689 * Create RX status DMA stuffs 690 */ 691 error = et_dma_mem_create(sc, sizeof(struct et_rxstatus), 692 (void **)&rxsd->rxsd_status, 693 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap, &rxsd->rxsd_seg); 694 if (error) { 695 aprint_error_dev(sc->sc_dev, "can't create RX status DMA stuffs\n"); 696 return error; 697 } 698 699 /* 700 * Create mbuf DMA stuffs 701 */ 702 error = et_dma_mbuf_create(sc); 703 if (error) 704 return error; 705 706 return 0; 707 } 708 709 void 710 et_dma_free(struct et_softc *sc) 711 { 712 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 713 struct et_txstatus_data *txsd = &sc->sc_tx_status; 714 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 715 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 716 int i, rx_done[ET_RX_NRING]; 717 718 /* 719 * Destroy TX ring DMA stuffs 720 */ 721 et_dma_mem_destroy(sc, tx_ring->tr_desc, tx_ring->tr_dmap); 722 723 /* 724 * Destroy TX status DMA stuffs 725 */ 726 et_dma_mem_destroy(sc, txsd->txsd_status, txsd->txsd_dmap); 727 728 /* 729 * Destroy DMA stuffs for RX rings 730 */ 731 for (i = 0; i < ET_RX_NRING; ++i) { 732 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 733 734 et_dma_mem_destroy(sc, rx_ring->rr_desc, rx_ring->rr_dmap); 735 } 736 737 /* 738 * Destroy RX stat ring DMA stuffs 739 */ 740 et_dma_mem_destroy(sc, rxst_ring->rsr_stat, rxst_ring->rsr_dmap); 741 742 /* 743 * Destroy RX status DMA stuffs 744 */ 745 et_dma_mem_destroy(sc, rxsd->rxsd_status, rxsd->rxsd_dmap); 746 747 /* 748 * Destroy mbuf DMA stuffs 749 */ 750 for (i = 0; i < ET_RX_NRING; ++i) 751 rx_done[i] = ET_RX_NDESC; 752 et_dma_mbuf_destroy(sc, ET_TX_NDESC, rx_done); 753 } 754 755 int 756 et_dma_mbuf_create(struct et_softc *sc) 757 { 758 struct et_txbuf_data *tbd = &sc->sc_tx_data; 759 int i, error, rx_done[ET_RX_NRING]; 760 761 /* 762 * Create spare DMA map for RX mbufs 763 */ 764 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 765 BUS_DMA_NOWAIT, &sc->sc_mbuf_tmp_dmap); 766 if (error) { 767 aprint_error_dev(sc->sc_dev, "can't create spare mbuf DMA map\n"); 768 return error; 769 } 770 771 /* 772 * Create DMA maps for RX mbufs 773 */ 774 bzero(rx_done, sizeof(rx_done)); 775 for (i = 0; i < ET_RX_NRING; ++i) { 776 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 777 int j; 778 779 for (j = 0; j < ET_RX_NDESC; ++j) { 780 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 781 MCLBYTES, 0, BUS_DMA_NOWAIT, 782 &rbd->rbd_buf[j].rb_dmap); 783 if (error) { 784 aprint_error_dev(sc->sc_dev, "can't create %d RX mbuf " 785 "for %d RX ring\n", j, i); 786 rx_done[i] = j; 787 et_dma_mbuf_destroy(sc, 0, rx_done); 788 return error; 789 } 790 } 791 rx_done[i] = ET_RX_NDESC; 792 793 rbd->rbd_softc = sc; 794 rbd->rbd_ring = &sc->sc_rx_ring[i]; 795 } 796 797 /* 798 * Create DMA maps for TX mbufs 799 */ 800 for (i = 0; i < ET_TX_NDESC; ++i) { 801 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 802 0, BUS_DMA_NOWAIT, &tbd->tbd_buf[i].tb_dmap); 803 if (error) { 804 aprint_error_dev(sc->sc_dev, "can't create %d TX mbuf " 805 "DMA map\n", i); 806 et_dma_mbuf_destroy(sc, i, rx_done); 807 return error; 808 } 809 } 810 811 return 0; 812 } 813 814 void 815 et_dma_mbuf_destroy(struct et_softc *sc, int tx_done, const int rx_done[]) 816 { 817 struct et_txbuf_data *tbd = &sc->sc_tx_data; 818 int i; 819 820 /* 821 * Destroy DMA maps for RX mbufs 822 */ 823 for (i = 0; i < ET_RX_NRING; ++i) { 824 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 825 int j; 826 827 for (j = 0; j < rx_done[i]; ++j) { 828 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 829 830 KASSERTMSG(rb->rb_mbuf == NULL, 831 "RX mbuf in %d RX ring is not freed yet\n", i); 832 bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); 833 } 834 } 835 836 /* 837 * Destroy DMA maps for TX mbufs 838 */ 839 for (i = 0; i < tx_done; ++i) { 840 struct et_txbuf *tb = &tbd->tbd_buf[i]; 841 842 KASSERTMSG(tb->tb_mbuf == NULL, "TX mbuf is not freed yet\n"); 843 bus_dmamap_destroy(sc->sc_dmat, tb->tb_dmap); 844 } 845 846 /* 847 * Destroy spare mbuf DMA map 848 */ 849 bus_dmamap_destroy(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 850 } 851 852 int 853 et_dma_mem_create(struct et_softc *sc, bus_size_t size, 854 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap, bus_dma_segment_t *seg) 855 { 856 int error, nsegs; 857 858 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 859 dmap); 860 if (error) { 861 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 862 return error; 863 } 864 865 error = bus_dmamem_alloc(sc->sc_dmat, size, ET_ALIGN, 0, seg, 866 1, &nsegs, BUS_DMA_WAITOK); 867 if (error) { 868 aprint_error_dev(sc->sc_dev, "can't allocate DMA mem\n"); 869 return error; 870 } 871 872 error = bus_dmamem_map(sc->sc_dmat, seg, nsegs, 873 size, (void **)addr, BUS_DMA_NOWAIT); 874 if (error) { 875 aprint_error_dev(sc->sc_dev, "can't map DMA mem\n"); 876 return (error); 877 } 878 879 error = bus_dmamap_load(sc->sc_dmat, *dmap, *addr, size, NULL, 880 BUS_DMA_WAITOK); 881 if (error) { 882 aprint_error_dev(sc->sc_dev, "can't load DMA mem\n"); 883 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)addr, 1); 884 return error; 885 } 886 887 memset(*addr, 0, size); 888 889 *paddr = (*dmap)->dm_segs[0].ds_addr; 890 891 return 0; 892 } 893 894 void 895 et_dma_mem_destroy(struct et_softc *sc, void *addr, bus_dmamap_t dmap) 896 { 897 bus_dmamap_unload(sc->sc_dmat, dmap); 898 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&addr, 1); 899 } 900 901 void 902 et_chip_attach(struct et_softc *sc) 903 { 904 uint32_t val; 905 906 /* 907 * Perform minimal initialization 908 */ 909 910 /* Disable loopback */ 911 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 912 913 /* Reset MAC */ 914 CSR_WRITE_4(sc, ET_MAC_CFG1, 915 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 916 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 917 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 918 919 /* 920 * Setup half duplex mode 921 */ 922 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 923 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 924 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 925 ET_MAC_HDX_EXC_DEFER; 926 CSR_WRITE_4(sc, ET_MAC_HDX, val); 927 928 /* Clear MAC control */ 929 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 930 931 /* Reset MII */ 932 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 933 934 /* Bring MAC out of reset state */ 935 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 936 937 /* Enable memory controllers */ 938 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 939 } 940 941 int 942 et_intr(void *xsc) 943 { 944 struct et_softc *sc = xsc; 945 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 946 uint32_t intrs; 947 948 if ((ifp->if_flags & IFF_RUNNING) == 0) 949 return (0); 950 951 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 952 if (intrs == 0 || intrs == 0xffffffff) 953 return (0); 954 955 et_disable_intrs(sc); 956 intrs &= ET_INTRS; 957 if (intrs == 0) /* Not interested */ 958 goto back; 959 960 if (intrs & ET_INTR_RXEOF) 961 et_rxeof(sc); 962 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 963 et_txeof(sc); 964 if (intrs & ET_INTR_TIMER) 965 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 966 back: 967 et_enable_intrs(sc, ET_INTRS); 968 969 return (1); 970 } 971 972 int 973 et_init(struct ifnet *ifp) 974 { 975 struct et_softc *sc = ifp->if_softc; 976 int error, i, s; 977 978 if (ifp->if_flags & IFF_RUNNING) 979 return 0; 980 981 s = splnet(); 982 983 et_stop(sc); 984 985 for (i = 0; i < ET_RX_NRING; ++i) { 986 sc->sc_rx_data[i].rbd_bufsize = et_bufsize[i].bufsize; 987 sc->sc_rx_data[i].rbd_newbuf = et_bufsize[i].newbuf; 988 } 989 990 error = et_init_tx_ring(sc); 991 if (error) 992 goto back; 993 994 error = et_init_rx_ring(sc); 995 if (error) 996 goto back; 997 998 error = et_chip_init(sc); 999 if (error) 1000 goto back; 1001 1002 error = et_enable_txrx(sc); 1003 if (error) 1004 goto back; 1005 1006 error = et_start_rxdma(sc); 1007 if (error) 1008 goto back; 1009 1010 error = et_start_txdma(sc); 1011 if (error) 1012 goto back; 1013 1014 et_enable_intrs(sc, ET_INTRS); 1015 1016 callout_schedule(&sc->sc_tick, hz); 1017 1018 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1019 1020 ifp->if_flags |= IFF_RUNNING; 1021 ifp->if_flags &= ~IFF_OACTIVE; 1022 back: 1023 if (error) 1024 et_stop(sc); 1025 1026 splx(s); 1027 1028 return (0); 1029 } 1030 1031 int 1032 et_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1033 { 1034 struct et_softc *sc = ifp->if_softc; 1035 struct ifreq *ifr = (struct ifreq *)data; 1036 int s, error = 0; 1037 1038 s = splnet(); 1039 1040 switch (cmd) { 1041 case SIOCSIFFLAGS: 1042 if (ifp->if_flags & IFF_UP) { 1043 /* 1044 * If only the PROMISC or ALLMULTI flag changes, then 1045 * don't do a full re-init of the chip, just update 1046 * the Rx filter. 1047 */ 1048 if ((ifp->if_flags & IFF_RUNNING) && 1049 ((ifp->if_flags ^ sc->sc_if_flags) & 1050 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1051 et_setmulti(sc); 1052 } else { 1053 if (!(ifp->if_flags & IFF_RUNNING)) 1054 et_init(ifp); 1055 } 1056 } else { 1057 if (ifp->if_flags & IFF_RUNNING) 1058 et_stop(sc); 1059 } 1060 sc->sc_if_flags = ifp->if_flags; 1061 break; 1062 case SIOCSIFMEDIA: 1063 case SIOCGIFMEDIA: 1064 error = ifmedia_ioctl(ifp, ifr, &sc->sc_miibus.mii_media, cmd); 1065 break; 1066 default: 1067 error = ether_ioctl(ifp, cmd, data); 1068 if (error == ENETRESET) { 1069 if (ifp->if_flags & IFF_RUNNING) 1070 et_setmulti(sc); 1071 error = 0; 1072 } 1073 break; 1074 1075 } 1076 1077 splx(s); 1078 1079 return error; 1080 } 1081 1082 void 1083 et_start(struct ifnet *ifp) 1084 { 1085 struct et_softc *sc = ifp->if_softc; 1086 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1087 int trans; 1088 struct mbuf *m; 1089 1090 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1091 return; 1092 1093 trans = 0; 1094 for (;;) { 1095 IFQ_DEQUEUE(&ifp->if_snd, m); 1096 if (m == NULL) 1097 break; 1098 1099 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1100 ifp->if_flags |= IFF_OACTIVE; 1101 break; 1102 } 1103 1104 if (et_encap(sc, &m)) { 1105 ifp->if_oerrors++; 1106 ifp->if_flags |= IFF_OACTIVE; 1107 break; 1108 } 1109 1110 trans = 1; 1111 1112 bpf_mtap(ifp, m, BPF_D_OUT); 1113 } 1114 1115 if (trans) { 1116 callout_schedule(&sc->sc_txtick, hz); 1117 ifp->if_timer = 5; 1118 } 1119 } 1120 1121 void 1122 et_watchdog(struct ifnet *ifp) 1123 { 1124 struct et_softc *sc = ifp->if_softc; 1125 aprint_error_dev(sc->sc_dev, "watchdog timed out\n"); 1126 1127 ifp->if_flags &= ~IFF_RUNNING; 1128 et_init(ifp); 1129 et_start(ifp); 1130 } 1131 1132 int 1133 et_stop_rxdma(struct et_softc *sc) 1134 { 1135 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1136 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1137 1138 DELAY(5); 1139 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1140 aprint_error_dev(sc->sc_dev, "can't stop RX DMA engine\n"); 1141 return ETIMEDOUT; 1142 } 1143 return 0; 1144 } 1145 1146 int 1147 et_stop_txdma(struct et_softc *sc) 1148 { 1149 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1150 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1151 return 0; 1152 } 1153 1154 void 1155 et_free_tx_ring(struct et_softc *sc) 1156 { 1157 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1158 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1159 int i; 1160 1161 for (i = 0; i < ET_TX_NDESC; ++i) { 1162 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1163 1164 if (tb->tb_mbuf != NULL) { 1165 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1166 m_freem(tb->tb_mbuf); 1167 tb->tb_mbuf = NULL; 1168 } 1169 } 1170 1171 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1172 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1173 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1174 } 1175 1176 void 1177 et_free_rx_ring(struct et_softc *sc) 1178 { 1179 int n; 1180 1181 for (n = 0; n < ET_RX_NRING; ++n) { 1182 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1183 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1184 int i; 1185 1186 for (i = 0; i < ET_RX_NDESC; ++i) { 1187 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1188 1189 if (rb->rb_mbuf != NULL) { 1190 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 1191 m_freem(rb->rb_mbuf); 1192 rb->rb_mbuf = NULL; 1193 } 1194 } 1195 1196 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1197 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 1198 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1199 } 1200 } 1201 1202 void 1203 et_setmulti(struct et_softc *sc) 1204 { 1205 struct ethercom *ec = &sc->sc_ethercom; 1206 struct ifnet *ifp = &ec->ec_if; 1207 uint32_t hash[4] = { 0, 0, 0, 0 }; 1208 uint32_t rxmac_ctrl, pktfilt; 1209 struct ether_multi *enm; 1210 struct ether_multistep step; 1211 uint8_t addr[ETHER_ADDR_LEN]; 1212 int i, count; 1213 1214 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1215 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1216 1217 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1218 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1219 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1220 goto back; 1221 } 1222 1223 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1224 1225 count = 0; 1226 ETHER_FIRST_MULTI(step, ec, enm); 1227 while (enm != NULL) { 1228 uint32_t *hp, h; 1229 1230 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1231 addr[i] &= enm->enm_addrlo[i]; 1232 } 1233 1234 h = ether_crc32_be(addr, ETHER_ADDR_LEN); 1235 h = (h & 0x3f800000) >> 23; 1236 1237 hp = &hash[0]; 1238 if (h >= 32 && h < 64) { 1239 h -= 32; 1240 hp = &hash[1]; 1241 } else if (h >= 64 && h < 96) { 1242 h -= 64; 1243 hp = &hash[2]; 1244 } else if (h >= 96) { 1245 h -= 96; 1246 hp = &hash[3]; 1247 } 1248 *hp |= (1 << h); 1249 1250 ++count; 1251 ETHER_NEXT_MULTI(step, enm); 1252 } 1253 1254 for (i = 0; i < 4; ++i) 1255 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1256 1257 if (count > 0) 1258 pktfilt |= ET_PKTFILT_MCAST; 1259 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1260 back: 1261 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1262 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1263 } 1264 1265 int 1266 et_chip_init(struct et_softc *sc) 1267 { 1268 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1269 uint32_t rxq_end; 1270 int error; 1271 1272 /* 1273 * Split internal memory between TX and RX according to MTU 1274 */ 1275 if (ifp->if_mtu < 2048) 1276 rxq_end = 0x2bc; 1277 else if (ifp->if_mtu < 8192) 1278 rxq_end = 0x1ff; 1279 else 1280 rxq_end = 0x1b3; 1281 CSR_WRITE_4(sc, ET_RXQ_START, 0); 1282 CSR_WRITE_4(sc, ET_RXQ_END, rxq_end); 1283 CSR_WRITE_4(sc, ET_TXQ_START, rxq_end + 1); 1284 CSR_WRITE_4(sc, ET_TXQ_END, ET_INTERN_MEM_END); 1285 1286 /* No loopback */ 1287 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1288 1289 /* Clear MSI configure */ 1290 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1291 1292 /* Disable timer */ 1293 CSR_WRITE_4(sc, ET_TIMER, 0); 1294 1295 /* Initialize MAC */ 1296 et_init_mac(sc); 1297 1298 /* Enable memory controllers */ 1299 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1300 1301 /* Initialize RX MAC */ 1302 et_init_rxmac(sc); 1303 1304 /* Initialize TX MAC */ 1305 et_init_txmac(sc); 1306 1307 /* Initialize RX DMA engine */ 1308 error = et_init_rxdma(sc); 1309 if (error) 1310 return error; 1311 1312 /* Initialize TX DMA engine */ 1313 error = et_init_txdma(sc); 1314 if (error) 1315 return error; 1316 1317 return 0; 1318 } 1319 1320 int 1321 et_init_tx_ring(struct et_softc *sc) 1322 { 1323 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1324 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1325 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1326 1327 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1328 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1329 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1330 1331 tbd->tbd_start_index = 0; 1332 tbd->tbd_start_wrap = 0; 1333 tbd->tbd_used = 0; 1334 1335 bzero(txsd->txsd_status, sizeof(uint32_t)); 1336 bus_dmamap_sync(sc->sc_dmat, txsd->txsd_dmap, 0, 1337 txsd->txsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1338 return 0; 1339 } 1340 1341 int 1342 et_init_rx_ring(struct et_softc *sc) 1343 { 1344 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1345 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1346 int n; 1347 1348 for (n = 0; n < ET_RX_NRING; ++n) { 1349 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1350 int i, error; 1351 1352 for (i = 0; i < ET_RX_NDESC; ++i) { 1353 error = rbd->rbd_newbuf(rbd, i, 1); 1354 if (error) { 1355 aprint_error_dev(sc->sc_dev, "%d ring %d buf, newbuf failed: " 1356 "%d\n", n, i, error); 1357 return error; 1358 } 1359 } 1360 } 1361 1362 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1363 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1364 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1365 1366 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1367 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1368 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1369 1370 return 0; 1371 } 1372 1373 int 1374 et_init_rxdma(struct et_softc *sc) 1375 { 1376 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1377 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1378 struct et_rxdesc_ring *rx_ring; 1379 int error; 1380 1381 error = et_stop_rxdma(sc); 1382 if (error) { 1383 aprint_error_dev(sc->sc_dev, "can't init RX DMA engine\n"); 1384 return error; 1385 } 1386 1387 /* 1388 * Install RX status 1389 */ 1390 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1391 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1392 1393 /* 1394 * Install RX stat ring 1395 */ 1396 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1397 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1398 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1399 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1400 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1401 1402 /* Match ET_RXSTAT_POS */ 1403 rxst_ring->rsr_index = 0; 1404 rxst_ring->rsr_wrap = 0; 1405 1406 /* 1407 * Install the 2nd RX descriptor ring 1408 */ 1409 rx_ring = &sc->sc_rx_ring[1]; 1410 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1411 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1412 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1413 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1414 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1415 1416 /* Match ET_RX_RING1_POS */ 1417 rx_ring->rr_index = 0; 1418 rx_ring->rr_wrap = 1; 1419 1420 /* 1421 * Install the 1st RX descriptor ring 1422 */ 1423 rx_ring = &sc->sc_rx_ring[0]; 1424 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1425 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1426 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1427 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1428 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1429 1430 /* Match ET_RX_RING0_POS */ 1431 rx_ring->rr_index = 0; 1432 rx_ring->rr_wrap = 1; 1433 1434 /* 1435 * RX intr moderation 1436 */ 1437 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1438 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1439 1440 return 0; 1441 } 1442 1443 int 1444 et_init_txdma(struct et_softc *sc) 1445 { 1446 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1447 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1448 int error; 1449 1450 error = et_stop_txdma(sc); 1451 if (error) { 1452 aprint_error_dev(sc->sc_dev, "can't init TX DMA engine\n"); 1453 return error; 1454 } 1455 1456 /* 1457 * Install TX descriptor ring 1458 */ 1459 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1460 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1461 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1462 1463 /* 1464 * Install TX status 1465 */ 1466 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1467 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1468 1469 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1470 1471 /* Match ET_TX_READY_POS */ 1472 tx_ring->tr_ready_index = 0; 1473 tx_ring->tr_ready_wrap = 0; 1474 1475 return 0; 1476 } 1477 1478 void 1479 et_init_mac(struct et_softc *sc) 1480 { 1481 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1482 const uint8_t *eaddr = CLLADDR(ifp->if_sadl); 1483 uint32_t val; 1484 1485 /* Reset MAC */ 1486 CSR_WRITE_4(sc, ET_MAC_CFG1, 1487 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1488 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1489 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1490 1491 /* 1492 * Setup inter packet gap 1493 */ 1494 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1495 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1496 __SHIFTIN(80, ET_IPG_MINIFG) | 1497 __SHIFTIN(96, ET_IPG_B2B); 1498 CSR_WRITE_4(sc, ET_IPG, val); 1499 1500 /* 1501 * Setup half duplex mode 1502 */ 1503 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1504 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1505 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1506 ET_MAC_HDX_EXC_DEFER; 1507 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1508 1509 /* Clear MAC control */ 1510 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1511 1512 /* Reset MII */ 1513 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1514 1515 /* 1516 * Set MAC address 1517 */ 1518 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1519 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1520 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1521 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1522 1523 /* Set max frame length */ 1524 CSR_WRITE_4(sc, ET_MAX_FRMLEN, 1525 ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + ETHER_CRC_LEN); 1526 1527 /* Bring MAC out of reset state */ 1528 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1529 } 1530 1531 void 1532 et_init_rxmac(struct et_softc *sc) 1533 { 1534 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1535 const uint8_t *eaddr = CLLADDR(ifp->if_sadl); 1536 uint32_t val; 1537 int i; 1538 1539 /* Disable RX MAC and WOL */ 1540 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1541 1542 /* 1543 * Clear all WOL related registers 1544 */ 1545 for (i = 0; i < 3; ++i) 1546 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1547 for (i = 0; i < 20; ++i) 1548 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1549 1550 /* 1551 * Set WOL source address. XXX is this necessary? 1552 */ 1553 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1554 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1555 val = (eaddr[0] << 8) | eaddr[1]; 1556 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1557 1558 /* Clear packet filters */ 1559 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1560 1561 /* No ucast filtering */ 1562 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1563 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1564 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1565 1566 if (ifp->if_mtu > 8192) { 1567 /* 1568 * In order to transmit jumbo packets greater than 8k, 1569 * the FIFO between RX MAC and RX DMA needs to be reduced 1570 * in size to (16k - MTU). In order to implement this, we 1571 * must use "cut through" mode in the RX MAC, which chops 1572 * packets down into segments which are (max_size * 16). 1573 * In this case we selected 256 bytes, since this is the 1574 * size of the PCI-Express TLP's that the 1310 uses. 1575 */ 1576 val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) | 1577 ET_RXMAC_MC_SEGSZ_ENABLE; 1578 } else { 1579 val = 0; 1580 } 1581 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1582 1583 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1584 1585 /* Initialize RX MAC management register */ 1586 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1587 1588 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1589 1590 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1591 ET_RXMAC_MGT_PASS_ECRC | 1592 ET_RXMAC_MGT_PASS_ELEN | 1593 ET_RXMAC_MGT_PASS_ETRUNC | 1594 ET_RXMAC_MGT_CHECK_PKT); 1595 1596 /* 1597 * Configure runt filtering (may not work on certain chip generation) 1598 */ 1599 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1600 CSR_WRITE_4(sc, ET_PKTFILT, val); 1601 1602 /* Enable RX MAC but leave WOL disabled */ 1603 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1604 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1605 1606 /* 1607 * Setup multicast hash and allmulti/promisc mode 1608 */ 1609 et_setmulti(sc); 1610 } 1611 1612 void 1613 et_init_txmac(struct et_softc *sc) 1614 { 1615 /* Disable TX MAC and FC(?) */ 1616 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1617 1618 /* No flow control yet */ 1619 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1620 1621 /* Enable TX MAC but leave FC(?) diabled */ 1622 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1623 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1624 } 1625 1626 int 1627 et_start_rxdma(struct et_softc *sc) 1628 { 1629 uint32_t val = 0; 1630 1631 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1632 ET_RXDMA_CTRL_RING0_SIZE) | 1633 ET_RXDMA_CTRL_RING0_ENABLE; 1634 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1635 ET_RXDMA_CTRL_RING1_SIZE) | 1636 ET_RXDMA_CTRL_RING1_ENABLE; 1637 1638 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1639 1640 DELAY(5); 1641 1642 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1643 aprint_error_dev(sc->sc_dev, "can't start RX DMA engine\n"); 1644 return ETIMEDOUT; 1645 } 1646 return 0; 1647 } 1648 1649 int 1650 et_start_txdma(struct et_softc *sc) 1651 { 1652 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1653 return 0; 1654 } 1655 1656 int 1657 et_enable_txrx(struct et_softc *sc) 1658 { 1659 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1660 uint32_t val; 1661 int i, rc = 0; 1662 1663 val = CSR_READ_4(sc, ET_MAC_CFG1); 1664 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1665 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1666 ET_MAC_CFG1_LOOPBACK); 1667 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1668 1669 if ((rc = ether_mediachange(ifp)) != 0) 1670 goto out; 1671 1672 #define NRETRY 100 1673 1674 for (i = 0; i < NRETRY; ++i) { 1675 val = CSR_READ_4(sc, ET_MAC_CFG1); 1676 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1677 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1678 break; 1679 1680 DELAY(10); 1681 } 1682 if (i == NRETRY) { 1683 aprint_error_dev(sc->sc_dev, "can't enable RX/TX\n"); 1684 return ETIMEDOUT; 1685 } 1686 1687 #undef NRETRY 1688 return 0; 1689 out: 1690 return rc; 1691 } 1692 1693 void 1694 et_rxeof(struct et_softc *sc) 1695 { 1696 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1697 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1698 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1699 uint32_t rxs_stat_ring; 1700 int rxst_wrap, rxst_index; 1701 1702 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1703 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1704 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1705 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1706 1707 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1708 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1709 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1710 1711 while (rxst_index != rxst_ring->rsr_index || 1712 rxst_wrap != rxst_ring->rsr_wrap) { 1713 struct et_rxbuf_data *rbd; 1714 struct et_rxdesc_ring *rx_ring; 1715 struct et_rxstat *st; 1716 struct et_rxbuf *rb; 1717 struct mbuf *m; 1718 int buflen, buf_idx, ring_idx; 1719 uint32_t rxstat_pos, rxring_pos; 1720 1721 KASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1722 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1723 1724 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1725 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1726 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1727 1728 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1729 rxst_ring->rsr_index = 0; 1730 rxst_ring->rsr_wrap ^= 1; 1731 } 1732 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1733 ET_RXSTAT_POS_INDEX); 1734 if (rxst_ring->rsr_wrap) 1735 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1736 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1737 1738 if (ring_idx >= ET_RX_NRING) { 1739 ifp->if_ierrors++; 1740 aprint_error_dev(sc->sc_dev, "invalid ring index %d\n", 1741 ring_idx); 1742 continue; 1743 } 1744 if (buf_idx >= ET_RX_NDESC) { 1745 ifp->if_ierrors++; 1746 aprint_error_dev(sc->sc_dev, "invalid buf index %d\n", 1747 buf_idx); 1748 continue; 1749 } 1750 1751 rbd = &sc->sc_rx_data[ring_idx]; 1752 rb = &rbd->rbd_buf[buf_idx]; 1753 m = rb->rb_mbuf; 1754 bus_dmamap_sync(sc->sc_dmat, rb->rb_dmap, 0, 1755 rb->rb_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1756 1757 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1758 if (buflen < ETHER_CRC_LEN) { 1759 m_freem(m); 1760 ifp->if_ierrors++; 1761 } else { 1762 m->m_pkthdr.len = m->m_len = buflen - 1763 ETHER_CRC_LEN; 1764 m_set_rcvif(m, ifp); 1765 1766 if_percpuq_enqueue(ifp->if_percpuq, m); 1767 } 1768 } else { 1769 ifp->if_ierrors++; 1770 } 1771 1772 rx_ring = &sc->sc_rx_ring[ring_idx]; 1773 1774 if (buf_idx != rx_ring->rr_index) { 1775 aprint_error_dev(sc->sc_dev, "WARNING!! ring %d, " 1776 "buf_idx %d, rr_idx %d\n", 1777 ring_idx, buf_idx, rx_ring->rr_index); 1778 } 1779 1780 KASSERT(rx_ring->rr_index < ET_RX_NDESC); 1781 if (++rx_ring->rr_index == ET_RX_NDESC) { 1782 rx_ring->rr_index = 0; 1783 rx_ring->rr_wrap ^= 1; 1784 } 1785 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1786 if (rx_ring->rr_wrap) 1787 rxring_pos |= ET_RX_RING_POS_WRAP; 1788 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1789 } 1790 } 1791 1792 int 1793 et_encap(struct et_softc *sc, struct mbuf **m0) 1794 { 1795 struct mbuf *m = *m0; 1796 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1797 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1798 struct et_txdesc *td; 1799 bus_dmamap_t map; 1800 int error, maxsegs, first_idx, last_idx, i; 1801 uint32_t tx_ready_pos, last_td_ctrl2; 1802 1803 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1804 if (maxsegs > ET_NSEG_MAX) 1805 maxsegs = ET_NSEG_MAX; 1806 KASSERTMSG(maxsegs >= ET_NSEG_SPARE, 1807 "not enough spare TX desc (%d)\n", maxsegs); 1808 1809 KASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1810 first_idx = tx_ring->tr_ready_index; 1811 map = tbd->tbd_buf[first_idx].tb_dmap; 1812 1813 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1814 BUS_DMA_NOWAIT); 1815 if (!error && map->dm_nsegs == 0) { 1816 bus_dmamap_unload(sc->sc_dmat, map); 1817 error = EFBIG; 1818 } 1819 if (error && error != EFBIG) { 1820 aprint_error_dev(sc->sc_dev, "can't load TX mbuf"); 1821 goto back; 1822 } 1823 if (error) { /* error == EFBIG */ 1824 struct mbuf *m_new; 1825 1826 error = 0; 1827 1828 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1829 if (m_new == NULL) { 1830 aprint_error_dev(sc->sc_dev, "can't defrag TX mbuf\n"); 1831 error = ENOBUFS; 1832 goto back; 1833 } 1834 1835 m_copy_pkthdr(m_new, m); 1836 if (m->m_pkthdr.len > MHLEN) { 1837 MCLGET(m_new, M_DONTWAIT); 1838 if (!(m_new->m_flags & M_EXT)) { 1839 m_freem(m_new); 1840 error = ENOBUFS; 1841 } 1842 } 1843 1844 if (error) { 1845 aprint_error_dev(sc->sc_dev, "can't defrag TX buffer\n"); 1846 goto back; 1847 } 1848 1849 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, void *)); 1850 m_freem(m); 1851 m_new->m_len = m_new->m_pkthdr.len; 1852 *m0 = m = m_new; 1853 1854 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1855 BUS_DMA_NOWAIT); 1856 if (error || map->dm_nsegs == 0) { 1857 if (map->dm_nsegs == 0) { 1858 bus_dmamap_unload(sc->sc_dmat, map); 1859 error = EFBIG; 1860 } 1861 aprint_error_dev(sc->sc_dev, "can't load defraged TX mbuf\n"); 1862 goto back; 1863 } 1864 } 1865 1866 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1867 BUS_DMASYNC_PREWRITE); 1868 1869 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1870 sc->sc_tx += map->dm_nsegs; 1871 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1872 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1873 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1874 } 1875 1876 last_idx = -1; 1877 for (i = 0; i < map->dm_nsegs; ++i) { 1878 int idx; 1879 1880 idx = (first_idx + i) % ET_TX_NDESC; 1881 td = &tx_ring->tr_desc[idx]; 1882 td->td_addr_hi = ET_ADDR_HI(map->dm_segs[i].ds_addr); 1883 td->td_addr_lo = ET_ADDR_LO(map->dm_segs[i].ds_addr); 1884 td->td_ctrl1 = 1885 __SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN); 1886 1887 if (i == map->dm_nsegs - 1) { /* Last frag */ 1888 td->td_ctrl2 = last_td_ctrl2; 1889 last_idx = idx; 1890 } 1891 1892 KASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1893 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1894 tx_ring->tr_ready_index = 0; 1895 tx_ring->tr_ready_wrap ^= 1; 1896 } 1897 } 1898 td = &tx_ring->tr_desc[first_idx]; 1899 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1900 1901 KASSERT(last_idx >= 0); 1902 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1903 tbd->tbd_buf[last_idx].tb_dmap = map; 1904 tbd->tbd_buf[last_idx].tb_mbuf = m; 1905 1906 tbd->tbd_used += map->dm_nsegs; 1907 KASSERT(tbd->tbd_used <= ET_TX_NDESC); 1908 1909 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1910 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1911 1912 1913 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 1914 ET_TX_READY_POS_INDEX); 1915 if (tx_ring->tr_ready_wrap) 1916 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1917 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1918 1919 error = 0; 1920 back: 1921 if (error) { 1922 m_freem(m); 1923 *m0 = NULL; 1924 } 1925 return error; 1926 } 1927 1928 void 1929 et_txeof(struct et_softc *sc) 1930 { 1931 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1932 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1933 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1934 uint32_t tx_done; 1935 int end, wrap; 1936 1937 if (tbd->tbd_used == 0) 1938 return; 1939 1940 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 1941 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 1942 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 1943 1944 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 1945 struct et_txbuf *tb; 1946 1947 KASSERT(tbd->tbd_start_index < ET_TX_NDESC); 1948 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 1949 1950 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 1951 sizeof(struct et_txdesc)); 1952 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1953 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1954 1955 if (tb->tb_mbuf != NULL) { 1956 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1957 m_freem(tb->tb_mbuf); 1958 tb->tb_mbuf = NULL; 1959 ifp->if_opackets++; 1960 } 1961 1962 if (++tbd->tbd_start_index == ET_TX_NDESC) { 1963 tbd->tbd_start_index = 0; 1964 tbd->tbd_start_wrap ^= 1; 1965 } 1966 1967 KASSERT(tbd->tbd_used > 0); 1968 tbd->tbd_used--; 1969 } 1970 1971 if (tbd->tbd_used == 0) { 1972 callout_stop(&sc->sc_txtick); 1973 ifp->if_timer = 0; 1974 } 1975 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 1976 ifp->if_flags &= ~IFF_OACTIVE; 1977 1978 if_schedule_deferred_start(ifp); 1979 } 1980 1981 void 1982 et_txtick(void *xsc) 1983 { 1984 struct et_softc *sc = xsc; 1985 int s; 1986 1987 s = splnet(); 1988 et_txeof(sc); 1989 splx(s); 1990 } 1991 1992 void 1993 et_tick(void *xsc) 1994 { 1995 struct et_softc *sc = xsc; 1996 int s; 1997 1998 s = splnet(); 1999 mii_tick(&sc->sc_miibus); 2000 callout_schedule(&sc->sc_tick, hz); 2001 splx(s); 2002 } 2003 2004 int 2005 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 2006 { 2007 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 2008 } 2009 2010 int 2011 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 2012 { 2013 return et_newbuf(rbd, buf_idx, init, MHLEN); 2014 } 2015 2016 int 2017 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 2018 { 2019 struct et_softc *sc = rbd->rbd_softc; 2020 struct et_rxdesc_ring *rx_ring; 2021 struct et_rxdesc *desc; 2022 struct et_rxbuf *rb; 2023 struct mbuf *m; 2024 bus_dmamap_t dmap; 2025 int error, len; 2026 2027 KASSERT(buf_idx < ET_RX_NDESC); 2028 rb = &rbd->rbd_buf[buf_idx]; 2029 2030 if (len0 >= MINCLSIZE) { 2031 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2032 if (m == NULL) 2033 return (ENOBUFS); 2034 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2035 if ((m->m_flags & M_EXT) == 0) { 2036 m_freem(m); 2037 return (ENOBUFS); 2038 } 2039 len = MCLBYTES; 2040 } else { 2041 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2042 len = MHLEN; 2043 } 2044 2045 if (m == NULL) { 2046 error = ENOBUFS; 2047 2048 /* XXX for debug */ 2049 aprint_error_dev(sc->sc_dev, "M_CLGET failed, size %d\n", len0); 2050 if (init) { 2051 return error; 2052 } else { 2053 goto back; 2054 } 2055 } 2056 m->m_len = m->m_pkthdr.len = len; 2057 2058 /* 2059 * Try load RX mbuf into temporary DMA tag 2060 */ 2061 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_mbuf_tmp_dmap, m, 2062 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2063 if (error) { 2064 m_freem(m); 2065 2066 /* XXX for debug */ 2067 aprint_error_dev(sc->sc_dev, "can't load RX mbuf\n"); 2068 if (init) { 2069 return error; 2070 } else { 2071 goto back; 2072 } 2073 } 2074 2075 if (!init) 2076 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 2077 rb->rb_mbuf = m; 2078 2079 /* 2080 * Swap RX buf's DMA map with the loaded temporary one 2081 */ 2082 dmap = rb->rb_dmap; 2083 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2084 rb->rb_paddr = rb->rb_dmap->dm_segs[0].ds_addr; 2085 sc->sc_mbuf_tmp_dmap = dmap; 2086 2087 error = 0; 2088 back: 2089 rx_ring = rbd->rbd_ring; 2090 desc = &rx_ring->rr_desc[buf_idx]; 2091 2092 desc->rd_addr_hi = ET_ADDR_HI(rb->rb_paddr); 2093 desc->rd_addr_lo = ET_ADDR_LO(rb->rb_paddr); 2094 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2095 2096 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 2097 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2098 return error; 2099 } 2100
Indexes created Fri Oct 03 02:09:57 GMT 2025