if_et.c revision 1.18
1 /* $NetBSD: if_et.c,v 1.18 2018/12/09 11:14:02 jdolecek Exp $ */ 2 /* $OpenBSD: if_et.c,v 1.11 2008/06/08 06:18:07 jsg Exp $ */ 3 /* 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa (at) gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: if_et.c,v 1.18 2018/12/09 11:14:02 jdolecek Exp $"); 41 42 #include "opt_inet.h" 43 #include "vlan.h" 44 45 #include <sys/param.h> 46 #include <sys/endian.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/sockio.h> 50 #include <sys/mbuf.h> 51 #include <sys/queue.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/socket.h> 56 57 #include <sys/bus.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 #include <net/if_arp.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #include <net/bpf.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcidevs.h> 81 82 #include <dev/pci/if_etreg.h> 83 84 int et_match(device_t, cfdata_t, void *); 85 void et_attach(device_t, device_t, void *); 86 int et_detach(device_t, int flags); 87 int et_shutdown(device_t); 88 89 int et_miibus_readreg(device_t, int, int); 90 void et_miibus_writereg(device_t, int, int, int); 91 void et_miibus_statchg(struct ifnet *); 92 93 int et_init(struct ifnet *ifp); 94 int et_ioctl(struct ifnet *, u_long, void *); 95 void et_start(struct ifnet *); 96 void et_watchdog(struct ifnet *); 97 98 int et_intr(void *); 99 void et_enable_intrs(struct et_softc *, uint32_t); 100 void et_disable_intrs(struct et_softc *); 101 void et_rxeof(struct et_softc *); 102 void et_txeof(struct et_softc *); 103 void et_txtick(void *); 104 105 int et_dma_alloc(struct et_softc *); 106 void et_dma_free(struct et_softc *); 107 int et_dma_mem_create(struct et_softc *, bus_size_t, 108 void **, bus_addr_t *, bus_dmamap_t *, bus_dma_segment_t *); 109 void et_dma_mem_destroy(struct et_softc *, void *, bus_dmamap_t); 110 int et_dma_mbuf_create(struct et_softc *); 111 void et_dma_mbuf_destroy(struct et_softc *, int, const int[]); 112 113 int et_init_tx_ring(struct et_softc *); 114 int et_init_rx_ring(struct et_softc *); 115 void et_free_tx_ring(struct et_softc *); 116 void et_free_rx_ring(struct et_softc *); 117 int et_encap(struct et_softc *, struct mbuf **); 118 int et_newbuf(struct et_rxbuf_data *, int, int, int); 119 int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 120 int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 121 122 void et_stop(struct et_softc *); 123 int et_chip_init(struct et_softc *); 124 void et_chip_attach(struct et_softc *); 125 void et_init_mac(struct et_softc *); 126 void et_init_rxmac(struct et_softc *); 127 void et_init_txmac(struct et_softc *); 128 int et_init_rxdma(struct et_softc *); 129 int et_init_txdma(struct et_softc *); 130 int et_start_rxdma(struct et_softc *); 131 int et_start_txdma(struct et_softc *); 132 int et_stop_rxdma(struct et_softc *); 133 int et_stop_txdma(struct et_softc *); 134 int et_enable_txrx(struct et_softc *); 135 void et_reset(struct et_softc *); 136 int et_bus_config(struct et_softc *); 137 void et_get_eaddr(struct et_softc *, uint8_t[]); 138 void et_setmulti(struct et_softc *); 139 void et_tick(void *); 140 141 static int et_rx_intr_npkts = 32; 142 static int et_rx_intr_delay = 20; /* x10 usec */ 143 static int et_tx_intr_nsegs = 128; 144 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 145 146 struct et_bsize { 147 int bufsize; 148 et_newbuf_t newbuf; 149 }; 150 151 static const struct et_bsize et_bufsize[ET_RX_NRING] = { 152 { .bufsize = 0, .newbuf = et_newbuf_hdr }, 153 { .bufsize = 0, .newbuf = et_newbuf_cluster }, 154 }; 155 156 const struct et_product { 157 pci_vendor_id_t vendor; 158 pci_product_id_t product; 159 } et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310 }, 161 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1301 } 162 }; 163 164 CFATTACH_DECL_NEW(et, sizeof(struct et_softc), et_match, et_attach, et_detach, 165 NULL); 166 167 int 168 et_match(device_t dev, cfdata_t match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 const struct et_product *ep; 172 int i; 173 174 for (i = 0; i < __arraycount(et_devices); i++) { 175 ep = &et_devices[i]; 176 if (PCI_VENDOR(pa->pa_id) == ep->vendor && 177 PCI_PRODUCT(pa->pa_id) == ep->product) 178 return 1; 179 } 180 return 0; 181 } 182 183 void 184 et_attach(device_t parent, device_t self, void *aux) 185 { 186 struct et_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 pci_intr_handle_t ih; 190 const char *intrstr; 191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 192 pcireg_t memtype; 193 int error; 194 char intrbuf[PCI_INTRSTR_LEN]; 195 196 pci_aprint_devinfo(pa, "Ethernet controller"); 197 198 sc->sc_dev = self; 199 200 /* 201 * Initialize tunables 202 */ 203 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 204 sc->sc_rx_intr_delay = et_rx_intr_delay; 205 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 206 sc->sc_timer = et_timer; 207 208 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ET_PCIR_BAR); 209 if (pci_mapreg_map(pa, ET_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 210 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 211 aprint_error_dev(self, "could not map mem space\n"); 212 return; 213 } 214 215 if (pci_intr_map(pa, &ih) != 0) { 216 aprint_error_dev(self, "could not map interrupt\n"); 217 goto fail; 218 } 219 220 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 221 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, et_intr, 222 sc, device_xname(self)); 223 if (sc->sc_irq_handle == NULL) { 224 aprint_error_dev(self, "could not establish interrupt"); 225 if (intrstr != NULL) 226 aprint_error(" at %s", intrstr); 227 aprint_error("\n"); 228 goto fail; 229 } 230 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 231 232 sc->sc_dmat = pa->pa_dmat; 233 sc->sc_pct = pa->pa_pc; 234 sc->sc_pcitag = pa->pa_tag; 235 236 error = et_bus_config(sc); 237 if (error) 238 goto fail; 239 240 et_get_eaddr(sc, sc->sc_enaddr); 241 242 aprint_normal_dev(self, "Ethernet address %s\n", 243 ether_sprintf(sc->sc_enaddr)); 244 245 CSR_WRITE_4(sc, ET_PM, 246 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 247 248 et_reset(sc); 249 250 et_disable_intrs(sc); 251 252 error = et_dma_alloc(sc); 253 if (error) 254 goto fail; 255 256 ifp->if_softc = sc; 257 ifp->if_mtu = ETHERMTU; 258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 259 ifp->if_init = et_init; 260 ifp->if_ioctl = et_ioctl; 261 ifp->if_start = et_start; 262 ifp->if_watchdog = et_watchdog; 263 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 264 IFQ_SET_READY(&ifp->if_snd); 265 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 266 267 et_chip_attach(sc); 268 269 sc->sc_miibus.mii_ifp = ifp; 270 sc->sc_miibus.mii_readreg = et_miibus_readreg; 271 sc->sc_miibus.mii_writereg = et_miibus_writereg; 272 sc->sc_miibus.mii_statchg = et_miibus_statchg; 273 274 sc->sc_ethercom.ec_mii = &sc->sc_miibus; 275 ifmedia_init(&sc->sc_miibus.mii_media, 0, ether_mediachange, 276 ether_mediastatus); 277 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 278 MII_OFFSET_ANY, 0); 279 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 280 aprint_error_dev(self, "no PHY found!\n"); 281 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 282 0, NULL); 283 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 284 } else 285 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 286 287 if_attach(ifp); 288 if_deferred_start_init(ifp, NULL); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 callout_init(&sc->sc_tick, 0); 292 callout_setfunc(&sc->sc_tick, et_tick, sc); 293 callout_init(&sc->sc_txtick, 0); 294 callout_setfunc(&sc->sc_txtick, et_txtick, sc); 295 296 if (pmf_device_register(self, NULL, NULL)) 297 pmf_class_network_register(self, ifp); 298 else 299 aprint_error_dev(self, "couldn't establish power handler\n"); 300 301 return; 302 303 fail: 304 et_dma_free(sc); 305 if (sc->sc_irq_handle != NULL) { 306 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 307 sc->sc_irq_handle = NULL; 308 } 309 if (sc->sc_mem_size) { 310 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 311 sc->sc_mem_size = 0; 312 } 313 } 314 315 int 316 et_detach(device_t self, int flags) 317 { 318 struct et_softc *sc = device_private(self); 319 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 320 int s; 321 322 pmf_device_deregister(self); 323 s = splnet(); 324 et_stop(sc); 325 splx(s); 326 327 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 328 329 /* Delete all remaining media. */ 330 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 331 332 ether_ifdetach(ifp); 333 if_detach(ifp); 334 et_dma_free(sc); 335 336 if (sc->sc_irq_handle != NULL) { 337 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 338 sc->sc_irq_handle = NULL; 339 } 340 341 if (sc->sc_mem_size) { 342 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 343 sc->sc_mem_size = 0; 344 } 345 346 return 0; 347 } 348 349 int 350 et_shutdown(device_t self) 351 { 352 struct et_softc *sc = device_private(self); 353 int s; 354 355 s = splnet(); 356 et_stop(sc); 357 splx(s); 358 359 return 0; 360 } 361 362 int 363 et_miibus_readreg(device_t dev, int phy, int reg) 364 { 365 struct et_softc *sc = device_private(dev); 366 uint32_t val; 367 int i, ret; 368 369 /* Stop any pending operations */ 370 CSR_WRITE_4(sc, ET_MII_CMD, 0); 371 372 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 373 __SHIFTIN(reg, ET_MII_ADDR_REG); 374 CSR_WRITE_4(sc, ET_MII_ADDR, val); 375 376 /* Start reading */ 377 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 378 379 #define NRETRY 50 380 381 for (i = 0; i < NRETRY; ++i) { 382 val = CSR_READ_4(sc, ET_MII_IND); 383 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 384 break; 385 DELAY(50); 386 } 387 if (i == NRETRY) { 388 aprint_error_dev(sc->sc_dev, "read phy %d, reg %d timed out\n", 389 phy, reg); 390 ret = 0; 391 goto back; 392 } 393 394 #undef NRETRY 395 396 val = CSR_READ_4(sc, ET_MII_STAT); 397 ret = __SHIFTOUT(val, ET_MII_STAT_VALUE); 398 399 back: 400 /* Make sure that the current operation is stopped */ 401 CSR_WRITE_4(sc, ET_MII_CMD, 0); 402 return ret; 403 } 404 405 void 406 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 407 { 408 struct et_softc *sc = device_private(dev); 409 uint32_t val; 410 int i; 411 412 /* Stop any pending operations */ 413 CSR_WRITE_4(sc, ET_MII_CMD, 0); 414 415 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 416 __SHIFTIN(reg, ET_MII_ADDR_REG); 417 CSR_WRITE_4(sc, ET_MII_ADDR, val); 418 419 /* Start writing */ 420 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE)); 421 422 #define NRETRY 100 423 424 for (i = 0; i < NRETRY; ++i) { 425 val = CSR_READ_4(sc, ET_MII_IND); 426 if ((val & ET_MII_IND_BUSY) == 0) 427 break; 428 DELAY(50); 429 } 430 if (i == NRETRY) { 431 aprint_error_dev(sc->sc_dev, "write phy %d, reg %d timed out\n", 432 phy, reg); 433 et_miibus_readreg(dev, phy, reg); 434 } 435 436 #undef NRETRY 437 438 /* Make sure that the current operation is stopped */ 439 CSR_WRITE_4(sc, ET_MII_CMD, 0); 440 } 441 442 void 443 et_miibus_statchg(struct ifnet *ifp) 444 { 445 struct et_softc *sc = ifp->if_softc; 446 struct mii_data *mii = &sc->sc_miibus; 447 uint32_t cfg2, ctrl; 448 449 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 450 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 451 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 452 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 453 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 454 455 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 456 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 457 458 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 459 cfg2 |= ET_MAC_CFG2_MODE_GMII; 460 } else { 461 cfg2 |= ET_MAC_CFG2_MODE_MII; 462 ctrl |= ET_MAC_CTRL_MODE_MII; 463 } 464 465 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 466 cfg2 |= ET_MAC_CFG2_FDX; 467 else 468 ctrl |= ET_MAC_CTRL_GHDX; 469 470 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 471 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 472 } 473 474 void 475 et_stop(struct et_softc *sc) 476 { 477 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 478 479 callout_stop(&sc->sc_tick); 480 callout_stop(&sc->sc_txtick); 481 482 et_stop_rxdma(sc); 483 et_stop_txdma(sc); 484 485 et_disable_intrs(sc); 486 487 et_free_tx_ring(sc); 488 et_free_rx_ring(sc); 489 490 et_reset(sc); 491 492 sc->sc_tx = 0; 493 sc->sc_tx_intr = 0; 494 495 ifp->if_timer = 0; 496 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 497 } 498 499 int 500 et_bus_config(struct et_softc *sc) 501 { 502 uint32_t val; //, max_plsz; 503 // uint16_t ack_latency, replay_timer; 504 505 /* 506 * Test whether EEPROM is valid 507 * NOTE: Read twice to get the correct value 508 */ 509 pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 510 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 511 512 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 513 aprint_error_dev(sc->sc_dev, "EEPROM status error 0x%02x\n", val); 514 return ENXIO; 515 } 516 517 /* TODO: LED */ 518 #if 0 519 /* 520 * Configure ACK latency and replay timer according to 521 * max playload size 522 */ 523 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CAPS); 524 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 525 526 switch (max_plsz) { 527 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 528 ack_latency = ET_PCIV_ACK_LATENCY_128; 529 replay_timer = ET_PCIV_REPLAY_TIMER_128; 530 break; 531 532 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 533 ack_latency = ET_PCIV_ACK_LATENCY_256; 534 replay_timer = ET_PCIV_REPLAY_TIMER_256; 535 break; 536 537 default: 538 ack_latency = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 539 ET_PCIR_ACK_LATENCY) >> 16; 540 replay_timer = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 541 ET_PCIR_REPLAY_TIMER) >> 16; 542 aprint_normal_dev(sc->sc_dev, "ack latency %u, replay timer %u\n", 543 ack_latency, replay_timer); 544 break; 545 } 546 if (ack_latency != 0) { 547 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 548 ET_PCIR_ACK_LATENCY, ack_latency << 16); 549 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 550 ET_PCIR_REPLAY_TIMER, replay_timer << 16); 551 } 552 553 /* 554 * Set L0s and L1 latency timer to 2us 555 */ 556 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 557 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_L0S_L1_LATENCY, 558 val << 24); 559 560 /* 561 * Set max read request size to 2048 bytes 562 */ 563 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 564 ET_PCIR_DEVICE_CTRL) >> 16; 565 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 566 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 567 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CTRL, 568 val << 16); 569 #endif 570 571 return 0; 572 } 573 574 void 575 et_get_eaddr(struct et_softc *sc, uint8_t eaddr[]) 576 { 577 uint32_t r; 578 579 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_LO); 580 eaddr[0] = r & 0xff; 581 eaddr[1] = (r >> 8) & 0xff; 582 eaddr[2] = (r >> 16) & 0xff; 583 eaddr[3] = (r >> 24) & 0xff; 584 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_HI); 585 eaddr[4] = r & 0xff; 586 eaddr[5] = (r >> 8) & 0xff; 587 } 588 589 void 590 et_reset(struct et_softc *sc) 591 { 592 CSR_WRITE_4(sc, ET_MAC_CFG1, 593 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 594 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 595 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 596 597 CSR_WRITE_4(sc, ET_SWRST, 598 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 599 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 600 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 601 602 CSR_WRITE_4(sc, ET_MAC_CFG1, 603 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 604 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 605 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 606 } 607 608 void 609 et_disable_intrs(struct et_softc *sc) 610 { 611 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 612 } 613 614 void 615 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 616 { 617 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 618 } 619 620 int 621 et_dma_alloc(struct et_softc *sc) 622 { 623 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 624 struct et_txstatus_data *txsd = &sc->sc_tx_status; 625 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 626 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 627 int i, error; 628 629 /* 630 * Create TX ring DMA stuffs 631 */ 632 error = et_dma_mem_create(sc, ET_TX_RING_SIZE, 633 (void **)&tx_ring->tr_desc, &tx_ring->tr_paddr, &tx_ring->tr_dmap, 634 &tx_ring->tr_seg); 635 if (error) { 636 aprint_error_dev(sc->sc_dev, "can't create TX ring DMA stuffs\n"); 637 return error; 638 } 639 640 /* 641 * Create TX status DMA stuffs 642 */ 643 error = et_dma_mem_create(sc, sizeof(uint32_t), 644 (void **)&txsd->txsd_status, 645 &txsd->txsd_paddr, &txsd->txsd_dmap, &txsd->txsd_seg); 646 if (error) { 647 aprint_error_dev(sc->sc_dev, "can't create TX status DMA stuffs\n"); 648 return error; 649 } 650 651 /* 652 * Create DMA stuffs for RX rings 653 */ 654 for (i = 0; i < ET_RX_NRING; ++i) { 655 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 656 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 657 658 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 659 660 error = et_dma_mem_create(sc, ET_RX_RING_SIZE, 661 (void **)&rx_ring->rr_desc, 662 &rx_ring->rr_paddr, &rx_ring->rr_dmap, &rx_ring->rr_seg); 663 if (error) { 664 aprint_error_dev(sc->sc_dev, "can't create DMA stuffs for " 665 "the %d RX ring\n", i); 666 return error; 667 } 668 rx_ring->rr_posreg = rx_ring_posreg[i]; 669 } 670 671 /* 672 * Create RX stat ring DMA stuffs 673 */ 674 error = et_dma_mem_create(sc, ET_RXSTAT_RING_SIZE, 675 (void **)&rxst_ring->rsr_stat, 676 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap, &rxst_ring->rsr_seg); 677 if (error) { 678 aprint_error_dev(sc->sc_dev, "can't create RX stat ring DMA stuffs\n"); 679 return error; 680 } 681 682 /* 683 * Create RX status DMA stuffs 684 */ 685 error = et_dma_mem_create(sc, sizeof(struct et_rxstatus), 686 (void **)&rxsd->rxsd_status, 687 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap, &rxsd->rxsd_seg); 688 if (error) { 689 aprint_error_dev(sc->sc_dev, "can't create RX status DMA stuffs\n"); 690 return error; 691 } 692 693 /* 694 * Create mbuf DMA stuffs 695 */ 696 error = et_dma_mbuf_create(sc); 697 if (error) 698 return error; 699 700 return 0; 701 } 702 703 void 704 et_dma_free(struct et_softc *sc) 705 { 706 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 707 struct et_txstatus_data *txsd = &sc->sc_tx_status; 708 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 709 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 710 int i, rx_done[ET_RX_NRING]; 711 712 /* 713 * Destroy TX ring DMA stuffs 714 */ 715 et_dma_mem_destroy(sc, tx_ring->tr_desc, tx_ring->tr_dmap); 716 717 /* 718 * Destroy TX status DMA stuffs 719 */ 720 et_dma_mem_destroy(sc, txsd->txsd_status, txsd->txsd_dmap); 721 722 /* 723 * Destroy DMA stuffs for RX rings 724 */ 725 for (i = 0; i < ET_RX_NRING; ++i) { 726 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 727 728 et_dma_mem_destroy(sc, rx_ring->rr_desc, rx_ring->rr_dmap); 729 } 730 731 /* 732 * Destroy RX stat ring DMA stuffs 733 */ 734 et_dma_mem_destroy(sc, rxst_ring->rsr_stat, rxst_ring->rsr_dmap); 735 736 /* 737 * Destroy RX status DMA stuffs 738 */ 739 et_dma_mem_destroy(sc, rxsd->rxsd_status, rxsd->rxsd_dmap); 740 741 /* 742 * Destroy mbuf DMA stuffs 743 */ 744 for (i = 0; i < ET_RX_NRING; ++i) 745 rx_done[i] = ET_RX_NDESC; 746 et_dma_mbuf_destroy(sc, ET_TX_NDESC, rx_done); 747 } 748 749 int 750 et_dma_mbuf_create(struct et_softc *sc) 751 { 752 struct et_txbuf_data *tbd = &sc->sc_tx_data; 753 int i, error, rx_done[ET_RX_NRING]; 754 755 /* 756 * Create spare DMA map for RX mbufs 757 */ 758 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 759 BUS_DMA_NOWAIT, &sc->sc_mbuf_tmp_dmap); 760 if (error) { 761 aprint_error_dev(sc->sc_dev, "can't create spare mbuf DMA map\n"); 762 return error; 763 } 764 765 /* 766 * Create DMA maps for RX mbufs 767 */ 768 bzero(rx_done, sizeof(rx_done)); 769 for (i = 0; i < ET_RX_NRING; ++i) { 770 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 771 int j; 772 773 for (j = 0; j < ET_RX_NDESC; ++j) { 774 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 775 MCLBYTES, 0, BUS_DMA_NOWAIT, 776 &rbd->rbd_buf[j].rb_dmap); 777 if (error) { 778 aprint_error_dev(sc->sc_dev, "can't create %d RX mbuf " 779 "for %d RX ring\n", j, i); 780 rx_done[i] = j; 781 et_dma_mbuf_destroy(sc, 0, rx_done); 782 return error; 783 } 784 } 785 rx_done[i] = ET_RX_NDESC; 786 787 rbd->rbd_softc = sc; 788 rbd->rbd_ring = &sc->sc_rx_ring[i]; 789 } 790 791 /* 792 * Create DMA maps for TX mbufs 793 */ 794 for (i = 0; i < ET_TX_NDESC; ++i) { 795 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 796 0, BUS_DMA_NOWAIT, &tbd->tbd_buf[i].tb_dmap); 797 if (error) { 798 aprint_error_dev(sc->sc_dev, "can't create %d TX mbuf " 799 "DMA map\n", i); 800 et_dma_mbuf_destroy(sc, i, rx_done); 801 return error; 802 } 803 } 804 805 return 0; 806 } 807 808 void 809 et_dma_mbuf_destroy(struct et_softc *sc, int tx_done, const int rx_done[]) 810 { 811 struct et_txbuf_data *tbd = &sc->sc_tx_data; 812 int i; 813 814 /* 815 * Destroy DMA maps for RX mbufs 816 */ 817 for (i = 0; i < ET_RX_NRING; ++i) { 818 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 819 int j; 820 821 for (j = 0; j < rx_done[i]; ++j) { 822 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 823 824 KASSERTMSG(rb->rb_mbuf == NULL, 825 "RX mbuf in %d RX ring is not freed yet\n", i); 826 bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); 827 } 828 } 829 830 /* 831 * Destroy DMA maps for TX mbufs 832 */ 833 for (i = 0; i < tx_done; ++i) { 834 struct et_txbuf *tb = &tbd->tbd_buf[i]; 835 836 KASSERTMSG(tb->tb_mbuf == NULL, "TX mbuf is not freed yet\n"); 837 bus_dmamap_destroy(sc->sc_dmat, tb->tb_dmap); 838 } 839 840 /* 841 * Destroy spare mbuf DMA map 842 */ 843 bus_dmamap_destroy(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 844 } 845 846 int 847 et_dma_mem_create(struct et_softc *sc, bus_size_t size, 848 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap, bus_dma_segment_t *seg) 849 { 850 int error, nsegs; 851 852 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 853 dmap); 854 if (error) { 855 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 856 return error; 857 } 858 859 error = bus_dmamem_alloc(sc->sc_dmat, size, ET_ALIGN, 0, seg, 860 1, &nsegs, BUS_DMA_WAITOK); 861 if (error) { 862 aprint_error_dev(sc->sc_dev, "can't allocate DMA mem\n"); 863 return error; 864 } 865 866 error = bus_dmamem_map(sc->sc_dmat, seg, nsegs, 867 size, (void **)addr, BUS_DMA_NOWAIT); 868 if (error) { 869 aprint_error_dev(sc->sc_dev, "can't map DMA mem\n"); 870 return (error); 871 } 872 873 error = bus_dmamap_load(sc->sc_dmat, *dmap, *addr, size, NULL, 874 BUS_DMA_WAITOK); 875 if (error) { 876 aprint_error_dev(sc->sc_dev, "can't load DMA mem\n"); 877 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)addr, 1); 878 return error; 879 } 880 881 memset(*addr, 0, size); 882 883 *paddr = (*dmap)->dm_segs[0].ds_addr; 884 885 return 0; 886 } 887 888 void 889 et_dma_mem_destroy(struct et_softc *sc, void *addr, bus_dmamap_t dmap) 890 { 891 bus_dmamap_unload(sc->sc_dmat, dmap); 892 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&addr, 1); 893 } 894 895 void 896 et_chip_attach(struct et_softc *sc) 897 { 898 uint32_t val; 899 900 /* 901 * Perform minimal initialization 902 */ 903 904 /* Disable loopback */ 905 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 906 907 /* Reset MAC */ 908 CSR_WRITE_4(sc, ET_MAC_CFG1, 909 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 910 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 911 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 912 913 /* 914 * Setup half duplex mode 915 */ 916 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 917 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 918 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 919 ET_MAC_HDX_EXC_DEFER; 920 CSR_WRITE_4(sc, ET_MAC_HDX, val); 921 922 /* Clear MAC control */ 923 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 924 925 /* Reset MII */ 926 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 927 928 /* Bring MAC out of reset state */ 929 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 930 931 /* Enable memory controllers */ 932 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 933 } 934 935 int 936 et_intr(void *xsc) 937 { 938 struct et_softc *sc = xsc; 939 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 940 uint32_t intrs; 941 942 if ((ifp->if_flags & IFF_RUNNING) == 0) 943 return (0); 944 945 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 946 if (intrs == 0 || intrs == 0xffffffff) 947 return (0); 948 949 et_disable_intrs(sc); 950 intrs &= ET_INTRS; 951 if (intrs == 0) /* Not interested */ 952 goto back; 953 954 if (intrs & ET_INTR_RXEOF) 955 et_rxeof(sc); 956 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 957 et_txeof(sc); 958 if (intrs & ET_INTR_TIMER) 959 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 960 back: 961 et_enable_intrs(sc, ET_INTRS); 962 963 return (1); 964 } 965 966 int 967 et_init(struct ifnet *ifp) 968 { 969 struct et_softc *sc = ifp->if_softc; 970 int error, i, s; 971 972 if (ifp->if_flags & IFF_RUNNING) 973 return 0; 974 975 s = splnet(); 976 977 et_stop(sc); 978 979 for (i = 0; i < ET_RX_NRING; ++i) { 980 sc->sc_rx_data[i].rbd_bufsize = et_bufsize[i].bufsize; 981 sc->sc_rx_data[i].rbd_newbuf = et_bufsize[i].newbuf; 982 } 983 984 error = et_init_tx_ring(sc); 985 if (error) 986 goto back; 987 988 error = et_init_rx_ring(sc); 989 if (error) 990 goto back; 991 992 error = et_chip_init(sc); 993 if (error) 994 goto back; 995 996 error = et_enable_txrx(sc); 997 if (error) 998 goto back; 999 1000 error = et_start_rxdma(sc); 1001 if (error) 1002 goto back; 1003 1004 error = et_start_txdma(sc); 1005 if (error) 1006 goto back; 1007 1008 et_enable_intrs(sc, ET_INTRS); 1009 1010 callout_schedule(&sc->sc_tick, hz); 1011 1012 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1013 1014 ifp->if_flags |= IFF_RUNNING; 1015 ifp->if_flags &= ~IFF_OACTIVE; 1016 back: 1017 if (error) 1018 et_stop(sc); 1019 1020 splx(s); 1021 1022 return (0); 1023 } 1024 1025 int 1026 et_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1027 { 1028 struct et_softc *sc = ifp->if_softc; 1029 struct ifreq *ifr = (struct ifreq *)data; 1030 int s, error = 0; 1031 1032 s = splnet(); 1033 1034 switch (cmd) { 1035 case SIOCSIFFLAGS: 1036 if (ifp->if_flags & IFF_UP) { 1037 /* 1038 * If only the PROMISC or ALLMULTI flag changes, then 1039 * don't do a full re-init of the chip, just update 1040 * the Rx filter. 1041 */ 1042 if ((ifp->if_flags & IFF_RUNNING) && 1043 ((ifp->if_flags ^ sc->sc_if_flags) & 1044 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1045 et_setmulti(sc); 1046 } else { 1047 if (!(ifp->if_flags & IFF_RUNNING)) 1048 et_init(ifp); 1049 } 1050 } else { 1051 if (ifp->if_flags & IFF_RUNNING) 1052 et_stop(sc); 1053 } 1054 sc->sc_if_flags = ifp->if_flags; 1055 break; 1056 case SIOCSIFMEDIA: 1057 case SIOCGIFMEDIA: 1058 error = ifmedia_ioctl(ifp, ifr, &sc->sc_miibus.mii_media, cmd); 1059 break; 1060 default: 1061 error = ether_ioctl(ifp, cmd, data); 1062 if (error == ENETRESET) { 1063 if (ifp->if_flags & IFF_RUNNING) 1064 et_setmulti(sc); 1065 error = 0; 1066 } 1067 break; 1068 1069 } 1070 1071 splx(s); 1072 1073 return error; 1074 } 1075 1076 void 1077 et_start(struct ifnet *ifp) 1078 { 1079 struct et_softc *sc = ifp->if_softc; 1080 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1081 int trans; 1082 struct mbuf *m; 1083 1084 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1085 return; 1086 1087 trans = 0; 1088 for (;;) { 1089 IFQ_DEQUEUE(&ifp->if_snd, m); 1090 if (m == NULL) 1091 break; 1092 1093 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1094 ifp->if_flags |= IFF_OACTIVE; 1095 break; 1096 } 1097 1098 if (et_encap(sc, &m)) { 1099 ifp->if_oerrors++; 1100 ifp->if_flags |= IFF_OACTIVE; 1101 break; 1102 } 1103 1104 trans = 1; 1105 1106 bpf_mtap(ifp, m, BPF_D_OUT); 1107 } 1108 1109 if (trans) { 1110 callout_schedule(&sc->sc_txtick, hz); 1111 ifp->if_timer = 5; 1112 } 1113 } 1114 1115 void 1116 et_watchdog(struct ifnet *ifp) 1117 { 1118 struct et_softc *sc = ifp->if_softc; 1119 aprint_error_dev(sc->sc_dev, "watchdog timed out\n"); 1120 1121 ifp->if_flags &= ~IFF_RUNNING; 1122 et_init(ifp); 1123 et_start(ifp); 1124 } 1125 1126 int 1127 et_stop_rxdma(struct et_softc *sc) 1128 { 1129 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1130 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1131 1132 DELAY(5); 1133 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1134 aprint_error_dev(sc->sc_dev, "can't stop RX DMA engine\n"); 1135 return ETIMEDOUT; 1136 } 1137 return 0; 1138 } 1139 1140 int 1141 et_stop_txdma(struct et_softc *sc) 1142 { 1143 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1144 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1145 return 0; 1146 } 1147 1148 void 1149 et_free_tx_ring(struct et_softc *sc) 1150 { 1151 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1152 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1153 int i; 1154 1155 for (i = 0; i < ET_TX_NDESC; ++i) { 1156 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1157 1158 if (tb->tb_mbuf != NULL) { 1159 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1160 m_freem(tb->tb_mbuf); 1161 tb->tb_mbuf = NULL; 1162 } 1163 } 1164 1165 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1166 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1167 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1168 } 1169 1170 void 1171 et_free_rx_ring(struct et_softc *sc) 1172 { 1173 int n; 1174 1175 for (n = 0; n < ET_RX_NRING; ++n) { 1176 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1177 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1178 int i; 1179 1180 for (i = 0; i < ET_RX_NDESC; ++i) { 1181 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1182 1183 if (rb->rb_mbuf != NULL) { 1184 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 1185 m_freem(rb->rb_mbuf); 1186 rb->rb_mbuf = NULL; 1187 } 1188 } 1189 1190 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1191 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 1192 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1193 } 1194 } 1195 1196 void 1197 et_setmulti(struct et_softc *sc) 1198 { 1199 struct ethercom *ec = &sc->sc_ethercom; 1200 struct ifnet *ifp = &ec->ec_if; 1201 uint32_t hash[4] = { 0, 0, 0, 0 }; 1202 uint32_t rxmac_ctrl, pktfilt; 1203 struct ether_multi *enm; 1204 struct ether_multistep step; 1205 uint8_t addr[ETHER_ADDR_LEN]; 1206 int i, count; 1207 1208 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1209 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1210 1211 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1212 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1213 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1214 goto back; 1215 } 1216 1217 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1218 1219 count = 0; 1220 ETHER_FIRST_MULTI(step, ec, enm); 1221 while (enm != NULL) { 1222 uint32_t *hp, h; 1223 1224 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1225 addr[i] &= enm->enm_addrlo[i]; 1226 } 1227 1228 h = ether_crc32_be(addr, ETHER_ADDR_LEN); 1229 h = (h & 0x3f800000) >> 23; 1230 1231 hp = &hash[0]; 1232 if (h >= 32 && h < 64) { 1233 h -= 32; 1234 hp = &hash[1]; 1235 } else if (h >= 64 && h < 96) { 1236 h -= 64; 1237 hp = &hash[2]; 1238 } else if (h >= 96) { 1239 h -= 96; 1240 hp = &hash[3]; 1241 } 1242 *hp |= (1 << h); 1243 1244 ++count; 1245 ETHER_NEXT_MULTI(step, enm); 1246 } 1247 1248 for (i = 0; i < 4; ++i) 1249 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1250 1251 if (count > 0) 1252 pktfilt |= ET_PKTFILT_MCAST; 1253 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1254 back: 1255 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1256 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1257 } 1258 1259 int 1260 et_chip_init(struct et_softc *sc) 1261 { 1262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1263 uint32_t rxq_end; 1264 int error; 1265 1266 /* 1267 * Split internal memory between TX and RX according to MTU 1268 */ 1269 if (ifp->if_mtu < 2048) 1270 rxq_end = 0x2bc; 1271 else if (ifp->if_mtu < 8192) 1272 rxq_end = 0x1ff; 1273 else 1274 rxq_end = 0x1b3; 1275 CSR_WRITE_4(sc, ET_RXQ_START, 0); 1276 CSR_WRITE_4(sc, ET_RXQ_END, rxq_end); 1277 CSR_WRITE_4(sc, ET_TXQ_START, rxq_end + 1); 1278 CSR_WRITE_4(sc, ET_TXQ_END, ET_INTERN_MEM_END); 1279 1280 /* No loopback */ 1281 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1282 1283 /* Clear MSI configure */ 1284 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1285 1286 /* Disable timer */ 1287 CSR_WRITE_4(sc, ET_TIMER, 0); 1288 1289 /* Initialize MAC */ 1290 et_init_mac(sc); 1291 1292 /* Enable memory controllers */ 1293 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1294 1295 /* Initialize RX MAC */ 1296 et_init_rxmac(sc); 1297 1298 /* Initialize TX MAC */ 1299 et_init_txmac(sc); 1300 1301 /* Initialize RX DMA engine */ 1302 error = et_init_rxdma(sc); 1303 if (error) 1304 return error; 1305 1306 /* Initialize TX DMA engine */ 1307 error = et_init_txdma(sc); 1308 if (error) 1309 return error; 1310 1311 return 0; 1312 } 1313 1314 int 1315 et_init_tx_ring(struct et_softc *sc) 1316 { 1317 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1318 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1319 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1320 1321 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1322 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1323 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1324 1325 tbd->tbd_start_index = 0; 1326 tbd->tbd_start_wrap = 0; 1327 tbd->tbd_used = 0; 1328 1329 bzero(txsd->txsd_status, sizeof(uint32_t)); 1330 bus_dmamap_sync(sc->sc_dmat, txsd->txsd_dmap, 0, 1331 txsd->txsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1332 return 0; 1333 } 1334 1335 int 1336 et_init_rx_ring(struct et_softc *sc) 1337 { 1338 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1339 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1340 int n; 1341 1342 for (n = 0; n < ET_RX_NRING; ++n) { 1343 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1344 int i, error; 1345 1346 for (i = 0; i < ET_RX_NDESC; ++i) { 1347 error = rbd->rbd_newbuf(rbd, i, 1); 1348 if (error) { 1349 aprint_error_dev(sc->sc_dev, "%d ring %d buf, newbuf failed: " 1350 "%d\n", n, i, error); 1351 return error; 1352 } 1353 } 1354 } 1355 1356 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1357 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1358 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1359 1360 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1361 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1362 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1363 1364 return 0; 1365 } 1366 1367 int 1368 et_init_rxdma(struct et_softc *sc) 1369 { 1370 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1371 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1372 struct et_rxdesc_ring *rx_ring; 1373 int error; 1374 1375 error = et_stop_rxdma(sc); 1376 if (error) { 1377 aprint_error_dev(sc->sc_dev, "can't init RX DMA engine\n"); 1378 return error; 1379 } 1380 1381 /* 1382 * Install RX status 1383 */ 1384 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1385 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1386 1387 /* 1388 * Install RX stat ring 1389 */ 1390 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1391 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1392 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1393 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1394 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1395 1396 /* Match ET_RXSTAT_POS */ 1397 rxst_ring->rsr_index = 0; 1398 rxst_ring->rsr_wrap = 0; 1399 1400 /* 1401 * Install the 2nd RX descriptor ring 1402 */ 1403 rx_ring = &sc->sc_rx_ring[1]; 1404 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1405 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1406 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1407 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1408 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1409 1410 /* Match ET_RX_RING1_POS */ 1411 rx_ring->rr_index = 0; 1412 rx_ring->rr_wrap = 1; 1413 1414 /* 1415 * Install the 1st RX descriptor ring 1416 */ 1417 rx_ring = &sc->sc_rx_ring[0]; 1418 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1419 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1420 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1421 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1422 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1423 1424 /* Match ET_RX_RING0_POS */ 1425 rx_ring->rr_index = 0; 1426 rx_ring->rr_wrap = 1; 1427 1428 /* 1429 * RX intr moderation 1430 */ 1431 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1432 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1433 1434 return 0; 1435 } 1436 1437 int 1438 et_init_txdma(struct et_softc *sc) 1439 { 1440 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1441 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1442 int error; 1443 1444 error = et_stop_txdma(sc); 1445 if (error) { 1446 aprint_error_dev(sc->sc_dev, "can't init TX DMA engine\n"); 1447 return error; 1448 } 1449 1450 /* 1451 * Install TX descriptor ring 1452 */ 1453 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1454 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1455 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1456 1457 /* 1458 * Install TX status 1459 */ 1460 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1461 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1462 1463 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1464 1465 /* Match ET_TX_READY_POS */ 1466 tx_ring->tr_ready_index = 0; 1467 tx_ring->tr_ready_wrap = 0; 1468 1469 return 0; 1470 } 1471 1472 void 1473 et_init_mac(struct et_softc *sc) 1474 { 1475 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1476 const uint8_t *eaddr = CLLADDR(ifp->if_sadl); 1477 uint32_t val; 1478 1479 /* Reset MAC */ 1480 CSR_WRITE_4(sc, ET_MAC_CFG1, 1481 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1482 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1483 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1484 1485 /* 1486 * Setup inter packet gap 1487 */ 1488 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1489 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1490 __SHIFTIN(80, ET_IPG_MINIFG) | 1491 __SHIFTIN(96, ET_IPG_B2B); 1492 CSR_WRITE_4(sc, ET_IPG, val); 1493 1494 /* 1495 * Setup half duplex mode 1496 */ 1497 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1498 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1499 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1500 ET_MAC_HDX_EXC_DEFER; 1501 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1502 1503 /* Clear MAC control */ 1504 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1505 1506 /* Reset MII */ 1507 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1508 1509 /* 1510 * Set MAC address 1511 */ 1512 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1513 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1514 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1515 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1516 1517 /* Set max frame length */ 1518 CSR_WRITE_4(sc, ET_MAX_FRMLEN, 1519 ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + ETHER_CRC_LEN); 1520 1521 /* Bring MAC out of reset state */ 1522 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1523 } 1524 1525 void 1526 et_init_rxmac(struct et_softc *sc) 1527 { 1528 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1529 const uint8_t *eaddr = CLLADDR(ifp->if_sadl); 1530 uint32_t val; 1531 int i; 1532 1533 /* Disable RX MAC and WOL */ 1534 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1535 1536 /* 1537 * Clear all WOL related registers 1538 */ 1539 for (i = 0; i < 3; ++i) 1540 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1541 for (i = 0; i < 20; ++i) 1542 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1543 1544 /* 1545 * Set WOL source address. XXX is this necessary? 1546 */ 1547 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1548 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1549 val = (eaddr[0] << 8) | eaddr[1]; 1550 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1551 1552 /* Clear packet filters */ 1553 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1554 1555 /* No ucast filtering */ 1556 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1557 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1558 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1559 1560 if (ifp->if_mtu > 8192) { 1561 /* 1562 * In order to transmit jumbo packets greater than 8k, 1563 * the FIFO between RX MAC and RX DMA needs to be reduced 1564 * in size to (16k - MTU). In order to implement this, we 1565 * must use "cut through" mode in the RX MAC, which chops 1566 * packets down into segments which are (max_size * 16). 1567 * In this case we selected 256 bytes, since this is the 1568 * size of the PCI-Express TLP's that the 1310 uses. 1569 */ 1570 val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) | 1571 ET_RXMAC_MC_SEGSZ_ENABLE; 1572 } else { 1573 val = 0; 1574 } 1575 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1576 1577 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1578 1579 /* Initialize RX MAC management register */ 1580 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1581 1582 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1583 1584 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1585 ET_RXMAC_MGT_PASS_ECRC | 1586 ET_RXMAC_MGT_PASS_ELEN | 1587 ET_RXMAC_MGT_PASS_ETRUNC | 1588 ET_RXMAC_MGT_CHECK_PKT); 1589 1590 /* 1591 * Configure runt filtering (may not work on certain chip generation) 1592 */ 1593 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1594 CSR_WRITE_4(sc, ET_PKTFILT, val); 1595 1596 /* Enable RX MAC but leave WOL disabled */ 1597 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1598 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1599 1600 /* 1601 * Setup multicast hash and allmulti/promisc mode 1602 */ 1603 et_setmulti(sc); 1604 } 1605 1606 void 1607 et_init_txmac(struct et_softc *sc) 1608 { 1609 /* Disable TX MAC and FC(?) */ 1610 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1611 1612 /* No flow control yet */ 1613 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1614 1615 /* Enable TX MAC but leave FC(?) diabled */ 1616 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1617 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1618 } 1619 1620 int 1621 et_start_rxdma(struct et_softc *sc) 1622 { 1623 uint32_t val = 0; 1624 1625 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1626 ET_RXDMA_CTRL_RING0_SIZE) | 1627 ET_RXDMA_CTRL_RING0_ENABLE; 1628 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1629 ET_RXDMA_CTRL_RING1_SIZE) | 1630 ET_RXDMA_CTRL_RING1_ENABLE; 1631 1632 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1633 1634 DELAY(5); 1635 1636 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1637 aprint_error_dev(sc->sc_dev, "can't start RX DMA engine\n"); 1638 return ETIMEDOUT; 1639 } 1640 return 0; 1641 } 1642 1643 int 1644 et_start_txdma(struct et_softc *sc) 1645 { 1646 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1647 return 0; 1648 } 1649 1650 int 1651 et_enable_txrx(struct et_softc *sc) 1652 { 1653 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1654 uint32_t val; 1655 int i, rc = 0; 1656 1657 val = CSR_READ_4(sc, ET_MAC_CFG1); 1658 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1659 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1660 ET_MAC_CFG1_LOOPBACK); 1661 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1662 1663 if ((rc = ether_mediachange(ifp)) != 0) 1664 goto out; 1665 1666 #define NRETRY 100 1667 1668 for (i = 0; i < NRETRY; ++i) { 1669 val = CSR_READ_4(sc, ET_MAC_CFG1); 1670 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1671 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1672 break; 1673 1674 DELAY(10); 1675 } 1676 if (i == NRETRY) { 1677 aprint_error_dev(sc->sc_dev, "can't enable RX/TX\n"); 1678 return ETIMEDOUT; 1679 } 1680 1681 #undef NRETRY 1682 return 0; 1683 out: 1684 return rc; 1685 } 1686 1687 void 1688 et_rxeof(struct et_softc *sc) 1689 { 1690 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1691 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1692 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1693 uint32_t rxs_stat_ring; 1694 int rxst_wrap, rxst_index; 1695 1696 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1697 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1698 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1699 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1700 1701 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1702 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1703 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1704 1705 while (rxst_index != rxst_ring->rsr_index || 1706 rxst_wrap != rxst_ring->rsr_wrap) { 1707 struct et_rxbuf_data *rbd; 1708 struct et_rxdesc_ring *rx_ring; 1709 struct et_rxstat *st; 1710 struct et_rxbuf *rb; 1711 struct mbuf *m; 1712 int buflen, buf_idx, ring_idx; 1713 uint32_t rxstat_pos, rxring_pos; 1714 1715 KASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1716 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1717 1718 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1719 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1720 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1721 1722 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1723 rxst_ring->rsr_index = 0; 1724 rxst_ring->rsr_wrap ^= 1; 1725 } 1726 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1727 ET_RXSTAT_POS_INDEX); 1728 if (rxst_ring->rsr_wrap) 1729 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1730 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1731 1732 if (ring_idx >= ET_RX_NRING) { 1733 ifp->if_ierrors++; 1734 aprint_error_dev(sc->sc_dev, "invalid ring index %d\n", 1735 ring_idx); 1736 continue; 1737 } 1738 if (buf_idx >= ET_RX_NDESC) { 1739 ifp->if_ierrors++; 1740 aprint_error_dev(sc->sc_dev, "invalid buf index %d\n", 1741 buf_idx); 1742 continue; 1743 } 1744 1745 rbd = &sc->sc_rx_data[ring_idx]; 1746 rb = &rbd->rbd_buf[buf_idx]; 1747 m = rb->rb_mbuf; 1748 bus_dmamap_sync(sc->sc_dmat, rb->rb_dmap, 0, 1749 rb->rb_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1750 1751 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1752 if (buflen < ETHER_CRC_LEN) { 1753 m_freem(m); 1754 ifp->if_ierrors++; 1755 } else { 1756 m->m_pkthdr.len = m->m_len = buflen - 1757 ETHER_CRC_LEN; 1758 m_set_rcvif(m, ifp); 1759 1760 if_percpuq_enqueue(ifp->if_percpuq, m); 1761 } 1762 } else { 1763 ifp->if_ierrors++; 1764 } 1765 1766 rx_ring = &sc->sc_rx_ring[ring_idx]; 1767 1768 if (buf_idx != rx_ring->rr_index) { 1769 aprint_error_dev(sc->sc_dev, "WARNING!! ring %d, " 1770 "buf_idx %d, rr_idx %d\n", 1771 ring_idx, buf_idx, rx_ring->rr_index); 1772 } 1773 1774 KASSERT(rx_ring->rr_index < ET_RX_NDESC); 1775 if (++rx_ring->rr_index == ET_RX_NDESC) { 1776 rx_ring->rr_index = 0; 1777 rx_ring->rr_wrap ^= 1; 1778 } 1779 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1780 if (rx_ring->rr_wrap) 1781 rxring_pos |= ET_RX_RING_POS_WRAP; 1782 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1783 } 1784 } 1785 1786 int 1787 et_encap(struct et_softc *sc, struct mbuf **m0) 1788 { 1789 struct mbuf *m = *m0; 1790 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1791 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1792 struct et_txdesc *td; 1793 bus_dmamap_t map; 1794 int error, maxsegs, first_idx, last_idx, i; 1795 uint32_t tx_ready_pos, last_td_ctrl2; 1796 1797 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1798 if (maxsegs > ET_NSEG_MAX) 1799 maxsegs = ET_NSEG_MAX; 1800 KASSERTMSG(maxsegs >= ET_NSEG_SPARE, 1801 "not enough spare TX desc (%d)\n", maxsegs); 1802 1803 KASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1804 first_idx = tx_ring->tr_ready_index; 1805 map = tbd->tbd_buf[first_idx].tb_dmap; 1806 1807 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1808 BUS_DMA_NOWAIT); 1809 if (!error && map->dm_nsegs == 0) { 1810 bus_dmamap_unload(sc->sc_dmat, map); 1811 error = EFBIG; 1812 } 1813 if (error && error != EFBIG) { 1814 aprint_error_dev(sc->sc_dev, "can't load TX mbuf"); 1815 goto back; 1816 } 1817 if (error) { /* error == EFBIG */ 1818 struct mbuf *m_new; 1819 1820 error = 0; 1821 1822 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1823 if (m_new == NULL) { 1824 aprint_error_dev(sc->sc_dev, "can't defrag TX mbuf\n"); 1825 error = ENOBUFS; 1826 goto back; 1827 } 1828 1829 M_COPY_PKTHDR(m_new, m); 1830 if (m->m_pkthdr.len > MHLEN) { 1831 MCLGET(m_new, M_DONTWAIT); 1832 if (!(m_new->m_flags & M_EXT)) { 1833 m_freem(m_new); 1834 error = ENOBUFS; 1835 } 1836 } 1837 1838 if (error) { 1839 aprint_error_dev(sc->sc_dev, "can't defrag TX buffer\n"); 1840 goto back; 1841 } 1842 1843 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, void *)); 1844 m_freem(m); 1845 m_new->m_len = m_new->m_pkthdr.len; 1846 *m0 = m = m_new; 1847 1848 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1849 BUS_DMA_NOWAIT); 1850 if (error || map->dm_nsegs == 0) { 1851 if (map->dm_nsegs == 0) { 1852 bus_dmamap_unload(sc->sc_dmat, map); 1853 error = EFBIG; 1854 } 1855 aprint_error_dev(sc->sc_dev, "can't load defraged TX mbuf\n"); 1856 goto back; 1857 } 1858 } 1859 1860 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1861 BUS_DMASYNC_PREWRITE); 1862 1863 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1864 sc->sc_tx += map->dm_nsegs; 1865 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1866 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1867 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1868 } 1869 1870 last_idx = -1; 1871 for (i = 0; i < map->dm_nsegs; ++i) { 1872 int idx; 1873 1874 idx = (first_idx + i) % ET_TX_NDESC; 1875 td = &tx_ring->tr_desc[idx]; 1876 td->td_addr_hi = ET_ADDR_HI(map->dm_segs[i].ds_addr); 1877 td->td_addr_lo = ET_ADDR_LO(map->dm_segs[i].ds_addr); 1878 td->td_ctrl1 = 1879 __SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN); 1880 1881 if (i == map->dm_nsegs - 1) { /* Last frag */ 1882 td->td_ctrl2 = last_td_ctrl2; 1883 last_idx = idx; 1884 } 1885 1886 KASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1887 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1888 tx_ring->tr_ready_index = 0; 1889 tx_ring->tr_ready_wrap ^= 1; 1890 } 1891 } 1892 td = &tx_ring->tr_desc[first_idx]; 1893 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1894 1895 KASSERT(last_idx >= 0); 1896 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1897 tbd->tbd_buf[last_idx].tb_dmap = map; 1898 tbd->tbd_buf[last_idx].tb_mbuf = m; 1899 1900 tbd->tbd_used += map->dm_nsegs; 1901 KASSERT(tbd->tbd_used <= ET_TX_NDESC); 1902 1903 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1904 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1905 1906 1907 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 1908 ET_TX_READY_POS_INDEX); 1909 if (tx_ring->tr_ready_wrap) 1910 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1911 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1912 1913 error = 0; 1914 back: 1915 if (error) { 1916 m_freem(m); 1917 *m0 = NULL; 1918 } 1919 return error; 1920 } 1921 1922 void 1923 et_txeof(struct et_softc *sc) 1924 { 1925 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1926 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1927 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1928 uint32_t tx_done; 1929 int end, wrap; 1930 1931 if (tbd->tbd_used == 0) 1932 return; 1933 1934 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 1935 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 1936 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 1937 1938 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 1939 struct et_txbuf *tb; 1940 1941 KASSERT(tbd->tbd_start_index < ET_TX_NDESC); 1942 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 1943 1944 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 1945 sizeof(struct et_txdesc)); 1946 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1947 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1948 1949 if (tb->tb_mbuf != NULL) { 1950 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1951 m_freem(tb->tb_mbuf); 1952 tb->tb_mbuf = NULL; 1953 ifp->if_opackets++; 1954 } 1955 1956 if (++tbd->tbd_start_index == ET_TX_NDESC) { 1957 tbd->tbd_start_index = 0; 1958 tbd->tbd_start_wrap ^= 1; 1959 } 1960 1961 KASSERT(tbd->tbd_used > 0); 1962 tbd->tbd_used--; 1963 } 1964 1965 if (tbd->tbd_used == 0) { 1966 callout_stop(&sc->sc_txtick); 1967 ifp->if_timer = 0; 1968 } 1969 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 1970 ifp->if_flags &= ~IFF_OACTIVE; 1971 1972 if_schedule_deferred_start(ifp); 1973 } 1974 1975 void 1976 et_txtick(void *xsc) 1977 { 1978 struct et_softc *sc = xsc; 1979 int s; 1980 1981 s = splnet(); 1982 et_txeof(sc); 1983 splx(s); 1984 } 1985 1986 void 1987 et_tick(void *xsc) 1988 { 1989 struct et_softc *sc = xsc; 1990 int s; 1991 1992 s = splnet(); 1993 mii_tick(&sc->sc_miibus); 1994 callout_schedule(&sc->sc_tick, hz); 1995 splx(s); 1996 } 1997 1998 int 1999 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 2000 { 2001 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 2002 } 2003 2004 int 2005 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 2006 { 2007 return et_newbuf(rbd, buf_idx, init, MHLEN); 2008 } 2009 2010 int 2011 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 2012 { 2013 struct et_softc *sc = rbd->rbd_softc; 2014 struct et_rxdesc_ring *rx_ring; 2015 struct et_rxdesc *desc; 2016 struct et_rxbuf *rb; 2017 struct mbuf *m; 2018 bus_dmamap_t dmap; 2019 int error, len; 2020 2021 KASSERT(buf_idx < ET_RX_NDESC); 2022 rb = &rbd->rbd_buf[buf_idx]; 2023 2024 if (len0 >= MINCLSIZE) { 2025 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2026 if (m == NULL) 2027 return (ENOBUFS); 2028 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2029 if ((m->m_flags & M_EXT) == 0) { 2030 m_freem(m); 2031 return (ENOBUFS); 2032 } 2033 len = MCLBYTES; 2034 } else { 2035 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2036 len = MHLEN; 2037 } 2038 2039 if (m == NULL) { 2040 error = ENOBUFS; 2041 2042 /* XXX for debug */ 2043 aprint_error_dev(sc->sc_dev, "M_CLGET failed, size %d\n", len0); 2044 if (init) { 2045 return error; 2046 } else { 2047 goto back; 2048 } 2049 } 2050 m->m_len = m->m_pkthdr.len = len; 2051 2052 /* 2053 * Try load RX mbuf into temporary DMA tag 2054 */ 2055 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_mbuf_tmp_dmap, m, 2056 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2057 if (error) { 2058 m_freem(m); 2059 2060 /* XXX for debug */ 2061 aprint_error_dev(sc->sc_dev, "can't load RX mbuf\n"); 2062 if (init) { 2063 return error; 2064 } else { 2065 goto back; 2066 } 2067 } 2068 2069 if (!init) 2070 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 2071 rb->rb_mbuf = m; 2072 2073 /* 2074 * Swap RX buf's DMA map with the loaded temporary one 2075 */ 2076 dmap = rb->rb_dmap; 2077 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2078 rb->rb_paddr = rb->rb_dmap->dm_segs[0].ds_addr; 2079 sc->sc_mbuf_tmp_dmap = dmap; 2080 2081 error = 0; 2082 back: 2083 rx_ring = rbd->rbd_ring; 2084 desc = &rx_ring->rr_desc[buf_idx]; 2085 2086 desc->rd_addr_hi = ET_ADDR_HI(rb->rb_paddr); 2087 desc->rd_addr_lo = ET_ADDR_LO(rb->rb_paddr); 2088 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2089 2090 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 2091 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2092 return error; 2093 } 2094
Indexes created Fri Oct 03 02:09:57 GMT 2025