if_et.c revision 1.25
1 /* $NetBSD: if_et.c,v 1.25 2019/07/31 16:08:23 msaitoh Exp $ */ 2 /* $OpenBSD: if_et.c,v 1.11 2008/06/08 06:18:07 jsg Exp $ */ 3 /* 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa (at) gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: if_et.c,v 1.25 2019/07/31 16:08:23 msaitoh Exp $"); 41 42 #include "opt_inet.h" 43 #include "vlan.h" 44 45 #include <sys/param.h> 46 #include <sys/endian.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/sockio.h> 50 #include <sys/mbuf.h> 51 #include <sys/queue.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 #include <sys/socket.h> 56 57 #include <sys/bus.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 #include <net/if_arp.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #include <net/bpf.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcidevs.h> 81 82 #include <dev/pci/if_etreg.h> 83 84 int et_match(device_t, cfdata_t, void *); 85 void et_attach(device_t, device_t, void *); 86 int et_detach(device_t, int flags); 87 int et_shutdown(device_t); 88 89 int et_miibus_readreg(device_t, int, int, uint16_t *); 90 int et_miibus_writereg(device_t, int, int, uint16_t); 91 void et_miibus_statchg(struct ifnet *); 92 93 int et_init(struct ifnet *ifp); 94 int et_ioctl(struct ifnet *, u_long, void *); 95 void et_start(struct ifnet *); 96 void et_watchdog(struct ifnet *); 97 98 int et_intr(void *); 99 void et_enable_intrs(struct et_softc *, uint32_t); 100 void et_disable_intrs(struct et_softc *); 101 void et_rxeof(struct et_softc *); 102 void et_txeof(struct et_softc *); 103 void et_txtick(void *); 104 105 int et_dma_alloc(struct et_softc *); 106 void et_dma_free(struct et_softc *); 107 int et_dma_mem_create(struct et_softc *, bus_size_t, 108 void **, bus_addr_t *, bus_dmamap_t *, bus_dma_segment_t *); 109 void et_dma_mem_destroy(struct et_softc *, void *, bus_dmamap_t); 110 int et_dma_mbuf_create(struct et_softc *); 111 void et_dma_mbuf_destroy(struct et_softc *, int, const int[]); 112 113 int et_init_tx_ring(struct et_softc *); 114 int et_init_rx_ring(struct et_softc *); 115 void et_free_tx_ring(struct et_softc *); 116 void et_free_rx_ring(struct et_softc *); 117 int et_encap(struct et_softc *, struct mbuf **); 118 int et_newbuf(struct et_rxbuf_data *, int, int, int); 119 int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 120 int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 121 122 void et_stop(struct et_softc *); 123 int et_chip_init(struct et_softc *); 124 void et_chip_attach(struct et_softc *); 125 void et_init_mac(struct et_softc *); 126 void et_init_rxmac(struct et_softc *); 127 void et_init_txmac(struct et_softc *); 128 int et_init_rxdma(struct et_softc *); 129 int et_init_txdma(struct et_softc *); 130 int et_start_rxdma(struct et_softc *); 131 int et_start_txdma(struct et_softc *); 132 int et_stop_rxdma(struct et_softc *); 133 int et_stop_txdma(struct et_softc *); 134 int et_enable_txrx(struct et_softc *); 135 void et_reset(struct et_softc *); 136 int et_bus_config(struct et_softc *); 137 void et_get_eaddr(struct et_softc *, uint8_t[]); 138 void et_setmulti(struct et_softc *); 139 void et_tick(void *); 140 141 static int et_rx_intr_npkts = 32; 142 static int et_rx_intr_delay = 20; /* x10 usec */ 143 static int et_tx_intr_nsegs = 128; 144 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 145 146 struct et_bsize { 147 int bufsize; 148 et_newbuf_t newbuf; 149 }; 150 151 static const struct et_bsize et_bufsize[ET_RX_NRING] = { 152 { .bufsize = 0, .newbuf = et_newbuf_hdr }, 153 { .bufsize = 0, .newbuf = et_newbuf_cluster }, 154 }; 155 156 const struct et_product { 157 pci_vendor_id_t vendor; 158 pci_product_id_t product; 159 } et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310 }, 161 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1301 } 162 }; 163 164 CFATTACH_DECL_NEW(et, sizeof(struct et_softc), et_match, et_attach, et_detach, 165 NULL); 166 167 int 168 et_match(device_t dev, cfdata_t match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 const struct et_product *ep; 172 int i; 173 174 for (i = 0; i < __arraycount(et_devices); i++) { 175 ep = &et_devices[i]; 176 if (PCI_VENDOR(pa->pa_id) == ep->vendor && 177 PCI_PRODUCT(pa->pa_id) == ep->product) 178 return 1; 179 } 180 return 0; 181 } 182 183 void 184 et_attach(device_t parent, device_t self, void *aux) 185 { 186 struct et_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 pci_intr_handle_t ih; 190 const char *intrstr; 191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 192 struct mii_data * const mii = &sc->sc_miibus; 193 pcireg_t memtype; 194 int error; 195 char intrbuf[PCI_INTRSTR_LEN]; 196 197 pci_aprint_devinfo(pa, "Ethernet controller"); 198 199 sc->sc_dev = self; 200 201 /* 202 * Initialize tunables 203 */ 204 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 205 sc->sc_rx_intr_delay = et_rx_intr_delay; 206 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 207 sc->sc_timer = et_timer; 208 209 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ET_PCIR_BAR); 210 if (pci_mapreg_map(pa, ET_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 211 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 212 aprint_error_dev(self, "could not map mem space\n"); 213 return; 214 } 215 216 if (pci_intr_map(pa, &ih) != 0) { 217 aprint_error_dev(self, "could not map interrupt\n"); 218 goto fail; 219 } 220 221 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 222 sc->sc_irq_handle = pci_intr_establish_xname(pc, ih, IPL_NET, et_intr, 223 sc, device_xname(self)); 224 if (sc->sc_irq_handle == NULL) { 225 aprint_error_dev(self, "could not establish interrupt"); 226 if (intrstr != NULL) 227 aprint_error(" at %s", intrstr); 228 aprint_error("\n"); 229 goto fail; 230 } 231 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 232 233 sc->sc_dmat = pa->pa_dmat; 234 sc->sc_pct = pa->pa_pc; 235 sc->sc_pcitag = pa->pa_tag; 236 237 error = et_bus_config(sc); 238 if (error) 239 goto fail; 240 241 et_get_eaddr(sc, sc->sc_enaddr); 242 243 aprint_normal_dev(self, "Ethernet address %s\n", 244 ether_sprintf(sc->sc_enaddr)); 245 246 CSR_WRITE_4(sc, ET_PM, 247 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 248 249 et_reset(sc); 250 251 et_disable_intrs(sc); 252 253 error = et_dma_alloc(sc); 254 if (error) 255 goto fail; 256 257 ifp->if_softc = sc; 258 ifp->if_mtu = ETHERMTU; 259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 ifp->if_init = et_init; 261 ifp->if_ioctl = et_ioctl; 262 ifp->if_start = et_start; 263 ifp->if_watchdog = et_watchdog; 264 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 265 IFQ_SET_READY(&ifp->if_snd); 266 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 267 268 et_chip_attach(sc); 269 270 mii->mii_ifp = ifp; 271 mii->mii_readreg = et_miibus_readreg; 272 mii->mii_writereg = et_miibus_writereg; 273 mii->mii_statchg = et_miibus_statchg; 274 275 sc->sc_ethercom.ec_mii = mii; 276 ifmedia_init(&mii->mii_media, 0, ether_mediachange, 277 ether_mediastatus); 278 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 279 if (LIST_FIRST(&mii->mii_phys) == NULL) { 280 aprint_error_dev(self, "no PHY found!\n"); 281 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 282 0, NULL); 283 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 284 } else 285 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 286 287 if_attach(ifp); 288 if_deferred_start_init(ifp, NULL); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 callout_init(&sc->sc_tick, 0); 292 callout_setfunc(&sc->sc_tick, et_tick, sc); 293 callout_init(&sc->sc_txtick, 0); 294 callout_setfunc(&sc->sc_txtick, et_txtick, sc); 295 296 if (pmf_device_register(self, NULL, NULL)) 297 pmf_class_network_register(self, ifp); 298 else 299 aprint_error_dev(self, "couldn't establish power handler\n"); 300 301 return; 302 303 fail: 304 et_dma_free(sc); 305 if (sc->sc_irq_handle != NULL) { 306 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 307 sc->sc_irq_handle = NULL; 308 } 309 if (sc->sc_mem_size) { 310 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 311 sc->sc_mem_size = 0; 312 } 313 } 314 315 int 316 et_detach(device_t self, int flags) 317 { 318 struct et_softc *sc = device_private(self); 319 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 320 int s; 321 322 pmf_device_deregister(self); 323 s = splnet(); 324 et_stop(sc); 325 splx(s); 326 327 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 328 329 /* Delete all remaining media. */ 330 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 331 332 ether_ifdetach(ifp); 333 if_detach(ifp); 334 et_dma_free(sc); 335 336 if (sc->sc_irq_handle != NULL) { 337 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 338 sc->sc_irq_handle = NULL; 339 } 340 341 if (sc->sc_mem_size) { 342 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 343 sc->sc_mem_size = 0; 344 } 345 346 return 0; 347 } 348 349 int 350 et_shutdown(device_t self) 351 { 352 struct et_softc *sc = device_private(self); 353 int s; 354 355 s = splnet(); 356 et_stop(sc); 357 splx(s); 358 359 return 0; 360 } 361 362 int 363 et_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 364 { 365 struct et_softc *sc = device_private(dev); 366 uint32_t data; 367 int i, ret; 368 369 /* Stop any pending operations */ 370 CSR_WRITE_4(sc, ET_MII_CMD, 0); 371 372 data = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 373 __SHIFTIN(reg, ET_MII_ADDR_REG); 374 CSR_WRITE_4(sc, ET_MII_ADDR, data); 375 376 /* Start reading */ 377 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 378 379 #define NRETRY 50 380 381 for (i = 0; i < NRETRY; ++i) { 382 data = CSR_READ_4(sc, ET_MII_IND); 383 if ((data & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 384 break; 385 DELAY(50); 386 } 387 if (i == NRETRY) { 388 aprint_error_dev(sc->sc_dev, "read phy %d, reg %d timed out\n", 389 phy, reg); 390 ret = ETIMEDOUT; 391 goto back; 392 } 393 394 #undef NRETRY 395 396 data = CSR_READ_4(sc, ET_MII_STAT); 397 *val = __SHIFTOUT(data, ET_MII_STAT_VALUE); 398 ret = 0; 399 400 back: 401 /* Make sure that the current operation is stopped */ 402 CSR_WRITE_4(sc, ET_MII_CMD, 0); 403 return ret; 404 } 405 406 int 407 et_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 408 { 409 struct et_softc *sc = device_private(dev); 410 uint32_t data; 411 uint16_t tmp; 412 int rv = 0; 413 int i; 414 415 /* Stop any pending operations */ 416 CSR_WRITE_4(sc, ET_MII_CMD, 0); 417 418 data = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 419 __SHIFTIN(reg, ET_MII_ADDR_REG); 420 CSR_WRITE_4(sc, ET_MII_ADDR, data); 421 422 /* Start writing */ 423 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val, ET_MII_CTRL_VALUE)); 424 425 #define NRETRY 100 426 427 for (i = 0; i < NRETRY; ++i) { 428 data = CSR_READ_4(sc, ET_MII_IND); 429 if ((data & ET_MII_IND_BUSY) == 0) 430 break; 431 DELAY(50); 432 } 433 if (i == NRETRY) { 434 aprint_error_dev(sc->sc_dev, "write phy %d, reg %d timed out\n", 435 phy, reg); 436 et_miibus_readreg(dev, phy, reg, &tmp); 437 rv = ETIMEDOUT; 438 } 439 440 #undef NRETRY 441 442 /* Make sure that the current operation is stopped */ 443 CSR_WRITE_4(sc, ET_MII_CMD, 0); 444 445 return rv; 446 } 447 448 void 449 et_miibus_statchg(struct ifnet *ifp) 450 { 451 struct et_softc *sc = ifp->if_softc; 452 struct mii_data *mii = &sc->sc_miibus; 453 uint32_t cfg2, ctrl; 454 455 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 456 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 457 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 458 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 459 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 460 461 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 462 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 463 464 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 465 cfg2 |= ET_MAC_CFG2_MODE_GMII; 466 } else { 467 cfg2 |= ET_MAC_CFG2_MODE_MII; 468 ctrl |= ET_MAC_CTRL_MODE_MII; 469 } 470 471 if ((mii->mii_media_active & IFM_FDX) != 0) 472 cfg2 |= ET_MAC_CFG2_FDX; 473 else 474 ctrl |= ET_MAC_CTRL_GHDX; 475 476 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 477 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 478 } 479 480 void 481 et_stop(struct et_softc *sc) 482 { 483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 484 485 callout_stop(&sc->sc_tick); 486 callout_stop(&sc->sc_txtick); 487 488 et_stop_rxdma(sc); 489 et_stop_txdma(sc); 490 491 et_disable_intrs(sc); 492 493 et_free_tx_ring(sc); 494 et_free_rx_ring(sc); 495 496 et_reset(sc); 497 498 sc->sc_tx = 0; 499 sc->sc_tx_intr = 0; 500 501 ifp->if_timer = 0; 502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 503 } 504 505 int 506 et_bus_config(struct et_softc *sc) 507 { 508 uint32_t val; //, max_plsz; 509 // uint16_t ack_latency, replay_timer; 510 511 /* 512 * Test whether EEPROM is valid 513 * NOTE: Read twice to get the correct value 514 */ 515 pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 516 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 517 518 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 519 aprint_error_dev(sc->sc_dev, "EEPROM status error 0x%02x\n", val); 520 return ENXIO; 521 } 522 523 /* TODO: LED */ 524 #if 0 525 /* 526 * Configure ACK latency and replay timer according to 527 * max playload size 528 */ 529 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CAPS); 530 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 531 532 switch (max_plsz) { 533 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 534 ack_latency = ET_PCIV_ACK_LATENCY_128; 535 replay_timer = ET_PCIV_REPLAY_TIMER_128; 536 break; 537 538 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 539 ack_latency = ET_PCIV_ACK_LATENCY_256; 540 replay_timer = ET_PCIV_REPLAY_TIMER_256; 541 break; 542 543 default: 544 ack_latency = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 545 ET_PCIR_ACK_LATENCY) >> 16; 546 replay_timer = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 547 ET_PCIR_REPLAY_TIMER) >> 16; 548 aprint_normal_dev(sc->sc_dev, "ack latency %u, replay timer %u\n", 549 ack_latency, replay_timer); 550 break; 551 } 552 if (ack_latency != 0) { 553 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 554 ET_PCIR_ACK_LATENCY, ack_latency << 16); 555 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 556 ET_PCIR_REPLAY_TIMER, replay_timer << 16); 557 } 558 559 /* 560 * Set L0s and L1 latency timer to 2us 561 */ 562 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 563 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_L0S_L1_LATENCY, 564 val << 24); 565 566 /* 567 * Set max read request size to 2048 bytes 568 */ 569 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 570 ET_PCIR_DEVICE_CTRL) >> 16; 571 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 572 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 573 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CTRL, 574 val << 16); 575 #endif 576 577 return 0; 578 } 579 580 void 581 et_get_eaddr(struct et_softc *sc, uint8_t eaddr[]) 582 { 583 uint32_t r; 584 585 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_LO); 586 eaddr[0] = r & 0xff; 587 eaddr[1] = (r >> 8) & 0xff; 588 eaddr[2] = (r >> 16) & 0xff; 589 eaddr[3] = (r >> 24) & 0xff; 590 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_HI); 591 eaddr[4] = r & 0xff; 592 eaddr[5] = (r >> 8) & 0xff; 593 } 594 595 void 596 et_reset(struct et_softc *sc) 597 { 598 CSR_WRITE_4(sc, ET_MAC_CFG1, 599 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 600 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 601 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 602 603 CSR_WRITE_4(sc, ET_SWRST, 604 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 605 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 606 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 607 608 CSR_WRITE_4(sc, ET_MAC_CFG1, 609 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 610 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 611 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 612 } 613 614 void 615 et_disable_intrs(struct et_softc *sc) 616 { 617 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 618 } 619 620 void 621 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 622 { 623 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 624 } 625 626 int 627 et_dma_alloc(struct et_softc *sc) 628 { 629 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 630 struct et_txstatus_data *txsd = &sc->sc_tx_status; 631 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 632 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 633 int i, error; 634 635 /* 636 * Create TX ring DMA stuffs 637 */ 638 error = et_dma_mem_create(sc, ET_TX_RING_SIZE, 639 (void **)&tx_ring->tr_desc, &tx_ring->tr_paddr, &tx_ring->tr_dmap, 640 &tx_ring->tr_seg); 641 if (error) { 642 aprint_error_dev(sc->sc_dev, "can't create TX ring DMA stuffs\n"); 643 return error; 644 } 645 646 /* 647 * Create TX status DMA stuffs 648 */ 649 error = et_dma_mem_create(sc, sizeof(uint32_t), 650 (void **)&txsd->txsd_status, 651 &txsd->txsd_paddr, &txsd->txsd_dmap, &txsd->txsd_seg); 652 if (error) { 653 aprint_error_dev(sc->sc_dev, "can't create TX status DMA stuffs\n"); 654 return error; 655 } 656 657 /* 658 * Create DMA stuffs for RX rings 659 */ 660 for (i = 0; i < ET_RX_NRING; ++i) { 661 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 662 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 663 664 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 665 666 error = et_dma_mem_create(sc, ET_RX_RING_SIZE, 667 (void **)&rx_ring->rr_desc, 668 &rx_ring->rr_paddr, &rx_ring->rr_dmap, &rx_ring->rr_seg); 669 if (error) { 670 aprint_error_dev(sc->sc_dev, "can't create DMA stuffs for " 671 "the %d RX ring\n", i); 672 return error; 673 } 674 rx_ring->rr_posreg = rx_ring_posreg[i]; 675 } 676 677 /* 678 * Create RX stat ring DMA stuffs 679 */ 680 error = et_dma_mem_create(sc, ET_RXSTAT_RING_SIZE, 681 (void **)&rxst_ring->rsr_stat, 682 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap, &rxst_ring->rsr_seg); 683 if (error) { 684 aprint_error_dev(sc->sc_dev, "can't create RX stat ring DMA stuffs\n"); 685 return error; 686 } 687 688 /* 689 * Create RX status DMA stuffs 690 */ 691 error = et_dma_mem_create(sc, sizeof(struct et_rxstatus), 692 (void **)&rxsd->rxsd_status, 693 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap, &rxsd->rxsd_seg); 694 if (error) { 695 aprint_error_dev(sc->sc_dev, "can't create RX status DMA stuffs\n"); 696 return error; 697 } 698 699 /* 700 * Create mbuf DMA stuffs 701 */ 702 error = et_dma_mbuf_create(sc); 703 if (error) 704 return error; 705 706 return 0; 707 } 708 709 void 710 et_dma_free(struct et_softc *sc) 711 { 712 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 713 struct et_txstatus_data *txsd = &sc->sc_tx_status; 714 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 715 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 716 int i, rx_done[ET_RX_NRING]; 717 718 /* 719 * Destroy TX ring DMA stuffs 720 */ 721 et_dma_mem_destroy(sc, tx_ring->tr_desc, tx_ring->tr_dmap); 722 723 /* 724 * Destroy TX status DMA stuffs 725 */ 726 et_dma_mem_destroy(sc, txsd->txsd_status, txsd->txsd_dmap); 727 728 /* 729 * Destroy DMA stuffs for RX rings 730 */ 731 for (i = 0; i < ET_RX_NRING; ++i) { 732 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 733 734 et_dma_mem_destroy(sc, rx_ring->rr_desc, rx_ring->rr_dmap); 735 } 736 737 /* 738 * Destroy RX stat ring DMA stuffs 739 */ 740 et_dma_mem_destroy(sc, rxst_ring->rsr_stat, rxst_ring->rsr_dmap); 741 742 /* 743 * Destroy RX status DMA stuffs 744 */ 745 et_dma_mem_destroy(sc, rxsd->rxsd_status, rxsd->rxsd_dmap); 746 747 /* 748 * Destroy mbuf DMA stuffs 749 */ 750 for (i = 0; i < ET_RX_NRING; ++i) 751 rx_done[i] = ET_RX_NDESC; 752 et_dma_mbuf_destroy(sc, ET_TX_NDESC, rx_done); 753 } 754 755 int 756 et_dma_mbuf_create(struct et_softc *sc) 757 { 758 struct et_txbuf_data *tbd = &sc->sc_tx_data; 759 int i, error, rx_done[ET_RX_NRING]; 760 761 /* 762 * Create spare DMA map for RX mbufs 763 */ 764 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 765 BUS_DMA_NOWAIT, &sc->sc_mbuf_tmp_dmap); 766 if (error) { 767 aprint_error_dev(sc->sc_dev, "can't create spare mbuf DMA map\n"); 768 return error; 769 } 770 771 /* 772 * Create DMA maps for RX mbufs 773 */ 774 bzero(rx_done, sizeof(rx_done)); 775 for (i = 0; i < ET_RX_NRING; ++i) { 776 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 777 int j; 778 779 for (j = 0; j < ET_RX_NDESC; ++j) { 780 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 781 MCLBYTES, 0, BUS_DMA_NOWAIT, 782 &rbd->rbd_buf[j].rb_dmap); 783 if (error) { 784 aprint_error_dev(sc->sc_dev, "can't create %d RX mbuf " 785 "for %d RX ring\n", j, i); 786 rx_done[i] = j; 787 et_dma_mbuf_destroy(sc, 0, rx_done); 788 return error; 789 } 790 } 791 rx_done[i] = ET_RX_NDESC; 792 793 rbd->rbd_softc = sc; 794 rbd->rbd_ring = &sc->sc_rx_ring[i]; 795 } 796 797 /* 798 * Create DMA maps for TX mbufs 799 */ 800 for (i = 0; i < ET_TX_NDESC; ++i) { 801 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 802 0, BUS_DMA_NOWAIT, &tbd->tbd_buf[i].tb_dmap); 803 if (error) { 804 aprint_error_dev(sc->sc_dev, "can't create %d TX mbuf " 805 "DMA map\n", i); 806 et_dma_mbuf_destroy(sc, i, rx_done); 807 return error; 808 } 809 } 810 811 return 0; 812 } 813 814 void 815 et_dma_mbuf_destroy(struct et_softc *sc, int tx_done, const int rx_done[]) 816 { 817 struct et_txbuf_data *tbd = &sc->sc_tx_data; 818 int i; 819 820 /* 821 * Destroy DMA maps for RX mbufs 822 */ 823 for (i = 0; i < ET_RX_NRING; ++i) { 824 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 825 int j; 826 827 for (j = 0; j < rx_done[i]; ++j) { 828 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 829 830 KASSERTMSG(rb->rb_mbuf == NULL, 831 "RX mbuf in %d RX ring is not freed yet\n", i); 832 bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); 833 } 834 } 835 836 /* 837 * Destroy DMA maps for TX mbufs 838 */ 839 for (i = 0; i < tx_done; ++i) { 840 struct et_txbuf *tb = &tbd->tbd_buf[i]; 841 842 KASSERTMSG(tb->tb_mbuf == NULL, "TX mbuf is not freed yet\n"); 843 bus_dmamap_destroy(sc->sc_dmat, tb->tb_dmap); 844 } 845 846 /* 847 * Destroy spare mbuf DMA map 848 */ 849 bus_dmamap_destroy(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 850 } 851 852 int 853 et_dma_mem_create(struct et_softc *sc, bus_size_t size, 854 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap, bus_dma_segment_t *seg) 855 { 856 int error, nsegs; 857 858 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 859 dmap); 860 if (error) { 861 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 862 return error; 863 } 864 865 error = bus_dmamem_alloc(sc->sc_dmat, size, ET_ALIGN, 0, seg, 866 1, &nsegs, BUS_DMA_WAITOK); 867 if (error) { 868 aprint_error_dev(sc->sc_dev, "can't allocate DMA mem\n"); 869 return error; 870 } 871 872 error = bus_dmamem_map(sc->sc_dmat, seg, nsegs, 873 size, (void **)addr, BUS_DMA_NOWAIT); 874 if (error) { 875 aprint_error_dev(sc->sc_dev, "can't map DMA mem\n"); 876 return (error); 877 } 878 879 error = bus_dmamap_load(sc->sc_dmat, *dmap, *addr, size, NULL, 880 BUS_DMA_WAITOK); 881 if (error) { 882 aprint_error_dev(sc->sc_dev, "can't load DMA mem\n"); 883 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)addr, 1); 884 return error; 885 } 886 887 memset(*addr, 0, size); 888 889 *paddr = (*dmap)->dm_segs[0].ds_addr; 890 891 return 0; 892 } 893 894 void 895 et_dma_mem_destroy(struct et_softc *sc, void *addr, bus_dmamap_t dmap) 896 { 897 bus_dmamap_unload(sc->sc_dmat, dmap); 898 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&addr, 1); 899 } 900 901 void 902 et_chip_attach(struct et_softc *sc) 903 { 904 uint32_t val; 905 906 /* 907 * Perform minimal initialization 908 */ 909 910 /* Disable loopback */ 911 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 912 913 /* Reset MAC */ 914 CSR_WRITE_4(sc, ET_MAC_CFG1, 915 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 916 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 917 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 918 919 /* 920 * Setup half duplex mode 921 */ 922 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 923 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 924 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 925 ET_MAC_HDX_EXC_DEFER; 926 CSR_WRITE_4(sc, ET_MAC_HDX, val); 927 928 /* Clear MAC control */ 929 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 930 931 /* Reset MII */ 932 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 933 934 /* Bring MAC out of reset state */ 935 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 936 937 /* Enable memory controllers */ 938 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 939 } 940 941 int 942 et_intr(void *xsc) 943 { 944 struct et_softc *sc = xsc; 945 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 946 uint32_t intrs; 947 948 if ((ifp->if_flags & IFF_RUNNING) == 0) 949 return (0); 950 951 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 952 if (intrs == 0 || intrs == 0xffffffff) 953 return (0); 954 955 et_disable_intrs(sc); 956 intrs &= ET_INTRS; 957 if (intrs == 0) /* Not interested */ 958 goto back; 959 960 if (intrs & ET_INTR_RXEOF) 961 et_rxeof(sc); 962 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 963 et_txeof(sc); 964 if (intrs & ET_INTR_TIMER) 965 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 966 back: 967 et_enable_intrs(sc, ET_INTRS); 968 969 return (1); 970 } 971 972 int 973 et_init(struct ifnet *ifp) 974 { 975 struct et_softc *sc = ifp->if_softc; 976 int error, i, s; 977 978 if (ifp->if_flags & IFF_RUNNING) 979 return 0; 980 981 s = splnet(); 982 983 et_stop(sc); 984 985 for (i = 0; i < ET_RX_NRING; ++i) { 986 sc->sc_rx_data[i].rbd_bufsize = et_bufsize[i].bufsize; 987 sc->sc_rx_data[i].rbd_newbuf = et_bufsize[i].newbuf; 988 } 989 990 error = et_init_tx_ring(sc); 991 if (error) 992 goto back; 993 994 error = et_init_rx_ring(sc); 995 if (error) 996 goto back; 997 998 error = et_chip_init(sc); 999 if (error) 1000 goto back; 1001 1002 error = et_enable_txrx(sc); 1003 if (error) 1004 goto back; 1005 1006 error = et_start_rxdma(sc); 1007 if (error) 1008 goto back; 1009 1010 error = et_start_txdma(sc); 1011 if (error) 1012 goto back; 1013 1014 et_enable_intrs(sc, ET_INTRS); 1015 1016 callout_schedule(&sc->sc_tick, hz); 1017 1018 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1019 1020 ifp->if_flags |= IFF_RUNNING; 1021 ifp->if_flags &= ~IFF_OACTIVE; 1022 back: 1023 if (error) 1024 et_stop(sc); 1025 1026 splx(s); 1027 1028 return (0); 1029 } 1030 1031 int 1032 et_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1033 { 1034 struct et_softc *sc = ifp->if_softc; 1035 int s, error = 0; 1036 1037 s = splnet(); 1038 1039 switch (cmd) { 1040 case SIOCSIFFLAGS: 1041 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1042 break; 1043 if (ifp->if_flags & IFF_UP) { 1044 /* 1045 * If only the PROMISC or ALLMULTI flag changes, then 1046 * don't do a full re-init of the chip, just update 1047 * the Rx filter. 1048 */ 1049 if ((ifp->if_flags & IFF_RUNNING) && 1050 ((ifp->if_flags ^ sc->sc_if_flags) & 1051 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1052 et_setmulti(sc); 1053 } else { 1054 if (!(ifp->if_flags & IFF_RUNNING)) 1055 et_init(ifp); 1056 } 1057 } else { 1058 if (ifp->if_flags & IFF_RUNNING) 1059 et_stop(sc); 1060 } 1061 sc->sc_if_flags = ifp->if_flags; 1062 break; 1063 default: 1064 error = ether_ioctl(ifp, cmd, data); 1065 if (error == ENETRESET) { 1066 if (ifp->if_flags & IFF_RUNNING) 1067 et_setmulti(sc); 1068 error = 0; 1069 } 1070 break; 1071 1072 } 1073 1074 splx(s); 1075 1076 return error; 1077 } 1078 1079 void 1080 et_start(struct ifnet *ifp) 1081 { 1082 struct et_softc *sc = ifp->if_softc; 1083 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1084 int trans; 1085 struct mbuf *m; 1086 1087 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1088 return; 1089 1090 trans = 0; 1091 for (;;) { 1092 IFQ_DEQUEUE(&ifp->if_snd, m); 1093 if (m == NULL) 1094 break; 1095 1096 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1097 ifp->if_flags |= IFF_OACTIVE; 1098 break; 1099 } 1100 1101 if (et_encap(sc, &m)) { 1102 ifp->if_oerrors++; 1103 ifp->if_flags |= IFF_OACTIVE; 1104 break; 1105 } 1106 1107 trans = 1; 1108 1109 bpf_mtap(ifp, m, BPF_D_OUT); 1110 } 1111 1112 if (trans) { 1113 callout_schedule(&sc->sc_txtick, hz); 1114 ifp->if_timer = 5; 1115 } 1116 } 1117 1118 void 1119 et_watchdog(struct ifnet *ifp) 1120 { 1121 struct et_softc *sc = ifp->if_softc; 1122 aprint_error_dev(sc->sc_dev, "watchdog timed out\n"); 1123 1124 ifp->if_flags &= ~IFF_RUNNING; 1125 et_init(ifp); 1126 et_start(ifp); 1127 } 1128 1129 int 1130 et_stop_rxdma(struct et_softc *sc) 1131 { 1132 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1133 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1134 1135 DELAY(5); 1136 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1137 aprint_error_dev(sc->sc_dev, "can't stop RX DMA engine\n"); 1138 return ETIMEDOUT; 1139 } 1140 return 0; 1141 } 1142 1143 int 1144 et_stop_txdma(struct et_softc *sc) 1145 { 1146 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1147 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1148 return 0; 1149 } 1150 1151 void 1152 et_free_tx_ring(struct et_softc *sc) 1153 { 1154 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1155 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1156 int i; 1157 1158 for (i = 0; i < ET_TX_NDESC; ++i) { 1159 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1160 1161 if (tb->tb_mbuf != NULL) { 1162 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1163 m_freem(tb->tb_mbuf); 1164 tb->tb_mbuf = NULL; 1165 } 1166 } 1167 1168 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1169 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1170 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1171 } 1172 1173 void 1174 et_free_rx_ring(struct et_softc *sc) 1175 { 1176 int n; 1177 1178 for (n = 0; n < ET_RX_NRING; ++n) { 1179 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1180 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1181 int i; 1182 1183 for (i = 0; i < ET_RX_NDESC; ++i) { 1184 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1185 1186 if (rb->rb_mbuf != NULL) { 1187 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 1188 m_freem(rb->rb_mbuf); 1189 rb->rb_mbuf = NULL; 1190 } 1191 } 1192 1193 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1194 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 1195 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1196 } 1197 } 1198 1199 void 1200 et_setmulti(struct et_softc *sc) 1201 { 1202 struct ethercom *ec = &sc->sc_ethercom; 1203 struct ifnet *ifp = &ec->ec_if; 1204 uint32_t hash[4] = { 0, 0, 0, 0 }; 1205 uint32_t rxmac_ctrl, pktfilt; 1206 struct ether_multi *enm; 1207 struct ether_multistep step; 1208 uint8_t addr[ETHER_ADDR_LEN]; 1209 int i, count; 1210 1211 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1212 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1213 1214 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1215 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1216 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1217 goto back; 1218 } 1219 1220 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1221 1222 count = 0; 1223 ETHER_LOCK(ec); 1224 ETHER_FIRST_MULTI(step, ec, enm); 1225 while (enm != NULL) { 1226 uint32_t *hp, h; 1227 1228 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1229 addr[i] &= enm->enm_addrlo[i]; 1230 } 1231 1232 h = ether_crc32_be(addr, ETHER_ADDR_LEN); 1233 h = (h & 0x3f800000) >> 23; 1234 1235 hp = &hash[0]; 1236 if (h >= 32 && h < 64) { 1237 h -= 32; 1238 hp = &hash[1]; 1239 } else if (h >= 64 && h < 96) { 1240 h -= 64; 1241 hp = &hash[2]; 1242 } else if (h >= 96) { 1243 h -= 96; 1244 hp = &hash[3]; 1245 } 1246 *hp |= (1 << h); 1247 1248 ++count; 1249 ETHER_NEXT_MULTI(step, enm); 1250 } 1251 ETHER_UNLOCK(ec); 1252 1253 for (i = 0; i < 4; ++i) 1254 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1255 1256 if (count > 0) 1257 pktfilt |= ET_PKTFILT_MCAST; 1258 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1259 back: 1260 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1261 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1262 } 1263 1264 int 1265 et_chip_init(struct et_softc *sc) 1266 { 1267 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1268 uint32_t rxq_end; 1269 int error; 1270 1271 /* 1272 * Split internal memory between TX and RX according to MTU 1273 */ 1274 if (ifp->if_mtu < 2048) 1275 rxq_end = 0x2bc; 1276 else if (ifp->if_mtu < 8192) 1277 rxq_end = 0x1ff; 1278 else 1279 rxq_end = 0x1b3; 1280 CSR_WRITE_4(sc, ET_RXQ_START, 0); 1281 CSR_WRITE_4(sc, ET_RXQ_END, rxq_end); 1282 CSR_WRITE_4(sc, ET_TXQ_START, rxq_end + 1); 1283 CSR_WRITE_4(sc, ET_TXQ_END, ET_INTERN_MEM_END); 1284 1285 /* No loopback */ 1286 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1287 1288 /* Clear MSI configure */ 1289 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1290 1291 /* Disable timer */ 1292 CSR_WRITE_4(sc, ET_TIMER, 0); 1293 1294 /* Initialize MAC */ 1295 et_init_mac(sc); 1296 1297 /* Enable memory controllers */ 1298 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1299 1300 /* Initialize RX MAC */ 1301 et_init_rxmac(sc); 1302 1303 /* Initialize TX MAC */ 1304 et_init_txmac(sc); 1305 1306 /* Initialize RX DMA engine */ 1307 error = et_init_rxdma(sc); 1308 if (error) 1309 return error; 1310 1311 /* Initialize TX DMA engine */ 1312 error = et_init_txdma(sc); 1313 if (error) 1314 return error; 1315 1316 return 0; 1317 } 1318 1319 int 1320 et_init_tx_ring(struct et_softc *sc) 1321 { 1322 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1323 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1324 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1325 1326 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1327 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1328 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1329 1330 tbd->tbd_start_index = 0; 1331 tbd->tbd_start_wrap = 0; 1332 tbd->tbd_used = 0; 1333 1334 bzero(txsd->txsd_status, sizeof(uint32_t)); 1335 bus_dmamap_sync(sc->sc_dmat, txsd->txsd_dmap, 0, 1336 txsd->txsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1337 return 0; 1338 } 1339 1340 int 1341 et_init_rx_ring(struct et_softc *sc) 1342 { 1343 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1344 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1345 int n; 1346 1347 for (n = 0; n < ET_RX_NRING; ++n) { 1348 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1349 int i, error; 1350 1351 for (i = 0; i < ET_RX_NDESC; ++i) { 1352 error = rbd->rbd_newbuf(rbd, i, 1); 1353 if (error) { 1354 aprint_error_dev(sc->sc_dev, "%d ring %d buf, newbuf failed: " 1355 "%d\n", n, i, error); 1356 return error; 1357 } 1358 } 1359 } 1360 1361 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1362 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1363 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1364 1365 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1366 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1367 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1368 1369 return 0; 1370 } 1371 1372 int 1373 et_init_rxdma(struct et_softc *sc) 1374 { 1375 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1376 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1377 struct et_rxdesc_ring *rx_ring; 1378 int error; 1379 1380 error = et_stop_rxdma(sc); 1381 if (error) { 1382 aprint_error_dev(sc->sc_dev, "can't init RX DMA engine\n"); 1383 return error; 1384 } 1385 1386 /* 1387 * Install RX status 1388 */ 1389 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1390 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1391 1392 /* 1393 * Install RX stat ring 1394 */ 1395 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1396 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1397 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1398 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1399 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1400 1401 /* Match ET_RXSTAT_POS */ 1402 rxst_ring->rsr_index = 0; 1403 rxst_ring->rsr_wrap = 0; 1404 1405 /* 1406 * Install the 2nd RX descriptor ring 1407 */ 1408 rx_ring = &sc->sc_rx_ring[1]; 1409 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1410 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1411 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1412 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1413 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1414 1415 /* Match ET_RX_RING1_POS */ 1416 rx_ring->rr_index = 0; 1417 rx_ring->rr_wrap = 1; 1418 1419 /* 1420 * Install the 1st RX descriptor ring 1421 */ 1422 rx_ring = &sc->sc_rx_ring[0]; 1423 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1424 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1425 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1426 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1427 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1428 1429 /* Match ET_RX_RING0_POS */ 1430 rx_ring->rr_index = 0; 1431 rx_ring->rr_wrap = 1; 1432 1433 /* 1434 * RX intr moderation 1435 */ 1436 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1437 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1438 1439 return 0; 1440 } 1441 1442 int 1443 et_init_txdma(struct et_softc *sc) 1444 { 1445 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1446 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1447 int error; 1448 1449 error = et_stop_txdma(sc); 1450 if (error) { 1451 aprint_error_dev(sc->sc_dev, "can't init TX DMA engine\n"); 1452 return error; 1453 } 1454 1455 /* 1456 * Install TX descriptor ring 1457 */ 1458 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1459 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1460 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1461 1462 /* 1463 * Install TX status 1464 */ 1465 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1466 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1467 1468 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1469 1470 /* Match ET_TX_READY_POS */ 1471 tx_ring->tr_ready_index = 0; 1472 tx_ring->tr_ready_wrap = 0; 1473 1474 return 0; 1475 } 1476 1477 void 1478 et_init_mac(struct et_softc *sc) 1479 { 1480 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1481 const uint8_t *eaddr = CLLADDR(ifp->if_sadl); 1482 uint32_t val; 1483 1484 /* Reset MAC */ 1485 CSR_WRITE_4(sc, ET_MAC_CFG1, 1486 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1487 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1488 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1489 1490 /* 1491 * Setup inter packet gap 1492 */ 1493 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1494 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1495 __SHIFTIN(80, ET_IPG_MINIFG) | 1496 __SHIFTIN(96, ET_IPG_B2B); 1497 CSR_WRITE_4(sc, ET_IPG, val); 1498 1499 /* 1500 * Setup half duplex mode 1501 */ 1502 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1503 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1504 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1505 ET_MAC_HDX_EXC_DEFER; 1506 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1507 1508 /* Clear MAC control */ 1509 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1510 1511 /* Reset MII */ 1512 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1513 1514 /* 1515 * Set MAC address 1516 */ 1517 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1518 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1519 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1520 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1521 1522 /* Set max frame length */ 1523 CSR_WRITE_4(sc, ET_MAX_FRMLEN, 1524 ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + ETHER_CRC_LEN); 1525 1526 /* Bring MAC out of reset state */ 1527 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1528 } 1529 1530 void 1531 et_init_rxmac(struct et_softc *sc) 1532 { 1533 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1534 const uint8_t *eaddr = CLLADDR(ifp->if_sadl); 1535 uint32_t val; 1536 int i; 1537 1538 /* Disable RX MAC and WOL */ 1539 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1540 1541 /* 1542 * Clear all WOL related registers 1543 */ 1544 for (i = 0; i < 3; ++i) 1545 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1546 for (i = 0; i < 20; ++i) 1547 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1548 1549 /* 1550 * Set WOL source address. XXX is this necessary? 1551 */ 1552 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1553 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1554 val = (eaddr[0] << 8) | eaddr[1]; 1555 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1556 1557 /* Clear packet filters */ 1558 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1559 1560 /* No ucast filtering */ 1561 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1562 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1563 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1564 1565 if (ifp->if_mtu > 8192) { 1566 /* 1567 * In order to transmit jumbo packets greater than 8k, 1568 * the FIFO between RX MAC and RX DMA needs to be reduced 1569 * in size to (16k - MTU). In order to implement this, we 1570 * must use "cut through" mode in the RX MAC, which chops 1571 * packets down into segments which are (max_size * 16). 1572 * In this case we selected 256 bytes, since this is the 1573 * size of the PCI-Express TLP's that the 1310 uses. 1574 */ 1575 val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) | 1576 ET_RXMAC_MC_SEGSZ_ENABLE; 1577 } else { 1578 val = 0; 1579 } 1580 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1581 1582 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1583 1584 /* Initialize RX MAC management register */ 1585 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1586 1587 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1588 1589 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1590 ET_RXMAC_MGT_PASS_ECRC | 1591 ET_RXMAC_MGT_PASS_ELEN | 1592 ET_RXMAC_MGT_PASS_ETRUNC | 1593 ET_RXMAC_MGT_CHECK_PKT); 1594 1595 /* 1596 * Configure runt filtering (may not work on certain chip generation) 1597 */ 1598 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1599 CSR_WRITE_4(sc, ET_PKTFILT, val); 1600 1601 /* Enable RX MAC but leave WOL disabled */ 1602 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1603 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1604 1605 /* 1606 * Setup multicast hash and allmulti/promisc mode 1607 */ 1608 et_setmulti(sc); 1609 } 1610 1611 void 1612 et_init_txmac(struct et_softc *sc) 1613 { 1614 /* Disable TX MAC and FC(?) */ 1615 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1616 1617 /* No flow control yet */ 1618 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1619 1620 /* Enable TX MAC but leave FC(?) diabled */ 1621 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1622 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1623 } 1624 1625 int 1626 et_start_rxdma(struct et_softc *sc) 1627 { 1628 uint32_t val = 0; 1629 1630 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1631 ET_RXDMA_CTRL_RING0_SIZE) | 1632 ET_RXDMA_CTRL_RING0_ENABLE; 1633 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1634 ET_RXDMA_CTRL_RING1_SIZE) | 1635 ET_RXDMA_CTRL_RING1_ENABLE; 1636 1637 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1638 1639 DELAY(5); 1640 1641 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1642 aprint_error_dev(sc->sc_dev, "can't start RX DMA engine\n"); 1643 return ETIMEDOUT; 1644 } 1645 return 0; 1646 } 1647 1648 int 1649 et_start_txdma(struct et_softc *sc) 1650 { 1651 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1652 return 0; 1653 } 1654 1655 int 1656 et_enable_txrx(struct et_softc *sc) 1657 { 1658 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1659 uint32_t val; 1660 int i, rc = 0; 1661 1662 val = CSR_READ_4(sc, ET_MAC_CFG1); 1663 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1664 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1665 ET_MAC_CFG1_LOOPBACK); 1666 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1667 1668 if ((rc = ether_mediachange(ifp)) != 0) 1669 goto out; 1670 1671 #define NRETRY 100 1672 1673 for (i = 0; i < NRETRY; ++i) { 1674 val = CSR_READ_4(sc, ET_MAC_CFG1); 1675 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1676 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1677 break; 1678 1679 DELAY(10); 1680 } 1681 if (i == NRETRY) { 1682 aprint_error_dev(sc->sc_dev, "can't enable RX/TX\n"); 1683 return ETIMEDOUT; 1684 } 1685 1686 #undef NRETRY 1687 return 0; 1688 out: 1689 return rc; 1690 } 1691 1692 void 1693 et_rxeof(struct et_softc *sc) 1694 { 1695 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1696 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1697 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1698 uint32_t rxs_stat_ring; 1699 int rxst_wrap, rxst_index; 1700 1701 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1702 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1703 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1704 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1705 1706 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1707 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1708 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1709 1710 while (rxst_index != rxst_ring->rsr_index || 1711 rxst_wrap != rxst_ring->rsr_wrap) { 1712 struct et_rxbuf_data *rbd; 1713 struct et_rxdesc_ring *rx_ring; 1714 struct et_rxstat *st; 1715 struct et_rxbuf *rb; 1716 struct mbuf *m; 1717 int buflen, buf_idx, ring_idx; 1718 uint32_t rxstat_pos, rxring_pos; 1719 1720 KASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1721 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1722 1723 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1724 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1725 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1726 1727 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1728 rxst_ring->rsr_index = 0; 1729 rxst_ring->rsr_wrap ^= 1; 1730 } 1731 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1732 ET_RXSTAT_POS_INDEX); 1733 if (rxst_ring->rsr_wrap) 1734 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1735 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1736 1737 if (ring_idx >= ET_RX_NRING) { 1738 ifp->if_ierrors++; 1739 aprint_error_dev(sc->sc_dev, "invalid ring index %d\n", 1740 ring_idx); 1741 continue; 1742 } 1743 if (buf_idx >= ET_RX_NDESC) { 1744 ifp->if_ierrors++; 1745 aprint_error_dev(sc->sc_dev, "invalid buf index %d\n", 1746 buf_idx); 1747 continue; 1748 } 1749 1750 rbd = &sc->sc_rx_data[ring_idx]; 1751 rb = &rbd->rbd_buf[buf_idx]; 1752 m = rb->rb_mbuf; 1753 bus_dmamap_sync(sc->sc_dmat, rb->rb_dmap, 0, 1754 rb->rb_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1755 1756 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1757 if (buflen < ETHER_CRC_LEN) { 1758 m_freem(m); 1759 ifp->if_ierrors++; 1760 } else { 1761 m->m_pkthdr.len = m->m_len = buflen - 1762 ETHER_CRC_LEN; 1763 m_set_rcvif(m, ifp); 1764 1765 if_percpuq_enqueue(ifp->if_percpuq, m); 1766 } 1767 } else { 1768 ifp->if_ierrors++; 1769 } 1770 1771 rx_ring = &sc->sc_rx_ring[ring_idx]; 1772 1773 if (buf_idx != rx_ring->rr_index) { 1774 aprint_error_dev(sc->sc_dev, "WARNING!! ring %d, " 1775 "buf_idx %d, rr_idx %d\n", 1776 ring_idx, buf_idx, rx_ring->rr_index); 1777 } 1778 1779 KASSERT(rx_ring->rr_index < ET_RX_NDESC); 1780 if (++rx_ring->rr_index == ET_RX_NDESC) { 1781 rx_ring->rr_index = 0; 1782 rx_ring->rr_wrap ^= 1; 1783 } 1784 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1785 if (rx_ring->rr_wrap) 1786 rxring_pos |= ET_RX_RING_POS_WRAP; 1787 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1788 } 1789 } 1790 1791 int 1792 et_encap(struct et_softc *sc, struct mbuf **m0) 1793 { 1794 struct mbuf *m = *m0; 1795 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1796 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1797 struct et_txdesc *td; 1798 bus_dmamap_t map; 1799 int error, maxsegs, first_idx, last_idx, i; 1800 uint32_t tx_ready_pos, last_td_ctrl2; 1801 1802 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1803 if (maxsegs > ET_NSEG_MAX) 1804 maxsegs = ET_NSEG_MAX; 1805 KASSERTMSG(maxsegs >= ET_NSEG_SPARE, 1806 "not enough spare TX desc (%d)\n", maxsegs); 1807 1808 KASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1809 first_idx = tx_ring->tr_ready_index; 1810 map = tbd->tbd_buf[first_idx].tb_dmap; 1811 1812 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1813 BUS_DMA_NOWAIT); 1814 if (!error && map->dm_nsegs == 0) { 1815 bus_dmamap_unload(sc->sc_dmat, map); 1816 error = EFBIG; 1817 } 1818 if (error && error != EFBIG) { 1819 aprint_error_dev(sc->sc_dev, "can't load TX mbuf"); 1820 goto back; 1821 } 1822 if (error) { /* error == EFBIG */ 1823 struct mbuf *m_new; 1824 1825 error = 0; 1826 1827 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1828 if (m_new == NULL) { 1829 aprint_error_dev(sc->sc_dev, "can't defrag TX mbuf\n"); 1830 error = ENOBUFS; 1831 goto back; 1832 } 1833 1834 m_copy_pkthdr(m_new, m); 1835 if (m->m_pkthdr.len > MHLEN) { 1836 MCLGET(m_new, M_DONTWAIT); 1837 if (!(m_new->m_flags & M_EXT)) { 1838 m_freem(m_new); 1839 error = ENOBUFS; 1840 } 1841 } 1842 1843 if (error) { 1844 aprint_error_dev(sc->sc_dev, "can't defrag TX buffer\n"); 1845 goto back; 1846 } 1847 1848 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, void *)); 1849 m_freem(m); 1850 m_new->m_len = m_new->m_pkthdr.len; 1851 *m0 = m = m_new; 1852 1853 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1854 BUS_DMA_NOWAIT); 1855 if (error || map->dm_nsegs == 0) { 1856 if (map->dm_nsegs == 0) { 1857 bus_dmamap_unload(sc->sc_dmat, map); 1858 error = EFBIG; 1859 } 1860 aprint_error_dev(sc->sc_dev, "can't load defraged TX mbuf\n"); 1861 goto back; 1862 } 1863 } 1864 1865 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1866 BUS_DMASYNC_PREWRITE); 1867 1868 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1869 sc->sc_tx += map->dm_nsegs; 1870 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1871 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1872 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1873 } 1874 1875 last_idx = -1; 1876 for (i = 0; i < map->dm_nsegs; ++i) { 1877 int idx; 1878 1879 idx = (first_idx + i) % ET_TX_NDESC; 1880 td = &tx_ring->tr_desc[idx]; 1881 td->td_addr_hi = ET_ADDR_HI(map->dm_segs[i].ds_addr); 1882 td->td_addr_lo = ET_ADDR_LO(map->dm_segs[i].ds_addr); 1883 td->td_ctrl1 = 1884 __SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN); 1885 1886 if (i == map->dm_nsegs - 1) { /* Last frag */ 1887 td->td_ctrl2 = last_td_ctrl2; 1888 last_idx = idx; 1889 } 1890 1891 KASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1892 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1893 tx_ring->tr_ready_index = 0; 1894 tx_ring->tr_ready_wrap ^= 1; 1895 } 1896 } 1897 td = &tx_ring->tr_desc[first_idx]; 1898 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1899 1900 KASSERT(last_idx >= 0); 1901 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1902 tbd->tbd_buf[last_idx].tb_dmap = map; 1903 tbd->tbd_buf[last_idx].tb_mbuf = m; 1904 1905 tbd->tbd_used += map->dm_nsegs; 1906 KASSERT(tbd->tbd_used <= ET_TX_NDESC); 1907 1908 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1909 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1910 1911 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 1912 ET_TX_READY_POS_INDEX); 1913 if (tx_ring->tr_ready_wrap) 1914 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1915 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1916 1917 error = 0; 1918 back: 1919 if (error) { 1920 m_freem(m); 1921 *m0 = NULL; 1922 } 1923 return error; 1924 } 1925 1926 void 1927 et_txeof(struct et_softc *sc) 1928 { 1929 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1930 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1931 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1932 uint32_t tx_done; 1933 int end, wrap; 1934 1935 if (tbd->tbd_used == 0) 1936 return; 1937 1938 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 1939 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 1940 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 1941 1942 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 1943 struct et_txbuf *tb; 1944 1945 KASSERT(tbd->tbd_start_index < ET_TX_NDESC); 1946 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 1947 1948 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 1949 sizeof(struct et_txdesc)); 1950 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1951 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1952 1953 if (tb->tb_mbuf != NULL) { 1954 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1955 m_freem(tb->tb_mbuf); 1956 tb->tb_mbuf = NULL; 1957 ifp->if_opackets++; 1958 } 1959 1960 if (++tbd->tbd_start_index == ET_TX_NDESC) { 1961 tbd->tbd_start_index = 0; 1962 tbd->tbd_start_wrap ^= 1; 1963 } 1964 1965 KASSERT(tbd->tbd_used > 0); 1966 tbd->tbd_used--; 1967 } 1968 1969 if (tbd->tbd_used == 0) { 1970 callout_stop(&sc->sc_txtick); 1971 ifp->if_timer = 0; 1972 } 1973 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 1974 ifp->if_flags &= ~IFF_OACTIVE; 1975 1976 if_schedule_deferred_start(ifp); 1977 } 1978 1979 void 1980 et_txtick(void *xsc) 1981 { 1982 struct et_softc *sc = xsc; 1983 int s; 1984 1985 s = splnet(); 1986 et_txeof(sc); 1987 splx(s); 1988 } 1989 1990 void 1991 et_tick(void *xsc) 1992 { 1993 struct et_softc *sc = xsc; 1994 int s; 1995 1996 s = splnet(); 1997 mii_tick(&sc->sc_miibus); 1998 callout_schedule(&sc->sc_tick, hz); 1999 splx(s); 2000 } 2001 2002 int 2003 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 2004 { 2005 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 2006 } 2007 2008 int 2009 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 2010 { 2011 return et_newbuf(rbd, buf_idx, init, MHLEN); 2012 } 2013 2014 int 2015 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 2016 { 2017 struct et_softc *sc = rbd->rbd_softc; 2018 struct et_rxdesc_ring *rx_ring; 2019 struct et_rxdesc *desc; 2020 struct et_rxbuf *rb; 2021 struct mbuf *m; 2022 bus_dmamap_t dmap; 2023 int error, len; 2024 2025 KASSERT(buf_idx < ET_RX_NDESC); 2026 rb = &rbd->rbd_buf[buf_idx]; 2027 2028 if (len0 >= MINCLSIZE) { 2029 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2030 if (m == NULL) 2031 return (ENOBUFS); 2032 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2033 if ((m->m_flags & M_EXT) == 0) { 2034 m_freem(m); 2035 return (ENOBUFS); 2036 } 2037 len = MCLBYTES; 2038 } else { 2039 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2040 len = MHLEN; 2041 } 2042 2043 if (m == NULL) { 2044 error = ENOBUFS; 2045 2046 /* XXX for debug */ 2047 aprint_error_dev(sc->sc_dev, "M_CLGET failed, size %d\n", len0); 2048 if (init) { 2049 return error; 2050 } else { 2051 goto back; 2052 } 2053 } 2054 m->m_len = m->m_pkthdr.len = len; 2055 2056 /* 2057 * Try load RX mbuf into temporary DMA tag 2058 */ 2059 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_mbuf_tmp_dmap, m, 2060 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2061 if (error) { 2062 m_freem(m); 2063 2064 /* XXX for debug */ 2065 aprint_error_dev(sc->sc_dev, "can't load RX mbuf\n"); 2066 if (init) { 2067 return error; 2068 } else { 2069 goto back; 2070 } 2071 } 2072 2073 if (!init) 2074 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 2075 rb->rb_mbuf = m; 2076 2077 /* 2078 * Swap RX buf's DMA map with the loaded temporary one 2079 */ 2080 dmap = rb->rb_dmap; 2081 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2082 rb->rb_paddr = rb->rb_dmap->dm_segs[0].ds_addr; 2083 sc->sc_mbuf_tmp_dmap = dmap; 2084 2085 error = 0; 2086 back: 2087 rx_ring = rbd->rbd_ring; 2088 desc = &rx_ring->rr_desc[buf_idx]; 2089 2090 desc->rd_addr_hi = ET_ADDR_HI(rb->rb_paddr); 2091 desc->rd_addr_lo = ET_ADDR_LO(rb->rb_paddr); 2092 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2093 2094 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 2095 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2096 return error; 2097 } 2098
Indexes created Fri Oct 03 02:09:57 GMT 2025