if_ex_pci.c revision 1.33
1 /* $NetBSD: if_ex_pci.c,v 1.33 2003/04/12 09:03:25 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: if_ex_pci.c,v 1.33 2003/04/12 09:03:25 christos Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/syslog.h> 50 #include <sys/select.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 58 #include <machine/cpu.h> 59 #include <machine/bus.h> 60 #include <machine/intr.h> 61 62 #include <dev/mii/miivar.h> 63 #include <dev/mii/mii.h> 64 65 #include <dev/ic/elink3var.h> 66 #include <dev/ic/elink3reg.h> 67 #include <dev/ic/elinkxlreg.h> 68 #include <dev/ic/elinkxlvar.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcidevs.h> 73 74 struct ex_pci_softc { 75 struct ex_softc sc_ex; 76 77 /* PCI function status space. 556,556B requests it. */ 78 bus_space_tag_t sc_funct; 79 bus_space_handle_t sc_funch; 80 81 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 82 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 83 pcitag_t psc_tag; /* pci device tag */ 84 85 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 86 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 87 }; 88 89 /* 90 * PCI constants. 91 * XXX These should be in a common file! 92 */ 93 #define PCI_CONN 0x48 /* Connector type */ 94 #define PCI_CBIO 0x10 /* Configuration Base IO Address */ 95 #define PCI_POWERCTL 0xe0 96 #define PCI_FUNCMEM 0x18 97 98 #define PCI_INTR 4 99 #define PCI_INTRACK 0x00008000 100 101 int ex_pci_match __P((struct device *, struct cfdata *, void *)); 102 void ex_pci_attach __P((struct device *, struct device *, void *)); 103 void ex_pci_intr_ack __P((struct ex_softc *)); 104 105 int ex_pci_enable __P((struct ex_softc *)); 106 void ex_pci_disable __P((struct ex_softc *)); 107 108 void ex_pci_confreg_restore __P((struct ex_pci_softc *)); 109 void ex_d3tod0 __P(( struct ex_softc *, struct pci_attach_args *)); 110 111 CFATTACH_DECL(ex_pci, sizeof(struct ex_pci_softc), 112 ex_pci_match, ex_pci_attach, NULL, NULL); 113 114 const struct ex_pci_product { 115 u_int32_t epp_prodid; /* PCI product ID */ 116 int epp_flags; /* initial softc flags */ 117 const char *epp_name; /* device name */ 118 } ex_pci_products[] = { 119 { PCI_PRODUCT_3COM_3C900TPO, 0, 120 "3c900-TPO Ethernet" }, 121 { PCI_PRODUCT_3COM_3C900COMBO, 0, 122 "3c900-COMBO Ethernet" }, 123 124 { PCI_PRODUCT_3COM_3C905TX, EX_CONF_MII, 125 "3c905-TX 10/100 Ethernet" }, 126 { PCI_PRODUCT_3COM_3C905T4, EX_CONF_MII, 127 "3c905-T4 10/100 Ethernet" }, 128 129 { PCI_PRODUCT_3COM_3C900BTPO, EX_CONF_90XB, 130 "3c900B-TPO Ethernet" }, 131 { PCI_PRODUCT_3COM_3C900BCOMBO, EX_CONF_90XB, 132 "3c900B-COMBO Ethernet" }, 133 { PCI_PRODUCT_3COM_3C900BTPC, EX_CONF_90XB, 134 "3c900B-TPC Ethernet" }, 135 136 { PCI_PRODUCT_3COM_3C905BTX, EX_CONF_90XB|EX_CONF_MII|EX_CONF_INTPHY, 137 "3c905B-TX 10/100 Ethernet" }, 138 { PCI_PRODUCT_3COM_3C905BT4, EX_CONF_90XB|EX_CONF_MII, 139 "3c905B-T4 10/100 Ethernet" }, 140 { PCI_PRODUCT_3COM_3C905BCOMBO, EX_CONF_90XB/*|EX_CONF_MII|EX_CONF_INTPHY*/, 141 "3c905B-COMBO 10/100 Ethernet" }, 142 { PCI_PRODUCT_3COM_3C905BFX, EX_CONF_90XB, 143 "3c905B-FX 10/100 Ethernet" }, 144 145 /* XXX Internal PHY? */ 146 { PCI_PRODUCT_3COM_3C980SRV, EX_CONF_90XB, 147 "3c980 Server Adapter 10/100 Ethernet" }, 148 { PCI_PRODUCT_3COM_3C980CTXM, EX_CONF_90XB|EX_CONF_MII, 149 "3c980C-TXM 10/100 Ethernet" }, 150 151 { PCI_PRODUCT_3COM_3C905CTX, EX_CONF_90XB|EX_CONF_MII, 152 "3c905C-TX 10/100 Ethernet with mngmt" }, 153 154 { PCI_PRODUCT_3COM_3C450TX, EX_CONF_90XB, 155 "3c450-TX 10/100 Ethernet" }, 156 157 { PCI_PRODUCT_3COM_3CSOHO100TX, EX_CONF_90XB, 158 "3cSOHO100-TX 10/100 Ethernet" }, 159 160 { PCI_PRODUCT_3COM_3C555, 161 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 162 EX_CONF_EEPROM_8BIT, 163 "3c555 MiniPCI 10/100 Ethernet" }, 164 165 { PCI_PRODUCT_3COM_3C556, 166 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 167 EX_CONF_PCI_FUNCREG | EX_CONF_RESETHACK | EX_CONF_INV_LED_POLARITY | 168 EX_CONF_PHY_POWER | EX_CONF_EEPROM_8BIT, 169 "3c556 MiniPCI 10/100 Ethernet" }, 170 171 { PCI_PRODUCT_3COM_3C556B, 172 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 173 EX_CONF_PCI_FUNCREG | EX_CONF_RESETHACK | EX_CONF_INV_LED_POLARITY | 174 EX_CONF_PHY_POWER, 175 "3c556B MiniPCI 10/100 Ethernet" }, 176 177 { PCI_PRODUCT_3COM_3C905CXTX, EX_CONF_90XB|EX_CONF_MII, 178 "3c905CX-TX 10/100 Ethernet with mngmt" }, 179 180 { 0, 0, 181 NULL }, 182 }; 183 184 const struct ex_pci_product *ex_pci_lookup 185 __P((const struct pci_attach_args *)); 186 187 const struct ex_pci_product * 188 ex_pci_lookup(pa) 189 const struct pci_attach_args *pa; 190 { 191 const struct ex_pci_product *epp; 192 193 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_3COM) 194 return (NULL); 195 196 for (epp = ex_pci_products; epp->epp_name != NULL; epp++) 197 if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid) 198 return (epp); 199 return (NULL); 200 } 201 202 int 203 ex_pci_match(parent, match, aux) 204 struct device *parent; 205 struct cfdata *match; 206 void *aux; 207 { 208 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 209 210 if (ex_pci_lookup(pa) != NULL) 211 return (2); /* beat ep_pci */ 212 213 return (0); 214 } 215 216 void 217 ex_pci_attach(parent, self, aux) 218 struct device *parent, *self; 219 void *aux; 220 { 221 struct ex_softc *sc = (void *)self; 222 struct ex_pci_softc *psc = (void *)self; 223 struct pci_attach_args *pa = aux; 224 pci_chipset_tag_t pc = pa->pa_pc; 225 pci_intr_handle_t ih; 226 const struct ex_pci_product *epp; 227 const char *intrstr = NULL; 228 int rev, pmreg; 229 pcireg_t reg; 230 231 aprint_naive(": Ethernet controller\n"); 232 233 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 234 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 235 aprint_error(": can't map i/o space\n"); 236 return; 237 } 238 239 epp = ex_pci_lookup(pa); 240 if (epp == NULL) { 241 printf("\n"); 242 panic("ex_pci_attach: impossible"); 243 } 244 245 rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 246 aprint_normal(": 3Com %s (rev. 0x%x)\n", epp->epp_name, rev); 247 248 sc->sc_dmat = pa->pa_dmat; 249 250 sc->ex_bustype = EX_BUS_PCI; 251 sc->ex_conf = epp->epp_flags; 252 253 /* Enable the card. */ 254 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 255 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 256 PCI_COMMAND_MASTER_ENABLE); 257 258 psc->psc_pc = pc; 259 psc->psc_tag = pa->pa_tag; 260 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 261 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 262 psc->psc_regs[PCI_BHLC_REG>>2] = 263 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 264 psc->psc_regs[PCI_CBIO>>2] = 265 pci_conf_read(pc, pa->pa_tag, PCI_CBIO); 266 267 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) { 268 /* Map PCI function status window. */ 269 if (pci_mapreg_map(pa, PCI_FUNCMEM, PCI_MAPREG_TYPE_MEM, 0, 270 &psc->sc_funct, &psc->sc_funch, NULL, NULL)) { 271 aprint_error( 272 "%s: unable to map function status window\n", 273 sc->sc_dev.dv_xname); 274 return; 275 } 276 sc->intr_ack = ex_pci_intr_ack; 277 278 psc->psc_regs[PCI_FUNCMEM>>2] = 279 pci_conf_read(pc, pa->pa_tag, PCI_FUNCMEM); 280 } 281 282 psc->psc_regs[PCI_INTERRUPT_REG>>2] = 283 pci_conf_read(pc, pa->pa_tag, PCI_INTERRUPT_REG); 284 285 /* Get it out of power save mode if needed (BIOS bugs) */ 286 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 287 sc->enable = ex_pci_enable; 288 sc->disable = ex_pci_disable; 289 290 psc->psc_pwrmgmt_csr_reg = pmreg + PCI_PMCSR; 291 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 292 293 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 294 PCI_PMCSR_STATE_D0; 295 296 switch (reg & PCI_PMCSR_STATE_MASK) { 297 case PCI_PMCSR_STATE_D3: 298 /* 299 * The card has lost all configuration data in 300 * this state, so punt. 301 */ 302 aprint_error( 303 "%s: unable to wake up from power state D3\n", 304 sc->sc_dev.dv_xname); 305 return; 306 case PCI_PMCSR_STATE_D1: 307 case PCI_PMCSR_STATE_D2: 308 aprint_normal("%s: waking up from power state D%d\n", 309 sc->sc_dev.dv_xname, reg); 310 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 311 (reg & ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D0); 312 break; 313 } 314 } 315 316 sc->enabled = 1; 317 318 /* Map and establish the interrupt. */ 319 if (pci_intr_map(pa, &ih)) { 320 aprint_error("%s: couldn't map interrupt\n", 321 sc->sc_dev.dv_xname); 322 return; 323 } 324 325 intrstr = pci_intr_string(pc, ih); 326 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ex_intr, sc); 327 if (sc->sc_ih == NULL) { 328 aprint_error("%s: couldn't establish interrupt", 329 sc->sc_dev.dv_xname); 330 if (intrstr != NULL) 331 aprint_normal(" at %s", intrstr); 332 aprint_normal("\n"); 333 return; 334 } 335 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 336 337 ex_config(sc); 338 339 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) 340 bus_space_write_4(psc->sc_funct, psc->sc_funch, PCI_INTR, 341 PCI_INTRACK); 342 343 if (sc->disable != NULL) 344 ex_disable(sc); 345 } 346 347 void 348 ex_pci_intr_ack(sc) 349 struct ex_softc *sc; 350 { 351 struct ex_pci_softc *psc = (struct ex_pci_softc *)sc; 352 353 bus_space_write_4(psc->sc_funct, psc->sc_funch, PCI_INTR, 354 PCI_INTRACK); 355 } 356 357 void 358 ex_d3tod0(sc, pa) 359 struct ex_softc *sc; 360 struct pci_attach_args *pa; 361 { 362 363 #define PCI_CACHE_LAT_BIST 0x0c 364 #define PCI_BAR0 0x10 365 #define PCI_BAR1 0x14 366 #define PCI_BAR2 0x18 367 #define PCI_BAR3 0x1C 368 #define PCI_BAR4 0x20 369 #define PCI_BAR5 0x24 370 #define PCI_EXP_ROM_BAR 0x30 371 #define PCI_INT_GNT_LAT 0x3c 372 373 pci_chipset_tag_t pc = pa->pa_pc; 374 375 u_int32_t base0; 376 u_int32_t base1; 377 u_int32_t romaddr; 378 u_int32_t pci_command; 379 u_int32_t pci_int_lat; 380 u_int32_t pci_cache_lat; 381 382 pci_command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 383 base0 = pci_conf_read(pc, pa->pa_tag, PCI_BAR0); 384 base1 = pci_conf_read(pc, pa->pa_tag, PCI_BAR1); 385 romaddr = pci_conf_read(pc, pa->pa_tag, PCI_EXP_ROM_BAR); 386 pci_cache_lat= pci_conf_read(pc, pa->pa_tag, PCI_CACHE_LAT_BIST); 387 pci_int_lat = pci_conf_read(pc, pa->pa_tag, PCI_INT_GNT_LAT); 388 389 pci_conf_write(pc, pa->pa_tag, PCI_POWERCTL, 0); 390 pci_conf_write(pc, pa->pa_tag, PCI_BAR0, base0); 391 pci_conf_write(pc, pa->pa_tag, PCI_BAR1, base1); 392 pci_conf_write(pc, pa->pa_tag, PCI_EXP_ROM_BAR, romaddr); 393 pci_conf_write(pc, pa->pa_tag, PCI_INT_GNT_LAT, pci_int_lat); 394 pci_conf_write(pc, pa->pa_tag, PCI_CACHE_LAT_BIST, pci_cache_lat); 395 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 396 (PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE)); 397 } 398 399 void 400 ex_pci_confreg_restore(psc) 401 struct ex_pci_softc *psc; 402 { 403 struct ex_softc *sc = (void *) psc; 404 pcireg_t reg; 405 406 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 407 408 pci_conf_write(psc->psc_pc, psc->psc_tag, 409 PCI_COMMAND_STATUS_REG, 410 (reg & 0xffff0000) | 411 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 412 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 413 psc->psc_regs[PCI_BHLC_REG>>2]); 414 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_CBIO, 415 psc->psc_regs[PCI_CBIO>>2]); 416 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) 417 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_FUNCMEM, 418 psc->psc_regs[PCI_FUNCMEM>>2]); 419 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_INTERRUPT_REG, 420 psc->psc_regs[PCI_INTERRUPT_REG>>2]); 421 } 422 423 int 424 ex_pci_enable(sc) 425 struct ex_softc *sc; 426 { 427 struct ex_pci_softc *psc = (void *) sc; 428 429 #if 0 430 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 431 #endif 432 433 /* Bring the device into D0 power state. */ 434 pci_conf_write(psc->psc_pc, psc->psc_tag, 435 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 436 437 /* Now restore the configuration registers. */ 438 ex_pci_confreg_restore(psc); 439 440 return (0); 441 } 442 443 void 444 ex_pci_disable(sc) 445 struct ex_softc *sc; 446 { 447 struct ex_pci_softc *psc = (void *) sc; 448 449 #if 0 450 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 451 #endif 452 453 /* Put the device into D3 state. */ 454 pci_conf_write(psc->psc_pc, psc->psc_tag, 455 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 456 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 457 } 458
Indexes created Wed Sep 24 22:09:59 GMT 2025