if_ex_pci.c revision 1.48
1 /* $NetBSD: if_ex_pci.c,v 1.48 2008/04/14 21:20:41 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: if_ex_pci.c,v 1.48 2008/04/14 21:20:41 cegger Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/syslog.h> 50 #include <sys/select.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 58 #include <sys/cpu.h> 59 #include <sys/bus.h> 60 #include <sys/intr.h> 61 62 #include <dev/mii/miivar.h> 63 #include <dev/mii/mii.h> 64 65 #include <dev/ic/elink3var.h> 66 #include <dev/ic/elink3reg.h> 67 #include <dev/ic/elinkxlreg.h> 68 #include <dev/ic/elinkxlvar.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcidevs.h> 73 74 struct ex_pci_softc { 75 struct ex_softc sc_ex; 76 77 /* PCI function status space. 556,556B requests it. */ 78 bus_space_tag_t sc_funct; 79 bus_space_handle_t sc_funch; 80 81 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 82 pcireg_t psc_regs[0x40>>2]; /* saved PCI config regs (sparse) */ 83 pcitag_t psc_tag; /* pci device tag */ 84 85 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 86 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 87 }; 88 89 /* 90 * PCI constants. 91 * XXX These should be in a common file! 92 */ 93 #define PCI_CONN 0x48 /* Connector type */ 94 #define PCI_CBIO 0x10 /* Configuration Base IO Address */ 95 #define PCI_POWERCTL 0xe0 96 #define PCI_FUNCMEM 0x18 97 98 #define PCI_INTR 4 99 #define PCI_INTRACK 0x00008000 100 101 static int ex_pci_match(device_t, cfdata_t, void *); 102 static void ex_pci_attach(device_t, device_t, void *); 103 static void ex_pci_intr_ack(struct ex_softc *); 104 105 static int ex_pci_enable(struct ex_softc *); 106 static void ex_pci_disable(struct ex_softc *); 107 108 static void ex_pci_confreg_restore(struct ex_pci_softc *); 109 static int ex_d3tod0(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t); 110 111 CFATTACH_DECL_NEW(ex_pci, sizeof(struct ex_pci_softc), 112 ex_pci_match, ex_pci_attach, NULL, NULL); 113 114 static const struct ex_pci_product { 115 uint32_t epp_prodid; /* PCI product ID */ 116 int epp_flags; /* initial softc flags */ 117 const char *epp_name; /* device name */ 118 } ex_pci_products[] = { 119 { PCI_PRODUCT_3COM_3C900TPO, 0, 120 "3c900-TPO Ethernet" }, 121 { PCI_PRODUCT_3COM_3C900COMBO, 0, 122 "3c900-COMBO Ethernet" }, 123 124 { PCI_PRODUCT_3COM_3C905TX, EX_CONF_MII, 125 "3c905-TX 10/100 Ethernet" }, 126 { PCI_PRODUCT_3COM_3C905T4, EX_CONF_MII, 127 "3c905-T4 10/100 Ethernet" }, 128 129 { PCI_PRODUCT_3COM_3C900BTPO, EX_CONF_90XB, 130 "3c900B-TPO Ethernet" }, 131 { PCI_PRODUCT_3COM_3C900BCOMBO, EX_CONF_90XB, 132 "3c900B-COMBO Ethernet" }, 133 { PCI_PRODUCT_3COM_3C900BTPC, EX_CONF_90XB, 134 "3c900B-TPC Ethernet" }, 135 136 { PCI_PRODUCT_3COM_3C905BTX, EX_CONF_90XB|EX_CONF_MII|EX_CONF_INTPHY, 137 "3c905B-TX 10/100 Ethernet" }, 138 { PCI_PRODUCT_3COM_3C905BT4, EX_CONF_90XB|EX_CONF_MII, 139 "3c905B-T4 10/100 Ethernet" }, 140 { PCI_PRODUCT_3COM_3C905BCOMBO, EX_CONF_90XB/*|EX_CONF_MII|EX_CONF_INTPHY*/, 141 "3c905B-COMBO 10/100 Ethernet" }, 142 { PCI_PRODUCT_3COM_3C905BFX, EX_CONF_90XB, 143 "3c905B-FX 10/100 Ethernet" }, 144 145 /* XXX Internal PHY? */ 146 { PCI_PRODUCT_3COM_3C980SRV, EX_CONF_90XB, 147 "3c980 Server Adapter 10/100 Ethernet" }, 148 { PCI_PRODUCT_3COM_3C980CTXM, EX_CONF_90XB|EX_CONF_MII, 149 "3c980C-TXM 10/100 Ethernet" }, 150 151 { PCI_PRODUCT_3COM_3C905CTX, EX_CONF_90XB|EX_CONF_MII, 152 "3c905C-TX 10/100 Ethernet with mngmt" }, 153 154 { PCI_PRODUCT_3COM_3C450TX, EX_CONF_90XB, 155 "3c450-TX 10/100 Ethernet" }, 156 157 { PCI_PRODUCT_3COM_3CSOHO100TX, EX_CONF_90XB, 158 "3cSOHO100-TX 10/100 Ethernet" }, 159 160 { PCI_PRODUCT_3COM_3C555, 161 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 162 EX_CONF_EEPROM_8BIT, 163 "3c555 MiniPCI 10/100 Ethernet" }, 164 165 { PCI_PRODUCT_3COM_3C556, 166 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 167 EX_CONF_PCI_FUNCREG | EX_CONF_RESETHACK | EX_CONF_INV_LED_POLARITY | 168 EX_CONF_PHY_POWER | EX_CONF_EEPROM_8BIT, 169 "3c556 MiniPCI 10/100 Ethernet" }, 170 171 { PCI_PRODUCT_3COM_3C556B, 172 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 173 EX_CONF_PCI_FUNCREG | EX_CONF_RESETHACK | EX_CONF_INV_LED_POLARITY | 174 EX_CONF_PHY_POWER | EX_CONF_NO_XCVR_PWR, 175 "3c556B MiniPCI 10/100 Ethernet" }, 176 177 { PCI_PRODUCT_3COM_3C905CXTX, EX_CONF_90XB|EX_CONF_MII, 178 "3c905CX-TX 10/100 Ethernet with mngmt" }, 179 180 { PCI_PRODUCT_3COM_3C920BEMBW, EX_CONF_90XB|EX_CONF_MII, 181 "3c920B-EMB-WNM Integrated Fast Ethernet" }, 182 183 { 0, 0, 184 NULL }, 185 }; 186 187 static const struct ex_pci_product * 188 ex_pci_lookup(const struct pci_attach_args *pa) 189 { 190 const struct ex_pci_product *epp; 191 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_3COM) 193 return (NULL); 194 195 for (epp = ex_pci_products; epp->epp_name != NULL; epp++) 196 if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid) 197 return (epp); 198 return (NULL); 199 } 200 201 static int 202 ex_pci_match(device_t parent, cfdata_t match, 203 void *aux) 204 { 205 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 206 207 if (ex_pci_lookup(pa) != NULL) 208 return (2); /* beat ep_pci */ 209 210 return (0); 211 } 212 213 static void 214 ex_pci_attach(device_t parent, device_t self, void *aux) 215 { 216 struct ex_pci_softc *psc = device_private(self); 217 struct ex_softc *sc = &psc->sc_ex; 218 struct pci_attach_args *pa = aux; 219 pci_chipset_tag_t pc = pa->pa_pc; 220 pci_intr_handle_t ih; 221 const struct ex_pci_product *epp; 222 const char *intrstr = NULL; 223 int rev; 224 int error; 225 226 aprint_naive(": Ethernet controller\n"); 227 228 sc->sc_dev = self; 229 230 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 231 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 232 aprint_error(": can't map i/o space\n"); 233 return; 234 } 235 236 epp = ex_pci_lookup(pa); 237 if (epp == NULL) { 238 printf("\n"); 239 panic("ex_pci_attach: impossible"); 240 } 241 242 rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 243 aprint_normal(": 3Com %s (rev. 0x%x)\n", epp->epp_name, rev); 244 245 sc->sc_dmat = pa->pa_dmat; 246 247 sc->ex_bustype = EX_BUS_PCI; 248 sc->ex_conf = epp->epp_flags; 249 250 /* Enable the card. */ 251 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 252 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 253 PCI_COMMAND_MASTER_ENABLE); 254 255 psc->psc_pc = pc; 256 psc->psc_tag = pa->pa_tag; 257 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 258 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 259 psc->psc_regs[PCI_BHLC_REG>>2] = 260 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 261 psc->psc_regs[PCI_CBIO>>2] = 262 pci_conf_read(pc, pa->pa_tag, PCI_CBIO); 263 264 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) { 265 /* Map PCI function status window. */ 266 if (pci_mapreg_map(pa, PCI_FUNCMEM, PCI_MAPREG_TYPE_MEM, 0, 267 &psc->sc_funct, &psc->sc_funch, NULL, NULL)) { 268 aprint_error_dev(self, 269 "unable to map function status window\n"); 270 return; 271 } 272 sc->intr_ack = ex_pci_intr_ack; 273 274 psc->psc_regs[PCI_FUNCMEM>>2] = 275 pci_conf_read(pc, pa->pa_tag, PCI_FUNCMEM); 276 } 277 278 psc->psc_regs[PCI_INTERRUPT_REG>>2] = 279 pci_conf_read(pc, pa->pa_tag, PCI_INTERRUPT_REG); 280 /* power up chip */ 281 error = pci_activate(pa->pa_pc, pa->pa_tag, self, ex_d3tod0); 282 switch (error) { 283 case EOPNOTSUPP: 284 break; 285 case 0: 286 sc->enable = ex_pci_enable; 287 sc->disable = ex_pci_disable; 288 break; 289 default: 290 aprint_error_dev(self, "cannot activate %d\n", error); 291 return; 292 } 293 sc->enabled = 1; 294 295 /* Map and establish the interrupt. */ 296 if (pci_intr_map(pa, &ih)) { 297 aprint_error_dev(self, "couldn't map interrupt\n"); 298 return; 299 } 300 301 intrstr = pci_intr_string(pc, ih); 302 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ex_intr, sc); 303 if (sc->sc_ih == NULL) { 304 aprint_error_dev(self, "couldn't establish interrupt"); 305 if (intrstr != NULL) 306 aprint_normal(" at %s", intrstr); 307 aprint_normal("\n"); 308 return; 309 } 310 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 311 312 ex_config(sc); 313 314 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) 315 bus_space_write_4(psc->sc_funct, psc->sc_funch, PCI_INTR, 316 PCI_INTRACK); 317 318 if (sc->disable != NULL) 319 ex_disable(sc); 320 } 321 322 static void 323 ex_pci_intr_ack(struct ex_softc *sc) 324 { 325 struct ex_pci_softc *psc = (struct ex_pci_softc *)sc; 326 327 bus_space_write_4(psc->sc_funct, psc->sc_funch, PCI_INTR, 328 PCI_INTRACK); 329 } 330 331 static int 332 ex_d3tod0(pci_chipset_tag_t pc, pcitag_t tag, device_t self, pcireg_t state) 333 { 334 335 #define PCI_CACHE_LAT_BIST 0x0c 336 #define PCI_BAR0 0x10 337 #define PCI_BAR1 0x14 338 #define PCI_BAR2 0x18 339 #define PCI_BAR3 0x1C 340 #define PCI_BAR4 0x20 341 #define PCI_BAR5 0x24 342 #define PCI_EXP_ROM_BAR 0x30 343 #define PCI_INT_GNT_LAT 0x3c 344 345 uint32_t base0; 346 uint32_t base1; 347 uint32_t romaddr; 348 uint32_t pci_command; 349 uint32_t pci_int_lat; 350 uint32_t pci_cache_lat; 351 352 if (state != PCI_PMCSR_STATE_D3) 353 return 0; 354 355 aprint_normal_dev(self, "found in power state D%d, " 356 "attempting to recover.\n", state); 357 pci_command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 358 base0 = pci_conf_read(pc, tag, PCI_BAR0); 359 base1 = pci_conf_read(pc, tag, PCI_BAR1); 360 romaddr = pci_conf_read(pc, tag, PCI_EXP_ROM_BAR); 361 pci_cache_lat= pci_conf_read(pc, tag, PCI_CACHE_LAT_BIST); 362 pci_int_lat = pci_conf_read(pc, tag, PCI_INT_GNT_LAT); 363 364 pci_conf_write(pc, tag, PCI_POWERCTL, 0); 365 pci_conf_write(pc, tag, PCI_BAR0, base0); 366 pci_conf_write(pc, tag, PCI_BAR1, base1); 367 pci_conf_write(pc, tag, PCI_EXP_ROM_BAR, romaddr); 368 pci_conf_write(pc, tag, PCI_INT_GNT_LAT, pci_int_lat); 369 pci_conf_write(pc, tag, PCI_CACHE_LAT_BIST, pci_cache_lat); 370 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 371 (PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE)); 372 aprint_normal_dev(self, "changed power state to D0.\n"); 373 return 0; 374 } 375 376 static void 377 ex_pci_confreg_restore(struct ex_pci_softc *psc) 378 { 379 struct ex_softc *sc = (void *) psc; 380 pcireg_t reg; 381 382 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 383 384 pci_conf_write(psc->psc_pc, psc->psc_tag, 385 PCI_COMMAND_STATUS_REG, 386 (reg & 0xffff0000) | 387 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 388 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 389 psc->psc_regs[PCI_BHLC_REG>>2]); 390 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_CBIO, 391 psc->psc_regs[PCI_CBIO>>2]); 392 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) 393 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_FUNCMEM, 394 psc->psc_regs[PCI_FUNCMEM>>2]); 395 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_INTERRUPT_REG, 396 psc->psc_regs[PCI_INTERRUPT_REG>>2]); 397 } 398 399 static int 400 ex_pci_enable(struct ex_softc *sc) 401 { 402 struct ex_pci_softc *psc = (void *) sc; 403 404 aprint_debug_dev(sc->sc_dev, "going to power state D0\n"); 405 406 /* Bring the device into D0 power state. */ 407 pci_conf_write(psc->psc_pc, psc->psc_tag, 408 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 409 410 /* Now restore the configuration registers. */ 411 ex_pci_confreg_restore(psc); 412 413 return (0); 414 } 415 416 static void 417 ex_pci_disable(struct ex_softc *sc) 418 { 419 struct ex_pci_softc *psc = (void *) sc; 420 421 aprint_debug_dev(sc->sc_dev, "going to power state D3\n"); 422 423 /* Put the device into D3 state. */ 424 pci_conf_write(psc->psc_pc, psc->psc_tag, 425 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 426 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 427 } 428
Indexes created Wed Sep 24 22:09:59 GMT 2025