if_fxp_pci.c revision 1.33 1 1.33 jdolecek /* $NetBSD: if_fxp_pci.c,v 1.33 2003/03/14 22:04:03 jdolecek Exp $ */
2 1.1 thorpej
3 1.1 thorpej /*-
4 1.15 thorpej * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
5 1.1 thorpej * All rights reserved.
6 1.1 thorpej *
7 1.1 thorpej * This code is derived from software contributed to The NetBSD Foundation
8 1.1 thorpej * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.1 thorpej * NASA Ames Research Center.
10 1.1 thorpej *
11 1.1 thorpej * Redistribution and use in source and binary forms, with or without
12 1.1 thorpej * modification, are permitted provided that the following conditions
13 1.1 thorpej * are met:
14 1.1 thorpej * 1. Redistributions of source code must retain the above copyright
15 1.1 thorpej * notice, this list of conditions and the following disclaimer.
16 1.1 thorpej * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 thorpej * notice, this list of conditions and the following disclaimer in the
18 1.1 thorpej * documentation and/or other materials provided with the distribution.
19 1.1 thorpej * 3. All advertising materials mentioning features or use of this software
20 1.1 thorpej * must display the following acknowledgement:
21 1.1 thorpej * This product includes software developed by the NetBSD
22 1.1 thorpej * Foundation, Inc. and its contributors.
23 1.1 thorpej * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 thorpej * contributors may be used to endorse or promote products derived
25 1.1 thorpej * from this software without specific prior written permission.
26 1.1 thorpej *
27 1.1 thorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 thorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 thorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 thorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 thorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 thorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 thorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 thorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 thorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 thorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 thorpej * POSSIBILITY OF SUCH DAMAGE.
38 1.1 thorpej */
39 1.1 thorpej
40 1.1 thorpej /*
41 1.1 thorpej * PCI bus front-end for the Intel i82557 fast Ethernet controller
42 1.1 thorpej * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards.
43 1.1 thorpej */
44 1.21 lukem
45 1.21 lukem #include <sys/cdefs.h>
46 1.33 jdolecek __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.33 2003/03/14 22:04:03 jdolecek Exp $");
47 1.1 thorpej
48 1.1 thorpej #include "rnd.h"
49 1.1 thorpej
50 1.1 thorpej #include <sys/param.h>
51 1.1 thorpej #include <sys/systm.h>
52 1.1 thorpej #include <sys/mbuf.h>
53 1.1 thorpej #include <sys/malloc.h>
54 1.1 thorpej #include <sys/kernel.h>
55 1.1 thorpej #include <sys/socket.h>
56 1.1 thorpej #include <sys/ioctl.h>
57 1.1 thorpej #include <sys/errno.h>
58 1.1 thorpej #include <sys/device.h>
59 1.1 thorpej
60 1.1 thorpej #if NRND > 0
61 1.1 thorpej #include <sys/rnd.h>
62 1.1 thorpej #endif
63 1.3 thorpej
64 1.3 thorpej #include <machine/endian.h>
65 1.1 thorpej
66 1.1 thorpej #include <net/if.h>
67 1.1 thorpej #include <net/if_dl.h>
68 1.1 thorpej #include <net/if_media.h>
69 1.1 thorpej #include <net/if_ether.h>
70 1.1 thorpej
71 1.1 thorpej #include <machine/bus.h>
72 1.1 thorpej #include <machine/intr.h>
73 1.1 thorpej
74 1.1 thorpej #include <dev/mii/miivar.h>
75 1.1 thorpej
76 1.1 thorpej #include <dev/ic/i82557reg.h>
77 1.1 thorpej #include <dev/ic/i82557var.h>
78 1.1 thorpej
79 1.1 thorpej #include <dev/pci/pcivar.h>
80 1.1 thorpej #include <dev/pci/pcireg.h>
81 1.1 thorpej #include <dev/pci/pcidevs.h>
82 1.1 thorpej
83 1.7 jhawk struct fxp_pci_softc {
84 1.7 jhawk struct fxp_softc psc_fxp;
85 1.7 jhawk
86 1.7 jhawk pci_chipset_tag_t psc_pc; /* pci chipset tag */
87 1.7 jhawk pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */
88 1.7 jhawk pcitag_t psc_tag; /* pci register tag */
89 1.7 jhawk void *psc_powerhook; /* power hook */
90 1.19 thorpej
91 1.19 thorpej int psc_pwrmgmt_csr_reg; /* ACPI power management register */
92 1.19 thorpej pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */
93 1.7 jhawk };
94 1.6 jhawk
95 1.1 thorpej int fxp_pci_match __P((struct device *, struct cfdata *, void *));
96 1.1 thorpej void fxp_pci_attach __P((struct device *, struct device *, void *));
97 1.1 thorpej
98 1.19 thorpej int fxp_pci_enable __P((struct fxp_softc *));
99 1.19 thorpej void fxp_pci_disable __P((struct fxp_softc *));
100 1.19 thorpej
101 1.6 jhawk static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc));
102 1.6 jhawk static void fxp_pci_power __P((int why, void *arg));
103 1.6 jhawk
104 1.28 thorpej CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc),
105 1.29 thorpej fxp_pci_match, fxp_pci_attach, NULL, NULL);
106 1.1 thorpej
107 1.5 thorpej const struct fxp_pci_product {
108 1.5 thorpej u_int32_t fpp_prodid; /* PCI product ID */
109 1.5 thorpej const char *fpp_name; /* device name */
110 1.5 thorpej } fxp_pci_products[] = {
111 1.5 thorpej { PCI_PRODUCT_INTEL_82557,
112 1.5 thorpej "Intel i82557 Ethernet" },
113 1.9 mycroft { PCI_PRODUCT_INTEL_82559ER,
114 1.9 mycroft "Intel i82559ER Ethernet" },
115 1.5 thorpej { PCI_PRODUCT_INTEL_IN_BUSINESS,
116 1.5 thorpej "Intel InBusiness Ethernet" },
117 1.11 ad { PCI_PRODUCT_INTEL_82801BA_LAN,
118 1.11 ad "Intel i82562 Ethernet" },
119 1.24 msaitoh { PCI_PRODUCT_INTEL_82801E_LAN_1,
120 1.24 msaitoh "Intel i82559 Ethernet" },
121 1.24 msaitoh { PCI_PRODUCT_INTEL_82801E_LAN_2,
122 1.24 msaitoh "Intel i82559 Ethernet" },
123 1.20 itojun { PCI_PRODUCT_INTEL_PRO_100_VE_0,
124 1.20 itojun "Intel PRO/100 VE Network Controller" },
125 1.20 itojun { PCI_PRODUCT_INTEL_PRO_100_VE_1,
126 1.20 itojun "Intel PRO/100 VE Network Controller" },
127 1.23 cjs { PCI_PRODUCT_INTEL_PRO_100_VE_2,
128 1.23 cjs "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" },
129 1.23 cjs { PCI_PRODUCT_INTEL_PRO_100_VE_3,
130 1.23 cjs "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" },
131 1.23 cjs { PCI_PRODUCT_INTEL_PRO_100_VE_4,
132 1.23 cjs "Intel PRO/100 VE (MOB) Network Controller" },
133 1.25 abs { PCI_PRODUCT_INTEL_PRO_100_VM_0,
134 1.25 abs "Intel PRO/100 VM Network Controller" },
135 1.25 abs { PCI_PRODUCT_INTEL_PRO_100_VM_1,
136 1.25 abs "Intel PRO/100 VM Network Controller" },
137 1.25 abs { PCI_PRODUCT_INTEL_PRO_100_VM_2,
138 1.25 abs "Intel PRO/100 VM Network Controller" },
139 1.33 jdolecek { PCI_PRODUCT_INTEL_PRO_100_VM_3,
140 1.33 jdolecek "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" },
141 1.33 jdolecek { PCI_PRODUCT_INTEL_PRO_100_VM_4,
142 1.33 jdolecek "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" },
143 1.32 grant { PCI_PRODUCT_INTEL_PRO_100_M,
144 1.32 grant "Intel PRO/100 M Network Controller" },
145 1.5 thorpej { 0,
146 1.5 thorpej NULL },
147 1.5 thorpej };
148 1.5 thorpej
149 1.15 thorpej static const struct fxp_pci_product *
150 1.15 thorpej fxp_pci_lookup(const struct pci_attach_args *pa)
151 1.5 thorpej {
152 1.5 thorpej const struct fxp_pci_product *fpp;
153 1.5 thorpej
154 1.5 thorpej if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
155 1.5 thorpej return (NULL);
156 1.5 thorpej
157 1.5 thorpej for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++)
158 1.5 thorpej if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid)
159 1.5 thorpej return (fpp);
160 1.5 thorpej
161 1.5 thorpej return (NULL);
162 1.5 thorpej }
163 1.5 thorpej
164 1.1 thorpej int
165 1.1 thorpej fxp_pci_match(parent, match, aux)
166 1.1 thorpej struct device *parent;
167 1.1 thorpej struct cfdata *match;
168 1.1 thorpej void *aux;
169 1.1 thorpej {
170 1.1 thorpej struct pci_attach_args *pa = aux;
171 1.1 thorpej
172 1.5 thorpej if (fxp_pci_lookup(pa) != NULL)
173 1.1 thorpej return (1);
174 1.1 thorpej
175 1.1 thorpej return (0);
176 1.1 thorpej }
177 1.1 thorpej
178 1.6 jhawk /*
179 1.6 jhawk * Restore PCI configuration registers that may have been clobbered.
180 1.6 jhawk * This is necessary due to bugs on the Sony VAIO Z505-series on-board
181 1.6 jhawk * ethernet, after an APM suspend/resume, as well as after an ACPI
182 1.6 jhawk * D3->D0 transition. We call this function from a power hook after
183 1.6 jhawk * APM resume events, as well as after the ACPI D3->D0 transition.
184 1.6 jhawk */
185 1.6 jhawk static void
186 1.6 jhawk fxp_pci_confreg_restore(psc)
187 1.6 jhawk struct fxp_pci_softc *psc;
188 1.6 jhawk {
189 1.6 jhawk pcireg_t reg;
190 1.6 jhawk
191 1.6 jhawk #if 0
192 1.6 jhawk /*
193 1.6 jhawk * Check to see if the command register is blank -- if so, then
194 1.6 jhawk * we'll assume that all the clobberable-registers have been
195 1.6 jhawk * clobbered.
196 1.6 jhawk */
197 1.6 jhawk
198 1.6 jhawk /*
199 1.6 jhawk * In general, the above metric is accurate. Unfortunately,
200 1.6 jhawk * it is inaccurate across a hibernation. Ideally APM/ACPI
201 1.6 jhawk * code should take note of hibernation events and execute
202 1.6 jhawk * a hibernation wakeup hook, but at present a hibernation wake
203 1.6 jhawk * is indistinguishable from a suspend wake.
204 1.6 jhawk */
205 1.6 jhawk
206 1.6 jhawk if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag,
207 1.6 jhawk PCI_COMMAND_STATUS_REG)) & 0xffff) != 0)
208 1.6 jhawk return;
209 1.10 jhawk #else
210 1.10 jhawk reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG);
211 1.6 jhawk #endif
212 1.6 jhawk
213 1.6 jhawk pci_conf_write(psc->psc_pc, psc->psc_tag,
214 1.6 jhawk PCI_COMMAND_STATUS_REG,
215 1.6 jhawk (reg & 0xffff0000) |
216 1.6 jhawk (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff));
217 1.6 jhawk pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG,
218 1.6 jhawk psc->psc_regs[PCI_BHLC_REG>>2]);
219 1.6 jhawk pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0,
220 1.6 jhawk psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]);
221 1.6 jhawk pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4,
222 1.6 jhawk psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]);
223 1.6 jhawk pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8,
224 1.6 jhawk psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]);
225 1.6 jhawk }
226 1.6 jhawk
227 1.6 jhawk
228 1.6 jhawk /*
229 1.6 jhawk * Power handler routine. Called when the system is transitioning into/out
230 1.6 jhawk * of power save modes. We restore the (bashed) PCI configuration registers
231 1.6 jhawk * on a resume.
232 1.6 jhawk */
233 1.6 jhawk static void
234 1.6 jhawk fxp_pci_power(why, arg)
235 1.6 jhawk int why;
236 1.6 jhawk void *arg;
237 1.6 jhawk {
238 1.6 jhawk struct fxp_pci_softc *psc = arg;
239 1.6 jhawk
240 1.6 jhawk if (why == PWR_RESUME)
241 1.6 jhawk fxp_pci_confreg_restore(psc);
242 1.6 jhawk }
243 1.6 jhawk
244 1.1 thorpej void
245 1.1 thorpej fxp_pci_attach(parent, self, aux)
246 1.1 thorpej struct device *parent, *self;
247 1.1 thorpej void *aux;
248 1.1 thorpej {
249 1.6 jhawk struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self;
250 1.1 thorpej struct fxp_softc *sc = (struct fxp_softc *)self;
251 1.1 thorpej struct pci_attach_args *pa = aux;
252 1.1 thorpej pci_chipset_tag_t pc = pa->pa_pc;
253 1.1 thorpej pci_intr_handle_t ih;
254 1.5 thorpej const struct fxp_pci_product *fpp;
255 1.1 thorpej const char *intrstr = NULL;
256 1.1 thorpej bus_space_tag_t iot, memt;
257 1.1 thorpej bus_space_handle_t ioh, memh;
258 1.1 thorpej int ioh_valid, memh_valid;
259 1.1 thorpej bus_addr_t addr;
260 1.1 thorpej bus_size_t size;
261 1.1 thorpej int flags;
262 1.19 thorpej int pci_pwrmgmt_cap_reg;
263 1.1 thorpej
264 1.31 thorpej aprint_naive(": Ethernet controller\n");
265 1.31 thorpej
266 1.1 thorpej /*
267 1.1 thorpej * Map control/status registers.
268 1.1 thorpej */
269 1.1 thorpej ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA,
270 1.1 thorpej PCI_MAPREG_TYPE_IO, 0,
271 1.1 thorpej &iot, &ioh, NULL, NULL) == 0);
272 1.1 thorpej
273 1.1 thorpej /*
274 1.1 thorpej * Version 2.1 of the PCI spec, page 196, "Address Maps":
275 1.1 thorpej *
276 1.1 thorpej * Prefetchable
277 1.1 thorpej *
278 1.1 thorpej * Set to one if there are no side effects on reads, the
279 1.1 thorpej * device returns all bytes regardless of the byte enables,
280 1.1 thorpej * and host bridges can merge processor writes into this
281 1.1 thorpej * range without causing errors. Bit must be set to zero
282 1.1 thorpej * otherwise.
283 1.1 thorpej *
284 1.1 thorpej * The 82557 incorrectly sets the "prefetchable" bit, resulting
285 1.1 thorpej * in errors on systems which will do merged reads and writes.
286 1.1 thorpej * These errors manifest themselves as all-bits-set when reading
287 1.1 thorpej * from the EEPROM or other < 4 byte registers.
288 1.1 thorpej *
289 1.1 thorpej * We must work around this problem by always forcing the mapping
290 1.1 thorpej * for memory space to be uncacheable. On systems which cannot
291 1.1 thorpej * create an uncacheable mapping (because the firmware mapped it
292 1.1 thorpej * into only cacheable/prefetchable space due to the "prefetchable"
293 1.1 thorpej * bit), we can fall back onto i/o mapped access.
294 1.1 thorpej */
295 1.1 thorpej memh_valid = 0;
296 1.1 thorpej memt = pa->pa_memt;
297 1.1 thorpej if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) &&
298 1.1 thorpej pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA,
299 1.1 thorpej PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT,
300 1.1 thorpej &addr, &size, &flags) == 0) {
301 1.4 drochner flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
302 1.1 thorpej if (bus_space_map(memt, addr, size, flags, &memh) == 0)
303 1.1 thorpej memh_valid = 1;
304 1.1 thorpej }
305 1.1 thorpej
306 1.1 thorpej if (memh_valid) {
307 1.1 thorpej sc->sc_st = memt;
308 1.1 thorpej sc->sc_sh = memh;
309 1.1 thorpej } else if (ioh_valid) {
310 1.1 thorpej sc->sc_st = iot;
311 1.1 thorpej sc->sc_sh = ioh;
312 1.1 thorpej } else {
313 1.31 thorpej aprint_error(": unable to map device registers\n");
314 1.1 thorpej return;
315 1.1 thorpej }
316 1.1 thorpej
317 1.1 thorpej sc->sc_dmat = pa->pa_dmat;
318 1.1 thorpej
319 1.5 thorpej fpp = fxp_pci_lookup(pa);
320 1.5 thorpej if (fpp == NULL) {
321 1.5 thorpej printf("\n");
322 1.5 thorpej panic("fxp_pci_attach: impossible");
323 1.5 thorpej }
324 1.5 thorpej
325 1.15 thorpej sc->sc_rev = PCI_REVISION(pa->pa_class);
326 1.13 thorpej
327 1.15 thorpej switch (fpp->fpp_prodid) {
328 1.15 thorpej case PCI_PRODUCT_INTEL_82557:
329 1.15 thorpej case PCI_PRODUCT_INTEL_82559ER:
330 1.15 thorpej case PCI_PRODUCT_INTEL_IN_BUSINESS:
331 1.15 thorpej {
332 1.15 thorpej const char *chipname = NULL;
333 1.15 thorpej
334 1.16 thorpej if (sc->sc_rev >= FXP_REV_82558_A4) {
335 1.15 thorpej chipname = "i82558 Ethernet";
336 1.16 thorpej /*
337 1.16 thorpej * Enable the MWI command for memory writes.
338 1.16 thorpej */
339 1.16 thorpej if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
340 1.16 thorpej sc->sc_flags |= FXPF_MWI;
341 1.16 thorpej }
342 1.15 thorpej if (sc->sc_rev >= FXP_REV_82559_A0)
343 1.15 thorpej chipname = "i82559 Ethernet";
344 1.15 thorpej if (sc->sc_rev >= FXP_REV_82559S_A)
345 1.15 thorpej chipname = "i82559S Ethernet";
346 1.15 thorpej if (sc->sc_rev >= FXP_REV_82550)
347 1.15 thorpej chipname = "i82550 Ethernet";
348 1.22 thorpej
349 1.22 thorpej /*
350 1.22 thorpej * Mark all i82559 and i82550 revisions as having
351 1.22 thorpej * the "resume bug". See i82557.c for details.
352 1.22 thorpej */
353 1.22 thorpej if (sc->sc_rev >= FXP_REV_82559_A0)
354 1.22 thorpej sc->sc_flags |= FXPF_HAS_RESUME_BUG;
355 1.15 thorpej
356 1.31 thorpej aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname :
357 1.15 thorpej fpp->fpp_name, sc->sc_rev);
358 1.15 thorpej break;
359 1.15 thorpej }
360 1.15 thorpej
361 1.15 thorpej case PCI_PRODUCT_INTEL_82801BA_LAN:
362 1.31 thorpej aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev);
363 1.15 thorpej
364 1.15 thorpej /*
365 1.15 thorpej * The 82801BA Ethernet has a bug which requires us to send a
366 1.15 thorpej * NOP before a CU_RESUME if we're in 10baseT mode.
367 1.15 thorpej */
368 1.15 thorpej if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN)
369 1.15 thorpej sc->sc_flags |= FXPF_HAS_RESUME_BUG;
370 1.15 thorpej break;
371 1.15 thorpej
372 1.15 thorpej case PCI_PRODUCT_INTEL_PRO_100_VE_0:
373 1.15 thorpej case PCI_PRODUCT_INTEL_PRO_100_VE_1:
374 1.15 thorpej case PCI_PRODUCT_INTEL_PRO_100_VM_0:
375 1.15 thorpej case PCI_PRODUCT_INTEL_PRO_100_VM_1:
376 1.15 thorpej case PCI_PRODUCT_INTEL_82562EH_HPNA_0:
377 1.15 thorpej case PCI_PRODUCT_INTEL_82562EH_HPNA_1:
378 1.15 thorpej case PCI_PRODUCT_INTEL_82562EH_HPNA_2:
379 1.15 thorpej case PCI_PRODUCT_INTEL_PRO_100_VM_2:
380 1.33 jdolecek case PCI_PRODUCT_INTEL_PRO_100_VM_3:
381 1.33 jdolecek case PCI_PRODUCT_INTEL_PRO_100_VM_4:
382 1.31 thorpej aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev);
383 1.15 thorpej
384 1.15 thorpej /*
385 1.15 thorpej * ICH3 chips apparently have problems with the enhanced
386 1.15 thorpej * features, so just treat them as an i82557. It also
387 1.15 thorpej * has the resume bug that the ICH2 has.
388 1.15 thorpej */
389 1.15 thorpej sc->sc_rev = 1;
390 1.13 thorpej sc->sc_flags |= FXPF_HAS_RESUME_BUG;
391 1.24 msaitoh break;
392 1.24 msaitoh case PCI_PRODUCT_INTEL_82801E_LAN_1:
393 1.24 msaitoh case PCI_PRODUCT_INTEL_82801E_LAN_2:
394 1.31 thorpej aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev);
395 1.24 msaitoh
396 1.24 msaitoh /*
397 1.24 msaitoh * XXX We have to read the C-ICH's developer's manual
398 1.24 msaitoh * in detail
399 1.24 msaitoh */
400 1.15 thorpej break;
401 1.15 thorpej }
402 1.1 thorpej
403 1.1 thorpej /* Make sure bus-mastering is enabled. */
404 1.1 thorpej pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
405 1.1 thorpej pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
406 1.1 thorpej PCI_COMMAND_MASTER_ENABLE);
407 1.1 thorpej
408 1.6 jhawk /*
409 1.6 jhawk * Under some circumstances (such as APM suspend/resume
410 1.6 jhawk * cycles, and across ACPI power state changes), the
411 1.6 jhawk * i82257-family can lose the contents of critical PCI
412 1.6 jhawk * configuration registers, causing the card to be
413 1.6 jhawk * non-responsive and useless. This occurs on the Sony VAIO
414 1.6 jhawk * Z505-series, among others. Preserve them here so they can
415 1.6 jhawk * be later restored (by fxp_pci_confreg_restore()).
416 1.6 jhawk */
417 1.6 jhawk psc->psc_pc = pc;
418 1.6 jhawk psc->psc_tag = pa->pa_tag;
419 1.6 jhawk psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] =
420 1.6 jhawk pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
421 1.6 jhawk psc->psc_regs[PCI_BHLC_REG>>2] =
422 1.6 jhawk pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG);
423 1.6 jhawk psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] =
424 1.6 jhawk pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0);
425 1.6 jhawk psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] =
426 1.6 jhawk pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4);
427 1.6 jhawk psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] =
428 1.6 jhawk pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8);
429 1.6 jhawk
430 1.6 jhawk /*
431 1.6 jhawk * Work around BIOS ACPI bugs where the chip is inadvertantly
432 1.6 jhawk * left in ACPI D3 (lowest power state). First confirm the device
433 1.6 jhawk * supports ACPI power management, then move it to the D0 (fully
434 1.6 jhawk * functional) state if it is not already there.
435 1.6 jhawk */
436 1.6 jhawk if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT,
437 1.6 jhawk &pci_pwrmgmt_cap_reg, 0)) {
438 1.6 jhawk pcireg_t reg;
439 1.6 jhawk
440 1.19 thorpej sc->sc_enable = fxp_pci_enable;
441 1.19 thorpej sc->sc_disable = fxp_pci_disable;
442 1.19 thorpej
443 1.30 tsutsui psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR;
444 1.19 thorpej reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg);
445 1.19 thorpej psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) |
446 1.19 thorpej PCI_PMCSR_STATE_D0;
447 1.19 thorpej if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0)
448 1.19 thorpej pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg,
449 1.19 thorpej psc->psc_pwrmgmt_csr);
450 1.6 jhawk }
451 1.6 jhawk /* Restore PCI configuration registers. */
452 1.6 jhawk fxp_pci_confreg_restore(psc);
453 1.6 jhawk
454 1.19 thorpej sc->sc_enabled = 1;
455 1.19 thorpej
456 1.1 thorpej /*
457 1.1 thorpej * Map and establish our interrupt.
458 1.1 thorpej */
459 1.12 sommerfe if (pci_intr_map(pa, &ih)) {
460 1.31 thorpej aprint_error("%s: couldn't map interrupt\n",
461 1.31 thorpej sc->sc_dev.dv_xname);
462 1.1 thorpej return;
463 1.1 thorpej }
464 1.1 thorpej intrstr = pci_intr_string(pc, ih);
465 1.8 jhawk sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc);
466 1.8 jhawk if (sc->sc_ih == NULL) {
467 1.31 thorpej aprint_error("%s: couldn't establish interrupt",
468 1.1 thorpej sc->sc_dev.dv_xname);
469 1.1 thorpej if (intrstr != NULL)
470 1.31 thorpej aprint_normal(" at %s", intrstr);
471 1.31 thorpej aprint_normal("\n");
472 1.1 thorpej return;
473 1.1 thorpej }
474 1.31 thorpej aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
475 1.1 thorpej
476 1.1 thorpej /* Finish off the attach. */
477 1.1 thorpej fxp_attach(sc);
478 1.19 thorpej if (sc->sc_disable != NULL)
479 1.19 thorpej fxp_disable(sc);
480 1.6 jhawk
481 1.6 jhawk /* Add a suspend hook to restore PCI config state */
482 1.6 jhawk psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc);
483 1.6 jhawk if (psc->psc_powerhook == NULL)
484 1.31 thorpej aprint_error(
485 1.31 thorpej "%s: WARNING: unable to establish pci power hook\n",
486 1.6 jhawk sc->sc_dev.dv_xname);
487 1.19 thorpej }
488 1.19 thorpej
489 1.19 thorpej int
490 1.19 thorpej fxp_pci_enable(struct fxp_softc *sc)
491 1.19 thorpej {
492 1.19 thorpej struct fxp_pci_softc *psc = (void *) sc;
493 1.19 thorpej
494 1.19 thorpej #if 0
495 1.19 thorpej printf("%s: going to power state D0\n", sc->sc_dev.dv_xname);
496 1.19 thorpej #endif
497 1.19 thorpej
498 1.19 thorpej /* Bring the device into D0 power state. */
499 1.19 thorpej pci_conf_write(psc->psc_pc, psc->psc_tag,
500 1.19 thorpej psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr);
501 1.19 thorpej
502 1.19 thorpej /* Now restore the configuration registers. */
503 1.19 thorpej fxp_pci_confreg_restore(psc);
504 1.19 thorpej
505 1.19 thorpej return (0);
506 1.19 thorpej }
507 1.19 thorpej
508 1.19 thorpej void
509 1.19 thorpej fxp_pci_disable(struct fxp_softc *sc)
510 1.19 thorpej {
511 1.19 thorpej struct fxp_pci_softc *psc = (void *) sc;
512 1.26 itojun
513 1.26 itojun /*
514 1.26 itojun * for some 82558_A4 and 82558_B0, entering D3 state makes
515 1.26 itojun * media detection disordered.
516 1.26 itojun */
517 1.26 itojun if (sc->sc_rev <= FXP_REV_82558_B0)
518 1.26 itojun return;
519 1.19 thorpej
520 1.19 thorpej #if 0
521 1.19 thorpej printf("%s: going to power state D3\n", sc->sc_dev.dv_xname);
522 1.19 thorpej #endif
523 1.19 thorpej
524 1.19 thorpej /* Put the device into D3 state. */
525 1.19 thorpej pci_conf_write(psc->psc_pc, psc->psc_tag,
526 1.19 thorpej psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr &
527 1.19 thorpej ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3);
528 1.1 thorpej }
529