if_fxp_pci.c revision 1.12.2.1
1 /* $NetBSD: if_fxp_pci.c,v 1.12.2.1 2001/06/21 20:04:43 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include "bpfilter.h" 46 #include "rnd.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 58 #if NRND > 0 59 #include <sys/rnd.h> 60 #endif 61 62 #include <machine/endian.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_ether.h> 68 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #endif 72 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 76 #include <dev/mii/miivar.h> 77 78 #include <dev/ic/i82557reg.h> 79 #include <dev/ic/i82557var.h> 80 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcidevs.h> 84 85 struct fxp_pci_softc { 86 struct fxp_softc psc_fxp; 87 88 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 89 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 90 pcitag_t psc_tag; /* pci register tag */ 91 void *psc_powerhook; /* power hook */ 92 }; 93 94 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 95 void fxp_pci_attach __P((struct device *, struct device *, void *)); 96 97 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 98 static void fxp_pci_power __P((int why, void *arg)); 99 100 struct cfattach fxp_pci_ca = { 101 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 102 }; 103 104 const struct fxp_pci_product { 105 u_int32_t fpp_prodid; /* PCI product ID */ 106 const char *fpp_name; /* device name */ 107 } fxp_pci_products[] = { 108 { PCI_PRODUCT_INTEL_82557, 109 "Intel i82557 Ethernet" }, 110 { PCI_PRODUCT_INTEL_82559ER, 111 "Intel i82559ER Ethernet" }, 112 { PCI_PRODUCT_INTEL_IN_BUSINESS, 113 "Intel InBusiness Ethernet" }, 114 { PCI_PRODUCT_INTEL_82801BA_LAN, 115 "Intel i82562 Ethernet" }, 116 { 0, 117 NULL }, 118 }; 119 120 static const struct fxp_pci_product * 121 fxp_pci_lookup(const struct pci_attach_args *pa) 122 { 123 const struct fxp_pci_product *fpp; 124 125 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 126 return (NULL); 127 128 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 129 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 130 return (fpp); 131 132 return (NULL); 133 } 134 135 int 136 fxp_pci_match(parent, match, aux) 137 struct device *parent; 138 struct cfdata *match; 139 void *aux; 140 { 141 struct pci_attach_args *pa = aux; 142 143 if (fxp_pci_lookup(pa) != NULL) 144 return (1); 145 146 return (0); 147 } 148 149 /* 150 * Restore PCI configuration registers that may have been clobbered. 151 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 152 * ethernet, after an APM suspend/resume, as well as after an ACPI 153 * D3->D0 transition. We call this function from a power hook after 154 * APM resume events, as well as after the ACPI D3->D0 transition. 155 */ 156 static void 157 fxp_pci_confreg_restore(psc) 158 struct fxp_pci_softc *psc; 159 { 160 pcireg_t reg; 161 162 #if 0 163 /* 164 * Check to see if the command register is blank -- if so, then 165 * we'll assume that all the clobberable-registers have been 166 * clobbered. 167 */ 168 169 /* 170 * In general, the above metric is accurate. Unfortunately, 171 * it is inaccurate across a hibernation. Ideally APM/ACPI 172 * code should take note of hibernation events and execute 173 * a hibernation wakeup hook, but at present a hibernation wake 174 * is indistinguishable from a suspend wake. 175 */ 176 177 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 178 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 179 return; 180 #else 181 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 182 #endif 183 184 pci_conf_write(psc->psc_pc, psc->psc_tag, 185 PCI_COMMAND_STATUS_REG, 186 (reg & 0xffff0000) | 187 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 188 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 189 psc->psc_regs[PCI_BHLC_REG>>2]); 190 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 191 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 192 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 193 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 194 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 195 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 196 } 197 198 199 /* 200 * Power handler routine. Called when the system is transitioning into/out 201 * of power save modes. We restore the (bashed) PCI configuration registers 202 * on a resume. 203 */ 204 static void 205 fxp_pci_power(why, arg) 206 int why; 207 void *arg; 208 { 209 struct fxp_pci_softc *psc = arg; 210 211 if (why == PWR_RESUME) 212 fxp_pci_confreg_restore(psc); 213 } 214 215 void 216 fxp_pci_attach(parent, self, aux) 217 struct device *parent, *self; 218 void *aux; 219 { 220 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 221 struct fxp_softc *sc = (struct fxp_softc *)self; 222 struct pci_attach_args *pa = aux; 223 pci_chipset_tag_t pc = pa->pa_pc; 224 pci_intr_handle_t ih; 225 const struct fxp_pci_product *fpp; 226 const char *intrstr = NULL; 227 bus_space_tag_t iot, memt; 228 bus_space_handle_t ioh, memh; 229 int ioh_valid, memh_valid; 230 bus_addr_t addr; 231 bus_size_t size; 232 int flags; 233 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 234 235 sc->sc_enabled = 1; 236 sc->sc_enable = NULL; 237 sc->sc_disable = NULL; 238 239 /* 240 * Map control/status registers. 241 */ 242 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 243 PCI_MAPREG_TYPE_IO, 0, 244 &iot, &ioh, NULL, NULL) == 0); 245 246 /* 247 * Version 2.1 of the PCI spec, page 196, "Address Maps": 248 * 249 * Prefetchable 250 * 251 * Set to one if there are no side effects on reads, the 252 * device returns all bytes regardless of the byte enables, 253 * and host bridges can merge processor writes into this 254 * range without causing errors. Bit must be set to zero 255 * otherwise. 256 * 257 * The 82557 incorrectly sets the "prefetchable" bit, resulting 258 * in errors on systems which will do merged reads and writes. 259 * These errors manifest themselves as all-bits-set when reading 260 * from the EEPROM or other < 4 byte registers. 261 * 262 * We must work around this problem by always forcing the mapping 263 * for memory space to be uncacheable. On systems which cannot 264 * create an uncacheable mapping (because the firmware mapped it 265 * into only cacheable/prefetchable space due to the "prefetchable" 266 * bit), we can fall back onto i/o mapped access. 267 */ 268 memh_valid = 0; 269 memt = pa->pa_memt; 270 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 271 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 272 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 273 &addr, &size, &flags) == 0) { 274 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 275 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 276 memh_valid = 1; 277 } 278 279 if (memh_valid) { 280 sc->sc_st = memt; 281 sc->sc_sh = memh; 282 } else if (ioh_valid) { 283 sc->sc_st = iot; 284 sc->sc_sh = ioh; 285 } else { 286 printf(": unable to map device registers\n"); 287 return; 288 } 289 290 sc->sc_dmat = pa->pa_dmat; 291 292 fpp = fxp_pci_lookup(pa); 293 if (fpp == NULL) { 294 printf("\n"); 295 panic("fxp_pci_attach: impossible"); 296 } 297 298 sc->sc_rev = PCI_REVISION(pa->pa_class); 299 300 switch (fpp->fpp_prodid) { 301 case PCI_PRODUCT_INTEL_82557: 302 case PCI_PRODUCT_INTEL_82559ER: 303 case PCI_PRODUCT_INTEL_IN_BUSINESS: 304 { 305 const char *chipname = NULL; 306 307 if (sc->sc_rev >= FXP_REV_82558_A4) { 308 chipname = "i82558 Ethernet"; 309 /* 310 * Enable the MWI command for memory writes. 311 */ 312 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 313 sc->sc_flags |= FXPF_MWI; 314 } 315 if (sc->sc_rev >= FXP_REV_82559_A0) 316 chipname = "i82559 Ethernet"; 317 if (sc->sc_rev >= FXP_REV_82559S_A) 318 chipname = "i82559S Ethernet"; 319 if (sc->sc_rev >= FXP_REV_82550) 320 chipname = "i82550 Ethernet"; 321 322 printf(": %s, rev %d\n", chipname != NULL ? chipname : 323 fpp->fpp_name, sc->sc_rev); 324 break; 325 } 326 327 case PCI_PRODUCT_INTEL_82801BA_LAN: 328 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 329 330 /* 331 * The 82801BA Ethernet has a bug which requires us to send a 332 * NOP before a CU_RESUME if we're in 10baseT mode. 333 */ 334 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 335 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 336 break; 337 338 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 339 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 340 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 341 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 342 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 343 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 344 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 345 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 346 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 347 348 /* 349 * ICH3 chips apparently have problems with the enhanced 350 * features, so just treat them as an i82557. It also 351 * has the resume bug that the ICH2 has. 352 */ 353 sc->sc_rev = 1; 354 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 355 break; 356 } 357 358 /* Make sure bus-mastering is enabled. */ 359 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 360 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 361 PCI_COMMAND_MASTER_ENABLE); 362 363 /* 364 * Under some circumstances (such as APM suspend/resume 365 * cycles, and across ACPI power state changes), the 366 * i82257-family can lose the contents of critical PCI 367 * configuration registers, causing the card to be 368 * non-responsive and useless. This occurs on the Sony VAIO 369 * Z505-series, among others. Preserve them here so they can 370 * be later restored (by fxp_pci_confreg_restore()). 371 */ 372 psc->psc_pc = pc; 373 psc->psc_tag = pa->pa_tag; 374 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 375 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 376 psc->psc_regs[PCI_BHLC_REG>>2] = 377 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 378 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 379 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 380 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 381 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 382 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 383 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 384 385 /* 386 * Work around BIOS ACPI bugs where the chip is inadvertantly 387 * left in ACPI D3 (lowest power state). First confirm the device 388 * supports ACPI power management, then move it to the D0 (fully 389 * functional) state if it is not already there. 390 */ 391 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 392 &pci_pwrmgmt_cap_reg, 0)) { 393 pcireg_t reg; 394 395 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 396 reg = pci_conf_read(pc, pa->pa_tag, pci_pwrmgmt_csr_reg); 397 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 398 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 399 (reg & ~PCI_PMCSR_STATE_MASK) | 400 PCI_PMCSR_STATE_D0); 401 } 402 } 403 /* Restore PCI configuration registers. */ 404 fxp_pci_confreg_restore(psc); 405 406 /* 407 * Map and establish our interrupt. 408 */ 409 if (pci_intr_map(pa, &ih)) { 410 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 411 return; 412 } 413 intrstr = pci_intr_string(pc, ih); 414 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 415 if (sc->sc_ih == NULL) { 416 printf("%s: couldn't establish interrupt", 417 sc->sc_dev.dv_xname); 418 if (intrstr != NULL) 419 printf(" at %s", intrstr); 420 printf("\n"); 421 return; 422 } 423 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 424 425 /* Finish off the attach. */ 426 fxp_attach(sc); 427 428 /* Add a suspend hook to restore PCI config state */ 429 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 430 if (psc->psc_powerhook == NULL) 431 printf ("%s: WARNING: unable to establish pci power hook\n", 432 sc->sc_dev.dv_xname); 433 434 } 435
Indexes created Thu Oct 02 01:09:59 GMT 2025