if_fxp_pci.c revision 1.18.2.1
1 /* $NetBSD: if_fxp_pci.c,v 1.18.2.1 2001/08/25 06:16:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include "rnd.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #if NRND > 0 58 #include <sys/rnd.h> 59 #endif 60 61 #include <machine/endian.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #include <machine/bus.h> 69 #include <machine/intr.h> 70 71 #include <dev/mii/miivar.h> 72 73 #include <dev/ic/i82557reg.h> 74 #include <dev/ic/i82557var.h> 75 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcidevs.h> 79 80 struct fxp_pci_softc { 81 struct fxp_softc psc_fxp; 82 83 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 84 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 85 pcitag_t psc_tag; /* pci register tag */ 86 void *psc_powerhook; /* power hook */ 87 88 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 89 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 90 }; 91 92 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 93 void fxp_pci_attach __P((struct device *, struct device *, void *)); 94 95 int fxp_pci_enable __P((struct fxp_softc *)); 96 void fxp_pci_disable __P((struct fxp_softc *)); 97 98 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 99 static void fxp_pci_power __P((int why, void *arg)); 100 101 struct cfattach fxp_pci_ca = { 102 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 103 }; 104 105 const struct fxp_pci_product { 106 u_int32_t fpp_prodid; /* PCI product ID */ 107 const char *fpp_name; /* device name */ 108 } fxp_pci_products[] = { 109 { PCI_PRODUCT_INTEL_82557, 110 "Intel i82557 Ethernet" }, 111 { PCI_PRODUCT_INTEL_82559ER, 112 "Intel i82559ER Ethernet" }, 113 { PCI_PRODUCT_INTEL_IN_BUSINESS, 114 "Intel InBusiness Ethernet" }, 115 { PCI_PRODUCT_INTEL_82801BA_LAN, 116 "Intel i82562 Ethernet" }, 117 { 0, 118 NULL }, 119 }; 120 121 static const struct fxp_pci_product * 122 fxp_pci_lookup(const struct pci_attach_args *pa) 123 { 124 const struct fxp_pci_product *fpp; 125 126 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 127 return (NULL); 128 129 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 130 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 131 return (fpp); 132 133 return (NULL); 134 } 135 136 int 137 fxp_pci_match(parent, match, aux) 138 struct device *parent; 139 struct cfdata *match; 140 void *aux; 141 { 142 struct pci_attach_args *pa = aux; 143 144 if (fxp_pci_lookup(pa) != NULL) 145 return (1); 146 147 return (0); 148 } 149 150 /* 151 * Restore PCI configuration registers that may have been clobbered. 152 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 153 * ethernet, after an APM suspend/resume, as well as after an ACPI 154 * D3->D0 transition. We call this function from a power hook after 155 * APM resume events, as well as after the ACPI D3->D0 transition. 156 */ 157 static void 158 fxp_pci_confreg_restore(psc) 159 struct fxp_pci_softc *psc; 160 { 161 pcireg_t reg; 162 163 #if 0 164 /* 165 * Check to see if the command register is blank -- if so, then 166 * we'll assume that all the clobberable-registers have been 167 * clobbered. 168 */ 169 170 /* 171 * In general, the above metric is accurate. Unfortunately, 172 * it is inaccurate across a hibernation. Ideally APM/ACPI 173 * code should take note of hibernation events and execute 174 * a hibernation wakeup hook, but at present a hibernation wake 175 * is indistinguishable from a suspend wake. 176 */ 177 178 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 179 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 180 return; 181 #else 182 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 183 #endif 184 185 pci_conf_write(psc->psc_pc, psc->psc_tag, 186 PCI_COMMAND_STATUS_REG, 187 (reg & 0xffff0000) | 188 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 189 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 190 psc->psc_regs[PCI_BHLC_REG>>2]); 191 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 192 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 193 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 194 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 195 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 196 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 197 } 198 199 200 /* 201 * Power handler routine. Called when the system is transitioning into/out 202 * of power save modes. We restore the (bashed) PCI configuration registers 203 * on a resume. 204 */ 205 static void 206 fxp_pci_power(why, arg) 207 int why; 208 void *arg; 209 { 210 struct fxp_pci_softc *psc = arg; 211 212 if (why == PWR_RESUME) 213 fxp_pci_confreg_restore(psc); 214 } 215 216 void 217 fxp_pci_attach(parent, self, aux) 218 struct device *parent, *self; 219 void *aux; 220 { 221 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 222 struct fxp_softc *sc = (struct fxp_softc *)self; 223 struct pci_attach_args *pa = aux; 224 pci_chipset_tag_t pc = pa->pa_pc; 225 pci_intr_handle_t ih; 226 const struct fxp_pci_product *fpp; 227 const char *intrstr = NULL; 228 bus_space_tag_t iot, memt; 229 bus_space_handle_t ioh, memh; 230 int ioh_valid, memh_valid; 231 bus_addr_t addr; 232 bus_size_t size; 233 int flags; 234 int pci_pwrmgmt_cap_reg; 235 236 /* 237 * Map control/status registers. 238 */ 239 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 240 PCI_MAPREG_TYPE_IO, 0, 241 &iot, &ioh, NULL, NULL) == 0); 242 243 /* 244 * Version 2.1 of the PCI spec, page 196, "Address Maps": 245 * 246 * Prefetchable 247 * 248 * Set to one if there are no side effects on reads, the 249 * device returns all bytes regardless of the byte enables, 250 * and host bridges can merge processor writes into this 251 * range without causing errors. Bit must be set to zero 252 * otherwise. 253 * 254 * The 82557 incorrectly sets the "prefetchable" bit, resulting 255 * in errors on systems which will do merged reads and writes. 256 * These errors manifest themselves as all-bits-set when reading 257 * from the EEPROM or other < 4 byte registers. 258 * 259 * We must work around this problem by always forcing the mapping 260 * for memory space to be uncacheable. On systems which cannot 261 * create an uncacheable mapping (because the firmware mapped it 262 * into only cacheable/prefetchable space due to the "prefetchable" 263 * bit), we can fall back onto i/o mapped access. 264 */ 265 memh_valid = 0; 266 memt = pa->pa_memt; 267 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 268 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 269 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 270 &addr, &size, &flags) == 0) { 271 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 272 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 273 memh_valid = 1; 274 } 275 276 if (memh_valid) { 277 sc->sc_st = memt; 278 sc->sc_sh = memh; 279 } else if (ioh_valid) { 280 sc->sc_st = iot; 281 sc->sc_sh = ioh; 282 } else { 283 printf(": unable to map device registers\n"); 284 return; 285 } 286 287 sc->sc_dmat = pa->pa_dmat; 288 289 fpp = fxp_pci_lookup(pa); 290 if (fpp == NULL) { 291 printf("\n"); 292 panic("fxp_pci_attach: impossible"); 293 } 294 295 sc->sc_rev = PCI_REVISION(pa->pa_class); 296 297 switch (fpp->fpp_prodid) { 298 case PCI_PRODUCT_INTEL_82557: 299 case PCI_PRODUCT_INTEL_82559ER: 300 case PCI_PRODUCT_INTEL_IN_BUSINESS: 301 { 302 const char *chipname = NULL; 303 304 if (sc->sc_rev >= FXP_REV_82558_A4) { 305 chipname = "i82558 Ethernet"; 306 /* 307 * Enable the MWI command for memory writes. 308 */ 309 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 310 sc->sc_flags |= FXPF_MWI; 311 } 312 if (sc->sc_rev >= FXP_REV_82559_A0) 313 chipname = "i82559 Ethernet"; 314 if (sc->sc_rev >= FXP_REV_82559S_A) 315 chipname = "i82559S Ethernet"; 316 if (sc->sc_rev >= FXP_REV_82550) 317 chipname = "i82550 Ethernet"; 318 319 printf(": %s, rev %d\n", chipname != NULL ? chipname : 320 fpp->fpp_name, sc->sc_rev); 321 break; 322 } 323 324 case PCI_PRODUCT_INTEL_82801BA_LAN: 325 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 326 327 /* 328 * The 82801BA Ethernet has a bug which requires us to send a 329 * NOP before a CU_RESUME if we're in 10baseT mode. 330 */ 331 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 332 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 333 break; 334 335 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 336 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 337 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 338 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 339 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 340 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 341 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 342 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 343 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 344 345 /* 346 * ICH3 chips apparently have problems with the enhanced 347 * features, so just treat them as an i82557. It also 348 * has the resume bug that the ICH2 has. 349 */ 350 sc->sc_rev = 1; 351 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 352 break; 353 } 354 355 /* Make sure bus-mastering is enabled. */ 356 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 357 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 358 PCI_COMMAND_MASTER_ENABLE); 359 360 /* 361 * Under some circumstances (such as APM suspend/resume 362 * cycles, and across ACPI power state changes), the 363 * i82257-family can lose the contents of critical PCI 364 * configuration registers, causing the card to be 365 * non-responsive and useless. This occurs on the Sony VAIO 366 * Z505-series, among others. Preserve them here so they can 367 * be later restored (by fxp_pci_confreg_restore()). 368 */ 369 psc->psc_pc = pc; 370 psc->psc_tag = pa->pa_tag; 371 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 372 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 373 psc->psc_regs[PCI_BHLC_REG>>2] = 374 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 375 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 376 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 377 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 378 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 379 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 380 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 381 382 /* 383 * Work around BIOS ACPI bugs where the chip is inadvertantly 384 * left in ACPI D3 (lowest power state). First confirm the device 385 * supports ACPI power management, then move it to the D0 (fully 386 * functional) state if it is not already there. 387 */ 388 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 389 &pci_pwrmgmt_cap_reg, 0)) { 390 pcireg_t reg; 391 392 sc->sc_enable = fxp_pci_enable; 393 sc->sc_disable = fxp_pci_disable; 394 395 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 396 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 397 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 398 PCI_PMCSR_STATE_D0; 399 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 400 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 401 psc->psc_pwrmgmt_csr); 402 } 403 /* Restore PCI configuration registers. */ 404 fxp_pci_confreg_restore(psc); 405 406 sc->sc_enabled = 1; 407 408 /* 409 * Map and establish our interrupt. 410 */ 411 if (pci_intr_map(pa, &ih)) { 412 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 413 return; 414 } 415 intrstr = pci_intr_string(pc, ih); 416 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 417 if (sc->sc_ih == NULL) { 418 printf("%s: couldn't establish interrupt", 419 sc->sc_dev.dv_xname); 420 if (intrstr != NULL) 421 printf(" at %s", intrstr); 422 printf("\n"); 423 return; 424 } 425 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 426 427 /* Finish off the attach. */ 428 fxp_attach(sc); 429 if (sc->sc_disable != NULL) 430 fxp_disable(sc); 431 432 /* Add a suspend hook to restore PCI config state */ 433 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 434 if (psc->psc_powerhook == NULL) 435 printf ("%s: WARNING: unable to establish pci power hook\n", 436 sc->sc_dev.dv_xname); 437 } 438 439 int 440 fxp_pci_enable(struct fxp_softc *sc) 441 { 442 struct fxp_pci_softc *psc = (void *) sc; 443 444 #if 0 445 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 446 #endif 447 448 /* Bring the device into D0 power state. */ 449 pci_conf_write(psc->psc_pc, psc->psc_tag, 450 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 451 452 /* Now restore the configuration registers. */ 453 fxp_pci_confreg_restore(psc); 454 455 return (0); 456 } 457 458 void 459 fxp_pci_disable(struct fxp_softc *sc) 460 { 461 struct fxp_pci_softc *psc = (void *) sc; 462 463 #if 0 464 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 465 #endif 466 467 /* Put the device into D3 state. */ 468 pci_conf_write(psc->psc_pc, psc->psc_tag, 469 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 470 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 471 } 472
Indexes created Thu Oct 02 01:09:59 GMT 2025