if_fxp_pci.c revision 1.22.4.5
1 /* $NetBSD: if_fxp_pci.c,v 1.22.4.5 2003/06/30 02:36:44 grant Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.22.4.5 2003/06/30 02:36:44 grant Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 struct cfattach fxp_pci_ca = { 105 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 106 }; 107 108 const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 135 "Intel PRO/100 VM Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 137 "Intel PRO/100 VM Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 139 "Intel PRO/100 VM Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 141 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 143 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 144 { PCI_PRODUCT_INTEL_PRO_100_M, 145 "Intel PRO/100 M Network Controller" }, 146 { 0, 147 NULL }, 148 }; 149 150 static const struct fxp_pci_product * 151 fxp_pci_lookup(const struct pci_attach_args *pa) 152 { 153 const struct fxp_pci_product *fpp; 154 155 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 156 return (NULL); 157 158 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 159 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 160 return (fpp); 161 162 return (NULL); 163 } 164 165 int 166 fxp_pci_match(parent, match, aux) 167 struct device *parent; 168 struct cfdata *match; 169 void *aux; 170 { 171 struct pci_attach_args *pa = aux; 172 173 if (fxp_pci_lookup(pa) != NULL) 174 return (1); 175 176 return (0); 177 } 178 179 /* 180 * Restore PCI configuration registers that may have been clobbered. 181 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 182 * ethernet, after an APM suspend/resume, as well as after an ACPI 183 * D3->D0 transition. We call this function from a power hook after 184 * APM resume events, as well as after the ACPI D3->D0 transition. 185 */ 186 static void 187 fxp_pci_confreg_restore(psc) 188 struct fxp_pci_softc *psc; 189 { 190 pcireg_t reg; 191 192 #if 0 193 /* 194 * Check to see if the command register is blank -- if so, then 195 * we'll assume that all the clobberable-registers have been 196 * clobbered. 197 */ 198 199 /* 200 * In general, the above metric is accurate. Unfortunately, 201 * it is inaccurate across a hibernation. Ideally APM/ACPI 202 * code should take note of hibernation events and execute 203 * a hibernation wakeup hook, but at present a hibernation wake 204 * is indistinguishable from a suspend wake. 205 */ 206 207 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 208 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 209 return; 210 #else 211 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 212 #endif 213 214 pci_conf_write(psc->psc_pc, psc->psc_tag, 215 PCI_COMMAND_STATUS_REG, 216 (reg & 0xffff0000) | 217 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 218 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 219 psc->psc_regs[PCI_BHLC_REG>>2]); 220 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 221 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 222 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 223 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 224 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 225 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 226 } 227 228 229 /* 230 * Power handler routine. Called when the system is transitioning into/out 231 * of power save modes. We restore the (bashed) PCI configuration registers 232 * on a resume. 233 */ 234 static void 235 fxp_pci_power(why, arg) 236 int why; 237 void *arg; 238 { 239 struct fxp_pci_softc *psc = arg; 240 241 if (why == PWR_RESUME) 242 fxp_pci_confreg_restore(psc); 243 } 244 245 void 246 fxp_pci_attach(parent, self, aux) 247 struct device *parent, *self; 248 void *aux; 249 { 250 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 251 struct fxp_softc *sc = (struct fxp_softc *)self; 252 struct pci_attach_args *pa = aux; 253 pci_chipset_tag_t pc = pa->pa_pc; 254 pci_intr_handle_t ih; 255 const struct fxp_pci_product *fpp; 256 const char *intrstr = NULL; 257 bus_space_tag_t iot, memt; 258 bus_space_handle_t ioh, memh; 259 int ioh_valid, memh_valid; 260 bus_addr_t addr; 261 bus_size_t size; 262 int flags; 263 int pci_pwrmgmt_cap_reg; 264 265 /* 266 * Map control/status registers. 267 */ 268 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 269 PCI_MAPREG_TYPE_IO, 0, 270 &iot, &ioh, NULL, NULL) == 0); 271 272 /* 273 * Version 2.1 of the PCI spec, page 196, "Address Maps": 274 * 275 * Prefetchable 276 * 277 * Set to one if there are no side effects on reads, the 278 * device returns all bytes regardless of the byte enables, 279 * and host bridges can merge processor writes into this 280 * range without causing errors. Bit must be set to zero 281 * otherwise. 282 * 283 * The 82557 incorrectly sets the "prefetchable" bit, resulting 284 * in errors on systems which will do merged reads and writes. 285 * These errors manifest themselves as all-bits-set when reading 286 * from the EEPROM or other < 4 byte registers. 287 * 288 * We must work around this problem by always forcing the mapping 289 * for memory space to be uncacheable. On systems which cannot 290 * create an uncacheable mapping (because the firmware mapped it 291 * into only cacheable/prefetchable space due to the "prefetchable" 292 * bit), we can fall back onto i/o mapped access. 293 */ 294 memh_valid = 0; 295 memt = pa->pa_memt; 296 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 297 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 298 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 299 &addr, &size, &flags) == 0) { 300 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 301 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 302 memh_valid = 1; 303 } 304 305 if (memh_valid) { 306 sc->sc_st = memt; 307 sc->sc_sh = memh; 308 } else if (ioh_valid) { 309 sc->sc_st = iot; 310 sc->sc_sh = ioh; 311 } else { 312 printf(": unable to map device registers\n"); 313 return; 314 } 315 316 sc->sc_dmat = pa->pa_dmat; 317 318 fpp = fxp_pci_lookup(pa); 319 if (fpp == NULL) { 320 printf("\n"); 321 panic("fxp_pci_attach: impossible"); 322 } 323 324 sc->sc_rev = PCI_REVISION(pa->pa_class); 325 326 switch (fpp->fpp_prodid) { 327 case PCI_PRODUCT_INTEL_82557: 328 case PCI_PRODUCT_INTEL_82559ER: 329 case PCI_PRODUCT_INTEL_IN_BUSINESS: 330 { 331 const char *chipname = NULL; 332 333 if (sc->sc_rev >= FXP_REV_82558_A4) { 334 chipname = "i82558 Ethernet"; 335 /* 336 * Enable the MWI command for memory writes. 337 */ 338 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 339 sc->sc_flags |= FXPF_MWI; 340 } 341 if (sc->sc_rev >= FXP_REV_82559_A0) 342 chipname = "i82559 Ethernet"; 343 if (sc->sc_rev >= FXP_REV_82559S_A) 344 chipname = "i82559S Ethernet"; 345 if (sc->sc_rev >= FXP_REV_82550) 346 chipname = "i82550 Ethernet"; 347 348 /* 349 * Mark all i82559 and i82550 revisions as having 350 * the "resume bug". See i82557.c for details. 351 */ 352 if (sc->sc_rev >= FXP_REV_82559_A0) 353 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 354 355 printf(": %s, rev %d\n", chipname != NULL ? chipname : 356 fpp->fpp_name, sc->sc_rev); 357 break; 358 } 359 360 case PCI_PRODUCT_INTEL_82801BA_LAN: 361 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 362 363 /* 364 * The 82801BA Ethernet has a bug which requires us to send a 365 * NOP before a CU_RESUME if we're in 10baseT mode. 366 */ 367 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 368 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 369 break; 370 371 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 372 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 373 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 374 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 375 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 376 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 377 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 378 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 379 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 380 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 381 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 382 383 /* 384 * ICH3 chips apparently have problems with the enhanced 385 * features, so just treat them as an i82557. It also 386 * has the resume bug that the ICH2 has. 387 */ 388 sc->sc_rev = 1; 389 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 390 break; 391 case PCI_PRODUCT_INTEL_82801E_LAN_1: 392 case PCI_PRODUCT_INTEL_82801E_LAN_2: 393 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 394 395 /* 396 * XXX We have to read the C-ICH's developer's manual 397 * in detail 398 */ 399 break; 400 } 401 402 /* Make sure bus-mastering is enabled. */ 403 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 404 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 405 PCI_COMMAND_MASTER_ENABLE); 406 407 /* 408 * Under some circumstances (such as APM suspend/resume 409 * cycles, and across ACPI power state changes), the 410 * i82257-family can lose the contents of critical PCI 411 * configuration registers, causing the card to be 412 * non-responsive and useless. This occurs on the Sony VAIO 413 * Z505-series, among others. Preserve them here so they can 414 * be later restored (by fxp_pci_confreg_restore()). 415 */ 416 psc->psc_pc = pc; 417 psc->psc_tag = pa->pa_tag; 418 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 419 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 420 psc->psc_regs[PCI_BHLC_REG>>2] = 421 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 422 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 423 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 424 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 425 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 426 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 427 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 428 429 /* 430 * Work around BIOS ACPI bugs where the chip is inadvertantly 431 * left in ACPI D3 (lowest power state). First confirm the device 432 * supports ACPI power management, then move it to the D0 (fully 433 * functional) state if it is not already there. 434 */ 435 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 436 &pci_pwrmgmt_cap_reg, 0)) { 437 pcireg_t reg; 438 439 sc->sc_enable = fxp_pci_enable; 440 sc->sc_disable = fxp_pci_disable; 441 442 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 443 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 444 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 445 PCI_PMCSR_STATE_D0; 446 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 447 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 448 psc->psc_pwrmgmt_csr); 449 } 450 /* Restore PCI configuration registers. */ 451 fxp_pci_confreg_restore(psc); 452 453 sc->sc_enabled = 1; 454 455 /* 456 * Map and establish our interrupt. 457 */ 458 if (pci_intr_map(pa, &ih)) { 459 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 460 return; 461 } 462 intrstr = pci_intr_string(pc, ih); 463 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 464 if (sc->sc_ih == NULL) { 465 printf("%s: couldn't establish interrupt", 466 sc->sc_dev.dv_xname); 467 if (intrstr != NULL) 468 printf(" at %s", intrstr); 469 printf("\n"); 470 return; 471 } 472 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 473 474 /* Finish off the attach. */ 475 fxp_attach(sc); 476 if (sc->sc_disable != NULL) 477 fxp_disable(sc); 478 479 /* Add a suspend hook to restore PCI config state */ 480 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 481 if (psc->psc_powerhook == NULL) 482 printf ("%s: WARNING: unable to establish pci power hook\n", 483 sc->sc_dev.dv_xname); 484 } 485 486 int 487 fxp_pci_enable(struct fxp_softc *sc) 488 { 489 struct fxp_pci_softc *psc = (void *) sc; 490 491 #if 0 492 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 493 #endif 494 495 /* Bring the device into D0 power state. */ 496 pci_conf_write(psc->psc_pc, psc->psc_tag, 497 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 498 499 /* Now restore the configuration registers. */ 500 fxp_pci_confreg_restore(psc); 501 502 return (0); 503 } 504 505 void 506 fxp_pci_disable(struct fxp_softc *sc) 507 { 508 struct fxp_pci_softc *psc = (void *) sc; 509 510 /* 511 * for some 82558_A4 and 82558_B0, entering D3 state makes 512 * media detection disordered. 513 */ 514 if (sc->sc_rev <= FXP_REV_82558_B0) 515 return; 516 517 #if 0 518 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 519 #endif 520 521 /* Put the device into D3 state. */ 522 pci_conf_write(psc->psc_pc, psc->psc_tag, 523 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 524 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 525 } 526
Indexes created Thu Oct 02 01:09:59 GMT 2025