if_fxp_pci.c revision 1.22.4.6
1 /* $NetBSD: if_fxp_pci.c,v 1.22.4.6 2003/08/15 19:29:32 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.22.4.6 2003/08/15 19:29:32 tron Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 struct cfattach fxp_pci_ca = { 105 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 106 }; 107 108 const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 135 "Intel PRO/100 VM Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 137 "Intel PRO/100 VM Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 139 "Intel PRO/100 VM Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 141 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 143 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 145 "Intel PRO/100 VM Network Controller with 82562ET PHY" }, 146 { PCI_PRODUCT_INTEL_PRO_100_M, 147 "Intel PRO/100 M Network Controller" }, 148 { 0, 149 NULL }, 150 }; 151 152 static const struct fxp_pci_product * 153 fxp_pci_lookup(const struct pci_attach_args *pa) 154 { 155 const struct fxp_pci_product *fpp; 156 157 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 158 return (NULL); 159 160 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 161 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 162 return (fpp); 163 164 return (NULL); 165 } 166 167 int 168 fxp_pci_match(parent, match, aux) 169 struct device *parent; 170 struct cfdata *match; 171 void *aux; 172 { 173 struct pci_attach_args *pa = aux; 174 175 if (fxp_pci_lookup(pa) != NULL) 176 return (1); 177 178 return (0); 179 } 180 181 /* 182 * Restore PCI configuration registers that may have been clobbered. 183 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 184 * ethernet, after an APM suspend/resume, as well as after an ACPI 185 * D3->D0 transition. We call this function from a power hook after 186 * APM resume events, as well as after the ACPI D3->D0 transition. 187 */ 188 static void 189 fxp_pci_confreg_restore(psc) 190 struct fxp_pci_softc *psc; 191 { 192 pcireg_t reg; 193 194 #if 0 195 /* 196 * Check to see if the command register is blank -- if so, then 197 * we'll assume that all the clobberable-registers have been 198 * clobbered. 199 */ 200 201 /* 202 * In general, the above metric is accurate. Unfortunately, 203 * it is inaccurate across a hibernation. Ideally APM/ACPI 204 * code should take note of hibernation events and execute 205 * a hibernation wakeup hook, but at present a hibernation wake 206 * is indistinguishable from a suspend wake. 207 */ 208 209 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 210 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 211 return; 212 #else 213 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 214 #endif 215 216 pci_conf_write(psc->psc_pc, psc->psc_tag, 217 PCI_COMMAND_STATUS_REG, 218 (reg & 0xffff0000) | 219 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 220 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 221 psc->psc_regs[PCI_BHLC_REG>>2]); 222 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 223 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 224 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 225 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 226 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 227 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 228 } 229 230 231 /* 232 * Power handler routine. Called when the system is transitioning into/out 233 * of power save modes. We restore the (bashed) PCI configuration registers 234 * on a resume. 235 */ 236 static void 237 fxp_pci_power(why, arg) 238 int why; 239 void *arg; 240 { 241 struct fxp_pci_softc *psc = arg; 242 243 if (why == PWR_RESUME) 244 fxp_pci_confreg_restore(psc); 245 } 246 247 void 248 fxp_pci_attach(parent, self, aux) 249 struct device *parent, *self; 250 void *aux; 251 { 252 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 253 struct fxp_softc *sc = (struct fxp_softc *)self; 254 struct pci_attach_args *pa = aux; 255 pci_chipset_tag_t pc = pa->pa_pc; 256 pci_intr_handle_t ih; 257 const struct fxp_pci_product *fpp; 258 const char *intrstr = NULL; 259 bus_space_tag_t iot, memt; 260 bus_space_handle_t ioh, memh; 261 int ioh_valid, memh_valid; 262 bus_addr_t addr; 263 bus_size_t size; 264 int flags; 265 int pci_pwrmgmt_cap_reg; 266 267 /* 268 * Map control/status registers. 269 */ 270 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 271 PCI_MAPREG_TYPE_IO, 0, 272 &iot, &ioh, NULL, NULL) == 0); 273 274 /* 275 * Version 2.1 of the PCI spec, page 196, "Address Maps": 276 * 277 * Prefetchable 278 * 279 * Set to one if there are no side effects on reads, the 280 * device returns all bytes regardless of the byte enables, 281 * and host bridges can merge processor writes into this 282 * range without causing errors. Bit must be set to zero 283 * otherwise. 284 * 285 * The 82557 incorrectly sets the "prefetchable" bit, resulting 286 * in errors on systems which will do merged reads and writes. 287 * These errors manifest themselves as all-bits-set when reading 288 * from the EEPROM or other < 4 byte registers. 289 * 290 * We must work around this problem by always forcing the mapping 291 * for memory space to be uncacheable. On systems which cannot 292 * create an uncacheable mapping (because the firmware mapped it 293 * into only cacheable/prefetchable space due to the "prefetchable" 294 * bit), we can fall back onto i/o mapped access. 295 */ 296 memh_valid = 0; 297 memt = pa->pa_memt; 298 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 299 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 300 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 301 &addr, &size, &flags) == 0) { 302 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 303 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 304 memh_valid = 1; 305 } 306 307 if (memh_valid) { 308 sc->sc_st = memt; 309 sc->sc_sh = memh; 310 } else if (ioh_valid) { 311 sc->sc_st = iot; 312 sc->sc_sh = ioh; 313 } else { 314 printf(": unable to map device registers\n"); 315 return; 316 } 317 318 sc->sc_dmat = pa->pa_dmat; 319 320 fpp = fxp_pci_lookup(pa); 321 if (fpp == NULL) { 322 printf("\n"); 323 panic("fxp_pci_attach: impossible"); 324 } 325 326 sc->sc_rev = PCI_REVISION(pa->pa_class); 327 328 switch (fpp->fpp_prodid) { 329 case PCI_PRODUCT_INTEL_82557: 330 case PCI_PRODUCT_INTEL_82559ER: 331 case PCI_PRODUCT_INTEL_IN_BUSINESS: 332 { 333 const char *chipname = NULL; 334 335 if (sc->sc_rev >= FXP_REV_82558_A4) { 336 chipname = "i82558 Ethernet"; 337 /* 338 * Enable the MWI command for memory writes. 339 */ 340 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 341 sc->sc_flags |= FXPF_MWI; 342 } 343 if (sc->sc_rev >= FXP_REV_82559_A0) 344 chipname = "i82559 Ethernet"; 345 if (sc->sc_rev >= FXP_REV_82559S_A) 346 chipname = "i82559S Ethernet"; 347 if (sc->sc_rev >= FXP_REV_82550) 348 chipname = "i82550 Ethernet"; 349 350 /* 351 * Mark all i82559 and i82550 revisions as having 352 * the "resume bug". See i82557.c for details. 353 */ 354 if (sc->sc_rev >= FXP_REV_82559_A0) 355 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 356 357 printf(": %s, rev %d\n", chipname != NULL ? chipname : 358 fpp->fpp_name, sc->sc_rev); 359 break; 360 } 361 362 case PCI_PRODUCT_INTEL_82801BA_LAN: 363 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 364 365 /* 366 * The 82801BA Ethernet has a bug which requires us to send a 367 * NOP before a CU_RESUME if we're in 10baseT mode. 368 */ 369 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 370 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 371 break; 372 373 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 374 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 375 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 376 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 377 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 378 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 379 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 380 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 381 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 382 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 383 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 384 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 385 386 /* 387 * ICH3 chips apparently have problems with the enhanced 388 * features, so just treat them as an i82557. It also 389 * has the resume bug that the ICH2 has. 390 */ 391 sc->sc_rev = 1; 392 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 393 break; 394 case PCI_PRODUCT_INTEL_82801E_LAN_1: 395 case PCI_PRODUCT_INTEL_82801E_LAN_2: 396 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 397 398 /* 399 * XXX We have to read the C-ICH's developer's manual 400 * in detail 401 */ 402 break; 403 } 404 405 /* Make sure bus-mastering is enabled. */ 406 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 407 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 408 PCI_COMMAND_MASTER_ENABLE); 409 410 /* 411 * Under some circumstances (such as APM suspend/resume 412 * cycles, and across ACPI power state changes), the 413 * i82257-family can lose the contents of critical PCI 414 * configuration registers, causing the card to be 415 * non-responsive and useless. This occurs on the Sony VAIO 416 * Z505-series, among others. Preserve them here so they can 417 * be later restored (by fxp_pci_confreg_restore()). 418 */ 419 psc->psc_pc = pc; 420 psc->psc_tag = pa->pa_tag; 421 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 422 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 423 psc->psc_regs[PCI_BHLC_REG>>2] = 424 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 425 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 426 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 427 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 428 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 429 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 430 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 431 432 /* 433 * Work around BIOS ACPI bugs where the chip is inadvertantly 434 * left in ACPI D3 (lowest power state). First confirm the device 435 * supports ACPI power management, then move it to the D0 (fully 436 * functional) state if it is not already there. 437 */ 438 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 439 &pci_pwrmgmt_cap_reg, 0)) { 440 pcireg_t reg; 441 442 sc->sc_enable = fxp_pci_enable; 443 sc->sc_disable = fxp_pci_disable; 444 445 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 446 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 447 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 448 PCI_PMCSR_STATE_D0; 449 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 450 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 451 psc->psc_pwrmgmt_csr); 452 } 453 /* Restore PCI configuration registers. */ 454 fxp_pci_confreg_restore(psc); 455 456 sc->sc_enabled = 1; 457 458 /* 459 * Map and establish our interrupt. 460 */ 461 if (pci_intr_map(pa, &ih)) { 462 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 463 return; 464 } 465 intrstr = pci_intr_string(pc, ih); 466 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 467 if (sc->sc_ih == NULL) { 468 printf("%s: couldn't establish interrupt", 469 sc->sc_dev.dv_xname); 470 if (intrstr != NULL) 471 printf(" at %s", intrstr); 472 printf("\n"); 473 return; 474 } 475 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 476 477 /* Finish off the attach. */ 478 fxp_attach(sc); 479 if (sc->sc_disable != NULL) 480 fxp_disable(sc); 481 482 /* Add a suspend hook to restore PCI config state */ 483 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 484 if (psc->psc_powerhook == NULL) 485 printf ("%s: WARNING: unable to establish pci power hook\n", 486 sc->sc_dev.dv_xname); 487 } 488 489 int 490 fxp_pci_enable(struct fxp_softc *sc) 491 { 492 struct fxp_pci_softc *psc = (void *) sc; 493 494 #if 0 495 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 496 #endif 497 498 /* Bring the device into D0 power state. */ 499 pci_conf_write(psc->psc_pc, psc->psc_tag, 500 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 501 502 /* Now restore the configuration registers. */ 503 fxp_pci_confreg_restore(psc); 504 505 return (0); 506 } 507 508 void 509 fxp_pci_disable(struct fxp_softc *sc) 510 { 511 struct fxp_pci_softc *psc = (void *) sc; 512 513 /* 514 * for some 82558_A4 and 82558_B0, entering D3 state makes 515 * media detection disordered. 516 */ 517 if (sc->sc_rev <= FXP_REV_82558_B0) 518 return; 519 520 #if 0 521 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 522 #endif 523 524 /* Put the device into D3 state. */ 525 pci_conf_write(psc->psc_pc, psc->psc_tag, 526 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 527 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 528 } 529
Indexes created Thu Oct 02 01:09:59 GMT 2025