if_fxp_pci.c revision 1.22.4.7
1 /* $NetBSD: if_fxp_pci.c,v 1.22.4.7 2004/04/06 05:25:04 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.22.4.7 2004/04/06 05:25:04 jmc Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 struct cfattach fxp_pci_ca = { 105 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 106 }; 107 108 const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 135 "Intel PRO/100 VM Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 137 "Intel PRO/100 VM Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 139 "Intel PRO/100 VM Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 141 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 143 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 145 "Intel PRO/100 VM Network Controller with 82562ET PHY" }, 146 { PCI_PRODUCT_INTEL_PRO_100_M, 147 "Intel PRO/100 M Network Controller" }, 148 { PCI_PRODUCT_INTEL_82801EB_LAN, 149 "Intel 82801EB/ER (ICH5) Network Controller" }, 150 { 0, 151 NULL }, 152 }; 153 154 static const struct fxp_pci_product * 155 fxp_pci_lookup(const struct pci_attach_args *pa) 156 { 157 const struct fxp_pci_product *fpp; 158 159 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 160 return (NULL); 161 162 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 163 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 164 return (fpp); 165 166 return (NULL); 167 } 168 169 int 170 fxp_pci_match(parent, match, aux) 171 struct device *parent; 172 struct cfdata *match; 173 void *aux; 174 { 175 struct pci_attach_args *pa = aux; 176 177 if (fxp_pci_lookup(pa) != NULL) 178 return (1); 179 180 return (0); 181 } 182 183 /* 184 * Restore PCI configuration registers that may have been clobbered. 185 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 186 * ethernet, after an APM suspend/resume, as well as after an ACPI 187 * D3->D0 transition. We call this function from a power hook after 188 * APM resume events, as well as after the ACPI D3->D0 transition. 189 */ 190 static void 191 fxp_pci_confreg_restore(psc) 192 struct fxp_pci_softc *psc; 193 { 194 pcireg_t reg; 195 196 #if 0 197 /* 198 * Check to see if the command register is blank -- if so, then 199 * we'll assume that all the clobberable-registers have been 200 * clobbered. 201 */ 202 203 /* 204 * In general, the above metric is accurate. Unfortunately, 205 * it is inaccurate across a hibernation. Ideally APM/ACPI 206 * code should take note of hibernation events and execute 207 * a hibernation wakeup hook, but at present a hibernation wake 208 * is indistinguishable from a suspend wake. 209 */ 210 211 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 212 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 213 return; 214 #else 215 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 216 #endif 217 218 pci_conf_write(psc->psc_pc, psc->psc_tag, 219 PCI_COMMAND_STATUS_REG, 220 (reg & 0xffff0000) | 221 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 222 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 223 psc->psc_regs[PCI_BHLC_REG>>2]); 224 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 225 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 226 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 227 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 228 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 229 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 230 } 231 232 233 /* 234 * Power handler routine. Called when the system is transitioning into/out 235 * of power save modes. We restore the (bashed) PCI configuration registers 236 * on a resume. 237 */ 238 static void 239 fxp_pci_power(why, arg) 240 int why; 241 void *arg; 242 { 243 struct fxp_pci_softc *psc = arg; 244 245 if (why == PWR_RESUME) 246 fxp_pci_confreg_restore(psc); 247 } 248 249 void 250 fxp_pci_attach(parent, self, aux) 251 struct device *parent, *self; 252 void *aux; 253 { 254 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 255 struct fxp_softc *sc = (struct fxp_softc *)self; 256 struct pci_attach_args *pa = aux; 257 pci_chipset_tag_t pc = pa->pa_pc; 258 pci_intr_handle_t ih; 259 const struct fxp_pci_product *fpp; 260 const char *intrstr = NULL; 261 bus_space_tag_t iot, memt; 262 bus_space_handle_t ioh, memh; 263 int ioh_valid, memh_valid; 264 bus_addr_t addr; 265 bus_size_t size; 266 int flags; 267 int pci_pwrmgmt_cap_reg; 268 269 /* 270 * Map control/status registers. 271 */ 272 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 273 PCI_MAPREG_TYPE_IO, 0, 274 &iot, &ioh, NULL, NULL) == 0); 275 276 /* 277 * Version 2.1 of the PCI spec, page 196, "Address Maps": 278 * 279 * Prefetchable 280 * 281 * Set to one if there are no side effects on reads, the 282 * device returns all bytes regardless of the byte enables, 283 * and host bridges can merge processor writes into this 284 * range without causing errors. Bit must be set to zero 285 * otherwise. 286 * 287 * The 82557 incorrectly sets the "prefetchable" bit, resulting 288 * in errors on systems which will do merged reads and writes. 289 * These errors manifest themselves as all-bits-set when reading 290 * from the EEPROM or other < 4 byte registers. 291 * 292 * We must work around this problem by always forcing the mapping 293 * for memory space to be uncacheable. On systems which cannot 294 * create an uncacheable mapping (because the firmware mapped it 295 * into only cacheable/prefetchable space due to the "prefetchable" 296 * bit), we can fall back onto i/o mapped access. 297 */ 298 memh_valid = 0; 299 memt = pa->pa_memt; 300 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 301 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 302 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 303 &addr, &size, &flags) == 0) { 304 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 305 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 306 memh_valid = 1; 307 } 308 309 if (memh_valid) { 310 sc->sc_st = memt; 311 sc->sc_sh = memh; 312 } else if (ioh_valid) { 313 sc->sc_st = iot; 314 sc->sc_sh = ioh; 315 } else { 316 printf(": unable to map device registers\n"); 317 return; 318 } 319 320 sc->sc_dmat = pa->pa_dmat; 321 322 fpp = fxp_pci_lookup(pa); 323 if (fpp == NULL) { 324 printf("\n"); 325 panic("fxp_pci_attach: impossible"); 326 } 327 328 sc->sc_rev = PCI_REVISION(pa->pa_class); 329 330 switch (fpp->fpp_prodid) { 331 case PCI_PRODUCT_INTEL_82557: 332 case PCI_PRODUCT_INTEL_82559ER: 333 case PCI_PRODUCT_INTEL_IN_BUSINESS: 334 { 335 const char *chipname = NULL; 336 337 if (sc->sc_rev >= FXP_REV_82558_A4) { 338 chipname = "i82558 Ethernet"; 339 /* 340 * Enable the MWI command for memory writes. 341 */ 342 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 343 sc->sc_flags |= FXPF_MWI; 344 } 345 if (sc->sc_rev >= FXP_REV_82559_A0) 346 chipname = "i82559 Ethernet"; 347 if (sc->sc_rev >= FXP_REV_82559S_A) 348 chipname = "i82559S Ethernet"; 349 if (sc->sc_rev >= FXP_REV_82550) 350 chipname = "i82550 Ethernet"; 351 352 /* 353 * Mark all i82559 and i82550 revisions as having 354 * the "resume bug". See i82557.c for details. 355 */ 356 if (sc->sc_rev >= FXP_REV_82559_A0) 357 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 358 359 printf(": %s, rev %d\n", chipname != NULL ? chipname : 360 fpp->fpp_name, sc->sc_rev); 361 break; 362 } 363 364 case PCI_PRODUCT_INTEL_82801BA_LAN: 365 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 366 367 /* 368 * The 82801BA Ethernet has a bug which requires us to send a 369 * NOP before a CU_RESUME if we're in 10baseT mode. 370 */ 371 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 372 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 373 break; 374 375 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 376 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 377 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 378 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 379 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 380 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 381 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 382 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 383 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 384 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 385 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 386 case PCI_PRODUCT_INTEL_82801EB_LAN: 387 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 388 389 /* 390 * ICH3 chips apparently have problems with the enhanced 391 * features, so just treat them as an i82557. It also 392 * has the resume bug that the ICH2 has. 393 */ 394 sc->sc_rev = 1; 395 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 396 break; 397 case PCI_PRODUCT_INTEL_82801E_LAN_1: 398 case PCI_PRODUCT_INTEL_82801E_LAN_2: 399 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 400 401 /* 402 * XXX We have to read the C-ICH's developer's manual 403 * in detail 404 */ 405 break; 406 } 407 408 /* Make sure bus-mastering is enabled. */ 409 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 410 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 411 PCI_COMMAND_MASTER_ENABLE); 412 413 /* 414 * Under some circumstances (such as APM suspend/resume 415 * cycles, and across ACPI power state changes), the 416 * i82257-family can lose the contents of critical PCI 417 * configuration registers, causing the card to be 418 * non-responsive and useless. This occurs on the Sony VAIO 419 * Z505-series, among others. Preserve them here so they can 420 * be later restored (by fxp_pci_confreg_restore()). 421 */ 422 psc->psc_pc = pc; 423 psc->psc_tag = pa->pa_tag; 424 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 425 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 426 psc->psc_regs[PCI_BHLC_REG>>2] = 427 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 428 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 429 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 430 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 431 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 432 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 433 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 434 435 /* 436 * Work around BIOS ACPI bugs where the chip is inadvertantly 437 * left in ACPI D3 (lowest power state). First confirm the device 438 * supports ACPI power management, then move it to the D0 (fully 439 * functional) state if it is not already there. 440 */ 441 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 442 &pci_pwrmgmt_cap_reg, 0)) { 443 pcireg_t reg; 444 445 sc->sc_enable = fxp_pci_enable; 446 sc->sc_disable = fxp_pci_disable; 447 448 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 449 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 450 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 451 PCI_PMCSR_STATE_D0; 452 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 453 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 454 psc->psc_pwrmgmt_csr); 455 } 456 /* Restore PCI configuration registers. */ 457 fxp_pci_confreg_restore(psc); 458 459 sc->sc_enabled = 1; 460 461 /* 462 * Map and establish our interrupt. 463 */ 464 if (pci_intr_map(pa, &ih)) { 465 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 466 return; 467 } 468 intrstr = pci_intr_string(pc, ih); 469 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 470 if (sc->sc_ih == NULL) { 471 printf("%s: couldn't establish interrupt", 472 sc->sc_dev.dv_xname); 473 if (intrstr != NULL) 474 printf(" at %s", intrstr); 475 printf("\n"); 476 return; 477 } 478 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 479 480 /* Finish off the attach. */ 481 fxp_attach(sc); 482 if (sc->sc_disable != NULL) 483 fxp_disable(sc); 484 485 /* Add a suspend hook to restore PCI config state */ 486 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 487 if (psc->psc_powerhook == NULL) 488 printf ("%s: WARNING: unable to establish pci power hook\n", 489 sc->sc_dev.dv_xname); 490 } 491 492 int 493 fxp_pci_enable(struct fxp_softc *sc) 494 { 495 struct fxp_pci_softc *psc = (void *) sc; 496 497 #if 0 498 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 499 #endif 500 501 /* Bring the device into D0 power state. */ 502 pci_conf_write(psc->psc_pc, psc->psc_tag, 503 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 504 505 /* Now restore the configuration registers. */ 506 fxp_pci_confreg_restore(psc); 507 508 return (0); 509 } 510 511 void 512 fxp_pci_disable(struct fxp_softc *sc) 513 { 514 struct fxp_pci_softc *psc = (void *) sc; 515 516 /* 517 * for some 82558_A4 and 82558_B0, entering D3 state makes 518 * media detection disordered. 519 */ 520 if (sc->sc_rev <= FXP_REV_82558_B0) 521 return; 522 523 #if 0 524 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 525 #endif 526 527 /* Put the device into D3 state. */ 528 pci_conf_write(psc->psc_pc, psc->psc_tag, 529 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 530 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 531 } 532
Indexes created Thu Oct 02 01:09:59 GMT 2025